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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_dram_jbus.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_dram_jbus (/*AUTOARG*/
// Outputs
so, rclk, dbginit_l, cluster_grst_l,
// Inputs
si, se, grst_l, gdbginit_l, gclk, cluster_cken, arst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cluster_grst_l; // From cluster_header of cluster_header.v
output dbginit_l; // From cluster_header of cluster_header.v
output rclk; // From cluster_header of cluster_header.v
output so; // From cluster_header of cluster_header.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To cluster_header of cluster_header.v
input arst_l; // To cluster_header of cluster_header.v
input cluster_cken; // To cluster_header of cluster_header.v
input gclk; // To cluster_header of cluster_header.v
input gdbginit_l; // To cluster_header of cluster_header.v
input grst_l; // To cluster_header of cluster_header.v
input se; // To cluster_header of cluster_header.v
input si; // To cluster_header of cluster_header.v
// End of automatics
/* cluster_header AUTO_TEMPLATE (
); */
cluster_header cluster_header
(/*AUTOINST*/
// Outputs
.dbginit_l (dbginit_l),
.cluster_grst_l (cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken (cluster_cken),
.arst_l (arst_l),
.grst_l (grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l),
.si (si),
.se (se));
endmodule // bw_clk_cl_ddr_ddr
// Local Variables:
// verilog-library-directories:("../../common/rtl")
// verilog-auto-sense-defines-constant:t
// End:
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : ram_dp_be.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Dual Port Ram Model with write byte enable
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module ram_dp_be (
clka ,
cena_i ,
oena_i ,
wena_i ,
addra_i ,
dataa_o ,
dataa_i ,
clkb ,
cenb_i ,
oenb_i ,
wenb_i ,
addrb_i ,
datab_o ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=8;
localparam Byte_Width=(Word_Width>>3);
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input oena_i; // data output enable, low active
input [Byte_Width-1:0] wena_i; // write enable, low active
input [Addr_Width-1:0] addra_i; // address input
input [Word_Width-1:0] dataa_i; // data input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input oenb_i; // data output enable, low active
input [Byte_Width-1:0] wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
output [Word_Width-1:0] datab_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
reg [Word_Width-1:0] datab_r;
reg [Word_Width-1:0] dataa_w;
reg [Word_Width-1:0] datab_w;
wire [Word_Width-1:0] dataa_m;
wire [Word_Width-1:0] datab_m;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
assign dataa_m = mem_array[addra_i];
genvar i;
generate
for (i=0; i<Byte_Width; i=i+1) begin:i_n
always@(*) begin
dataa_w[(i+1)*8-1:i*8] = wena_i[i] ? dataa_m[(i+1)*8-1:i*8] : dataa_i[(i+1)*8-1:i*8];
end
end
endgenerate
always @(posedge clka) begin
if(!cena_i && !(&wena_i))
mem_array[addra_i] <= dataa_w;
end
always @(posedge clka) begin
if (!cena_i && wena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = oena_i ? 'bz : dataa_r;
// -- B Port --//
assign datab_m = mem_array[addrb_i];
genvar j;
generate
for (j=0; j<Byte_Width; j=j+1) begin:j_n
always@(*) begin
datab_w[(j+1)*8-1:j*8] = wenb_i[j] ? datab_m[(j+1)*8-1:j*8] : datab_i[(j+1)*8-1:j*8];
end
end
endgenerate
always @(posedge clkb) begin
if(!cenb_i && !(&wenb_i))
mem_array[addrb_i] <= datab_w;
end
always @(posedge clkb) begin
if (!cenb_i && wenb_i)
datab_r <= mem_array[addrb_i];
else
datab_r <= 'bx;
end
assign datab_o = oenb_i ? 'bz : datab_r;
endmodule |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_de5.v
// Version: 1.00a
// Verilog Standard: Verilog-2001
// Description: Wrapper file for all riffa logic for Altera DE5 boards
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "altera.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_de5
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Quartus IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "ADE5")
(// Interface: Altera RX
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_EMPTY,
// Interface: Altera TX
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
// Interface: Altera Config
input [`SIG_CFG_CTL_W-1:0] TL_CFG_CTL,
input [`SIG_CFG_ADD_W-1:0] TL_CFG_ADD,
input [`SIG_CFG_STS_W-1:0] TL_CFG_STS,
// Interface: Altera Flow Control
input [`SIG_KO_CPLH_W-1:0] KO_CPL_SPC_HEADER,
input [`SIG_KO_CPLD_W-1:0] KO_CPL_SPC_DATA,
// Interface: Altera Interrupt
input APP_MSI_ACK,
output APP_MSI_REQ,
// Interface: Altera CLK/RESET
input PLD_CLK,
input RESET_STATUS,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
localparam C_VENDOR = "ALTERA";
localparam C_ALTERA_TX_READY_LATENCY = 2;
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire rx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_tlp;
wire rx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset;
wire rx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset;
wire rx_tlp_valid;
wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode;
wire tx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_tlp;
wire tx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset;
wire tx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset;
wire tx_tlp_valid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
assign clk = PLD_CLK;
assign rst_in = RESET_STATUS;
translation_altera
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(
// Outputs
.RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (tx_tlp_ready),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (rx_tlp_ready),
.TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
// Inputs
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
.APP_MSI_ACK (APP_MSI_ACK));
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset),
.RX_TLP_READY (rx_tlp_ready),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (rx_tlp),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode),
.TX_TLP_READY (tx_tlp_ready),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rst),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 8
(* X_CORE_INFO = "axi_protocol_converter_v2_1_8_axi_protocol_converter,Vivado 2016.1" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_2,axi_protocol_converter_v2_1_8_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_pc_2,axi_protocol_converter_v2_1_8_axi_protocol_converter,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH\
=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_2 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_8_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
bit global_bit;
module t (clk);
input clk;
integer cyc=0;
typedef struct packed {
bit b1;
bit b0;
} strp_t;
typedef struct packed {
strp_t x1;
strp_t x0;
} strp_strp_t;
typedef union packed {
strp_t x1;
strp_t x0;
} unip_strp_t;
typedef bit [2:1] arrp_t;
typedef arrp_t [4:3] arrp_arrp_t;
typedef strp_t [4:3] arrp_strp_t;
typedef bit arru_t [2:1];
typedef arru_t arru_arru_t [4:3];
typedef arrp_t arru_arrp_t [4:3];
typedef strp_t arru_strp_t [4:3];
strp_t v_strp;
strp_strp_t v_strp_strp;
unip_strp_t v_unip_strp;
arrp_t v_arrp;
arrp_arrp_t v_arrp_arrp;
arrp_strp_t v_arrp_strp;
arru_t v_arru;
arru_arru_t v_arru_arru;
arru_arrp_t v_arru_arrp;
arru_strp_t v_arru_strp;
real v_real;
real v_arr_real [2];
string v_string;
p #(.PARAM(2)) p2 ();
p #(.PARAM(3)) p3 ();
always @ (posedge clk) begin
cyc <= cyc + 1;
v_strp <= ~v_strp;
v_strp_strp <= ~v_strp_strp;
v_unip_strp <= ~v_unip_strp;
v_arrp_strp <= ~v_arrp_strp;
v_arrp <= ~v_arrp;
v_arrp_arrp <= ~v_arrp_arrp;
v_real <= v_real + 0.1;
v_string <= "foo";
v_arr_real[0] <= v_arr_real[0] + 0.2;
v_arr_real[1] <= v_arr_real[1] + 0.3;
for (integer b=3; b<=4; b++) begin
v_arru[b] <= ~v_arru[b];
v_arru_strp[b] <= ~v_arru_strp[b];
v_arru_arrp[b] <= ~v_arru_arrp[b];
for (integer a=3; a<=4; a++) begin
v_arru_arru[a][b] = ~v_arru_arru[a][b];
end
end
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module p;
parameter PARAM = 1;
initial global_bit = 1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DLATCH_P_PP_PG_N_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Refresh SM
// File : sm_ref.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module has the refresh state machine. At the
// begining of line_end signal from crt module, a refresh
// request is done to arbritation module and a refresh
// grant is obtained. A refresh cycle of 1, 3 or 5 is
// done according to the programmed value.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module sm_ref
(
input mem_clk,
input hreset_n,
input ref_gnt,
input svga_ack,
input c_cr11_b6,
input sync_c_crt_line_end,
output ref_svga_req,
output ref_req,
output m_t_ref_n,
output ref_cycle_done
);
//
// Define varialbes
//
reg [2:0] current_state;
reg [2:0] next_state;
reg [2:0] rfsh_cnt_out;
reg ref_s1, ref_s2, ref_s3, ref_s4, ref_s5;
wire rfsh_done;
wire en_ref_inc;
assign rfsh_done = (c_cr11_b6) ? (rfsh_cnt_out == 3'b101) :
(rfsh_cnt_out == 3'b011);
//
// Define state machine states
//
parameter ref_state0 = 3'b000,
ref_state1 = 3'b001,
ref_state2 = 3'b100,
ref_state3 = 3'b010,
ref_state4 = 3'b011,
ref_state5 = 3'b111;
always @(posedge mem_clk or negedge hreset_n) begin
if (!hreset_n) current_state <= ref_state0;
else current_state <= next_state;
end
always @* begin
ref_s1 = 1'b0;
ref_s2 = 1'b0;
ref_s3 = 1'b0;
ref_s4 = 1'b0;
ref_s5 = 1'b0;
case (current_state) // synopsys parallel_case full_case
ref_state0: begin
if (sync_c_crt_line_end) next_state = ref_state1;
else next_state = ref_state0;
end
ref_state1: begin
ref_s1 = 1'b1;
if (ref_gnt) next_state = ref_state2;
else next_state = ref_state1;
end
ref_state2: begin
ref_s2 = 1'b1;
if (svga_ack) next_state = ref_state3;
else next_state = ref_state2;
end
ref_state3: begin
ref_s3 = 1'b1;
next_state = ref_state4;
end
ref_state4: begin
ref_s4 = 1'b1;
if (rfsh_done) next_state = ref_state5;
else next_state = ref_state2;
end
ref_state5: begin
ref_s5 = 1'b1;
next_state = ref_state0;
end
endcase
end
assign ref_req = ref_s1 & ~ref_gnt;
assign ref_svga_req = ref_s2;
assign m_t_ref_n = ~ref_svga_req;
assign ref_cycle_done = ref_s5;
assign en_ref_inc = ref_s3;
always @ (posedge mem_clk or negedge hreset_n) begin
if (~hreset_n) rfsh_cnt_out <= 3'b000;
else if (ref_s5) rfsh_cnt_out <= 3'b000;
else if (en_ref_inc) rfsh_cnt_out <= rfsh_cnt_out + 1'b1;
else rfsh_cnt_out <= rfsh_cnt_out;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_PP_SYMBOL_V
`define SKY130_FD_SC_LS__FILL_DIODE_PP_SYMBOL_V
/**
* fill_diode: Fill diode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fill_diode (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_PP_SYMBOL_V
|
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLanguage=VERILOG,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,da_ps7_cnt=2}" *)
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
GND GND
(.G(GND_1));
design_1_processing_system7_0_1 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.I2C0_SCL_I(GND_1),
.I2C0_SDA_I(GND_1),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.SDIO0_WP(GND_1),
.USB0_VBUS_PWRFAULT(GND_1));
endmodule
|
// ethernet_port_interface_0.v
// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module ethernet_port_interface_0 (
input wire clk, // clock_reset.clk
input wire reset, // clock_reset_reset.reset
input wire [26:0] control_port_address, // control_port.address
input wire control_port_read, // .read
output wire [31:0] control_port_readdata, // .readdata
input wire control_port_write, // .write
input wire [31:0] control_port_writedata, // .writedata
output wire control_port_waitrequest, // .waitrequest
input wire [7:0] sink_data0, // avalon_streaming_sink.data
output wire sink_ready0, // .ready
input wire sink_valid0, // .valid
input wire [5:0] sink_error0, // .error
input wire sink_startofpacket0, // .startofpacket
input wire sink_endofpacket0, // .endofpacket
input wire [7:0] sink_data1, // avalon_streaming_sink_1.data
output wire sink_ready1, // .ready
input wire sink_valid1, // .valid
input wire [5:0] sink_error1, // .error
input wire sink_startofpacket1, // .startofpacket
input wire sink_endofpacket1, // .endofpacket
input wire [7:0] sink_data2, // avalon_streaming_sink_2.data
output wire sink_ready2, // .ready
input wire sink_valid2, // .valid
input wire [5:0] sink_error2, // .error
input wire sink_startofpacket2, // .startofpacket
input wire sink_endofpacket2, // .endofpacket
input wire [7:0] sink_data3, // avalon_streaming_sink_3.data
output wire sink_ready3, // .ready
input wire sink_valid3, // .valid
input wire [5:0] sink_error3, // .error
input wire sink_startofpacket3, // .startofpacket
input wire sink_endofpacket3, // .endofpacket
output wire [7:0] source_data0, // avalon_streaming_source.data
input wire source_ready0, // .ready
output wire source_valid0, // .valid
output wire source_error0, // .error
output wire source_startofpacket0, // .startofpacket
output wire source_endofpacket0, // .endofpacket
output wire [7:0] source_data1, // avalon_streaming_source_1.data
input wire source_ready1, // .ready
output wire source_valid1, // .valid
output wire source_error1, // .error
output wire source_startofpacket1, // .startofpacket
output wire source_endofpacket1, // .endofpacket
output wire [7:0] source_data2, // avalon_streaming_source_2.data
input wire source_ready2, // .ready
output wire source_valid2, // .valid
output wire source_error2, // .error
output wire source_startofpacket2, // .startofpacket
output wire source_endofpacket2, // .endofpacket
output wire [7:0] source_data3, // avalon_streaming_source_3.data
input wire source_ready3, // .ready
output wire source_valid3, // .valid
output wire source_error3, // .error
output wire source_startofpacket3, // .startofpacket
output wire source_endofpacket3, // .endofpacket
input wire rxm_read_bar_0_1, // avalon_slave.read
input wire rxm_write_bar_0_1, // .write
input wire [26:0] rxm_address_bar_0_1, // .address
input wire [31:0] rxm_writedata_bar_0_1, // .writedata
output wire rxm_wait_request_bar_0_1, // .waitrequest
output wire [31:0] rxm_readdata_bar_0_1, // .readdata
output wire rxm_read_valid_bar_0_1, // .readdatavalid
input wire rxm_read_bar_1, // avalon_slave_1.read
input wire rxm_write_bar_1, // .write
input wire [26:0] rxm_address_bar_1, // .address
input wire [31:0] rxm_writedata_bar_1, // .writedata
output wire rxm_wait_request_bar_1, // .waitrequest
output wire [31:0] rxm_readdata_bar_1, // .readdata
output wire rxm_read_valid_bar_1, // .readdatavalid
output wire txs_chip_select, // avalon_master.chipselect
output wire txs_read, // .read
output wire txs_write, // .write
output wire [31:0] txs_address, // .address
output wire [9:0] txs_burst_count, // .burstcount
output wire [31:0] txs_writedata, // .writedata
output wire [3:0] txs_byteenable, // .byteenable
input wire txs_read_valid, // .readdatavalid
input wire [31:0] txs_readdata, // .readdata
input wire txs_wait_request, // .waitrequest
input wire protocol, // conduit_end.export
input wire user_sw, // .export
output wire rxm_read_bar_1_out, // avalon_master_1.read
output wire rxm_write_bar_1_out, // .write
output wire [31:0] rxm_address_bar_1_out, // .address
input wire rxm_wait_request_bar_1_in, // .waitrequest
input wire [31:0] rxm_readdata_bar_1_in, // .readdata
input wire rxm_read_valid_bar_1_in, // .readdatavalid
output wire [31:0] rxm_writedata_bar_1_out, // .writedata
output wire interrupt_request // interrupt_sender_1.irq
);
ethernet_port_interface ethernet_port_interface_0 (
.clk (clk), // clock_reset.clk
.reset (reset), // clock_reset_reset.reset
.control_port_address (control_port_address), // control_port.address
.control_port_read (control_port_read), // .read
.control_port_readdata (control_port_readdata), // .readdata
.control_port_write (control_port_write), // .write
.control_port_writedata (control_port_writedata), // .writedata
.control_port_waitrequest (control_port_waitrequest), // .waitrequest
.sink_data0 (sink_data0), // avalon_streaming_sink.data
.sink_ready0 (sink_ready0), // .ready
.sink_valid0 (sink_valid0), // .valid
.sink_error0 (sink_error0), // .error
.sink_startofpacket0 (sink_startofpacket0), // .startofpacket
.sink_endofpacket0 (sink_endofpacket0), // .endofpacket
.sink_data1 (sink_data1), // avalon_streaming_sink_1.data
.sink_ready1 (sink_ready1), // .ready
.sink_valid1 (sink_valid1), // .valid
.sink_error1 (sink_error1), // .error
.sink_startofpacket1 (sink_startofpacket1), // .startofpacket
.sink_endofpacket1 (sink_endofpacket1), // .endofpacket
.sink_data2 (sink_data2), // avalon_streaming_sink_2.data
.sink_ready2 (sink_ready2), // .ready
.sink_valid2 (sink_valid2), // .valid
.sink_error2 (sink_error2), // .error
.sink_startofpacket2 (sink_startofpacket2), // .startofpacket
.sink_endofpacket2 (sink_endofpacket2), // .endofpacket
.sink_data3 (sink_data3), // avalon_streaming_sink_3.data
.sink_ready3 (sink_ready3), // .ready
.sink_valid3 (sink_valid3), // .valid
.sink_error3 (sink_error3), // .error
.sink_startofpacket3 (sink_startofpacket3), // .startofpacket
.sink_endofpacket3 (sink_endofpacket3), // .endofpacket
.source_data0 (source_data0), // avalon_streaming_source.data
.source_ready0 (source_ready0), // .ready
.source_valid0 (source_valid0), // .valid
.source_error0 (source_error0), // .error
.source_startofpacket0 (source_startofpacket0), // .startofpacket
.source_endofpacket0 (source_endofpacket0), // .endofpacket
.source_data1 (source_data1), // avalon_streaming_source_1.data
.source_ready1 (source_ready1), // .ready
.source_valid1 (source_valid1), // .valid
.source_error1 (source_error1), // .error
.source_startofpacket1 (source_startofpacket1), // .startofpacket
.source_endofpacket1 (source_endofpacket1), // .endofpacket
.source_data2 (source_data2), // avalon_streaming_source_2.data
.source_ready2 (source_ready2), // .ready
.source_valid2 (source_valid2), // .valid
.source_error2 (source_error2), // .error
.source_startofpacket2 (source_startofpacket2), // .startofpacket
.source_endofpacket2 (source_endofpacket2), // .endofpacket
.source_data3 (source_data3), // avalon_streaming_source_3.data
.source_ready3 (source_ready3), // .ready
.source_valid3 (source_valid3), // .valid
.source_error3 (source_error3), // .error
.source_startofpacket3 (source_startofpacket3), // .startofpacket
.source_endofpacket3 (source_endofpacket3), // .endofpacket
.rxm_read_bar_0_1 (rxm_read_bar_0_1), // avalon_slave.read
.rxm_write_bar_0_1 (rxm_write_bar_0_1), // .write
.rxm_address_bar_0_1 (rxm_address_bar_0_1), // .address
.rxm_writedata_bar_0_1 (rxm_writedata_bar_0_1), // .writedata
.rxm_wait_request_bar_0_1 (rxm_wait_request_bar_0_1), // .waitrequest
.rxm_readdata_bar_0_1 (rxm_readdata_bar_0_1), // .readdata
.rxm_read_valid_bar_0_1 (rxm_read_valid_bar_0_1), // .readdatavalid
.rxm_read_bar_1 (rxm_read_bar_1), // avalon_slave_1.read
.rxm_write_bar_1 (rxm_write_bar_1), // .write
.rxm_address_bar_1 (rxm_address_bar_1), // .address
.rxm_writedata_bar_1 (rxm_writedata_bar_1), // .writedata
.rxm_wait_request_bar_1 (rxm_wait_request_bar_1), // .waitrequest
.rxm_readdata_bar_1 (rxm_readdata_bar_1), // .readdata
.rxm_read_valid_bar_1 (rxm_read_valid_bar_1), // .readdatavalid
.txs_chip_select (txs_chip_select), // avalon_master.chipselect
.txs_read (txs_read), // .read
.txs_write (txs_write), // .write
.txs_address (txs_address), // .address
.txs_burst_count (txs_burst_count), // .burstcount
.txs_writedata (txs_writedata), // .writedata
.txs_byteenable (txs_byteenable), // .byteenable
.txs_read_valid (txs_read_valid), // .readdatavalid
.txs_readdata (txs_readdata), // .readdata
.txs_wait_request (txs_wait_request), // .waitrequest
.protocol (protocol), // conduit_end.export
.user_sw (user_sw), // .export
.rxm_read_bar_1_out (rxm_read_bar_1_out), // avalon_master_1.read
.rxm_write_bar_1_out (rxm_write_bar_1_out), // .write
.rxm_address_bar_1_out (rxm_address_bar_1_out), // .address
.rxm_wait_request_bar_1_in (rxm_wait_request_bar_1_in), // .waitrequest
.rxm_readdata_bar_1_in (rxm_readdata_bar_1_in), // .readdata
.rxm_read_valid_bar_1_in (rxm_read_valid_bar_1_in), // .readdatavalid
.rxm_writedata_bar_1_out (rxm_writedata_bar_1_out), // .writedata
.interrupt_request (interrupt_request) // interrupt_sender_1.irq
);
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2018 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief RTL equivalent of std::unordered_set (but with a fixed maximum size)
Single cycle insert/remove. The internal data structure is essentially a fully associative cache with
automatic de-duplication.
This is meant for VERY SMALL depths, as critical paths will get massive if you have more than a handful of elements!
*/
module UnorderedSet #(
parameter DEPTH = 16, //number of elements in the set
parameter ITER_SIZE = 4, //must be clog2(DEPTH)
parameter KEY_SIZE = 16 //Size of a single key element in bits
) (
input wire clk,
input wire insert_en, //assert to add a new element
input wire[KEY_SIZE-1:0] insert_key, //the element to insert
output reg insert_ok = 0, //goes high after 1 cycle on successful insert
//stays low to indicate the set is full
input wire iter_inc, //assert to increment the iterator at iter_in
input wire iter_begin, //assert to look up the first element in the set, ignoring iter_in
input wire[ITER_SIZE-1:0] iter_in, //previous value of the iterator
output reg iter_end = 0, //true if we hit the end (iter_next not valid)
output reg[ITER_SIZE-1:0] iter_next = 0, //next value of the iterator
output reg[KEY_SIZE-1:0] iter_key = 0, //key associated with this iterator
input wire remove_en, //assert to clear an item by iterator (remove by key not supported)
input wire[ITER_SIZE-1:0] remove_iter //the iterator to remove
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual storage array
integer i;
reg slot_valid[DEPTH-1:0];
reg[KEY_SIZE-1:0] slot_key[DEPTH-1:0];
initial begin
for(i=0; i<DEPTH; i=i+1) begin
slot_valid[i] <= 0;
slot_key[i] <= 0;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Iterator management. This is combinatorial so external registers can be used.
reg hit = 0;
always @(*) begin
iter_end <= 1; //Default to "end of set, iterator not valid"
iter_next <= 0;
hit = 0;
//When RESETTING the iterator: find the first valid element
if(iter_begin) begin
for(i=0; i<DEPTH; i=i+1) begin
if(slot_valid[i] && !hit) begin
hit = 1;
iter_end <= 0;
iter_next <= i;
iter_key <= slot_key[i];
end
end
end
//When INCREMENTING the iterator: find the first valid element with index >= iter_in
else if(iter_inc) begin
for(i=0; i<DEPTH; i=i+1) begin
if(slot_valid[i] && !hit && (i > iter_in) ) begin
hit = 1;
iter_end <= 0;
iter_next <= i;
iter_key <= slot_key[i];
end
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Insertion/removal
always @(posedge clk) begin
insert_ok = 0;
//Process inserts
if(insert_en) begin
//Check if the key is already in the set. If so, no action needed.
for(i=0; i<DEPTH; i=i+1) begin
if(slot_valid[i] && (slot_key[i] == insert_key) ) begin
insert_ok = 1;
end
end
//If not in the set, insert it.
for(i=0; i<DEPTH; i=i+1) begin
if(!slot_valid[i] && !insert_ok) begin
insert_ok = 1;
slot_valid[i] <= 1;
slot_key[i] <= insert_key;
end
end
end
//Process removal
if(remove_en)
slot_valid[remove_iter] <= 0;
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression evaluates to a value outside the range specified by parameters min and max");
end
end
end
assign fire_2state_1 = ((test_expr < min) || (test_expr > max));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
// REVISIT: update only if SANITY on?
prev_test_expr <= test_expr; // deliberately not reset
end
wire fire_cover_1, fire_cover_2, fire_cover_3;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("test_expr_at_min covered"); // corner
end
if (fire_cover_3) begin
ovl_cover_t("test_expr_at_max covered"); // corner
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == min));
assign fire_cover_3 = ((OVL_COVER_CORNER_ON > 0) && (test_expr == max));
`endif // OVL_COVER_ON
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rambuffer.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rambuffer (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [16:0] address_a;
input [16:0] address_b;
input clock;
input [0:0] data_a;
input [0:0] data_b;
input wren_a;
input wren_b;
output [0:0] q_a;
output [0:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [0:0] q_a = sub_wire0[0:0];
wire [0:0] q_b = sub_wire1[0:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (wren_a),
.address_b (address_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 131072,
altsyncram_component.numwords_b = 131072,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 17,
altsyncram_component.widthad_b = 17,
altsyncram_component.width_a = 1,
altsyncram_component.width_b = 1,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "131072"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "131072"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "17"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "17"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 17 0 INPUT NODEFVAL "address_a[16..0]"
// Retrieval info: USED_PORT: address_b 0 0 17 0 INPUT NODEFVAL "address_b[16..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 1 0 INPUT NODEFVAL "data_a[0..0]"
// Retrieval info: USED_PORT: data_b 0 0 1 0 INPUT NODEFVAL "data_b[0..0]"
// Retrieval info: USED_PORT: q_a 0 0 1 0 OUTPUT NODEFVAL "q_a[0..0]"
// Retrieval info: USED_PORT: q_b 0 0 1 0 OUTPUT NODEFVAL "q_b[0..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 17 0 address_a 0 0 17 0
// Retrieval info: CONNECT: @address_b 0 0 17 0 address_b 0 0 17 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 1 0 data_a 0 0 1 0
// Retrieval info: CONNECT: @data_b 0 0 1 0 data_b 0 0 1 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 1 0 @q_a 0 0 1 0
// Retrieval info: CONNECT: q_b 0 0 1 0 @q_b 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rambuffer.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rambuffer.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rambuffer.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rambuffer.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rambuffer_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rambuffer_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21A_TB_V
`define SKY130_FD_SC_HS__O21A_TB_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1 = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1 = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1 = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1 = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__o21a dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21A_TB_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:29:26 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire operation_reg_0_, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_fmtted_Result_31_, FPSENCOS_enab_d_ff4_Xn,
FPSENCOS_enab_d_ff4_Yn, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_operation_out, FPSENCOS_enab_d_ff5_data_out,
FPSENCOS_enab_RB3, FPSENCOS_enab_d_ff_RB1, FPSENCOS_enab_d_ff4_Zn,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_exp_operation_A_S, FPMULT_FSM_barrel_shifter_load,
FPMULT_FSM_final_result_load, FPMULT_FSM_adder_round_norm_load,
FPMULT_FSM_load_second_step, FPMULT_FSM_exp_operation_load_result,
FPMULT_FSM_first_phase_load, FPMULT_zero_flag, FPADDSUB_N60,
FPADDSUB_N59, FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG,
FPADDSUB__19_net_, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2, FPADDSUB__6_net_,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_Shift_reg_FLAGS_7_5, FPADDSUB_Shift_reg_FLAGS_7_6,
FPADDSUB_enable_Pipeline_input, FPSENCOS_ITER_CONT_net8093770,
FPSENCOS_ITER_CONT_N5, FPSENCOS_ITER_CONT_N4, FPSENCOS_ITER_CONT_N3,
FPMULT_FS_Module_net8093716, FPMULT_Exp_module_Overflow_flag_A,
FPMULT_Exp_module_Overflow_A, FPMULT_Sgf_operation_EVEN1_S_B_14_,
FPMULT_final_result_ieee_Module_Sign_S_mux,
FPADDSUB_inst_ShiftRegister_net8093608,
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518,
FPSENCOS_d_ff5_data_out_net8093734,
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446,
FPADDSUB_SGF_STAGE_DMP_net8093500,
FPADDSUB_NRM_STAGE_Raw_mant_net8093482, FPSENCOS_reg_Z0_net8093734,
FPSENCOS_reg_val_muxZ_2stage_net8093734,
FPSENCOS_reg_shift_y_net8093734, FPSENCOS_d_ff4_Xn_net8093734,
FPSENCOS_d_ff4_Yn_net8093734, FPSENCOS_d_ff4_Zn_net8093734,
FPADDSUB_INPUT_STAGE_OPERANDY_net8093446,
FPADDSUB_EXP_STAGE_DMP_net8093500, FPADDSUB_SHT1_STAGE_DMP_net8093500,
FPADDSUB_SHT2_STAGE_DMP_net8093500,
FPADDSUB_SHT2_SHIFT_DATA_net8093482,
FPMULT_Exp_module_exp_result_m_net8093680,
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662,
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644,
FPMULT_Adder_M_Add_Subt_Result_net8093626,
FPMULT_Operands_load_reg_XMRegister_net8093698,
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446, n30,
n106, n107, n810, n813, n816, n819, n824, n829, n830, n834, n842,
n843, n844, n846, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n859, n860, n861, n862, n863, n864, n865, n874, n875,
DP_OP_26J311_126_1325_n18, DP_OP_26J311_126_1325_n17,
DP_OP_26J311_126_1325_n16, DP_OP_26J311_126_1325_n15,
DP_OP_26J311_126_1325_n14, DP_OP_26J311_126_1325_n8,
DP_OP_26J311_126_1325_n7, DP_OP_26J311_126_1325_n6,
DP_OP_26J311_126_1325_n5, DP_OP_26J311_126_1325_n4,
DP_OP_26J311_126_1325_n3, DP_OP_26J311_126_1325_n2,
DP_OP_26J311_126_1325_n1, DP_OP_234J311_129_4955_n22,
DP_OP_234J311_129_4955_n21, DP_OP_234J311_129_4955_n20,
DP_OP_234J311_129_4955_n19, DP_OP_234J311_129_4955_n18,
DP_OP_234J311_129_4955_n17, DP_OP_234J311_129_4955_n16,
DP_OP_234J311_129_4955_n15, DP_OP_234J311_129_4955_n9,
DP_OP_234J311_129_4955_n8, DP_OP_234J311_129_4955_n7,
DP_OP_234J311_129_4955_n6, DP_OP_234J311_129_4955_n5,
DP_OP_234J311_129_4955_n4, DP_OP_234J311_129_4955_n3,
DP_OP_234J311_129_4955_n2, DP_OP_234J311_129_4955_n1, intadd_1045_CI,
intadd_1045_n3, intadd_1045_n2, intadd_1045_n1, intadd_1046_CI,
intadd_1046_n3, intadd_1046_n2, intadd_1046_n1, intadd_1047_CI,
intadd_1047_SUM_2_, intadd_1047_SUM_1_, intadd_1047_SUM_0_,
intadd_1047_n3, intadd_1047_n2, intadd_1047_n1, add_x_246_A_7_,
add_x_246_A_6_, add_x_246_A_5_, add_x_246_A_3_, add_x_246_A_2_,
add_x_246_A_1_, add_x_246_A_0_, add_x_246_n17, add_x_246_n2,
add_x_69_n282, add_x_69_n272, add_x_69_n271, add_x_69_n268,
add_x_69_n257, add_x_69_n250, add_x_69_n244, add_x_69_n243,
add_x_69_n242, add_x_69_n241, add_x_69_n239, add_x_69_n238,
add_x_69_n236, add_x_69_n235, add_x_69_n233, add_x_69_n231,
add_x_69_n230, add_x_69_n228, add_x_69_n113, add_x_69_n105,
add_x_69_n95, add_x_69_n94, add_x_69_n85, add_x_69_n77, add_x_69_n69,
add_x_69_n57, add_x_69_n50, add_x_69_n47, add_x_69_n39, add_x_69_n26,
add_x_69_n24, add_x_69_n23, add_x_69_n22, add_x_69_n21, add_x_69_n19,
DP_OP_496J311_122_3540_n1516, DP_OP_496J311_122_3540_n1515,
DP_OP_496J311_122_3540_n1514, DP_OP_496J311_122_3540_n1513,
DP_OP_496J311_122_3540_n1509, DP_OP_496J311_122_3540_n1498,
DP_OP_496J311_122_3540_n1495, DP_OP_496J311_122_3540_n1476,
DP_OP_496J311_122_3540_n1467, DP_OP_496J311_122_3540_n1465,
DP_OP_496J311_122_3540_n1464, DP_OP_496J311_122_3540_n1456,
DP_OP_496J311_122_3540_n1203, DP_OP_496J311_122_3540_n1202,
DP_OP_496J311_122_3540_n1138, DP_OP_496J311_122_3540_n1120,
DP_OP_496J311_122_3540_n1118, DP_OP_496J311_122_3540_n1117,
DP_OP_496J311_122_3540_n1114, DP_OP_496J311_122_3540_n1108,
DP_OP_496J311_122_3540_n1107, DP_OP_496J311_122_3540_n1105,
DP_OP_496J311_122_3540_n1103, DP_OP_496J311_122_3540_n1097,
DP_OP_496J311_122_3540_n1096, DP_OP_496J311_122_3540_n846,
DP_OP_496J311_122_3540_n778, DP_OP_497J311_123_1725_n795,
DP_OP_497J311_123_1725_n794, DP_OP_497J311_123_1725_n793,
DP_OP_497J311_123_1725_n792, DP_OP_497J311_123_1725_n791,
DP_OP_497J311_123_1725_n780, DP_OP_497J311_123_1725_n779,
DP_OP_497J311_123_1725_n721, DP_OP_497J311_123_1725_n720,
DP_OP_497J311_123_1725_n719, DP_OP_497J311_123_1725_n715,
DP_OP_497J311_123_1725_n714, DP_OP_497J311_123_1725_n709,
DP_OP_497J311_123_1725_n705, DP_OP_497J311_123_1725_n699,
DP_OP_497J311_123_1725_n693, DP_OP_497J311_123_1725_n687,
DP_OP_497J311_123_1725_n685, DP_OP_497J311_123_1725_n684,
DP_OP_497J311_123_1725_n683, DP_OP_497J311_123_1725_n675,
DP_OP_497J311_123_1725_n674, DP_OP_497J311_123_1725_n638,
DP_OP_497J311_123_1725_n635, DP_OP_497J311_123_1725_n634,
DP_OP_497J311_123_1725_n629, DP_OP_497J311_123_1725_n628,
DP_OP_497J311_123_1725_n623, DP_OP_497J311_123_1725_n613,
DP_OP_497J311_123_1725_n609, DP_OP_497J311_123_1725_n388,
DP_OP_497J311_123_1725_n386, DP_OP_497J311_123_1725_n385,
DP_OP_497J311_123_1725_n378, DP_OP_497J311_123_1725_n367,
DP_OP_497J311_123_1725_n357, DP_OP_497J311_123_1725_n336,
DP_OP_497J311_123_1725_n335, DP_OP_497J311_123_1725_n324,
DP_OP_498J311_124_1725_n805, DP_OP_498J311_124_1725_n804,
DP_OP_498J311_124_1725_n802, DP_OP_498J311_124_1725_n801,
DP_OP_498J311_124_1725_n799, DP_OP_498J311_124_1725_n798,
DP_OP_498J311_124_1725_n795, DP_OP_498J311_124_1725_n793,
DP_OP_498J311_124_1725_n792, DP_OP_498J311_124_1725_n791,
DP_OP_498J311_124_1725_n789, DP_OP_498J311_124_1725_n788,
DP_OP_498J311_124_1725_n787, DP_OP_498J311_124_1725_n786,
DP_OP_498J311_124_1725_n785, DP_OP_498J311_124_1725_n784,
DP_OP_498J311_124_1725_n783, DP_OP_498J311_124_1725_n782,
DP_OP_498J311_124_1725_n732, DP_OP_498J311_124_1725_n730,
DP_OP_498J311_124_1725_n729, DP_OP_498J311_124_1725_n728,
DP_OP_498J311_124_1725_n727, DP_OP_498J311_124_1725_n726,
DP_OP_498J311_124_1725_n725, DP_OP_498J311_124_1725_n724,
DP_OP_498J311_124_1725_n723, DP_OP_498J311_124_1725_n722,
DP_OP_498J311_124_1725_n721, DP_OP_498J311_124_1725_n717,
DP_OP_498J311_124_1725_n708, DP_OP_498J311_124_1725_n698,
DP_OP_498J311_124_1725_n694, DP_OP_498J311_124_1725_n645,
DP_OP_498J311_124_1725_n642, DP_OP_498J311_124_1725_n641,
DP_OP_498J311_124_1725_n640, DP_OP_498J311_124_1725_n638,
DP_OP_498J311_124_1725_n635, DP_OP_498J311_124_1725_n634,
DP_OP_498J311_124_1725_n630, DP_OP_498J311_124_1725_n618,
DP_OP_498J311_124_1725_n394, DP_OP_498J311_124_1725_n392,
DP_OP_498J311_124_1725_n380, DP_OP_499J311_125_1651_n202,
DP_OP_499J311_125_1651_n199, DP_OP_499J311_125_1651_n194,
DP_OP_499J311_125_1651_n191, DP_OP_499J311_125_1651_n190,
DP_OP_499J311_125_1651_n187, DP_OP_499J311_125_1651_n186,
DP_OP_499J311_125_1651_n185, DP_OP_499J311_125_1651_n166,
DP_OP_499J311_125_1651_n93, DP_OP_499J311_125_1651_n86,
DP_OP_499J311_125_1651_n84, DP_OP_499J311_125_1651_n83,
DP_OP_499J311_125_1651_n81, DP_OP_499J311_125_1651_n79,
DP_OP_499J311_125_1651_n78, DP_OP_499J311_125_1651_n74,
DP_OP_499J311_125_1651_n73, DP_OP_499J311_125_1651_n72,
DP_OP_499J311_125_1651_n69, DP_OP_499J311_125_1651_n64,
DP_OP_499J311_125_1651_n61, DP_OP_499J311_125_1651_n54,
DP_OP_499J311_125_1651_n53, DP_OP_499J311_125_1651_n48,
DP_OP_499J311_125_1651_n38, DP_OP_499J311_125_1651_n29,
DP_OP_499J311_125_1651_n13, DP_OP_499J311_125_1651_n12,
DP_OP_499J311_125_1651_n10, DP_OP_499J311_125_1651_n9, n910, n914,
n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925,
n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936,
n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947,
n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958,
n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969,
n970, n971, n972, n973, n974, n975, n976, n977, n978, n979, n980,
n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991,
n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002,
n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012,
n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022,
n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1032, n1033,
n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043,
n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053,
n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063,
n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073,
n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083,
n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476,
n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486,
n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496,
n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506,
n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516,
n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526,
n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536,
n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726,
n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736,
n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746,
n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756,
n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766,
n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776,
n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786,
n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796,
n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806,
n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816,
n1817, n1818, n1819, n1820, n1821, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597,
n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607,
n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617,
n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627,
n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637,
n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647,
n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697,
n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707,
n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717,
n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727,
n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737,
n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747,
n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757,
n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767,
n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777,
n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787,
n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797,
n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807,
n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817,
n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827,
n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837,
n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847,
n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857,
n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867,
n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877,
n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887,
n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897,
n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907,
n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917,
n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927,
n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937,
n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947,
n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957,
n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967,
n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977,
n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987,
n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997,
n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007,
n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017,
n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027,
n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037,
n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047,
n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057,
n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067,
n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077,
n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087,
n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097,
n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107,
n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117,
n3118, n3119, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128,
n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138,
n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148,
n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158,
n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168,
n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178,
n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188,
n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198,
n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208,
n3209, n3210, n3211, n3213, n3214, n3215, n3216, n3217, n3218, n3219,
n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229,
n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239,
n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259,
n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269,
n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279,
n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289,
n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299,
n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309,
n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319,
n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329,
n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339,
n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349,
n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359,
n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369,
n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379,
n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389,
n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399,
n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409,
n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419,
n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429,
n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439,
n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449,
n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459,
n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469,
n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479,
n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489,
n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499,
n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509,
n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519,
n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529,
n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539,
n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549,
n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559,
n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569,
n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579,
n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589,
n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599,
n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609,
n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619,
n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629,
n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639,
n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649,
n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659,
n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669,
n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679,
n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689,
n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699,
n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709,
n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719,
n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729,
n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739,
n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749,
n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759,
n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769,
n3770, n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779,
n3780, n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789,
n3790, n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799,
n3800, n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809,
n3810, n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819,
n3820, n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829,
n3830, n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839,
n3840, n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849,
n3850, n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859,
n3860, n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869,
n3870, n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879,
n3880, n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889,
n3890, n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899,
n3900, n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909,
n3910, n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919,
n3920, n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929,
n3930, n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939,
n3940, n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949,
n3950, n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959,
n3960, n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969,
n3970, n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979,
n3980, n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989,
n3990, n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999,
n4000, n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009,
n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019,
n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029,
n4030, n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039,
n4040, n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049,
n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059,
n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069,
n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079,
n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089,
n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099,
n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109,
n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119,
n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129,
n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139,
n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149,
n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159,
n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169,
n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179,
n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189,
n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199,
n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209,
n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219,
n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229,
n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239,
n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249,
n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259,
n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269,
n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279,
n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289,
n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299,
n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309,
n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319,
n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329,
n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339,
n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349,
n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359,
n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369,
n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379,
n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389,
n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399,
n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409,
n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419,
n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429,
n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439,
n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449,
n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459,
n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469,
n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479,
n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489,
n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499,
n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509,
n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519,
n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529,
n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539,
n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549,
n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559,
n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569,
n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579,
n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589,
n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599,
n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609,
n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619,
n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629,
n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639,
n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649,
n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659,
n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669,
n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679,
n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689,
n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699,
n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709,
n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719,
n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729,
n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739,
n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749,
n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759,
n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769,
n4770, n4771, n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779,
n4780, n4781, n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789,
n4790, n4791, n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799,
n4800, n4801, n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809,
n4810, n4811, n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819,
n4820, n4821, n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829,
n4830, n4831, n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839,
n4840, n4841, n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849,
n4850, n4851, n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859,
n4860, n4861, n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869,
n4870, n4871, n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879,
n4880, n4881, n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889,
n4890, n4891, n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899,
n4900, n4901, n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909,
n4910, n4911, n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919,
n4920, n4921, n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929,
n4930, n4931, n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939,
n4940, n4941, n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949,
n4950, n4951, n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959,
n4960, n4961, n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969,
n4970, n4971, n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979,
n4980, n4981, n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989,
n4990, n4991, n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999,
n5000, n5001, n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009,
n5010, n5011, n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019,
n5020, n5021, n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029,
n5030, n5031, n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039,
n5040, n5041, n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049,
n5050, n5051, n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059,
n5060, n5061, n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069,
n5070, n5071, n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079,
n5080, n5081, n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089,
n5090, n5091, n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099,
n5100, n5101, n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109,
n5110, n5111, n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119,
n5120, n5121, n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129,
n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139,
n5140, n5141, n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149,
n5150, n5151, n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159,
n5160, n5161, n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169,
n5170, n5171, n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179,
n5180, n5181, n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189,
n5190, n5191, n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199,
n5200, n5201, n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209,
n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219,
n5220, n5221, n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229,
n5230, n5231, n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239,
n5240, n5241, n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249,
n5250, n5251, n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259,
n5260, n5261, n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269,
n5270, n5271, n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279,
n5280, n5281, n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289,
n5290, n5291, n5292, n5293, n5294, n5295, n5296, n5297, n5298, n5299,
n5300, n5301, n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309,
n5310, n5311, n5312, n5313, n5314, n5315, n5316, n5317, n5318, n5319,
n5320, n5321, n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329,
n5330, n5331, n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339,
n5340, n5341, n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349,
n5350, n5351, n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359,
n5360, n5361, n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369,
n5370, n5371, n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379,
n5380, n5381, n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389,
n5390, n5391, n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399,
n5400, n5401, n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409,
n5410, n5411, n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419,
n5420, n5421, n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429,
n5430, n5431, n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439,
n5440, n5441, n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449,
n5450, n5451, n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459,
n5460, n5461, n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469,
n5470, n5471, n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479,
n5480, n5481, n5482, n5483, n5484, n5485, n5486, n5487, n5488, n5489,
n5490, n5491, n5492, n5493, n5494, n5495, n5496, n5497, n5498, n5499,
n5500, n5501, n5502, n5503, n5504, n5505, n5506, n5507, n5508, n5509,
n5510, n5511, n5512, n5513, n5514, n5515, n5516, n5517, n5518, n5519,
n5520, n5521, n5522, n5523, n5524, n5525, n5526, n5527, n5528, n5529,
n5530, n5531, n5532, n5533, n5534, n5535, n5536, n5537, n5538, n5539,
n5540, n5541, n5542, n5543, n5544, n5545, n5546, n5547, n5548, n5549,
n5550, n5551, n5552, n5553, n5554, n5555, n5556, n5557, n5559, n5560,
n5561, n5562, n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570,
n5571, n5572, n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580,
n5581, n5582, n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590,
n5591, n5592, n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600,
n5601, n5602, n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610,
n5611, n5612, n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620,
n5621, n5622, n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630,
n5631, n5632, n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640,
n5641, n5642, n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650,
n5651, n5652, n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660,
n5661, n5662, n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670,
n5671, n5672, n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680,
n5681, n5682, n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690,
n5691, n5692, n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700,
n5701, n5702, n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710,
n5711, n5712, n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720,
n5721, n5722, n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730,
n5731, n5732, n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740,
n5741, n5742, n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750,
n5751, n5752, n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760,
n5761, n5762, n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770,
n5771, n5772, n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780,
n5781, n5782, n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790,
n5791, n5792, n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800,
n5801, n5802, n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810,
n5811, n5812, n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820,
n5821, n5822, n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830,
n5831, n5832, n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840,
n5841, n5842, n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850,
n5851, n5852, n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860,
n5861, n5862, n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870,
n5871, n5872, n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880,
n5881, n5882, n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890,
n5891, n5892, n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900,
n5901, n5902, n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910,
n5911, n5912, n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920,
n5921, n5922, n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930,
n5931, n5932, n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940,
n5941, n5942, n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950,
n5951, n5952, n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960,
n5961, n5962, n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970,
n5971, n5972, n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980,
n5981, n5982, n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990,
n5991, n5992, n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000,
n6001, n6002, n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010,
n6011, n6012, n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020,
n6021, n6022, n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030,
n6031, n6032, n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040,
n6041, n6042, n6044, n6045, n6047, n6048, n6049, n6050, n6051, n6052,
n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062,
n6063, n6064, n6065, n6066, n6067, n6068;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] add_subt_data1;
wire [30:0] add_subt_data2;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_mux_sal;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [25:4] FPSENCOS_data_out_LUT;
wire [7:0] FPSENCOS_sh_exp_y;
wire [7:0] FPSENCOS_sh_exp_x;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_first_mux_Z;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_first_mux_Y;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_first_mux_X;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [22:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [30:2] FPMULT_Op_MY;
wire [30:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [19:0] FPMULT_P_Sgf;
wire [31:0] FPADDSUB_formatted_number_W;
wire [25:1] FPADDSUB_Raw_mant_SGF;
wire [25:2] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [3:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] FPADDSUB_LZD_raw_out_EWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [27:0] FPADDSUB_DmP_INIT_EWSW;
wire [30:0] FPADDSUB_DMP_INIT_EWSW;
wire [30:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_next;
wire [3:1] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [19:0] FPMULT_Sgf_operation_Result;
wire [20:2] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [22:1] FPMULT_Adder_M_result_A_adder;
wire [22:0] FPMULT_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] FPMULT_final_result_ieee_Module_Exp_S_mux;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 FPSENCOS_ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(n5960), .ENCLK(FPSENCOS_ITER_CONT_net8093770), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function FPMULT_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n846), .ENCLK(FPMULT_FS_Module_net8093716), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n875), .ENCLK(FPADDSUB_inst_ShiftRegister_net8093608),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[1]), .ENCLK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 FPSENCOS_d_ff5_data_out_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff5_data_out), .ENCLK(
FPSENCOS_d_ff5_data_out_net8093734), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[0]), .ENCLK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__19_net_), .ENCLK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[2]), .ENCLK(
FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 FPSENCOS_reg_Z0_clk_gate_Q_reg ( .CLK(
clk), .EN(FPSENCOS_enab_d_ff_RB1), .ENCLK(FPSENCOS_reg_Z0_net8093734),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 FPSENCOS_reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
FPSENCOS_reg_val_muxZ_2stage_net8093734), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 FPSENCOS_reg_shift_y_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_RB3), .ENCLK(
FPSENCOS_reg_shift_y_net8093734), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 FPSENCOS_d_ff4_Xn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Xn), .ENCLK(
FPSENCOS_d_ff4_Xn_net8093734), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 FPSENCOS_d_ff4_Yn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Yn), .ENCLK(
FPSENCOS_d_ff4_Yn_net8093734), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 FPSENCOS_d_ff4_Zn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Zn), .ENCLK(
FPSENCOS_d_ff4_Zn_net8093734), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_enable_Pipeline_input), .ENCLK(
FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_6), .ENCLK(
FPADDSUB_EXP_STAGE_DMP_net8093500), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_5), .ENCLK(
FPADDSUB_SHT1_STAGE_DMP_net8093500), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__6_net_), .ENCLK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 FPMULT_Exp_module_exp_result_m_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_exp_operation_load_result), .ENCLK(
FPMULT_Exp_module_exp_result_m_net8093680), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 FPMULT_Sgf_operation_EVEN1_finalreg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_load_second_step), .ENCLK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 FPMULT_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_barrel_shifter_load), .ENCLK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 FPMULT_Adder_M_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_adder_round_norm_load), .ENCLK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 FPMULT_Operands_load_reg_XMRegister_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_first_phase_load), .ENCLK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 FPMULT_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_final_result_load), .ENCLK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .TE(
1'b0) );
DFFRXLTS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n6005),
.QN(n975) );
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n6009), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n6003), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n1059), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n6001), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n6001), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n6001), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n6001), .Q(
dataB[31]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n6048), .CK(
FPADDSUB_inst_ShiftRegister_net8093608), .RN(n5903), .Q(
FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
FPADDSUB_inst_ShiftRegister_net8093608), .RN(n5903), .Q(
FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
FPADDSUB_inst_ShiftRegister_net8093608), .RN(n5903), .Q(
FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
FPADDSUB_inst_ShiftRegister_net8093608), .RN(n5903), .Q(
FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5904), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5904), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5904), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5904), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5904), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(region_flag[0]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5963), .Q(
FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n1193) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n852), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n1059), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n862), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n6008), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n856), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n6009), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n864), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n4442), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(FPSENCOS_data_out_LUT[4]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5963), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n853), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n855), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n859), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n5709), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n861), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n854), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n860), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n851), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n863), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n865), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5998), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n850), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5997), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n849), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5997), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n848), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5997), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(FPSENCOS_data_out_LUT[25]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5997), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n857), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5997), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5997), .Q(FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5997), .Q(FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5997), .Q(FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5997), .Q(FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(Data_1[10]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(Data_1[11]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(Data_1[12]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(Data_1[13]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5996), .Q(FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(Data_1[14]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(Data_1[15]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(Data_1[16]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(Data_1[17]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(Data_1[18]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(Data_1[19]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(Data_1[20]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(Data_1[21]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(Data_1[22]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(Data_1[23]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5995), .Q(FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(Data_1[24]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5994), .Q(FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(Data_1[25]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5994), .Q(FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(Data_1[26]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5994), .Q(FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(Data_1[27]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5994), .Q(FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(Data_1[28]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5994), .Q(FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(Data_1[29]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5994), .Q(FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(Data_1[30]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5994), .Q(FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(Data_1[31]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5994), .Q(FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(FPSENCOS_sh_exp_x[0]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5994), .Q(
FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(FPSENCOS_sh_exp_x[1]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5994), .Q(
FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(FPSENCOS_sh_exp_x[2]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(FPSENCOS_sh_exp_x[3]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(FPSENCOS_sh_exp_x[4]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(FPSENCOS_sh_exp_x[5]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(FPSENCOS_sh_exp_x[6]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(FPSENCOS_sh_exp_x[7]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(FPSENCOS_sh_exp_y[0]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(FPSENCOS_sh_exp_y[1]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(FPSENCOS_sh_exp_y[2]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(FPSENCOS_sh_exp_y[3]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5993), .Q(
FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(FPSENCOS_sh_exp_y[4]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n6007), .Q(
FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(FPSENCOS_sh_exp_y[5]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n6007), .Q(
FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(FPSENCOS_sh_exp_y[6]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n824), .Q(
FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(FPSENCOS_sh_exp_y[7]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n824), .Q(
FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n824), .Q(FPSENCOS_d_ff_Xn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_X[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n6006), .Q(FPSENCOS_d_ff2_X[23]), .QN(n5769) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n6006), .Q(FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n6007), .Q(FPSENCOS_d_ff_Xn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff_Xn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff_Xn[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5991), .Q(FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Y[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5991), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n5768) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(FPSENCOS_mux_sal[23]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5991), .Q(cordic_result[23])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5991), .Q(FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(FPSENCOS_mux_sal[24]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5991), .Q(cordic_result[24])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5991), .Q(FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(FPSENCOS_mux_sal[25]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5991), .Q(cordic_result[25])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5991), .Q(FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(FPSENCOS_mux_sal[26]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5990), .Q(cordic_result[26])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5990), .Q(FPSENCOS_d_ff_Yn[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(FPSENCOS_mux_sal[27]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5990), .Q(cordic_result[27])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5990), .Q(FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Y[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5990), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n5831) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(FPSENCOS_mux_sal[28]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5990), .Q(cordic_result[28])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5990), .Q(FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(FPSENCOS_mux_sal[29]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5989), .Q(cordic_result[29])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5989), .Q(FPSENCOS_d_ff_Yn[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(FPSENCOS_mux_sal[30]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5989), .Q(cordic_result[30])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5989), .Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Z[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5989), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5989), .Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Z[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5989), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5989), .Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Z[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5989), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Z[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Z[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Z[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Z[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Z[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5988), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(FPADDSUB_DmP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5905), .Q(
FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(FPADDSUB_DmP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5905), .Q(
FPADDSUB_DmP_EXP_EWSW[24]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(FPADDSUB_DmP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5905), .Q(
FPADDSUB_DmP_EXP_EWSW[25]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(FPADDSUB_DmP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5906), .Q(
FPADDSUB_DmP_EXP_EWSW[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(FPADDSUB_DmP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5906), .Q(
FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(add_subt_data2[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5906), .Q(
FPADDSUB_intDY_EWSW[29]), .QN(n5724) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(add_subt_data2[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5906), .Q(
FPADDSUB_intDY_EWSW[30]), .QN(n5782) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5906), .Q(
FPADDSUB_DMP_EXP_EWSW[23]), .QN(n5783) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5906), .Q(
FPADDSUB_DMP_EXP_EWSW[24]), .QN(n5798) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5906), .Q(
FPADDSUB_DMP_EXP_EWSW[25]), .QN(n5828) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5906), .Q(
FPADDSUB_DMP_EXP_EWSW[26]), .QN(n5827) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_INIT_EWSW[28]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_INIT_EWSW[29]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_INIT_EWSW[30]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_EXP_EWSW[23]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_EXP_EWSW[24]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_EXP_EWSW[25]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_EXP_EWSW[26]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_EXP_EWSW[27]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_EXP_EWSW[28]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5907), .Q(
FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_EXP_EWSW[29]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_EXP_EWSW[30]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT1_EWSW[23]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT2_EWSW[23]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5923), .Q(
FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(FPADDSUB_DMP_SFG[23]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5923), .Q(
FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5923), .Q(
FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT1_EWSW[24]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT2_EWSW[24]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5923), .Q(
FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(FPADDSUB_DMP_SFG[24]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5923), .Q(
FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5923), .Q(
FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT1_EWSW[25]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT2_EWSW[25]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5924), .Q(
FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(FPADDSUB_DMP_SFG[25]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5924), .Q(
FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5923), .Q(
FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT1_EWSW[26]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT2_EWSW[26]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5924), .Q(
FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(FPADDSUB_DMP_SFG[26]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5924), .Q(
FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5924), .Q(
FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT1_EWSW[27]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT2_EWSW[27]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5924), .Q(
FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(FPADDSUB_DMP_SFG[27]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5924), .Q(
FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5924), .Q(
FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT1_EWSW[28]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT2_EWSW[28]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5925), .Q(
FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(FPADDSUB_DMP_SFG[28]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5924), .Q(
FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5924), .Q(
FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT1_EWSW[29]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT2_EWSW[29]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5925), .Q(
FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(FPADDSUB_DMP_SFG[29]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5925), .Q(
FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5925), .Q(
FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT1_EWSW[30]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5908), .Q(
FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT2_EWSW[30]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5925), .Q(
FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(FPADDSUB_DMP_SFG[30]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5925), .Q(
FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5925), .Q(
FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5987), .Q(FPSENCOS_d_ff_Xn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_X[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5987), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(FPSENCOS_d_ff2_X[22]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5987), .Q(
FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5987), .Q(FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Y[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5987), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(FPSENCOS_d_ff2_Y[22]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5987), .Q(
FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(FPSENCOS_mux_sal[22]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5987), .Q(cordic_result[22])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5987), .Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Z[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5987), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(FPADDSUB_DmP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5933), .Q(
FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_DmP_EXP_EWSW[22]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5927), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5987), .Q(FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_X[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5986), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(FPSENCOS_d_ff2_X[19]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5986), .Q(
FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5986), .Q(FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Y[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5986), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(FPSENCOS_d_ff2_Y[19]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5986), .Q(
FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(FPSENCOS_mux_sal[19]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5986), .Q(cordic_result[19])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5986), .Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Z[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5986), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(FPADDSUB_DmP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5912), .Q(
FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_DmP_EXP_EWSW[19]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5926), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5986), .Q(FPSENCOS_d_ff_Xn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_X[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5986), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(FPSENCOS_d_ff2_X[21]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5985), .Q(
FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5985), .Q(FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Y[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5985), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(FPSENCOS_d_ff2_Y[21]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5985), .Q(
FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(FPSENCOS_mux_sal[21]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5985), .Q(cordic_result[21])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5985), .Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Z[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5985), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(FPADDSUB_DmP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5909), .Q(
FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_DmP_EXP_EWSW[21]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5926), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5985), .Q(FPSENCOS_d_ff_Xn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_X[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5985), .Q(
FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(FPSENCOS_d_ff2_X[2]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5985), .Q(
FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5984), .Q(FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Y[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5984), .Q(
FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(FPSENCOS_d_ff2_Y[2]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5984), .Q(
FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(FPSENCOS_mux_sal[2]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5984), .Q(cordic_result[2])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5984), .Q(FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Z[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5984), .Q(
FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(FPADDSUB_DmP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5909), .Q(
FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(FPADDSUB_DmP_EXP_EWSW[2]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5925), .Q(
FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5984), .Q(FPSENCOS_d_ff_Xn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_X[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5984), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(FPSENCOS_d_ff2_X[16]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5984), .Q(
FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5984), .Q(FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Y[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5983), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(FPSENCOS_d_ff2_Y[16]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5983), .Q(
FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(FPSENCOS_mux_sal[16]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5983), .Q(cordic_result[16])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5983), .Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Z[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5983), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(FPADDSUB_DmP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5912), .Q(
FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_DmP_EXP_EWSW[16]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5930), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5983), .Q(FPSENCOS_d_ff_Xn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_X[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5983), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(FPSENCOS_d_ff2_X[18]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5983), .Q(
FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5983), .Q(FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Y[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5983), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(FPSENCOS_d_ff2_Y[18]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5982), .Q(
FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(FPSENCOS_mux_sal[18]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5982), .Q(cordic_result[18])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5982), .Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Z[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5982), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(FPADDSUB_DmP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5933), .Q(
FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_DmP_EXP_EWSW[18]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5926), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5982), .Q(FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_X[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5982), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(FPSENCOS_d_ff2_X[20]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5982), .Q(
FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5982), .Q(FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Y[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5982), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(FPSENCOS_d_ff2_Y[20]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5982), .Q(
FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(FPSENCOS_mux_sal[20]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5981), .Q(cordic_result[20])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5981), .Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Z[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5981), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(FPADDSUB_DmP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5911), .Q(
FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_DmP_EXP_EWSW[20]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5926), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5981), .Q(FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_X[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5981), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(FPSENCOS_d_ff2_X[17]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5981), .Q(
FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5981), .Q(FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Y[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5981), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(FPSENCOS_d_ff2_Y[17]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5981), .Q(
FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(FPSENCOS_mux_sal[17]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5981), .Q(cordic_result[17])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5980), .Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Z[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5980), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(FPADDSUB_DmP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5911), .Q(
FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_DmP_EXP_EWSW[17]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5926), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5980), .Q(FPSENCOS_d_ff_Xn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_X[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5980), .Q(
FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(FPSENCOS_d_ff2_X[4]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5980), .Q(
FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5980), .Q(FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Y[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5980), .Q(
FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(FPSENCOS_d_ff2_Y[4]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5980), .Q(
FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(FPSENCOS_mux_sal[4]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5980), .Q(cordic_result[4])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5980), .Q(FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Z[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5979), .Q(
FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(FPADDSUB_DmP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n1051), .Q(
FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(FPADDSUB_DmP_EXP_EWSW[4]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5926), .Q(
FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5979), .Q(FPSENCOS_d_ff_Xn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_X[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5979), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(FPSENCOS_d_ff2_X[15]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5979), .Q(
FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5979), .Q(FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Y[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5979), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(FPSENCOS_d_ff2_Y[15]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5979), .Q(
FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(FPSENCOS_mux_sal[15]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5979), .Q(cordic_result[15])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5979), .Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Z[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5979), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(FPADDSUB_DmP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5912), .Q(
FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_DmP_EXP_EWSW[15]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5926), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5978), .Q(FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_X[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5978), .Q(
FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(FPSENCOS_d_ff2_X[5]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5978), .Q(
FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5978), .Q(FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Y[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5978), .Q(
FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(FPSENCOS_d_ff2_Y[5]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5978), .Q(
FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(FPSENCOS_mux_sal[5]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5978), .Q(cordic_result[5])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5978), .Q(FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Z[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5978), .Q(
FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(add_subt_data1[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5931), .Q(
FPADDSUB_intDX_EWSW[5]), .QN(n5722) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(FPADDSUB_DmP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5933), .Q(
FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(FPADDSUB_DmP_EXP_EWSW[5]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5926), .Q(
FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5978), .Q(FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_X[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5977), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(FPSENCOS_d_ff2_X[13]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5977), .Q(
FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5977), .Q(FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Y[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5977), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(FPSENCOS_d_ff2_Y[13]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5977), .Q(
FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(FPSENCOS_mux_sal[13]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5977), .Q(cordic_result[13])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5977), .Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Z[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5977), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(FPADDSUB_DmP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n4439), .Q(
FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_DmP_EXP_EWSW[13]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n4443), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5977), .Q(FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_X[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5977), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(FPSENCOS_d_ff2_X[14]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5976), .Q(
FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5976), .Q(FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Y[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5976), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(FPSENCOS_d_ff2_Y[14]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5976), .Q(
FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(FPSENCOS_mux_sal[14]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5976), .Q(cordic_result[14])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5976), .Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Z[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5976), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(FPADDSUB_DmP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n4441), .Q(
FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_DmP_EXP_EWSW[14]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5920), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5976), .Q(FPSENCOS_d_ff_Xn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_X[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5976), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(FPSENCOS_d_ff2_X[11]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5976), .Q(
FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5975), .Q(FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Y[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5975), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(FPSENCOS_d_ff2_Y[11]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5975), .Q(
FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(FPSENCOS_mux_sal[11]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5975), .Q(cordic_result[11])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5975), .Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Z[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5975), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(FPADDSUB_DmP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5917), .Q(
FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_DmP_EXP_EWSW[11]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5913), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5975), .Q(FPSENCOS_d_ff_Xn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_X[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5975), .Q(
FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(FPSENCOS_d_ff2_X[8]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5975), .Q(
FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5975), .Q(FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Y[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5974), .Q(
FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(FPSENCOS_d_ff2_Y[8]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5974), .Q(
FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(FPSENCOS_mux_sal[8]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5974), .Q(cordic_result[8])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5974), .Q(FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Z[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5974), .Q(
FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(FPADDSUB_DmP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5915), .Q(
FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(FPADDSUB_DmP_EXP_EWSW[8]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5915), .Q(
FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5974), .Q(FPSENCOS_d_ff_Xn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_X[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5974), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(FPSENCOS_d_ff2_X[10]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5974), .Q(
FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5974), .Q(FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Y[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5974), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(FPSENCOS_d_ff2_Y[10]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5973), .Q(
FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(FPSENCOS_mux_sal[10]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5973), .Q(cordic_result[10])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5973), .Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Z[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5973), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(FPADDSUB_DmP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5915), .Q(
FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_DmP_EXP_EWSW[10]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5915), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5973), .Q(FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_X[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5973), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(FPSENCOS_d_ff2_X[12]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5973), .Q(
FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5973), .Q(FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Y[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5973), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(FPSENCOS_d_ff2_Y[12]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5973), .Q(
FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(FPSENCOS_mux_sal[12]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5972), .Q(cordic_result[12])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5972), .Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Z[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5972), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(FPADDSUB_DmP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5933), .Q(
FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_DmP_EXP_EWSW[12]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500),
.RN(n5934), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5972), .Q(FPSENCOS_d_ff_Xn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_X[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5972), .Q(
FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(FPSENCOS_d_ff2_X[9]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5972), .Q(
FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5972), .Q(FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Y[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5972), .Q(
FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(FPSENCOS_d_ff2_Y[9]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5972), .Q(
FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(FPSENCOS_mux_sal[9]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5972), .Q(cordic_result[9])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5969), .Q(FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Z[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5968), .Q(
FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5971), .Q(FPSENCOS_d_ff_Xn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_X[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5970), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(FPSENCOS_d_ff2_X[31]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5967), .Q(
FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5966), .Q(FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(FPSENCOS_fmtted_Result_31_),
.CK(FPSENCOS_d_ff5_data_out_net8093734), .RN(n5967), .Q(
cordic_result[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Y[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5966), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(FPSENCOS_d_ff2_Y[31]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5967), .Q(
FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5966), .Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Z[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5971), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(add_subt_data1[31]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5916), .Q(
FPADDSUB_intDX_EWSW[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Z[31]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5970), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n5959), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n1052), .Q(
FPADDSUB_left_right_SHT2), .QN(n1042) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
FPADDSUB_LZD_raw_out_EWR[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5923), .Q(
FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
FPADDSUB_LZD_raw_out_EWR[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5922), .Q(
FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
FPADDSUB_LZD_raw_out_EWR[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5922), .Q(
FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
FPADDSUB_LZD_raw_out_EWR[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5922), .Q(
FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
FPADDSUB_LZD_raw_out_EWR[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8093518), .RN(n5923), .Q(
FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5969), .Q(FPSENCOS_d_ff_Xn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_X[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5968), .Q(
FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(FPSENCOS_d_ff2_X[0]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5971), .Q(
FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5970), .Q(FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Y[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5969), .Q(
FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Y[0]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5968), .Q(
FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(FPSENCOS_mux_sal[0]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5971), .Q(cordic_result[0])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5970), .Q(FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Z[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5999), .Q(
FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(FPADDSUB_DmP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n4439), .Q(
FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(FPADDSUB_DmP_EXP_EWSW[0]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5925), .Q(
FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n1052), .Q(
FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_EXP_EWSW[0]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5935), .Q(
FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT1_EWSW[0]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5918), .Q(
FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n6006), .Q(FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_X[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n4442), .Q(
FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(FPSENCOS_d_ff2_X[1]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5963), .Q(
FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5999), .Q(FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Y[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5966), .Q(
FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(FPSENCOS_d_ff2_Y[1]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n1058), .Q(
FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(FPSENCOS_mux_sal[1]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n6004), .Q(cordic_result[1])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5967), .Q(FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Z[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5967), .Q(
FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(FPADDSUB_DmP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n4443), .Q(
FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(FPADDSUB_DmP_EXP_EWSW[1]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5925), .Q(
FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5930), .Q(
FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_EXP_EWSW[1]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5912), .Q(
FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT1_EWSW[1]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5910), .Q(
FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5968), .Q(FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_X[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5971), .Q(
FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(FPSENCOS_d_ff2_X[3]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5970), .Q(
FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5964), .Q(FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Y[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5969), .Q(
FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(FPSENCOS_d_ff2_Y[3]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5968), .Q(
FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(FPSENCOS_mux_sal[3]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5971), .Q(cordic_result[3])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5970), .Q(FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Z[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5969), .Q(
FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(FPADDSUB_DmP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n4441), .Q(
FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(FPADDSUB_DmP_EXP_EWSW[3]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5926), .Q(
FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5910), .Q(
FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_EXP_EWSW[3]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n1052), .Q(
FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT1_EWSW[3]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n1051), .Q(
FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5968), .Q(FPSENCOS_d_ff_Xn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_X[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5968), .Q(
FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(FPSENCOS_d_ff2_X[6]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5971), .Q(
FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5970), .Q(FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Y[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5964), .Q(
FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(FPSENCOS_d_ff2_Y[6]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5969), .Q(
FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(FPSENCOS_mux_sal[6]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5968), .Q(cordic_result[6])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5971), .Q(FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Z[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5970), .Q(
FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(FPADDSUB_DmP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5920), .Q(
FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(FPADDSUB_DmP_EXP_EWSW[6]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5926), .Q(
FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_EXP_EWSW[6]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT1_EWSW[6]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Xn_net8093734), .RN(n5964), .Q(FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_X[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5969), .Q(
FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(FPSENCOS_d_ff2_X[7]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5964), .Q(
FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Yn_net8093734), .RN(n5969), .Q(FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Y[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5968), .Q(
FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(FPSENCOS_d_ff2_Y[7]), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5971), .Q(
FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(FPSENCOS_mux_sal[7]), .CK(
FPSENCOS_d_ff5_data_out_net8093734), .RN(n5970), .Q(cordic_result[7])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Zn_net8093734), .RN(n5964), .Q(FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Z[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5969), .Q(
FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(add_subt_data1[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5917), .Q(
FPADDSUB_intDX_EWSW[7]), .QN(n5721) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(FPADDSUB_DmP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5913), .Q(
FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(FPADDSUB_DmP_EXP_EWSW[7]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n4443), .Q(
FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_EXP_EWSW[7]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT1_EWSW[7]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(FPADDSUB_DmP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n4441), .Q(
FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(FPADDSUB_DmP_EXP_EWSW[9]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5920), .Q(
FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5919), .Q(
FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_EXP_EWSW[9]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT1_EWSW[9]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5919), .Q(
FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_EXP_EWSW[12]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT1_EWSW[12]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5919), .Q(
FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_EXP_EWSW[10]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT1_EWSW[10]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5919), .Q(
FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_EXP_EWSW[8]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT1_EWSW[8]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5919), .Q(
FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_EXP_EWSW[11]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT1_EWSW[11]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5919), .Q(
FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_EXP_EWSW[14]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT1_EWSW[14]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5919), .Q(
FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_EXP_EWSW[13]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT1_EWSW[13]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_EXP_EWSW[5]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT1_EWSW[5]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5919), .Q(
FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_EXP_EWSW[15]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT1_EWSW[15]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5912), .Q(
FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_EXP_EWSW[4]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5935), .Q(
FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT1_EWSW[4]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5935), .Q(
FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5919), .Q(
FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_EXP_EWSW[17]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT1_EWSW[17]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n997), .Q(
FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_EXP_EWSW[20]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT1_EWSW[20]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n997), .Q(
FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_EXP_EWSW[18]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT1_EWSW[18]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n996), .Q(
FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_EXP_EWSW[16]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT1_EWSW[16]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5934), .Q(
FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_EXP_EWSW[2]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5933), .Q(
FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT1_EWSW[2]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5931), .Q(
FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n996), .Q(
FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_EXP_EWSW[21]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n4440), .Q(
FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT1_EWSW[21]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5911), .Q(
FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n996), .Q(
FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_EXP_EWSW[19]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT1_EWSW[19]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n996), .Q(
FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_EXP_EWSW[22]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5918), .Q(
FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT1_EWSW[22]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8093500), .RN(n5914), .Q(
FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5929), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n5743) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5930), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n5742) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5934), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n5736) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n5752), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5910), .Q(
FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n5716) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n5750), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5934), .Q(
FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n5715) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n5749), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5933), .Q(
FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n5720) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n5748), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n1051), .Q(
FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n5719) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5934), .Q(
FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n5746) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5934), .Q(
FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n5774) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n1052), .Q(
FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n5775) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5910), .Q(
FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n5786) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n1051), .Q(
FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n5787) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n1052), .Q(
FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n5785) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5910), .Q(
FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n5795) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5935), .Q(
FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n5793) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5918), .Q(
FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n5794) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5930), .Q(
FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n5833) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(Data_2[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5943), .Q(
FPMULT_Op_MY[30]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(Data_2[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5954), .Q(
FPMULT_Op_MY[29]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(Data_2[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5840), .Q(
FPMULT_Op_MY[28]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(Data_2[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5953), .Q(
FPMULT_Op_MY[27]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(Data_2[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5961), .Q(
FPMULT_Op_MY[26]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(Data_2[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5961), .Q(
FPMULT_Op_MY[25]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(Data_2[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5961), .Q(
FPMULT_Op_MY[24]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(Data_2[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5953), .Q(
FPMULT_Op_MY[23]) );
DFFRX4TS R_237 ( .D(Data_2[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5838), .Q(
FPMULT_Op_MY[7]), .QN(n1176) );
DFFRX4TS R_1172 ( .D(Data_2[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5838), .Q(
FPMULT_Op_MY[2]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(Data_1[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5839), .Q(
FPMULT_Op_MX[24]) );
DFFRX4TS R_230 ( .D(Data_1[21]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5952), .Q(
FPMULT_Op_MX[21]) );
DFFRX4TS R_433 ( .D(Data_1[20]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5837), .Q(
FPMULT_Op_MX[20]), .QN(n5890) );
DFFRX4TS R_317 ( .D(Data_1[19]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5836), .Q(
FPMULT_Op_MX[19]), .QN(n5891) );
DFFRX4TS R_267 ( .D(Data_1[16]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5836), .Q(
FPMULT_Op_MX[16]) );
DFFRX4TS R_296 ( .D(Data_1[15]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5836), .Q(
FPMULT_Op_MX[15]), .QN(n5901) );
DFFRX4TS R_224 ( .D(Data_1[12]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5837), .Q(
FPMULT_Op_MX[12]) );
DFFRX4TS R_243 ( .D(Data_1[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1054), .Q(
FPMULT_Op_MX[6]) );
DFFRX4TS R_201 ( .D(Data_1[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5951), .Q(
FPMULT_Op_MX[0]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n106), .CK(
n6045), .RN(n5946), .Q(FPMULT_zero_flag) );
DFFRXLTS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n6044), .CK(n6045),
.RN(n5949), .Q(underflow_flag_mult), .QN(n5829) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1189), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5950), .Q(
FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(
FPMULT_Sgf_operation_Result[19]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5966), .Q(
FPMULT_P_Sgf[19]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(
FPMULT_Sgf_operation_Result[5]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5962), .Q(
FPMULT_P_Sgf[5]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(
FPMULT_Sgf_operation_Result[4]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5962), .Q(
FPMULT_P_Sgf[4]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(
FPMULT_Sgf_operation_Result[3]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5962), .Q(
FPMULT_P_Sgf[3]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(
FPMULT_Sgf_operation_Result[1]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5962), .Q(
FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(
FPMULT_Sgf_operation_Result[0]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5962), .Q(
FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(
FPMULT_Exp_module_Data_S[8]), .CK(
FPMULT_Exp_module_exp_result_m_net8093680), .RN(n5951), .Q(
FPMULT_exp_oper_result[8]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(
FPMULT_Exp_module_Data_S[7]), .CK(
FPMULT_Exp_module_exp_result_m_net8093680), .RN(n5950), .Q(
FPMULT_exp_oper_result[7]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(
FPMULT_Exp_module_Data_S[6]), .CK(
FPMULT_Exp_module_exp_result_m_net8093680), .RN(n5948), .Q(
FPMULT_exp_oper_result[6]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(
FPMULT_Exp_module_Data_S[5]), .CK(
FPMULT_Exp_module_exp_result_m_net8093680), .RN(n5947), .Q(
FPMULT_exp_oper_result[5]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(
FPMULT_Exp_module_Data_S[4]), .CK(
FPMULT_Exp_module_exp_result_m_net8093680), .RN(n5951), .Q(
FPMULT_exp_oper_result[4]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(
FPMULT_Exp_module_Data_S[3]), .CK(
FPMULT_Exp_module_exp_result_m_net8093680), .RN(n5946), .Q(
FPMULT_exp_oper_result[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(
FPMULT_Exp_module_Data_S[2]), .CK(
FPMULT_Exp_module_exp_result_m_net8093680), .RN(n5949), .Q(
FPMULT_exp_oper_result[2]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(
FPMULT_Exp_module_Data_S[1]), .CK(
FPMULT_Exp_module_exp_result_m_net8093680), .RN(n5950), .Q(
FPMULT_exp_oper_result[1]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Data_S[0]), .CK(
FPMULT_Exp_module_exp_result_m_net8093680), .RN(n5946), .Q(
FPMULT_exp_oper_result[0]) );
DFFRXLTS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Overflow_A), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5947), .Q(
FPMULT_Exp_module_Overflow_flag_A) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n6068), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5951), .Q(
FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n6067), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5951), .Q(
FPMULT_Sgf_normalized_result[22]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n6066), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5948), .Q(
FPMULT_Sgf_normalized_result[21]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n6065), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5947), .Q(
FPMULT_Sgf_normalized_result[20]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n6064), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5949), .Q(
FPMULT_Sgf_normalized_result[19]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n6063), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5951), .Q(
FPMULT_Sgf_normalized_result[18]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n6062), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5948), .Q(
FPMULT_Sgf_normalized_result[17]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n6061), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5944), .Q(
FPMULT_Sgf_normalized_result[16]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n6059), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5942), .Q(
FPMULT_Sgf_normalized_result[14]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n6057), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5943), .Q(
FPMULT_Sgf_normalized_result[12]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n6056), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5944), .Q(
FPMULT_Sgf_normalized_result[11]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n6055), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5942), .Q(
FPMULT_Sgf_normalized_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n1002), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5944), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5945), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5941), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5945), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5941), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5944), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5943), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5945), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5942), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5941), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5942), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5945), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5942), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5943), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5941), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5945), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5941), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5941), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5944), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5945), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5943), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5944), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5943), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5942), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5941), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5944), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5945), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5942), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5942), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5943), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
FPMULT_final_result_ieee_Module_Sign_S_mux), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8093446), .RN(
n5945), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n6040), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5922), .Q(
underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n6041), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5922), .Q(
overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n6039), .CK(
FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n996), .Q(
FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_EXP),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5921), .Q(
FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n819), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5921), .Q(
FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_SHT2),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5921), .Q(
FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_SIGN_FLAG_SFG),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5921), .Q(
FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n816), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5921), .Q(
FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n30), .CK(
FPADDSUB_EXP_STAGE_DMP_net8093500), .RN(n5921), .Q(
FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_EXP), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8093500), .RN(n5921), .Q(
FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n813), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5935), .Q(
FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n6042), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5910), .Q(
FPADDSUB_ADD_OVRFLW_NRM), .QN(n5800) );
SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_FPMULT_Exp_module_Underflow_m_Q_reg (
.CLK(clk), .EN(n107), .ENCLK(n6045), .TE(1'b0) );
CMPR32X2TS DP_OP_26J311_126_1325_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n1027), .C(DP_OP_26J311_126_1325_n18), .CO(DP_OP_26J311_126_1325_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_234J311_129_4955_U8 ( .A(DP_OP_234J311_129_4955_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J311_129_4955_n8), .CO(
DP_OP_234J311_129_4955_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J311_129_4955_U6 ( .A(DP_OP_234J311_129_4955_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J311_129_4955_n6), .CO(
DP_OP_234J311_129_4955_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J311_129_4955_U4 ( .A(DP_OP_234J311_129_4955_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J311_129_4955_n4), .CO(
DP_OP_234J311_129_4955_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS intadd_1045_U4 ( .A(n998), .B(FPSENCOS_d_ff2_X[24]), .C(
intadd_1045_CI), .CO(intadd_1045_n3), .S(FPSENCOS_sh_exp_x[1]) );
CMPR32X2TS intadd_1045_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n5709), .C(
intadd_1045_n3), .CO(intadd_1045_n2), .S(FPSENCOS_sh_exp_x[2]) );
CMPR32X2TS intadd_1045_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n5710), .C(
intadd_1045_n2), .CO(intadd_1045_n1), .S(FPSENCOS_sh_exp_x[3]) );
CMPR32X2TS intadd_1047_U4 ( .A(FPADDSUB_DmP_EXP_EWSW[24]), .B(n5798), .C(
intadd_1047_CI), .CO(intadd_1047_n3), .S(intadd_1047_SUM_0_) );
CMPR32X2TS intadd_1047_U3 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n5828), .C(
intadd_1047_n3), .CO(intadd_1047_n2), .S(intadd_1047_SUM_1_) );
CMPR32X2TS intadd_1047_U2 ( .A(FPADDSUB_DmP_EXP_EWSW[26]), .B(n5827), .C(
intadd_1047_n2), .CO(intadd_1047_n1), .S(intadd_1047_SUM_2_) );
DFFRX4TS R_290 ( .D(Data_1[14]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5837), .Q(
DP_OP_496J311_122_3540_n1495), .QN(n953) );
DFFRX4TS R_271 ( .D(Data_1[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1056), .Q(
DP_OP_498J311_124_1725_n802) );
DFFRX4TS R_390 ( .D(Data_1[13]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5837), .Q(
DP_OP_497J311_123_1725_n792), .QN(n919) );
DFFRX4TS R_322 ( .D(Data_2[21]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5542), .Q(
DP_OP_496J311_122_3540_n1465), .QN(n1172) );
DFFRX4TS R_342 ( .D(Data_1[17]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5837), .Q(
DP_OP_496J311_122_3540_n1498) );
DFFRX4TS R_405 ( .D(Data_2[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5838), .Q(
DP_OP_498J311_124_1725_n791) );
DFFRX4TS R_413 ( .D(Data_1[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1055), .Q(
DP_OP_496J311_122_3540_n1509) );
DFFRX4TS R_447 ( .D(Data_1[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5953), .Q(
DP_OP_496J311_122_3540_n1514) );
DFFRX4TS R_450 ( .D(Data_1[22]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5952), .Q(
DP_OP_497J311_123_1725_n687), .QN(n1166) );
DFFRX4TS R_453 ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1054), .Q(
DP_OP_496J311_122_3540_n1513) );
DFFRX4TS R_798 ( .D(Data_2[22]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1001), .Q(n5902)
);
DFFRX2TS R_864 ( .D(n6027), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(
n1051), .QN(n5764) );
DFFRX2TS R_1050 ( .D(n4373), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(
n5932), .QN(n5765) );
DFFSX2TS R_1084 ( .D(n5884), .CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446),
.SN(n5916), .Q(n6038) );
DFFRX4TS R_1091 ( .D(Data_1[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1055), .Q(
FPMULT_Op_MX[4]) );
DFFRX4TS R_1092 ( .D(Data_1[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1056), .Q(
FPMULT_Op_MX[5]) );
DFFRX4TS R_1095 ( .D(Data_2[19]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1056), .Q(
DP_OP_496J311_122_3540_n778), .QN(n952) );
DFFRX2TS R_1102 ( .D(Data_1[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1055), .Q(
DP_OP_496J311_122_3540_n1515) );
DFFRX2TS R_1100 ( .D(Data_1[18]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5837), .Q(
FPMULT_Op_MX[18]) );
DFFSX2TS R_1112 ( .D(n6034), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5931), .Q(n5872), .QN(n1060) );
DFFSX2TS R_1116 ( .D(n6029), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n997), .Q(n5868) );
DFFSX2TS R_1117 ( .D(n6031), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5932), .Q(n5867) );
DFFSX2TS R_1119 ( .D(n6024), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5912), .Q(n5865) );
DFFSX2TS R_1121 ( .D(n6022), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5919), .Q(n5863) );
DFFSX2TS R_1122 ( .D(n6021), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5930), .Q(n5862) );
DFFSX2TS R_1123 ( .D(n6020), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5930), .Q(n5861) );
DFFSX2TS R_1125 ( .D(n6018), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5915), .Q(n5859) );
DFFSX2TS R_1126 ( .D(n6017), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5918), .Q(n5858) );
DFFSX2TS R_1128 ( .D(n5756), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5932), .Q(n5856) );
DFFSX2TS R_1129 ( .D(n5754), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5932), .Q(n5855) );
DFFSX2TS R_1130 ( .D(n5758), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5932), .Q(n5854) );
DFFSX2TS R_1131 ( .D(n5757), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5934), .Q(n5853) );
DFFSX2TS R_1132 ( .D(n5762), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5914), .Q(n5852) );
DFFSX2TS R_1134 ( .D(n5763), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5912), .Q(n5850) );
DFFSX2TS R_1135 ( .D(n5761), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n997), .Q(n5849) );
DFFSX2TS R_1136 ( .D(n5760), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5930), .Q(n5848) );
DFFSX2TS R_1137 ( .D(n5759), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n1051), .Q(n5847) );
DFFSX2TS R_1138 ( .D(n5755), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n997), .Q(n5846) );
DFFSX2TS R_1139 ( .D(n5747), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5934), .Q(n5845) );
DFFSX2TS R_1143 ( .D(n6033), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n997), .Q(n5844) );
DFFSX2TS R_1145 ( .D(n6014), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5933), .Q(n5842) );
DFFRX4TS R_1171 ( .D(Data_2[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5838), .Q(
DP_OP_498J311_124_1725_n788) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(
FPSENCOS_reg_shift_y_net8093734), .RN(n5962), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_X[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff2_X[28]), .QN(n5832) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(FPADDSUB_Data_array_SWR[1]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5934), .Q(
FPADDSUB_Data_array_SWR[3]), .QN(n5797) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n6000), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n5784) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(
FPMULT_FS_Module_state_next[3]), .CK(FPMULT_FS_Module_net8093716),
.RN(n5968), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n5771) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n829), .CK(FPMULT_FS_Module_net8093716),
.RN(n5949), .Q(FPMULT_FSM_selector_B[1]), .QN(n5733) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n834), .CK(FPMULT_FS_Module_net8093716),
.RN(n5946), .Q(FPMULT_FSM_selector_C), .QN(n5731) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n843), .CK(clk), .RN(n6000), .Q(
FPSENCOS_cont_var_out[0]), .QN(n5730) );
DFFRXLTS R_1090 ( .D(n5879), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5840), .QN(n5727) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n5712), .CK(
FPSENCOS_ITER_CONT_net8093770), .RN(n6000), .Q(
FPSENCOS_cont_iter_out[0]), .QN(n5712) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(
FPMULT_FS_Module_state_next[1]), .CK(FPMULT_FS_Module_net8093716),
.RN(n5970), .Q(FPMULT_FS_Module_state_reg[1]), .QN(n5711) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(FPSENCOS_ITER_CONT_N5), .CK(
FPSENCOS_ITER_CONT_net8093770), .RN(n6000), .Q(
FPSENCOS_cont_iter_out[3]), .QN(n5710) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(FPSENCOS_ITER_CONT_N4), .CK(
FPSENCOS_ITER_CONT_net8093770), .RN(n6000), .Q(
FPSENCOS_cont_iter_out[2]), .QN(n5709) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n6001), .Q(NaN_flag)
);
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
FPADDSUB_inst_ShiftRegister_net8093608), .RN(n5903), .Q(busy), .QN(
n5835) );
CMPR32X2TS DP_OP_26J311_126_1325_U3 ( .A(n1027), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J311_126_1325_n3), .CO(
DP_OP_26J311_126_1325_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J311_126_1325_U4 ( .A(n1027), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J311_126_1325_n4), .CO(
DP_OP_26J311_126_1325_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J311_126_1325_U5 ( .A(DP_OP_26J311_126_1325_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J311_126_1325_n5), .CO(
DP_OP_26J311_126_1325_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J311_126_1325_U6 ( .A(DP_OP_26J311_126_1325_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J311_126_1325_n6), .CO(
DP_OP_26J311_126_1325_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J311_126_1325_U7 ( .A(DP_OP_26J311_126_1325_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J311_126_1325_n7), .CO(
DP_OP_26J311_126_1325_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J311_126_1325_U8 ( .A(DP_OP_26J311_126_1325_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J311_126_1325_n8), .CO(
DP_OP_26J311_126_1325_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
DFFSX2TS add_x_246_R_1103 ( .D(n5708), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .SN(n5941), .Q(
FPMULT_Adder_M_result_A_adder[4]) );
DFFSX2TS add_x_69_R_1155 ( .D(FPMULT_Sgf_operation_EVEN1_S_B_14_), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(n5694)
);
DFFSX2TS add_x_69_R_1150 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5698), .Q(n5693)
);
DFFSX2TS add_x_69_R_1149 ( .D(add_x_69_n243), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5698), .Q(n5692)
);
DFFSX2TS add_x_69_R_899_RW_1 ( .D(add_x_69_n242), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5682)
);
DFFSX2TS add_x_69_R_1053 ( .D(add_x_69_n231), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5698), .Q(n5685)
);
DFFSX2TS add_x_69_R_1051 ( .D(add_x_69_n230), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5698), .Q(n5684)
);
DFFSX2TS add_x_69_R_876 ( .D(add_x_69_n236), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5698), .Q(n5680)
);
DFFSX2TS add_x_69_R_869 ( .D(add_x_69_n233), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(n5679)
);
DFFSX2TS add_x_69_R_825 ( .D(add_x_69_n239), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(n5677)
);
DFFSX2TS add_x_69_R_823 ( .D(add_x_69_n257), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(n5675)
);
DFFSX2TS add_x_69_R_818 ( .D(add_x_69_n250), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(n5673)
);
DFFSX2TS add_x_69_R_816 ( .D(add_x_69_n268), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(n5671)
);
DFFSX2TS add_x_69_R_791 ( .D(add_x_69_n24), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(n5669)
);
DFFSX2TS add_x_69_R_755 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(n5667)
);
DFFSX2TS add_x_69_R_723_RW_0 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[5]),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(
n5664) );
DFFSX2TS add_x_69_R_627 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5699), .Q(n5661)
);
DFFSX2TS add_x_69_R_164_RW_0 ( .D(n924), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5636)
);
DFFSX2TS add_x_69_R_163_RW_0 ( .D(add_x_69_n94), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5635)
);
DFFSX2TS add_x_69_R_155_RW_0 ( .D(n4025), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5634)
);
DFFSX2TS add_x_69_R_148_RW_0 ( .D(add_x_69_n77), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5633)
);
DFFSX2TS add_x_69_R_146_RW_0 ( .D(n3998), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5632)
);
DFFSX2TS add_x_69_R_144_RW_0 ( .D(add_x_69_n47), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5631)
);
DFFSX2TS add_x_69_R_134_RW_0 ( .D(add_x_69_n39), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5629)
);
DFFSX2TS add_x_69_R_502 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5646)
);
DFFSX2TS add_x_69_R_480 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5696), .Q(n5644)
);
DFFSX2TS add_x_69_R_21 ( .D(n4002), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5696), .Q(n5628)
);
DFFSX2TS add_x_69_R_19 ( .D(add_x_69_n50), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5696), .Q(n5627)
);
DFFSX2TS add_x_69_R_17 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[20]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5696), .Q(n5626)
);
DFFSX2TS add_x_69_R_15 ( .D(n3995), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5696), .Q(n5625)
);
DFFSX2TS add_x_69_R_13 ( .D(add_x_69_n95), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5696), .Q(n5624)
);
DFFSX2TS add_x_69_R_11 ( .D(add_x_69_n105), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5696), .Q(n5623)
);
DFFSX2TS DP_OP_496J311_122_3540_R_1176 ( .D(n5613), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5838), .Q(
DP_OP_496J311_122_3540_n1097) );
DFFRX2TS DP_OP_496J311_122_3540_R_1175 ( .D(n5612), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5540), .Q(n5596),
.QN(n951) );
DFFRX2TS DP_OP_496J311_122_3540_R_1170 ( .D(n5610), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5540), .Q(
DP_OP_496J311_122_3540_n1105) );
DFFSX4TS DP_OP_496J311_122_3540_R_1106 ( .D(n5606), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5954), .Q(
DP_OP_496J311_122_3540_n1117), .QN(n5617) );
DFFRX2TS DP_OP_496J311_122_3540_R_847 ( .D(Data_2[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5954), .Q(
DP_OP_496J311_122_3540_n1467) );
DFFRX2TS DP_OP_496J311_122_3540_R_846 ( .D(Data_2[12]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5582), .Q(
DP_OP_496J311_122_3540_n1456) );
DFFSX2TS DP_OP_496J311_122_3540_R_1169 ( .D(n5602), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5584), .Q(
DP_OP_496J311_122_3540_n1107), .QN(n5615) );
DFFSX4TS DP_OP_496J311_122_3540_R_400 ( .D(n5601), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1002), .Q(
DP_OP_496J311_122_3540_n1118) );
DFFSX4TS DP_OP_496J311_122_3540_R_391 ( .D(n5600), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5836), .Q(
DP_OP_496J311_122_3540_n1202), .QN(n5619) );
DFFSX4TS DP_OP_496J311_122_3540_R_272 ( .D(n5597), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1055), .Q(n5594),
.QN(n915) );
DFFSX4TS DP_OP_496J311_122_3540_R_219 ( .D(n5595), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5540), .Q(
DP_OP_496J311_122_3540_n1114) );
DFFSX4TS DP_OP_497J311_123_1725_R_449 ( .D(n5580), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5584), .Q(
DP_OP_497J311_123_1725_n628), .QN(n954) );
DFFRXLTS DP_OP_497J311_123_1725_R_440 ( .D(n5579), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5584), .Q(
DP_OP_497J311_123_1725_n613) );
DFFSX4TS DP_OP_497J311_123_1725_R_441 ( .D(n5553), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5584), .Q(n5554)
);
DFFSX4TS DP_OP_497J311_123_1725_R_434 ( .D(n5577), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5585), .Q(
DP_OP_497J311_123_1725_n720) );
DFFSX4TS DP_OP_497J311_123_1725_R_381 ( .D(n5564), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5585), .Q(n5567),
.QN(n1178) );
DFFSX4TS DP_OP_497J311_123_1725_R_354 ( .D(n5562), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5585), .Q(
DP_OP_497J311_123_1725_n324), .QN(n5568) );
DFFSX4TS DP_OP_497J311_123_1725_R_409 ( .D(n5560), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5582), .Q(
DP_OP_497J311_123_1725_n714) );
DFFSX4TS DP_OP_497J311_123_1725_R_318 ( .D(n5559), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5585), .Q(
DP_OP_497J311_123_1725_n721) );
DFFSX4TS DP_OP_497J311_123_1725_R_305 ( .D(n5557), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5584), .Q(
DP_OP_497J311_123_1725_n629) );
DFFSX4TS DP_OP_497J311_123_1725_R_303 ( .D(n5555), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5585), .Q(
DP_OP_497J311_123_1725_n635), .QN(n5565) );
DFFRXLTS DP_OP_497J311_123_1725_R_279 ( .D(n5551), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .Q(
DP_OP_497J311_123_1725_n674) );
DFFRX4TS DP_OP_497J311_123_1725_R_281 ( .D(Data_1[18]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .Q(
DP_OP_497J311_123_1725_n709), .QN(n1165) );
DFFRX4TS DP_OP_497J311_123_1725_R_346 ( .D(Data_2[18]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .QN(n920)
);
DFFSX4TS DP_OP_497J311_123_1725_R_439 ( .D(n5550), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5584), .Q(
DP_OP_497J311_123_1725_n367), .QN(n5578) );
DFFRXLTS DP_OP_497J311_123_1725_R_264 ( .D(Data_2[17]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5584), .Q(
DP_OP_497J311_123_1725_n357) );
DFFSX4TS DP_OP_497J311_123_1725_R_235 ( .D(n5548), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5583), .Q(
DP_OP_497J311_123_1725_n715) );
DFFRX4TS DP_OP_497J311_123_1725_R_232 ( .D(Data_1[21]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5839), .Q(
DP_OP_497J311_123_1725_n693) );
DFFSX4TS DP_OP_497J311_123_1725_R_231 ( .D(n5547), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5839), .Q(
DP_OP_497J311_123_1725_n719) );
DFFSX4TS DP_OP_497J311_123_1725_R_261 ( .D(n5546), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5585), .Q(
DP_OP_497J311_123_1725_n638), .QN(n5570) );
DFFRX4TS DP_OP_497J311_123_1725_R_352 ( .D(Data_2[19]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5583), .Q(
DP_OP_497J311_123_1725_n685) );
DFFRX4TS DP_OP_497J311_123_1725_R_353 ( .D(Data_2[13]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5583), .Q(
DP_OP_497J311_123_1725_n779) );
DFFSX4TS DP_OP_498J311_124_1725_R_860 ( .D(n5537), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1056), .Q(
DP_OP_498J311_124_1725_n729) );
DFFSX4TS DP_OP_498J311_124_1725_R_858 ( .D(n5536), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5540), .Q(
DP_OP_498J311_124_1725_n732) );
DFFSX4TS DP_OP_498J311_124_1725_R_460 ( .D(n5534), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5542), .Q(
DP_OP_498J311_124_1725_n728) );
DFFRX4TS DP_OP_498J311_124_1725_R_461 ( .D(Data_1[10]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5542), .Q(
DP_OP_498J311_124_1725_n798) );
DFFRX4TS DP_OP_498J311_124_1725_R_455 ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1056), .Q(
DP_OP_498J311_124_1725_n795), .QN(n1175) );
DFFRX4TS DP_OP_498J311_124_1725_R_456 ( .D(Data_1[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1054), .Q(
DP_OP_498J311_124_1725_n801) );
DFFSX4TS DP_OP_498J311_124_1725_R_445 ( .D(n5531), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5541), .Q(
DP_OP_498J311_124_1725_n730) );
DFFRX4TS DP_OP_498J311_124_1725_R_446 ( .D(Data_1[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5541), .QN(n5543) );
DFFSX4TS DP_OP_498J311_124_1725_R_422 ( .D(n5529), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5542), .Q(
DP_OP_498J311_124_1725_n638) );
DFFRX4TS DP_OP_498J311_124_1725_R_423 ( .D(Data_2[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5945), .Q(
DP_OP_498J311_124_1725_n789) );
DFFSX4TS DP_OP_498J311_124_1725_R_420 ( .D(n5527), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1056), .Q(
DP_OP_498J311_124_1725_n642) );
DFFSX4TS DP_OP_498J311_124_1725_R_327 ( .D(n5526), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5541), .Q(
DP_OP_498J311_124_1725_n723) );
DFFSX4TS DP_OP_498J311_124_1725_R_313 ( .D(n5525), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5836), .Q(
DP_OP_498J311_124_1725_n727) );
DFFSX4TS DP_OP_498J311_124_1725_R_855 ( .D(n5523), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5541), .Q(
DP_OP_498J311_124_1725_n721) );
DFFSX4TS DP_OP_498J311_124_1725_R_294 ( .D(n5522), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5542), .Q(
DP_OP_498J311_124_1725_n635) );
DFFSX4TS DP_OP_498J311_124_1725_R_311 ( .D(n5520), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5542), .Q(
DP_OP_498J311_124_1725_n726) );
DFFSX4TS DP_OP_498J311_124_1725_R_257 ( .D(n5519), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1054), .Q(
DP_OP_498J311_124_1725_n640) );
DFFSX4TS DP_OP_498J311_124_1725_R_442 ( .D(n5518), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5541), .Q(
DP_OP_498J311_124_1725_n722) );
DFFSX4TS DP_OP_498J311_124_1725_R_248 ( .D(n5517), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1055), .Q(
DP_OP_498J311_124_1725_n641) );
DFFRX4TS DP_OP_498J311_124_1725_R_249 ( .D(Data_1[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1054), .Q(
DP_OP_498J311_124_1725_n804) );
DFFSX4TS DP_OP_498J311_124_1725_R_245 ( .D(n5516), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1054), .Q(
DP_OP_498J311_124_1725_n394) );
DFFSX4TS DP_OP_498J311_124_1725_R_457 ( .D(n5515), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5542), .Q(
DP_OP_498J311_124_1725_n724) );
DFFSX4TS DP_OP_498J311_124_1725_R_238 ( .D(n5514), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5542), .Q(
DP_OP_498J311_124_1725_n725) );
DFFRX4TS DP_OP_498J311_124_1725_R_239 ( .D(Data_2[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5944), .Q(
DP_OP_498J311_124_1725_n783) );
DFFSX4TS DP_OP_498J311_124_1725_R_287 ( .D(n5513), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5542), .Q(
DP_OP_498J311_124_1725_n634) );
DFFSX4TS DP_OP_498J311_124_1725_R_288 ( .D(n5512), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5947), .Q(
DP_OP_498J311_124_1725_n645) );
DFFRX1TS DP_OP_499J311_125_1651_R_1069 ( .D(DP_OP_499J311_125_1651_n86),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5965), .QN(
n5510) );
DFFRXLTS DP_OP_499J311_125_1651_R_863_RW_0 ( .D(DP_OP_499J311_125_1651_n61),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5999), .QN(
n5506) );
DFFSX2TS DP_OP_499J311_125_1651_R_1152 ( .D(DP_OP_499J311_125_1651_n61),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(
n5500) );
DFFSX2TS DP_OP_499J311_125_1651_R_1151 ( .D(DP_OP_499J311_125_1651_n38),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5504), .Q(
n5499), .QN(n5507) );
DFFSX2TS DP_OP_499J311_125_1651_R_1142 ( .D(DP_OP_499J311_125_1651_n53),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(
n5498), .QN(n5508) );
DFFSX2TS DP_OP_499J311_125_1651_R_889_RW_0 ( .D(DP_OP_499J311_125_1651_n64),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(
n5478), .QN(n5509) );
DFFSX2TS DP_OP_499J311_125_1651_R_1059 ( .D(DP_OP_499J311_125_1651_n199),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(
n5495) );
DFFSX2TS DP_OP_499J311_125_1651_R_1058 ( .D(DP_OP_499J311_125_1651_n202),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(
n5494) );
DFFSX2TS DP_OP_499J311_125_1651_R_1027 ( .D(DP_OP_499J311_125_1651_n194),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(
n5489) );
DFFSX2TS DP_OP_499J311_125_1651_R_731_RW_0 ( .D(DP_OP_499J311_125_1651_n73),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(
n5473) );
DFFSX2TS DP_OP_499J311_125_1651_R_962 ( .D(DP_OP_499J311_125_1651_n81), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(n5484)
);
DFFSX2TS DP_OP_499J311_125_1651_R_815 ( .D(DP_OP_499J311_125_1651_n79), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5504), .Q(n5477)
);
DFFSX2TS DP_OP_499J311_125_1651_R_736 ( .D(DP_OP_499J311_125_1651_n12), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(n5474)
);
DFFSX4TS DP_OP_496J311_122_3540_R_845 ( .D(n5603), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5837), .Q(
DP_OP_496J311_122_3540_n1120) );
DFFSX4TS DP_OP_496J311_122_3540_R_1105 ( .D(n5605), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5836), .Q(
DP_OP_496J311_122_3540_n1203) );
DFFSX4TS DP_OP_496J311_122_3540_R_1168 ( .D(n5604), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5954), .QN(n5469) );
DFFRX4TS DP_OP_497J311_123_1725_R_268_IP ( .D(Data_1[16]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5585), .Q(n5566),
.QN(DP_OP_497J311_123_1725_n634) );
DFFSXLTS DP_OP_497J311_123_1725_R_355 ( .D(n5571), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5582), .QN(n5589) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n810), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5923), .Q(
FPADDSUB_ADD_OVRFLW_NRM2) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
FPADDSUB_Raw_mant_SGF[13]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5929), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
FPADDSUB_Raw_mant_SGF[11]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5929), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
FPADDSUB_Raw_mant_SGF[18]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]) );
DFFRXLTS R_1159 ( .D(Data_2[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5839), .QN(n5896) );
DFFRXLTS DP_OP_497J311_123_1725_R_344 ( .D(Data_1[17]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .Q(n5563),
.QN(n5591) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(
FPMULT_Adder_M_result_A_adder[7]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5950), .Q(
FPMULT_Add_result[7]) );
DFFRXLTS add_x_69_R_824 ( .D(add_x_69_n22), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(n5676)
);
DFFSXLTS add_x_69_R_892_RW_0 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[2]),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1058), .Q(
n5681) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
FPADDSUB_Raw_mant_SGF[22]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(
FPADDSUB_Raw_mant_SGF[25]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n5796) );
DFFRX1TS R_165 ( .D(n6051), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1001), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFSXLTS R_989 ( .D(n6032), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n997), .Q(n5888) );
DFFRX1TS add_x_246_R_850 ( .D(n5707), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5943), .Q(
FPMULT_Adder_M_result_A_adder[7]) );
DFFSX1TS add_x_69_R_1146 ( .D(add_x_69_n85), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5696), .Q(n5689)
);
DFFRXLTS add_x_69_R_852 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5965), .Q(n5678)
);
DFFSX1TS add_x_69_R_142_RW_0 ( .D(add_x_69_n57), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5695), .Q(n5630)
);
DFFRXLTS add_x_69_R_181 ( .D(add_x_69_n47), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5697), .Q(n5637)
);
DFFRX2TS DP_OP_497J311_123_1725_R_319 ( .D(Data_1[19]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .Q(
DP_OP_497J311_123_1725_n705) );
DFFSX1TS DP_OP_499J311_125_1651_R_1154 ( .D(DP_OP_499J311_125_1651_n54),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5962), .Q(
n5502), .QN(n5503) );
DFFSX1TS DP_OP_499J311_125_1651_R_1026 ( .D(DP_OP_499J311_125_1651_n191),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5505), .Q(
n5488) );
DFFRX1TS DP_OP_498J311_124_1725_R_421 ( .D(n5528), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5961), .Q(
DP_OP_498J311_124_1725_n618) );
DFFRX2TS R_253 ( .D(Data_2[10]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5840), .Q(
FPMULT_Op_MY[10]), .QN(n1191) );
DFFRX1TS add_x_246_R_171 ( .D(n6049), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1001), .Q(
add_x_246_A_0_), .QN(n1189) );
DFFRX2TS R_326 ( .D(Data_2[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5840), .Q(
DP_OP_496J311_122_3540_n1476), .QN(n1174) );
DFFRX1TS DP_OP_497J311_123_1725_R_388 ( .D(n5575), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5585), .Q(
DP_OP_497J311_123_1725_n388), .QN(n1159) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n842), .CK(clk), .RN(n6000), .Q(
FPSENCOS_cont_var_out[1]) );
DFFRX4TS FPMULT_Sel_A_Q_reg_0_ ( .D(1'b1), .CK(n6045), .RN(n5946), .Q(
FPMULT_FSM_selector_A) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(FPADDSUB_Raw_mant_SGF[5]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5927), .Q(
FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n5790) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[1]), .CK(
FPADDSUB_inst_ShiftRegister_net8093608), .RN(n5903), .Q(
FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
FPADDSUB_Raw_mant_SGF[10]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5927), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5916), .Q(
FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n6000), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5932), .Q(
FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n968) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(add_subt_data1[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5905), .Q(
FPADDSUB_intDX_EWSW[29]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n844), .CK(clk), .RN(n5903), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(FPADDSUB_Raw_mant_SGF[2]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5927), .Q(
FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(add_subt_data1[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5905), .Q(
FPADDSUB_intDX_EWSW[30]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(add_subt_data2[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5932), .Q(
FPADDSUB_intDY_EWSW[5]), .QN(n5792) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(add_subt_data2[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5913), .Q(
FPADDSUB_intDY_EWSW[7]), .QN(n5791) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(FPADDSUB_Raw_mant_SGF[7]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5927), .Q(
FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT2_EWSW[5]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5918), .Q(
FPADDSUB_DMP_SFG[5]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT2_EWSW[10]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_SFG[10]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT2_EWSW[7]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_SFG[7]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT2_EWSW[6]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5936), .Q(
FPADDSUB_DMP_SFG[6]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT2_EWSW[8]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_SFG[8]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(add_subt_data1[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4443), .Q(
FPADDSUB_intDX_EWSW[3]), .QN(n942) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(add_subt_data1[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5931), .Q(
FPADDSUB_intDX_EWSW[15]), .QN(n972) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(FPADDSUB_Raw_mant_SGF[8]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5929), .Q(
FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT2_EWSW[19]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SFG[19]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT2_EWSW[21]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5916), .Q(
FPADDSUB_DMP_SFG[21]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT2_EWSW[2]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n1052), .Q(
FPADDSUB_DMP_SFG[2]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT2_EWSW[17]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SFG[17]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT2_EWSW[15]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SFG[15]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT2_EWSW[13]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SFG[13]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT2_EWSW[3]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5930), .Q(
FPADDSUB_DMP_SFG[3]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT2_EWSW[1]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5935), .Q(
FPADDSUB_DMP_SFG[1]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(FPADDSUB_Raw_mant_SGF[9]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5929), .Q(
FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(add_subt_data2[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5915), .Q(
FPADDSUB_intDY_EWSW[10]), .QN(n5804) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT2_EWSW[11]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SFG[11]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(add_subt_data1[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4440), .Q(
FPADDSUB_intDX_EWSW[13]), .QN(n943) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(add_subt_data1[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5909), .Q(
FPADDSUB_intDX_EWSW[21]), .QN(n973) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(add_subt_data2[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5905), .Q(
FPADDSUB_intDY_EWSW[24]), .QN(n5810) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(add_subt_data2[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5909), .Q(
FPADDSUB_intDY_EWSW[16]), .QN(n5806) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(add_subt_data2[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5906), .Q(
FPADDSUB_intDY_EWSW[27]), .QN(n5812) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n6009), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Y[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5990), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_X[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT2_EWSW[0]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5933), .Q(
FPADDSUB_DMP_SFG[0]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT2_EWSW[9]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5937), .Q(
FPADDSUB_DMP_SFG[9]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT2_EWSW[22]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5920), .Q(
FPADDSUB_DMP_SFG[22]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT2_EWSW[16]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5939), .Q(
FPADDSUB_DMP_SFG[16]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT2_EWSW[18]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SFG[18]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT2_EWSW[20]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5940), .Q(
FPADDSUB_DMP_SFG[20]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT2_EWSW[14]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SFG[14]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT2_EWSW[12]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5938), .Q(
FPADDSUB_DMP_SFG[12]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(add_subt_data1[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5935), .Q(
FPADDSUB_intDX_EWSW[18]), .QN(n980) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
FPADDSUB_formatted_number_W[20]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n997), .Q(
result_add_subt[20]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(add_subt_data2[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5910), .Q(
FPADDSUB_intDY_EWSW[20]), .QN(n5814) );
DFFRX1TS R_1118 ( .D(n6025), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(
n1052), .Q(n5866) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
FPADDSUB_formatted_number_W[7]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5920), .Q(
result_add_subt[7]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
FPADDSUB_formatted_number_W[6]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n4441), .Q(
result_add_subt[6]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
FPADDSUB_formatted_number_W[3]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5920), .Q(
result_add_subt[3]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
FPADDSUB_formatted_number_W[1]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n4440), .Q(
result_add_subt[1]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
FPADDSUB_formatted_number_W[0]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5916), .Q(
result_add_subt[0]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
FPADDSUB_formatted_number_W[31]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5916), .Q(
result_add_subt[31]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
FPADDSUB_formatted_number_W[9]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n1051), .Q(
result_add_subt[9]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
FPADDSUB_formatted_number_W[12]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5930), .Q(
result_add_subt[12]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
FPADDSUB_formatted_number_W[10]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5915), .Q(
result_add_subt[10]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
FPADDSUB_formatted_number_W[8]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n4440), .Q(
result_add_subt[8]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
FPADDSUB_formatted_number_W[11]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n4439), .Q(
result_add_subt[11]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
FPADDSUB_formatted_number_W[14]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n4439), .Q(
result_add_subt[14]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
FPADDSUB_formatted_number_W[13]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5917), .Q(
result_add_subt[13]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
FPADDSUB_formatted_number_W[5]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5930), .Q(
result_add_subt[5]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
FPADDSUB_formatted_number_W[15]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n997), .Q(
result_add_subt[15]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
FPADDSUB_formatted_number_W[4]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5911), .Q(
result_add_subt[4]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
FPADDSUB_formatted_number_W[17]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5911), .Q(
result_add_subt[17]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
FPADDSUB_formatted_number_W[16]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5909), .Q(
result_add_subt[16]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
FPADDSUB_formatted_number_W[2]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5909), .Q(
result_add_subt[2]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
FPADDSUB_formatted_number_W[21]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5935), .Q(
result_add_subt[21]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
FPADDSUB_formatted_number_W[19]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5931), .Q(
result_add_subt[19]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
FPADDSUB_formatted_number_W[22]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n4440), .Q(
result_add_subt[22]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
FPADDSUB_formatted_number_W[30]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5922), .Q(
result_add_subt[30]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
FPADDSUB_formatted_number_W[29]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5922), .Q(
result_add_subt[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
FPADDSUB_formatted_number_W[28]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5922), .Q(
result_add_subt[28]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
FPADDSUB_formatted_number_W[27]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5922), .Q(
result_add_subt[27]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
FPADDSUB_formatted_number_W[26]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5922), .Q(
result_add_subt[26]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
FPADDSUB_formatted_number_W[25]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5921), .Q(
result_add_subt[25]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
FPADDSUB_formatted_number_W[24]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5921), .Q(
result_add_subt[24]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
FPADDSUB_formatted_number_W[23]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5921), .Q(
result_add_subt[23]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(add_subt_data2[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5935), .Q(
FPADDSUB_intDY_EWSW[15]), .QN(n5816) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(add_subt_data1[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5911), .Q(
FPADDSUB_intDX_EWSW[20]), .QN(n981) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(add_subt_data1[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5915), .Q(
FPADDSUB_intDX_EWSW[8]), .QN(n925) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(add_subt_data1[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5917), .Q(
FPADDSUB_intDX_EWSW[11]), .QN(n969) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(add_subt_data1[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5911), .Q(
FPADDSUB_intDX_EWSW[17]), .QN(n977) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(add_subt_data1[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5904), .Q(
FPADDSUB_intDX_EWSW[25]), .QN(n944) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(add_subt_data1[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5904), .Q(
FPADDSUB_intDX_EWSW[26]), .QN(n978) );
DFFRX1TS DP_OP_497J311_123_1725_R_356 ( .D(n5572), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5583), .Q(n1049),
.QN(DP_OP_497J311_123_1725_n335) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(add_subt_data2[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4439), .Q(
FPADDSUB_intDY_EWSW[1]), .QN(n5821) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(add_subt_data2[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5905), .Q(
FPADDSUB_intDY_EWSW[26]), .QN(n5822) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(add_subt_data2[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5915), .Q(
FPADDSUB_intDY_EWSW[8]), .QN(n5819) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(add_subt_data1[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4440), .Q(
FPADDSUB_intDX_EWSW[19]), .QN(n940) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(add_subt_data1[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4443), .Q(
FPADDSUB_intDX_EWSW[1]), .QN(n945) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(add_subt_data1[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5909), .Q(
FPADDSUB_intDX_EWSW[2]), .QN(n970) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(n1016), .CK(clk), .RN(n6002), .Q(
operation_reg_0_) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(add_subt_data1[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5910), .Q(
FPADDSUB_intDX_EWSW[9]), .QN(n971) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(add_subt_data1[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5904), .Q(
FPADDSUB_intDX_EWSW[23]), .QN(n5779) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Y[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5990), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_SHT2), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n1051), .Q(
FPADDSUB_OP_FLAG_SFG) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_X[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n830), .CK(FPMULT_FS_Module_net8093716),
.RN(n5951), .Q(FPMULT_FSM_selector_B[0]), .QN(n5729) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(add_subt_data2[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5906), .Q(
FPADDSUB_intDY_EWSW[28]), .QN(n5781) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(add_subt_data1[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5905), .Q(
FPADDSUB_intDX_EWSW[28]), .QN(n5745) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n6047), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n5997), .Q(
FPSENCOS_d_ff1_operation_out) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n6058), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5944), .Q(
FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n6060), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5941), .Q(
FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
FPADDSUB_Raw_mant_SGF[14]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n5770) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
FPADDSUB_Raw_mant_SGF[12]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5929), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n5799) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Y[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5991), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_X[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n6007), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Y[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5990), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Y[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5991), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_X[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_X[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n6007), .Q(FPSENCOS_d_ff2_X[25]) );
DFFSX1TS R_1076 ( .D(n5886), .CK(clk), .SN(n5999), .Q(n6013) );
DFFSX1TS R_1110 ( .D(n5874), .CK(clk), .SN(n5963), .Q(n6011) );
DFFSX1TS R_1075 ( .D(n5887), .CK(clk), .SN(n1058), .Q(n6012) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(FPADDSUB_Data_array_SWR[0]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5912), .Q(
FPADDSUB_Data_array_SWR[2]), .QN(n974) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(add_subt_data1[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5916), .Q(
FPADDSUB_intDX_EWSW[0]), .QN(n983) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(add_subt_data2[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5905), .Q(
FPADDSUB_intDY_EWSW[23]), .QN(n5830) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n6001), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n6003), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n6003), .Q(
dataA[29]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Y[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5989), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_X[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8093734), .RN(n5992), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(
FPMULT_Adder_M_result_A_adder[22]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5950), .Q(
FPMULT_Add_result[22]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5929), .Q(FPADDSUB_N60), .QN(n5744) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(
FPMULT_Adder_M_result_A_adder[1]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5948), .Q(
FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(
FPMULT_Adder_M_result_A_adder[8]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5947), .Q(
FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(
FPMULT_Adder_M_result_A_adder[10]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5947), .Q(
FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(
FPMULT_Adder_M_result_A_adder[12]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5948), .Q(
FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(
FPMULT_Adder_M_result_A_adder[14]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5950), .Q(
FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(
FPMULT_Adder_M_result_A_adder[16]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5946), .Q(
FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(
FPMULT_Adder_M_result_A_adder[18]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5951), .Q(
FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(
FPMULT_Adder_M_result_A_adder[20]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5949), .Q(
FPMULT_Add_result[20]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(add_subt_data2[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4443), .Q(
FPADDSUB_intDY_EWSW[14]), .QN(n5723) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(add_subt_data1[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5913), .Q(
FPADDSUB_intDX_EWSW[14]), .QN(n5780) );
DFFSXLTS R_1113 ( .D(n4373), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5931), .Q(n5871) );
DFFSXLTS R_1115 ( .D(n6027), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5933), .Q(n5869), .QN(n965) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n6000), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(FPADDSUB_Raw_mant_SGF[4]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5927), .Q(
FPADDSUB_Raw_mant_NRM_SWR[4]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(FPADDSUB_Raw_mant_SGF[3]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5927), .Q(
FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n5825) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(add_subt_data2[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5911), .Q(
FPADDSUB_intDY_EWSW[4]), .QN(n5807) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(add_subt_data2[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4440), .Q(
FPADDSUB_intDY_EWSW[6]), .QN(n5805) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n6048), .CK(
clk), .RN(n5903), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]),
.QN(n979) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(add_subt_data2[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5909), .Q(
FPADDSUB_intDY_EWSW[21]), .QN(n5813) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(add_subt_data2[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4441), .Q(
FPADDSUB_intDY_EWSW[13]), .QN(n5808) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(add_subt_data2[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5909), .Q(
FPADDSUB_intDY_EWSW[2]), .QN(n5809) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(add_subt_data2[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n1052), .Q(
FPADDSUB_intDY_EWSW[9]), .QN(n5811) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n6000), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
FPADDSUB_formatted_number_W[18]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8093446), .RN(n5931), .Q(
result_add_subt[18]) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
FPADDSUB_inst_ShiftRegister_net8093608), .RN(n5932), .Q(
FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n5789) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[2]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5916), .Q(
FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n5772) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n6054), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5944), .Q(
FPMULT_Sgf_normalized_result[9]) );
DFFRXLTS R_848 ( .D(add_x_246_A_7_), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5943), .Q(
FPMULT_Sgf_normalized_result[7]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n5958), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(n5916), .Q(
FPADDSUB_bit_shift_SHT2) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(add_subt_data2[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5905), .Q(
FPADDSUB_intDY_EWSW[25]), .QN(n5818) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(add_subt_data2[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5911), .Q(
FPADDSUB_intDY_EWSW[17]), .QN(n5817) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(add_subt_data2[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5913), .Q(
FPADDSUB_intDY_EWSW[11]), .QN(n5815) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(add_subt_data2[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5934), .Q(
FPADDSUB_intDY_EWSW[18]), .QN(n5820) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(add_subt_data2[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4441), .Q(
FPADDSUB_intDY_EWSW[3]), .QN(n5823) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(Data_1[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5952), .Q(
FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(Data_1[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5952), .Q(
FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(Data_1[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5952), .Q(
FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(Data_1[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5952), .Q(
FPMULT_Op_MX[28]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(Data_1[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5952), .Q(
FPMULT_Op_MX[30]), .QN(n5895) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(add_subt_data1[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5904), .Q(
FPADDSUB_intDX_EWSW[24]), .QN(n982) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(add_subt_data1[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5904), .Q(
FPADDSUB_intDX_EWSW[27]), .QN(n966) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(add_subt_data2[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5914), .Q(
FPADDSUB_intDY_EWSW[19]), .QN(n5725) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(FPADDSUB_N59), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5927), .Q(
FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(FPADDSUB_Raw_mant_SGF[6]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5927), .Q(
FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n5734) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(add_subt_data2[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n996), .Q(
FPADDSUB_intDY_EWSW[22]), .QN(n5726) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(add_subt_data2[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5916), .Q(
FPADDSUB_intDY_EWSW[0]), .QN(n5824) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(region_flag[1]), .CK(
FPSENCOS_reg_Z0_net8093734), .RN(n1058), .Q(
FPSENCOS_d_ff1_shift_region_flag_out[1]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(add_subt_data1[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n996), .Q(
FPADDSUB_intDX_EWSW[22]), .QN(n946) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n874), .CK(clk), .RN(n5903), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFSX1TS DP_OP_499J311_125_1651_R_813 ( .D(DP_OP_499J311_125_1651_n78), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5504), .Q(n5475)
);
DFFSXLTS DP_OP_499J311_125_1651_R_1043 ( .D(n5511), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5504), .Q(n5492)
);
DFFSX1TS DP_OP_499J311_125_1651_R_814 ( .D(DP_OP_499J311_125_1651_n86), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5504), .Q(n5476)
);
DFFSXLTS DP_OP_499J311_125_1651_R_1041 ( .D(DP_OP_499J311_125_1651_n186),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5504), .Q(
n5490) );
DFFSXLTS DP_OP_499J311_125_1651_R_1044 ( .D(DP_OP_499J311_125_1651_n29),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5504), .Q(
n5493) );
DFFSXLTS DP_OP_499J311_125_1651_R_1042 ( .D(DP_OP_499J311_125_1651_n185),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5504), .Q(
n5491) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(
FPMULT_Sgf_operation_Result[8]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5962), .QN(n5881) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n5903), .Q(ready_add_subt), .QN(n976) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n5999), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .QN(n1194) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(
FPMULT_FS_Module_state_next[2]), .CK(FPMULT_FS_Module_net8093716),
.RN(n5969), .Q(n5728), .QN(n5738) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5931), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n5737) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5912), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n5741) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5933), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n5740) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n1052), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n5735) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5910), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n5739) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n5751), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5931), .Q(
FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n5714) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(add_subt_data1[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5909), .Q(
FPADDSUB_intDX_EWSW[16]), .QN(n5776) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(add_subt_data1[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5915), .Q(
FPADDSUB_intDX_EWSW[10]), .QN(n5766) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n4442), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(add_subt_data1[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5911), .Q(
FPADDSUB_intDX_EWSW[4]), .QN(n5777) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(add_subt_data1[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n4439), .Q(
FPADDSUB_intDX_EWSW[6]), .QN(n5778) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(add_subt_data2[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5931), .Q(
FPADDSUB_intDY_EWSW[12]), .QN(n5767) );
DFFSX1TS add_x_69_R_1148 ( .D(add_x_69_n238), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n6007), .Q(n5691)
);
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n6001), .Q(
dataB[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(Data_1[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5839), .Q(
FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(
FPMULT_Adder_M_result_A_adder[21]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5946), .Q(
FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(
FPMULT_Adder_M_result_A_adder[19]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5947), .Q(
FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(
FPMULT_Adder_M_result_A_adder[17]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5949), .Q(
FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(
FPMULT_Adder_M_result_A_adder[15]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5949), .Q(
FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(
FPMULT_Adder_M_result_A_adder[13]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5948), .Q(
FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(
FPMULT_Adder_M_result_A_adder[11]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5948), .Q(
FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(
FPMULT_Adder_M_result_A_adder[9]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5950), .Q(
FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(
FPMULT_Adder_M_result_A_adder[2]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5951), .Q(
FPMULT_Add_result[2]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(FPADDSUB_Raw_mant_SGF[1]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5927), .Q(
FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n5773) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n6001), .Q(
dataB[23]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n6003), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n6003), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n6001), .Q(
dataB[26]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n6008), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n6003), .Q(
dataA[27]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n6001), .Q(
dataB[24]) );
DFFRX2TS DP_OP_497J311_123_1725_R_793 ( .D(Data_2[14]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5583), .Q(
DP_OP_497J311_123_1725_n780), .QN(n960) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(FPSENCOS_ITER_CONT_N3), .CK(
FPSENCOS_ITER_CONT_net8093770), .RN(n6000), .Q(
FPSENCOS_cont_iter_out[1]), .QN(n5732) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
FPADDSUB_Raw_mant_SGF[20]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5929), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
FPADDSUB_Raw_mant_SGF[21]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5929), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n5788) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
FPADDSUB_Raw_mant_SGF[23]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
FPADDSUB_Raw_mant_SGF[24]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n5801) );
DFFRX2TS R_240 ( .D(Data_2[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5838), .Q(
FPMULT_Op_MY[8]), .QN(n5898) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n6002), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX1TS R_167 ( .D(n6049), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1001), .Q(
FPMULT_Sgf_normalized_result[0]) );
DFFRX1TS R_166 ( .D(n6050), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1001), .Q(
FPMULT_Sgf_normalized_result[1]) );
DFFRX1TS R_227 ( .D(add_x_246_A_3_), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1001), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(
FPMULT_Adder_M_result_A_adder[3]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5949), .Q(
FPMULT_Add_result[3]) );
DFFRXLTS R_250 ( .D(Data_1[14]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5837), .QN(n5900) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(Data_1[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5839), .Q(
FPMULT_Op_MX[29]), .QN(n5894) );
DFFRXLTS R_398 ( .D(Data_2[13]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5840), .QN(n5899) );
DFFRXLTS R_451 ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1056), .QN(n5892) );
DFFRX1TS R_488 ( .D(n6052), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1002), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS R_528 ( .D(add_x_246_A_5_), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1002), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(
FPMULT_Adder_M_result_A_adder[5]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5946), .Q(
FPMULT_Add_result[5]) );
DFFRX1TS R_650 ( .D(add_x_246_A_6_), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1002), .Q(
FPMULT_Sgf_normalized_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(
FPMULT_Adder_M_result_A_adder[6]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5951), .Q(
FPMULT_Add_result[6]) );
DFFSXLTS R_719 ( .D(n6026), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5932), .Q(n5889) );
DFFSX1TS R_1083 ( .D(n5885), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5839), .Q(n6037),
.QN(n5826) );
DFFSX1TS R_1085 ( .D(n5883), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1059), .Q(n6036)
);
DFFSX1TS R_1086 ( .D(n5882), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n6008), .Q(n5955)
);
DFFSX1TS R_1087 ( .D(n5880), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n6009), .Q(n6035)
);
DFFSX1TS R_1093 ( .D(n5878), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1054), .Q(n5957)
);
DFFSX1TS R_1096 ( .D(n5877), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5542), .Q(n5897)
);
DFFRX2TS R_1094 ( .D(Data_2[20]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5953), .Q(
DP_OP_496J311_122_3540_n1464) );
DFFSX1TS R_1099 ( .D(n5876), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5839), .Q(n5893)
);
DFFRXLTS R_1101 ( .D(n5875), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1054), .QN(n5834) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(
FPMULT_Adder_M_result_A_adder[4]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5950), .Q(
FPMULT_Add_result[4]) );
DFFRX1TS R_1111 ( .D(n5873), .CK(clk), .RN(n6002), .Q(n6010) );
DFFRX1TS R_1120 ( .D(n6023), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(
n1052), .Q(n5864) );
DFFRX1TS R_1124 ( .D(n6019), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(
n1051), .Q(n5860) );
DFFRX1TS R_1127 ( .D(n6015), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(
n5932), .Q(n5857) );
DFFRX1TS R_1133 ( .D(n6016), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(
n5917), .Q(n5851) );
DFFRX1TS R_1144 ( .D(n6030), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .RN(
n996), .Q(n5843) );
DFFSX1TS R_1173 ( .D(n5841), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5839), .Q(n5956)
);
DFFRX1TS add_x_246_R_849 ( .D(n5706), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5945), .Q(
add_x_246_n17) );
DFFRX1TS add_x_246_R_652 ( .D(n5705), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1002), .Q(
FPMULT_Adder_M_result_A_adder[6]) );
DFFRX1TS add_x_246_R_530 ( .D(n5704), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1002), .Q(
FPMULT_Adder_M_result_A_adder[5]) );
DFFRX1TS add_x_246_R_229 ( .D(n5703), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1002), .Q(
FPMULT_Adder_M_result_A_adder[3]) );
DFFRX1TS add_x_246_R_170 ( .D(n6050), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1001), .Q(
add_x_246_A_1_) );
DFFRX1TS add_x_246_R_169 ( .D(n6051), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n1001), .Q(
add_x_246_A_2_) );
DFFRX1TS add_x_246_R_25 ( .D(add_x_246_n2), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5947), .Q(n5702) );
DFFRX1TS add_x_246_R_24 ( .D(FPMULT_Sgf_normalized_result[23]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8093626), .RN(n5948), .Q(n5701) );
DFFSX1TS add_x_69_R_1147 ( .D(add_x_69_n228), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n824), .Q(n5690)
);
DFFSX1TS add_x_69_R_1140 ( .D(add_x_69_n271), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n4463), .Q(n5688)
);
DFFRXLTS add_x_69_R_744_RW_1 ( .D(add_x_69_n242), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(n5665)
);
DFFRXLTS add_x_69_R_810_RW_0 ( .D(add_x_69_n243), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(n5670)
);
DFFRXLTS add_x_69_R_776_RW_0 ( .D(add_x_69_n271), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(n5668)
);
DFFSX1TS add_x_69_R_1055 ( .D(add_x_69_n26), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n4442), .Q(n5687)
);
DFFSX1TS add_x_69_R_1054 ( .D(add_x_69_n282), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1058), .Q(n5686)
);
DFFRXLTS add_x_69_R_995 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(n5683)
);
DFFRXLTS add_x_69_R_819 ( .D(add_x_69_n21), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(n5674)
);
DFFRXLTS add_x_69_R_817 ( .D(add_x_69_n23), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(n5672)
);
DFFRXLTS add_x_69_R_750 ( .D(add_x_69_n19), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(n5666)
);
DFFRXLTS add_x_69_R_642_RW_0 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[5]),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(
n5663) );
DFFRXLTS add_x_69_R_639 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5700), .Q(n5662)
);
DFFSX1TS add_x_69_R_617 ( .D(add_x_69_n244), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5999), .Q(n5660)
);
DFFSX1TS add_x_69_R_582 ( .D(add_x_69_n241), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1059), .Q(n5659)
);
DFFRXLTS add_x_69_R_581 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5965), .Q(n5658)
);
DFFRXLTS add_x_69_R_575 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5965), .Q(n5657)
);
DFFRXLTS add_x_69_R_573 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5965), .Q(n5656)
);
DFFRXLTS add_x_69_R_567 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5965), .Q(n5655)
);
DFFSX1TS add_x_69_R_544 ( .D(add_x_69_n272), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n6008), .Q(n5654)
);
DFFSX1TS add_x_69_R_543 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1059), .Q(n5653)
);
DFFSX1TS add_x_69_R_538 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1058), .Q(n5652)
);
DFFSX1TS add_x_69_R_524 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1058), .Q(n5651)
);
DFFRXLTS add_x_69_R_514 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5697), .Q(n5650)
);
DFFRXLTS add_x_69_R_511 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5697), .Q(n5649)
);
DFFSX1TS add_x_69_R_508 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1058), .Q(n5648)
);
DFFRXLTS add_x_69_R_504 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5965), .Q(n5647)
);
DFFSX1TS add_x_69_R_497 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1059), .Q(n5645)
);
DFFRXLTS add_x_69_R_211 ( .D(n924), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5697), .Q(n5643)
);
DFFRXLTS add_x_69_R_210 ( .D(n4025), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5697), .Q(n5642)
);
DFFRXLTS add_x_69_R_196 ( .D(add_x_69_n94), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5696), .Q(n5641)
);
DFFRXLTS add_x_69_R_187 ( .D(n3998), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5696), .Q(n5640)
);
DFFRXLTS add_x_69_R_185 ( .D(add_x_69_n57), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5697), .Q(n5639)
);
DFFRXLTS add_x_69_R_183 ( .D(add_x_69_n39), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5697), .Q(n5638)
);
DFFSX1TS add_x_69_R_9 ( .D(add_x_69_n113), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1059), .Q(n5622)
);
DFFRXLTS add_x_69_R_5 ( .D(n918), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5971), .Q(n5621)
);
DFFRXLTS add_x_69_R_3 ( .D(add_x_69_n69), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5697), .Q(n5620)
);
DFFRXLTS DP_OP_496J311_122_3540_R_1174 ( .D(n5611), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5540), .Q(n5598),
.QN(n5618) );
DFFSX2TS DP_OP_496J311_122_3540_R_1164 ( .D(n5609), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5838), .Q(
DP_OP_496J311_122_3540_n1096), .QN(n5616) );
DFFRX1TS DP_OP_496J311_122_3540_R_1160 ( .D(n5608), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5540), .Q(n5599)
);
DFFSX2TS DP_OP_497J311_123_1725_R_794 ( .D(n5581), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5582), .Q(
DP_OP_497J311_123_1725_n386) );
DFFSX1TS DP_OP_497J311_123_1725_R_383 ( .D(n5574), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5585), .Q(n5569),
.QN(n5588) );
DFFSX2TS DP_OP_497J311_123_1725_R_358 ( .D(DP_OP_497J311_123_1725_n336),
.CK(FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5582), .Q(
n5545) );
DFFRX2TS DP_OP_497J311_123_1725_R_359 ( .D(n5573), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5583), .QN(n5592) );
DFFSX1TS DP_OP_497J311_123_1725_R_334 ( .D(n5561), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5582), .Q(
DP_OP_497J311_123_1725_n385), .QN(n5590) );
DFFRX1TS DP_OP_497J311_123_1725_R_330 ( .D(Data_2[21]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5583), .Q(
DP_OP_497J311_123_1725_n683) );
DFFRXLTS DP_OP_497J311_123_1725_R_269 ( .D(Data_1[16]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .Q(
DP_OP_497J311_123_1725_n795) );
DFFSX1TS DP_OP_498J311_124_1725_R_1108 ( .D(n5538), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1056), .QN(n1170) );
DFFSX2TS DP_OP_498J311_124_1725_R_454 ( .D(n5532), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1055), .Q(
DP_OP_498J311_124_1725_n392) );
DFFRX2TS DP_OP_498J311_124_1725_R_314 ( .D(Data_1[11]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5836), .Q(
DP_OP_498J311_124_1725_n799) );
DFFRXLTS DP_OP_498J311_124_1725_R_310 ( .D(Data_2[11]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5541), .Q(
DP_OP_498J311_124_1725_n787) );
DFFRXLTS DP_OP_498J311_124_1725_R_289 ( .D(n5521), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5942), .Q(
DP_OP_498J311_124_1725_n630) );
DFFRXLTS DP_OP_498J311_124_1725_R_286 ( .D(Data_2[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5941), .Q(
DP_OP_498J311_124_1725_n782) );
DFFRX2TS DP_OP_498J311_124_1725_R_258 ( .D(Data_1[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n1055), .Q(
DP_OP_498J311_124_1725_n805) );
DFFRXLTS DP_OP_498J311_124_1725_R_242 ( .D(Data_2[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5947), .Q(
DP_OP_498J311_124_1725_n784) );
DFFSX1TS DP_OP_499J311_125_1651_R_1153 ( .D(DP_OP_499J311_125_1651_n187),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1058), .Q(
n5501) );
DFFSX1TS DP_OP_499J311_125_1651_R_1141 ( .D(DP_OP_499J311_125_1651_n48),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1059), .Q(
n5497) );
DFFRXLTS DP_OP_499J311_125_1651_R_1071 ( .D(DP_OP_499J311_125_1651_n190),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5965), .Q(
n5496) );
DFFRXLTS DP_OP_499J311_125_1651_R_902_RW_0 ( .D(DP_OP_499J311_125_1651_n69),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5999), .Q(
n5480) );
DFFRXLTS DP_OP_499J311_125_1651_R_901_RW_0 ( .D(DP_OP_499J311_125_1651_n74),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5504), .Q(
n5479) );
DFFSX1TS DP_OP_499J311_125_1651_R_730_RW_0 ( .D(DP_OP_499J311_125_1651_n72),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n6004), .Q(
n5472) );
DFFSX1TS DP_OP_499J311_125_1651_R_620_RW_0 ( .D(DP_OP_499J311_125_1651_n9),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n6004), .Q(
n5470) );
DFFSX1TS DP_OP_499J311_125_1651_R_971 ( .D(DP_OP_499J311_125_1651_n190),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5999), .Q(
n5487) );
DFFRXLTS DP_OP_499J311_125_1651_R_968 ( .D(DP_OP_499J311_125_1651_n13), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5965), .Q(n5486)
);
DFFSX1TS DP_OP_499J311_125_1651_R_967 ( .D(DP_OP_499J311_125_1651_n93), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5999), .Q(n5485)
);
DFFSX1TS DP_OP_499J311_125_1651_R_961 ( .D(DP_OP_499J311_125_1651_n166),
.CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n824), .Q(
n5483) );
DFFRXLTS DP_OP_499J311_125_1651_R_936 ( .D(DP_OP_499J311_125_1651_n84), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5504), .Q(n5482)
);
DFFSX1TS DP_OP_499J311_125_1651_R_935 ( .D(DP_OP_499J311_125_1651_n83), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5965), .Q(n5481)
);
DFFSX1TS DP_OP_499J311_125_1651_R_699 ( .D(DP_OP_499J311_125_1651_n10), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n1058), .Q(n5471)
);
DFFRX1TS DP_OP_497J311_123_1725_R_792 ( .D(Data_2[20]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5583), .Q(
DP_OP_497J311_123_1725_n684) );
DFFSX2TS DP_OP_496J311_122_3540_R_1107 ( .D(n5607), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5954), .Q(
DP_OP_496J311_122_3540_n1108) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n6053), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8093644), .RN(n5942), .Q(
FPMULT_Sgf_normalized_result[8]) );
DFFSX2TS DP_OP_496J311_122_3540_R_1167 ( .D(n5614), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5954), .Q(
DP_OP_496J311_122_3540_n1103) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
FPADDSUB_Raw_mant_SGF[19]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n5802) );
DFFRX1TS R_315 ( .D(Data_1[11]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5837), .Q(
DP_OP_496J311_122_3540_n1138), .QN(DP_OP_496J311_122_3540_n846) );
DFFRXLTS DP_OP_498J311_124_1725_R_444 ( .D(n5530), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5541), .Q(
DP_OP_498J311_124_1725_n708) );
DFFRX1TS DP_OP_497J311_123_1725_R_280 ( .D(n5552), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .Q(
DP_OP_497J311_123_1725_n675) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
FPADDSUB_Raw_mant_SGF[15]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
FPADDSUB_Raw_mant_SGF[16]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
FPADDSUB_Raw_mant_SGF[17]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8093482), .RN(n5928), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(add_subt_data1[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8093446), .RN(n5910), .Q(
FPADDSUB_intDX_EWSW[12]), .QN(n5803) );
DFFRX1TS DP_OP_498J311_124_1725_R_207 ( .D(Data_2[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5837), .Q(
DP_OP_498J311_124_1725_n793) );
DFFSX2TS DP_OP_498J311_124_1725_R_1177 ( .D(n5539), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n1055), .Q(
DP_OP_498J311_124_1725_n380), .QN(n5544) );
DFFRX1TS DP_OP_498J311_124_1725_R_312 ( .D(n5524), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5836), .Q(
DP_OP_498J311_124_1725_n694) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5929), .Q(FPADDSUB_N59), .QN(n5717) );
DFFRX2TS DP_OP_498J311_124_1725_R_459 ( .D(n5533), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5838), .Q(
DP_OP_498J311_124_1725_n698) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT2_EWSW[4]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n5912), .Q(
FPADDSUB_DMP_SFG[4]) );
DFFRX2TS DP_OP_497J311_123_1725_R_262 ( .D(n5549), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5584), .Q(
DP_OP_497J311_123_1725_n623) );
DFFRX2TS DP_OP_498J311_124_1725_R_255 ( .D(Data_2[10]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5541), .Q(
DP_OP_498J311_124_1725_n786) );
DFFRX2TS DP_OP_498J311_124_1725_R_295 ( .D(Data_2[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5943), .Q(
DP_OP_498J311_124_1725_n792) );
DFFSX2TS DP_OP_497J311_123_1725_R_789 ( .D(n5587), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .SN(n5583), .Q(
DP_OP_497J311_123_1725_n378), .QN(n5593) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n5753), .CK(
FPADDSUB_SGF_STAGE_DMP_net8093500), .RN(n1051), .Q(
FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n5713) );
DFFRX2TS DP_OP_498J311_124_1725_R_328 ( .D(Data_2[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5541), .Q(
DP_OP_498J311_124_1725_n785) );
DFFRX2TS R_462 ( .D(Data_1[10]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5838), .Q(
DP_OP_496J311_122_3540_n1516) );
DFFRX1TS DP_OP_497J311_123_1725_R_304 ( .D(n5556), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5584), .Q(
DP_OP_497J311_123_1725_n609) );
ADDFX2TS DP_OP_234J311_129_4955_U2 ( .A(n1034), .B(FPMULT_S_Oper_A_exp[8]),
.CI(DP_OP_234J311_129_4955_n2), .CO(DP_OP_234J311_129_4955_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
DFFRX1TS DP_OP_497J311_123_1725_R_226 ( .D(Data_1[12]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .Q(
DP_OP_497J311_123_1725_n791) );
DFFSX2TS R_1178 ( .D(add_x_69_n235), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .SN(n5698), .Q(n934)
);
DFFRX1TS DP_OP_497J311_123_1725_R_292 ( .D(Data_1[14]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5585), .Q(
DP_OP_497J311_123_1725_n793) );
DFFRX1TS DP_OP_498J311_124_1725_R_857 ( .D(n5535), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5541), .Q(
DP_OP_498J311_124_1725_n717) );
DFFRXLTS R_1179 ( .D(add_x_69_n77), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8093662), .RN(n5697), .Q(n933)
);
DFFRX2TS DP_OP_497J311_123_1725_R_298 ( .D(Data_1[15]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .Q(
DP_OP_497J311_123_1725_n794) );
DFFRX2TS DP_OP_497J311_123_1725_R_435 ( .D(Data_1[20]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5586), .Q(
DP_OP_497J311_123_1725_n699) );
DFFRX2TS DP_OP_497J311_123_1725_R_410 ( .D(n5576), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5583), .QN(n910)
);
DFFRX2TS R_1089 ( .D(Data_2[11]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8093698), .RN(n5953), .Q(
FPMULT_Op_MY[11]), .QN(n950) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(
FPMULT_FS_Module_state_next[0]), .CK(FPMULT_FS_Module_net8093716),
.RN(n5964), .Q(n937), .QN(n5718) );
CMPR32X2TS DP_OP_234J311_129_4955_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_234J311_129_4955_n22), .CO(
DP_OP_234J311_129_4955_n9), .S(FPMULT_Exp_module_Data_S[0]) );
DFFSX2TS R_1114 ( .D(n6028), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8093482), .SN(
n5935), .Q(n5870), .QN(n939) );
CMPR32X2TS DP_OP_234J311_129_4955_U9 ( .A(DP_OP_234J311_129_4955_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J311_129_4955_n9), .CO(
DP_OP_234J311_129_4955_n8), .S(FPMULT_Exp_module_Data_S[1]) );
ADDFHX1TS DP_OP_234J311_129_4955_U7 ( .A(DP_OP_234J311_129_4955_n19), .B(
FPMULT_S_Oper_A_exp[3]), .CI(DP_OP_234J311_129_4955_n7), .CO(
DP_OP_234J311_129_4955_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_26J311_126_1325_U2 ( .A(n1027), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J311_126_1325_n2), .CO(
DP_OP_26J311_126_1325_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS intadd_1046_U4 ( .A(n998), .B(FPSENCOS_d_ff2_Y[24]), .C(
intadd_1046_CI), .CO(intadd_1046_n3), .S(FPSENCOS_sh_exp_y[1]) );
CMPR32X2TS intadd_1046_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n5709), .C(
intadd_1046_n3), .CO(intadd_1046_n2), .S(FPSENCOS_sh_exp_y[2]) );
CMPR32X2TS DP_OP_234J311_129_4955_U5 ( .A(DP_OP_234J311_129_4955_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J311_129_4955_n5), .CO(
DP_OP_234J311_129_4955_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS intadd_1046_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n5710), .C(
intadd_1046_n2), .CO(intadd_1046_n1), .S(FPSENCOS_sh_exp_y[3]) );
CMPR32X2TS DP_OP_234J311_129_4955_U3 ( .A(DP_OP_234J311_129_4955_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J311_129_4955_n3), .CO(
DP_OP_234J311_129_4955_n2), .S(FPMULT_Exp_module_Data_S[7]) );
NAND2X4TS U1399 ( .A(DP_OP_499J311_125_1651_n199), .B(
DP_OP_499J311_125_1651_n202), .Y(DP_OP_499J311_125_1651_n61) );
ADDHXLTS U1400 ( .A(add_x_246_A_7_), .B(n4123), .CO(n5706), .S(n5707) );
NOR2X4TS U1401 ( .A(n3924), .B(n3925), .Y(DP_OP_499J311_125_1651_n53) );
NAND2X1TS U1402 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[20]), .B(n4018), .Y(
add_x_69_n57) );
OAI21X2TS U1403 ( .A0(add_x_69_n271), .A1(n3930), .B0(n3929), .Y(
add_x_69_n250) );
NOR2X2TS U1404 ( .A(n4029), .B(add_x_69_n230), .Y(add_x_69_n228) );
INVX2TS U1405 ( .A(n5269), .Y(n5271) );
INVX2TS U1406 ( .A(n5269), .Y(n5268) );
BUFX3TS U1407 ( .A(n5239), .Y(n5242) );
BUFX3TS U1408 ( .A(n5233), .Y(n5234) );
INVX2TS U1409 ( .A(n5264), .Y(n5262) );
INVX2TS U1410 ( .A(n5264), .Y(n5254) );
INVX2TS U1411 ( .A(n5264), .Y(n5263) );
INVX2TS U1412 ( .A(n5264), .Y(n5265) );
INVX2TS U1413 ( .A(n1192), .Y(n4508) );
NOR2X1TS U1414 ( .A(n4703), .B(n4132), .Y(n6029) );
NAND2X6TS U1415 ( .A(n3909), .B(n3908), .Y(n3974) );
INVX6TS U1416 ( .A(n990), .Y(n992) );
INVX6TS U1417 ( .A(n990), .Y(n991) );
ADDHXLTS U1418 ( .A(add_x_246_A_6_), .B(n4122), .CO(n4123), .S(n5705) );
NAND2X1TS U1419 ( .A(n4792), .B(n4791), .Y(n4794) );
CLKINVX1TS U1420 ( .A(n4030), .Y(n4032) );
NAND2X4TS U1421 ( .A(n3984), .B(n3982), .Y(n3963) );
INVX4TS U1422 ( .A(n4029), .Y(add_x_69_n235) );
AOI21X2TS U1423 ( .A0(n3928), .A1(n4011), .B0(n3927), .Y(n3929) );
INVX4TS U1424 ( .A(add_x_69_n244), .Y(add_x_69_n242) );
BUFX3TS U1425 ( .A(n5372), .Y(n5354) );
BUFX3TS U1426 ( .A(n5077), .Y(n5285) );
BUFX3TS U1427 ( .A(n5369), .Y(n5291) );
BUFX3TS U1428 ( .A(n5331), .Y(n5380) );
BUFX3TS U1429 ( .A(n5331), .Y(n5353) );
NOR2X4TS U1430 ( .A(n3965), .B(n3964), .Y(DP_OP_499J311_125_1651_n83) );
ADDHXLTS U1431 ( .A(add_x_246_A_5_), .B(n4125), .CO(n4122), .S(n5704) );
OR3X1TS U1432 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_1045_n1), .Y(n5467) );
INVX2TS U1433 ( .A(n3985), .Y(n1067) );
NAND2X1TS U1434 ( .A(add_x_69_n113), .B(add_x_69_n105), .Y(n4025) );
BUFX3TS U1435 ( .A(n5272), .Y(n5269) );
BUFX3TS U1436 ( .A(n1192), .Y(n5259) );
NOR2X6TS U1437 ( .A(n4015), .B(n4014), .Y(n4029) );
INVX2TS U1438 ( .A(n5270), .Y(n5266) );
NAND2X6TS U1439 ( .A(n3720), .B(n3719), .Y(add_x_69_n272) );
AND2X2TS U1440 ( .A(n5829), .B(n5195), .Y(n5251) );
XOR2X2TS U1441 ( .A(n3293), .B(n3292), .Y(n3642) );
INVX2TS U1442 ( .A(n3802), .Y(add_x_69_n95) );
ADDFHX2TS U1443 ( .A(n3258), .B(n3877), .CI(n3257), .CO(n3644), .S(n3832) );
BUFX3TS U1444 ( .A(n5233), .Y(n5239) );
BUFX3TS U1445 ( .A(n1192), .Y(n5264) );
ADDFHX2TS U1446 ( .A(n3923), .B(n918), .CI(n3922), .CO(n3911), .S(n3931) );
BUFX3TS U1447 ( .A(n5386), .Y(n5424) );
BUFX3TS U1448 ( .A(n5425), .Y(n5395) );
INVX6TS U1449 ( .A(n4002), .Y(n3919) );
INVX2TS U1450 ( .A(n3726), .Y(n3862) );
NAND2X1TS U1451 ( .A(n865), .B(FPSENCOS_cont_iter_out[0]), .Y(n5433) );
NAND2X1TS U1452 ( .A(n3291), .B(n3839), .Y(n3292) );
NAND2X1TS U1453 ( .A(n4108), .B(n4107), .Y(add_x_246_A_5_) );
AOI21X2TS U1454 ( .A0(n3918), .A1(n3272), .B0(n3271), .Y(n3293) );
CLKAND2X2TS U1455 ( .A(n3272), .B(n3841), .Y(n3234) );
NOR2X6TS U1456 ( .A(n6040), .B(n6041), .Y(n938) );
NAND2X2TS U1457 ( .A(n1142), .B(n3957), .Y(n936) );
BUFX3TS U1458 ( .A(n5272), .Y(n5270) );
BUFX4TS U1459 ( .A(n5369), .Y(n5372) );
NAND4BX1TS U1460 ( .AN(n4166), .B(n3629), .C(n3628), .D(n3627), .Y(
FPADDSUB_LZD_raw_out_EWR[1]) );
INVX2TS U1461 ( .A(n3877), .Y(FPMULT_Sgf_operation_EVEN1_Q_left[20]) );
INVX2TS U1462 ( .A(operation[1]), .Y(n1015) );
INVX1TS U1463 ( .A(add_x_69_n69), .Y(n3996) );
OR2X2TS U1464 ( .A(FPSENCOS_cont_iter_out[2]), .B(n5196), .Y(n1192) );
BUFX3TS U1465 ( .A(n5407), .Y(n5425) );
BUFX6TS U1466 ( .A(n5386), .Y(n5397) );
CLKINVX2TS U1467 ( .A(n3995), .Y(n3971) );
BUFX3TS U1468 ( .A(FPADDSUB_left_right_SHT2), .Y(n4774) );
ADDHXLTS U1469 ( .A(add_x_246_A_3_), .B(n4124), .CO(n4121), .S(n5703) );
NAND2X1TS U1470 ( .A(n3859), .B(n3858), .Y(n3915) );
NAND2X1TS U1471 ( .A(n4067), .B(n4066), .Y(n6052) );
NOR2X4TS U1472 ( .A(n3732), .B(n3731), .Y(n4028) );
NAND2X2TS U1473 ( .A(n3733), .B(n3726), .Y(n4000) );
NOR3X6TS U1474 ( .A(n4702), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n4599),
.Y(n6040) );
INVX2TS U1475 ( .A(n5221), .Y(n5272) );
INVX2TS U1476 ( .A(n5958), .Y(n4728) );
NAND2BX1TS U1477 ( .AN(n3620), .B(n3619), .Y(n4166) );
NOR2X4TS U1478 ( .A(n3726), .B(n3733), .Y(n3999) );
NOR2X2TS U1479 ( .A(n3838), .B(n3840), .Y(n3913) );
INVX2TS U1480 ( .A(n1043), .Y(n1003) );
NAND3X2TS U1481 ( .A(n5710), .B(n5712), .C(n998), .Y(n5196) );
NOR2X4TS U1482 ( .A(n5378), .B(n4383), .Y(n4517) );
BUFX3TS U1483 ( .A(n5077), .Y(n5369) );
INVX4TS U1484 ( .A(n5435), .Y(n5386) );
NOR2X6TS U1485 ( .A(n5378), .B(operation[2]), .Y(n5407) );
INVX6TS U1486 ( .A(n1741), .Y(add_x_69_n77) );
NAND2X1TS U1487 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n5280) );
NAND2X1TS U1488 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n4738) );
AND4X1TS U1489 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n4700), .Y(n4701) );
NAND2X1TS U1490 ( .A(n3714), .B(n3801), .Y(n4174) );
INVX2TS U1491 ( .A(n1042), .Y(n1043) );
NOR2X1TS U1492 ( .A(n4600), .B(n4181), .Y(n3712) );
NAND2X4TS U1493 ( .A(n3791), .B(n1076), .Y(n1072) );
AOI21X2TS U1494 ( .A0(n3897), .A1(n3790), .B0(n3791), .Y(n3796) );
NAND2X2TS U1495 ( .A(n3715), .B(n3787), .Y(n4034) );
NAND2X1TS U1496 ( .A(n3716), .B(n3663), .Y(n4021) );
XNOR2X2TS U1497 ( .A(DP_OP_26J311_126_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n4702) );
NAND2X2TS U1498 ( .A(n3794), .B(n3793), .Y(n3795) );
NOR2X1TS U1499 ( .A(n4707), .B(FPADDSUB_ADD_OVRFLW_NRM), .Y(n5959) );
NAND4BBX1TS U1500 ( .AN(n5143), .BN(n5142), .C(n5141), .D(n5140), .Y(n5144)
);
NAND3BXLTS U1501 ( .AN(n5128), .B(n5126), .C(n5125), .Y(n5146) );
BUFX3TS U1502 ( .A(n4566), .Y(n5077) );
AOI2BB2X1TS U1503 ( .B0(n5090), .B1(n5141), .A0N(n5089), .A1N(n5088), .Y(
n5147) );
NAND2X2TS U1504 ( .A(n5338), .B(operation[2]), .Y(n5435) );
INVX2TS U1505 ( .A(FPSENCOS_cont_iter_out[1]), .Y(n998) );
OAI2BB2XLTS U1506 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n5136), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n5135), .Y(n5137) );
NAND2X1TS U1507 ( .A(n4606), .B(n4605), .Y(n4607) );
BUFX3TS U1508 ( .A(n5789), .Y(n4707) );
NAND2X1TS U1509 ( .A(n3689), .B(n3688), .Y(n4187) );
NAND2X1TS U1510 ( .A(n3710), .B(n3763), .Y(n4183) );
INVX2TS U1511 ( .A(n3792), .Y(n3794) );
OAI2BB1X1TS U1512 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[18]), .A1N(n3638), .B0(
n4724), .Y(n3633) );
NAND2X6TS U1513 ( .A(n1773), .B(n1772), .Y(n3873) );
NAND2X1TS U1514 ( .A(n3891), .B(n3890), .Y(n3892) );
NOR2X4TS U1515 ( .A(n3663), .B(n3716), .Y(n4020) );
NAND2X1TS U1516 ( .A(n2846), .B(n2873), .Y(n3864) );
NAND2X4TS U1517 ( .A(n3204), .B(n3203), .Y(n3778) );
NAND2X1TS U1518 ( .A(FPSENCOS_d_ff1_operation_out), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n5222) );
NOR2X1TS U1519 ( .A(n5246), .B(FPADDSUB_intDX_EWSW[30]), .Y(n5088) );
INVX4TS U1520 ( .A(n4167), .Y(n4165) );
NOR3X6TS U1521 ( .A(n2639), .B(n2638), .C(n1084), .Y(n1083) );
NAND2X2TS U1522 ( .A(n3818), .B(n3263), .Y(n3265) );
AOI21X2TS U1523 ( .A0(n3823), .A1(n3252), .B0(n3251), .Y(n3253) );
NAND2BX1TS U1524 ( .AN(n4163), .B(FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n4724)
);
BUFX3TS U1525 ( .A(n5290), .Y(n5378) );
NAND3X4TS U1526 ( .A(n3888), .B(n1771), .C(n2637), .Y(n1772) );
CLKXOR2X2TS U1527 ( .A(n3672), .B(n3671), .Y(n3715) );
OA22X1TS U1528 ( .A0(n5726), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n5135), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n5158) );
NOR2X1TS U1529 ( .A(n3082), .B(n3106), .Y(n3782) );
NAND2X4TS U1530 ( .A(n3198), .B(n3197), .Y(n3894) );
OAI2BB2XLTS U1531 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n5115), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n5114), .Y(n5116) );
NAND2X1TS U1532 ( .A(n3697), .B(n3696), .Y(n3698) );
NAND2XLTS U1533 ( .A(n3665), .B(n3664), .Y(n3667) );
NAND2X1TS U1534 ( .A(n3670), .B(n3669), .Y(n3671) );
OAI2BB2XLTS U1535 ( .B0(n5113), .B1(n5121), .A0N(n5112), .A1N(n5111), .Y(
n5117) );
NOR2X6TS U1536 ( .A(n3529), .B(n3528), .Y(n3814) );
NOR2X6TS U1537 ( .A(n2643), .B(n2640), .Y(n1771) );
OAI21X2TS U1538 ( .A0(n3675), .A1(n3674), .B0(n3673), .Y(n3680) );
NAND2BX1TS U1539 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n5082) );
NAND2X1TS U1540 ( .A(n4215), .B(n4241), .Y(n4402) );
NAND2X2TS U1541 ( .A(n3252), .B(n3820), .Y(n3240) );
NOR2X1TS U1542 ( .A(n5244), .B(FPADDSUB_intDX_EWSW[29]), .Y(n5086) );
NAND2X2TS U1543 ( .A(n3757), .B(n3756), .Y(n3758) );
NAND2BX2TS U1544 ( .AN(n3360), .B(n3361), .Y(n3362) );
NAND2X2TS U1545 ( .A(n3661), .B(n3673), .Y(n3662) );
BUFX3TS U1546 ( .A(n4395), .Y(n5290) );
CMPR32X2TS U1547 ( .A(n3599), .B(n3277), .C(n3276), .CO(n3844), .S(n3286) );
NAND2X4TS U1548 ( .A(n3503), .B(n3502), .Y(n3727) );
NOR2X1TS U1549 ( .A(n5818), .B(FPADDSUB_intDX_EWSW[25]), .Y(n5142) );
BUFX6TS U1550 ( .A(n2640), .Y(n2638) );
INVX6TS U1551 ( .A(n3817), .Y(n3252) );
NAND2X2TS U1552 ( .A(n3476), .B(n3475), .Y(n3722) );
NAND2X4TS U1553 ( .A(n3098), .B(n3097), .Y(n3942) );
NOR2X1TS U1554 ( .A(n5817), .B(FPADDSUB_intDX_EWSW[17]), .Y(n5128) );
INVX3TS U1555 ( .A(n3941), .Y(n927) );
NAND2X4TS U1556 ( .A(n1737), .B(n1736), .Y(n2641) );
NAND2X1TS U1557 ( .A(n1891), .B(n3751), .Y(n3752) );
INVX2TS U1558 ( .A(n3755), .Y(n3757) );
INVX2TS U1559 ( .A(n3602), .Y(n3695) );
NOR2X1TS U1560 ( .A(n4252), .B(n5644), .Y(n4268) );
CLKINVX1TS U1561 ( .A(n3676), .Y(n3678) );
NAND2X2TS U1562 ( .A(n1769), .B(n1768), .Y(n2644) );
NOR2X2TS U1563 ( .A(n3820), .B(n3819), .Y(n3821) );
INVX4TS U1564 ( .A(operation[1]), .Y(n4395) );
NAND2X2TS U1565 ( .A(n3885), .B(n3887), .Y(n3748) );
CLKBUFX2TS U1566 ( .A(n5869), .Y(n1030) );
CLKINVX2TS U1567 ( .A(n3738), .Y(n3740) );
NOR2X6TS U1568 ( .A(n3098), .B(n3097), .Y(n3941) );
NAND2X6TS U1569 ( .A(n1709), .B(n1710), .Y(n3885) );
BUFX3TS U1570 ( .A(n4039), .Y(n5189) );
BUFX3TS U1571 ( .A(n4041), .Y(n5188) );
XOR2X2TS U1572 ( .A(n3547), .B(n3546), .Y(n3565) );
INVX6TS U1573 ( .A(n1086), .Y(n1085) );
CMPR32X2TS U1574 ( .A(n3004), .B(n3003), .C(n3002), .CO(n3039), .S(n3007) );
NAND2X1TS U1575 ( .A(n1775), .B(n1774), .Y(n1780) );
INVX2TS U1576 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .Y(n3510) );
OA22X1TS U1577 ( .A0(n5723), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n5114), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n5119) );
NAND2X1TS U1578 ( .A(n3506), .B(n3505), .Y(n3508) );
INVX2TS U1579 ( .A(n3560), .Y(n3184) );
AND2X2TS U1580 ( .A(n4451), .B(n3986), .Y(FPMULT_FSM_exp_operation_A_S) );
XOR2X1TS U1581 ( .A(n3524), .B(n3523), .Y(n3530) );
NOR2X6TS U1582 ( .A(n2593), .B(n2592), .Y(n3675) );
BUFX12TS U1583 ( .A(n3889), .Y(n1086) );
NAND2X1TS U1584 ( .A(n1765), .B(n1764), .Y(n1781) );
INVX2TS U1585 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .Y(n3499) );
NOR2X4TS U1586 ( .A(n3181), .B(n3180), .Y(n3533) );
NOR2X1TS U1587 ( .A(n3020), .B(n989), .Y(n3227) );
NAND2X1TS U1588 ( .A(n3486), .B(n3517), .Y(n3487) );
NAND2X1TS U1589 ( .A(n1728), .B(n1744), .Y(n1729) );
NAND2X1TS U1590 ( .A(n3522), .B(n3569), .Y(n3523) );
XOR2X1TS U1591 ( .A(n4223), .B(n4222), .Y(n4246) );
NOR2X4TS U1592 ( .A(n1628), .B(n1627), .Y(n3766) );
NOR2X6TS U1593 ( .A(n2595), .B(n2594), .Y(n3676) );
NAND2X2TS U1594 ( .A(n2454), .B(n2453), .Y(n3653) );
NOR2X2TS U1595 ( .A(n4049), .B(n5667), .Y(n4055) );
XNOR2X1TS U1596 ( .A(n2395), .B(n2394), .Y(n3255) );
CMPR32X2TS U1597 ( .A(n2627), .B(n2626), .C(n2625), .CO(n2974), .S(n2987) );
NAND2X1TS U1598 ( .A(n1732), .B(n1731), .Y(n1758) );
INVX6TS U1599 ( .A(n2347), .Y(n2593) );
OA21XLTS U1600 ( .A0(n1190), .A1(n4218), .B0(n5497), .Y(n4223) );
NAND2XLTS U1601 ( .A(n3345), .B(n3344), .Y(n3346) );
NAND2X1TS U1602 ( .A(n3496), .B(n3495), .Y(n3497) );
NAND2X1TS U1603 ( .A(n3483), .B(n3518), .Y(n3468) );
AO21X2TS U1604 ( .A0(n3062), .A1(n1038), .B0(n3081), .Y(n3026) );
INVX2TS U1605 ( .A(n3548), .Y(n3550) );
OAI21X2TS U1606 ( .A0(n4853), .A1(n4850), .B0(n4851), .Y(n4995) );
XNOR2X2TS U1607 ( .A(n3494), .B(n3338), .Y(FPMULT_Sgf_operation_Result[8])
);
OAI21X2TS U1608 ( .A0(n2418), .A1(n2417), .B0(n2416), .Y(n2419) );
NOR2X4TS U1609 ( .A(n2413), .B(n2417), .Y(n2420) );
CMPR32X2TS U1610 ( .A(n3019), .B(n3018), .C(n3017), .CO(n3578), .S(n3543) );
INVX2TS U1611 ( .A(n2873), .Y(n3049) );
INVX2TS U1612 ( .A(n3466), .Y(n2905) );
INVX2TS U1613 ( .A(n2839), .Y(n2889) );
CMPR32X2TS U1614 ( .A(n3221), .B(n3220), .C(n3219), .CO(n3222), .S(n3577) );
CLKINVX2TS U1615 ( .A(n4509), .Y(n3442) );
NAND2X1TS U1616 ( .A(n3493), .B(n3337), .Y(n3338) );
NAND2X1TS U1617 ( .A(n1715), .B(n1746), .Y(n1700) );
NAND2X1TS U1618 ( .A(n1145), .B(n3462), .Y(n1144) );
CLKXOR2X2TS U1619 ( .A(n3435), .B(n1141), .Y(n3422) );
NAND2X2TS U1620 ( .A(n1435), .B(n1434), .Y(n3352) );
NAND2X2TS U1621 ( .A(n1483), .B(n1482), .Y(n3357) );
NAND2X2TS U1622 ( .A(n2373), .B(n2416), .Y(n2374) );
NAND2X2TS U1623 ( .A(n1573), .B(n1582), .Y(n1574) );
XOR2X1TS U1624 ( .A(n3418), .B(n3428), .Y(n3423) );
CMPR32X2TS U1625 ( .A(n3109), .B(n3108), .C(n3107), .CO(n3110), .S(n3127) );
CLKINVX2TS U1626 ( .A(n3106), .Y(n3128) );
AO21X1TS U1627 ( .A0(n3032), .A1(n3031), .B0(n3030), .Y(n3219) );
OAI21X2TS U1628 ( .A0(n2864), .A1(n3426), .B0(n2863), .Y(n2898) );
NAND2X2TS U1629 ( .A(n1699), .B(n1698), .Y(n1746) );
NOR2X2TS U1630 ( .A(n3466), .B(n3467), .Y(n3516) );
NAND2X2TS U1631 ( .A(n3485), .B(n3484), .Y(n3517) );
CMPR32X2TS U1632 ( .A(n1950), .B(n1949), .C(n1948), .CO(n2625), .S(n1943) );
INVX2TS U1633 ( .A(n1674), .Y(n1620) );
INVX8TS U1634 ( .A(n1137), .Y(n1713) );
AOI21X1TS U1635 ( .A0(n5475), .A1(n5476), .B0(n5477), .Y(n4201) );
INVX4TS U1636 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1027) );
OAI22X2TS U1637 ( .A0(n2912), .A1(n3278), .B0(n2911), .B1(n2809), .Y(n2908)
);
CLKINVX2TS U1638 ( .A(n1584), .Y(n1573) );
NAND2X1TS U1639 ( .A(n3465), .B(n1134), .Y(n1145) );
NOR2X1TS U1640 ( .A(n4854), .B(n4856), .Y(n4859) );
NAND2X2TS U1641 ( .A(n2418), .B(n2358), .Y(n2345) );
XNOR2X1TS U1642 ( .A(n2815), .B(n3079), .Y(n2845) );
XNOR2X1TS U1643 ( .A(n3037), .B(n3079), .Y(n2828) );
NAND2X2TS U1644 ( .A(n2414), .B(n2358), .Y(n2360) );
OAI21X1TS U1645 ( .A0(n3463), .A1(n3462), .B0(n3461), .Y(n3464) );
CMPR32X2TS U1646 ( .A(n3123), .B(n3122), .C(n3121), .CO(n3126), .S(n3151) );
CMPR32X2TS U1647 ( .A(n3159), .B(n3158), .C(n3157), .CO(n3150), .S(n3175) );
CLKINVX6TS U1648 ( .A(n3467), .Y(n2817) );
INVX2TS U1649 ( .A(n2953), .Y(n3073) );
NAND2X1TS U1650 ( .A(n2349), .B(n2348), .Y(n2384) );
NAND2X1TS U1651 ( .A(n4869), .B(n4844), .Y(n4854) );
NAND2X2TS U1652 ( .A(n2570), .B(n2569), .Y(n3549) );
NAND2X2TS U1653 ( .A(n1480), .B(n1477), .Y(n1422) );
NOR2BX2TS U1654 ( .AN(n2947), .B(n2948), .Y(n2864) );
INVX4TS U1655 ( .A(n2413), .Y(n2358) );
NOR2X6TS U1656 ( .A(n1674), .B(n1677), .Y(n1743) );
NAND2X2TS U1657 ( .A(n2437), .B(n2436), .Y(n2438) );
NAND2X2TS U1658 ( .A(n2447), .B(n2446), .Y(n2448) );
XNOR2X1TS U1659 ( .A(n2844), .B(n3079), .Y(n2887) );
XNOR2X2TS U1660 ( .A(n2815), .B(n3143), .Y(n3057) );
AOI21X1TS U1661 ( .A0(n1183), .A1(n1672), .B0(n1671), .Y(n1704) );
BUFX6TS U1662 ( .A(n2768), .Y(n995) );
CMPR32X2TS U1663 ( .A(n1910), .B(n1909), .C(n1908), .CO(n1925), .S(n1915) );
OR2X2TS U1664 ( .A(n3425), .B(n3426), .Y(n1134) );
NAND2X4TS U1665 ( .A(n2344), .B(n2343), .Y(n2418) );
NOR2X6TS U1666 ( .A(n1662), .B(n1663), .Y(n1677) );
NOR2X6TS U1667 ( .A(n2344), .B(n2343), .Y(n2413) );
NAND2X6TS U1668 ( .A(n2768), .B(n2775), .Y(n2776) );
INVX2TS U1669 ( .A(n2445), .Y(n2447) );
NOR2X1TS U1670 ( .A(n4828), .B(n4811), .Y(n4813) );
OAI22X1TS U1671 ( .A0(n1914), .A1(n1932), .B0(n1921), .B1(n1931), .Y(n1922)
);
NAND2X2TS U1672 ( .A(n1328), .B(n1327), .Y(n3345) );
ADDHX1TS U1673 ( .A(n1883), .B(n1882), .CO(n1916), .S(n1884) );
XNOR2X2TS U1674 ( .A(n3104), .B(n988), .Y(n2809) );
NOR2X4TS U1675 ( .A(n2445), .B(n2435), .Y(n2414) );
NOR2X1TS U1676 ( .A(n5498), .B(n4229), .Y(n4197) );
BUFX6TS U1677 ( .A(n2787), .Y(n1038) );
NAND2XLTS U1678 ( .A(n3146), .B(n1095), .Y(n3162) );
NOR2BX1TS U1679 ( .AN(n3166), .B(n2787), .Y(n3144) );
NAND2X1TS U1680 ( .A(n2778), .B(n2796), .Y(n2779) );
INVX2TS U1681 ( .A(n3079), .Y(n3081) );
NOR2X2TS U1682 ( .A(n3412), .B(n3411), .Y(n3429) );
NAND2X1TS U1683 ( .A(n1530), .B(n1529), .Y(n1624) );
BUFX8TS U1684 ( .A(n2874), .Y(n2972) );
INVX2TS U1685 ( .A(n1582), .Y(n1125) );
OA21XLTS U1686 ( .A0(n1371), .A1(n1433), .B0(n1118), .Y(n1117) );
OAI21X2TS U1687 ( .A0(n2827), .A1(n2800), .B0(n2799), .Y(n2802) );
NAND2X2TS U1688 ( .A(n2574), .B(n2573), .Y(n2575) );
XNOR2X2TS U1689 ( .A(n2630), .B(n1913), .Y(n1921) );
INVX6TS U1690 ( .A(n3847), .Y(n988) );
OAI22X1TS U1691 ( .A0(n3224), .A1(n2744), .B0(n3028), .B1(n2930), .Y(n2923)
);
XNOR2X2TS U1692 ( .A(n3119), .B(n3118), .Y(n3397) );
NAND2X4TS U1693 ( .A(n2312), .B(n2311), .Y(n2461) );
NAND2X4TS U1694 ( .A(n1523), .B(n1522), .Y(n1583) );
NOR2X4TS U1695 ( .A(n1523), .B(n1522), .Y(n1579) );
INVX2TS U1696 ( .A(n3368), .Y(n3078) );
INVX2TS U1697 ( .A(n1938), .Y(n2631) );
NAND2X2TS U1698 ( .A(n1571), .B(n1572), .Y(n1582) );
NAND2X2TS U1699 ( .A(n1475), .B(n1474), .Y(n1525) );
INVX6TS U1700 ( .A(n2460), .Y(n929) );
BUFX16TS U1701 ( .A(n3099), .Y(n3079) );
INVX2TS U1702 ( .A(n3495), .Y(n2534) );
BUFX8TS U1703 ( .A(n2706), .Y(n3278) );
OR2X1TS U1704 ( .A(n3390), .B(n3391), .Y(n3400) );
NAND2X2TS U1705 ( .A(n1258), .B(n1257), .Y(n3332) );
BUFX3TS U1706 ( .A(n3166), .Y(n1057) );
XNOR2X2TS U1707 ( .A(n1162), .B(n1934), .Y(n1887) );
XNOR2X2TS U1708 ( .A(n1934), .B(n1936), .Y(n1894) );
XNOR2X2TS U1709 ( .A(n1934), .B(n2630), .Y(n1858) );
OR2X6TS U1710 ( .A(n1418), .B(n1417), .Y(n1480) );
NOR2X1TS U1711 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n3623) );
NAND2X4TS U1712 ( .A(n2728), .B(n2727), .Y(n3224) );
CLKINVX6TS U1713 ( .A(n1477), .Y(n1478) );
NAND2X1TS U1714 ( .A(n2678), .B(n2746), .Y(n2695) );
NAND2X2TS U1715 ( .A(n3369), .B(n3368), .Y(n3380) );
OAI22X2TS U1716 ( .A0(n2928), .A1(n2834), .B0(n2804), .B1(n1068), .Y(n2838)
);
NAND2BXLTS U1717 ( .AN(n1834), .B(n1934), .Y(n1892) );
BUFX16TS U1718 ( .A(n1865), .Y(n1931) );
NAND2X2TS U1719 ( .A(n2531), .B(n2530), .Y(n3337) );
XOR2X1TS U1720 ( .A(n2871), .B(n2870), .Y(n2872) );
CLKXOR2X2TS U1721 ( .A(n3378), .B(n3377), .Y(n4609) );
BUFX3TS U1722 ( .A(n1642), .Y(n1092) );
OR2X6TS U1723 ( .A(n2271), .B(n2270), .Y(n2556) );
CMPR32X2TS U1724 ( .A(n2339), .B(n2338), .C(n2337), .CO(n2368), .S(n2341) );
NOR2X1TS U1725 ( .A(n2761), .B(n2769), .Y(n2760) );
NOR3X1TS U1726 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[19]), .C(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(
n4139) );
NAND2X1TS U1727 ( .A(n2680), .B(n2683), .Y(n2656) );
NOR2X1TS U1728 ( .A(n926), .B(n921), .Y(n2366) );
NAND2X1TS U1729 ( .A(n1876), .B(n1875), .Y(n1877) );
NAND2X1TS U1730 ( .A(n3625), .B(n3624), .Y(n4138) );
OAI21X2TS U1731 ( .A0(n2686), .A1(n2679), .B0(n2810), .Y(n2657) );
XOR2X2TS U1732 ( .A(n2770), .B(n2758), .Y(n2772) );
ADDFHX2TS U1733 ( .A(n1496), .B(n1495), .CI(n1494), .CO(n1569), .S(n1519) );
XNOR2X2TS U1734 ( .A(n2791), .B(n2783), .Y(n2786) );
XOR2X2TS U1735 ( .A(n1433), .B(n1237), .Y(n1258) );
CMPR32X2TS U1736 ( .A(n2331), .B(n2330), .C(n2329), .CO(n2370), .S(n2328) );
CMPR32X2TS U1737 ( .A(n2158), .B(n2157), .C(n2156), .CO(n2337), .S(n2160) );
AO22XLTS U1738 ( .A0(n1403), .A1(n5591), .B0(n1350), .B1(n5568), .Y(n1692)
);
CMPR32X2TS U1739 ( .A(n1658), .B(n1657), .C(n1656), .CO(n1694), .S(n1643) );
NOR2X1TS U1740 ( .A(FPADDSUB_Raw_mant_NRM_SWR[22]), .B(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3624) );
NAND2X1TS U1741 ( .A(n1814), .B(n1859), .Y(n1820) );
CLKINVX3TS U1742 ( .A(n2728), .Y(n2729) );
NAND2X1TS U1743 ( .A(n2497), .B(n2496), .Y(n2498) );
NAND2XLTS U1744 ( .A(n1243), .B(n1281), .Y(n1246) );
NAND2X2TS U1745 ( .A(n3367), .B(n3117), .Y(n3365) );
BUFX6TS U1746 ( .A(n2726), .Y(n2727) );
OAI21X2TS U1747 ( .A0(n3322), .A1(n3319), .B0(n3320), .Y(n2499) );
NAND2X2TS U1748 ( .A(n3142), .B(n3141), .Y(n3388) );
ADDHX1TS U1749 ( .A(n1689), .B(n1794), .CO(n1722), .S(n1687) );
AOI21X2TS U1750 ( .A0(n1873), .A1(n1872), .B0(n1871), .Y(n1874) );
CMPR32X2TS U1751 ( .A(n1590), .B(n1589), .C(n1588), .CO(n1639), .S(n1617) );
OR2X4TS U1752 ( .A(n2929), .B(DP_OP_496J311_122_3540_n1138), .Y(n2777) );
NAND2X2TS U1753 ( .A(n1861), .B(n1860), .Y(n1864) );
CMPR32X2TS U1754 ( .A(n1416), .B(n1415), .C(n1414), .CO(n1436), .S(n1361) );
CMPR32X2TS U1755 ( .A(n1500), .B(n1499), .C(n1498), .CO(n1537), .S(n1518) );
INVX2TS U1756 ( .A(n1598), .Y(n1657) );
CLKBUFX2TS U1757 ( .A(n1850), .Y(n1860) );
NOR2X1TS U1758 ( .A(n987), .B(n1534), .Y(n1590) );
NAND2X1TS U1759 ( .A(n2865), .B(n2868), .Y(n2666) );
INVX2TS U1760 ( .A(n2813), .Y(n2686) );
NAND2X1TS U1761 ( .A(n2722), .B(n2721), .Y(n2723) );
OAI21X2TS U1762 ( .A0(n2770), .A1(n2758), .B0(n2761), .Y(n1065) );
NAND2X1TS U1763 ( .A(n1250), .B(n1249), .Y(n1251) );
BUFX12TS U1764 ( .A(n2725), .Y(n2921) );
OAI21X2TS U1765 ( .A0(n1248), .A1(n3325), .B0(n1249), .Y(n1222) );
OAI22X1TS U1766 ( .A0(n1660), .A1(n1540), .B0(n1661), .B1(n1609), .Y(n1538)
);
OAI22X2TS U1767 ( .A0(n2202), .A1(n2335), .B0(n2175), .B1(n2364), .Y(n2151)
);
ADDFX2TS U1768 ( .A(DP_OP_496J311_122_3540_n1476), .B(
DP_OP_496J311_122_3540_n1465), .CI(n2762), .CO(n2769), .S(n2782) );
OAI22X1TS U1769 ( .A0(n1660), .A1(n1609), .B0(n987), .B1(n1540), .Y(n1593)
);
CMPR32X2TS U1770 ( .A(n1459), .B(n1458), .C(n1457), .CO(n1488), .S(n1460) );
CMPR32X2TS U1771 ( .A(n2061), .B(n2060), .C(n2059), .CO(n2110), .S(n2064) );
CLKINVX2TS U1772 ( .A(n2509), .Y(n2129) );
CLKINVX2TS U1773 ( .A(n1536), .Y(n1594) );
NOR2X1TS U1774 ( .A(n987), .B(n1609), .Y(n1654) );
NOR2X1TS U1775 ( .A(n986), .B(n1503), .Y(n1541) );
OAI21X2TS U1776 ( .A0(n1450), .A1(n1449), .B0(n1448), .Y(n1122) );
BUFX3TS U1777 ( .A(n1614), .Y(n1078) );
INVX2TS U1778 ( .A(n1836), .Y(n1876) );
INVX2TS U1779 ( .A(n1827), .Y(n1872) );
BUFX6TS U1780 ( .A(n2753), .Y(n2850) );
OAI2BB2X1TS U1781 ( .B0(n985), .B1(n1610), .A0N(n1287), .A1N(n1610), .Y(
n1595) );
NAND2X2TS U1782 ( .A(n1280), .B(n1279), .Y(n1306) );
INVX2TS U1783 ( .A(n958), .Y(n1000) );
NOR2X1TS U1784 ( .A(DP_OP_497J311_123_1725_n367), .B(
DP_OP_497J311_123_1725_n634), .Y(n1374) );
NAND2X1TS U1785 ( .A(n5616), .B(DP_OP_496J311_122_3540_n1097), .Y(n2700) );
NOR2X2TS U1786 ( .A(n2486), .B(n2485), .Y(n2521) );
OR2X2TS U1787 ( .A(FPMULT_Op_MX[20]), .B(DP_OP_496J311_122_3540_n1514), .Y(
n1825) );
NAND2X2TS U1788 ( .A(n2233), .B(n2232), .Y(n2527) );
NOR2BX2TS U1789 ( .AN(n1828), .B(DP_OP_496J311_122_3540_n1515), .Y(n1827) );
INVX2TS U1790 ( .A(n1719), .Y(n987) );
INVX4TS U1791 ( .A(n1852), .Y(n2665) );
INVX2TS U1792 ( .A(n1719), .Y(n986) );
ADDFX2TS U1793 ( .A(n1360), .B(n1359), .CI(n1358), .CO(n1391), .S(n1331) );
CLKXOR2X2TS U1794 ( .A(n2881), .B(n2763), .Y(n1070) );
NOR2X1TS U1795 ( .A(DP_OP_498J311_124_1725_n634), .B(
DP_OP_498J311_124_1725_n641), .Y(n2149) );
INVX6TS U1796 ( .A(n1403), .Y(n1660) );
NOR2X1TS U1797 ( .A(DP_OP_498J311_124_1725_n722), .B(
DP_OP_498J311_124_1725_n728), .Y(n2122) );
NAND2X1TS U1798 ( .A(FPMULT_Op_MX[20]), .B(DP_OP_496J311_122_3540_n1514),
.Y(n1823) );
INVX2TS U1799 ( .A(n1350), .Y(n1032) );
INVX3TS U1800 ( .A(n1765), .Y(n1551) );
NOR2X2TS U1801 ( .A(n1354), .B(n1333), .Y(n3314) );
NAND2X2TS U1802 ( .A(n1354), .B(n1333), .Y(n3315) );
CLKINVX2TS U1803 ( .A(n2688), .Y(n2692) );
NAND2X2TS U1804 ( .A(n1154), .B(n1152), .Y(n2255) );
CLKINVX6TS U1805 ( .A(n959), .Y(n930) );
INVX6TS U1806 ( .A(n2336), .Y(n1039) );
INVX4TS U1807 ( .A(n958), .Y(n999) );
BUFX6TS U1808 ( .A(n2175), .Y(n2201) );
NAND2X2TS U1809 ( .A(n2672), .B(n1805), .Y(n2673) );
ADDFHX2TS U1810 ( .A(n1441), .B(n1440), .CI(n1439), .CO(n1731), .S(n1706) );
ADDFHX2TS U1811 ( .A(n2213), .B(n2212), .CI(n2211), .CO(n2252), .S(n2238) );
ADDFHX2TS U1812 ( .A(n2091), .B(n2090), .CI(n2089), .CO(n2389), .S(n2378) );
CMPR32X2TS U1813 ( .A(n1319), .B(n1318), .C(n1317), .CO(n1608), .S(n1558) );
CMPR32X2TS U1814 ( .A(n2200), .B(n2199), .C(n2198), .CO(n2192), .S(n2217) );
INVX2TS U1815 ( .A(n1354), .Y(n1399) );
NAND2X1TS U1816 ( .A(n5596), .B(DP_OP_496J311_122_3540_n1103), .Y(n2662) );
NAND2X1TS U1817 ( .A(n2475), .B(n2474), .Y(n3300) );
AND2X2TS U1818 ( .A(n2659), .B(n5599), .Y(n1847) );
NOR2X2TS U1819 ( .A(DP_OP_496J311_122_3540_n1467), .B(
DP_OP_496J311_122_3540_n1456), .Y(n1131) );
XOR2X2TS U1820 ( .A(n2177), .B(n2477), .Y(n1156) );
CLKXOR2X2TS U1821 ( .A(n2197), .B(n2196), .Y(n2218) );
NOR2X2TS U1822 ( .A(n2187), .B(n2335), .Y(n2007) );
ADDFHX2TS U1823 ( .A(n2025), .B(n2024), .CI(n2023), .CO(n2054), .S(n2090) );
ADDHX2TS U1824 ( .A(n1390), .B(n1389), .CO(n1454), .S(n1395) );
ADDFHX2TS U1825 ( .A(n1235), .B(n1234), .CI(n1233), .CO(n1504), .S(n1442) );
ADDFHX2TS U1826 ( .A(n1266), .B(n1265), .CI(n1264), .CO(n1317), .S(n1259) );
ADDFHX2TS U1827 ( .A(n1512), .B(n1511), .CI(n1510), .CO(n1764), .S(n1732) );
CMPR32X2TS U1828 ( .A(DP_OP_498J311_124_1725_n630), .B(n2016), .C(n2015),
.CO(n2068), .S(n2042) );
CMPR32X2TS U1829 ( .A(n1232), .B(DP_OP_497J311_123_1725_n609), .C(n1231),
.CO(n1264), .S(n1235) );
CMPR32X2TS U1830 ( .A(DP_OP_497J311_123_1725_n674), .B(n1509), .C(n1508),
.CO(n1560), .S(n1510) );
CMPR32X2TS U1831 ( .A(n2076), .B(n2075), .C(n2074), .CO(n2080), .S(n2087) );
NOR2X1TS U1832 ( .A(DP_OP_497J311_123_1725_n714), .B(n1165), .Y(n1335) );
ADDFX2TS U1833 ( .A(n2000), .B(n1999), .CI(n1998), .CO(n2043), .S(n2206) );
NOR2X1TS U1834 ( .A(DP_OP_498J311_124_1725_n635), .B(
DP_OP_498J311_124_1725_n641), .Y(n2119) );
INVX6TS U1835 ( .A(n1961), .Y(n2224) );
NAND2X1TS U1836 ( .A(n1277), .B(n5588), .Y(n3311) );
NOR2X1TS U1837 ( .A(n932), .B(n1554), .Y(n1597) );
INVX6TS U1838 ( .A(n1501), .Y(n985) );
CMPR32X2TS U1839 ( .A(n2029), .B(DP_OP_498J311_124_1725_n708), .C(n2028),
.CO(n2050), .S(n2091) );
CLKAND2X2TS U1840 ( .A(n954), .B(n5566), .Y(n1321) );
OR2X1TS U1841 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[0]), .Y(n2650) );
INVX2TS U1842 ( .A(n1273), .Y(n1534) );
INVX2TS U1843 ( .A(n1239), .Y(n1467) );
INVX4TS U1844 ( .A(n1962), .Y(n2335) );
NOR2X6TS U1845 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[4]), .Y(n2731) );
INVX2TS U1846 ( .A(n1240), .Y(n1503) );
INVX4TS U1847 ( .A(n2040), .Y(n2225) );
NOR2X2TS U1848 ( .A(n2094), .B(DP_OP_498J311_124_1725_n640), .Y(n2120) );
NAND2X1TS U1849 ( .A(n5617), .B(DP_OP_496J311_122_3540_n1118), .Y(n2668) );
ADDHX2TS U1850 ( .A(DP_OP_498J311_124_1725_n698), .B(n2027), .CO(n2051), .S(
n2024) );
NAND2X2TS U1851 ( .A(n3372), .B(n3371), .Y(n3373) );
CMPR22X2TS U1852 ( .A(DP_OP_498J311_124_1725_n694), .B(n2017), .CO(n2025),
.S(n2021) );
ADDFHX2TS U1853 ( .A(n2194), .B(n2193), .CI(n2458), .CO(n2219), .S(n2220) );
ADDFHX2TS U1854 ( .A(n1218), .B(n1217), .CI(n1216), .CO(n1384), .S(n1354) );
NOR2X1TS U1855 ( .A(DP_OP_497J311_123_1725_n714), .B(
DP_OP_497J311_123_1725_n719), .Y(n1505) );
NOR2X1TS U1856 ( .A(n5592), .B(n1540), .Y(n1288) );
OR2X6TS U1857 ( .A(FPMULT_Op_MX[5]), .B(DP_OP_496J311_122_3540_n1498), .Y(
n2712) );
CMPR32X2TS U1858 ( .A(n1276), .B(n1530), .C(n1275), .CO(n1303), .S(n1270) );
INVX2TS U1859 ( .A(n1577), .Y(n1289) );
CMPR32X2TS U1860 ( .A(n2173), .B(n2172), .C(n2171), .CO(n2354), .S(n2352) );
NOR2X1TS U1861 ( .A(DP_OP_497J311_123_1725_n715), .B(n1554), .Y(n1507) );
INVX6TS U1862 ( .A(n1964), .Y(n2187) );
NOR2X2TS U1863 ( .A(DP_OP_498J311_124_1725_n722), .B(
DP_OP_498J311_124_1725_n732), .Y(n2005) );
INVX2TS U1864 ( .A(n1401), .Y(n1465) );
NAND2BX1TS U1865 ( .AN(DP_OP_497J311_123_1725_n628), .B(n5565), .Y(n1228) );
NOR2X4TS U1866 ( .A(n2188), .B(DP_OP_498J311_124_1725_n640), .Y(n2013) );
NOR2X2TS U1867 ( .A(DP_OP_498J311_124_1725_n723), .B(
DP_OP_498J311_124_1725_n729), .Y(n2029) );
NOR2X2TS U1868 ( .A(DP_OP_498J311_124_1725_n638), .B(
DP_OP_498J311_124_1725_n640), .Y(n2072) );
NAND2X2TS U1869 ( .A(FPMULT_Op_MX[15]), .B(DP_OP_496J311_122_3540_n1509),
.Y(n1805) );
NOR2X1TS U1870 ( .A(n932), .B(DP_OP_497J311_123_1725_n721), .Y(n1444) );
NOR2X2TS U1871 ( .A(n2095), .B(DP_OP_498J311_124_1725_n641), .Y(n2073) );
ADDHX1TS U1872 ( .A(n1203), .B(n1202), .CO(n1200), .S(n1217) );
NOR2X1TS U1873 ( .A(n2095), .B(DP_OP_498J311_124_1725_n642), .Y(n2015) );
ADDHX1TS U1874 ( .A(DP_OP_497J311_123_1725_n623), .B(n1196), .CO(n1227), .S(
n1201) );
OR2X4TS U1875 ( .A(n932), .B(DP_OP_497J311_123_1725_n628), .Y(n1463) );
NOR2X2TS U1876 ( .A(DP_OP_498J311_124_1725_n725), .B(
DP_OP_498J311_124_1725_n727), .Y(n2027) );
NOR2X1TS U1877 ( .A(DP_OP_497J311_123_1725_n714), .B(
DP_OP_497J311_123_1725_n720), .Y(n1445) );
NOR2X1TS U1878 ( .A(DP_OP_498J311_124_1725_n723), .B(
DP_OP_498J311_124_1725_n732), .Y(n2173) );
NOR2X1TS U1879 ( .A(DP_OP_497J311_123_1725_n714), .B(n1554), .Y(n1553) );
NOR2BX2TS U1880 ( .AN(n5568), .B(n5567), .Y(n1197) );
NOR2X2TS U1881 ( .A(DP_OP_497J311_123_1725_n628), .B(n919), .Y(n1198) );
NOR2X2TS U1882 ( .A(n1224), .B(n919), .Y(n1220) );
INVX2TS U1883 ( .A(n1238), .Y(n1497) );
NOR2X2TS U1884 ( .A(DP_OP_497J311_123_1725_n629), .B(n919), .Y(n1206) );
OAI21X2TS U1885 ( .A0(DP_OP_497J311_123_1725_n378), .A1(
DP_OP_497J311_123_1725_n386), .B0(n910), .Y(n1347) );
NOR2X6TS U1886 ( .A(FPMULT_Op_MX[15]), .B(DP_OP_496J311_122_3540_n1509), .Y(
n2671) );
NAND2X6TS U1887 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[12]), .Y(n2649) );
NOR2X2TS U1888 ( .A(DP_OP_497J311_123_1725_n367), .B(n919), .Y(n1230) );
NOR2X2TS U1889 ( .A(DP_OP_498J311_124_1725_n725), .B(
DP_OP_498J311_124_1725_n730), .Y(n2033) );
OR2X2TS U1890 ( .A(n2698), .B(n954), .Y(n1401) );
NOR2X2TS U1891 ( .A(n1224), .B(DP_OP_497J311_123_1725_n634), .Y(n1229) );
NOR2X2TS U1892 ( .A(n1214), .B(DP_OP_497J311_123_1725_n634), .Y(n1196) );
NOR2X2TS U1893 ( .A(DP_OP_497J311_123_1725_n635), .B(n1214), .Y(n1203) );
INVX4TS U1894 ( .A(n1278), .Y(n1540) );
NOR2X2TS U1895 ( .A(n920), .B(n1554), .Y(n1409) );
NOR2X2TS U1896 ( .A(n960), .B(n5554), .Y(n1205) );
NOR2X1TS U1897 ( .A(DP_OP_497J311_123_1725_n715), .B(n1165), .Y(n1299) );
BUFX8TS U1898 ( .A(DP_OP_498J311_124_1725_n729), .Y(n2026) );
CLKINVX6TS U1899 ( .A(DP_OP_497J311_123_1725_n687), .Y(n1554) );
INVX2TS U1900 ( .A(n1965), .Y(n1959) );
NAND2BX2TS U1901 ( .AN(n5567), .B(n5566), .Y(n1195) );
INVX4TS U1902 ( .A(n1964), .Y(n2226) );
NOR2X4TS U1903 ( .A(n920), .B(DP_OP_497J311_123_1725_n719), .Y(n1356) );
NOR2X2TS U1904 ( .A(n1407), .B(DP_OP_497J311_123_1725_n720), .Y(n1355) );
INVX6TS U1905 ( .A(DP_OP_497J311_123_1725_n685), .Y(n1407) );
INVX6TS U1906 ( .A(DP_OP_498J311_124_1725_n801), .Y(n2189) );
INVX6TS U1907 ( .A(DP_OP_497J311_123_1725_n780), .Y(n1224) );
AND2X4TS U1908 ( .A(n1170), .B(DP_OP_498J311_124_1725_n394), .Y(n1964) );
BUFX12TS U1909 ( .A(n5902), .Y(n2698) );
INVX6TS U1910 ( .A(DP_OP_497J311_123_1725_n779), .Y(n1214) );
CLKINVX6TS U1911 ( .A(n1967), .Y(n1981) );
INVX8TS U1912 ( .A(DP_OP_498J311_124_1725_n788), .Y(n2188) );
BUFX4TS U1913 ( .A(n2071), .Y(n2168) );
NAND2X2TS U1914 ( .A(n5615), .B(DP_OP_496J311_122_3540_n1108), .Y(n2696) );
NAND2X2TS U1915 ( .A(n2733), .B(n2732), .Y(n2734) );
NAND2X4TS U1916 ( .A(n953), .B(n5594), .Y(n2689) );
INVX2TS U1917 ( .A(n2401), .Y(n2150) );
BUFX3TS U1918 ( .A(n2881), .Y(n2852) );
XNOR2X1TS U1919 ( .A(n2784), .B(n2871), .Y(n2670) );
XNOR2X2TS U1920 ( .A(n2976), .B(n2852), .Y(n2737) );
INVX2TS U1921 ( .A(n2348), .Y(n2250) );
NOR2BX1TS U1922 ( .AN(n1000), .B(n2927), .Y(n3117) );
NOR2X2TS U1923 ( .A(n2921), .B(n2702), .Y(n2703) );
NAND2X1TS U1924 ( .A(n5593), .B(n910), .Y(n1285) );
INVX2TS U1925 ( .A(n1504), .Y(n1552) );
BUFX6TS U1926 ( .A(n2202), .Y(n994) );
OAI22X1TS U1927 ( .A0(n3135), .A1(n3165), .B0(n3147), .B1(n3146), .Y(n3159)
);
XOR2X1TS U1928 ( .A(n2949), .B(n3426), .Y(n3087) );
ADDFX2TS U1929 ( .A(n2808), .B(n2807), .CI(n2806), .CO(n2893), .S(n2847) );
NAND2X4TS U1930 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[4]), .Y(n2732) );
INVX2TS U1931 ( .A(n2418), .Y(n2357) );
ADDFHX2TS U1932 ( .A(n2192), .B(n2191), .CI(n2190), .CO(n2261), .S(n2236) );
NAND2X2TS U1933 ( .A(n929), .B(n2461), .Y(n2455) );
XOR2X1TS U1934 ( .A(n2468), .B(n2195), .Y(n2196) );
NOR2XLTS U1935 ( .A(n1854), .B(DP_OP_496J311_122_3540_n778), .Y(n1855) );
ADDFHX2TS U1936 ( .A(n3087), .B(n3086), .CI(n3085), .CO(n3068), .S(n3185) );
NAND2X2TS U1937 ( .A(n3173), .B(n3172), .Y(n3472) );
BUFX4TS U1938 ( .A(n2649), .Y(n2653) );
AOI21X1TS U1939 ( .A0(n3542), .A1(n3483), .B0(n3482), .Y(n3488) );
XNOR2X2TS U1940 ( .A(n1936), .B(n1913), .Y(n1879) );
OAI21XLTS U1941 ( .A0(n4239), .A1(n4238), .B0(n4237), .Y(n4240) );
OAI2BB2X1TS U1942 ( .B0(n1140), .B1(n961), .A0N(n3436), .A1N(n3437), .Y(
n3440) );
OAI21XLTS U1943 ( .A0(n2563), .A1(n2562), .B0(n2561), .Y(n2564) );
NOR2X1TS U1944 ( .A(n3282), .B(n989), .Y(n3849) );
NOR2X4TS U1945 ( .A(n3817), .B(n3819), .Y(n3822) );
OAI21XLTS U1946 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n5114), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n5115) );
NAND2X1TS U1947 ( .A(n1242), .B(n1241), .Y(n1281) );
INVX2TS U1948 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .Y(n3563) );
OAI22X2TS U1949 ( .A0(n1947), .A1(n2629), .B0(n2628), .B1(n2631), .Y(n3033)
);
NAND2X2TS U1950 ( .A(n1362), .B(n1361), .Y(n1419) );
NOR2X1TS U1951 ( .A(DP_OP_497J311_123_1725_n628), .B(
DP_OP_497J311_123_1725_n638), .Y(n1204) );
NOR2X1TS U1952 ( .A(DP_OP_498J311_124_1725_n635), .B(n2189), .Y(n2012) );
NOR2XLTS U1953 ( .A(n5128), .B(FPADDSUB_intDY_EWSW[16]), .Y(n5129) );
BUFX12TS U1954 ( .A(n3674), .Y(n3825) );
NOR2X1TS U1955 ( .A(n2226), .B(n2225), .Y(n2504) );
ADDFX2TS U1956 ( .A(n1945), .B(n1944), .CI(n1943), .CO(n2934), .S(n2903) );
NOR2XLTS U1957 ( .A(n5743), .B(FPADDSUB_DMP_SFG[0]), .Y(n4803) );
INVX4TS U1958 ( .A(n3815), .Y(n1109) );
NAND2X6TS U1959 ( .A(n3202), .B(n3201), .Y(n3793) );
NAND2X1TS U1960 ( .A(n1786), .B(n1785), .Y(n1795) );
INVX2TS U1961 ( .A(n3664), .Y(n3457) );
NAND2X1TS U1962 ( .A(n4252), .B(n5650), .Y(n4271) );
NAND2X1TS U1963 ( .A(n4253), .B(n5649), .Y(n4276) );
OR2X1TS U1964 ( .A(n4459), .B(n4282), .Y(n4286) );
OAI21XLTS U1965 ( .A0(n5889), .A1(n1014), .B0(n4649), .Y(n4650) );
OAI21XLTS U1966 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n5813), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n5127) );
NOR2XLTS U1967 ( .A(n5719), .B(FPADDSUB_DMP_SFG[13]), .Y(n4888) );
OR2X1TS U1968 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n4977) );
XNOR2X2TS U1969 ( .A(n2499), .B(n2498), .Y(n3432) );
CLKXOR2X4TS U1970 ( .A(n3656), .B(n3655), .Y(n3747) );
BUFX3TS U1971 ( .A(n4196), .Y(n4425) );
NAND2X2TS U1972 ( .A(n3233), .B(n3232), .Y(n3841) );
OAI21XLTS U1973 ( .A0(n4459), .A1(n4458), .B0(n4457), .Y(n4460) );
OAI21XLTS U1974 ( .A0(n4459), .A1(n4291), .B0(n4290), .Y(n4292) );
OR2X1TS U1975 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4546), .Y(n964) );
CLKINVX3TS U1976 ( .A(n1013), .Y(n931) );
AOI21X2TS U1977 ( .A0(n4937), .A1(n4936), .B0(n4935), .Y(n4947) );
OAI21XLTS U1978 ( .A0(n5063), .A1(n5052), .B0(n5051), .Y(n5055) );
OAI21XLTS U1979 ( .A0(n5006), .A1(n4854), .B0(n4857), .Y(n4847) );
INVX2TS U1980 ( .A(n938), .Y(n990) );
OAI21XLTS U1981 ( .A0(n5020), .A1(n4828), .B0(n4827), .Y(n4831) );
BUFX4TS U1982 ( .A(n3828), .Y(n1106) );
AOI21X1TS U1983 ( .A0(n4834), .A1(n4154), .B0(n4153), .Y(n4853) );
INVX2TS U1984 ( .A(n3663), .Y(n3788) );
NAND2X1TS U1985 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[20]), .B(add_x_69_n50), .Y(n3997) );
OR2X1TS U1986 ( .A(n1298), .B(n1292), .Y(n3304) );
OR2X1TS U1987 ( .A(n2475), .B(n2474), .Y(n3299) );
NOR2X2TS U1988 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n3617), .Y(n4168) );
BUFX3TS U1989 ( .A(n5372), .Y(n5328) );
BUFX3TS U1990 ( .A(n5425), .Y(n5421) );
NOR2X4TS U1991 ( .A(n4028), .B(n3999), .Y(n4013) );
INVX2TS U1992 ( .A(n5959), .Y(n4506) );
NOR2XLTS U1993 ( .A(add_x_246_A_1_), .B(add_x_246_A_0_), .Y(n4038) );
OR2X1TS U1994 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n4194) );
BUFX3TS U1995 ( .A(n5290), .Y(n5338) );
OAI21X2TS U1996 ( .A0(n3310), .A1(n3373), .B0(n3311), .Y(n3305) );
OR2X1TS U1997 ( .A(n3329), .B(n3328), .Y(n3331) );
CLKINVX3TS U1998 ( .A(n4728), .Y(n5074) );
NOR2X1TS U1999 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n937), .Y(n3986) );
BUFX3TS U2000 ( .A(n5239), .Y(n5240) );
BUFX3TS U2001 ( .A(n5233), .Y(n5226) );
BUFX3TS U2002 ( .A(n5233), .Y(n5228) );
NAND2X2TS U2003 ( .A(n4015), .B(n4014), .Y(add_x_69_n238) );
OAI211XLTS U2004 ( .A0(n1016), .A1(n4447), .B0(n4574), .C0(n4573), .Y(
add_subt_data2[19]) );
OAI211XLTS U2005 ( .A0(n1016), .A1(n4577), .B0(n4576), .C0(n4575), .Y(
add_subt_data2[13]) );
OR2X1TS U2006 ( .A(FPSENCOS_d_ff_Xn[24]), .B(n4508), .Y(
FPSENCOS_first_mux_X[24]) );
OAI211XLTS U2007 ( .A0(n1017), .A1(n5557), .B0(n4588), .C0(n4594), .Y(
add_subt_data2[15]) );
NOR2XLTS U2008 ( .A(Data_1[13]), .B(Data_1[1]), .Y(n5600) );
INVX2TS U2009 ( .A(n917), .Y(add_x_69_n50) );
XNOR2X2TS U2010 ( .A(n3983), .B(n3980), .Y(
FPMULT_Sgf_operation_EVEN1_S_B_14_) );
OR2X1TS U2011 ( .A(FPSENCOS_d_ff_Xn[17]), .B(n4508), .Y(
FPSENCOS_first_mux_X[17]) );
OAI211XLTS U2012 ( .A0(operation[1]), .A1(n4584), .B0(n4583), .C0(n4590),
.Y(add_subt_data2[29]) );
OAI21XLTS U2013 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n5768), .B0(
intadd_1046_CI), .Y(FPSENCOS_sh_exp_y[0]) );
OAI21XLTS U2014 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n865), .B0(n5433), .Y(
n849) );
OAI31X1TS U2015 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[1]), .A2(n5709), .B0(n4304), .Y(n856) );
OR2X2TS U2016 ( .A(n1068), .B(n2877), .Y(n914) );
AND2X2TS U2017 ( .A(n3818), .B(n3252), .Y(n916) );
XNOR2X4TS U2018 ( .A(n3270), .B(n1185), .Y(n917) );
XNOR2X4TS U2019 ( .A(n1802), .B(n1184), .Y(n918) );
NAND2X2TS U2020 ( .A(DP_OP_498J311_124_1725_n786), .B(
DP_OP_498J311_124_1725_n792), .Y(n921) );
XNOR2X4TS U2021 ( .A(DP_OP_498J311_124_1725_n792), .B(
DP_OP_498J311_124_1725_n786), .Y(n922) );
OAI22X1TS U2022 ( .A0(n2202), .A1(n2109), .B0(n2175), .B1(n2146), .Y(n923)
);
BUFX3TS U2023 ( .A(n4396), .Y(n5331) );
NOR2X4TS U2024 ( .A(n5378), .B(n5280), .Y(n4396) );
XNOR2X4TS U2025 ( .A(n3769), .B(n3768), .Y(n924) );
INVX2TS U2026 ( .A(n2472), .Y(n2195) );
INVX2TS U2027 ( .A(n5738), .Y(n4735) );
INVX4TS U2028 ( .A(n5148), .Y(n5233) );
CLKINVX3TS U2029 ( .A(n5233), .Y(n5245) );
AOI32X1TS U2030 ( .A0(n5147), .A1(n5146), .A2(n5145), .B0(n5144), .B1(n5147),
.Y(n5148) );
INVX2TS U2031 ( .A(n3998), .Y(n4018) );
NAND2X2TS U2032 ( .A(n4019), .B(add_x_69_n95), .Y(add_x_69_n94) );
INVX4TS U2033 ( .A(n3981), .Y(n3978) );
CLKBUFX2TS U2034 ( .A(n3956), .Y(n1139) );
INVX2TS U2035 ( .A(n3763), .Y(n3952) );
INVX6TS U2036 ( .A(n3888), .Y(n1084) );
AND2X2TS U2037 ( .A(n4608), .B(n4607), .Y(n4611) );
XOR2X2TS U2038 ( .A(n3944), .B(n3943), .Y(n3954) );
INVX3TS U2039 ( .A(n4605), .Y(n3605) );
OR2X2TS U2040 ( .A(n4606), .B(n4605), .Y(n4608) );
INVX3TS U2041 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .Y(n3604) );
NAND2X4TS U2042 ( .A(n3581), .B(n3580), .Y(n1150) );
NOR2X4TS U2043 ( .A(n3476), .B(n3475), .Y(n3721) );
NAND2X2TS U2044 ( .A(n4703), .B(n4704), .Y(n4373) );
XOR3X2TS U2045 ( .A(n3857), .B(n3856), .C(n3855), .Y(n3858) );
NAND2X2TS U2046 ( .A(n1664), .B(n1675), .Y(n1665) );
INVX2TS U2047 ( .A(n1677), .Y(n1664) );
AOI22X4TS U2048 ( .A0(n5302), .A1(FPADDSUB_LZD_raw_out_EWR[1]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n5247), .Y(n4703) );
ADDFHX2TS U2049 ( .A(n3191), .B(n3190), .CI(n3189), .CO(n3192), .S(n3182) );
INVX2TS U2050 ( .A(n3516), .Y(n3483) );
INVX2TS U2051 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .Y(n3471) );
INVX2TS U2052 ( .A(n3452), .Y(n2899) );
AND2X2TS U2053 ( .A(n938), .B(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
FPADDSUB_formatted_number_W[5]) );
AND2X2TS U2054 ( .A(n938), .B(n5753), .Y(FPADDSUB_formatted_number_W[8]) );
AND2X2TS U2055 ( .A(n938), .B(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
FPADDSUB_formatted_number_W[4]) );
AND2X2TS U2056 ( .A(n938), .B(FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
FPADDSUB_formatted_number_W[2]) );
AND2X2TS U2057 ( .A(n3872), .B(n3874), .Y(n1793) );
AND2X2TS U2058 ( .A(n938), .B(n5749), .Y(FPADDSUB_formatted_number_W[12]) );
AND2X2TS U2059 ( .A(n938), .B(n5752), .Y(FPADDSUB_formatted_number_W[9]) );
INVX2TS U2060 ( .A(n3082), .Y(n3125) );
AND2X2TS U2061 ( .A(n938), .B(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
FPADDSUB_formatted_number_W[6]) );
NAND2X4TS U2062 ( .A(n1418), .B(n1417), .Y(n1477) );
NOR2X2TS U2063 ( .A(n3250), .B(n1185), .Y(n3872) );
INVX4TS U2064 ( .A(n5239), .Y(n5243) );
NOR2X4TS U2065 ( .A(n1362), .B(n1361), .Y(n1421) );
BUFX4TS U2066 ( .A(n4251), .Y(n4456) );
NOR2X4TS U2067 ( .A(n4402), .B(n4250), .Y(n4236) );
INVX4TS U2068 ( .A(n5233), .Y(n5229) );
INVX1TS U2069 ( .A(n4453), .Y(n4283) );
INVX4TS U2070 ( .A(n5233), .Y(n5241) );
INVX4TS U2071 ( .A(n5233), .Y(n5227) );
NAND2X2TS U2072 ( .A(n1895), .B(n1892), .Y(n3751) );
INVX4TS U2073 ( .A(n5233), .Y(n5238) );
ADDFHX2TS U2074 ( .A(n1383), .B(n1382), .CI(n1381), .CO(n1473), .S(n1362) );
NAND2X2TS U2075 ( .A(n1122), .B(n1121), .Y(n1516) );
NOR2X2TS U2076 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n4163), .Y(n3616) );
OAI21X2TS U2077 ( .A0(n4277), .A1(n4271), .B0(n4276), .Y(n4295) );
ADDHX1TS U2078 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n3878), .CO(n4127),
.S(FPMULT_Adder_M_result_A_adder[15]) );
NAND2X2TS U2079 ( .A(n1345), .B(n1344), .Y(n1127) );
CLKMX2X2TS U2080 ( .A(n5000), .B(n4999), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[14]) );
INVX4TS U2081 ( .A(n959), .Y(n926) );
BUFX12TS U2082 ( .A(n2854), .Y(n3031) );
ADDHX2TS U2083 ( .A(n1455), .B(n1454), .CO(n1487), .S(n1451) );
CLKMX2X2TS U2084 ( .A(n5023), .B(n5022), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[7]) );
CLKMX2X2TS U2085 ( .A(n4864), .B(n4863), .S0(n4928), .Y(
FPADDSUB_Raw_mant_SGF[13]) );
CLKMX2X2TS U2086 ( .A(n5035), .B(n5034), .S0(n5071), .Y(
FPADDSUB_Raw_mant_SGF[6]) );
INVX4TS U2087 ( .A(n1018), .Y(n1020) );
CLKMX2X2TS U2088 ( .A(n5045), .B(n5044), .S0(n5071), .Y(
FPADDSUB_Raw_mant_SGF[5]) );
INVX3TS U2089 ( .A(n2679), .Y(n2811) );
INVX4TS U2090 ( .A(n1021), .Y(n1023) );
INVX2TS U2091 ( .A(n1764), .Y(n1550) );
INVX2TS U2092 ( .A(n1608), .Y(n1655) );
INVX3TS U2093 ( .A(n1732), .Y(n1514) );
INVX4TS U2094 ( .A(n1668), .Y(n1398) );
INVX2TS U2095 ( .A(n1774), .Y(n1607) );
INVX2TS U2096 ( .A(n1775), .Y(n1605) );
INVX4TS U2097 ( .A(n1558), .Y(n1606) );
INVX4TS U2098 ( .A(n5259), .Y(n5257) );
OR2X2TS U2099 ( .A(FPSENCOS_d_ff_Xn[10]), .B(n4508), .Y(
FPSENCOS_first_mux_X[10]) );
INVX4TS U2100 ( .A(n1024), .Y(n1026) );
INVX4TS U2101 ( .A(n5259), .Y(n5255) );
OR2X2TS U2102 ( .A(FPSENCOS_d_ff_Xn[12]), .B(n4508), .Y(
FPSENCOS_first_mux_X[12]) );
OR2X2TS U2103 ( .A(FPSENCOS_d_ff_Xn[14]), .B(n4508), .Y(
FPSENCOS_first_mux_X[14]) );
INVX2TS U2104 ( .A(n2548), .Y(n2332) );
OR2X2TS U2105 ( .A(FPSENCOS_d_ff_Xn[13]), .B(n4508), .Y(
FPSENCOS_first_mux_X[13]) );
OR2X2TS U2106 ( .A(FPSENCOS_d_ff_Xn[25]), .B(n4508), .Y(
FPSENCOS_first_mux_X[25]) );
OR2X2TS U2107 ( .A(FPSENCOS_d_ff_Xn[16]), .B(n4508), .Y(
FPSENCOS_first_mux_X[16]) );
OR2X2TS U2108 ( .A(FPSENCOS_d_ff_Xn[20]), .B(n4508), .Y(
FPSENCOS_first_mux_X[20]) );
INVX2TS U2109 ( .A(n1384), .Y(n1453) );
OR2X2TS U2110 ( .A(FPSENCOS_d_ff_Xn[19]), .B(n4508), .Y(
FPSENCOS_first_mux_X[19]) );
BUFX6TS U2111 ( .A(n5397), .Y(n5409) );
OAI21X1TS U2112 ( .A0(n5844), .A1(n931), .B0(n4537), .Y(n4538) );
INVX4TS U2113 ( .A(n4506), .Y(n5302) );
INVX4TS U2114 ( .A(n4728), .Y(n4706) );
INVX4TS U2115 ( .A(n4506), .Y(n5248) );
INVX4TS U2116 ( .A(n4506), .Y(n4501) );
NOR2X2TS U2117 ( .A(n3615), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n4719) );
OAI211X1TS U2118 ( .A0(n5097), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n5095), .C0(
n5094), .Y(n5099) );
OR2X2TS U2119 ( .A(n2458), .B(n2457), .Y(n2459) );
INVX1TS U2120 ( .A(n4219), .Y(n4220) );
INVX2TS U2121 ( .A(n2731), .Y(n2733) );
INVX2TS U2122 ( .A(n1195), .Y(n1202) );
CLKMX2X2TS U2123 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
AND2X2TS U2124 ( .A(n5787), .B(FPADDSUB_DMP_SFG[18]), .Y(n4897) );
AND2X2TS U2125 ( .A(n5795), .B(FPADDSUB_DMP_SFG[20]), .Y(n4935) );
OAI21X2TS U2126 ( .A0(n5684), .A1(n5691), .B0(n5685), .Y(n4058) );
AO22X1TS U2127 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n5835), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n819) );
INVX8TS U2128 ( .A(FPMULT_Op_MY[2]), .Y(n2095) );
INVX4TS U2129 ( .A(n965), .Y(n1011) );
NAND2BX1TS U2130 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n5094) );
OR2X2TS U2131 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n4994) );
OR2X2TS U2132 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n4960) );
XOR2X2TS U2133 ( .A(n4023), .B(n984), .Y(FPMULT_Sgf_operation_Result[19]) );
NAND2X2TS U2134 ( .A(n3977), .B(DP_OP_499J311_125_1651_n84), .Y(
DP_OP_499J311_125_1651_n12) );
NAND2X6TS U2135 ( .A(n3829), .B(n1106), .Y(n4010) );
XNOR2X1TS U2136 ( .A(n4185), .B(n4184), .Y(n4191) );
NOR2X1TS U2137 ( .A(n4025), .B(n4024), .Y(add_x_69_n85) );
INVX8TS U2138 ( .A(n2648), .Y(add_x_69_n69) );
NOR2X4TS U2139 ( .A(n4172), .B(n4173), .Y(n4017) );
NAND2X2TS U2140 ( .A(n4008), .B(n4007), .Y(n4009) );
NAND2X6TS U2141 ( .A(n3957), .B(n3956), .Y(n1149) );
ADDFHX2TS U2142 ( .A(n3955), .B(n3954), .CI(n3953), .CO(n3960), .S(n3959) );
INVX2TS U2143 ( .A(n4181), .Y(n4182) );
NOR2X4TS U2144 ( .A(n3776), .B(n3775), .Y(n3781) );
INVX4TS U2145 ( .A(n3747), .Y(n3803) );
NAND2X2TS U2146 ( .A(n3587), .B(n3586), .Y(n4007) );
INVX2TS U2147 ( .A(n4186), .Y(n4188) );
INVX8TS U2148 ( .A(n2589), .Y(n2590) );
NAND2X6TS U2149 ( .A(n3810), .B(n3809), .Y(n3811) );
INVX4TS U2150 ( .A(n2638), .Y(n1738) );
NAND2X2TS U2151 ( .A(n2645), .B(n2644), .Y(n2646) );
NAND2X2TS U2152 ( .A(n3654), .B(n3653), .Y(n3655) );
OAI21X1TS U2153 ( .A0(n6014), .A1(n4373), .B0(n4728), .Y(
FPADDSUB_Data_array_SWR[1]) );
NAND2X2TS U2154 ( .A(n4703), .B(n4132), .Y(n6027) );
INVX4TS U2155 ( .A(n3704), .Y(n928) );
NAND2X4TS U2156 ( .A(n1628), .B(n1627), .Y(n3767) );
NAND2X4TS U2157 ( .A(n2580), .B(n2579), .Y(n3601) );
NAND2X4TS U2158 ( .A(n3561), .B(n3560), .Y(n3562) );
NAND2X4TS U2159 ( .A(n1087), .B(n1676), .Y(n1666) );
NAND2X6TS U2160 ( .A(n1151), .B(n2228), .Y(n3581) );
AO22X1TS U2161 ( .A0(n5248), .A1(FPADDSUB_LZD_raw_out_EWR[2]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n5462), .Y(
FPADDSUB_shft_value_mux_o_EWR[2]) );
AO22X1TS U2162 ( .A0(n4501), .A1(FPADDSUB_LZD_raw_out_EWR[4]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n5462), .Y(
FPADDSUB_shft_value_mux_o_EWR[4]) );
AO22X1TS U2163 ( .A0(n4501), .A1(FPADDSUB_LZD_raw_out_EWR[3]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n5789), .Y(
FPADDSUB_shft_value_mux_o_EWR[3]) );
BUFX12TS U2164 ( .A(n2434), .Y(n2449) );
NOR2X4TS U2165 ( .A(n1126), .B(n1532), .Y(n3360) );
NAND2X4TS U2166 ( .A(n1126), .B(n1532), .Y(n3361) );
OAI21X1TS U2167 ( .A0(n3866), .A1(n2624), .B0(n2623), .Y(n2636) );
OAI21X1TS U2168 ( .A0(n3244), .A1(n3243), .B0(n3242), .Y(n3249) );
NAND3BX1TS U2169 ( .AN(n4171), .B(n4170), .C(n4169), .Y(
FPADDSUB_LZD_raw_out_EWR[4]) );
OAI21X1TS U2170 ( .A0(n3866), .A1(n1942), .B0(n1941), .Y(n1953) );
CLKMX2X2TS U2171 ( .A(n4958), .B(n4957), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[25]) );
OAI21X1TS U2172 ( .A0(n937), .A1(n4735), .B0(n4462), .Y(
FPMULT_FS_Module_state_next[0]) );
CLKMX2X2TS U2173 ( .A(n4951), .B(n4950), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[24]) );
NAND2X4TS U2174 ( .A(n3358), .B(n3357), .Y(n3359) );
ADDFHX2TS U2175 ( .A(n2940), .B(n2939), .CI(n2938), .CO(n2989), .S(n2946) );
INVX6TS U2176 ( .A(n3576), .Y(n3542) );
NAND2X2TS U2177 ( .A(n3353), .B(n3352), .Y(n3355) );
INVX2TS U2178 ( .A(n3185), .Y(n3091) );
CLKMX2X2TS U2179 ( .A(n4941), .B(n4940), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[23]) );
AOI21X2TS U2180 ( .A0(n4955), .A1(n4954), .B0(n4953), .Y(n4956) );
INVX4TS U2181 ( .A(n1742), .Y(n1715) );
ADDFHX2TS U2182 ( .A(n3115), .B(n3114), .CI(n3113), .CO(n3186), .S(n3189) );
NAND2X2TS U2183 ( .A(n1524), .B(n1583), .Y(n1528) );
CLKMX2X2TS U2184 ( .A(n4930), .B(n4929), .S0(n4928), .Y(
FPADDSUB_Raw_mant_SGF[22]) );
NAND2X6TS U2185 ( .A(n2318), .B(n2317), .Y(n2433) );
OAI21X1TS U2186 ( .A0(n2619), .A1(n2618), .B0(n2617), .Y(n2620) );
NOR2X1TS U2187 ( .A(n3215), .B(n989), .Y(n3283) );
NOR2X4TS U2188 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(n3630), .Y(n4167) );
NOR2X1TS U2189 ( .A(n3846), .B(n989), .Y(n3848) );
CLKMX2X2TS U2190 ( .A(n4902), .B(n4901), .S0(n4928), .Y(
FPADDSUB_Raw_mant_SGF[21]) );
NAND2X6TS U2191 ( .A(n1619), .B(n1618), .Y(n1676) );
ADDFHX2TS U2192 ( .A(n2910), .B(n2909), .CI(n2908), .CO(n3000), .S(n2937) );
NAND2X6TS U2193 ( .A(n3332), .B(n1115), .Y(n3343) );
ADDFHX2TS U2194 ( .A(n2363), .B(n2362), .CI(n2361), .CO(n2372), .S(n2343) );
AND2X2TS U2195 ( .A(n3434), .B(n3433), .Y(n4509) );
NAND2X2TS U2196 ( .A(n3381), .B(n3380), .Y(n3383) );
INVX2TS U2197 ( .A(n3770), .Y(n3760) );
AOI2BB2X1TS U2198 ( .B0(n5239), .B1(n6038), .A0N(FPADDSUB_intDX_EWSW[31]),
.A1N(n5183), .Y(n6039) );
INVX6TS U2199 ( .A(n3425), .Y(n2948) );
NAND2X4TS U2200 ( .A(n3334), .B(n3333), .Y(n1115) );
OR2X2TS U2201 ( .A(n3214), .B(n3213), .Y(n3284) );
CLKMX2X2TS U2202 ( .A(n4910), .B(n4909), .S0(n4928), .Y(
FPADDSUB_Raw_mant_SGF[20]) );
ADDFHX2TS U2203 ( .A(n1926), .B(n1925), .CI(n1924), .CO(n2839), .S(n2873) );
OAI21X1TS U2204 ( .A0(n4425), .A1(n4267), .B0(n4266), .Y(n4270) );
OAI21X1TS U2205 ( .A0(n4459), .A1(n4312), .B0(n4311), .Y(n4313) );
OR2X2TS U2206 ( .A(n6040), .B(FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
FPADDSUB_formatted_number_W[24]) );
OR2X2TS U2207 ( .A(n6040), .B(FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
FPADDSUB_formatted_number_W[27]) );
OR2X2TS U2208 ( .A(n6040), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
FPADDSUB_formatted_number_W[28]) );
OR2X2TS U2209 ( .A(n6040), .B(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
FPADDSUB_formatted_number_W[25]) );
OR2X2TS U2210 ( .A(n6040), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
FPADDSUB_formatted_number_W[29]) );
OR2X2TS U2211 ( .A(n6040), .B(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
FPADDSUB_formatted_number_W[23]) );
AND2X2TS U2212 ( .A(n3753), .B(n3752), .Y(n3770) );
AOI2BB1X1TS U2213 ( .A0N(n6040), .A1N(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
n6041), .Y(FPADDSUB_formatted_number_W[31]) );
NOR3X1TS U2214 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n3613), .Y(n6044) );
AO21X1TS U2215 ( .A0(n2776), .A1(n995), .B0(n3211), .Y(n3285) );
OR2X2TS U2216 ( .A(n6040), .B(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
FPADDSUB_formatted_number_W[26]) );
AOI31X1TS U2217 ( .A0(n5182), .A1(n5181), .A2(n5180), .B0(n5245), .Y(n5183)
);
ADDFHX2TS U2218 ( .A(n1904), .B(n1903), .CI(n1902), .CO(n2953), .S(n3106) );
CLKMX2X2TS U2219 ( .A(n4919), .B(n4918), .S0(n4928), .Y(
FPADDSUB_Raw_mant_SGF[19]) );
OR2X2TS U2220 ( .A(n6052), .B(n4121), .Y(n4125) );
OAI21X1TS U2221 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n3618), .Y(n3619) );
NOR2X4TS U2222 ( .A(n1727), .B(n1726), .Y(n1745) );
INVX3TS U2223 ( .A(n3363), .Y(n3060) );
CLKMX2X2TS U2224 ( .A(n4966), .B(n4965), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[18]) );
OR2X2TS U2225 ( .A(n3819), .B(n948), .Y(n1157) );
ADDFHX2TS U2226 ( .A(n2838), .B(n2837), .CI(n2836), .CO(n2848), .S(n2859) );
OR2X4TS U2227 ( .A(n1326), .B(n1325), .Y(n3342) );
NOR2X1TS U2228 ( .A(n4330), .B(n5635), .Y(n4296) );
NOR2X1TS U2229 ( .A(n4330), .B(n5634), .Y(n4323) );
ADDFHX2TS U2230 ( .A(n2106), .B(n2105), .CI(n2104), .CO(n2139), .S(n2136) );
NOR2X1TS U2231 ( .A(n4453), .B(n5630), .Y(n4254) );
OAI21X1TS U2232 ( .A0(n4699), .A1(n4632), .B0(n4561), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[25]) );
NOR2X1TS U2233 ( .A(n4330), .B(n5636), .Y(n4317) );
NOR2X1TS U2234 ( .A(n1946), .B(n2631), .Y(n2627) );
OAI21X1TS U2235 ( .A0(n4425), .A1(n4424), .B0(n4423), .Y(n4429) );
CLKMX2X2TS U2236 ( .A(n4975), .B(n4974), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[17]) );
AOI31X1TS U2237 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n3634), .A2(n5799),
.B0(n3633), .Y(n3629) );
OAI21X1TS U2238 ( .A0(n4425), .A1(n4349), .B0(n4348), .Y(n4354) );
ADDFHX2TS U2239 ( .A(n1718), .B(n1717), .CI(n1716), .CO(n1727), .S(n1698) );
OAI21X1TS U2240 ( .A0(n4250), .A1(n4344), .B0(n4249), .Y(n4251) );
OR2X2TS U2241 ( .A(n3402), .B(n3401), .Y(n1167) );
NAND2BX1TS U2242 ( .AN(n1057), .B(n2972), .Y(n2950) );
ADDFHX2TS U2243 ( .A(n3386), .B(n3385), .CI(n3384), .CO(n3420), .S(n3404) );
OAI21X1TS U2244 ( .A0(n4632), .A1(n4717), .B0(n4558), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[0]) );
INVX2TS U2245 ( .A(n3166), .Y(n1096) );
NAND2X4TS U2246 ( .A(n1128), .B(n1127), .Y(n1381) );
ADDFHX2TS U2247 ( .A(n1697), .B(n1696), .CI(n1695), .CO(n1716), .S(n1680) );
OAI21X1TS U2248 ( .A0(n4425), .A1(n4410), .B0(n4409), .Y(n4415) );
OAI21X1TS U2249 ( .A0(n4425), .A1(n4402), .B0(n4401), .Y(n4405) );
OAI21X1TS U2250 ( .A0(n1801), .A1(n1800), .B0(n1791), .Y(n1792) );
XNOR2X2TS U2251 ( .A(n1123), .B(n1450), .Y(n1471) );
CLKMX2X2TS U2252 ( .A(n4983), .B(n4982), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[16]) );
OAI21X1TS U2253 ( .A0(n4695), .A1(n4717), .B0(n4541), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[1]) );
NAND2BX1TS U2254 ( .AN(n1834), .B(n1938), .Y(n1835) );
NAND2BX1TS U2255 ( .AN(n1834), .B(n1913), .Y(n1893) );
NAND2BX1TS U2256 ( .AN(n4277), .B(n4276), .Y(n4278) );
XOR2X2TS U2257 ( .A(n1246), .B(n1282), .Y(n1257) );
OAI21X1TS U2258 ( .A0(n4419), .A1(n4342), .B0(n4426), .Y(n4346) );
INVX8TS U2259 ( .A(n2715), .Y(n2976) );
NOR2X1TS U2260 ( .A(n926), .B(n2364), .Y(n2426) );
XOR2X1TS U2261 ( .A(n2774), .B(n2773), .Y(n2775) );
ADDFHX2TS U2262 ( .A(n1685), .B(n1684), .CI(n1683), .CO(n1718), .S(n1695) );
CLKMX2X2TS U2263 ( .A(n4992), .B(n4991), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[15]) );
AO22X1TS U2264 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[21]), .B0(n5270), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(FPSENCOS_mux_sal[21]) );
CLKMX2X2TS U2265 ( .A(n4877), .B(n4876), .S0(n4928), .Y(
FPADDSUB_Raw_mant_SGF[11]) );
AO22X1TS U2266 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[23]), .B0(n5269), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(FPSENCOS_mux_sal[23]) );
CLKMX2X2TS U2267 ( .A(n4849), .B(n4848), .S0(n4928), .Y(
FPADDSUB_Raw_mant_SGF[12]) );
AO22X1TS U2268 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[9]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(FPSENCOS_mux_sal[9]) );
AO22X1TS U2269 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[22]), .B0(n5269), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(FPSENCOS_mux_sal[22]) );
INVX12TS U2270 ( .A(n1069), .Y(n2928) );
NAND2BX1TS U2271 ( .AN(n1000), .B(n1041), .Y(n2876) );
AO22X1TS U2272 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[19]), .B0(n5269), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(FPSENCOS_mux_sal[19]) );
AO22X1TS U2273 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[24]), .B0(n5270), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(FPSENCOS_mux_sal[24]) );
AOI31X1TS U2274 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n3638), .A2(n3623),
.B0(n4721), .Y(n3628) );
AO22X1TS U2275 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[26]), .B0(n5272), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(FPSENCOS_mux_sal[26]) );
AO22X1TS U2276 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[27]), .B0(n5272), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(FPSENCOS_mux_sal[27]) );
AO22X1TS U2277 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[20]), .B0(n5272), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(FPSENCOS_mux_sal[20]) );
AO22X1TS U2278 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[28]), .B0(n5272), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(FPSENCOS_mux_sal[28]) );
AO22X1TS U2279 ( .A0(n5273), .A1(FPSENCOS_d_ff_Yn[29]), .B0(n5272), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(FPSENCOS_mux_sal[29]) );
AO22X1TS U2280 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[17]), .B0(n5269), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(FPSENCOS_mux_sal[17]) );
CLKMX2X2TS U2281 ( .A(n4819), .B(n4818), .S0(n4928), .Y(
FPADDSUB_Raw_mant_SGF[9]) );
CLKMX2X2TS U2282 ( .A(n4833), .B(n4832), .S0(n4928), .Y(
FPADDSUB_Raw_mant_SGF[8]) );
AO22X1TS U2283 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[15]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(FPSENCOS_mux_sal[15]) );
CLKMX2X2TS U2284 ( .A(n5011), .B(n5010), .S0(n5021), .Y(
FPADDSUB_Raw_mant_SGF[10]) );
AO22X1TS U2285 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[11]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(FPSENCOS_mux_sal[11]) );
XNOR2X2TS U2286 ( .A(n2772), .B(n2760), .Y(n2767) );
OAI21X1TS U2287 ( .A0(n4425), .A1(n4099), .B0(n4110), .Y(n4102) );
AO22X1TS U2288 ( .A0(n5273), .A1(FPSENCOS_d_ff_Yn[30]), .B0(n5272), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(FPSENCOS_mux_sal[30]) );
AO22X1TS U2289 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[13]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(FPSENCOS_mux_sal[13]) );
NAND2X2TS U2290 ( .A(n2811), .B(n2810), .Y(n2812) );
OAI21X1TS U2291 ( .A0(n4425), .A1(n4112), .B0(n4111), .Y(n4117) );
AO22X1TS U2292 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[14]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(FPSENCOS_mux_sal[14]) );
AO22X1TS U2293 ( .A0(n5271), .A1(FPSENCOS_d_ff_Yn[25]), .B0(n5272), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(FPSENCOS_mux_sal[25]) );
AO22X1TS U2294 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[18]), .B0(n5269), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(FPSENCOS_mux_sal[18]) );
AO22X1TS U2295 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[10]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(FPSENCOS_mux_sal[10]) );
ADDHX2TS U2296 ( .A(n2007), .B(n2006), .CO(n2099), .S(n2249) );
AO22X1TS U2297 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[16]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(FPSENCOS_mux_sal[16]) );
OR2X4TS U2298 ( .A(n2233), .B(n2232), .Y(n1186) );
OAI21X1TS U2299 ( .A0(n5443), .A1(n5730), .B0(FPSENCOS_cont_var_out[1]), .Y(
n4737) );
AO22X1TS U2300 ( .A0(n5268), .A1(FPSENCOS_d_ff_Yn[12]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(FPSENCOS_mux_sal[12]) );
INVX2TS U2301 ( .A(n3365), .Y(n3366) );
AO22X1TS U2302 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[0]), .B0(n5269), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(FPSENCOS_mux_sal[0]) );
AO22X1TS U2303 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[7]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(FPSENCOS_mux_sal[7]) );
AO22X1TS U2304 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[6]), .B0(n5270), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(FPSENCOS_mux_sal[6]) );
OAI21X1TS U2305 ( .A0(n1427), .A1(n1426), .B0(n1425), .Y(n1428) );
AO22X1TS U2306 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[3]), .B0(n5270), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(FPSENCOS_mux_sal[3]) );
AO22X1TS U2307 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[1]), .B0(n5270), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(FPSENCOS_mux_sal[1]) );
OAI21X1TS U2308 ( .A0(n4741), .A1(n4766), .B0(n4740), .Y(n4742) );
OAI21X1TS U2309 ( .A0(n4766), .A1(n5797), .B0(n4760), .Y(n4761) );
OAI21X1TS U2310 ( .A0(n4766), .A1(n974), .B0(n4765), .Y(n4767) );
XOR2X1TS U2311 ( .A(FPSENCOS_d_ff2_Y[30]), .B(n5463), .Y(
FPSENCOS_sh_exp_y[7]) );
OAI21X1TS U2312 ( .A0(n4766), .A1(n4749), .B0(n4748), .Y(n4750) );
XOR2X1TS U2313 ( .A(FPSENCOS_d_ff2_X[30]), .B(n5466), .Y(
FPSENCOS_sh_exp_x[7]) );
ADDFHX2TS U2314 ( .A(n2219), .B(n2218), .CI(n2217), .CO(n2235), .S(n2232) );
ADDFHX2TS U2315 ( .A(n2216), .B(n2215), .CI(n2214), .CO(n2237), .S(n2233) );
AO22X1TS U2316 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[2]), .B0(n5270), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(FPSENCOS_mux_sal[2]) );
AO22X1TS U2317 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[8]), .B0(n5267), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(FPSENCOS_mux_sal[8]) );
AO22X1TS U2318 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[4]), .B0(n5270), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(FPSENCOS_mux_sal[4]) );
AO22X1TS U2319 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[5]), .B0(n5270), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(FPSENCOS_mux_sal[5]) );
CMPR22X2TS U2320 ( .A(n1595), .B(n1594), .CO(n1645), .S(n1588) );
OAI211X1TS U2321 ( .A0(n1016), .A1(n5548), .B0(n4585), .C0(n4594), .Y(
add_subt_data2[20]) );
OAI211X1TS U2322 ( .A0(n1016), .A1(n4592), .B0(n4591), .C0(n4590), .Y(
add_subt_data2[27]) );
OAI211X1TS U2323 ( .A0(n1017), .A1(n5580), .B0(n4579), .C0(n4578), .Y(
add_subt_data2[16]) );
OAI211X1TS U2324 ( .A0(n1017), .A1(n4448), .B0(n4571), .C0(n4575), .Y(
add_subt_data2[18]) );
OAI211X1TS U2325 ( .A0(n1017), .A1(n5550), .B0(n4595), .C0(n4594), .Y(
add_subt_data2[17]) );
OAI211X1TS U2326 ( .A0(n1016), .A1(n4582), .B0(n4581), .C0(n4580), .Y(
add_subt_data2[14]) );
OAI211X1TS U2327 ( .A0(n1016), .A1(n4587), .B0(n4586), .C0(n4590), .Y(
add_subt_data2[28]) );
OAI211X1TS U2328 ( .A0(n1017), .A1(n4449), .B0(n4572), .C0(n4573), .Y(
add_subt_data2[22]) );
OAI21X1TS U2329 ( .A0(n5770), .A1(n4728), .B0(n4473), .Y(n6019) );
AO22X1TS U2330 ( .A0(n5262), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(FPSENCOS_first_mux_Z[29]) );
AO22X1TS U2331 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(FPSENCOS_first_mux_Z[13]) );
AO22X1TS U2332 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n5264), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(FPSENCOS_first_mux_Z[30]) );
OAI21X1TS U2333 ( .A0(n5465), .A1(n5831), .B0(n5464), .Y(
FPSENCOS_sh_exp_y[5]) );
AO22X1TS U2334 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n979), .B1(n5439),
.Y(n5441) );
AO22X1TS U2335 ( .A0(n5254), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(FPSENCOS_first_mux_Z[12]) );
AO22X1TS U2336 ( .A0(n5254), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(FPSENCOS_first_mux_Z[14]) );
AO22X1TS U2337 ( .A0(n1006), .A1(n4751), .B0(n1009), .B1(n4747), .Y(n4744)
);
AO21X1TS U2338 ( .A0(intadd_1046_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n5465),
.Y(FPSENCOS_sh_exp_y[4]) );
AO22X1TS U2339 ( .A0(n5265), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(FPSENCOS_first_mux_Z[10]) );
AO22X1TS U2340 ( .A0(n4753), .A1(n1006), .B0(n1009), .B1(n4752), .Y(n4754)
);
AO22X1TS U2341 ( .A0(n5263), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n5259), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(FPSENCOS_first_mux_Z[8]) );
OAI21X1TS U2342 ( .A0(n5003), .A1(n4865), .B0(n5001), .Y(n4868) );
XOR2X1TS U2343 ( .A(intadd_1047_n1), .B(n5075), .Y(
FPADDSUB_Shift_amount_EXP_EW[4]) );
AO22X1TS U2344 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(FPSENCOS_first_mux_Z[11]) );
OAI21X1TS U2345 ( .A0(n5006), .A1(n4872), .B0(n4871), .Y(n4875) );
AO22X1TS U2346 ( .A0(n5265), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n5259), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(FPSENCOS_first_mux_Z[6]) );
AO22X1TS U2347 ( .A0(n5254), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(FPSENCOS_first_mux_Z[23]) );
OAI21X1TS U2348 ( .A0(n5429), .A1(n5732), .B0(n5431), .Y(n854) );
OAI21X1TS U2349 ( .A0(n4732), .A1(n4729), .B0(n5731), .Y(n834) );
AO22X1TS U2350 ( .A0(n5254), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n5259), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(FPSENCOS_first_mux_Z[7]) );
NOR2X1TS U2351 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n5464), .Y(n5463) );
NAND3X1TS U2352 ( .A(n5276), .B(n5282), .C(n5275), .Y(n5277) );
OA21X2TS U2353 ( .A0(n1190), .A1(n4204), .B0(n4203), .Y(n4206) );
AO22X1TS U2354 ( .A0(n5263), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n5264), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(FPSENCOS_first_mux_Z[31]) );
OAI21X1TS U2355 ( .A0(n5688), .A1(n4048), .B0(n4047), .Y(n4052) );
AO22X1TS U2356 ( .A0(n5263), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(FPSENCOS_first_mux_Z[28]) );
OAI21X1TS U2357 ( .A0(n4823), .A1(n4820), .B0(n4821), .Y(n4801) );
OAI21X1TS U2358 ( .A0(n5003), .A1(n4836), .B0(n4835), .Y(n4840) );
AO22X1TS U2359 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(FPSENCOS_first_mux_Z[27]) );
AO22X1TS U2360 ( .A0(n5265), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(FPSENCOS_first_mux_Z[26]) );
AO22X1TS U2361 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(FPSENCOS_first_mux_Z[25]) );
OAI21X1TS U2362 ( .A0(n5006), .A1(n5005), .B0(n5004), .Y(n5009) );
AO22X1TS U2363 ( .A0(n5262), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(FPSENCOS_first_mux_Z[24]) );
AND3X2TS U2364 ( .A(n4710), .B(n4709), .C(n4708), .Y(n5747) );
AO22X1TS U2365 ( .A0(n5262), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n5259), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(FPSENCOS_first_mux_Z[9]) );
AOI211X1TS U2366 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n5442), .B0(n5439), .C0(n4564), .Y(FPADDSUB_enable_Pipeline_input) );
AO22X1TS U2367 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(FPSENCOS_first_mux_Z[19]) );
AND2X2TS U2368 ( .A(n1719), .B(n5568), .Y(n1754) );
AO22X1TS U2369 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(FPSENCOS_first_mux_Z[17]) );
OAI21X1TS U2370 ( .A0(n2607), .A1(n2606), .B0(n2605), .Y(n2608) );
INVX3TS U2371 ( .A(n1442), .Y(n1515) );
AO22X1TS U2372 ( .A0(n5262), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(FPSENCOS_first_mux_Z[20]) );
NOR2X1TS U2373 ( .A(FPSENCOS_d_ff2_X[29]), .B(n5467), .Y(n5466) );
OR2X2TS U2374 ( .A(n1786), .B(n1785), .Y(n1797) );
OAI21X1TS U2375 ( .A0(n5734), .A1(n4728), .B0(n4472), .Y(n6025) );
ADDFHX2TS U2376 ( .A(n2334), .B(n2333), .CI(n2332), .CO(n2367), .S(n2329) );
AO22X1TS U2377 ( .A0(n5263), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(FPSENCOS_first_mux_Z[21]) );
AO22X1TS U2378 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(FPSENCOS_first_mux_Z[18]) );
AO22X1TS U2379 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(FPSENCOS_first_mux_Z[16]) );
OAI21X1TS U2380 ( .A0(n5468), .A1(n5832), .B0(n5467), .Y(
FPSENCOS_sh_exp_x[5]) );
AO22X1TS U2381 ( .A0(n5256), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n5260), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(FPSENCOS_first_mux_Z[15]) );
INVX2TS U2382 ( .A(n1786), .Y(n1656) );
AO21X1TS U2383 ( .A0(intadd_1045_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n5468),
.Y(FPSENCOS_sh_exp_x[4]) );
AO22X1TS U2384 ( .A0(n5265), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n5261), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(FPSENCOS_first_mux_Z[22]) );
OAI21X1TS U2385 ( .A0(n4506), .A1(n5825), .B0(n4505), .Y(n6015) );
OAI211X1TS U2386 ( .A0(n1017), .A1(n5523), .B0(n4518), .C0(n4519), .Y(
add_subt_data2[11]) );
OAI211X1TS U2387 ( .A0(n1016), .A1(n4568), .B0(n4567), .C0(n4578), .Y(
add_subt_data2[3]) );
OAI211X1TS U2388 ( .A0(n1017), .A1(n5513), .B0(n4565), .C0(n4580), .Y(
add_subt_data2[5]) );
OAI211X1TS U2389 ( .A0(n1017), .A1(n5514), .B0(n4520), .C0(n4519), .Y(
add_subt_data2[7]) );
NAND2BX1TS U2390 ( .AN(n5284), .B(n5283), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
AO22X1TS U2391 ( .A0(n5258), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n5259), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(FPSENCOS_first_mux_Z[5]) );
OAI21X2TS U2392 ( .A0(n1271), .A1(n1272), .B0(n1270), .Y(n1132) );
AO21X1TS U2393 ( .A0(n4736), .A1(n5280), .B0(FPSENCOS_enab_RB3), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
OAI21X1TS U2394 ( .A0(n5668), .A1(n4069), .B0(n4068), .Y(n4073) );
ADDFHX2TS U2395 ( .A(n1290), .B(n1289), .CI(n1288), .CO(n1342), .S(n1301) );
AO22X1TS U2396 ( .A0(n5258), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n1192), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(FPSENCOS_first_mux_Z[2]) );
AO22X1TS U2397 ( .A0(n5258), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n5259), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(FPSENCOS_first_mux_Z[4]) );
OR2X2TS U2398 ( .A(n863), .B(n5432), .Y(n850) );
AO22X1TS U2399 ( .A0(n5258), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n5264), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(FPSENCOS_first_mux_Z[1]) );
AO22X1TS U2400 ( .A0(n5258), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n5259), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(FPSENCOS_first_mux_Z[3]) );
NOR2X1TS U2401 ( .A(n5660), .B(n4060), .Y(n4062) );
AOI222X1TS U2402 ( .A0(n5462), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n5248), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(
n5074), .Y(n6018) );
AOI222X1TS U2403 ( .A0(n5462), .A1(FPADDSUB_DmP_mant_SHT1_SW[14]), .B0(n4501), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(
n5958), .Y(n6017) );
NAND2X4TS U2404 ( .A(n2693), .B(n2879), .Y(n2747) );
NAND4X1TS U2405 ( .A(n6013), .B(n6012), .C(n6011), .D(n5216), .Y(n5218) );
OR2X2TS U2406 ( .A(n1623), .B(n1622), .Y(n1183) );
ADDFHX2TS U2407 ( .A(n1561), .B(n1560), .CI(n1559), .CO(n1775), .S(n1765) );
ADDFHX2TS U2408 ( .A(n1601), .B(n1600), .CI(n1599), .CO(n1786), .S(n1774) );
AO22X1TS U2409 ( .A0(n5258), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n1192), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(FPSENCOS_first_mux_Z[0]) );
OAI211X1TS U2410 ( .A0(n4778), .A1(n4467), .B0(n4597), .C0(n4466), .Y(
FPMULT_FS_Module_state_next[3]) );
OR2X2TS U2411 ( .A(n1576), .B(n1577), .Y(n1182) );
OAI21X1TS U2412 ( .A0(n5428), .A1(n5732), .B0(n5430), .Y(n859) );
OR2X2TS U2413 ( .A(n2352), .B(n2351), .Y(n1188) );
OAI21X1TS U2414 ( .A0(n5846), .A1(n1014), .B0(n4625), .Y(n4626) );
AND2X2TS U2415 ( .A(n3309), .B(n3377), .Y(FPMULT_Sgf_operation_Result[1]) );
OAI21X1TS U2416 ( .A0(n4515), .A1(n4514), .B0(n4513), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
AND2X2TS U2417 ( .A(n1531), .B(n1624), .Y(n1532) );
AND2X2TS U2418 ( .A(n2720), .B(n2722), .Y(n955) );
OAI21X1TS U2419 ( .A0(n5732), .A1(n5430), .B0(n4305), .Y(n860) );
NOR3X1TS U2420 ( .A(n5711), .B(n5718), .C(n4597), .Y(
FPMULT_FSM_final_result_load) );
NOR2X1TS U2421 ( .A(n4596), .B(n4464), .Y(FPMULT_FSM_first_phase_load) );
OAI21X1TS U2422 ( .A0(n5049), .A1(n5046), .B0(n5047), .Y(n5040) );
ADDFHX2TS U2423 ( .A(n1557), .B(n1556), .CI(n1555), .CO(n1599), .S(n1559) );
NOR2X1TS U2424 ( .A(n4515), .B(n857), .Y(FPSENCOS_ITER_CONT_N5) );
INVX1TS U2425 ( .A(n5274), .Y(n4369) );
NAND2BX1TS U2426 ( .AN(FPMULT_exp_oper_result[0]), .B(n5253), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]) );
INVX2TS U2427 ( .A(n2409), .Y(n2331) );
OAI21X1TS U2428 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n5430), .B0(n4516),
.Y(n862) );
INVX2TS U2429 ( .A(n5433), .Y(n5432) );
NAND2BX1TS U2430 ( .AN(n4098), .B(n4096), .Y(n4093) );
NAND2BX1TS U2431 ( .AN(FPMULT_exp_oper_result[7]), .B(n5253), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]) );
NAND2BX1TS U2432 ( .AN(FPMULT_exp_oper_result[6]), .B(n5253), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]) );
NAND2BX1TS U2433 ( .AN(FPMULT_exp_oper_result[5]), .B(n5253), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]) );
NAND2BX1TS U2434 ( .AN(FPMULT_exp_oper_result[4]), .B(n5253), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]) );
NAND2BX1TS U2435 ( .AN(FPMULT_exp_oper_result[3]), .B(n5253), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]) );
NAND2BX1TS U2436 ( .AN(FPMULT_exp_oper_result[2]), .B(n5253), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]) );
NAND2BX1TS U2437 ( .AN(FPMULT_exp_oper_result[1]), .B(n5253), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]) );
INVX1TS U2438 ( .A(n4719), .Y(n4722) );
NAND3BX1TS U2439 ( .AN(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(n3638), .C(
FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n3639) );
ADDFHX2TS U2440 ( .A(DP_OP_497J311_123_1725_n693), .B(
DP_OP_497J311_123_1725_n683), .CI(n1597), .CO(n1650), .S(n1600) );
AOI222X1TS U2441 ( .A0(n5338), .A1(Data_2[30]), .B0(n4593), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .C0(FPSENCOS_d_ff3_sh_y_out[30]), .C1(
n5077), .Y(n4569) );
AOI222X1TS U2442 ( .A0(n5338), .A1(Data_2[31]), .B0(n4593), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .C0(FPSENCOS_d_ff3_sh_y_out[31]), .C1(
n5077), .Y(n5078) );
BUFX3TS U2443 ( .A(n5331), .Y(n4570) );
BUFX12TS U2444 ( .A(n2718), .Y(n1033) );
NAND2X4TS U2445 ( .A(n2650), .B(n2653), .Y(n958) );
OR2X2TS U2446 ( .A(n3372), .B(n3371), .Y(n1146) );
AOI2BB1X1TS U2447 ( .A0N(n5826), .A1N(underflow_flag_mult), .B0(n5300), .Y(
FPMULT_final_result_ieee_Module_Sign_S_mux) );
INVX2TS U2448 ( .A(n4869), .Y(n4872) );
OR2X2TS U2449 ( .A(n4743), .B(n4768), .Y(n4755) );
ADDFHX2TS U2450 ( .A(n1374), .B(n1373), .CI(n1372), .CO(n1649), .S(n1598) );
NAND3BX1TS U2451 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n4394), .Y(n4513) );
NAND3X1TS U2452 ( .A(n5960), .B(n5428), .C(n5384), .Y(n5283) );
ADDFHX2TS U2453 ( .A(DP_OP_496J311_122_3540_n1515), .B(FPMULT_Op_MX[21]),
.CI(n2687), .CO(n2676), .S(n2693) );
ADDFHX2TS U2454 ( .A(n1447), .B(n1446), .CI(n1445), .CO(n1508), .S(n1440) );
OR2X2TS U2455 ( .A(n1530), .B(n1529), .Y(n1531) );
INVX2TS U2456 ( .A(n5036), .Y(n5049) );
NAND3X1TS U2457 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n4444), .C(n5718),
.Y(n4470) );
AND2X2TS U2458 ( .A(n4731), .B(n4451), .Y(n4792) );
NAND3X1TS U2459 ( .A(n5711), .B(n5718), .C(n4444), .Y(n4729) );
INVX4TS U2460 ( .A(n4766), .Y(n4528) );
AND2X2TS U2461 ( .A(n2459), .B(n2470), .Y(n2579) );
OAI211X2TS U2462 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n5236), .B0(n5119),
.C0(n5104), .Y(n5121) );
OAI21X1TS U2463 ( .A0(n4055), .A1(n4070), .B0(n4054), .Y(n4056) );
NOR2X4TS U2464 ( .A(FPMULT_FSM_selector_C), .B(n5187), .Y(n4053) );
OAI211X2TS U2465 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n5814), .B0(n5158),
.C0(n5124), .Y(n5133) );
NOR2X1TS U2466 ( .A(n5731), .B(n5187), .Y(n4041) );
AO22XLTS U2467 ( .A0(operation[2]), .A1(n5300), .B0(n5301), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
OAI211X1TS U2468 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n5819), .B0(n5108), .C0(
n5111), .Y(n5123) );
AOI2BB2X1TS U2469 ( .B0(n5572), .B1(n5562), .A0N(DP_OP_497J311_123_1725_n336), .A1N(n5562), .Y(n5571) );
AO22X1TS U2470 ( .A0(n1017), .A1(n5076), .B0(n5338), .B1(operation[0]), .Y(
n5080) );
INVX1TS U2471 ( .A(n4071), .Y(n4044) );
OAI21X1TS U2472 ( .A0(n3636), .A1(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(n5801),
.Y(n3637) );
OAI21X1TS U2473 ( .A0(n5688), .A1(n5679), .B0(n4077), .Y(n4078) );
NAND3X1TS U2474 ( .A(n5819), .B(n5108), .C(FPADDSUB_intDX_EWSW[8]), .Y(n5109) );
INVX2TS U2475 ( .A(n5058), .Y(n5060) );
NAND2BX1TS U2476 ( .AN(n4071), .B(n4070), .Y(n4072) );
INVX2TS U2477 ( .A(n4850), .Y(n4852) );
NOR2X1TS U2478 ( .A(n5106), .B(FPADDSUB_intDY_EWSW[10]), .Y(n5107) );
ADDFHX2TS U2479 ( .A(n1322), .B(n1321), .CI(n1320), .CO(n1372), .S(n1318) );
NOR2X4TS U2480 ( .A(n4774), .B(n4738), .Y(n4559) );
AO22X1TS U2481 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n5462), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n816) );
OAI21X1TS U2482 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n5769), .B0(
intadd_1045_CI), .Y(FPSENCOS_sh_exp_x[0]) );
NOR2X1TS U2483 ( .A(n5142), .B(FPADDSUB_intDY_EWSW[24]), .Y(n5081) );
NAND2BX1TS U2484 ( .AN(n5545), .B(n1610), .Y(n1388) );
INVX2TS U2485 ( .A(n5027), .Y(n5030) );
OR2X2TS U2486 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4663), .Y(n963) );
XOR2X1TS U2487 ( .A(add_x_246_A_2_), .B(n4038), .Y(
FPMULT_Adder_M_result_A_adder[2]) );
OAI21X1TS U2488 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n3610), .B0(n4785), .Y(
n3611) );
INVX2TS U2489 ( .A(n5012), .Y(n5025) );
NAND3X1TS U2490 ( .A(n5822), .B(n5082), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n5084) );
OAI21X1TS U2491 ( .A0(n5509), .A1(n4229), .B0(n5500), .Y(n4230) );
OAI21X1TS U2492 ( .A0(n4811), .A1(n4827), .B0(n4810), .Y(n4812) );
NOR2X1TS U2493 ( .A(n5384), .B(n4465), .Y(FPSENCOS_ITER_CONT_N3) );
OAI21X1TS U2494 ( .A0(n4798), .A1(n4821), .B0(n4799), .Y(n4147) );
INVX2TS U2495 ( .A(n5028), .Y(n5029) );
OAI21X1TS U2496 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n5135), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n5136) );
INVX1TS U2497 ( .A(n5195), .Y(n5300) );
OAI21X1TS U2498 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .B0(n5222), .Y(n5220) );
NOR3X2TS U2499 ( .A(FPSENCOS_cont_var_out[1]), .B(n5378), .C(n5730), .Y(
n4566) );
CLKMX2X2TS U2500 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
NOR2X4TS U2501 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4521) );
NOR2X1TS U2502 ( .A(n5715), .B(FPADDSUB_DMP_SFG[11]), .Y(n4883) );
OR2X2TS U2503 ( .A(n5490), .B(n5491), .Y(n4208) );
AO22XLTS U2504 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n5301),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
CLKMX2X2TS U2505 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
CLKMX2X2TS U2506 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
CLKMX2X2TS U2507 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
NOR2X1TS U2508 ( .A(n5774), .B(FPADDSUB_DMP_SFG[15]), .Y(n4892) );
CLKMX2X2TS U2509 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
NAND2BX1TS U2510 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n5108) );
ADDHX2TS U2511 ( .A(FPMULT_Op_MY[7]), .B(DP_OP_496J311_122_3540_n778), .CO(
n2759), .S(n2868) );
NAND2BX1TS U2512 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n5110) );
NOR2X1TS U2513 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n4137) );
OR2X2TS U2514 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n4904) );
OR2X2TS U2515 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n4921) );
OR2X2TS U2516 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n4943) );
NAND2BX1TS U2517 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n5140) );
OAI21X1TS U2518 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n5808), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n5105) );
NAND2BX1TS U2519 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n5124) );
NAND2BX1TS U2520 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n5130) );
OAI21X1TS U2521 ( .A0(n5510), .A1(n5481), .B0(n5482), .Y(n4091) );
OR2X2TS U2522 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n4867) );
NAND2BX1TS U2523 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n5083) );
NOR2X1TS U2524 ( .A(n5793), .B(FPADDSUB_DMP_SFG[21]), .Y(n4946) );
NAND2BX1TS U2525 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n5104) );
INVX16TS U2526 ( .A(n2698), .Y(n932) );
NAND3X1TS U2527 ( .A(n5203), .B(n5202), .C(n5201), .Y(n5873) );
NOR2X1TS U2528 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n4307) );
NAND2BX1TS U2529 ( .AN(Data_2[18]), .B(n5564), .Y(n3989) );
NAND4BX1TS U2530 ( .AN(Data_1[9]), .B(n5531), .C(n4777), .D(n5534), .Y(n5875) );
NOR2X1TS U2531 ( .A(n5513), .B(n5512), .Y(n5521) );
NAND2BX1TS U2532 ( .AN(Data_2[16]), .B(n5522), .Y(n5612) );
NOR2X1TS U2533 ( .A(n5604), .B(n5602), .Y(n5610) );
NOR2X1TS U2534 ( .A(n5557), .B(n5555), .Y(n5556) );
NOR2X1TS U2535 ( .A(n5515), .B(n5534), .Y(n5533) );
NOR2X1TS U2536 ( .A(n5550), .B(n5546), .Y(n5549) );
NOR2X1TS U2537 ( .A(n5525), .B(n5520), .Y(n5524) );
NOR2X1TS U2538 ( .A(n5523), .B(n5536), .Y(n5535) );
NAND2BX1TS U2539 ( .AN(Data_2[18]), .B(n5520), .Y(n5608) );
NOR2X1TS U2540 ( .A(n5560), .B(n5557), .Y(n5576) );
NAND2BX1TS U2541 ( .AN(n5564), .B(Data_1[14]), .Y(n5574) );
NAND4BX1TS U2542 ( .AN(Data_2[16]), .B(n5557), .C(n4582), .D(n5523), .Y(
n5879) );
OAI21X1TS U2543 ( .A0(n3992), .A1(n3991), .B0(n3990), .Y(n5575) );
NOR2X1TS U2544 ( .A(n5518), .B(n5531), .Y(n5530) );
NOR2X1TS U2545 ( .A(n5529), .B(n5527), .Y(n5528) );
NAND3X1TS U2546 ( .A(n4135), .B(n4134), .C(n4133), .Y(n4136) );
NOR2X4TS U2547 ( .A(operation[1]), .B(operation[2]), .Y(n4367) );
NOR2X1TS U2548 ( .A(Data_1[6]), .B(Data_1[0]), .Y(n5538) );
NOR2X1TS U2549 ( .A(Data_2[20]), .B(Data_2[14]), .Y(n5561) );
NOR2X1TS U2550 ( .A(Data_2[5]), .B(Data_2[17]), .Y(n5609) );
NOR2X1TS U2551 ( .A(Data_1[9]), .B(Data_1[3]), .Y(n5539) );
NOR2X1TS U2552 ( .A(Data_2[21]), .B(Data_2[15]), .Y(n5587) );
NOR2X1TS U2553 ( .A(Data_2[13]), .B(Data_2[1]), .Y(n5606) );
ADDHX4TS U2554 ( .A(n2002), .B(n2001), .CO(n2020), .S(n2038) );
XNOR2X4TS U2555 ( .A(n3346), .B(n1114), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[9]) );
OR2X4TS U2556 ( .A(n1258), .B(n1257), .Y(n3333) );
INVX2TS U2557 ( .A(n2494), .Y(n3322) );
NAND2X4TS U2558 ( .A(n2677), .B(n2676), .Y(n2746) );
OAI2BB1X2TS U2559 ( .A0N(n2689), .A1N(n2688), .B0(n2690), .Y(n2674) );
AND2X4TS U2560 ( .A(n1070), .B(n2927), .Y(n1069) );
OAI22X4TS U2561 ( .A0(n2776), .A1(n3211), .B0(n995), .B1(n2950), .Y(n3075)
);
NOR2X6TS U2562 ( .A(DP_OP_498J311_124_1725_n638), .B(
DP_OP_498J311_124_1725_n641), .Y(n2014) );
NOR2X4TS U2563 ( .A(DP_OP_498J311_124_1725_n635), .B(n2071), .Y(n2075) );
NOR2X2TS U2564 ( .A(DP_OP_498J311_124_1725_n724), .B(n1175), .Y(n2172) );
NOR2X4TS U2565 ( .A(DP_OP_498J311_124_1725_n726), .B(n2026), .Y(n2034) );
INVX2TS U2566 ( .A(n2862), .Y(n2947) );
NOR2BX2TS U2567 ( .AN(n3166), .B(n3278), .Y(n2862) );
OR2X6TS U2568 ( .A(n1328), .B(n1327), .Y(n3344) );
ADDFX2TS U2569 ( .A(n3035), .B(n3034), .CI(n3033), .CO(n3036), .S(n2985) );
OAI22X2TS U2570 ( .A0(n2975), .A1(n3032), .B0(n3030), .B1(n3031), .Y(n3019)
);
XNOR2X4TS U2571 ( .A(n2801), .B(n1041), .Y(n2975) );
NOR2X2TS U2572 ( .A(n1584), .B(n1579), .Y(n1580) );
NOR2X6TS U2573 ( .A(n1125), .B(n1089), .Y(n1088) );
INVX8TS U2574 ( .A(n1978), .Y(n2202) );
NAND2X4TS U2575 ( .A(n1976), .B(n1991), .Y(n1977) );
NOR2X6TS U2576 ( .A(DP_OP_498J311_124_1725_n795), .B(
DP_OP_498J311_124_1725_n801), .Y(n1965) );
OAI22X2TS U2577 ( .A0(n2175), .A1(n922), .B0(n1173), .B1(n921), .Y(n2060) );
INVX8TS U2578 ( .A(n1986), .Y(n2175) );
ADDFHX4TS U2579 ( .A(n2284), .B(n2283), .CI(n2282), .CO(n2294), .S(n2289) );
NOR2X6TS U2580 ( .A(DP_OP_498J311_124_1725_n725), .B(n2026), .Y(n2001) );
CLKXOR2X2TS U2581 ( .A(n3481), .B(n3480), .Y(n3527) );
XNOR2X1TS U2582 ( .A(n3474), .B(n1158), .Y(n3501) );
AOI21X2TS U2583 ( .A0(n3473), .A1(n1158), .B0(n3174), .Y(n3480) );
ADDFHX2TS U2584 ( .A(n1493), .B(n1492), .CI(n1491), .CO(n1565), .S(n1494) );
ADDFHX2TS U2585 ( .A(n2240), .B(n2239), .CI(n2238), .CO(n2260), .S(n2241) );
NOR2X6TS U2586 ( .A(n3792), .B(n3777), .Y(n1076) );
NAND3X2TS U2587 ( .A(n2822), .B(n2821), .C(n2820), .Y(n2914) );
NOR2X2TS U2588 ( .A(n926), .B(n2146), .Y(n2330) );
ADDFHX4TS U2589 ( .A(n2115), .B(n2114), .CI(n2113), .CO(n2163), .S(n2305) );
ADDHX1TS U2590 ( .A(FPMULT_Sgf_normalized_result[8]), .B(add_x_246_n17),
.CO(n3881), .S(FPMULT_Adder_M_result_A_adder[8]) );
ADDHX1TS U2591 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n3879), .CO(n4128),
.S(FPMULT_Adder_M_result_A_adder[13]) );
ADDFHX2TS U2592 ( .A(n2899), .B(n2898), .CI(n2897), .CO(n2967), .S(n3050) );
ADDFHX4TS U2593 ( .A(n3491), .B(n3490), .CI(n3489), .CO(n3525), .S(n3476) );
NAND2X2TS U2594 ( .A(n2502), .B(n2501), .Y(n2503) );
NOR2X8TS U2595 ( .A(n2482), .B(n2481), .Y(n2495) );
NAND2X4TS U2596 ( .A(n3181), .B(n3180), .Y(n3535) );
ADDFHX2TS U2597 ( .A(n3126), .B(n3125), .CI(n3124), .CO(n3113), .S(n3132) );
NOR2X4TS U2598 ( .A(DP_OP_498J311_124_1725_n726), .B(
DP_OP_498J311_124_1725_n730), .Y(n2181) );
ADDFHX4TS U2599 ( .A(n2278), .B(n2277), .CI(n2276), .CO(n2299), .S(n2303) );
ADDFHX4TS U2600 ( .A(n2248), .B(n2247), .CI(n2246), .CO(n2277), .S(n2290) );
NOR2X4TS U2601 ( .A(n2094), .B(DP_OP_498J311_124_1725_n642), .Y(n2076) );
INVX8TS U2602 ( .A(DP_OP_498J311_124_1725_n791), .Y(n2094) );
NAND2X6TS U2603 ( .A(n5543), .B(n2071), .Y(n1967) );
INVX12TS U2604 ( .A(n2336), .Y(n1040) );
OAI21X2TS U2605 ( .A0(n1713), .A1(n1105), .B0(n1104), .Y(n1103) );
ADDFHX4TS U2606 ( .A(n2067), .B(n2066), .CI(n2065), .CO(n2133), .S(n2062) );
ADDFHX2TS U2607 ( .A(n1929), .B(n1928), .CI(n1927), .CO(n2933), .S(n2840) );
NOR2X4TS U2608 ( .A(DP_OP_498J311_124_1725_n638), .B(n2189), .Y(n2179) );
XNOR2X2TS U2609 ( .A(n1324), .B(n1323), .Y(n1327) );
OAI21X2TS U2610 ( .A0(n1433), .A1(n1316), .B0(n1315), .Y(n1324) );
OAI2BB1X2TS U2611 ( .A0N(n1272), .A1N(n1271), .B0(n1132), .Y(n1296) );
NOR2X4TS U2612 ( .A(n5545), .B(n1497), .Y(n1271) );
NAND2X4TS U2613 ( .A(n2553), .B(n2552), .Y(n3512) );
OAI21X1TS U2614 ( .A0(n2542), .A1(n2521), .B0(n2520), .Y(n2526) );
NAND2X4TS U2615 ( .A(n2245), .B(n2244), .Y(n2539) );
AOI21X2TS U2616 ( .A0(n3542), .A1(n3541), .B0(n3540), .Y(n3547) );
NOR2X6TS U2617 ( .A(DP_OP_498J311_124_1725_n725), .B(n1175), .Y(n2468) );
XOR2X2TS U2618 ( .A(n2865), .B(n2868), .Y(n2869) );
OAI22X4TS U2619 ( .A0(n3141), .A1(n2880), .B0(n2851), .B1(n3167), .Y(n2886)
);
NOR2X6TS U2620 ( .A(n1131), .B(n1102), .Y(n2865) );
OA21X2TS U2621 ( .A0(n4202), .A1(n4201), .B0(n4200), .Y(n1190) );
INVX4TS U2622 ( .A(n1581), .Y(n1533) );
NAND2X4TS U2623 ( .A(n1580), .B(n1581), .Y(n1090) );
NOR2X6TS U2624 ( .A(n2677), .B(n2676), .Y(n2748) );
ADDFHX4TS U2625 ( .A(DP_OP_496J311_122_3540_n1516), .B(n5454), .CI(n2753),
.CO(n2754), .S(n2677) );
XNOR2X2TS U2626 ( .A(n3037), .B(n3143), .Y(n2962) );
XNOR2X4TS U2627 ( .A(n2515), .B(n2514), .Y(n2532) );
XNOR2X2TS U2628 ( .A(n2529), .B(n2528), .Y(n2530) );
NOR2X4TS U2629 ( .A(n2495), .B(n3319), .Y(n2484) );
CLKXOR2X2TS U2630 ( .A(n3552), .B(n3551), .Y(n4512) );
BUFX12TS U2631 ( .A(n1974), .Y(n2336) );
ADDFX2TS U2632 ( .A(n2112), .B(n2111), .CI(n2110), .CO(n2137), .S(n2134) );
AOI21X4TS U2633 ( .A0(n1826), .A1(n1825), .B0(n1824), .Y(n1842) );
INVX2TS U2634 ( .A(n1831), .Y(n1826) );
AOI21X4TS U2635 ( .A0(n1480), .A1(n1479), .B0(n1478), .Y(n935) );
XNOR2X2TS U2636 ( .A(n2403), .B(n2402), .Y(n3266) );
NOR2X4TS U2637 ( .A(n3544), .B(n3543), .Y(n3570) );
ADDFHX2TS U2638 ( .A(n2055), .B(n2054), .CI(n2053), .CO(n2392), .S(n2390) );
ADDFHX4TS U2639 ( .A(n3806), .B(n3805), .CI(add_x_69_n77), .CO(n3836), .S(
n3905) );
NOR2X4TS U2640 ( .A(n920), .B(DP_OP_497J311_123_1725_n721), .Y(n1529) );
AND2X8TS U2641 ( .A(n936), .B(n1139), .Y(n3979) );
ADDFHX2TS U2642 ( .A(n2932), .B(n2933), .CI(n2931), .CO(n2991), .S(n2941) );
AOI21X2TS U2643 ( .A0(n1870), .A1(n2813), .B0(n1873), .Y(n1830) );
AND2X4TS U2644 ( .A(n1870), .B(n1872), .Y(n1160) );
NAND2X8TS U2645 ( .A(n2730), .B(n3031), .Y(n3032) );
XNOR2X2TS U2646 ( .A(n3214), .B(n3213), .Y(n3217) );
AOI21X2TS U2647 ( .A0(n4981), .A1(n4890), .B0(n4889), .Y(n4973) );
OAI21X2TS U2648 ( .A0(n4990), .A1(n4888), .B0(n4887), .Y(n4981) );
ADDFHX4TS U2649 ( .A(n1521), .B(n1520), .CI(n1519), .CO(n1522), .S(n1475) );
ADDFHX2TS U2650 ( .A(n1336), .B(n1335), .CI(n1334), .CO(n1667), .S(n1623) );
CMPR22X2TS U2651 ( .A(n1300), .B(n1299), .CO(n1334), .S(n1577) );
INVX12TS U2652 ( .A(n1633), .Y(n3888) );
INVX2TS U2653 ( .A(n1424), .Y(n1316) );
NOR2X2TS U2654 ( .A(n3754), .B(n3770), .Y(n3761) );
NAND2X4TS U2655 ( .A(n1343), .B(n1129), .Y(n1128) );
NOR2X4TS U2656 ( .A(DP_OP_498J311_124_1725_n635), .B(
DP_OP_498J311_124_1725_n645), .Y(n2000) );
ADDFHX4TS U2657 ( .A(n2208), .B(n2207), .CI(n2206), .CO(n2479), .S(n2478) );
ADDFHX2TS U2658 ( .A(n3156), .B(n3155), .CI(n3154), .CO(n3148), .S(n3176) );
ADDFHX2TS U2659 ( .A(n3164), .B(n3163), .CI(n3162), .CO(n3156), .S(n3172) );
NAND2BX1TS U2660 ( .AN(n999), .B(n1033), .Y(n3142) );
NAND2X4TS U2661 ( .A(n999), .B(n2651), .Y(n2810) );
ADDFHX4TS U2662 ( .A(n1587), .B(n1586), .CI(n1585), .CO(n1618), .S(n1571) );
OAI21X4TS U2663 ( .A0(n1713), .A1(n1751), .B0(n1750), .Y(n1756) );
ADDFHX2TS U2664 ( .A(n3112), .B(n3111), .CI(n3110), .CO(n3089), .S(n3190) );
XOR2X4TS U2665 ( .A(n2782), .B(n2789), .Y(n2791) );
INVX4TS U2666 ( .A(n2955), .Y(n3065) );
ADDFHX2TS U2667 ( .A(n1886), .B(n1885), .CI(n1884), .CO(n2955), .S(n3072) );
ADDFHX2TS U2668 ( .A(n2295), .B(n2294), .CI(n2293), .CO(n2310), .S(n2302) );
ADDFHX2TS U2669 ( .A(n2005), .B(n2004), .CI(n2003), .CO(n2046), .S(n2037) );
AOI21X2TS U2670 ( .A0(n1749), .A1(n1748), .B0(n1747), .Y(n1750) );
NOR2X2TS U2671 ( .A(n1742), .B(n1745), .Y(n1748) );
INVX4TS U2672 ( .A(n3749), .Y(n3896) );
OAI22X2TS U2673 ( .A0(n2845), .A1(n3062), .B0(n2828), .B1(n1038), .Y(n2901)
);
ADDFHX2TS U2674 ( .A(n2902), .B(n2901), .CI(n2900), .CO(n2939), .S(n2966) );
ADDFHX4TS U2675 ( .A(n2328), .B(n2327), .CI(n2326), .CO(n2363), .S(n2342) );
NOR2X8TS U2676 ( .A(n4030), .B(n3926), .Y(n4012) );
NAND2X4TS U2677 ( .A(n2479), .B(n2480), .Y(n3320) );
XNOR2X4TS U2678 ( .A(n2526), .B(n2525), .Y(n2531) );
ADDFHX4TS U2679 ( .A(n2301), .B(n2300), .CI(n2299), .CO(n2307), .S(n2308) );
ADDFHX4TS U2680 ( .A(n2064), .B(n2063), .CI(n2062), .CO(n2115), .S(n2300) );
ADDFHX4TS U2681 ( .A(n2260), .B(n2259), .CI(n2258), .CO(n2288), .S(n2245) );
ADDFHX4TS U2682 ( .A(n2263), .B(n2262), .CI(n2261), .CO(n2275), .S(n2259) );
ADDHX4TS U2683 ( .A(n1996), .B(n1995), .CO(n2208), .S(n2475) );
NOR2X4TS U2684 ( .A(n2188), .B(DP_OP_498J311_124_1725_n642), .Y(n1996) );
XNOR2X4TS U2685 ( .A(n2176), .B(n1156), .Y(n2262) );
NAND3X8TS U2686 ( .A(n3897), .B(n1076), .C(n3790), .Y(n1075) );
ADDFHX2TS U2687 ( .A(n3075), .B(n3074), .CI(n3073), .CO(n3086), .S(n3114) );
INVX8TS U2688 ( .A(n1062), .Y(n1063) );
ADDFHX4TS U2689 ( .A(n2070), .B(n2069), .CI(n2068), .CO(n2085), .S(n2086) );
ADDFHX2TS U2690 ( .A(n2130), .B(n2129), .CI(n2128), .CO(n2159), .S(n2131) );
OR2X4TS U2691 ( .A(DP_OP_498J311_124_1725_n729), .B(
DP_OP_498J311_124_1725_n642), .Y(n1983) );
ADDFHX2TS U2692 ( .A(n2093), .B(n923), .CI(n2092), .CO(n2132), .S(n2297) );
INVX6TS U2693 ( .A(n2486), .Y(n2093) );
ADDFHX2TS U2694 ( .A(n2266), .B(n2265), .CI(n2264), .CO(n2276), .S(n2274) );
OAI21X4TS U2695 ( .A0(n2878), .A1(n2928), .B0(n914), .Y(n3077) );
ADDFHX4TS U2696 ( .A(n3090), .B(n3089), .CI(n3088), .CO(n3070), .S(n3188) );
XNOR2X4TS U2697 ( .A(n3083), .B(n3079), .Y(n2959) );
OAI21X1TS U2698 ( .A0(n1746), .A1(n1745), .B0(n1744), .Y(n1747) );
ADDFHX4TS U2699 ( .A(n2161), .B(n2160), .CI(n2159), .CO(n2340), .S(n2142) );
ADDFHX2TS U2700 ( .A(n2257), .B(n2256), .CI(n2255), .CO(n2287), .S(n2282) );
ADDFHX2TS U2701 ( .A(n1722), .B(n1721), .CI(n1720), .CO(n1753), .S(n1724) );
INVX4TS U2702 ( .A(n1394), .Y(n1690) );
NOR2X4TS U2703 ( .A(n1584), .B(n1583), .Y(n1089) );
NOR2X4TS U2704 ( .A(n1571), .B(n1572), .Y(n1584) );
ADDFHX4TS U2705 ( .A(n1221), .B(n1220), .CI(n1219), .CO(n1333), .S(n1298) );
ADDFHX2TS U2706 ( .A(n2965), .B(n2964), .CI(n2963), .CO(n2970), .S(n3066) );
ADDFHX2TS U2707 ( .A(n1917), .B(n1916), .CI(n1915), .CO(n2846), .S(n2954) );
ADDFHX4TS U2708 ( .A(n2275), .B(n2274), .CI(n2273), .CO(n2304), .S(n2270) );
NOR2X4TS U2709 ( .A(n2188), .B(n2168), .Y(n2472) );
CLKINVX6TS U2710 ( .A(n4026), .Y(add_x_69_n243) );
NAND3X4TS U2711 ( .A(n3344), .B(n3343), .C(n3342), .Y(n1100) );
NOR2X6TS U2712 ( .A(n2317), .B(n2318), .Y(n2445) );
NAND2X4TS U2713 ( .A(n1741), .B(n3996), .Y(n3998) );
NOR2X6TS U2714 ( .A(n2291), .B(n2292), .Y(n2572) );
NOR2X4TS U2715 ( .A(DP_OP_498J311_124_1725_n725), .B(
DP_OP_498J311_124_1725_n732), .Y(n2458) );
CMPR22X2TS U2716 ( .A(n2034), .B(n2033), .CO(n2039), .S(n2351) );
ADDFHX4TS U2717 ( .A(n2994), .B(n2993), .CI(n2992), .CO(n3041), .S(n2990) );
OAI22X2TS U2718 ( .A0(n3147), .A1(n3165), .B0(n1057), .B1(n3146), .Y(n3160)
);
INVX4TS U2719 ( .A(n2867), .Y(n3165) );
ADDFHX2TS U2720 ( .A(n2154), .B(n2155), .CI(n2153), .CO(n2326), .S(n2138) );
NAND2X4TS U2721 ( .A(n2320), .B(n2319), .Y(n2436) );
OAI22X2TS U2722 ( .A0(n1039), .A1(n922), .B0(n2202), .B1(n921), .Y(n2155) );
NAND2X6TS U2723 ( .A(n3694), .B(n3697), .Y(n2585) );
NOR2X8TS U2724 ( .A(n3095), .B(n3096), .Y(n3755) );
ADDFHX4TS U2725 ( .A(n2971), .B(n2970), .CI(n2969), .CO(n2945), .S(n3045) );
ADDFHX2TS U2726 ( .A(n2890), .B(n2889), .CI(n2888), .CO(n2943), .S(n2971) );
NAND2X4TS U2727 ( .A(add_x_69_n242), .B(add_x_69_n235), .Y(add_x_69_n233) );
NAND2X4TS U2728 ( .A(n1476), .B(n1525), .Y(n1481) );
ADDFHX4TS U2729 ( .A(n3231), .B(n3230), .CI(n3229), .CO(n3273), .S(n3206) );
ADDFHX2TS U2730 ( .A(n3210), .B(n3209), .CI(n3208), .CO(n3275), .S(n3229) );
ADDFHX2TS U2731 ( .A(n2915), .B(n2914), .CI(n2913), .CO(n3003), .S(n2938) );
OAI22X2TS U2732 ( .A0(n2805), .A1(n3141), .B0(n2979), .B1(n3167), .Y(n2808)
);
OR2X4TS U2733 ( .A(n3460), .B(n1135), .Y(n1136) );
ADDFHX4TS U2734 ( .A(n3585), .B(n3584), .CI(n3583), .CO(n3586), .S(n3557) );
ADDFHX4TS U2735 ( .A(n2861), .B(n2860), .CI(n2859), .CO(n3451), .S(n3426) );
NOR2X8TS U2736 ( .A(n1769), .B(n1768), .Y(n2643) );
NAND2BX4TS U2737 ( .AN(n1143), .B(n3456), .Y(n3664) );
ADDHX4TS U2738 ( .A(n3077), .B(n3076), .CO(n3363), .S(n3369) );
XNOR2X2TS U2739 ( .A(n3454), .B(n1144), .Y(n3455) );
NAND2X2TS U2740 ( .A(n3473), .B(n3472), .Y(n3474) );
OR2X4TS U2741 ( .A(n3173), .B(n3172), .Y(n3473) );
NAND2X4TS U2742 ( .A(DP_OP_499J311_125_1651_n72), .B(n3974), .Y(
DP_OP_499J311_125_1651_n10) );
NOR2X4TS U2743 ( .A(n1407), .B(DP_OP_497J311_123_1725_n721), .Y(n1576) );
NAND2X4TS U2744 ( .A(n3096), .B(n3095), .Y(n3756) );
OAI22X4TS U2745 ( .A0(n2928), .A1(n2877), .B0(n2853), .B1(n1068), .Y(n2885)
);
ADDFHX2TS U2746 ( .A(n1655), .B(n1654), .CI(n1653), .CO(n1684), .S(n1646) );
OAI21X2TS U2747 ( .A0(n1466), .A1(n1465), .B0(n1463), .Y(n1402) );
ADDFHX4TS U2748 ( .A(n3041), .B(n3040), .CI(n3039), .CO(n3205), .S(n3042) );
ADDFHX2TS U2749 ( .A(n3010), .B(n3009), .CI(n3008), .CO(n3207), .S(n3044) );
ADDFHX2TS U2750 ( .A(n3013), .B(n3012), .CI(n3011), .CO(n3231), .S(n3010) );
OAI22X2TS U2751 ( .A0(n1939), .A1(n2629), .B0(n1947), .B1(n2628), .Y(n1948)
);
OAI21X1TS U2752 ( .A0(n4425), .A1(n4095), .B0(n4097), .Y(n4094) );
CLKXOR2X2TS U2753 ( .A(n5485), .B(n5486), .Y(n4049) );
ADDFHX4TS U2754 ( .A(n2281), .B(n2280), .CI(n2279), .CO(n2298), .S(n2295) );
OAI21X4TS U2755 ( .A0(n2464), .A1(n2461), .B0(n2463), .Y(n2315) );
XNOR2X4TS U2756 ( .A(n3335), .B(n3334), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[7]) );
OAI21X1TS U2757 ( .A0(n1433), .A1(n1311), .B0(n1313), .Y(n1269) );
INVX2TS U2758 ( .A(n1311), .Y(n1236) );
NOR2X4TS U2759 ( .A(DP_OP_497J311_123_1725_n638), .B(n1214), .Y(n3371) );
NOR2X4TS U2760 ( .A(n1214), .B(n5554), .Y(n1211) );
OAI21X2TS U2761 ( .A0(n4970), .A1(n4967), .B0(n4968), .Y(n4961) );
OAI21X4TS U2762 ( .A0(n4987), .A1(n4984), .B0(n4985), .Y(n4978) );
AOI21X4TS U2763 ( .A0(n4922), .A1(n4921), .B0(n4159), .Y(n4934) );
OAI21X4TS U2764 ( .A0(n2495), .A1(n3320), .B0(n2496), .Y(n2483) );
NAND2X4TS U2765 ( .A(n2482), .B(n2481), .Y(n2496) );
ADDFHX4TS U2766 ( .A(n2043), .B(n2042), .CI(n2041), .CO(n2481), .S(n2480) );
XNOR2X2TS U2767 ( .A(n2844), .B(n3143), .Y(n3084) );
ADDFHX4TS U2768 ( .A(n1552), .B(n1551), .CI(n1550), .CO(n1614), .S(n1548) );
AND2X8TS U2769 ( .A(n3959), .B(n3958), .Y(n3981) );
OAI21X4TS U2770 ( .A0(n1533), .A1(n1579), .B0(n1583), .Y(n1575) );
NAND2X2TS U2771 ( .A(n3975), .B(n1163), .Y(DP_OP_499J311_125_1651_n29) );
ADDFHX2TS U2772 ( .A(DP_OP_497J311_123_1725_n699), .B(
DP_OP_497J311_123_1725_n684), .CI(n1553), .CO(n1601), .S(n1555) );
ADDFHX4TS U2773 ( .A(n2133), .B(n2132), .CI(n2131), .CO(n2141), .S(n2114) );
NAND2X4TS U2774 ( .A(n2595), .B(n2594), .Y(n3677) );
NOR4X2TS U2775 ( .A(n4193), .B(n4192), .C(n4191), .D(n4190), .Y(n5882) );
ADDFHX4TS U2776 ( .A(n2088), .B(n2087), .CI(n2086), .CO(n2485), .S(n2482) );
NOR2X2TS U2777 ( .A(n3689), .B(n3688), .Y(n4186) );
OAI21X4TS U2778 ( .A0(n2445), .A1(n2434), .B0(n2446), .Y(n2439) );
NAND2X4TS U2779 ( .A(n1326), .B(n1325), .Y(n3339) );
NAND2X4TS U2780 ( .A(n2577), .B(n2576), .Y(n3580) );
INVX4TS U2781 ( .A(n2577), .Y(n1151) );
NAND2X8TS U2782 ( .A(n2593), .B(n2592), .Y(n3673) );
OAI21X2TS U2783 ( .A0(n4973), .A1(n4892), .B0(n4891), .Y(n4964) );
OAI21X1TS U2784 ( .A0(n5068), .A1(n4803), .B0(n4802), .Y(n5050) );
XOR2X4TS U2785 ( .A(n3903), .B(n3904), .Y(n3762) );
ADDHX4TS U2786 ( .A(n3078), .B(n3365), .CO(n3059), .S(n3122) );
OAI22X2TS U2787 ( .A0(n1660), .A1(n1596), .B0(n1661), .B1(n1652), .Y(n1592)
);
ADDFHX4TS U2788 ( .A(n2164), .B(n2163), .CI(n2162), .CO(n2319), .S(n2318) );
ADDFHX4TS U2789 ( .A(n3921), .B(n3919), .CI(n3920), .CO(n3932), .S(n3934) );
AOI21X4TS U2790 ( .A0(n2415), .A1(n2358), .B0(n2357), .Y(n2359) );
NAND2BX4TS U2791 ( .AN(DP_OP_499J311_125_1651_n69), .B(n3910), .Y(
DP_OP_499J311_125_1651_n9) );
NOR2X8TS U2792 ( .A(n3202), .B(n3201), .Y(n3792) );
AOI21X2TS U2793 ( .A0(n3897), .A1(n3896), .B0(n3895), .Y(n3902) );
CMPR22X2TS U2794 ( .A(n1901), .B(n1900), .CO(n3082), .S(n3116) );
AOI21X2TS U2795 ( .A0(n3983), .A1(n3982), .B0(n3981), .Y(
DP_OP_499J311_125_1651_n93) );
INVX6TS U2796 ( .A(n3979), .Y(n3983) );
OAI21X2TS U2797 ( .A0(n2489), .A1(n2492), .B0(n2490), .Y(n2528) );
OA21X4TS U2798 ( .A0(n2229), .A1(n2500), .B0(n2501), .Y(n2492) );
ADDFHX4TS U2799 ( .A(n3565), .B(n3564), .CI(n3563), .CO(n3594), .S(n3583) );
OA21X4TS U2800 ( .A0(n3429), .A1(n3428), .B0(n3427), .Y(n1135) );
XNOR2X4TS U2801 ( .A(n1149), .B(n1142), .Y(n1147) );
ADDFHX4TS U2802 ( .A(n2304), .B(n2303), .CI(n2302), .CO(n2311), .S(n2292) );
NAND2X4TS U2803 ( .A(n3925), .B(n3924), .Y(DP_OP_499J311_125_1651_n54) );
ADDFHX2TS U2804 ( .A(n1539), .B(n1538), .CI(n1537), .CO(n1616), .S(n1546) );
ADDFHX2TS U2805 ( .A(n1406), .B(n1405), .CI(n1404), .CO(n1441), .S(n1385) );
XOR2X1TS U2806 ( .A(n1148), .B(n1142), .Y(add_x_69_n19) );
ADDFHX2TS U2807 ( .A(n2920), .B(n2919), .CI(n2918), .CO(n3520), .S(n3485) );
ADDFHX4TS U2808 ( .A(n2991), .B(n2990), .CI(n2989), .CO(n3043), .S(n3006) );
BUFX16TS U2809 ( .A(n2736), .Y(n2929) );
NAND2X4TS U2810 ( .A(n4727), .B(n3621), .Y(n4163) );
NOR2X4TS U2811 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .B(n3622), .Y(n3621) );
NAND2X4TS U2812 ( .A(n4723), .B(n4719), .Y(n3622) );
OAI21X4TS U2813 ( .A0(n1120), .A1(n3904), .B0(n3903), .Y(n1119) );
NOR2X8TS U2814 ( .A(n3898), .B(n3749), .Y(n3790) );
ADDFHX4TS U2815 ( .A(n2849), .B(n2848), .CI(n2847), .CO(n3467), .S(n3452) );
NOR2X4TS U2816 ( .A(n1083), .B(n1081), .Y(n2647) );
NOR2X6TS U2817 ( .A(n1712), .B(n1711), .Y(n3889) );
ADDFHX4TS U2818 ( .A(n1570), .B(n1569), .CI(n1568), .CO(n1572), .S(n1523) );
ADDFHX4TS U2819 ( .A(n1546), .B(n1545), .CI(n1544), .CO(n1586), .S(n1568) );
NAND2X4TS U2820 ( .A(DP_OP_499J311_125_1651_n191), .B(
DP_OP_499J311_125_1651_n194), .Y(DP_OP_499J311_125_1651_n48) );
ADDFHX4TS U2821 ( .A(n3936), .B(n3935), .CI(n3934), .CO(
DP_OP_499J311_125_1651_n190), .S(DP_OP_499J311_125_1651_n191) );
CMPR22X2TS U2822 ( .A(n1230), .B(n1229), .CO(n1265), .S(n1226) );
OAI21X4TS U2823 ( .A0(n2643), .A1(n2641), .B0(n2644), .Y(n1770) );
NOR2X8TS U2824 ( .A(n2454), .B(n2453), .Y(n3652) );
AOI21X4TS U2825 ( .A0(n3928), .A1(n4012), .B0(n3831), .Y(n4026) );
NOR2X8TS U2826 ( .A(n1110), .B(n3830), .Y(n4030) );
XOR2X4TS U2827 ( .A(n3355), .B(n3354), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[11]) );
OAI21X4TS U2828 ( .A0(n1421), .A1(n1420), .B0(n1419), .Y(n1479) );
AOI21X4TS U2829 ( .A0(n1367), .A1(n1366), .B0(n1365), .Y(n1420) );
ADDHX4TS U2830 ( .A(n1211), .B(n1210), .CO(n1218), .S(n1292) );
OAI21X1TS U2831 ( .A0(add_x_69_n271), .A1(n4028), .B0(n4027), .Y(
add_x_69_n268) );
INVX12TS U2832 ( .A(add_x_69_n272), .Y(add_x_69_n271) );
NOR2X4TS U2833 ( .A(n2226), .B(n2210), .Y(n2198) );
INVX6TS U2834 ( .A(n1975), .Y(n2210) );
XOR2X2TS U2835 ( .A(n1149), .B(n3609), .Y(n1148) );
NAND2X4TS U2836 ( .A(n3608), .B(n3607), .Y(n3956) );
ADDFHX2TS U2837 ( .A(n3939), .B(n3938), .CI(n3937), .CO(n3955), .S(n3607) );
ADDFHX2TS U2838 ( .A(n3501), .B(n3500), .CI(n3499), .CO(n3509), .S(n3475) );
AOI21X4TS U2839 ( .A0(n3823), .A1(n3822), .B0(n3821), .Y(n3824) );
CMPR22X2TS U2840 ( .A(n2073), .B(n2072), .CO(n2081), .S(n2069) );
ADDFHX4TS U2841 ( .A(n3527), .B(n3526), .CI(n3525), .CO(n3528), .S(n3503) );
ADDFHX4TS U2842 ( .A(n2958), .B(n2957), .CI(n2956), .CO(n3425), .S(n3412) );
XNOR2X2TS U2843 ( .A(n2921), .B(n1063), .Y(n2730) );
XOR2X4TS U2844 ( .A(n3762), .B(n1120), .Y(n3965) );
ADDFHX4TS U2845 ( .A(n3804), .B(n3803), .CI(n3802), .CO(n3966), .S(n3903) );
XOR2X4TS U2846 ( .A(n1466), .B(n1349), .Y(n1350) );
XNOR2X4TS U2847 ( .A(n1310), .B(n1366), .Y(n1328) );
NAND2X2TS U2848 ( .A(n1367), .B(n1364), .Y(n1310) );
ADDFHX4TS U2849 ( .A(n2310), .B(n2309), .CI(n2308), .CO(n2314), .S(n2312) );
XNOR2X4TS U2850 ( .A(n2439), .B(n2438), .Y(n2454) );
OR2X8TS U2851 ( .A(n3608), .B(n3607), .Y(n3957) );
XOR2X4TS U2852 ( .A(n2571), .B(n2575), .Y(n2577) );
XNOR2X4TS U2853 ( .A(n3603), .B(n3695), .Y(n3688) );
AOI21X1TS U2854 ( .A0(n3494), .A1(n3493), .B0(n3492), .Y(n3498) );
NAND2X4TS U2855 ( .A(n3496), .B(n3493), .Y(n2536) );
ADDFHX4TS U2856 ( .A(n2342), .B(n2341), .CI(n2340), .CO(n2361), .S(n2323) );
AOI21X4TS U2857 ( .A0(n3666), .A1(n3665), .B0(n3457), .Y(n3725) );
NOR2X2TS U2858 ( .A(n3439), .B(n3438), .Y(n3668) );
ADDHX1TS U2859 ( .A(DP_OP_497J311_123_1725_n791), .B(
DP_OP_497J311_123_1725_n709), .CO(n1240), .S(n1239) );
OAI21X4TS U2860 ( .A0(n3826), .A1(n3825), .B0(n3824), .Y(n3827) );
ADDFHX4TS U2861 ( .A(n2325), .B(n2324), .CI(n2323), .CO(n2344), .S(n2320) );
ADDFHX4TS U2862 ( .A(n2142), .B(n2141), .CI(n2140), .CO(n2324), .S(n2162) );
CMPR22X2TS U2863 ( .A(DP_OP_498J311_124_1725_n793), .B(
DP_OP_498J311_124_1725_n787), .CO(n1963), .S(n1962) );
ADDFHX4TS U2864 ( .A(n3511), .B(n3510), .CI(n3509), .CO(n3554), .S(n3502) );
ADDFHX2TS U2865 ( .A(n2022), .B(n2021), .CI(n2020), .CO(n2089), .S(n2044) );
NOR2X2TS U2866 ( .A(DP_OP_498J311_124_1725_n722), .B(n1175), .Y(n2022) );
ADDFHX2TS U2867 ( .A(n1543), .B(n1542), .CI(n1541), .CO(n1591), .S(n1549) );
OAI22X2TS U2868 ( .A0(n1611), .A1(n1659), .B0(n1535), .B1(n1690), .Y(n1542)
);
NAND2X2TS U2869 ( .A(n4003), .B(n4002), .Y(add_x_69_n39) );
NOR2X4TS U2870 ( .A(n3998), .B(n3997), .Y(n4003) );
XNOR2X4TS U2871 ( .A(n1756), .B(n1755), .Y(n1769) );
NAND2X4TS U2872 ( .A(n1110), .B(n3830), .Y(n4031) );
XNOR2X4TS U2873 ( .A(n3812), .B(n3811), .Y(n1110) );
NOR2X8TS U2874 ( .A(n2598), .B(n2597), .Y(n3817) );
NAND2X8TS U2875 ( .A(n1033), .B(n3167), .Y(n3141) );
AOI21X4TS U2876 ( .A0(n3417), .A1(n3416), .B0(n3415), .Y(n3428) );
XOR2X4TS U2877 ( .A(n4005), .B(n4009), .Y(n4015) );
NAND2BX4TS U2878 ( .AN(n1109), .B(n3816), .Y(n1108) );
XNOR2X2TS U2879 ( .A(n1284), .B(n1308), .Y(n1325) );
NAND2X2TS U2880 ( .A(n1309), .B(n1306), .Y(n1284) );
OAI21X2TS U2881 ( .A0(n4030), .A1(n4010), .B0(n4031), .Y(n3831) );
OA21X2TS U2882 ( .A0(n1992), .A1(n1991), .B0(n1990), .Y(n949) );
OR2X2TS U2883 ( .A(n1992), .B(n1989), .Y(n1164) );
NAND2X6TS U2884 ( .A(n4013), .B(n4012), .Y(add_x_69_n244) );
XNOR2X4TS U2885 ( .A(n1269), .B(n1268), .Y(n1326) );
NOR2X4TS U2886 ( .A(n3829), .B(n1106), .Y(n3926) );
XOR2X4TS U2887 ( .A(n1108), .B(n3813), .Y(n3829) );
NOR2X4TS U2888 ( .A(n1147), .B(n3609), .Y(add_x_69_n230) );
CLKAND2X2TS U2889 ( .A(n5746), .B(FPADDSUB_DMP_SFG[14]), .Y(n4889) );
XOR2X1TS U2890 ( .A(n2412), .B(n2411), .Y(n948) );
INVX2TS U2891 ( .A(n3255), .Y(n3261) );
CLKAND2X2TS U2892 ( .A(n4216), .B(n5497), .Y(n4217) );
OAI21X1TS U2893 ( .A0(n1704), .A1(n1703), .B0(n1702), .Y(n1762) );
AOI21X2TS U2894 ( .A0(n1906), .A1(n3235), .B0(n1905), .Y(n3866) );
NOR2X1TS U2895 ( .A(n3245), .B(n3243), .Y(n1906) );
AOI21X2TS U2896 ( .A0(n4964), .A1(n4894), .B0(n4893), .Y(n4917) );
CLKAND2X2TS U2897 ( .A(n5775), .B(FPADDSUB_DMP_SFG[16]), .Y(n4893) );
MX2X1TS U2898 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
INVX2TS U2899 ( .A(n1501), .Y(n1535) );
INVX2TS U2900 ( .A(n3364), .Y(n3058) );
NAND2X4TS U2901 ( .A(n2170), .B(n2169), .Y(n2212) );
OAI21X2TS U2902 ( .A0(n2827), .A1(n2795), .B0(n2797), .Y(n2780) );
INVX4TS U2903 ( .A(n4512), .Y(n3564) );
NOR2X1TS U2904 ( .A(n4214), .B(n4239), .Y(n4241) );
NOR2X1TS U2905 ( .A(n2933), .B(n2903), .Y(n2615) );
OR2X1TS U2906 ( .A(n4403), .B(n4411), .Y(n4343) );
OR2X1TS U2907 ( .A(n3116), .B(n3103), .Y(n3798) );
NOR2X1TS U2908 ( .A(n1779), .B(n1782), .Y(n1789) );
AOI21X2TS U2909 ( .A0(n928), .A1(n3706), .B0(n3651), .Y(n3656) );
CLKAND2X2TS U2910 ( .A(n5720), .B(FPADDSUB_DMP_SFG[12]), .Y(n4885) );
AOI21X2TS U2911 ( .A0(n4961), .A1(n4960), .B0(n4157), .Y(n4914) );
XNOR2X1TS U2912 ( .A(n3871), .B(n3870), .Y(n3921) );
INVX2TS U2913 ( .A(n3828), .Y(n3920) );
AOI21X2TS U2914 ( .A0(n1763), .A1(n1762), .B0(n1761), .Y(n1801) );
INVX2TS U2915 ( .A(n3357), .Y(n1484) );
NOR2X6TS U2916 ( .A(n3715), .B(n3787), .Y(n4033) );
OAI22X1TS U2917 ( .A0(n2175), .A1(n2335), .B0(n1173), .B1(n2364), .Y(n2108)
);
NAND2X1TS U2918 ( .A(n3143), .B(n1096), .Y(n1095) );
OAI22X1TS U2919 ( .A0(n1040), .A1(n921), .B0(n930), .B1(n922), .Y(n2338) );
INVX2TS U2920 ( .A(n3143), .Y(n2909) );
NAND2X2TS U2921 ( .A(n5590), .B(DP_OP_497J311_123_1725_n386), .Y(n1274) );
OAI22X2TS U2922 ( .A0(n3141), .A1(n3140), .B0(n2883), .B1(n3167), .Y(n3367)
);
ADDFHX2TS U2923 ( .A(n2205), .B(n2204), .CI(n2203), .CO(n2247), .S(n2268) );
NOR2X4TS U2924 ( .A(n951), .B(DP_OP_496J311_122_3540_n1096), .Y(n2659) );
ADDFHX2TS U2925 ( .A(n3027), .B(n3026), .CI(n3025), .CO(n3218), .S(n3022) );
NAND2X4TS U2926 ( .A(n3178), .B(n3177), .Y(n3505) );
OAI22X1TS U2927 ( .A0(n3057), .A1(n3165), .B0(n3084), .B1(n3146), .Y(n3111)
);
AOI2BB2XLTS U2928 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n5097), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n5096), .Y(n5098) );
OAI21X2TS U2929 ( .A0(n1842), .A1(n1841), .B0(n1840), .Y(n1843) );
ADDFHX2TS U2930 ( .A(n2988), .B(n2987), .CI(n2986), .CO(n3008), .S(n3002) );
NOR2X4TS U2931 ( .A(n1699), .B(n1698), .Y(n1742) );
AOI21X2TS U2932 ( .A0(n3573), .A1(n3572), .B0(n3571), .Y(n3574) );
INVX4TS U2933 ( .A(n2555), .Y(n2272) );
NOR2X1TS U2934 ( .A(n2385), .B(n2382), .Y(n2388) );
INVX2TS U2935 ( .A(n1749), .Y(n1678) );
NOR2X4TS U2936 ( .A(n1536), .B(n1558), .Y(n1314) );
NAND2X2TS U2937 ( .A(n1558), .B(n1536), .Y(n1312) );
AO21X1TS U2938 ( .A0(n1932), .A1(n1931), .B0(n1930), .Y(n1945) );
NOR2X1TS U2939 ( .A(n4820), .B(n4798), .Y(n4148) );
CLKAND2X2TS U2940 ( .A(n5716), .B(FPADDSUB_DMP_SFG[9]), .Y(n4843) );
INVX2TS U2941 ( .A(n3764), .Y(n3945) );
NAND2X1TS U2942 ( .A(n2953), .B(n3072), .Y(n3242) );
NOR2X2TS U2943 ( .A(n1384), .B(n1410), .Y(n3324) );
NOR2X2TS U2944 ( .A(DP_OP_498J311_124_1725_n645), .B(n2094), .Y(n2167) );
AND2X4TS U2945 ( .A(n3774), .B(n3897), .Y(n3775) );
INVX4TS U2946 ( .A(n3787), .Y(n3805) );
NAND2X1TS U2947 ( .A(n3259), .B(n3864), .Y(n3260) );
XNOR2X1TS U2948 ( .A(n1958), .B(n1957), .Y(n3923) );
INVX2TS U2949 ( .A(n3830), .Y(n3922) );
NAND2X1TS U2950 ( .A(n1956), .B(n2618), .Y(n1957) );
NAND2X2TS U2951 ( .A(n1101), .B(n1100), .Y(n1099) );
NAND2X2TS U2952 ( .A(n3341), .B(n3344), .Y(n1101) );
NAND3XLTS U2953 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n5214) );
AOI31XLTS U2954 ( .A0(n5212), .A1(n5211), .A2(n5210), .B0(n5217), .Y(n5215)
);
NOR3XLTS U2955 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n5199) );
OAI221XLTS U2956 ( .A0(n5779), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n946), .B1(
FPADDSUB_intDY_EWSW[22]), .C0(n5158), .Y(n5163) );
XOR2X1TS U2957 ( .A(n1027), .B(n1171), .Y(DP_OP_26J311_126_1325_n18) );
NOR2X1TS U2958 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3625) );
INVX2TS U2959 ( .A(n3617), .Y(n3618) );
NOR3X4TS U2960 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(
FPADDSUB_Raw_mant_NRM_SWR[4]), .C(n4144), .Y(n4141) );
OAI22X2TS U2961 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n4162), .B0(n3631),
.B1(n4165), .Y(n3632) );
NOR2X4TS U2962 ( .A(n3614), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4723) );
NAND2X4TS U2963 ( .A(n1161), .B(n957), .Y(n3720) );
MX2X1TS U2964 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
CLKAND2X2TS U2965 ( .A(FPMULT_FSM_selector_A), .B(FPMULT_exp_oper_result[8]),
.Y(FPMULT_S_Oper_A_exp[8]) );
OAI22X1TS U2966 ( .A0(n994), .A1(n922), .B0(n2201), .B1(n921), .Y(n2128) );
INVX2TS U2967 ( .A(n2508), .Y(n2130) );
INVX2TS U2968 ( .A(n2485), .Y(n2067) );
INVX2TS U2969 ( .A(n2389), .Y(n2066) );
NOR2X2TS U2970 ( .A(DP_OP_498J311_124_1725_n799), .B(
DP_OP_498J311_124_1725_n805), .Y(n1992) );
INVX2TS U2971 ( .A(n2513), .Y(n2156) );
INVX2TS U2972 ( .A(n2400), .Y(n2157) );
INVX2TS U2973 ( .A(n1071), .Y(n2717) );
OAI2BB1X2TS U2974 ( .A0N(n2477), .A1N(n1155), .B0(n2176), .Y(n1154) );
INVX2TS U2975 ( .A(n2177), .Y(n1155) );
NAND2X1TS U2976 ( .A(n2177), .B(n1153), .Y(n1152) );
INVX2TS U2977 ( .A(n2477), .Y(n1153) );
NOR2X2TS U2978 ( .A(DP_OP_498J311_124_1725_n798), .B(
DP_OP_498J311_124_1725_n804), .Y(n1989) );
ADDFHX2TS U2979 ( .A(n2103), .B(n2102), .CI(n2101), .CO(n2056), .S(n2285) );
INVX2TS U2980 ( .A(n2377), .Y(n2103) );
XNOR2X2TS U2981 ( .A(n2881), .B(n2850), .Y(n2834) );
INVX2TS U2982 ( .A(n2879), .Y(n2744) );
INVX2TS U2983 ( .A(n2979), .Y(n2924) );
ADDHX1TS U2984 ( .A(DP_OP_496J311_122_3540_n1513), .B(FPMULT_Op_MX[19]),
.CO(n2675), .S(n2651) );
ADDFHX2TS U2985 ( .A(DP_OP_496J311_122_3540_n1514), .B(FPMULT_Op_MX[20]),
.CI(n2675), .CO(n2687), .S(n2655) );
ADDHX1TS U2986 ( .A(n1339), .B(n1338), .CO(n1389), .S(n1352) );
INVX2TS U2987 ( .A(n1292), .Y(n1338) );
BUFX6TS U2988 ( .A(n2670), .Y(n3143) );
NAND2X1TS U2989 ( .A(n2948), .B(n2862), .Y(n2863) );
XNOR2X1TS U2990 ( .A(n3104), .B(n2972), .Y(n2875) );
INVX6TS U2991 ( .A(n2718), .Y(n2979) );
INVX2TS U2992 ( .A(n2850), .Y(n2930) );
OAI2BB1X1TS U2993 ( .A0N(n2472), .A1N(n2035), .B0(n2197), .Y(n2170) );
NAND2BX1TS U2994 ( .AN(n2035), .B(n2195), .Y(n2169) );
INVX2TS U2995 ( .A(n1987), .Y(n2109) );
INVX2TS U2996 ( .A(n2378), .Y(n2280) );
INVX2TS U2997 ( .A(FPMULT_Op_MX[21]), .Y(n1828) );
NAND2X1TS U2998 ( .A(n2712), .B(n2711), .Y(n2713) );
ADDFX1TS U2999 ( .A(n1645), .B(n1644), .CI(n1643), .CO(n1697), .S(n1637) );
ADDFHX2TS U3000 ( .A(n1549), .B(n1548), .CI(n1547), .CO(n1604), .S(n1545) );
INVX2TS U3001 ( .A(n1731), .Y(n1499) );
NAND2X1TS U3002 ( .A(n1401), .B(n1463), .Y(n1349) );
INVX2TS U3003 ( .A(n1357), .Y(n1652) );
NOR2X1TS U3004 ( .A(n2869), .B(n2868), .Y(n2870) );
OAI22X1TS U3005 ( .A0(n3062), .A1(n3100), .B0(n3061), .B1(n1038), .Y(n3107)
);
INVX2TS U3006 ( .A(n3412), .Y(n3056) );
INVX2TS U3007 ( .A(n2846), .Y(n2963) );
INVX2TS U3008 ( .A(n2480), .Y(n2266) );
NAND2BXLTS U3009 ( .AN(n999), .B(n2881), .Y(n2882) );
INVX2TS U3010 ( .A(n3609), .Y(n3391) );
AND2X2TS U3011 ( .A(n3387), .B(n3388), .Y(n3396) );
NAND2X1TS U3012 ( .A(n3412), .B(n3411), .Y(n3427) );
OR2X1TS U3013 ( .A(n3170), .B(n3169), .Y(n3444) );
NAND2X1TS U3014 ( .A(n3170), .B(n3169), .Y(n3443) );
NAND2X2TS U3015 ( .A(n1967), .B(n1980), .Y(n1966) );
INVX2TS U3016 ( .A(n2008), .Y(n2186) );
INVX2TS U3017 ( .A(n2009), .Y(n2185) );
INVX2TS U3018 ( .A(n2467), .Y(n2199) );
NAND2X1TS U3019 ( .A(n1832), .B(n1825), .Y(n1837) );
AOI21X2TS U3020 ( .A0(n1876), .A1(n1871), .B0(n1839), .Y(n1840) );
INVX2TS U3021 ( .A(n1875), .Y(n1839) );
INVX2TS U3022 ( .A(n1842), .Y(n1873) );
XOR2X2TS U3023 ( .A(n2817), .B(n2814), .Y(n2900) );
INVX2TS U3024 ( .A(n2414), .Y(n2322) );
XNOR2X1TS U3025 ( .A(n3037), .B(n2972), .Y(n2973) );
INVX2TS U3026 ( .A(n3521), .Y(n2996) );
CLKBUFX2TS U3027 ( .A(n1852), .Y(n2866) );
NAND2X1TS U3028 ( .A(FPMULT_Op_MX[19]), .B(DP_OP_496J311_122_3540_n1513),
.Y(n1831) );
OR2X2TS U3029 ( .A(FPMULT_Op_MX[19]), .B(DP_OP_496J311_122_3540_n1513), .Y(
n1832) );
BUFX3TS U3030 ( .A(n2415), .Y(n2421) );
NAND2X6TS U3031 ( .A(n1806), .B(n956), .Y(n2735) );
NOR2X4TS U3032 ( .A(n1803), .B(n2671), .Y(n1804) );
OAI21X2TS U3033 ( .A0(n1808), .A1(n2732), .B0(n2711), .Y(n2719) );
NAND2X2TS U3034 ( .A(n2683), .B(n2811), .Y(n2685) );
AOI21X2TS U3035 ( .A0(n2683), .A1(n2682), .B0(n2681), .Y(n2684) );
INVX6TS U3036 ( .A(n2729), .Y(n3028) );
INVX2TS U3037 ( .A(n2921), .Y(n3030) );
NAND2X4TS U3038 ( .A(n1065), .B(n1064), .Y(n1077) );
XNOR2X1TS U3039 ( .A(n2815), .B(n988), .Y(n3038) );
OAI22X1TS U3040 ( .A0(n2907), .A1(n3062), .B0(n1038), .B1(n3081), .Y(n3001)
);
ADDFX2TS U3041 ( .A(n2046), .B(n2045), .CI(n2044), .CO(n2377), .S(n2349) );
ADDFHX2TS U3042 ( .A(n2039), .B(n2038), .CI(n2037), .CO(n2348), .S(n2355) );
ADDFHX2TS U3043 ( .A(n2145), .B(n2144), .CI(n2143), .CO(n2409), .S(n2400) );
NOR2X1TS U3044 ( .A(DP_OP_498J311_124_1725_n721), .B(
DP_OP_498J311_124_1725_n728), .Y(n2145) );
NOR2X1TS U3045 ( .A(DP_OP_498J311_124_1725_n722), .B(
DP_OP_498J311_124_1725_n727), .Y(n2144) );
ADDFX2TS U3046 ( .A(n1639), .B(n1638), .CI(n1637), .CO(n1682), .S(n1636) );
ADDFHX2TS U3047 ( .A(n1470), .B(n1469), .CI(n1468), .CO(n1491), .S(n1438) );
INVX2TS U3048 ( .A(n1449), .Y(n1124) );
INVX2TS U3049 ( .A(n1623), .Y(n1358) );
OR2X4TS U3050 ( .A(n1345), .B(n1344), .Y(n1129) );
ADDFHX2TS U3051 ( .A(n1412), .B(n1413), .CI(n1411), .CO(n1437), .S(n1382) );
NOR2X1TS U3052 ( .A(n3538), .B(n3566), .Y(n3541) );
OAI21X1TS U3053 ( .A0(n3539), .A1(n3566), .B0(n3569), .Y(n3540) );
NAND2X1TS U3054 ( .A(n3545), .B(n3568), .Y(n3546) );
ADDFHX2TS U3055 ( .A(n3050), .B(n3049), .CI(n3048), .CO(n2969), .S(n3071) );
ADDFHX2TS U3056 ( .A(n3068), .B(n3067), .CI(n3066), .CO(n3047), .S(n3069) );
NOR2X1TS U3057 ( .A(DP_OP_498J311_124_1725_n634), .B(n2189), .Y(n2074) );
AND2X2TS U3058 ( .A(n3389), .B(n1138), .Y(n3394) );
OR2X1TS U3059 ( .A(n3388), .B(n3387), .Y(n3389) );
INVX2TS U3060 ( .A(n3396), .Y(n1138) );
ADDFX2TS U3061 ( .A(n2269), .B(n2268), .CI(n2267), .CO(n2273), .S(n2244) );
NAND2X2TS U3062 ( .A(DP_OP_496J311_122_3540_n1456), .B(
DP_OP_496J311_122_3540_n1467), .Y(n2669) );
INVX2TS U3063 ( .A(n3435), .Y(n1140) );
XOR2X1TS U3064 ( .A(n1174), .B(n1172), .Y(n1866) );
INVX2TS U3065 ( .A(n2903), .Y(n2932) );
INVX2TS U3066 ( .A(n3544), .Y(n3023) );
XNOR2X1TS U3067 ( .A(n1919), .B(n1913), .Y(n1888) );
XNOR2X1TS U3068 ( .A(n1911), .B(n1938), .Y(n1881) );
OAI22X1TS U3069 ( .A0(n1887), .A1(n1895), .B0(n1858), .B1(n3168), .Y(n1882)
);
NAND2X1TS U3070 ( .A(n5599), .B(n5618), .Y(n2660) );
XNOR2X1TS U3071 ( .A(n3037), .B(n988), .Y(n3225) );
NOR2X1TS U3072 ( .A(n1912), .B(n2631), .Y(n1923) );
NAND2X1TS U3073 ( .A(n1623), .B(n1622), .Y(n1670) );
NOR2X1TS U3074 ( .A(n932), .B(DP_OP_497J311_123_1725_n719), .Y(n1557) );
AOI21X2TS U3075 ( .A0(n1749), .A1(n1715), .B0(n1714), .Y(n1104) );
NAND2X1TS U3076 ( .A(n1743), .B(n1715), .Y(n1105) );
ADDFX2TS U3077 ( .A(n1296), .B(n1295), .CI(n1294), .CO(n1343), .S(n1280) );
OAI22X1TS U3078 ( .A0(n1050), .A1(n1497), .B0(n5545), .B1(n1534), .Y(n1295)
);
INVX2TS U3079 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .Y(n3531) );
INVX2TS U3080 ( .A(n4610), .Y(n3532) );
INVX2TS U3081 ( .A(n3505), .Y(n3179) );
INVX2TS U3082 ( .A(n4511), .Y(n3511) );
INVX2TS U3083 ( .A(FPMULT_Sgf_operation_Result[8]), .Y(n3500) );
NOR2X1TS U3084 ( .A(DP_OP_497J311_123_1725_n324), .B(n1214), .Y(n1231) );
NOR2X2TS U3085 ( .A(DP_OP_497J311_123_1725_n628), .B(n5554), .Y(n1232) );
INVX2TS U3086 ( .A(n3183), .Y(n3130) );
NAND2X2TS U3087 ( .A(n3094), .B(n3093), .Y(n3097) );
INVX2TS U3088 ( .A(n3186), .Y(n3092) );
ADDFHX2TS U3089 ( .A(n3071), .B(n3070), .CI(n3069), .CO(n3096), .S(n3098) );
INVX2TS U3090 ( .A(n2435), .Y(n2437) );
NAND2X1TS U3091 ( .A(n3405), .B(n3404), .Y(n3700) );
XNOR2X1TS U3092 ( .A(n3370), .B(n3417), .Y(n3407) );
INVX2TS U3093 ( .A(n2516), .Y(n2243) );
INVX2TS U3094 ( .A(n2669), .Y(n1102) );
OR2X6TS U3095 ( .A(n2580), .B(n2579), .Y(n3694) );
NAND2X1TS U3096 ( .A(n4197), .B(n4228), .Y(n4202) );
NOR2X1TS U3097 ( .A(n4071), .B(n4055), .Y(n4057) );
XOR2X1TS U3098 ( .A(n3430), .B(n1135), .Y(n3439) );
NAND2X1TS U3099 ( .A(n1134), .B(n3462), .Y(n3430) );
NAND2X1TS U3100 ( .A(n3453), .B(n3461), .Y(n3454) );
AOI32X1TS U3101 ( .A0(n5820), .A1(n5130), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n5725), .Y(n5131) );
NOR2BX1TS U3102 ( .AN(n1834), .B(n3168), .Y(n3946) );
NAND2X1TS U3103 ( .A(n2823), .B(n2801), .Y(n2826) );
NAND2X4TS U3104 ( .A(n1137), .B(n1620), .Y(n1087) );
NAND2X2TS U3105 ( .A(n1662), .B(n1663), .Y(n1675) );
AOI21X1TS U3106 ( .A0(n1430), .A1(n1370), .B0(n1369), .Y(n1118) );
NAND2X2TS U3107 ( .A(n1178), .B(DP_OP_497J311_123_1725_n792), .Y(n1272) );
NAND2X2TS U3108 ( .A(n3193), .B(n3192), .Y(n3589) );
INVX2TS U3109 ( .A(n3688), .Y(n3938) );
AOI21X1TS U3110 ( .A0(n3598), .A1(n1177), .B0(n3597), .Y(n3600) );
XOR2X2TS U3111 ( .A(n2542), .B(n2488), .Y(n2506) );
NAND2X1TS U3112 ( .A(n2487), .B(n2520), .Y(n2488) );
XOR2X1TS U3113 ( .A(n2493), .B(n2492), .Y(n2505) );
NAND2X1TS U3114 ( .A(n2491), .B(n2490), .Y(n2493) );
NOR2X1TS U3115 ( .A(n2228), .B(n2227), .Y(n2500) );
OAI21X2TS U3116 ( .A0(n2542), .A1(n2511), .B0(n2510), .Y(n2515) );
NAND2X1TS U3117 ( .A(n3658), .B(n3657), .Y(n3660) );
INVX2TS U3118 ( .A(n3705), .Y(n3651) );
NAND2X1TS U3119 ( .A(n3407), .B(n3406), .Y(n3647) );
OR2X2TS U3120 ( .A(n3405), .B(n3404), .Y(n3701) );
NAND2X1TS U3121 ( .A(n3694), .B(n3601), .Y(n3603) );
NOR2X1TS U3122 ( .A(DP_OP_498J311_124_1725_n726), .B(
DP_OP_498J311_124_1725_n732), .Y(n2576) );
INVX4TS U3123 ( .A(n2865), .Y(n3167) );
ADDHX1TS U3124 ( .A(DP_OP_498J311_124_1725_n618), .B(n1997), .CO(n2011), .S(
n2207) );
INVX2TS U3125 ( .A(n3657), .Y(n3424) );
NAND2X1TS U3126 ( .A(n3439), .B(n3438), .Y(n3669) );
INVX2TS U3127 ( .A(n3455), .Y(n1143) );
AOI211X2TS U3128 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n5745), .B0(n5088),
.C0(n5086), .Y(n5141) );
AOI211X1TS U3129 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5237), .B0(n5133),
.C0(n5134), .Y(n5125) );
NAND2X1TS U3130 ( .A(n2527), .B(n1186), .Y(n2529) );
OR2X1TS U3131 ( .A(n2974), .B(n2985), .Y(n2634) );
NOR2X1TS U3132 ( .A(n5005), .B(n4842), .Y(n4869) );
OAI21X1TS U3133 ( .A0(n4842), .A1(n5004), .B0(n4841), .Y(n4870) );
NAND2X1TS U3134 ( .A(n3705), .B(n928), .Y(n3708) );
INVX2TS U3135 ( .A(n3706), .Y(n3707) );
NAND2X2TS U3136 ( .A(n3896), .B(n3894), .Y(n3750) );
NAND2X1TS U3137 ( .A(n3900), .B(n3899), .Y(n3901) );
ADDFHX2TS U3138 ( .A(n3275), .B(n3274), .CI(n3273), .CO(n3290), .S(n3232) );
INVX2TS U3139 ( .A(n3778), .Y(n1074) );
XNOR2X2TS U3140 ( .A(n3827), .B(n948), .Y(n3828) );
NAND2X1TS U3141 ( .A(n3869), .B(n3868), .Y(n3870) );
NAND2X1TS U3142 ( .A(n2903), .B(n2933), .Y(n2618) );
OAI21X2TS U3143 ( .A0(n2602), .A1(n3825), .B0(n2601), .Y(n2614) );
NAND2X1TS U3144 ( .A(n1743), .B(n1748), .Y(n1751) );
INVX2TS U3145 ( .A(n1743), .Y(n1679) );
NAND2X1TS U3146 ( .A(n1313), .B(n1236), .Y(n1237) );
NAND2X1TS U3147 ( .A(n1370), .B(n1427), .Y(n1323) );
NOR2X2TS U3148 ( .A(n3587), .B(n3586), .Y(n4006) );
INVX2TS U3149 ( .A(n3809), .Y(n3558) );
AND2X4TS U3150 ( .A(n1178), .B(n5565), .Y(n1210) );
OR2X2TS U3151 ( .A(n2506), .B(n2505), .Y(n3448) );
INVX2TS U3152 ( .A(n3433), .Y(n3449) );
NAND2X2TS U3153 ( .A(n2533), .B(n2532), .Y(n3495) );
NOR2X4TS U3154 ( .A(n2570), .B(n2569), .Y(n3548) );
INVX2TS U3155 ( .A(n3512), .Y(n2554) );
NOR2X4TS U3156 ( .A(n3710), .B(n3763), .Y(n4181) );
NOR2X4TS U3157 ( .A(n3714), .B(n3801), .Y(n4173) );
NAND2X1TS U3158 ( .A(n3747), .B(n3713), .Y(n4177) );
OR2X4TS U3159 ( .A(n2553), .B(n2552), .Y(n3513) );
AOI221X1TS U3160 ( .A0(n972), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[13]), .B1(n943), .C0(n5172), .Y(n5173) );
NOR2X2TS U3161 ( .A(n4268), .B(n4277), .Y(n4331) );
INVX2TS U3162 ( .A(n4266), .Y(n1036) );
NOR2X2TS U3163 ( .A(DP_OP_498J311_124_1725_n638), .B(n2168), .Y(n1995) );
INVX2TS U3164 ( .A(n4006), .Y(n4008) );
INVX2TS U3165 ( .A(n4451), .Y(n4471) );
OR2X2TS U3166 ( .A(n2531), .B(n2530), .Y(n3493) );
INVX2TS U3167 ( .A(n3336), .Y(n3494) );
INVX2TS U3168 ( .A(n5046), .Y(n5048) );
INVX2TS U3169 ( .A(n4837), .Y(n4839) );
BUFX3TS U3170 ( .A(n5331), .Y(n5307) );
INVX2TS U3171 ( .A(n4798), .Y(n4800) );
INVX2TS U3172 ( .A(n4820), .Y(n4822) );
INVX2TS U3173 ( .A(n5024), .Y(n5013) );
BUFX3TS U3174 ( .A(n4517), .Y(n5375) );
INVX2TS U3175 ( .A(n5037), .Y(n5039) );
CLKBUFX2TS U3176 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n5071) );
CLKAND2X2TS U3177 ( .A(n5794), .B(FPADDSUB_DMP_SFG[22]), .Y(n4953) );
INVX2TS U3178 ( .A(n3801), .Y(n3967) );
INVX2TS U3179 ( .A(n3838), .Y(n3272) );
INVX2TS U3180 ( .A(n3731), .Y(n3257) );
NAND2X1TS U3181 ( .A(n3247), .B(n3246), .Y(n3248) );
OR2X6TS U3182 ( .A(n3961), .B(n3960), .Y(n3984) );
NAND2X2TS U3183 ( .A(n1082), .B(n2641), .Y(n1081) );
INVX2TS U3184 ( .A(n1709), .Y(n1097) );
INVX2TS U3185 ( .A(n1710), .Y(n1098) );
OR2X4TS U3186 ( .A(n1483), .B(n1482), .Y(n3358) );
AND2X2TS U3187 ( .A(n4017), .B(n3718), .Y(n1161) );
NOR2X6TS U3188 ( .A(n4020), .B(n4033), .Y(n3718) );
INVX2TS U3189 ( .A(n3330), .Y(n3334) );
INVX2TS U3190 ( .A(n3339), .Y(n3341) );
NAND2X2TS U3191 ( .A(n1379), .B(n1378), .Y(n3347) );
NAND2X1TS U3192 ( .A(n1298), .B(n1292), .Y(n3303) );
INVX2TS U3193 ( .A(n3926), .Y(n4011) );
AND2X2TS U3194 ( .A(n3373), .B(n1146), .Y(n3609) );
OR2X4TS U3195 ( .A(n3959), .B(n3958), .Y(n3982) );
INVX2TS U3196 ( .A(n4055), .Y(n4050) );
AOI21X1TS U3197 ( .A0(n4944), .A1(n4943), .B0(n4160), .Y(n4952) );
INVX2TS U3198 ( .A(n4350), .Y(n4352) );
NOR2XLTS U3199 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n3610) );
BUFX3TS U3200 ( .A(n4517), .Y(n5379) );
BUFX3TS U3201 ( .A(n4517), .Y(n5327) );
MX2X1TS U3202 ( .A(FPADDSUB_N60), .B(n5072), .S0(n5071), .Y(
FPADDSUB_Raw_mant_SGF[1]) );
XNOR2X1TS U3203 ( .A(n1953), .B(n1952), .Y(n3912) );
MX2X1TS U3204 ( .A(n5065), .B(n5064), .S0(n5071), .Y(
FPADDSUB_Raw_mant_SGF[3]) );
MX2X1TS U3205 ( .A(n5057), .B(n5056), .S0(n5071), .Y(
FPADDSUB_Raw_mant_SGF[4]) );
MX2X1TS U3206 ( .A(n5070), .B(n5069), .S0(n5071), .Y(
FPADDSUB_Raw_mant_SGF[2]) );
CLKAND2X2TS U3207 ( .A(n5067), .B(n5066), .Y(n5070) );
OAI31X1TS U3208 ( .A0(n5443), .A1(FPSENCOS_cont_var_out[1]), .A2(n5730),
.B0(n4737), .Y(n842) );
NAND2X1TS U3209 ( .A(n4011), .B(n4010), .Y(add_x_69_n22) );
INVX2TS U3210 ( .A(DP_OP_499J311_125_1651_n83), .Y(n3977) );
NAND2X4TS U3211 ( .A(n3965), .B(n3964), .Y(DP_OP_499J311_125_1651_n84) );
NAND2X1TS U3212 ( .A(n3985), .B(n3984), .Y(DP_OP_499J311_125_1651_n13) );
INVX4TS U3213 ( .A(DP_OP_499J311_125_1651_n74), .Y(
DP_OP_499J311_125_1651_n72) );
NAND2X1TS U3214 ( .A(n3779), .B(n3778), .Y(n3780) );
XOR2X2TS U3215 ( .A(n3861), .B(n3860), .Y(n3936) );
INVX2TS U3216 ( .A(n3915), .Y(n3860) );
NAND2X1TS U3217 ( .A(n3916), .B(n3915), .Y(n3917) );
INVX2TS U3218 ( .A(n3914), .Y(n3916) );
NAND2X4TS U3219 ( .A(n3873), .B(n3872), .Y(n3876) );
NAND2X1TS U3220 ( .A(n3333), .B(n3332), .Y(n3335) );
XNOR2X2TS U3221 ( .A(n3343), .B(n3340), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[8]) );
NAND2X1TS U3222 ( .A(n3342), .B(n3339), .Y(n3340) );
AO21X1TS U3223 ( .A0(n3342), .A1(n3343), .B0(n3341), .Y(n1114) );
INVX2TS U3224 ( .A(add_x_69_n243), .Y(add_x_69_n241) );
NAND2X1TS U3225 ( .A(n3316), .B(n3315), .Y(n3318) );
INVX2TS U3226 ( .A(n1247), .Y(n3326) );
NAND2X1TS U3227 ( .A(n4004), .B(n4027), .Y(add_x_69_n24) );
NAND2X1TS U3228 ( .A(n4001), .B(n4000), .Y(add_x_69_n23) );
NAND2X1TS U3229 ( .A(n4032), .B(n4031), .Y(add_x_69_n21) );
OAI21X1TS U3230 ( .A0(add_x_69_n271), .A1(n3735), .B0(n3734), .Y(
add_x_69_n257) );
OAI21X1TS U3231 ( .A0(add_x_69_n271), .A1(add_x_69_n244), .B0(n4026), .Y(
add_x_69_n239) );
INVX2TS U3232 ( .A(add_x_69_n238), .Y(add_x_69_n236) );
INVX2TS U3233 ( .A(n3310), .Y(n3312) );
NAND2X1TS U3234 ( .A(n1147), .B(n3609), .Y(add_x_69_n231) );
NAND2X1TS U3235 ( .A(n4035), .B(n4034), .Y(add_x_69_n26) );
INVX2TS U3236 ( .A(n4033), .Y(n4035) );
AND2X2TS U3237 ( .A(n3331), .B(n3330), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[6]) );
OAI31X1TS U3238 ( .A0(n937), .A1(n4735), .A2(n5711), .B0(n4734), .Y(
FPMULT_FS_Module_state_next[1]) );
OR2X1TS U3239 ( .A(FPSENCOS_d_ff_Xn[28]), .B(n5258), .Y(
FPSENCOS_first_mux_X[28]) );
AND3X1TS U3240 ( .A(n4500), .B(n4499), .C(n4498), .Y(n5755) );
AND3X1TS U3241 ( .A(n4476), .B(n4475), .C(n4474), .Y(n5759) );
AND3X1TS U3242 ( .A(n4479), .B(n4478), .C(n4477), .Y(n5760) );
AND3X1TS U3243 ( .A(n4482), .B(n4481), .C(n4480), .Y(n5761) );
AND3X1TS U3244 ( .A(n4485), .B(n4484), .C(n4483), .Y(n5763) );
AND3X1TS U3245 ( .A(n4488), .B(n4487), .C(n4486), .Y(n5762) );
AND3X1TS U3246 ( .A(n4491), .B(n4490), .C(n4489), .Y(n5757) );
AND3X1TS U3247 ( .A(n4494), .B(n4493), .C(n4492), .Y(n5758) );
AND3X1TS U3248 ( .A(n4504), .B(n4503), .C(n4502), .Y(n5754) );
AND3X1TS U3249 ( .A(n4497), .B(n4496), .C(n4495), .Y(n5756) );
AOI222X1TS U3250 ( .A0(n5462), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n4501), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(
n5074), .Y(n6020) );
AOI222X1TS U3251 ( .A0(n5462), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n5074), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n5302), .Y(n6021) );
AOI222X1TS U3252 ( .A0(n5462), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n5074), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n4501), .Y(n6022) );
AOI222X1TS U3253 ( .A0(n5462), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n5074), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n5302), .Y(n6024) );
XOR2X1TS U3254 ( .A(n4172), .B(n4176), .Y(n4193) );
OR4X2TS U3255 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n4598), .Y(n4599) );
OR2X1TS U3256 ( .A(n3308), .B(n3307), .Y(n3309) );
NAND2X1TS U3257 ( .A(n3300), .B(n3299), .Y(n3302) );
XOR2X1TS U3258 ( .A(n3298), .B(n3297), .Y(FPMULT_Sgf_operation_Result[4]) );
XOR2X1TS U3259 ( .A(n3323), .B(n3322), .Y(FPMULT_Sgf_operation_Result[5]) );
AND2X2TS U3260 ( .A(n4022), .B(n4021), .Y(n984) );
OR2X1TS U3261 ( .A(FPSENCOS_d_ff_Xn[7]), .B(n4507), .Y(
FPSENCOS_first_mux_X[7]) );
OR2X1TS U3262 ( .A(FPSENCOS_d_ff_Xn[3]), .B(n4507), .Y(
FPSENCOS_first_mux_X[3]) );
CLKBUFX3TS U3263 ( .A(n1059), .Y(n6004) );
OR2X1TS U3264 ( .A(FPSENCOS_d_ff_Xn[1]), .B(n4507), .Y(
FPSENCOS_first_mux_X[1]) );
OR2X1TS U3265 ( .A(FPSENCOS_d_ff_Xn[5]), .B(n4507), .Y(
FPSENCOS_first_mux_X[5]) );
OR2X1TS U3266 ( .A(FPSENCOS_d_ff_Xn[2]), .B(n4507), .Y(
FPSENCOS_first_mux_X[2]) );
NAND2BXLTS U3267 ( .AN(FPADDSUB_intDX_EWSW[30]), .B(n5246), .Y(
FPADDSUB_DMP_INIT_EWSW[30]) );
INVX2TS U3268 ( .A(rst), .Y(n824) );
CLKAND2X2TS U3269 ( .A(n5383), .B(n5710), .Y(n857) );
NAND2X4TS U3270 ( .A(n3467), .B(n3466), .Y(n3518) );
XNOR2X4TS U3271 ( .A(n3542), .B(n3468), .Y(n3490) );
OAI21X2TS U3272 ( .A0(n1159), .A1(DP_OP_497J311_123_1725_n385), .B0(
DP_OP_497J311_123_1725_n386), .Y(n1286) );
NOR2X4TS U3273 ( .A(n3766), .B(n3738), .Y(n1632) );
NAND2X4TS U3274 ( .A(n1630), .B(n1629), .Y(n3739) );
OAI21X4TS U3275 ( .A0(n2911), .A1(n3847), .B0(n2829), .Y(n2892) );
OAI22X2TS U3276 ( .A0(n3102), .A1(n3081), .B0(n1038), .B1(n3080), .Y(n3121)
);
ADDFHX2TS U3277 ( .A(n2983), .B(n2982), .CI(n2981), .CO(n3544), .S(n3521) );
ADDFHX2TS U3278 ( .A(n3129), .B(n3128), .CI(n3127), .CO(n3191), .S(n3131) );
INVX12TS U3279 ( .A(n2596), .Y(n3823) );
INVX2TS U3280 ( .A(n2415), .Y(n2321) );
INVX2TS U3281 ( .A(n4053), .Y(n1024) );
OR2X1TS U3282 ( .A(n1048), .B(n967), .Y(n941) );
OR2X1TS U3283 ( .A(n5960), .B(rst), .Y(n947) );
OAI22X2TS U3284 ( .A0(n1890), .A1(n3168), .B0(n1834), .B1(n1895), .Y(n1891)
);
NAND2X4TS U3285 ( .A(n1098), .B(n1097), .Y(n3887) );
XNOR2X2TS U3286 ( .A(FPMULT_Op_MY[10]), .B(n2698), .Y(n1814) );
INVX2TS U3287 ( .A(n3324), .Y(n1113) );
INVX2TS U3288 ( .A(n1135), .Y(n3465) );
OA21X4TS U3289 ( .A0(n2690), .A1(n2671), .B0(n1805), .Y(n956) );
AO21X4TS U3290 ( .A0(n4180), .A1(n3712), .B0(n3711), .Y(n957) );
OAI21X4TS U3291 ( .A0(n1993), .A1(n1164), .B0(n949), .Y(n959) );
NOR2X4TS U3292 ( .A(n1618), .B(n1619), .Y(n1674) );
INVX2TS U3293 ( .A(n1134), .Y(n3460) );
NOR2X1TS U3294 ( .A(n3437), .B(n3436), .Y(n961) );
INVX2TS U3295 ( .A(n5188), .Y(n1021) );
OAI21X1TS U3296 ( .A0(n2613), .A1(n2612), .B0(n2611), .Y(n962) );
OR2X1TS U3297 ( .A(n1046), .B(n1047), .Y(n967) );
INVX2TS U3298 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n4685) );
INVX2TS U3299 ( .A(n4774), .Y(n4757) );
CLKINVX3TS U3300 ( .A(n5437), .Y(n5941) );
XNOR2X2TS U3301 ( .A(n3515), .B(n3514), .Y(n4610) );
ADDFX2TS U3302 ( .A(n3016), .B(n3015), .CI(n3014), .CO(n3230), .S(n3040) );
INVX12TS U3303 ( .A(n1066), .Y(n2881) );
OR2X4TS U3304 ( .A(n2532), .B(n2533), .Y(n3496) );
OAI22X2TS U3305 ( .A0(n2174), .A1(n2109), .B0(n2224), .B1(n2146), .Y(n2256)
);
OAI22X2TS U3306 ( .A0(n2224), .A1(n2210), .B0(n2226), .B1(n2209), .Y(n2191)
);
ADDFHX2TS U3307 ( .A(n2943), .B(n2942), .CI(n2941), .CO(n3005), .S(n2944) );
ADDFHX2TS U3308 ( .A(n2968), .B(n2967), .CI(n2966), .CO(n2942), .S(n3046) );
XNOR2X2TS U3309 ( .A(n2703), .B(n2727), .Y(n2704) );
CLKINVX6TS U3310 ( .A(n2699), .Y(n2663) );
XNOR2X4TS U3311 ( .A(n1033), .B(n2788), .Y(n2871) );
INVX4TS U3312 ( .A(n3790), .Y(n3773) );
NAND2X4TS U3313 ( .A(n2706), .B(n1168), .Y(n2911) );
XOR2X4TS U3314 ( .A(n2786), .B(n2785), .Y(n2787) );
NAND2X1TS U3315 ( .A(n2784), .B(n2871), .Y(n2785) );
CLKINVX3TS U3316 ( .A(n3993), .Y(n5947) );
OAI22X1TS U3317 ( .A0(n985), .A1(n1596), .B0(n1050), .B1(n1652), .Y(n1458)
);
INVX4TS U3318 ( .A(n988), .Y(n989) );
CLKBUFX2TS U3319 ( .A(n1029), .Y(n5914) );
INVX4TS U3320 ( .A(n1287), .Y(n993) );
OAI22X2TS U3321 ( .A0(n1611), .A1(n1467), .B0(n985), .B1(n1503), .Y(n1345)
);
OAI22X2TS U3322 ( .A0(n1661), .A1(n1596), .B0(n993), .B1(n1652), .Y(n1563)
);
INVX2TS U3323 ( .A(n1287), .Y(n1611) );
OAI22X1TS U3324 ( .A0(n2816), .A1(n995), .B0(n2776), .B1(n2832), .Y(n2902)
);
OAI22X2TS U3325 ( .A0(n2776), .A1(n2875), .B0(n995), .B1(n2832), .Y(n2842)
);
INVX2TS U3326 ( .A(n947), .Y(n996) );
INVX2TS U3327 ( .A(n947), .Y(n997) );
CLKINVX3TS U3328 ( .A(n5437), .Y(n5945) );
CLKINVX3TS U3329 ( .A(n5437), .Y(n5942) );
CLKINVX3TS U3330 ( .A(n5437), .Y(n5943) );
INVX2TS U3331 ( .A(n1053), .Y(n1001) );
INVX2TS U3332 ( .A(n1053), .Y(n1002) );
INVX2TS U3333 ( .A(n964), .Y(n1004) );
INVX2TS U3334 ( .A(n964), .Y(n1005) );
INVX2TS U3335 ( .A(n963), .Y(n1006) );
INVX2TS U3336 ( .A(n963), .Y(n1007) );
INVX2TS U3337 ( .A(n4535), .Y(n1008) );
INVX2TS U3338 ( .A(n1008), .Y(n1009) );
INVX2TS U3339 ( .A(n1008), .Y(n1010) );
INVX2TS U3340 ( .A(n939), .Y(n1012) );
INVX2TS U3341 ( .A(n5871), .Y(n1013) );
INVX2TS U3342 ( .A(n1013), .Y(n1014) );
INVX2TS U3343 ( .A(n1015), .Y(n1016) );
INVX2TS U3344 ( .A(n1015), .Y(n1017) );
INVX2TS U3345 ( .A(n5189), .Y(n1018) );
INVX2TS U3346 ( .A(n1018), .Y(n1019) );
INVX2TS U3347 ( .A(n1021), .Y(n1022) );
INVX2TS U3348 ( .A(n1024), .Y(n1025) );
OAI21X1TS U3349 ( .A0(n5302), .A1(n5796), .B0(FPADDSUB_Shift_reg_FLAGS_7[1]),
.Y(n4705) );
OAI21X1TS U3350 ( .A0(n4663), .A1(n5797), .B0(n4662), .Y(n4661) );
BUFX3TS U3351 ( .A(n5963), .Y(n6007) );
CLKBUFX3TS U3352 ( .A(n5838), .Y(n5542) );
NOR4X2TS U3353 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n4308) );
AOI221X1TS U3354 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n5246), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n5244), .C0(n5087), .Y(n5089) );
OAI221X1TS U3355 ( .A0(n5246), .A1(FPADDSUB_intDX_EWSW[30]), .B0(n981), .B1(
FPADDSUB_intDY_EWSW[20]), .C0(n5165), .Y(n5179) );
INVX2TS U3356 ( .A(FPADDSUB_intDY_EWSW[30]), .Y(n5246) );
CLKBUFX3TS U3357 ( .A(n6002), .Y(n6005) );
OAI32X1TS U3358 ( .A0(n5711), .A1(n5728), .A2(n5718), .B0(
FPMULT_FS_Module_state_reg[1]), .B1(n4471), .Y(
FPMULT_FS_Module_state_next[2]) );
CLKBUFX3TS U3359 ( .A(n6005), .Y(n6006) );
OAI21X2TS U3360 ( .A0(n5863), .A1(n1011), .B0(n4621), .Y(n4739) );
OAI21X2TS U3361 ( .A0(n5853), .A1(n931), .B0(n4555), .Y(n4666) );
OAI21X2TS U3362 ( .A0(n5863), .A1(n931), .B0(n4645), .Y(n4746) );
OAI21X2TS U3363 ( .A0(n4638), .A1(n4745), .B0(n4637), .Y(n4698) );
OAI21X2TS U3364 ( .A0(n5865), .A1(n1014), .B0(n4532), .Y(n4682) );
NOR2X4TS U3365 ( .A(n5709), .B(n5710), .Y(n5428) );
NAND2X4TS U3366 ( .A(n1003), .B(n4685), .Y(n4699) );
BUFX3TS U3367 ( .A(n6008), .Y(n5962) );
CLKBUFX3TS U3368 ( .A(n5966), .Y(n5504) );
BUFX3TS U3369 ( .A(n1029), .Y(n4439) );
NAND2BX1TS U3370 ( .AN(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n5194) );
NAND2X1TS U3371 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n979),
.Y(n5440) );
OAI221X1TS U3372 ( .A0(n945), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n983), .B1(
FPADDSUB_intDY_EWSW[0]), .C0(n5151), .Y(n5154) );
INVX2TS U3373 ( .A(n975), .Y(n1028) );
AOI211X1TS U3374 ( .A0(n4167), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(n4166),
.C0(n4720), .Y(n4170) );
AOI21X2TS U3375 ( .A0(n5302), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(n4705),
.Y(n6014) );
AOI221X1TS U3376 ( .A0(n940), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[27]), .B1(n966), .C0(n5167), .Y(n5168) );
CLKINVX3TS U3377 ( .A(n3993), .Y(n5952) );
CLKBUFX3TS U3378 ( .A(n6004), .Y(n5966) );
OAI221XLTS U3379 ( .A0(n978), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n942), .B1(
FPADDSUB_intDY_EWSW[3]), .C0(n5152), .Y(n5153) );
OAI221X1TS U3380 ( .A0(n5244), .A1(FPADDSUB_intDX_EWSW[29]), .B0(n980), .B1(
FPADDSUB_intDY_EWSW[18]), .C0(n5149), .Y(n5156) );
AOI221X1TS U3381 ( .A0(n5225), .A1(FPADDSUB_intDY_EWSW[10]), .B0(
FPADDSUB_intDY_EWSW[11]), .B1(n969), .C0(n5171), .Y(n5174) );
OAI221X1TS U3382 ( .A0(n977), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n5237), .B1(
FPADDSUB_intDY_EWSW[16]), .C0(n5159), .Y(n5162) );
OAI221XLTS U3383 ( .A0(n944), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n982), .B1(
FPADDSUB_intDY_EWSW[24]), .C0(n5166), .Y(n5178) );
NOR2BX4TS U3384 ( .AN(FPADDSUB_bit_shift_SHT2), .B(n4521), .Y(n4638) );
OAI21X2TS U3385 ( .A0(n5859), .A1(n1014), .B0(n4643), .Y(n4747) );
AOI21X2TS U3386 ( .A0(n4521), .A1(n4751), .B0(n4641), .Y(n4689) );
OAI21X2TS U3387 ( .A0(n5850), .A1(n931), .B0(n4640), .Y(n4751) );
OAI21X2TS U3388 ( .A0(n5859), .A1(n1011), .B0(n4619), .Y(n4752) );
AOI211X2TS U3389 ( .A0(n4521), .A1(n4764), .B0(n4743), .C0(n4548), .Y(n4692)
);
OAI21X2TS U3390 ( .A0(n5858), .A1(n931), .B0(n4543), .Y(n4764) );
OAI21X2TS U3391 ( .A0(n5862), .A1(n1014), .B0(n4550), .Y(n4763) );
OAI21X2TS U3392 ( .A0(n5861), .A1(n931), .B0(n4530), .Y(n4758) );
AOI211X2TS U3393 ( .A0(n4521), .A1(n4759), .B0(n4743), .C0(n4527), .Y(n4680)
);
OAI21X2TS U3394 ( .A0(n5852), .A1(n1014), .B0(n4523), .Y(n4759) );
AOI21X2TS U3395 ( .A0(n4521), .A1(n4762), .B0(n4661), .Y(n4718) );
OAI21X2TS U3396 ( .A0(n5848), .A1(n931), .B0(n4525), .Y(n4762) );
INVX3TS U3397 ( .A(n5437), .Y(n5951) );
BUFX3TS U3398 ( .A(n5789), .Y(n5462) );
INVX2TS U3399 ( .A(n947), .Y(n1029) );
AOI221X1TS U3400 ( .A0(n5235), .A1(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDY_EWSW[9]), .B1(n971), .C0(n5170), .Y(n5175) );
AOI221X1TS U3401 ( .A0(n5236), .A1(FPADDSUB_intDX_EWSW[12]), .B0(
FPADDSUB_intDY_EWSW[2]), .B1(n970), .C0(n5169), .Y(n5176) );
OAI221XLTS U3402 ( .A0(n5781), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n5232),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n5150), .Y(n5155) );
OAI221X1TS U3403 ( .A0(n5231), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n5230), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n5157), .Y(n5164) );
NOR4X4TS U3404 ( .A(n4366), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .D(n5784), .Y(n5960) );
NOR4X2TS U3405 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n4195) );
NAND3BX2TS U3406 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .C(n4562), .Y(n5282) );
OAI22X2TS U3407 ( .A0(n1660), .A1(n1467), .B0(n1032), .B1(n1503), .Y(n1448)
);
OAI22X2TS U3408 ( .A0(n1032), .A1(n1497), .B0(n993), .B1(n1534), .Y(n1450)
);
XNOR2X2TS U3409 ( .A(n2976), .B(n1033), .Y(n2835) );
XNOR2X2TS U3410 ( .A(n2929), .B(n1033), .Y(n2851) );
INVX2TS U3411 ( .A(n4778), .Y(n1034) );
XOR2X1TS U3412 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3611), .Y(
DP_OP_234J311_129_4955_n22) );
INVX2TS U3413 ( .A(n4267), .Y(n1035) );
INVX2TS U3414 ( .A(n1961), .Y(n1037) );
OAI22X1TS U3415 ( .A0(n1040), .A1(n2210), .B0(n994), .B1(n2209), .Y(n2057)
);
INVX2TS U3416 ( .A(n3030), .Y(n1041) );
NAND2X4TS U3417 ( .A(n968), .B(n4774), .Y(n4717) );
BUFX3TS U3418 ( .A(n4043), .Y(n1044) );
BUFX3TS U3419 ( .A(n4043), .Y(n1045) );
NOR2X2TS U3420 ( .A(FPMULT_FSM_selector_C), .B(n4042), .Y(n4043) );
NOR2XLTS U3421 ( .A(n5780), .B(FPADDSUB_intDY_EWSW[14]), .Y(n1046) );
NOR2XLTS U3422 ( .A(FPADDSUB_intDX_EWSW[14]), .B(n5723), .Y(n1047) );
INVX2TS U3423 ( .A(n5168), .Y(n1048) );
AOI31XLTS U3424 ( .A0(n5208), .A1(n5207), .A2(n5206), .B0(dataB[27]), .Y(
n5219) );
OAI21X2TS U3425 ( .A0(n4638), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n4637),
.Y(n4695) );
NOR4X1TS U3426 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5887) );
NOR4X1TS U3427 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n4136),
.Y(n5874) );
NOR4X1TS U3428 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5886) );
OR2X1TS U3429 ( .A(FPSENCOS_d_ff_Xn[26]), .B(n5258), .Y(
FPSENCOS_first_mux_X[26]) );
ADDFHX2TS U3430 ( .A(n1694), .B(n1693), .CI(n1692), .CO(n1723), .S(n1683) );
NOR2X2TS U3431 ( .A(n3709), .B(n3764), .Y(n4600) );
NAND2X1TS U3432 ( .A(n3709), .B(n3764), .Y(n4601) );
NOR3X2TS U3433 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(
n4727) );
NOR2X2TS U3434 ( .A(n5770), .B(n3622), .Y(n4721) );
NAND2X2TS U3435 ( .A(n3432), .B(n3431), .Y(n3433) );
OR2X1TS U3436 ( .A(n3432), .B(n3431), .Y(n3434) );
NOR2X4TS U3437 ( .A(n5712), .B(n5732), .Y(n5384) );
NOR2X2TS U3438 ( .A(n5771), .B(n4735), .Y(n4444) );
OAI21X2TS U3439 ( .A0(n4638), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n4637),
.Y(n4632) );
OAI21X2TS U3440 ( .A0(n4638), .A1(n4756), .B0(n4637), .Y(n4676) );
OAI21X2TS U3441 ( .A0(n5842), .A1(n1012), .B0(n4616), .Y(n4756) );
NAND2X1TS U3442 ( .A(n3329), .B(n3328), .Y(n3330) );
ADDHXLTS U3443 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n3884), .CO(
add_x_246_n2), .S(FPMULT_Adder_M_result_A_adder[22]) );
ADDHXLTS U3444 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n3883), .CO(n4037),
.S(FPMULT_Adder_M_result_A_adder[19]) );
ADDHXLTS U3445 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n3882), .CO(n4126),
.S(FPMULT_Adder_M_result_A_adder[17]) );
ADDHXLTS U3446 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n3881), .CO(n4130),
.S(FPMULT_Adder_M_result_A_adder[9]) );
OR2X1TS U3447 ( .A(n107), .B(FPMULT_FSM_load_second_step), .Y(
FPMULT_FSM_exp_operation_load_result) );
NOR3X2TS U3448 ( .A(n5711), .B(n5718), .C(n4464), .Y(n107) );
NOR2X2TS U3449 ( .A(n4662), .B(n5772), .Y(n4743) );
OAI32X4TS U3450 ( .A0(n1193), .A1(FPSENCOS_d_ff1_operation_out), .A2(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .B0(
FPSENCOS_d_ff1_shift_region_flag_out[0]), .B1(n5222), .Y(n5223) );
OAI21XLTS U3451 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n5821), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n5093) );
INVX2TS U3452 ( .A(n1049), .Y(n1050) );
OAI21XLTS U3453 ( .A0(n5428), .A1(FPSENCOS_cont_iter_out[1]), .B0(n4516),
.Y(n864) );
AOI21X2TS U3454 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n5710), .B0(n4450),
.Y(n4516) );
AOI21X2TS U3455 ( .A0(n4521), .A1(n4753), .B0(n4617), .Y(n4672) );
OAI21X2TS U3456 ( .A0(n5850), .A1(n1011), .B0(n4614), .Y(n4753) );
AOI21X2TS U3457 ( .A0(n4521), .A1(n4769), .B0(n4664), .Y(n4713) );
OAI21X2TS U3458 ( .A0(n5849), .A1(n931), .B0(n4545), .Y(n4769) );
BUFX3TS U3459 ( .A(n5917), .Y(n1051) );
BUFX3TS U3460 ( .A(n5913), .Y(n1052) );
BUFX3TS U3461 ( .A(n1029), .Y(n4443) );
OR2X1TS U3462 ( .A(FPSENCOS_d_ff_Xn[27]), .B(n5258), .Y(
FPSENCOS_first_mux_X[27]) );
INVX2TS U3463 ( .A(n5947), .Y(n1053) );
INVX2TS U3464 ( .A(n1053), .Y(n1054) );
INVX2TS U3465 ( .A(n1053), .Y(n1055) );
INVX2TS U3466 ( .A(n1053), .Y(n1056) );
NOR2X1TS U3467 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4164) );
NOR2X2TS U3468 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n5037) );
NOR2X2TS U3469 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n5046) );
NOR3BX2TS U3470 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n4194),
.C(n4306), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
NOR4BX2TS U3471 ( .AN(n4195), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]),
.C(n4194), .D(n1194), .Y(FPSENCOS_enab_RB3) );
NOR2BX1TS U3472 ( .AN(n3166), .B(n3165), .Y(n3170) );
OAI21XLTS U3473 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n5097), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n5096) );
NAND2X1TS U3474 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n5001) );
CLKBUFX3TS U3475 ( .A(n6006), .Y(n1058) );
CLKBUFX3TS U3476 ( .A(n6006), .Y(n1059) );
BUFX3TS U3477 ( .A(n5962), .Y(n5965) );
OAI21XLTS U3478 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n5440), .B0(n5194), .Y(n874) );
OAI31X1TS U3479 ( .A0(n4164), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n4163),
.B0(n4162), .Y(n4171) );
INVX2TS U3480 ( .A(n1060), .Y(n1061) );
NAND2X1TS U3481 ( .A(FPSENCOS_cont_var_out[1]), .B(n5730), .Y(n4383) );
NOR3BX2TS U3482 ( .AN(FPSENCOS_cont_var_out[1]), .B(n976), .C(
FPSENCOS_cont_var_out[0]), .Y(FPSENCOS_enab_d_ff4_Zn) );
NAND2X4TS U3483 ( .A(n1063), .B(n950), .Y(n2702) );
XOR2X4TS U3484 ( .A(n1063), .B(FPMULT_Op_MY[11]), .Y(n2758) );
XOR2X4TS U3485 ( .A(n2881), .B(n1063), .Y(n2854) );
XNOR2X4TS U3486 ( .A(n2663), .B(n2662), .Y(n1062) );
OAI21X4TS U3487 ( .A0(DP_OP_496J311_122_3540_n1120), .A1(
DP_OP_496J311_122_3540_n1117), .B0(DP_OP_496J311_122_3540_n1118), .Y(
n1071) );
NAND2X4TS U3488 ( .A(n1077), .B(n2773), .Y(n2705) );
NAND2X2TS U3489 ( .A(n2770), .B(n2758), .Y(n1064) );
XOR2X4TS U3490 ( .A(n2697), .B(n2696), .Y(n1066) );
AOI21X4TS U3491 ( .A0(n3984), .A1(n3981), .B0(n1067), .Y(n3962) );
NAND2X4TS U3492 ( .A(n3961), .B(n3960), .Y(n3985) );
BUFX6TS U3493 ( .A(n2927), .Y(n1068) );
XOR2X4TS U3494 ( .A(n2763), .B(n2979), .Y(n2927) );
NAND3X8TS U3495 ( .A(n1075), .B(n1073), .C(n1072), .Y(n3918) );
OAI21X4TS U3496 ( .A0(n3898), .A1(n3894), .B0(n3899), .Y(n3791) );
NAND2X4TS U3497 ( .A(n3199), .B(n3200), .Y(n3899) );
AOI2BB1X4TS U3498 ( .A0N(n3793), .A1N(n3777), .B0(n1074), .Y(n1073) );
NOR2X8TS U3499 ( .A(n3203), .B(n3204), .Y(n3777) );
NAND2X8TS U3500 ( .A(n3196), .B(n3195), .Y(n3897) );
XNOR2X4TS U3501 ( .A(n1077), .B(n2773), .Y(n2874) );
OAI2BB1X4TS U3502 ( .A0N(n1078), .A1N(n1613), .B0(n1079), .Y(n1641) );
OAI21X4TS U3503 ( .A0(n1613), .A1(n1078), .B0(n1612), .Y(n1079) );
XNOR2X4TS U3504 ( .A(n1080), .B(n1613), .Y(n1603) );
XNOR2X4TS U3505 ( .A(n1612), .B(n1614), .Y(n1080) );
OAI21X4TS U3506 ( .A0(n1677), .A1(n1676), .B0(n1675), .Y(n1749) );
NAND2BX4TS U3507 ( .AN(n2640), .B(n2642), .Y(n1082) );
OAI21X4TS U3508 ( .A0(n3889), .A1(n3885), .B0(n3890), .Y(n2642) );
NAND2X4TS U3509 ( .A(n1712), .B(n1711), .Y(n3890) );
NOR2X8TS U3510 ( .A(n1737), .B(n1736), .Y(n2640) );
NAND2X8TS U3511 ( .A(n1085), .B(n3887), .Y(n2639) );
AOI21X4TS U3512 ( .A0(n2637), .A1(n3888), .B0(n2642), .Y(n1740) );
NAND2X8TS U3513 ( .A(n1090), .B(n1088), .Y(n1137) );
OAI2BB1X4TS U3514 ( .A0N(n1092), .A1N(n1641), .B0(n1093), .Y(n1681) );
OAI21X4TS U3515 ( .A0(n1092), .A1(n1641), .B0(n1640), .Y(n1093) );
XOR2X4TS U3516 ( .A(n1094), .B(n1640), .Y(n1634) );
XOR2X4TS U3517 ( .A(n1642), .B(n1641), .Y(n1094) );
XNOR2X4TS U3518 ( .A(n2812), .B(n2813), .Y(n3166) );
NAND2BX4TS U3519 ( .AN(n2867), .B(n2872), .Y(n3146) );
INVX12TS U3520 ( .A(n2639), .Y(n2637) );
XNOR2X4TS U3521 ( .A(n1701), .B(n1700), .Y(n1712) );
OAI21X4TS U3522 ( .A0(n3354), .A1(n3351), .B0(n3352), .Y(n3356) );
AOI21X4TS U3523 ( .A0(n3348), .A1(n3350), .B0(n1380), .Y(n3354) );
OR2X8TS U3524 ( .A(n1329), .B(n1099), .Y(n3350) );
XNOR2X4TS U3525 ( .A(n1103), .B(n1729), .Y(n1737) );
XOR2X4TS U3526 ( .A(n2614), .B(n962), .Y(n3830) );
XNOR2X4TS U3527 ( .A(n1251), .B(n1111), .Y(n3329) );
NAND2X4TS U3528 ( .A(n1112), .B(n3325), .Y(n1111) );
NAND2X4TS U3529 ( .A(n1247), .B(n1113), .Y(n1112) );
AOI21X4TS U3530 ( .A0(n3356), .A1(n3358), .B0(n1484), .Y(n1116) );
OAI21X4TS U3531 ( .A0(n1116), .A1(n3360), .B0(n3361), .Y(n3765) );
CLKXOR2X2TS U3532 ( .A(n3362), .B(n1116), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[13]) );
XOR2X4TS U3533 ( .A(n1117), .B(n1377), .Y(n1378) );
OAI22X4TS U3534 ( .A0(n3761), .A1(n3772), .B0(add_x_69_n105), .B1(n3760),
.Y(n1120) );
OAI2BB1X4TS U3535 ( .A0N(n3904), .A1N(n1120), .B0(n1119), .Y(n3969) );
XOR2X4TS U3536 ( .A(n3742), .B(n3741), .Y(n3754) );
NAND2BX4TS U3537 ( .AN(n1124), .B(n1450), .Y(n1121) );
XOR2X2TS U3538 ( .A(n1448), .B(n1124), .Y(n1123) );
XNOR2X4TS U3539 ( .A(n1666), .B(n1665), .Y(n1710) );
NOR2X4TS U3540 ( .A(n1475), .B(n1474), .Y(n1526) );
XOR2X4TS U3541 ( .A(n1533), .B(n1528), .Y(n1126) );
OAI21X4TS U3542 ( .A0(n4005), .A1(n4006), .B0(n4007), .Y(n1142) );
XOR2X4TS U3543 ( .A(n1343), .B(n1130), .Y(n1305) );
XOR2X4TS U3544 ( .A(n1344), .B(n1345), .Y(n1130) );
OR2X8TS U3545 ( .A(n3503), .B(n3502), .Y(n3728) );
XOR2X4TS U3546 ( .A(n1270), .B(n1133), .Y(n1242) );
XOR2X4TS U3547 ( .A(n1271), .B(n1272), .Y(n1133) );
OAI21X4TS U3548 ( .A0(n3382), .A1(n3379), .B0(n3380), .Y(n3417) );
AOI2BB1X4TS U3549 ( .A0N(n3463), .A1N(n1136), .B0(n3464), .Y(n3576) );
XNOR2X4TS U3550 ( .A(n1137), .B(n1621), .Y(n1630) );
NOR2X8TS U3551 ( .A(n1630), .B(n1629), .Y(n3738) );
AOI21X4TS U3552 ( .A0(n3812), .A1(n3810), .B0(n3558), .Y(n4005) );
XOR2X1TS U3553 ( .A(n3437), .B(n3436), .Y(n1141) );
XNOR2X4TS U3554 ( .A(n3582), .B(n1150), .Y(n4605) );
NAND2X6TS U3555 ( .A(n2587), .B(n2586), .Y(n3705) );
CLKINVX3TS U3556 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .Y(n3949) );
NAND2X6TS U3557 ( .A(n3706), .B(n2588), .Y(n2589) );
ADDFHX4TS U3558 ( .A(n2946), .B(n2945), .CI(n2944), .CO(n3200), .S(n3198) );
XNOR2X2TS U3559 ( .A(n2815), .B(n2972), .Y(n2916) );
XNOR2X2TS U3560 ( .A(n2844), .B(n2972), .Y(n2816) );
CLKXOR2X4TS U3561 ( .A(n2827), .B(n2757), .Y(n2844) );
ADDHX1TS U3562 ( .A(n2892), .B(n2891), .CO(n2906), .S(n2843) );
AO21X1TS U3563 ( .A0(n3444), .A1(n3445), .B0(n3171), .Y(n1158) );
XNOR2X4TS U3564 ( .A(n1857), .B(DP_OP_496J311_122_3540_n846), .Y(n1162) );
XOR2X1TS U3565 ( .A(n2636), .B(n2635), .Y(n1163) );
INVX4TS U3566 ( .A(n3994), .Y(n3802) );
BUFX3TS U3567 ( .A(DP_OP_497J311_123_1725_n687), .Y(n5454) );
CLKXOR2X2TS U3568 ( .A(n3893), .B(n3892), .Y(n3995) );
INVX2TS U3569 ( .A(n1651), .Y(n1794) );
OR2X1TS U3570 ( .A(n1041), .B(n2727), .Y(n1168) );
OR2X1TS U3571 ( .A(n932), .B(n950), .Y(n1169) );
OR2X1TS U3572 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n1171) );
INVX2TS U3573 ( .A(n924), .Y(add_x_69_n113) );
XNOR2X4TS U3574 ( .A(n1982), .B(n1966), .Y(n1173) );
NOR2X1TS U3575 ( .A(n2188), .B(DP_OP_498J311_124_1725_n645), .Y(
FPMULT_Sgf_operation_Result[0]) );
OR2X1TS U3576 ( .A(n3578), .B(n3577), .Y(n1177) );
AND2X2TS U3577 ( .A(n2414), .B(n2420), .Y(n1179) );
AND2X4TS U3578 ( .A(n1969), .B(n1968), .Y(n1180) );
NOR2X1TS U3579 ( .A(DP_OP_497J311_123_1725_n629), .B(n5554), .Y(n1181) );
OA21XLTS U3580 ( .A0(n1801), .A1(n1800), .B0(n1799), .Y(n1184) );
CLKXOR2X2TS U3581 ( .A(n1788), .B(n1787), .Y(n1185) );
INVX2TS U3582 ( .A(n3269), .Y(n3250) );
OR2X1TS U3583 ( .A(n2468), .B(n2467), .Y(n1187) );
NAND2X1TS U3584 ( .A(n5469), .B(DP_OP_496J311_122_3540_n1114), .Y(n2716) );
NOR2X1TS U3585 ( .A(n2791), .B(n2790), .Y(n2792) );
NOR2X4TS U3586 ( .A(n2693), .B(n2879), .Y(n2745) );
OAI21X2TS U3587 ( .A0(n1993), .A1(n1989), .B0(n1991), .Y(n1973) );
NOR2BX2TS U3588 ( .AN(n1166), .B(DP_OP_496J311_122_3540_n1516), .Y(n1836) );
OAI22X1TS U3589 ( .A0(n1661), .A1(n1659), .B0(n993), .B1(n1690), .Y(n1589)
);
XNOR2X2TS U3590 ( .A(n2881), .B(n2879), .Y(n2853) );
INVX2TS U3591 ( .A(n1988), .Y(n2146) );
INVX2TS U3592 ( .A(n1293), .Y(n1596) );
AO21X2TS U3593 ( .A0(n2658), .A1(n5599), .B0(n5598), .Y(n1846) );
AOI21X2TS U3594 ( .A0(n1832), .A1(n2813), .B0(n1826), .Y(n1813) );
NOR2X1TS U3595 ( .A(DP_OP_497J311_123_1725_n715), .B(
DP_OP_497J311_123_1725_n721), .Y(n1336) );
NOR2X1TS U3596 ( .A(DP_OP_497J311_123_1725_n324), .B(
DP_OP_497J311_123_1725_n629), .Y(n1320) );
INVX4TS U3597 ( .A(n1350), .Y(n1661) );
NAND2X1TS U3598 ( .A(n3444), .B(n3443), .Y(n3446) );
NOR2X2TS U3599 ( .A(DP_OP_498J311_124_1725_n634), .B(
DP_OP_498J311_124_1725_n642), .Y(n2121) );
NAND2X4TS U3600 ( .A(n955), .B(n2735), .Y(n1811) );
NAND2X1TS U3601 ( .A(n3567), .B(n3572), .Y(n3575) );
INVX2TS U3602 ( .A(n4510), .Y(n3458) );
INVX2TS U3603 ( .A(n3533), .Y(n3534) );
XOR2X1TS U3604 ( .A(DP_OP_496J311_122_3540_n778), .B(FPMULT_Op_MY[7]), .Y(
n1854) );
NAND2X6TS U3605 ( .A(n1811), .B(n1810), .Y(n2813) );
ADDFHX2TS U3606 ( .A(n1332), .B(n1331), .CI(n1330), .CO(n1383), .S(n1304) );
XOR2X1TS U3607 ( .A(n3383), .B(n3382), .Y(n3405) );
NAND2X1TS U3608 ( .A(n3413), .B(n3427), .Y(n3418) );
NAND2X1TS U3609 ( .A(n5690), .B(n4057), .Y(n4060) );
OR2X1TS U3610 ( .A(n1891), .B(n3751), .Y(n3753) );
NOR2X2TS U3611 ( .A(n2954), .B(n2955), .Y(n3245) );
NOR2X1TS U3612 ( .A(n2094), .B(n2189), .Y(n1998) );
NOR2X1TS U3613 ( .A(n5713), .B(FPADDSUB_DMP_SFG[8]), .Y(n4842) );
NAND2X1TS U3614 ( .A(n2955), .B(n2954), .Y(n3246) );
OAI21X1TS U3615 ( .A0(n1283), .A1(n1282), .B0(n1281), .Y(n1308) );
NAND2X2TS U3616 ( .A(n3678), .B(n3677), .Y(n3679) );
OR2X1TS U3617 ( .A(n5716), .B(FPADDSUB_DMP_SFG[9]), .Y(n4844) );
INVX2TS U3618 ( .A(n4870), .Y(n4871) );
OAI21X2TS U3619 ( .A0(n4181), .A1(n4601), .B0(n4183), .Y(n3711) );
INVX2TS U3620 ( .A(n5014), .Y(n5016) );
AOI21X1TS U3621 ( .A0(n4860), .A1(n4859), .B0(n4858), .Y(n4884) );
CLKXOR2X2TS U3622 ( .A(n3725), .B(n3724), .Y(n3732) );
NOR3XLTS U3623 ( .A(dataB[25]), .B(dataB[31]), .C(n5209), .Y(n5206) );
INVX2TS U3624 ( .A(n3319), .Y(n3321) );
OAI21X2TS U3625 ( .A0(n4884), .A1(n4883), .B0(n4882), .Y(n4998) );
INVX2TS U3626 ( .A(n4025), .Y(n4019) );
XNOR2X2TS U3627 ( .A(n3450), .B(n3449), .Y(n4510) );
OAI211XLTS U3628 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n979), .B0(n5440), .C0(n5194), .Y(n875) );
OR2X4TS U3629 ( .A(n3975), .B(n1163), .Y(n5511) );
ADDHXLTS U3630 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n3880), .CO(n4129),
.S(FPMULT_Adder_M_result_A_adder[11]) );
OR2X1TS U3631 ( .A(FPSENCOS_d_ff_Xn[6]), .B(n4507), .Y(
FPSENCOS_first_mux_X[6]) );
OR2X1TS U3632 ( .A(FPSENCOS_d_ff_Xn[29]), .B(n5258), .Y(
FPSENCOS_first_mux_X[29]) );
OAI211XLTS U3633 ( .A0(n4465), .A1(n4305), .B0(n4304), .C0(n5196), .Y(n855)
);
NOR2X2TS U3634 ( .A(n1224), .B(DP_OP_497J311_123_1725_n635), .Y(n1199) );
ADDFHX4TS U3635 ( .A(n1199), .B(n1198), .CI(n1197), .CO(n1225), .S(n1208) );
ADDFHX2TS U3636 ( .A(n1181), .B(n1201), .CI(n1200), .CO(n1234), .S(n1207) );
NOR2X4TS U3637 ( .A(n1442), .B(n1456), .Y(n1248) );
ADDFHX2TS U3638 ( .A(n1206), .B(n1205), .CI(n1204), .CO(n1209), .S(n1216) );
ADDFHX2TS U3639 ( .A(n1209), .B(n1208), .CI(n1207), .CO(n1456), .S(n1410) );
NOR2X2TS U3640 ( .A(n1248), .B(n3324), .Y(n1223) );
NOR2X2TS U3641 ( .A(DP_OP_497J311_123_1725_n629), .B(
DP_OP_497J311_123_1725_n638), .Y(n1221) );
NOR2X4TS U3642 ( .A(n1224), .B(DP_OP_497J311_123_1725_n638), .Y(n1213) );
NOR2X4TS U3643 ( .A(n1214), .B(n919), .Y(n1212) );
CMPR22X2TS U3644 ( .A(n1213), .B(n1212), .CO(n1219), .S(n1277) );
NOR2X2TS U3645 ( .A(n1277), .B(n5588), .Y(n3310) );
INVX2TS U3646 ( .A(n1272), .Y(n3372) );
INVX2TS U3647 ( .A(n3303), .Y(n1215) );
AOI21X4TS U3648 ( .A0(n3304), .A1(n3305), .B0(n1215), .Y(n3317) );
OAI21X4TS U3649 ( .A0(n3317), .A1(n3314), .B0(n3315), .Y(n1247) );
NAND2X2TS U3650 ( .A(n1410), .B(n1384), .Y(n3325) );
NAND2X2TS U3651 ( .A(n1442), .B(n1456), .Y(n1249) );
AOI21X4TS U3652 ( .A0(n1223), .A1(n1247), .B0(n1222), .Y(n1433) );
NOR2X2TS U3653 ( .A(DP_OP_497J311_123_1725_n629), .B(
DP_OP_497J311_123_1725_n634), .Y(n1263) );
NOR2X1TS U3654 ( .A(DP_OP_497J311_123_1725_n324), .B(n1224), .Y(n1262) );
ADDFHX2TS U3655 ( .A(n1227), .B(n1226), .CI(n1225), .CO(n1260), .S(n1233) );
INVX2TS U3656 ( .A(n1228), .Y(n1266) );
NAND2X2TS U3657 ( .A(n1485), .B(n1504), .Y(n1313) );
NOR2X2TS U3658 ( .A(n1485), .B(n1504), .Y(n1311) );
INVX2TS U3659 ( .A(n3371), .Y(n1276) );
NOR2X4TS U3660 ( .A(n1407), .B(n1165), .Y(n1530) );
INVX2TS U3661 ( .A(n1529), .Y(n1275) );
OAI22X1TS U3662 ( .A0(DP_OP_497J311_123_1725_n335), .A1(n1467), .B0(n5592),
.B1(n1503), .Y(n1241) );
NOR2X2TS U3663 ( .A(n1242), .B(n1241), .Y(n1283) );
INVX2TS U3664 ( .A(n1283), .Y(n1243) );
NOR2X2TS U3665 ( .A(n5592), .B(n1467), .Y(n1256) );
INVX2TS U3666 ( .A(n1256), .Y(n1245) );
NOR2X2TS U3667 ( .A(n920), .B(n1165), .Y(n1482) );
INVX2TS U3668 ( .A(n1482), .Y(n1244) );
NAND2BX1TS U3669 ( .AN(n5567), .B(n5570), .Y(n3392) );
NOR2X1TS U3670 ( .A(n1244), .B(n3392), .Y(n1252) );
NAND2X1TS U3671 ( .A(n1244), .B(n3392), .Y(n1253) );
OA21X2TS U3672 ( .A0(n1245), .A1(n1252), .B0(n1253), .Y(n1282) );
INVX2TS U3673 ( .A(n1248), .Y(n1250) );
INVX2TS U3674 ( .A(n1252), .Y(n1254) );
NAND2X1TS U3675 ( .A(n1254), .B(n1253), .Y(n1255) );
XNOR2X1TS U3676 ( .A(n1256), .B(n1255), .Y(n3328) );
ADDFHX4TS U3677 ( .A(n1261), .B(n1260), .CI(n1259), .CO(n1536), .S(n1485) );
CMPR32X2TS U3678 ( .A(DP_OP_497J311_123_1725_n613), .B(n1263), .C(n1262),
.CO(n1319), .S(n1261) );
NOR2X2TS U3679 ( .A(DP_OP_497J311_123_1725_n367), .B(
DP_OP_497J311_123_1725_n635), .Y(n1322) );
INVX2TS U3680 ( .A(n1314), .Y(n1267) );
NAND2X1TS U3681 ( .A(n1267), .B(n1312), .Y(n1268) );
ADDHX1TS U3682 ( .A(DP_OP_497J311_123_1725_n792), .B(
DP_OP_497J311_123_1725_n705), .CO(n1273), .S(n1238) );
XOR2X4TS U3683 ( .A(n1159), .B(n1274), .Y(n1501) );
OAI22X1TS U3684 ( .A0(n985), .A1(n1467), .B0(n1050), .B1(n1503), .Y(n1294)
);
INVX2TS U3685 ( .A(n1530), .Y(n1297) );
INVX2TS U3686 ( .A(n1277), .Y(n1290) );
NOR2X2TS U3687 ( .A(DP_OP_497J311_123_1725_n720), .B(n920), .Y(n1300) );
OR2X2TS U3688 ( .A(n1280), .B(n1279), .Y(n1309) );
XNOR2X4TS U3689 ( .A(n1286), .B(n1285), .Y(n1287) );
ADDHX1TS U3690 ( .A(DP_OP_497J311_123_1725_n793), .B(
DP_OP_497J311_123_1725_n699), .CO(n1291), .S(n1278) );
INVX4TS U3691 ( .A(n1291), .Y(n1609) );
OAI22X1TS U3692 ( .A0(DP_OP_497J311_123_1725_n335), .A1(n1540), .B0(n5592),
.B1(n1609), .Y(n1341) );
INVX2TS U3693 ( .A(n1622), .Y(n1353) );
INVX2TS U3694 ( .A(n1576), .Y(n1339) );
NOR2X1TS U3695 ( .A(n5545), .B(n1596), .Y(n1351) );
OAI22X1TS U3696 ( .A0(n985), .A1(n1497), .B0(n1050), .B1(n1534), .Y(n1332)
);
CMPR32X2TS U3697 ( .A(n5569), .B(n1576), .C(n1297), .CO(n1360), .S(n1302) );
INVX2TS U3698 ( .A(n1298), .Y(n1359) );
CMPR32X2TS U3699 ( .A(n1303), .B(n1302), .C(n1301), .CO(n1330), .S(n1279) );
OR2X4TS U3700 ( .A(n1305), .B(n1304), .Y(n1367) );
NAND2X2TS U3701 ( .A(n1305), .B(n1304), .Y(n1364) );
INVX2TS U3702 ( .A(n1306), .Y(n1307) );
AO21X4TS U3703 ( .A0(n1309), .A1(n1308), .B0(n1307), .Y(n1366) );
NOR2X2TS U3704 ( .A(n1311), .B(n1314), .Y(n1424) );
OAI21X2TS U3705 ( .A0(n1314), .A1(n1313), .B0(n1312), .Y(n1430) );
INVX2TS U3706 ( .A(n1430), .Y(n1315) );
AND2X2TS U3707 ( .A(n5568), .B(n954), .Y(n1373) );
NOR2X2TS U3708 ( .A(n1608), .B(n1598), .Y(n1423) );
INVX2TS U3709 ( .A(n1423), .Y(n1370) );
NAND2X1TS U3710 ( .A(n1598), .B(n1608), .Y(n1427) );
INVX2TS U3711 ( .A(n3345), .Y(n1329) );
INVX2TS U3712 ( .A(n1333), .Y(n1397) );
INVX4TS U3713 ( .A(n1667), .Y(n1396) );
INVX6TS U3714 ( .A(n1337), .Y(n1659) );
NOR2X4TS U3715 ( .A(n5592), .B(n1659), .Y(n1390) );
OAI22X1TS U3716 ( .A0(n993), .A1(n1497), .B0(n985), .B1(n1534), .Y(n1412) );
ADDFHX2TS U3717 ( .A(n1342), .B(n1341), .CI(n1340), .CO(n1411), .S(n1344) );
NOR2X4TS U3718 ( .A(DP_OP_497J311_123_1725_n378), .B(
DP_OP_497J311_123_1725_n385), .Y(n1348) );
AOI21X4TS U3719 ( .A0(DP_OP_497J311_123_1725_n388), .A1(n1348), .B0(n1347),
.Y(n1466) );
OAI22X1TS U3720 ( .A0(n1032), .A1(n1467), .B0(n993), .B1(n1503), .Y(n1416)
);
ADDFHX2TS U3721 ( .A(n1353), .B(n1352), .CI(n1351), .CO(n1400), .S(n1340) );
ADDHX1TS U3722 ( .A(n1356), .B(n1355), .CO(n1387), .S(n1622) );
NOR2X2TS U3723 ( .A(DP_OP_497J311_123_1725_n714), .B(
DP_OP_497J311_123_1725_n721), .Y(n1408) );
NOR2X2TS U3724 ( .A(n932), .B(n1165), .Y(n1406) );
NOR2X2TS U3725 ( .A(DP_OP_497J311_123_1725_n715), .B(
DP_OP_497J311_123_1725_n720), .Y(n1405) );
NOR2X1TS U3726 ( .A(n1407), .B(DP_OP_497J311_123_1725_n719), .Y(n1404) );
ADDHX1TS U3727 ( .A(DP_OP_497J311_123_1725_n794), .B(
DP_OP_497J311_123_1725_n693), .CO(n1357), .S(n1293) );
OAI22X1TS U3728 ( .A0(n1050), .A1(n1596), .B0(n5545), .B1(n1652), .Y(n1393)
);
OAI22X1TS U3729 ( .A0(n985), .A1(n1540), .B0(n1050), .B1(n1609), .Y(n1392)
);
INVX2TS U3730 ( .A(n1421), .Y(n1363) );
NAND2X2TS U3731 ( .A(n1363), .B(n1419), .Y(n1368) );
INVX2TS U3732 ( .A(n1364), .Y(n1365) );
XOR2X4TS U3733 ( .A(n1368), .B(n1420), .Y(n1379) );
NAND2X1TS U3734 ( .A(n1424), .B(n1370), .Y(n1371) );
INVX2TS U3735 ( .A(n1427), .Y(n1369) );
BUFX3TS U3736 ( .A(DP_OP_497J311_123_1725_n324), .Y(n1610) );
NAND2BX1TS U3737 ( .AN(n1610), .B(n5578), .Y(n1689) );
INVX2TS U3738 ( .A(n1689), .Y(n1375) );
NOR2X2TS U3739 ( .A(n1649), .B(n1375), .Y(n1426) );
INVX2TS U3740 ( .A(n1426), .Y(n1376) );
NAND2X1TS U3741 ( .A(n1649), .B(n1375), .Y(n1425) );
NAND2X1TS U3742 ( .A(n1376), .B(n1425), .Y(n1377) );
OR2X4TS U3743 ( .A(n1379), .B(n1378), .Y(n3348) );
INVX2TS U3744 ( .A(n3347), .Y(n1380) );
CMPR32X2TS U3745 ( .A(n1387), .B(n1386), .C(n1385), .CO(n1705), .S(n1668) );
INVX4TS U3746 ( .A(n1705), .Y(n1452) );
INVX2TS U3747 ( .A(n1388), .Y(n1455) );
ADDFHX2TS U3748 ( .A(n1393), .B(n1392), .CI(n1391), .CO(n1461), .S(n1414) );
ADDHX1TS U3749 ( .A(DP_OP_497J311_123_1725_n795), .B(n5454), .CO(n1394), .S(
n1337) );
OAI22X1TS U3750 ( .A0(n1050), .A1(n1659), .B0(n5592), .B1(n1690), .Y(n1459)
);
ADDFHX2TS U3751 ( .A(n1397), .B(n1396), .CI(n1395), .CO(n1457), .S(n1413) );
ADDFHX4TS U3752 ( .A(n1400), .B(n1399), .CI(n1398), .CO(n1449), .S(n1415) );
XNOR2X4TS U3753 ( .A(n1402), .B(DP_OP_497J311_123_1725_n357), .Y(n1403) );
NOR2X4TS U3754 ( .A(DP_OP_497J311_123_1725_n715), .B(
DP_OP_497J311_123_1725_n719), .Y(n1447) );
NOR2X4TS U3755 ( .A(n1407), .B(n1554), .Y(n1446) );
ADDHX1TS U3756 ( .A(n1409), .B(n1408), .CO(n1443), .S(n1386) );
INVX2TS U3757 ( .A(n1706), .Y(n1470) );
INVX2TS U3758 ( .A(n1410), .Y(n1469) );
OAI22X1TS U3759 ( .A0(n993), .A1(n1540), .B0(n985), .B1(n1609), .Y(n1468) );
XNOR2X4TS U3760 ( .A(n1422), .B(n1479), .Y(n1435) );
NOR2X1TS U3761 ( .A(n1423), .B(n1426), .Y(n1429) );
NAND2X1TS U3762 ( .A(n1424), .B(n1429), .Y(n1432) );
AOI21X1TS U3763 ( .A0(n1430), .A1(n1429), .B0(n1428), .Y(n1431) );
OAI21X2TS U3764 ( .A0(n1433), .A1(n1432), .B0(n1431), .Y(n1434) );
NOR2X4TS U3765 ( .A(n1435), .B(n1434), .Y(n3351) );
ADDFHX2TS U3766 ( .A(n1438), .B(n1437), .CI(n1436), .CO(n1521), .S(n1417) );
OAI22X1TS U3767 ( .A0(n1535), .A1(n1659), .B0(DP_OP_497J311_123_1725_n335),
.B1(n1690), .Y(n1500) );
OAI22X1TS U3768 ( .A0(n993), .A1(n1596), .B0(n985), .B1(n1652), .Y(n1498) );
NOR2X2TS U3769 ( .A(n932), .B(DP_OP_497J311_123_1725_n720), .Y(n1506) );
ADDFHX2TS U3770 ( .A(n1444), .B(DP_OP_497J311_123_1725_n675), .CI(n1443),
.CO(n1511), .S(n1439) );
OAI22X1TS U3771 ( .A0(n1032), .A1(n1540), .B0(n993), .B1(n1609), .Y(n1513)
);
ADDFHX2TS U3772 ( .A(n1453), .B(n1452), .CI(n1451), .CO(n1490), .S(n1462) );
INVX2TS U3773 ( .A(n1456), .Y(n1486) );
ADDFHX2TS U3774 ( .A(n1462), .B(n1461), .CI(n1460), .CO(n1495), .S(n1472) );
AND2X2TS U3775 ( .A(n1463), .B(DP_OP_497J311_123_1725_n367), .Y(n1464) );
OAI21X4TS U3776 ( .A0(n1466), .A1(n1465), .B0(n1464), .Y(n1719) );
OAI22X1TS U3777 ( .A0(n1660), .A1(n1503), .B0(n987), .B1(n1467), .Y(n1493)
);
OAI22X1TS U3778 ( .A0(n1660), .A1(n1497), .B0(n1661), .B1(n1534), .Y(n1492)
);
ADDFHX2TS U3779 ( .A(n1473), .B(n1472), .CI(n1471), .CO(n1474), .S(n1418) );
INVX2TS U3780 ( .A(n1526), .Y(n1476) );
AOI21X4TS U3781 ( .A0(n1480), .A1(n1479), .B0(n1478), .Y(n1527) );
XOR2X4TS U3782 ( .A(n1481), .B(n935), .Y(n1483) );
INVX4TS U3783 ( .A(n1485), .Y(n1564) );
ADDFHX2TS U3784 ( .A(n5589), .B(n1487), .CI(n1486), .CO(n1562), .S(n1489) );
ADDFHX4TS U3785 ( .A(n1490), .B(n1489), .CI(n1488), .CO(n1566), .S(n1496) );
OAI22X1TS U3786 ( .A0(n1660), .A1(n1534), .B0(n986), .B1(n1497), .Y(n1539)
);
AOI2BB2X1TS U3787 ( .B0(n1501), .B1(n1610), .A0N(DP_OP_497J311_123_1725_n335), .A1N(n1610), .Y(n1502) );
INVX2TS U3788 ( .A(n1502), .Y(n1543) );
CMPR32X2TS U3789 ( .A(n1507), .B(n1506), .C(n1505), .CO(n1561), .S(n1512) );
ADDHX1TS U3790 ( .A(DP_OP_497J311_123_1725_n705), .B(
DP_OP_497J311_123_1725_n685), .CO(n1556), .S(n1509) );
ADDFHX2TS U3791 ( .A(n1515), .B(n1514), .CI(n1513), .CO(n1547), .S(n1517) );
ADDFHX2TS U3792 ( .A(n1518), .B(n1517), .CI(n1516), .CO(n1544), .S(n1520) );
INVX2TS U3793 ( .A(n1579), .Y(n1524) );
OAI21X4TS U3794 ( .A0(n1527), .A1(n1526), .B0(n1525), .Y(n1581) );
ADDFHX2TS U3795 ( .A(n1564), .B(n1563), .CI(n1562), .CO(n1612), .S(n1567) );
ADDFHX2TS U3796 ( .A(n1567), .B(n1566), .CI(n1565), .CO(n1602), .S(n1570) );
XNOR2X4TS U3797 ( .A(n1575), .B(n1574), .Y(n1628) );
NAND2X1TS U3798 ( .A(n1577), .B(n1576), .Y(n1625) );
NAND2X1TS U3799 ( .A(n1182), .B(n1625), .Y(n1578) );
CLKXOR2X2TS U3800 ( .A(n1578), .B(n1624), .Y(n1627) );
CMPR32X2TS U3801 ( .A(n1593), .B(n1592), .C(n1591), .CO(n1638), .S(n1615) );
OAI22X1TS U3802 ( .A0(n1660), .A1(n1652), .B0(n987), .B1(n1596), .Y(n1644)
);
INVX2TS U3803 ( .A(n1785), .Y(n1658) );
ADDFHX2TS U3804 ( .A(n1604), .B(n1603), .CI(n1602), .CO(n1635), .S(n1585) );
OAI22X1TS U3805 ( .A0(n1660), .A1(n1659), .B0(n1032), .B1(n1690), .Y(n1648)
);
ADDFHX4TS U3806 ( .A(n1607), .B(n1606), .CI(n1605), .CO(n1647), .S(n1613) );
OAI22X1TS U3807 ( .A0(n1661), .A1(n5563), .B0(n993), .B1(n1610), .Y(n1653)
);
ADDFHX4TS U3808 ( .A(n1617), .B(n1616), .CI(n1615), .CO(n1640), .S(n1587) );
NAND2X4TS U3809 ( .A(n1620), .B(n1676), .Y(n1621) );
NAND2X1TS U3810 ( .A(n1183), .B(n1670), .Y(n1626) );
NAND2X1TS U3811 ( .A(n1625), .B(n1624), .Y(n1672) );
XNOR2X2TS U3812 ( .A(n1626), .B(n1672), .Y(n1629) );
OAI21X4TS U3813 ( .A0(n3738), .A1(n3767), .B0(n3739), .Y(n1631) );
AOI21X4TS U3814 ( .A0(n3765), .A1(n1632), .B0(n1631), .Y(n1633) );
ADDFHX4TS U3815 ( .A(n1636), .B(n1635), .CI(n1634), .CO(n1663), .S(n1619) );
ADDFHX2TS U3816 ( .A(n1648), .B(n1647), .CI(n1646), .CO(n1696), .S(n1642) );
INVX2TS U3817 ( .A(n1649), .Y(n1688) );
CMPR32X2TS U3818 ( .A(n5454), .B(n2698), .C(n1650), .CO(n1651), .S(n1785) );
NOR2X1TS U3819 ( .A(n987), .B(n1652), .Y(n1686) );
OAI22X1TS U3820 ( .A0(n1660), .A1(n1690), .B0(n986), .B1(n1659), .Y(n1693)
);
NOR2X1TS U3821 ( .A(n1668), .B(n1667), .Y(n1703) );
INVX2TS U3822 ( .A(n1703), .Y(n1669) );
NAND2X1TS U3823 ( .A(n1668), .B(n1667), .Y(n1702) );
NAND2X1TS U3824 ( .A(n1669), .B(n1702), .Y(n1673) );
INVX2TS U3825 ( .A(n1670), .Y(n1671) );
CLKXOR2X2TS U3826 ( .A(n1673), .B(n1704), .Y(n1709) );
OAI21X4TS U3827 ( .A0(n1713), .A1(n1679), .B0(n1678), .Y(n1701) );
ADDFHX4TS U3828 ( .A(n1682), .B(n1681), .CI(n1680), .CO(n1699), .S(n1662) );
CMPR32X2TS U3829 ( .A(n1688), .B(n1687), .C(n1686), .CO(n1725), .S(n1685) );
NOR2X1TS U3830 ( .A(n986), .B(n1690), .Y(n1721) );
AOI2BB2X1TS U3831 ( .B0(n1403), .B1(n5568), .A0N(n986), .A1N(n5568), .Y(
n1691) );
INVX2TS U3832 ( .A(n1691), .Y(n1720) );
INVX2TS U3833 ( .A(n1762), .Y(n1730) );
NOR2X2TS U3834 ( .A(n1706), .B(n1705), .Y(n1757) );
INVX2TS U3835 ( .A(n1757), .Y(n1707) );
NAND2X1TS U3836 ( .A(n1706), .B(n1705), .Y(n1759) );
NAND2X1TS U3837 ( .A(n1707), .B(n1759), .Y(n1708) );
CLKXOR2X2TS U3838 ( .A(n1730), .B(n1708), .Y(n1711) );
INVX2TS U3839 ( .A(n1746), .Y(n1714) );
CMPR32X2TS U3840 ( .A(n1725), .B(n1724), .C(n1723), .CO(n1752), .S(n1717) );
INVX2TS U3841 ( .A(n1745), .Y(n1728) );
NAND2X2TS U3842 ( .A(n1727), .B(n1726), .Y(n1744) );
OAI21X1TS U3843 ( .A0(n1730), .A1(n1757), .B0(n1759), .Y(n1735) );
NOR2X2TS U3844 ( .A(n1732), .B(n1731), .Y(n1760) );
INVX2TS U3845 ( .A(n1760), .Y(n1733) );
NAND2X1TS U3846 ( .A(n1733), .B(n1758), .Y(n1734) );
XNOR2X2TS U3847 ( .A(n1735), .B(n1734), .Y(n1736) );
NAND2X4TS U3848 ( .A(n1738), .B(n2641), .Y(n1739) );
XOR2X4TS U3849 ( .A(n1740), .B(n1739), .Y(n1741) );
CMPR32X2TS U3850 ( .A(n1754), .B(n1753), .C(n1752), .CO(n1755), .S(n1726) );
NOR2X1TS U3851 ( .A(n1760), .B(n1757), .Y(n1763) );
OAI21X1TS U3852 ( .A0(n1760), .A1(n1759), .B0(n1758), .Y(n1761) );
NOR2X2TS U3853 ( .A(n1765), .B(n1764), .Y(n1779) );
INVX2TS U3854 ( .A(n1779), .Y(n1766) );
NAND2X1TS U3855 ( .A(n1766), .B(n1781), .Y(n1767) );
CLKXOR2X2TS U3856 ( .A(n1801), .B(n1767), .Y(n1768) );
AOI21X4TS U3857 ( .A0(n1771), .A1(n2642), .B0(n1770), .Y(n1773) );
OAI21X1TS U3858 ( .A0(n1801), .A1(n1779), .B0(n1781), .Y(n1778) );
NOR2X2TS U3859 ( .A(n1775), .B(n1774), .Y(n1782) );
INVX2TS U3860 ( .A(n1782), .Y(n1776) );
NAND2X1TS U3861 ( .A(n1776), .B(n1780), .Y(n1777) );
XNOR2X2TS U3862 ( .A(n1778), .B(n1777), .Y(n3269) );
INVX2TS U3863 ( .A(n1789), .Y(n1784) );
OAI21X2TS U3864 ( .A0(n1782), .A1(n1781), .B0(n1780), .Y(n1798) );
INVX2TS U3865 ( .A(n1798), .Y(n1783) );
OAI21X1TS U3866 ( .A0(n1801), .A1(n1784), .B0(n1783), .Y(n1788) );
NAND2X1TS U3867 ( .A(n1797), .B(n1795), .Y(n1787) );
NAND2X1TS U3868 ( .A(n1789), .B(n1797), .Y(n1800) );
INVX2TS U3869 ( .A(n1795), .Y(n1790) );
AOI21X1TS U3870 ( .A0(n1798), .A1(n1797), .B0(n1790), .Y(n1791) );
XNOR2X1TS U3871 ( .A(n1792), .B(n1651), .Y(n3874) );
NAND2X2TS U3872 ( .A(n3873), .B(n1793), .Y(n1802) );
NAND2X1TS U3873 ( .A(n1795), .B(n1794), .Y(n1796) );
AOI21X1TS U3874 ( .A0(n1798), .A1(n1797), .B0(n1796), .Y(n1799) );
CLKINVX6TS U3875 ( .A(n2712), .Y(n1808) );
NOR2X4TS U3876 ( .A(n2731), .B(n1808), .Y(n2720) );
OR2X4TS U3877 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[6]), .Y(n2722) );
INVX4TS U3878 ( .A(n2689), .Y(n1803) );
OAI21X4TS U3879 ( .A0(n2649), .A1(DP_OP_496J311_122_3540_n1202), .B0(
DP_OP_496J311_122_3540_n1203), .Y(n2688) );
NAND2X4TS U3880 ( .A(n1804), .B(n2688), .Y(n1806) );
NAND2X8TS U3881 ( .A(DP_OP_496J311_122_3540_n1495), .B(n915), .Y(n2690) );
AND2X4TS U3882 ( .A(FPMULT_Op_MX[5]), .B(DP_OP_496J311_122_3540_n1498), .Y(
n1807) );
INVX4TS U3883 ( .A(n1807), .Y(n2711) );
NAND2X2TS U3884 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[6]), .Y(n2721) );
INVX2TS U3885 ( .A(n2721), .Y(n1809) );
AOI21X4TS U3886 ( .A0(n2719), .A1(n2722), .B0(n1809), .Y(n1810) );
NAND2X1TS U3887 ( .A(n1825), .B(n1823), .Y(n1812) );
XOR2X4TS U3888 ( .A(n1813), .B(n1812), .Y(n1911) );
NAND2X2TS U3889 ( .A(n1191), .B(n950), .Y(n1938) );
AO21X2TS U3890 ( .A0(n1174), .A1(n1172), .B0(n5898), .Y(n1817) );
NOR2BX2TS U3891 ( .AN(DP_OP_496J311_122_3540_n1476), .B(n1172), .Y(n1815) );
INVX2TS U3892 ( .A(n1815), .Y(n1816) );
NAND2X2TS U3893 ( .A(n1817), .B(n1816), .Y(n1859) );
NOR2BX2TS U3894 ( .AN(n1191), .B(n2698), .Y(n1818) );
XNOR2X1TS U3895 ( .A(n1818), .B(n950), .Y(n1819) );
XOR2X2TS U3896 ( .A(n1820), .B(n1819), .Y(n1821) );
BUFX12TS U3897 ( .A(n1821), .Y(n2628) );
NAND2X6TS U3898 ( .A(n2628), .B(n1169), .Y(n2629) );
INVX2TS U3899 ( .A(n1837), .Y(n1870) );
INVX2TS U3900 ( .A(n1823), .Y(n1824) );
NAND2BX2TS U3901 ( .AN(n1828), .B(DP_OP_496J311_122_3540_n1515), .Y(n1838)
);
NAND2X1TS U3902 ( .A(n1872), .B(n1838), .Y(n1829) );
XOR2X4TS U3903 ( .A(n1830), .B(n1829), .Y(n1919) );
XNOR2X1TS U3904 ( .A(n1919), .B(n1938), .Y(n1907) );
OAI22X1TS U3905 ( .A0(n1881), .A1(n2629), .B0(n1907), .B1(n2628), .Y(n1917)
);
NAND2X1TS U3906 ( .A(n1832), .B(n1831), .Y(n1833) );
XNOR2X4TS U3907 ( .A(n2813), .B(n1833), .Y(n1834) );
OAI22X1TS U3908 ( .A0(n1835), .A1(n2628), .B0(n2629), .B1(n2631), .Y(n1883)
);
NAND2X4TS U3909 ( .A(n1872), .B(n1876), .Y(n1841) );
NOR2X2TS U3910 ( .A(n1841), .B(n1837), .Y(n1844) );
INVX2TS U3911 ( .A(n1838), .Y(n1871) );
NAND2BX2TS U3912 ( .AN(n1166), .B(DP_OP_496J311_122_3540_n1516), .Y(n1875)
);
AOI21X4TS U3913 ( .A0(n2813), .A1(n1844), .B0(n1843), .Y(n1857) );
OAI21X4TS U3914 ( .A0(DP_OP_496J311_122_3540_n1107), .A1(
DP_OP_496J311_122_3540_n1114), .B0(DP_OP_496J311_122_3540_n1108), .Y(
n1845) );
AOI21X4TS U3915 ( .A0(n1071), .A1(DP_OP_496J311_122_3540_n1105), .B0(n1845),
.Y(n2699) );
OAI21X4TS U3916 ( .A0(DP_OP_496J311_122_3540_n1096), .A1(
DP_OP_496J311_122_3540_n1103), .B0(DP_OP_496J311_122_3540_n1097), .Y(
n2658) );
AOI21X4TS U3917 ( .A0(n2663), .A1(n1847), .B0(n1846), .Y(n1852) );
OAI2BB1X4TS U3918 ( .A0N(n952), .A1N(n1176), .B0(n2665), .Y(n1849) );
NAND2X1TS U3919 ( .A(DP_OP_496J311_122_3540_n778), .B(FPMULT_Op_MY[7]), .Y(
n1848) );
NAND2X4TS U3920 ( .A(n1849), .B(n1848), .Y(n1861) );
XNOR2X1TS U3921 ( .A(FPMULT_Op_MY[8]), .B(DP_OP_496J311_122_3540_n1464), .Y(
n1850) );
XOR2X4TS U3922 ( .A(n1861), .B(n1860), .Y(n1851) );
INVX8TS U3923 ( .A(n1851), .Y(n1934) );
XNOR2X2TS U3924 ( .A(n2866), .B(n1854), .Y(n1853) );
INVX8TS U3925 ( .A(n1853), .Y(n3168) );
CLKXOR2X2TS U3926 ( .A(n1855), .B(n1860), .Y(n1856) );
NAND2X6TS U3927 ( .A(n3168), .B(n1856), .Y(n1895) );
NAND2X4TS U3928 ( .A(n1857), .B(DP_OP_496J311_122_3540_n846), .Y(n2630) );
NOR2BX1TS U3929 ( .AN(n1834), .B(n2631), .Y(n1910) );
INVX2TS U3930 ( .A(n1934), .Y(n1949) );
OAI22X2TS U3931 ( .A0(n1858), .A1(n1895), .B0(n1949), .B1(n3168), .Y(n1909)
);
XNOR2X4TS U3932 ( .A(n1814), .B(n1859), .Y(n1913) );
XNOR2X2TS U3933 ( .A(n1162), .B(n1913), .Y(n1914) );
NOR2BX1TS U3934 ( .AN(n5898), .B(DP_OP_496J311_122_3540_n1464), .Y(n1862) );
XNOR2X1TS U3935 ( .A(n1866), .B(n1862), .Y(n1863) );
XOR2X4TS U3936 ( .A(n1864), .B(n1863), .Y(n1865) );
XNOR2X1TS U3937 ( .A(DP_OP_496J311_122_3540_n1464), .B(n1172), .Y(n1867) );
NOR2X1TS U3938 ( .A(n1867), .B(n1866), .Y(n1868) );
XOR2X1TS U3939 ( .A(n1868), .B(n1814), .Y(n1869) );
NAND2X8TS U3940 ( .A(n1931), .B(n1869), .Y(n1932) );
OAI2BB1X4TS U3941 ( .A0N(n2813), .A1N(n1160), .B0(n1874), .Y(n1878) );
XNOR2X4TS U3942 ( .A(n1878), .B(n1877), .Y(n1936) );
OAI22X2TS U3943 ( .A0(n1914), .A1(n1931), .B0(n1932), .B1(n1879), .Y(n1908)
);
OAI22X1TS U3944 ( .A0(n1888), .A1(n1932), .B0(n1931), .B1(n1879), .Y(n1886)
);
XNOR2X1TS U3945 ( .A(n1834), .B(n1938), .Y(n1880) );
OAI22X1TS U3946 ( .A0(n1881), .A1(n2628), .B0(n1880), .B1(n2629), .Y(n1885)
);
NOR2BX1TS U3947 ( .AN(n1834), .B(n2628), .Y(n1904) );
OAI22X2TS U3948 ( .A0(n1887), .A1(n3168), .B0(n1894), .B1(n1895), .Y(n1903)
);
XNOR2X2TS U3949 ( .A(n1911), .B(n1913), .Y(n1898) );
OAI22X1TS U3950 ( .A0(n1898), .A1(n1932), .B0(n1888), .B1(n1931), .Y(n1902)
);
NOR2X2TS U3951 ( .A(n3072), .B(n2953), .Y(n3243) );
XNOR2X2TS U3952 ( .A(n1911), .B(n1934), .Y(n1890) );
XNOR2X2TS U3953 ( .A(n1919), .B(n1934), .Y(n1896) );
OAI22X2TS U3954 ( .A0(n1890), .A1(n1895), .B0(n1896), .B1(n3168), .Y(n3136)
);
NOR2BX2TS U3955 ( .AN(n1834), .B(n1931), .Y(n1889) );
NOR2X1TS U3956 ( .A(n3136), .B(n1889), .Y(n3743) );
NAND2X1TS U3957 ( .A(n3136), .B(n1889), .Y(n3744) );
OAI21X1TS U3958 ( .A0(n3743), .A1(n3752), .B0(n3744), .Y(n3799) );
INVX2TS U3959 ( .A(n1913), .Y(n1930) );
OAI22X1TS U3960 ( .A0(n1932), .A1(n1930), .B0(n1931), .B1(n1893), .Y(n1901)
);
OAI22X1TS U3961 ( .A0(n1896), .A1(n1895), .B0(n1894), .B1(n3168), .Y(n1900)
);
XNOR2X1TS U3962 ( .A(n1834), .B(n1913), .Y(n1897) );
OAI22X2TS U3963 ( .A0(n1898), .A1(n1931), .B0(n1932), .B1(n1897), .Y(n3103)
);
NAND2X1TS U3964 ( .A(n3116), .B(n3103), .Y(n3797) );
INVX2TS U3965 ( .A(n3797), .Y(n1899) );
AOI21X2TS U3966 ( .A0(n3799), .A1(n3798), .B0(n1899), .Y(n3786) );
NAND2X1TS U3967 ( .A(n3082), .B(n3106), .Y(n3783) );
OAI21X4TS U3968 ( .A0(n3786), .A1(n3782), .B0(n3783), .Y(n3235) );
OAI21X1TS U3969 ( .A0(n3245), .A1(n3242), .B0(n3246), .Y(n1905) );
XNOR2X1TS U3970 ( .A(n1936), .B(n1938), .Y(n1918) );
OAI22X1TS U3971 ( .A0(n1907), .A1(n2629), .B0(n1918), .B1(n2628), .Y(n1926)
);
INVX2TS U3972 ( .A(n1911), .Y(n1912) );
NOR2X2TS U3973 ( .A(n2873), .B(n2846), .Y(n3865) );
XNOR2X2TS U3974 ( .A(n1162), .B(n1938), .Y(n1939) );
OAI22X1TS U3975 ( .A0(n1939), .A1(n2628), .B0(n1918), .B1(n2629), .Y(n1929)
);
INVX2TS U3976 ( .A(n1919), .Y(n1920) );
NOR2X2TS U3977 ( .A(n1920), .B(n2631), .Y(n1935) );
OAI22X4TS U3978 ( .A0(n1932), .A1(n1921), .B0(n1931), .B1(n1930), .Y(n1933)
);
CMPR32X2TS U3979 ( .A(n1923), .B(n1934), .C(n1922), .CO(n1927), .S(n1924) );
NOR2X2TS U3980 ( .A(n2840), .B(n2839), .Y(n3867) );
NOR2X2TS U3981 ( .A(n3865), .B(n3867), .Y(n2616) );
CMPR32X2TS U3982 ( .A(n1935), .B(n1934), .C(n1933), .CO(n1944), .S(n1928) );
INVX2TS U3983 ( .A(n1936), .Y(n1937) );
NOR2X2TS U3984 ( .A(n1937), .B(n2631), .Y(n1950) );
XNOR2X2TS U3985 ( .A(n2630), .B(n1938), .Y(n1947) );
INVX2TS U3986 ( .A(n2615), .Y(n1956) );
NAND2X1TS U3987 ( .A(n2616), .B(n1956), .Y(n1942) );
NAND2X1TS U3988 ( .A(n2840), .B(n2839), .Y(n3868) );
OAI21X2TS U3989 ( .A0(n3867), .A1(n3864), .B0(n3868), .Y(n2622) );
INVX2TS U3990 ( .A(n2618), .Y(n1940) );
AOI21X1TS U3991 ( .A0(n2622), .A1(n1956), .B0(n1940), .Y(n1941) );
INVX2TS U3992 ( .A(n1162), .Y(n1946) );
INVX2TS U3993 ( .A(n3033), .Y(n2626) );
NOR2X2TS U3994 ( .A(n2934), .B(n2987), .Y(n2619) );
INVX2TS U3995 ( .A(n2619), .Y(n1951) );
NAND2X1TS U3996 ( .A(n2934), .B(n2987), .Y(n2617) );
NAND2X1TS U3997 ( .A(n1951), .B(n2617), .Y(n1952) );
INVX2TS U3998 ( .A(n2616), .Y(n1955) );
INVX2TS U3999 ( .A(n2622), .Y(n1954) );
OAI21X1TS U4000 ( .A0(n3866), .A1(n1955), .B0(n1954), .Y(n1958) );
NAND2X4TS U4001 ( .A(n1959), .B(DP_OP_498J311_124_1725_n392), .Y(n1960) );
XOR2X4TS U4002 ( .A(n1960), .B(DP_OP_498J311_124_1725_n394), .Y(n1961) );
INVX4TS U4003 ( .A(n1963), .Y(n2364) );
OAI22X1TS U4004 ( .A0(n2224), .A1(n2335), .B0(n2187), .B1(n2364), .Y(n2100)
);
NOR2X4TS U4005 ( .A(n2226), .B(n922), .Y(n2097) );
INVX16TS U4006 ( .A(DP_OP_498J311_124_1725_n802), .Y(n2071) );
INVX6TS U4007 ( .A(n2475), .Y(n2036) );
INVX2TS U4008 ( .A(n2468), .Y(n2035) );
OAI21X4TS U4009 ( .A0(n1965), .A1(DP_OP_498J311_124_1725_n394), .B0(
DP_OP_498J311_124_1725_n392), .Y(n1968) );
INVX4TS U4010 ( .A(n1968), .Y(n1982) );
OR2X8TS U4011 ( .A(n5543), .B(n2071), .Y(n1980) );
OAI22X1TS U4012 ( .A0(n1173), .A1(n922), .B0(n1037), .B1(n921), .Y(n2098) );
OAI21X4TS U4013 ( .A0(DP_OP_498J311_124_1725_n380), .A1(n1980), .B0(n1983),
.Y(n1970) );
NOR2X4TS U4014 ( .A(n1981), .B(DP_OP_498J311_124_1725_n380), .Y(n1969) );
NOR2X8TS U4015 ( .A(n1970), .B(n1180), .Y(n1993) );
NAND2X2TS U4016 ( .A(DP_OP_498J311_124_1725_n798), .B(
DP_OP_498J311_124_1725_n804), .Y(n1991) );
INVX2TS U4017 ( .A(n1992), .Y(n1971) );
NAND2X1TS U4018 ( .A(DP_OP_498J311_124_1725_n799), .B(
DP_OP_498J311_124_1725_n805), .Y(n1990) );
NAND2X2TS U4019 ( .A(n1971), .B(n1990), .Y(n1972) );
XNOR2X4TS U4020 ( .A(n1973), .B(n1972), .Y(n1974) );
INVX2TS U4021 ( .A(n1989), .Y(n1976) );
XOR2X4TS U4022 ( .A(n1993), .B(n1977), .Y(n1978) );
ADDHX1TS U4023 ( .A(FPMULT_Op_MY[2]), .B(DP_OP_498J311_124_1725_n784), .CO(
n1979), .S(n1975) );
INVX4TS U4024 ( .A(n1979), .Y(n2209) );
NOR2X2TS U4025 ( .A(DP_OP_498J311_124_1725_n724), .B(
DP_OP_498J311_124_1725_n730), .Y(n2004) );
NOR2X1TS U4026 ( .A(DP_OP_498J311_124_1725_n723), .B(n1175), .Y(n2003) );
NOR2X8TS U4027 ( .A(n2026), .B(DP_OP_498J311_124_1725_n724), .Y(n2019) );
NOR2X2TS U4028 ( .A(DP_OP_498J311_124_1725_n723), .B(
DP_OP_498J311_124_1725_n730), .Y(n2018) );
NOR2X4TS U4029 ( .A(DP_OP_498J311_124_1725_n725), .B(
DP_OP_498J311_124_1725_n728), .Y(n2017) );
NOR2X4TS U4030 ( .A(DP_OP_498J311_124_1725_n726), .B(
DP_OP_498J311_124_1725_n728), .Y(n2002) );
NOR2X2TS U4031 ( .A(n2095), .B(n2071), .Y(n1999) );
NOR2X4TS U4032 ( .A(n2094), .B(n2071), .Y(n2016) );
NOR2X4TS U4033 ( .A(n2188), .B(DP_OP_498J311_124_1725_n641), .Y(n1997) );
INVX2TS U4034 ( .A(n2481), .Y(n2102) );
OAI21X4TS U4035 ( .A0(n1982), .A1(n1981), .B0(n1980), .Y(n1985) );
NAND2X2TS U4036 ( .A(n5544), .B(n1983), .Y(n1984) );
XNOR2X4TS U4037 ( .A(n1985), .B(n1984), .Y(n1986) );
BUFX8TS U4038 ( .A(n1173), .Y(n2174) );
ADDHX1TS U4039 ( .A(DP_OP_498J311_124_1725_n791), .B(
DP_OP_498J311_124_1725_n785), .CO(n1988), .S(n1987) );
OAI22X1TS U4040 ( .A0(n2201), .A1(n2109), .B0(n2174), .B1(n2146), .Y(n2101)
);
OAI22X1TS U4041 ( .A0(n1173), .A1(n2335), .B0(n2224), .B1(n2364), .Y(n2061)
);
INVX4TS U4042 ( .A(n1994), .Y(n2223) );
NOR2X1TS U4043 ( .A(n930), .B(n2223), .Y(n2059) );
OAI22X1TS U4044 ( .A0(n2202), .A1(n2210), .B0(n2175), .B1(n2209), .Y(n2032)
);
INVX4TS U4045 ( .A(n2479), .Y(n2251) );
ADDHX1TS U4046 ( .A(DP_OP_498J311_124_1725_n789), .B(
DP_OP_498J311_124_1725_n783), .CO(n2009), .S(n2008) );
OAI22X1TS U4047 ( .A0(n1039), .A1(n2186), .B0(n2202), .B1(n2185), .Y(n2030)
);
ADDFHX2TS U4048 ( .A(n2012), .B(n2011), .CI(n2010), .CO(n2088), .S(n2041) );
ADDHX1TS U4049 ( .A(n2014), .B(n2013), .CO(n2070), .S(n2010) );
NOR2X2TS U4050 ( .A(DP_OP_498J311_124_1725_n721), .B(n1175), .Y(n2028) );
ADDFHX2TS U4051 ( .A(DP_OP_498J311_124_1725_n717), .B(n2019), .CI(n2018),
.CO(n2023), .S(n2045) );
NOR2X2TS U4052 ( .A(DP_OP_498J311_124_1725_n721), .B(
DP_OP_498J311_124_1725_n730), .Y(n2049) );
NOR2X2TS U4053 ( .A(DP_OP_498J311_124_1725_n724), .B(
DP_OP_498J311_124_1725_n727), .Y(n2048) );
NOR2X1TS U4054 ( .A(DP_OP_498J311_124_1725_n723), .B(
DP_OP_498J311_124_1725_n728), .Y(n2047) );
NOR2X1TS U4055 ( .A(DP_OP_498J311_124_1725_n722), .B(n2026), .Y(n2052) );
INVX2TS U4056 ( .A(n2390), .Y(n2065) );
ADDFHX4TS U4057 ( .A(n2032), .B(n2031), .CI(n2030), .CO(n2063), .S(n2278) );
OAI22X1TS U4058 ( .A0(n2186), .A1(n2202), .B0(n2201), .B1(n2185), .Y(n2248)
);
OAI22X1TS U4059 ( .A0(n2224), .A1(n2109), .B0(n2187), .B1(n2146), .Y(n2205)
);
INVX2TS U4060 ( .A(n2351), .Y(n2184) );
NOR2X4TS U4061 ( .A(n2187), .B(n2109), .Y(n2183) );
ADDHX4TS U4062 ( .A(n2036), .B(n2035), .CO(n2096), .S(n2182) );
INVX2TS U4063 ( .A(n2355), .Y(n2203) );
ADDHX1TS U4064 ( .A(DP_OP_498J311_124_1725_n782), .B(
DP_OP_498J311_124_1725_n788), .CO(n1994), .S(n2040) );
OAI22X1TS U4065 ( .A0(n1040), .A1(n2225), .B0(n994), .B1(n2223), .Y(n2246)
);
OAI22X1TS U4066 ( .A0(n2201), .A1(n2210), .B0(n2174), .B1(n2209), .Y(n2265)
);
INVX2TS U4067 ( .A(n2349), .Y(n2264) );
CMPR32X2TS U4068 ( .A(n2049), .B(n2048), .C(n2047), .CO(n2118), .S(n2055) );
NOR2X2TS U4069 ( .A(DP_OP_498J311_124_1725_n723), .B(
DP_OP_498J311_124_1725_n727), .Y(n2124) );
NOR2X4TS U4070 ( .A(DP_OP_498J311_124_1725_n721), .B(
DP_OP_498J311_124_1725_n729), .Y(n2123) );
ADDFHX2TS U4071 ( .A(n2052), .B(n2051), .CI(n2050), .CO(n2116), .S(n2053) );
INVX2TS U4072 ( .A(n2391), .Y(n2106) );
INVX2TS U4073 ( .A(n2392), .Y(n2105) );
NOR2X2TS U4074 ( .A(n930), .B(n2185), .Y(n2107) );
ADDFHX2TS U4075 ( .A(n2058), .B(n2057), .CI(n2056), .CO(n2135), .S(n2301) );
OAI22X1TS U4076 ( .A0(n1040), .A1(n2209), .B0(n926), .B1(n2210), .Y(n2112)
);
OAI22X1TS U4077 ( .A0(n1040), .A1(n2109), .B0(n994), .B1(n2146), .Y(n2111)
);
NOR2X1TS U4078 ( .A(DP_OP_498J311_124_1725_n634), .B(n2071), .Y(n2079) );
NOR2X2TS U4079 ( .A(n2095), .B(DP_OP_498J311_124_1725_n640), .Y(n2078) );
NOR2X1TS U4080 ( .A(n2094), .B(DP_OP_498J311_124_1725_n641), .Y(n2077) );
NOR2X1TS U4081 ( .A(DP_OP_498J311_124_1725_n635), .B(
DP_OP_498J311_124_1725_n642), .Y(n2082) );
OAI22X1TS U4082 ( .A0(n1039), .A1(n2185), .B0(n930), .B1(n2186), .Y(n2092)
);
ADDFX2TS U4083 ( .A(n2079), .B(n2078), .CI(n2077), .CO(n2127), .S(n2084) );
ADDFHX2TS U4084 ( .A(n2082), .B(n2081), .CI(n2080), .CO(n2125), .S(n2083) );
ADDFHX4TS U4085 ( .A(n2085), .B(n2084), .CI(n2083), .CO(n2509), .S(n2486) );
INVX2TS U4086 ( .A(n2482), .Y(n2281) );
OAI22X1TS U4087 ( .A0(n1040), .A1(n2223), .B0(n930), .B1(n2225), .Y(n2279)
);
OAI22X1TS U4088 ( .A0(n2224), .A1(n922), .B0(n2226), .B1(n921), .Y(n2257) );
NOR2X2TS U4089 ( .A(n2095), .B(n2189), .Y(n2166) );
NOR2X2TS U4090 ( .A(n2095), .B(DP_OP_498J311_124_1725_n645), .Y(n2178) );
ADDHX4TS U4091 ( .A(n2097), .B(n2096), .CO(n2006), .S(n2177) );
NOR2X2TS U4092 ( .A(DP_OP_498J311_124_1725_n724), .B(
DP_OP_498J311_124_1725_n732), .Y(n2180) );
INVX2TS U4093 ( .A(n2354), .Y(n2176) );
ADDFHX2TS U4094 ( .A(n2100), .B(n2099), .CI(n2098), .CO(n2058), .S(n2286) );
ADDHX1TS U4095 ( .A(n2108), .B(n2107), .CO(n2154), .S(n2104) );
OAI22X1TS U4096 ( .A0(n1039), .A1(n2146), .B0(n926), .B1(n2109), .Y(n2153)
);
NOR2X2TS U4097 ( .A(n930), .B(n2209), .Y(n2152) );
ADDFHX2TS U4098 ( .A(n2118), .B(n2117), .CI(n2116), .CO(n2401), .S(n2391) );
NOR2X2TS U4099 ( .A(DP_OP_498J311_124_1725_n635), .B(
DP_OP_498J311_124_1725_n640), .Y(n2148) );
CMPR32X2TS U4100 ( .A(n2121), .B(n2120), .C(n2119), .CO(n2147), .S(n2126) );
INVX2TS U4101 ( .A(n2512), .Y(n2158) );
CMPR32X2TS U4102 ( .A(n2124), .B(n2123), .C(n2122), .CO(n2143), .S(n2117) );
ADDFHX4TS U4103 ( .A(n2127), .B(n2126), .CI(n2125), .CO(n2513), .S(n2508) );
ADDFHX2TS U4104 ( .A(n2136), .B(n2135), .CI(n2134), .CO(n2140), .S(n2306) );
CMPR32X2TS U4105 ( .A(n2139), .B(n2138), .C(n2137), .CO(n2325), .S(n2164) );
NOR2X2TS U4106 ( .A(DP_OP_498J311_124_1725_n634), .B(
DP_OP_498J311_124_1725_n640), .Y(n2547) );
INVX2TS U4107 ( .A(n2547), .Y(n2334) );
NOR2X2TS U4108 ( .A(DP_OP_498J311_124_1725_n721), .B(
DP_OP_498J311_124_1725_n727), .Y(n2408) );
INVX2TS U4109 ( .A(n2408), .Y(n2333) );
ADDFHX4TS U4110 ( .A(n2149), .B(n2148), .CI(n2147), .CO(n2548), .S(n2512) );
CMPR32X2TS U4111 ( .A(n2152), .B(n2151), .C(n2150), .CO(n2327), .S(n2161) );
OAI22X1TS U4112 ( .A0(n1040), .A1(n2335), .B0(n994), .B1(n2364), .Y(n2339)
);
NOR2X8TS U4113 ( .A(n2320), .B(n2319), .Y(n2435) );
OAI22X1TS U4114 ( .A0(n2174), .A1(n2186), .B0(n1037), .B1(n2185), .Y(n2240)
);
OAI22X1TS U4115 ( .A0(n2175), .A1(n2225), .B0(n1173), .B1(n2223), .Y(n2239)
);
ADDFHX4TS U4116 ( .A(n2167), .B(n2166), .CI(n2165), .CO(n2477), .S(n2474) );
INVX2TS U4117 ( .A(n2474), .Y(n2213) );
INVX2TS U4118 ( .A(n2458), .Y(n2197) );
INVX2TS U4119 ( .A(n2352), .Y(n2211) );
OAI22X1TS U4120 ( .A0(n2175), .A1(n2186), .B0(n2174), .B1(n2185), .Y(n2263)
);
CMPR22X2TS U4121 ( .A(n2179), .B(n2178), .CO(n2165), .S(n2473) );
INVX2TS U4122 ( .A(n2473), .Y(n2200) );
CMPR22X2TS U4123 ( .A(n2181), .B(n2180), .CO(n2171), .S(n2467) );
ADDFHX2TS U4124 ( .A(n2184), .B(n2183), .CI(n2182), .CO(n2204), .S(n2190) );
OAI22X1TS U4125 ( .A0(n2224), .A1(n2186), .B0(n2187), .B1(n2185), .Y(n2216)
);
NOR2X2TS U4126 ( .A(DP_OP_498J311_124_1725_n638), .B(
DP_OP_498J311_124_1725_n645), .Y(n3307) );
INVX2TS U4127 ( .A(n3307), .Y(n2222) );
NOR2X2TS U4128 ( .A(n2187), .B(n2186), .Y(n2221) );
NOR2X2TS U4129 ( .A(DP_OP_498J311_124_1725_n726), .B(n1175), .Y(n2457) );
INVX2TS U4130 ( .A(n2457), .Y(n2194) );
NOR2X2TS U4131 ( .A(n2189), .B(n2188), .Y(n3308) );
INVX2TS U4132 ( .A(n3308), .Y(n2193) );
OAI22X1TS U4133 ( .A0(n1173), .A1(n2225), .B0(n2224), .B1(n2223), .Y(n2214)
);
OAI22X1TS U4134 ( .A0(n994), .A1(n2225), .B0(n2201), .B1(n2223), .Y(n2269)
);
INVX2TS U4135 ( .A(n2478), .Y(n2254) );
OAI22X1TS U4136 ( .A0(n1173), .A1(n2210), .B0(n2209), .B1(n2224), .Y(n2253)
);
NOR2X4TS U4137 ( .A(n2245), .B(n2244), .Y(n2537) );
ADDFHX4TS U4138 ( .A(n2222), .B(n2221), .CI(n2220), .CO(n2215), .S(n2231) );
OAI22X1TS U4139 ( .A0(n2224), .A1(n2225), .B0(n2226), .B1(n2223), .Y(n2230)
);
NOR2X2TS U4140 ( .A(n2231), .B(n2230), .Y(n2489) );
INVX2TS U4141 ( .A(n2504), .Y(n2229) );
INVX2TS U4142 ( .A(n2576), .Y(n2228) );
INVX2TS U4143 ( .A(FPMULT_Sgf_operation_Result[0]), .Y(n2227) );
NAND2X1TS U4144 ( .A(n2228), .B(n2227), .Y(n2501) );
NAND2X2TS U4145 ( .A(n2231), .B(n2230), .Y(n2490) );
INVX2TS U4146 ( .A(n2527), .Y(n2234) );
AO21X4TS U4147 ( .A0(n1186), .A1(n2528), .B0(n2234), .Y(n2518) );
ADDFHX2TS U4148 ( .A(n2237), .B(n2236), .CI(n2235), .CO(n2258), .S(n2242) );
OR2X4TS U4149 ( .A(n2242), .B(n2241), .Y(n2517) );
NAND2X4TS U4150 ( .A(n2242), .B(n2241), .Y(n2516) );
AOI21X4TS U4151 ( .A0(n2518), .A1(n2517), .B0(n2243), .Y(n2540) );
OAI21X4TS U4152 ( .A0(n2537), .A1(n2540), .B0(n2539), .Y(n2558) );
ADDFHX4TS U4153 ( .A(n2251), .B(n2250), .CI(n2249), .CO(n2031), .S(n2284) );
ADDFHX2TS U4154 ( .A(n2254), .B(n2253), .CI(n2252), .CO(n2283), .S(n2267) );
NAND2X4TS U4155 ( .A(n2271), .B(n2270), .Y(n2555) );
AOI21X4TS U4156 ( .A0(n2558), .A1(n2556), .B0(n2272), .Y(n2571) );
ADDFHX2TS U4157 ( .A(n2287), .B(n2286), .CI(n2285), .CO(n2296), .S(n2293) );
ADDFHX4TS U4158 ( .A(n2290), .B(n2289), .CI(n2288), .CO(n2291), .S(n2271) );
NAND2X4TS U4159 ( .A(n2292), .B(n2291), .Y(n2573) );
OAI21X4TS U4160 ( .A0(n2571), .A1(n2572), .B0(n2573), .Y(n2462) );
ADDFHX4TS U4161 ( .A(n2298), .B(n2297), .CI(n2296), .CO(n2113), .S(n2309) );
NOR2X8TS U4162 ( .A(n2312), .B(n2311), .Y(n2460) );
ADDFHX4TS U4163 ( .A(n2307), .B(n2306), .CI(n2305), .CO(n2317), .S(n2313) );
NOR2X8TS U4164 ( .A(n2313), .B(n2314), .Y(n2464) );
NOR2X4TS U4165 ( .A(n2460), .B(n2464), .Y(n2316) );
NAND2X4TS U4166 ( .A(n2314), .B(n2313), .Y(n2463) );
AOI21X4TS U4167 ( .A0(n2462), .A1(n2316), .B0(n2315), .Y(n2434) );
OAI21X4TS U4168 ( .A0(n2435), .A1(n2433), .B0(n2436), .Y(n2415) );
OAI21X4TS U4169 ( .A0(n2322), .A1(n2449), .B0(n2321), .Y(n2346) );
OAI22X1TS U4170 ( .A0(n1040), .A1(n2364), .B0(n926), .B1(n2335), .Y(n2365)
);
XOR2X4TS U4171 ( .A(n2346), .B(n2345), .Y(n2347) );
NOR2X2TS U4172 ( .A(n2349), .B(n2348), .Y(n2382) );
INVX2TS U4173 ( .A(n2382), .Y(n2350) );
NAND2X1TS U4174 ( .A(n2350), .B(n2384), .Y(n2356) );
NAND2X1TS U4175 ( .A(n2467), .B(n2468), .Y(n2469) );
NAND2X1TS U4176 ( .A(n2458), .B(n2457), .Y(n2470) );
NAND2X1TS U4177 ( .A(n2469), .B(n2470), .Y(n2451) );
NAND2X1TS U4178 ( .A(n2352), .B(n2351), .Y(n2450) );
INVX2TS U4179 ( .A(n2450), .Y(n2353) );
AOI21X1TS U4180 ( .A0(n1188), .A1(n2451), .B0(n2353), .Y(n2443) );
NOR2X1TS U4181 ( .A(n2354), .B(n2355), .Y(n2440) );
NAND2X1TS U4182 ( .A(n2355), .B(n2354), .Y(n2441) );
OAI21X2TS U4183 ( .A0(n2443), .A1(n2440), .B0(n2441), .Y(n2387) );
INVX2TS U4184 ( .A(n2387), .Y(n2376) );
CLKXOR2X2TS U4185 ( .A(n2356), .B(n2376), .Y(n2592) );
OAI21X4TS U4186 ( .A0(n2360), .A1(n2449), .B0(n2359), .Y(n2375) );
CMPR32X2TS U4187 ( .A(n2367), .B(n2366), .C(n2365), .CO(n2425), .S(n2369) );
CMPR32X2TS U4188 ( .A(n2370), .B(n2369), .C(n2368), .CO(n2424), .S(n2362) );
NOR2X6TS U4189 ( .A(n2372), .B(n2371), .Y(n2417) );
INVX2TS U4190 ( .A(n2417), .Y(n2373) );
NAND2X2TS U4191 ( .A(n2372), .B(n2371), .Y(n2416) );
XNOR2X4TS U4192 ( .A(n2375), .B(n2374), .Y(n2595) );
OAI21X1TS U4193 ( .A0(n2376), .A1(n2382), .B0(n2384), .Y(n2381) );
NOR2X2TS U4194 ( .A(n2378), .B(n2377), .Y(n2385) );
INVX2TS U4195 ( .A(n2385), .Y(n2379) );
NAND2X1TS U4196 ( .A(n2378), .B(n2377), .Y(n2383) );
NAND2X1TS U4197 ( .A(n2379), .B(n2383), .Y(n2380) );
XNOR2X2TS U4198 ( .A(n2381), .B(n2380), .Y(n2594) );
NOR2X8TS U4199 ( .A(n3675), .B(n3676), .Y(n3818) );
OAI21X1TS U4200 ( .A0(n2385), .A1(n2384), .B0(n2383), .Y(n2386) );
AOI21X4TS U4201 ( .A0(n2388), .A1(n2387), .B0(n2386), .Y(n2613) );
NOR2X2TS U4202 ( .A(n2390), .B(n2389), .Y(n2429) );
NAND2X1TS U4203 ( .A(n2390), .B(n2389), .Y(n2430) );
OAI21X1TS U4204 ( .A0(n2613), .A1(n2429), .B0(n2430), .Y(n2395) );
NOR2X2TS U4205 ( .A(n2392), .B(n2391), .Y(n2397) );
INVX2TS U4206 ( .A(n2397), .Y(n2393) );
NAND2X1TS U4207 ( .A(n2392), .B(n2391), .Y(n2396) );
NAND2X1TS U4208 ( .A(n2393), .B(n2396), .Y(n2394) );
NOR2X2TS U4209 ( .A(n2429), .B(n2397), .Y(n2604) );
INVX2TS U4210 ( .A(n2604), .Y(n2399) );
OAI21X2TS U4211 ( .A0(n2397), .A1(n2430), .B0(n2396), .Y(n2610) );
INVX2TS U4212 ( .A(n2610), .Y(n2398) );
OAI21X1TS U4213 ( .A0(n2613), .A1(n2399), .B0(n2398), .Y(n2403) );
NOR2X1TS U4214 ( .A(n2401), .B(n2400), .Y(n2603) );
INVX2TS U4215 ( .A(n2603), .Y(n2405) );
NAND2X1TS U4216 ( .A(n2401), .B(n2400), .Y(n2607) );
NAND2X1TS U4217 ( .A(n2405), .B(n2607), .Y(n2402) );
NAND2X2TS U4218 ( .A(n3255), .B(n3266), .Y(n3819) );
NAND2X1TS U4219 ( .A(n2604), .B(n2405), .Y(n2407) );
INVX2TS U4220 ( .A(n2607), .Y(n2404) );
AOI21X1TS U4221 ( .A0(n2610), .A1(n2405), .B0(n2404), .Y(n2406) );
OAI21X1TS U4222 ( .A0(n2613), .A1(n2407), .B0(n2406), .Y(n2412) );
NOR2X2TS U4223 ( .A(n2409), .B(n2408), .Y(n2606) );
INVX2TS U4224 ( .A(n2606), .Y(n2410) );
NAND2X1TS U4225 ( .A(n2409), .B(n2408), .Y(n2605) );
NAND2X1TS U4226 ( .A(n2410), .B(n2605), .Y(n2411) );
INVX2TS U4227 ( .A(n2449), .Y(n2423) );
AOI21X4TS U4228 ( .A0(n2421), .A1(n2420), .B0(n2419), .Y(n2422) );
OAI2BB1X4TS U4229 ( .A0N(n1179), .A1N(n2423), .B0(n2422), .Y(n2428) );
CMPR32X2TS U4230 ( .A(n2426), .B(n2425), .C(n2424), .CO(n2427), .S(n2371) );
XNOR2X4TS U4231 ( .A(n2428), .B(n2427), .Y(n2598) );
INVX2TS U4232 ( .A(n2429), .Y(n2431) );
NAND2X1TS U4233 ( .A(n2431), .B(n2430), .Y(n2432) );
CLKXOR2X2TS U4234 ( .A(n2613), .B(n2432), .Y(n2597) );
NOR2X4TS U4235 ( .A(n1157), .B(n3817), .Y(n2600) );
NAND2X2TS U4236 ( .A(n3818), .B(n2600), .Y(n2602) );
BUFX3TS U4237 ( .A(n2433), .Y(n2446) );
INVX2TS U4238 ( .A(n2440), .Y(n2442) );
NAND2X1TS U4239 ( .A(n2442), .B(n2441), .Y(n2444) );
CLKXOR2X2TS U4240 ( .A(n2444), .B(n2443), .Y(n2453) );
XOR2X4TS U4241 ( .A(n2449), .B(n2448), .Y(n2587) );
NAND2X1TS U4242 ( .A(n1188), .B(n2450), .Y(n2452) );
XNOR2X2TS U4243 ( .A(n2452), .B(n2451), .Y(n2586) );
OAI21X4TS U4244 ( .A0(n3652), .A1(n3705), .B0(n3653), .Y(n2591) );
INVX2TS U4245 ( .A(n2462), .Y(n2456) );
XOR2X4TS U4246 ( .A(n2456), .B(n2455), .Y(n2580) );
OAI2BB1X4TS U4247 ( .A0N(n929), .A1N(n2462), .B0(n2461), .Y(n2466) );
NAND2BX4TS U4248 ( .AN(n2464), .B(n2463), .Y(n2465) );
XNOR2X4TS U4249 ( .A(n2466), .B(n2465), .Y(n2582) );
NAND2X1TS U4250 ( .A(n1187), .B(n2469), .Y(n2471) );
CLKXOR2X2TS U4251 ( .A(n2471), .B(n2470), .Y(n2581) );
OR2X8TS U4252 ( .A(n2582), .B(n2581), .Y(n3697) );
NOR2X4TS U4253 ( .A(n2479), .B(n2480), .Y(n3319) );
NOR2X2TS U4254 ( .A(n2473), .B(n2472), .Y(n3374) );
NAND2X2TS U4255 ( .A(n3308), .B(n3307), .Y(n3377) );
NAND2X1TS U4256 ( .A(n2473), .B(n2472), .Y(n3375) );
OAI21X2TS U4257 ( .A0(n3374), .A1(n3377), .B0(n3375), .Y(n3301) );
INVX2TS U4258 ( .A(n3300), .Y(n2476) );
AOI21X4TS U4259 ( .A0(n3299), .A1(n3301), .B0(n2476), .Y(n3297) );
NOR2X2TS U4260 ( .A(n2478), .B(n2477), .Y(n3294) );
NAND2X2TS U4261 ( .A(n2478), .B(n2477), .Y(n3295) );
OAI21X4TS U4262 ( .A0(n3297), .A1(n3294), .B0(n3295), .Y(n2494) );
AOI21X4TS U4263 ( .A0(n2484), .A1(n2494), .B0(n2483), .Y(n2542) );
INVX2TS U4264 ( .A(n2521), .Y(n2487) );
NAND2X2TS U4265 ( .A(n2486), .B(n2485), .Y(n2520) );
INVX2TS U4266 ( .A(n2489), .Y(n2491) );
INVX2TS U4267 ( .A(n2495), .Y(n2497) );
INVX2TS U4268 ( .A(n2500), .Y(n2502) );
XNOR2X1TS U4269 ( .A(n2504), .B(n2503), .Y(n3431) );
NAND2X2TS U4270 ( .A(n2506), .B(n2505), .Y(n3447) );
INVX2TS U4271 ( .A(n3447), .Y(n2507) );
AOI21X4TS U4272 ( .A0(n3448), .A1(n3449), .B0(n2507), .Y(n3336) );
NOR2X2TS U4273 ( .A(n2509), .B(n2508), .Y(n2522) );
NOR2X2TS U4274 ( .A(n2521), .B(n2522), .Y(n2560) );
INVX2TS U4275 ( .A(n2560), .Y(n2511) );
NAND2X1TS U4276 ( .A(n2509), .B(n2508), .Y(n2523) );
OAI21X2TS U4277 ( .A0(n2522), .A1(n2520), .B0(n2523), .Y(n2566) );
INVX2TS U4278 ( .A(n2566), .Y(n2510) );
NOR2X1TS U4279 ( .A(n2513), .B(n2512), .Y(n2559) );
INVX2TS U4280 ( .A(n2559), .Y(n2544) );
NAND2X1TS U4281 ( .A(n2513), .B(n2512), .Y(n2563) );
NAND2X1TS U4282 ( .A(n2544), .B(n2563), .Y(n2514) );
NAND2X2TS U4283 ( .A(n2517), .B(n2516), .Y(n2519) );
XNOR2X4TS U4284 ( .A(n2519), .B(n2518), .Y(n2533) );
INVX2TS U4285 ( .A(n2522), .Y(n2524) );
NAND2X1TS U4286 ( .A(n2524), .B(n2523), .Y(n2525) );
INVX2TS U4287 ( .A(n3337), .Y(n3492) );
AOI21X4TS U4288 ( .A0(n3496), .A1(n3492), .B0(n2534), .Y(n2535) );
OAI21X4TS U4289 ( .A0(n3336), .A1(n2536), .B0(n2535), .Y(n3515) );
INVX2TS U4290 ( .A(n2537), .Y(n2538) );
NAND2X2TS U4291 ( .A(n2539), .B(n2538), .Y(n2541) );
XOR2X4TS U4292 ( .A(n2541), .B(n2540), .Y(n2553) );
NAND2X1TS U4293 ( .A(n2560), .B(n2544), .Y(n2546) );
INVX2TS U4294 ( .A(n2563), .Y(n2543) );
AOI21X1TS U4295 ( .A0(n2566), .A1(n2544), .B0(n2543), .Y(n2545) );
OAI21X1TS U4296 ( .A0(n2542), .A1(n2546), .B0(n2545), .Y(n2551) );
NOR2X2TS U4297 ( .A(n2548), .B(n2547), .Y(n2562) );
INVX2TS U4298 ( .A(n2562), .Y(n2549) );
NAND2X1TS U4299 ( .A(n2548), .B(n2547), .Y(n2561) );
NAND2X1TS U4300 ( .A(n2549), .B(n2561), .Y(n2550) );
XNOR2X2TS U4301 ( .A(n2551), .B(n2550), .Y(n2552) );
AOI21X4TS U4302 ( .A0(n3515), .A1(n3513), .B0(n2554), .Y(n3552) );
NAND2X2TS U4303 ( .A(n2556), .B(n2555), .Y(n2557) );
XNOR2X4TS U4304 ( .A(n2558), .B(n2557), .Y(n2570) );
NOR2X1TS U4305 ( .A(n2559), .B(n2562), .Y(n2565) );
NAND2X1TS U4306 ( .A(n2560), .B(n2565), .Y(n2568) );
AOI21X1TS U4307 ( .A0(n2566), .A1(n2565), .B0(n2564), .Y(n2567) );
OAI21X2TS U4308 ( .A0(n2542), .A1(n2568), .B0(n2567), .Y(n2569) );
OAI21X4TS U4309 ( .A0(n3552), .A1(n3548), .B0(n3549), .Y(n3582) );
INVX2TS U4310 ( .A(n2572), .Y(n2574) );
INVX4TS U4311 ( .A(n3580), .Y(n2578) );
AOI21X4TS U4312 ( .A0(n3582), .A1(n3581), .B0(n2578), .Y(n3602) );
INVX6TS U4313 ( .A(n3601), .Y(n3693) );
NAND2X4TS U4314 ( .A(n2582), .B(n2581), .Y(n3696) );
INVX4TS U4315 ( .A(n3696), .Y(n2583) );
AOI21X4TS U4316 ( .A0(n3697), .A1(n3693), .B0(n2583), .Y(n2584) );
OAI21X4TS U4317 ( .A0(n2585), .A1(n3602), .B0(n2584), .Y(n3706) );
NOR2X8TS U4318 ( .A(n2587), .B(n2586), .Y(n3704) );
NOR2X8TS U4319 ( .A(n3704), .B(n3652), .Y(n2588) );
NOR2X8TS U4320 ( .A(n2591), .B(n2590), .Y(n3674) );
OA21X4TS U4321 ( .A0(n3676), .A1(n3673), .B0(n3677), .Y(n2596) );
NAND2X6TS U4322 ( .A(n2598), .B(n2597), .Y(n3820) );
NOR2X2TS U4323 ( .A(n3820), .B(n1157), .Y(n2599) );
AOI21X2TS U4324 ( .A0(n2600), .A1(n3823), .B0(n2599), .Y(n2601) );
NOR2X1TS U4325 ( .A(n2603), .B(n2606), .Y(n2609) );
NAND2X1TS U4326 ( .A(n2604), .B(n2609), .Y(n2612) );
AOI21X1TS U4327 ( .A0(n2610), .A1(n2609), .B0(n2608), .Y(n2611) );
NOR2X1TS U4328 ( .A(n2615), .B(n2619), .Y(n2621) );
NAND2X1TS U4329 ( .A(n2616), .B(n2621), .Y(n2624) );
AOI21X1TS U4330 ( .A0(n2622), .A1(n2621), .B0(n2620), .Y(n2623) );
AO21X2TS U4331 ( .A0(n2629), .A1(n2628), .B0(n2631), .Y(n3035) );
INVX2TS U4332 ( .A(n2630), .Y(n2632) );
NOR2X2TS U4333 ( .A(n2632), .B(n2631), .Y(n3034) );
NAND2X1TS U4334 ( .A(n2974), .B(n2985), .Y(n2633) );
NAND2X1TS U4335 ( .A(n2634), .B(n2633), .Y(n2635) );
INVX2TS U4336 ( .A(n2643), .Y(n2645) );
XOR2X4TS U4337 ( .A(n2647), .B(n2646), .Y(n2648) );
NOR2X4TS U4338 ( .A(n999), .B(n2651), .Y(n2679) );
NAND2X2TS U4339 ( .A(n5619), .B(DP_OP_496J311_122_3540_n1203), .Y(n2652) );
XOR2X4TS U4340 ( .A(n2653), .B(n2652), .Y(n2654) );
NAND2X2TS U4341 ( .A(n2654), .B(n2655), .Y(n2680) );
OR2X4TS U4342 ( .A(n2654), .B(n2655), .Y(n2683) );
XNOR2X4TS U4343 ( .A(n2657), .B(n2656), .Y(n3134) );
INVX2TS U4344 ( .A(n3134), .Y(n2664) );
AOI21X4TS U4345 ( .A0(n2663), .A1(n2659), .B0(n2658), .Y(n2661) );
XOR2X4TS U4346 ( .A(n2661), .B(n2660), .Y(n2726) );
NAND2X2TS U4347 ( .A(n2727), .B(n2702), .Y(n3847) );
NOR2X1TS U4348 ( .A(n2664), .B(n3847), .Y(n2910) );
OAI21X2TS U4349 ( .A0(n2865), .A1(n2868), .B0(n2665), .Y(n2667) );
NAND2X4TS U4350 ( .A(n2667), .B(n2666), .Y(n2784) );
XOR2X4TS U4351 ( .A(n2669), .B(n2668), .Y(n2718) );
INVX2TS U4352 ( .A(n2671), .Y(n2672) );
XNOR2X4TS U4353 ( .A(n2674), .B(n2673), .Y(n2753) );
INVX2TS U4354 ( .A(n2748), .Y(n2678) );
INVX2TS U4355 ( .A(n2810), .Y(n2682) );
INVX2TS U4356 ( .A(n2680), .Y(n2681) );
OAI21X4TS U4357 ( .A0(n2686), .A1(n2685), .B0(n2684), .Y(n2751) );
INVX4TS U4358 ( .A(n2751), .Y(n2709) );
NAND2X2TS U4359 ( .A(n2690), .B(n2689), .Y(n2691) );
XOR2X4TS U4360 ( .A(n2692), .B(n2691), .Y(n2879) );
OAI21X4TS U4361 ( .A0(n2709), .A1(n2745), .B0(n2747), .Y(n2694) );
XNOR2X4TS U4362 ( .A(n2695), .B(n2694), .Y(n3083) );
XNOR2X4TS U4363 ( .A(n3083), .B(n988), .Y(n2912) );
OAI2BB1X4TS U4364 ( .A0N(n5469), .A1N(n1071), .B0(
DP_OP_496J311_122_3540_n1114), .Y(n2697) );
ADDFHX4TS U4365 ( .A(FPMULT_Op_MY[10]), .B(n2698), .CI(n2881), .CO(n2770),
.S(n2761) );
OAI21X4TS U4366 ( .A0(n2699), .A1(n951), .B0(DP_OP_496J311_122_3540_n1103),
.Y(n2701) );
XNOR2X4TS U4367 ( .A(n2701), .B(n2700), .Y(n2725) );
XNOR2X4TS U4368 ( .A(n2921), .B(n2702), .Y(n2773) );
XOR2X4TS U4369 ( .A(n2705), .B(n2704), .Y(n2706) );
INVX2TS U4370 ( .A(n2745), .Y(n2707) );
NAND2X2TS U4371 ( .A(n2707), .B(n2747), .Y(n2708) );
XOR2X4TS U4372 ( .A(n2709), .B(n2708), .Y(n3104) );
INVX4TS U4373 ( .A(n2735), .Y(n2710) );
OAI21X4TS U4374 ( .A0(n2731), .A1(n2710), .B0(n2732), .Y(n2714) );
XOR2X4TS U4375 ( .A(n2714), .B(n2713), .Y(n2715) );
XOR2X4TS U4376 ( .A(n2717), .B(n2716), .Y(n2763) );
AO21X4TS U4377 ( .A0(n2735), .A1(n2720), .B0(n2719), .Y(n2724) );
XNOR2X4TS U4378 ( .A(n2724), .B(n2723), .Y(n2801) );
XNOR2X4TS U4379 ( .A(n2801), .B(n2852), .Y(n2743) );
OAI22X2TS U4380 ( .A0(n2737), .A1(n2928), .B0(n2743), .B1(n1068), .Y(n2741)
);
XNOR2X4TS U4381 ( .A(n2726), .B(n2725), .Y(n2728) );
INVX2TS U4382 ( .A(n2654), .Y(n2738) );
OAI22X1TS U4383 ( .A0(n3224), .A1(n2738), .B0(n3028), .B1(n2744), .Y(n2740)
);
XNOR2X1TS U4384 ( .A(n2921), .B(n2850), .Y(n2803) );
XNOR2X4TS U4385 ( .A(n2735), .B(n2734), .Y(n2736) );
XNOR2X1TS U4386 ( .A(n2921), .B(n2929), .Y(n2742) );
OAI22X1TS U4387 ( .A0(n3032), .A1(n2803), .B0(n2742), .B1(n3031), .Y(n2894)
);
XOR2X4TS U4388 ( .A(n2801), .B(n2979), .Y(n2805) );
XNOR2X2TS U4389 ( .A(n2881), .B(n2736), .Y(n2804) );
OAI22X2TS U4390 ( .A0(n2737), .A1(n1068), .B0(n2928), .B1(n2804), .Y(n2807)
);
INVX2TS U4391 ( .A(n1000), .Y(n2739) );
OAI22X1TS U4392 ( .A0(n3224), .A1(n2739), .B0(n3028), .B1(n2738), .Y(n2806)
);
INVX2TS U4393 ( .A(n3484), .Y(n2936) );
ADDFHX2TS U4394 ( .A(n2924), .B(n2741), .CI(n2740), .CO(n2920), .S(n2895) );
XNOR2X1TS U4395 ( .A(n2921), .B(n2976), .Y(n2922) );
OAI22X1TS U4396 ( .A0(n3032), .A1(n2742), .B0(n2922), .B1(n3031), .Y(n2919)
);
INVX2TS U4397 ( .A(n2852), .Y(n2926) );
OAI22X2TS U4398 ( .A0(n2743), .A1(n2928), .B0(n1068), .B1(n2926), .Y(n2925)
);
INVX2TS U4399 ( .A(n3485), .Y(n2935) );
NOR2X4TS U4400 ( .A(n2745), .B(n2748), .Y(n2750) );
OAI21X4TS U4401 ( .A0(n2748), .A1(n2747), .B0(n2746), .Y(n2749) );
AOI21X4TS U4402 ( .A0(n2751), .A1(n2750), .B0(n2749), .Y(n2752) );
BUFX12TS U4403 ( .A(n2752), .Y(n2827) );
XNOR2X4TS U4404 ( .A(n2929), .B(DP_OP_496J311_122_3540_n1138), .Y(n2755) );
NOR2X4TS U4405 ( .A(n2755), .B(n2754), .Y(n2795) );
INVX2TS U4406 ( .A(n2795), .Y(n2756) );
NAND2X4TS U4407 ( .A(n2755), .B(n2754), .Y(n2797) );
NAND2X2TS U4408 ( .A(n2756), .B(n2797), .Y(n2757) );
ADDFHX2TS U4409 ( .A(FPMULT_Op_MY[8]), .B(DP_OP_496J311_122_3540_n1464),
.CI(n2759), .CO(n2762), .S(n2788) );
XNOR2X4TS U4410 ( .A(n2761), .B(n2769), .Y(n2793) );
BUFX4TS U4411 ( .A(n2763), .Y(n2789) );
NAND2X1TS U4412 ( .A(n2782), .B(n2789), .Y(n2765) );
OAI21X2TS U4413 ( .A0(n2782), .A1(n2789), .B0(n1033), .Y(n2764) );
NAND2X2TS U4414 ( .A(n2765), .B(n2764), .Y(n2781) );
NAND2X2TS U4415 ( .A(n2793), .B(n2781), .Y(n2766) );
XOR2X4TS U4416 ( .A(n2767), .B(n2766), .Y(n2768) );
XOR2X1TS U4417 ( .A(n2770), .B(n2769), .Y(n2771) );
NOR2X2TS U4418 ( .A(n2772), .B(n2771), .Y(n2774) );
XNOR2X2TS U4419 ( .A(n3083), .B(n2972), .Y(n2832) );
NOR2X4TS U4420 ( .A(n2976), .B(n2777), .Y(n2798) );
INVX2TS U4421 ( .A(n2798), .Y(n2778) );
NAND2X2TS U4422 ( .A(n2976), .B(n2777), .Y(n2796) );
XNOR2X4TS U4423 ( .A(n2780), .B(n2779), .Y(n2815) );
XNOR2X4TS U4424 ( .A(n2781), .B(n2793), .Y(n3099) );
NOR2X1TS U4425 ( .A(n1033), .B(n2788), .Y(n2783) );
XOR2X1TS U4426 ( .A(n2789), .B(n2788), .Y(n2790) );
XOR2X2TS U4427 ( .A(n2793), .B(n2792), .Y(n2794) );
NAND2X4TS U4428 ( .A(n2787), .B(n2794), .Y(n3102) );
BUFX12TS U4429 ( .A(n3102), .Y(n3062) );
NOR2X4TS U4430 ( .A(n2795), .B(n2798), .Y(n2823) );
INVX2TS U4431 ( .A(n2823), .Y(n2800) );
OAI21X4TS U4432 ( .A0(n2798), .A1(n2797), .B0(n2796), .Y(n2824) );
INVX2TS U4433 ( .A(n2824), .Y(n2799) );
INVX4TS U4434 ( .A(n2801), .Y(n3223) );
XNOR2X4TS U4435 ( .A(n2802), .B(n3223), .Y(n3037) );
XNOR2X1TS U4436 ( .A(n2921), .B(n2879), .Y(n2833) );
OAI22X1TS U4437 ( .A0(n3032), .A1(n2833), .B0(n2803), .B1(n3031), .Y(n2849)
);
OAI22X4TS U4438 ( .A0(n2835), .A1(n3141), .B0(n2805), .B1(n3167), .Y(n2837)
);
NOR2BX1TS U4439 ( .AN(n1000), .B(n3028), .Y(n2836) );
XNOR2X2TS U4440 ( .A(n3134), .B(n988), .Y(n2830) );
OAI22X4TS U4441 ( .A0(n2911), .A1(n2830), .B0(n2809), .B1(n3278), .Y(n2818)
);
NOR2BX2TS U4442 ( .AN(n3166), .B(n989), .Y(n2819) );
XOR2X2TS U4443 ( .A(n2818), .B(n2819), .Y(n2814) );
OAI22X1TS U4444 ( .A0(n2916), .A1(n995), .B0(n2816), .B1(n2776), .Y(n2915)
);
NAND2X2TS U4445 ( .A(n2819), .B(n2817), .Y(n2822) );
NAND2X2TS U4446 ( .A(n2818), .B(n2817), .Y(n2821) );
NAND2X1TS U4447 ( .A(n2819), .B(n2818), .Y(n2820) );
NAND2X1TS U4448 ( .A(n2824), .B(n2801), .Y(n2825) );
OAI21X4TS U4449 ( .A0(n2827), .A1(n2826), .B0(n2825), .Y(n3845) );
XNOR2X2TS U4450 ( .A(n3845), .B(n3079), .Y(n2907) );
OAI22X1TS U4451 ( .A0(n2828), .A1(n3062), .B0(n2907), .B1(n1038), .Y(n2913)
);
NAND2BX1TS U4452 ( .AN(n3166), .B(n988), .Y(n2829) );
XNOR2X1TS U4453 ( .A(n3166), .B(n988), .Y(n2831) );
OAI22X2TS U4454 ( .A0(n2911), .A1(n2831), .B0(n3278), .B1(n2830), .Y(n2891)
);
XNOR2X1TS U4455 ( .A(n2921), .B(n2654), .Y(n2857) );
OAI22X1TS U4456 ( .A0(n3032), .A1(n2857), .B0(n2833), .B1(n3031), .Y(n2861)
);
OAI22X2TS U4457 ( .A0(n2928), .A1(n2853), .B0(n2834), .B1(n1068), .Y(n2856)
);
OAI22X2TS U4458 ( .A0(n2835), .A1(n3167), .B0(n3141), .B1(n2851), .Y(n2855)
);
INVX2TS U4459 ( .A(n3451), .Y(n2841) );
INVX2TS U4460 ( .A(n2840), .Y(n2888) );
ADDFHX2TS U4461 ( .A(n2843), .B(n2842), .CI(n2841), .CO(n2890), .S(n2965) );
OAI22X1TS U4462 ( .A0(n2845), .A1(n1038), .B0(n2887), .B1(n3062), .Y(n2964)
);
XNOR2X2TS U4463 ( .A(n2850), .B(n1033), .Y(n2880) );
XNOR2X4TS U4464 ( .A(n2852), .B(n2654), .Y(n2877) );
NOR2BX1TS U4465 ( .AN(n1000), .B(n2854), .Y(n2884) );
CMPR22X2TS U4466 ( .A(n2856), .B(n2855), .CO(n2860), .S(n2957) );
XNOR2X1TS U4467 ( .A(n2921), .B(n1000), .Y(n2858) );
OAI22X1TS U4468 ( .A0(n3032), .A1(n2858), .B0(n2857), .B1(n3031), .Y(n2956)
);
XNOR2X2TS U4469 ( .A(n2866), .B(n2869), .Y(n2867) );
XNOR2X2TS U4470 ( .A(n3845), .B(n3143), .Y(n2896) );
OAI22X1TS U4471 ( .A0(n2962), .A1(n3146), .B0(n2896), .B1(n3165), .Y(n2897)
);
XNOR2X1TS U4472 ( .A(n2874), .B(n3134), .Y(n2951) );
OAI22X1TS U4473 ( .A0(n2776), .A1(n2951), .B0(n995), .B1(n2875), .Y(n3053)
);
OAI22X2TS U4474 ( .A0(n3032), .A1(n3030), .B0(n2876), .B1(n3031), .Y(n3411)
);
INVX2TS U4475 ( .A(n3411), .Y(n2961) );
XNOR2X1TS U4476 ( .A(n2881), .B(n1000), .Y(n2878) );
XNOR2X2TS U4477 ( .A(n2879), .B(n1033), .Y(n2883) );
OAI22X2TS U4478 ( .A0(n3141), .A1(n2883), .B0(n2880), .B1(n3167), .Y(n3076)
);
OAI22X4TS U4479 ( .A0(n2928), .A1(n2926), .B0(n1068), .B1(n2882), .Y(n3368)
);
XNOR2X2TS U4480 ( .A(n1033), .B(n2654), .Y(n3140) );
ADDFHX2TS U4481 ( .A(n2886), .B(n2885), .CI(n2884), .CO(n2958), .S(n3364) );
OAI22X1TS U4482 ( .A0(n2887), .A1(n1038), .B0(n2959), .B1(n3062), .Y(n3051)
);
ADDFHX2TS U4483 ( .A(n2895), .B(n2894), .CI(n2893), .CO(n3484), .S(n3466) );
OAI22X1TS U4484 ( .A0(n2896), .A1(n3146), .B0(n2909), .B1(n3165), .Y(n2904)
);
ADDFHX2TS U4485 ( .A(n2906), .B(n2905), .CI(n2904), .CO(n2931), .S(n2968) );
XNOR2X2TS U4486 ( .A(n2844), .B(n988), .Y(n2995) );
OAI22X1TS U4487 ( .A0(n2995), .A1(n3278), .B0(n2912), .B1(n2911), .Y(n2999)
);
OAI22X1TS U4488 ( .A0(n2916), .A1(n2776), .B0(n2973), .B1(n995), .Y(n2988)
);
INVX2TS U4489 ( .A(n3104), .Y(n2917) );
NOR2X1TS U4490 ( .A(n2917), .B(n989), .Y(n2998) );
INVX2TS U4491 ( .A(n3520), .Y(n2997) );
OAI22X1TS U4492 ( .A0(n3032), .A1(n2922), .B0(n2975), .B1(n3031), .Y(n2983)
);
CMPR32X2TS U4493 ( .A(n2925), .B(n2924), .C(n2923), .CO(n2982), .S(n2918) );
AO21X4TS U4494 ( .A0(n2928), .A1(n1068), .B0(n2926), .Y(n2980) );
INVX2TS U4495 ( .A(n2929), .Y(n2977) );
OAI22X1TS U4496 ( .A0(n3224), .A1(n2930), .B0(n3028), .B1(n2977), .Y(n2978)
);
INVX2TS U4497 ( .A(n2933), .Y(n2994) );
INVX2TS U4498 ( .A(n2934), .Y(n2993) );
ADDFHX2TS U4499 ( .A(n2937), .B(n2936), .CI(n2935), .CO(n2992), .S(n2940) );
NOR2X8TS U4500 ( .A(n3200), .B(n3199), .Y(n3898) );
XOR2X4TS U4501 ( .A(n2948), .B(n2947), .Y(n2949) );
INVX2TS U4502 ( .A(n2972), .Y(n3211) );
XNOR2X1TS U4503 ( .A(n2972), .B(n3166), .Y(n2952) );
OAI22X2TS U4504 ( .A0(n2776), .A1(n2952), .B0(n995), .B1(n2951), .Y(n3074)
);
INVX2TS U4505 ( .A(n2954), .Y(n3085) );
XNOR2X2TS U4506 ( .A(n3104), .B(n3079), .Y(n3061) );
OAI22X2TS U4507 ( .A0(n2959), .A1(n1038), .B0(n3062), .B1(n3061), .Y(n3055)
);
ADDHX1TS U4508 ( .A(n2961), .B(n2960), .CO(n3052), .S(n3054) );
OAI22X1TS U4509 ( .A0(n3057), .A1(n3146), .B0(n2962), .B1(n3165), .Y(n3063)
);
NOR2X4TS U4510 ( .A(n3198), .B(n3197), .Y(n3749) );
XNOR2X2TS U4511 ( .A(n3845), .B(n2972), .Y(n3021) );
OAI22X1TS U4512 ( .A0(n2973), .A1(n2776), .B0(n3021), .B1(n995), .Y(n3013)
);
INVX2TS U4513 ( .A(n2974), .Y(n3012) );
INVX2TS U4514 ( .A(n2987), .Y(n3011) );
INVX2TS U4515 ( .A(n2976), .Y(n3029) );
OAI22X2TS U4516 ( .A0(n3224), .A1(n2977), .B0(n3028), .B1(n3029), .Y(n3220)
);
INVX2TS U4517 ( .A(n3220), .Y(n3018) );
CMPR32X2TS U4518 ( .A(n2980), .B(n2979), .C(n2978), .CO(n3017), .S(n2981) );
INVX2TS U4519 ( .A(n3543), .Y(n3024) );
INVX2TS U4520 ( .A(n3083), .Y(n2984) );
NOR2X2TS U4521 ( .A(n2984), .B(n989), .Y(n3027) );
INVX2TS U4522 ( .A(n2985), .Y(n3025) );
OAI22X1TS U4523 ( .A0(n3038), .A1(n3278), .B0(n2995), .B1(n2911), .Y(n3016)
);
ADDFHX2TS U4524 ( .A(n2998), .B(n2997), .CI(n2996), .CO(n3015), .S(n2986) );
CMPR32X2TS U4525 ( .A(n3001), .B(n3000), .C(n2999), .CO(n3014), .S(n3004) );
ADDFHX4TS U4526 ( .A(n3007), .B(n3006), .CI(n3005), .CO(n3201), .S(n3199) );
INVX2TS U4527 ( .A(n3578), .Y(n3228) );
INVX2TS U4528 ( .A(n2844), .Y(n3020) );
OAI22X1TS U4529 ( .A0(n3021), .A1(n2776), .B0(n995), .B1(n3211), .Y(n3226)
);
CMPR32X2TS U4530 ( .A(n3024), .B(n3023), .C(n3022), .CO(n3209), .S(n3009) );
OAI22X1TS U4531 ( .A0(n3224), .A1(n3029), .B0(n3028), .B1(n3223), .Y(n3221)
);
INVX2TS U4532 ( .A(n3577), .Y(n3214) );
INVX2TS U4533 ( .A(n3036), .Y(n3213) );
OAI22X1TS U4534 ( .A0(n3038), .A1(n2911), .B0(n3225), .B1(n3278), .Y(n3216)
);
ADDFHX4TS U4535 ( .A(n3044), .B(n3043), .CI(n3042), .CO(n3204), .S(n3202) );
ADDFHX4TS U4536 ( .A(n3047), .B(n3046), .CI(n3045), .CO(n3197), .S(n3095) );
CMPR32X2TS U4537 ( .A(n3053), .B(n3052), .C(n3051), .CO(n3048), .S(n3090) );
ADDFHX2TS U4538 ( .A(n3056), .B(n3055), .CI(n3054), .CO(n3064), .S(n3112) );
NOR2BX1TS U4539 ( .AN(n1057), .B(n2768), .Y(n3109) );
ADDFHX2TS U4540 ( .A(n3060), .B(n3059), .CI(n3058), .CO(n2960), .S(n3108) );
XNOR2X4TS U4541 ( .A(n3134), .B(n3079), .Y(n3100) );
ADDFX2TS U4542 ( .A(n3065), .B(n3064), .CI(n3063), .CO(n3067), .S(n3088) );
INVX2TS U4543 ( .A(n3072), .Y(n3115) );
INVX2TS U4544 ( .A(n3369), .Y(n3123) );
NAND2BX2TS U4545 ( .AN(n1057), .B(n3079), .Y(n3080) );
XNOR2X2TS U4546 ( .A(n3083), .B(n3143), .Y(n3105) );
OAI22X1TS U4547 ( .A0(n3084), .A1(n3165), .B0(n3105), .B1(n3146), .Y(n3124)
);
OAI2BB1X2TS U4548 ( .A0N(n3092), .A1N(n3091), .B0(n3188), .Y(n3094) );
NAND2X1TS U4549 ( .A(n3186), .B(n3185), .Y(n3093) );
OA21X4TS U4550 ( .A0(n3755), .A1(n3942), .B0(n3756), .Y(n3196) );
NOR2X4TS U4551 ( .A(n3755), .B(n3941), .Y(n3194) );
XNOR2X1TS U4552 ( .A(n3099), .B(n3166), .Y(n3101) );
OAI22X2TS U4553 ( .A0(n3102), .A1(n3101), .B0(n1038), .B1(n3100), .Y(n3139)
);
INVX2TS U4554 ( .A(n3103), .Y(n3138) );
XNOR2X2TS U4555 ( .A(n3104), .B(n3143), .Y(n3135) );
OAI22X2TS U4556 ( .A0(n3105), .A1(n3165), .B0(n3135), .B1(n3146), .Y(n3137)
);
INVX2TS U4557 ( .A(n3116), .Y(n3153) );
INVX2TS U4558 ( .A(n3367), .Y(n3119) );
INVX2TS U4559 ( .A(n3117), .Y(n3118) );
INVX2TS U4560 ( .A(n1889), .Y(n3145) );
NAND2BX4TS U4561 ( .AN(n3182), .B(n3130), .Y(n3561) );
ADDFHX4TS U4562 ( .A(n3133), .B(n3132), .CI(n3131), .CO(n3183), .S(n3181) );
XNOR2X2TS U4563 ( .A(n3143), .B(n3134), .Y(n3147) );
INVX2TS U4564 ( .A(n1891), .Y(n3158) );
INVX2TS U4565 ( .A(n3136), .Y(n3157) );
CMPR32X2TS U4566 ( .A(n3139), .B(n3138), .C(n3137), .CO(n3129), .S(n3149) );
OAI22X2TS U4567 ( .A0(n3141), .A1(n1000), .B0(n3140), .B1(n3167), .Y(n3387)
);
INVX2TS U4568 ( .A(n3387), .Y(n3164) );
INVX2TS U4569 ( .A(n3388), .Y(n3163) );
CMPR32X2TS U4570 ( .A(n3397), .B(n3145), .C(n3144), .CO(n3152), .S(n3155) );
INVX2TS U4571 ( .A(n3751), .Y(n3161) );
ADDFHX4TS U4572 ( .A(n3150), .B(n3149), .CI(n3148), .CO(n3180), .S(n3178) );
CMPR32X2TS U4573 ( .A(n3153), .B(n3152), .C(n3151), .CO(n3133), .S(n3177) );
OR2X4TS U4574 ( .A(n3178), .B(n3177), .Y(n3506) );
NOR2X4TS U4575 ( .A(n3176), .B(n3175), .Y(n3477) );
ADDFHX2TS U4576 ( .A(n3161), .B(n3160), .CI(n1891), .CO(n3154), .S(n3173) );
NOR2BX1TS U4577 ( .AN(n1000), .B(n3167), .Y(n3686) );
INVX2TS U4578 ( .A(n3686), .Y(n3169) );
INVX2TS U4579 ( .A(n3946), .Y(n3445) );
INVX2TS U4580 ( .A(n3443), .Y(n3171) );
INVX2TS U4581 ( .A(n3472), .Y(n3174) );
NAND2X2TS U4582 ( .A(n3176), .B(n3175), .Y(n3478) );
OAI21X4TS U4583 ( .A0(n3477), .A1(n3480), .B0(n3478), .Y(n3507) );
AOI21X4TS U4584 ( .A0(n3506), .A1(n3507), .B0(n3179), .Y(n3536) );
OAI21X4TS U4585 ( .A0(n3533), .A1(n3536), .B0(n3535), .Y(n3559) );
NAND2X4TS U4586 ( .A(n3183), .B(n3182), .Y(n3560) );
AOI21X4TS U4587 ( .A0(n3561), .A1(n3559), .B0(n3184), .Y(n3591) );
XOR2X4TS U4588 ( .A(n3186), .B(n3185), .Y(n3187) );
XOR2X4TS U4589 ( .A(n3188), .B(n3187), .Y(n3193) );
NOR2X4TS U4590 ( .A(n3193), .B(n3192), .Y(n3588) );
OAI21X4TS U4591 ( .A0(n3591), .A1(n3588), .B0(n3589), .Y(n3940) );
NAND2X4TS U4592 ( .A(n3194), .B(n3940), .Y(n3195) );
ADDFHX4TS U4593 ( .A(n3207), .B(n3206), .CI(n3205), .CO(n3233), .S(n3203) );
INVX2TS U4594 ( .A(n2815), .Y(n3215) );
ADDFHX1TS U4595 ( .A(n3218), .B(n3217), .CI(n3216), .CO(n3287), .S(n3208) );
INVX4TS U4596 ( .A(n3222), .Y(n3281) );
NOR2X2TS U4597 ( .A(n3224), .B(n3223), .Y(n3280) );
XNOR2X1TS U4598 ( .A(n3281), .B(n3280), .Y(n3599) );
XNOR2X1TS U4599 ( .A(n3845), .B(n988), .Y(n3279) );
OAI22X1TS U4600 ( .A0(n3225), .A1(n2911), .B0(n3279), .B1(n3278), .Y(n3277)
);
CMPR32X2TS U4601 ( .A(n3228), .B(n3227), .C(n3226), .CO(n3276), .S(n3210) );
NOR2X4TS U4602 ( .A(n3233), .B(n3232), .Y(n3838) );
XOR2X4TS U4603 ( .A(n3918), .B(n3234), .Y(n3834) );
INVX2TS U4604 ( .A(n3235), .Y(n3244) );
INVX2TS U4605 ( .A(n3243), .Y(n3236) );
NAND2X1TS U4606 ( .A(n3236), .B(n3242), .Y(n3237) );
XOR2X1TS U4607 ( .A(n3244), .B(n3237), .Y(n3789) );
INVX2TS U4608 ( .A(n3818), .Y(n3239) );
INVX8TS U4609 ( .A(n3823), .Y(n3238) );
OAI21X4TS U4610 ( .A0(n3825), .A1(n3239), .B0(n3238), .Y(n3241) );
XNOR2X4TS U4611 ( .A(n3241), .B(n3240), .Y(n3663) );
INVX2TS U4612 ( .A(n3245), .Y(n3247) );
XNOR2X1TS U4613 ( .A(n3249), .B(n3248), .Y(n3258) );
XOR2X4TS U4614 ( .A(n3873), .B(n3250), .Y(n3877) );
INVX2TS U4615 ( .A(n3674), .Y(n3254) );
INVX2TS U4616 ( .A(n3820), .Y(n3251) );
OAI2BB1X4TS U4617 ( .A0N(n3254), .A1N(n916), .B0(n3253), .Y(n3256) );
XNOR2X4TS U4618 ( .A(n3256), .B(n3261), .Y(n3731) );
INVX2TS U4619 ( .A(n3865), .Y(n3259) );
XOR2X1TS U4620 ( .A(n3866), .B(n3260), .Y(n3863) );
NOR2X4TS U4621 ( .A(n3817), .B(n3261), .Y(n3263) );
NOR2X2TS U4622 ( .A(n3820), .B(n3261), .Y(n3262) );
AOI21X4TS U4623 ( .A0(n3823), .A1(n3263), .B0(n3262), .Y(n3264) );
OAI21X4TS U4624 ( .A0(n3265), .A1(n3825), .B0(n3264), .Y(n3268) );
INVX2TS U4625 ( .A(n3266), .Y(n3267) );
XNOR2X4TS U4626 ( .A(n3268), .B(n3267), .Y(n3726) );
NAND2X4TS U4627 ( .A(n3873), .B(n3269), .Y(n3270) );
INVX2TS U4628 ( .A(n3841), .Y(n3271) );
OAI22X1TS U4629 ( .A0(n3279), .A1(n2911), .B0(n3278), .B1(n989), .Y(n3854)
);
INVX2TS U4630 ( .A(n3280), .Y(n3851) );
OR2X2TS U4631 ( .A(n3281), .B(n3280), .Y(n3850) );
INVX2TS U4632 ( .A(n3037), .Y(n3282) );
CMPR32X2TS U4633 ( .A(n3285), .B(n3284), .C(n3283), .CO(n3852), .S(n3288) );
CMPR32X2TS U4634 ( .A(n3288), .B(n3287), .C(n3286), .CO(n3842), .S(n3274) );
NOR2X6TS U4635 ( .A(n3290), .B(n3289), .Y(n3840) );
INVX2TS U4636 ( .A(n3840), .Y(n3291) );
NAND2X2TS U4637 ( .A(n3290), .B(n3289), .Y(n3839) );
INVX2TS U4638 ( .A(n3294), .Y(n3296) );
NAND2X1TS U4639 ( .A(n3296), .B(n3295), .Y(n3298) );
XNOR2X2TS U4640 ( .A(n3302), .B(n3301), .Y(FPMULT_Sgf_operation_Result[3])
);
NAND2X1TS U4641 ( .A(n3304), .B(n3303), .Y(n3306) );
XNOR2X2TS U4642 ( .A(n3306), .B(n3305), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[3]) );
NAND2X1TS U4643 ( .A(n3312), .B(n3311), .Y(n3313) );
CLKXOR2X2TS U4644 ( .A(n3313), .B(n3373), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[2]) );
INVX2TS U4645 ( .A(n3314), .Y(n3316) );
CLKXOR2X2TS U4646 ( .A(n3318), .B(n3317), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[4]) );
NAND2X1TS U4647 ( .A(n3321), .B(n3320), .Y(n3323) );
NAND2X1TS U4648 ( .A(n1113), .B(n3325), .Y(n3327) );
CLKXOR2X2TS U4649 ( .A(n3327), .B(n3326), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
NAND2X2TS U4650 ( .A(n3348), .B(n3347), .Y(n3349) );
XNOR2X4TS U4651 ( .A(n3350), .B(n3349), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[10]) );
INVX2TS U4652 ( .A(n3351), .Y(n3353) );
XNOR2X4TS U4653 ( .A(n3356), .B(n3359), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[12]) );
OR2X2TS U4654 ( .A(n3364), .B(n3363), .Y(n3416) );
NAND2X2TS U4655 ( .A(n3364), .B(n3363), .Y(n3414) );
NAND2X1TS U4656 ( .A(n3416), .B(n3414), .Y(n3370) );
NOR2X2TS U4657 ( .A(n3369), .B(n3368), .Y(n3379) );
AOI21X2TS U4658 ( .A0(n3367), .A1(n3396), .B0(n3366), .Y(n3382) );
INVX2TS U4659 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n3421) );
INVX2TS U4660 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n3386) );
INVX2TS U4661 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(n3385) );
INVX2TS U4662 ( .A(FPMULT_Sgf_operation_Result[1]), .Y(n3390) );
INVX2TS U4663 ( .A(n3374), .Y(n3376) );
NAND2X1TS U4664 ( .A(n3376), .B(n3375), .Y(n3378) );
INVX2TS U4665 ( .A(n4609), .Y(n3399) );
INVX2TS U4666 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(n3398) );
INVX2TS U4667 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(n3419) );
OR2X2TS U4668 ( .A(n3407), .B(n3406), .Y(n3648) );
INVX2TS U4669 ( .A(n3379), .Y(n3381) );
NAND2X2TS U4670 ( .A(n3648), .B(n3701), .Y(n3410) );
XNOR2X1TS U4671 ( .A(n3391), .B(n3390), .Y(n3393) );
NOR2X1TS U4672 ( .A(n3394), .B(n3393), .Y(n3681) );
INVX2TS U4673 ( .A(n3392), .Y(n4014) );
INVX2TS U4674 ( .A(n4014), .Y(n3687) );
INVX2TS U4675 ( .A(n3684), .Y(n3395) );
NAND2X1TS U4676 ( .A(n3394), .B(n3393), .Y(n3682) );
OAI21X1TS U4677 ( .A0(n3681), .A1(n3395), .B0(n3682), .Y(n3692) );
XNOR2X1TS U4678 ( .A(n3397), .B(n3396), .Y(n3402) );
CMPR32X2TS U4679 ( .A(n3400), .B(n3399), .C(n3398), .CO(n3384), .S(n3401) );
NAND2X1TS U4680 ( .A(n3402), .B(n3401), .Y(n3690) );
INVX2TS U4681 ( .A(n3690), .Y(n3403) );
AOI21X2TS U4682 ( .A0(n3692), .A1(n1167), .B0(n3403), .Y(n3645) );
INVX2TS U4683 ( .A(n3700), .Y(n3646) );
INVX2TS U4684 ( .A(n3647), .Y(n3408) );
AOI21X4TS U4685 ( .A0(n3648), .A1(n3646), .B0(n3408), .Y(n3409) );
OAI21X4TS U4686 ( .A0(n3410), .A1(n3645), .B0(n3409), .Y(n3659) );
INVX2TS U4687 ( .A(n3429), .Y(n3413) );
INVX2TS U4688 ( .A(n3414), .Y(n3415) );
INVX2TS U4689 ( .A(FPMULT_Sgf_operation_Result[5]), .Y(n3437) );
INVX2TS U4690 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n3436) );
ADDFHX4TS U4691 ( .A(n3421), .B(n3420), .CI(n3419), .CO(n3435), .S(n3406) );
OR2X4TS U4692 ( .A(n3423), .B(n3422), .Y(n3658) );
NAND2X2TS U4693 ( .A(n3423), .B(n3422), .Y(n3657) );
AOI21X4TS U4694 ( .A0(n3659), .A1(n3658), .B0(n3424), .Y(n3672) );
NAND2X2TS U4695 ( .A(n3426), .B(n3425), .Y(n3462) );
INVX2TS U4696 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .Y(n3441) );
OAI21X4TS U4697 ( .A0(n3672), .A1(n3668), .B0(n3669), .Y(n3666) );
ADDFHX2TS U4698 ( .A(n3442), .B(n3441), .CI(n3440), .CO(n3470), .S(n3438) );
XNOR2X1TS U4699 ( .A(n3446), .B(n3445), .Y(n3459) );
NAND2X2TS U4700 ( .A(n3448), .B(n3447), .Y(n3450) );
NOR2X4TS U4701 ( .A(n3452), .B(n3451), .Y(n3463) );
INVX2TS U4702 ( .A(n3463), .Y(n3453) );
NAND2X2TS U4703 ( .A(n3452), .B(n3451), .Y(n3461) );
OR2X4TS U4704 ( .A(n3456), .B(n3455), .Y(n3665) );
ADDHX1TS U4705 ( .A(n3459), .B(n3458), .CO(n3491), .S(n3469) );
ADDFHX2TS U4706 ( .A(n3471), .B(n3470), .CI(n3469), .CO(n3489), .S(n3456) );
OAI21X4TS U4707 ( .A0(n3725), .A1(n3721), .B0(n3722), .Y(n3730) );
INVX2TS U4708 ( .A(n3477), .Y(n3479) );
NAND2X2TS U4709 ( .A(n3479), .B(n3478), .Y(n3481) );
INVX2TS U4710 ( .A(n3518), .Y(n3482) );
NOR2X4TS U4711 ( .A(n3485), .B(n3484), .Y(n3519) );
INVX2TS U4712 ( .A(n3519), .Y(n3486) );
XOR2X4TS U4713 ( .A(n3488), .B(n3487), .Y(n3526) );
XOR2X4TS U4714 ( .A(n3498), .B(n3497), .Y(n4511) );
INVX4TS U4715 ( .A(n3727), .Y(n3504) );
AOI21X4TS U4716 ( .A0(n3730), .A1(n3728), .B0(n3504), .Y(n3813) );
XNOR2X2TS U4717 ( .A(n3508), .B(n3507), .Y(n3555) );
NAND2X2TS U4718 ( .A(n3513), .B(n3512), .Y(n3514) );
NOR2X4TS U4719 ( .A(n3516), .B(n3519), .Y(n3567) );
OAI21X4TS U4720 ( .A0(n3519), .A1(n3518), .B0(n3517), .Y(n3573) );
AOI21X2TS U4721 ( .A0(n3542), .A1(n3567), .B0(n3573), .Y(n3524) );
NOR2X4TS U4722 ( .A(n3521), .B(n3520), .Y(n3566) );
INVX2TS U4723 ( .A(n3566), .Y(n3522) );
NAND2X2TS U4724 ( .A(n3521), .B(n3520), .Y(n3569) );
NAND2X4TS U4725 ( .A(n3529), .B(n3528), .Y(n3815) );
OAI21X4TS U4726 ( .A0(n3813), .A1(n3814), .B0(n3815), .Y(n3812) );
ADDFHX2TS U4727 ( .A(n3532), .B(n3531), .CI(n3530), .CO(n3585), .S(n3553) );
NAND2X2TS U4728 ( .A(n3535), .B(n3534), .Y(n3537) );
XOR2X4TS U4729 ( .A(n3537), .B(n3536), .Y(n3584) );
INVX2TS U4730 ( .A(n3567), .Y(n3538) );
INVX2TS U4731 ( .A(n3573), .Y(n3539) );
INVX2TS U4732 ( .A(n3570), .Y(n3545) );
NAND2X1TS U4733 ( .A(n3544), .B(n3543), .Y(n3568) );
NAND2X2TS U4734 ( .A(n3550), .B(n3549), .Y(n3551) );
ADDFHX4TS U4735 ( .A(n3555), .B(n3554), .CI(n3553), .CO(n3556), .S(n3529) );
OR2X8TS U4736 ( .A(n3557), .B(n3556), .Y(n3810) );
NAND2X4TS U4737 ( .A(n3557), .B(n3556), .Y(n3809) );
XNOR2X4TS U4738 ( .A(n3559), .B(n3562), .Y(n3595) );
NOR2X2TS U4739 ( .A(n3566), .B(n3570), .Y(n3572) );
OAI21X1TS U4740 ( .A0(n3570), .A1(n3569), .B0(n3568), .Y(n3571) );
OAI21X2TS U4741 ( .A0(n3576), .A1(n3575), .B0(n3574), .Y(n3598) );
NAND2X1TS U4742 ( .A(n3578), .B(n3577), .Y(n3596) );
NAND2X1TS U4743 ( .A(n1177), .B(n3596), .Y(n3579) );
XNOR2X2TS U4744 ( .A(n3598), .B(n3579), .Y(n3606) );
INVX2TS U4745 ( .A(n3588), .Y(n3590) );
NAND2X2TS U4746 ( .A(n3590), .B(n3589), .Y(n3592) );
XOR2X4TS U4747 ( .A(n3592), .B(n3591), .Y(n3948) );
ADDFHX4TS U4748 ( .A(n3595), .B(n3594), .CI(n3593), .CO(n3947), .S(n3587) );
INVX2TS U4749 ( .A(n3596), .Y(n3597) );
XOR2X1TS U4750 ( .A(n3600), .B(n3599), .Y(n3939) );
ADDFHX2TS U4751 ( .A(n3606), .B(n3605), .CI(n3604), .CO(n3937), .S(n3593) );
NOR2X2TS U4752 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n5738), .Y(n4451) );
OR2X2TS U4753 ( .A(FPMULT_FSM_selector_B[1]), .B(n5729), .Y(n4785) );
AND4X1TS U4754 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[0]), .D(
FPMULT_Exp_module_Data_S[1]), .Y(n3612) );
AND4X1TS U4755 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n3612), .Y(n3613) );
NOR2BX4TS U4756 ( .AN(n4139), .B(n4138), .Y(n3638) );
INVX2TS U4757 ( .A(n3638), .Y(n3614) );
INVX2TS U4758 ( .A(n3623), .Y(n3615) );
NAND2X2TS U4759 ( .A(n4164), .B(n3616), .Y(n3617) );
NAND2X4TS U4760 ( .A(n4168), .B(n5734), .Y(n4144) );
OA21XLTS U4761 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(n4141), .Y(n3620) );
INVX2TS U4762 ( .A(n3621), .Y(n4726) );
NOR2X1TS U4763 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n4726), .Y(n3634) );
OAI31X1TS U4764 ( .A0(n5802), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n3624), .Y(n3626) );
NAND2X1TS U4765 ( .A(n3626), .B(n3625), .Y(n3627) );
NAND2BX1TS U4766 ( .AN(n4144), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n4162)
);
AOI21X1TS U4767 ( .A0(n5773), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n3631) );
INVX2TS U4768 ( .A(n4141), .Y(n3630) );
AOI211X2TS U4769 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n3634), .B0(n3633), .C0(n3632), .Y(n4143) );
NOR4X1TS U4770 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .D(
n4726), .Y(n3635) );
AOI22X1TS U4771 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n3635), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n4168), .Y(n3641) );
AOI21X1TS U4772 ( .A0(n5788), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n3636) );
AOI21X1TS U4773 ( .A0(n3637), .A1(n5796), .B0(n4721), .Y(n3640) );
NAND4X2TS U4774 ( .A(n4143), .B(n3641), .C(n3640), .D(n3639), .Y(
FPADDSUB_LZD_raw_out_EWR[0]) );
BUFX3TS U4775 ( .A(n5789), .Y(n5247) );
OAI22X2TS U4776 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(FPADDSUB_LZD_raw_out_EWR[0]),
.B1(n4506), .Y(n4704) );
INVX2TS U4777 ( .A(n4704), .Y(n4132) );
ADDFHX4TS U4778 ( .A(n3644), .B(n3643), .CI(n3642), .CO(
DP_OP_499J311_125_1651_n194), .S(n3925) );
INVX2TS U4779 ( .A(n3645), .Y(n3702) );
AOI21X1TS U4780 ( .A0(n3702), .A1(n3701), .B0(n3646), .Y(n3650) );
NAND2X1TS U4781 ( .A(n3648), .B(n3647), .Y(n3649) );
CLKXOR2X2TS U4782 ( .A(n3650), .B(n3649), .Y(n3713) );
INVX2TS U4783 ( .A(n3652), .Y(n3654) );
NOR2X4TS U4784 ( .A(n3713), .B(n3747), .Y(n4172) );
XNOR2X2TS U4785 ( .A(n3660), .B(n3659), .Y(n3714) );
INVX2TS U4786 ( .A(n3675), .Y(n3661) );
XOR2X4TS U4787 ( .A(n3674), .B(n3662), .Y(n3801) );
XNOR2X4TS U4788 ( .A(n3667), .B(n3666), .Y(n3716) );
INVX2TS U4789 ( .A(n3668), .Y(n3670) );
XNOR2X4TS U4790 ( .A(n3680), .B(n3679), .Y(n3787) );
INVX2TS U4791 ( .A(n3681), .Y(n3683) );
NAND2X1TS U4792 ( .A(n3683), .B(n3682), .Y(n3685) );
XNOR2X1TS U4793 ( .A(n3685), .B(n3684), .Y(n3689) );
CMPR32X2TS U4794 ( .A(n3687), .B(n2227), .C(n3686), .CO(n3684), .S(n4606) );
OAI21X4TS U4795 ( .A0(n4186), .A1(n4607), .B0(n4187), .Y(n4180) );
NAND2X1TS U4796 ( .A(n1167), .B(n3690), .Y(n3691) );
XNOR2X1TS U4797 ( .A(n3692), .B(n3691), .Y(n3709) );
AOI21X4TS U4798 ( .A0(n3695), .A1(n3694), .B0(n3693), .Y(n3699) );
XOR2X4TS U4799 ( .A(n3699), .B(n3698), .Y(n3764) );
NAND2X1TS U4800 ( .A(n3701), .B(n3700), .Y(n3703) );
XNOR2X2TS U4801 ( .A(n3703), .B(n3702), .Y(n3710) );
XOR2X4TS U4802 ( .A(n3708), .B(n3707), .Y(n3763) );
OAI21X4TS U4803 ( .A0(n4173), .A1(n4177), .B0(n4174), .Y(n4016) );
OAI21X4TS U4804 ( .A0(n4020), .A1(n4034), .B0(n4021), .Y(n3717) );
AOI21X4TS U4805 ( .A0(n4016), .A1(n3718), .B0(n3717), .Y(n3719) );
INVX2TS U4806 ( .A(n3721), .Y(n3723) );
NAND2X2TS U4807 ( .A(n3723), .B(n3722), .Y(n3724) );
NAND2X2TS U4808 ( .A(n3728), .B(n3727), .Y(n3729) );
XNOR2X4TS U4809 ( .A(n3730), .B(n3729), .Y(n3733) );
INVX2TS U4810 ( .A(n4013), .Y(n3735) );
NAND2X4TS U4811 ( .A(n3732), .B(n3731), .Y(n4027) );
OAI21X4TS U4812 ( .A0(n3999), .A1(n4027), .B0(n4000), .Y(n3928) );
INVX2TS U4813 ( .A(n3928), .Y(n3734) );
INVX2TS U4814 ( .A(n3766), .Y(n3737) );
INVX2TS U4815 ( .A(n3767), .Y(n3736) );
AO21X4TS U4816 ( .A0(n3765), .A1(n3737), .B0(n3736), .Y(n3742) );
NAND2X4TS U4817 ( .A(n3740), .B(n3739), .Y(n3741) );
INVX4TS U4818 ( .A(n3754), .Y(add_x_69_n105) );
INVX2TS U4819 ( .A(n3743), .Y(n3745) );
NAND2X1TS U4820 ( .A(n3745), .B(n3744), .Y(n3746) );
XOR2X1TS U4821 ( .A(n3746), .B(n3752), .Y(n3804) );
XNOR2X4TS U4822 ( .A(n3888), .B(n3748), .Y(n3994) );
XNOR2X4TS U4823 ( .A(n3897), .B(n3750), .Y(n3904) );
OAI2BB1X4TS U4824 ( .A0N(n927), .A1N(n3940), .B0(n3942), .Y(n3759) );
XOR2X4TS U4825 ( .A(n3759), .B(n3758), .Y(n3772) );
INVX2TS U4826 ( .A(n3765), .Y(n3769) );
NAND2X2TS U4827 ( .A(n3737), .B(n3767), .Y(n3768) );
XOR2X4TS U4828 ( .A(n3754), .B(n3770), .Y(n3771) );
XNOR2X4TS U4829 ( .A(n3772), .B(n3771), .Y(n3950) );
OAI2BB1X4TS U4830 ( .A0N(n3794), .A1N(n3791), .B0(n3793), .Y(n3776) );
NOR2X4TS U4831 ( .A(n3773), .B(n3792), .Y(n3774) );
INVX2TS U4832 ( .A(n3777), .Y(n3779) );
XOR2X4TS U4833 ( .A(n3781), .B(n3780), .Y(n3837) );
INVX2TS U4834 ( .A(n3782), .Y(n3784) );
NAND2X1TS U4835 ( .A(n3784), .B(n3783), .Y(n3785) );
XOR2X1TS U4836 ( .A(n3786), .B(n3785), .Y(n3806) );
ADDFHX4TS U4837 ( .A(n3789), .B(add_x_69_n69), .CI(n3788), .CO(n3833), .S(
n3835) );
XOR2X4TS U4838 ( .A(n3796), .B(n3795), .Y(n3907) );
NAND2X1TS U4839 ( .A(n3798), .B(n3797), .Y(n3800) );
XNOR2X1TS U4840 ( .A(n3800), .B(n3799), .Y(n3968) );
NOR2X8TS U4841 ( .A(n3808), .B(n3807), .Y(DP_OP_499J311_125_1651_n69) );
NAND2X4TS U4842 ( .A(n3808), .B(n3807), .Y(n3910) );
INVX2TS U4843 ( .A(n3814), .Y(n3816) );
NAND2X2TS U4844 ( .A(n3822), .B(n3818), .Y(n3826) );
ADDFHX4TS U4845 ( .A(n3834), .B(n3833), .CI(n3832), .CO(n3924), .S(
DP_OP_499J311_125_1651_n199) );
ADDFHX4TS U4846 ( .A(n3837), .B(n3836), .CI(n3835), .CO(
DP_OP_499J311_125_1651_n202), .S(n3808) );
OAI21X4TS U4847 ( .A0(n3841), .A1(n3840), .B0(n3839), .Y(n3914) );
AOI21X4TS U4848 ( .A0(n3918), .A1(n3913), .B0(n3914), .Y(n3861) );
CMPR32X2TS U4849 ( .A(n3844), .B(n3843), .C(n3842), .CO(n3859), .S(n3289) );
INVX2TS U4850 ( .A(n3845), .Y(n3846) );
XNOR2X1TS U4851 ( .A(n3848), .B(n3847), .Y(n3857) );
CMPR32X2TS U4852 ( .A(n3851), .B(n3850), .C(n3849), .CO(n3856), .S(n3853) );
CMPR32X2TS U4853 ( .A(n3854), .B(n3853), .C(n3852), .CO(n3855), .S(n3843) );
ADDFHX4TS U4854 ( .A(n3863), .B(n3862), .CI(n917), .CO(n3935), .S(n3643) );
OAI21X1TS U4855 ( .A0(n3866), .A1(n3865), .B0(n3864), .Y(n3871) );
INVX2TS U4856 ( .A(n3867), .Y(n3869) );
INVX2TS U4857 ( .A(n3874), .Y(n3875) );
XOR2X4TS U4858 ( .A(n3876), .B(n3875), .Y(n4002) );
INVX2TS U4859 ( .A(n3885), .Y(n3886) );
AOI21X4TS U4860 ( .A0(n3888), .A1(n3887), .B0(n3886), .Y(n3893) );
INVX2TS U4861 ( .A(n1086), .Y(n3891) );
INVX2TS U4862 ( .A(n3894), .Y(n3895) );
INVX2TS U4863 ( .A(n3898), .Y(n3900) );
XOR2X4TS U4864 ( .A(n3902), .B(n3901), .Y(n3970) );
ADDFHX4TS U4865 ( .A(n3907), .B(n3906), .CI(n3905), .CO(n3807), .S(n3909) );
NOR2X8TS U4866 ( .A(n3908), .B(n3909), .Y(DP_OP_499J311_125_1651_n74) );
OAI21X4TS U4867 ( .A0(n3974), .A1(DP_OP_499J311_125_1651_n69), .B0(n3910),
.Y(DP_OP_499J311_125_1651_n64) );
ADDHX2TS U4868 ( .A(n3912), .B(n3911), .CO(n3975), .S(
DP_OP_499J311_125_1651_n185) );
AOI21X4TS U4869 ( .A0(n3913), .A1(n3918), .B0(n3917), .Y(n3933) );
NAND2X4TS U4870 ( .A(DP_OP_499J311_125_1651_n186), .B(
DP_OP_499J311_125_1651_n185), .Y(DP_OP_499J311_125_1651_n38) );
NAND2X2TS U4871 ( .A(n4013), .B(n4011), .Y(n3930) );
INVX2TS U4872 ( .A(n4010), .Y(n3927) );
ADDFHX4TS U4873 ( .A(n3933), .B(n3932), .CI(n3931), .CO(
DP_OP_499J311_125_1651_n186), .S(DP_OP_499J311_125_1651_n187) );
INVX2TS U4874 ( .A(n3940), .Y(n3944) );
NAND2X4TS U4875 ( .A(n927), .B(n3942), .Y(n3943) );
ADDFHX2TS U4876 ( .A(n3946), .B(n3945), .CI(n924), .CO(n3951), .S(n3953) );
ADDFHX4TS U4877 ( .A(n3949), .B(n3948), .CI(n3947), .CO(n3958), .S(n3608) );
ADDFHX4TS U4878 ( .A(n3952), .B(n3951), .CI(n3950), .CO(n3964), .S(n3961) );
OAI21X4TS U4879 ( .A0(n3963), .A1(n3979), .B0(n3962), .Y(
DP_OP_499J311_125_1651_n86) );
ADDFHX4TS U4880 ( .A(n3968), .B(n3967), .CI(n3966), .CO(n3906), .S(n3972) );
NAND2X4TS U4881 ( .A(n3973), .B(n3972), .Y(DP_OP_499J311_125_1651_n81) );
ADDFHX4TS U4882 ( .A(n3971), .B(n3970), .CI(n3969), .CO(n3908), .S(n3973) );
NOR2X8TS U4883 ( .A(n3973), .B(n3972), .Y(n3976) );
OAI21X4TS U4884 ( .A0(n3976), .A1(DP_OP_499J311_125_1651_n84), .B0(
DP_OP_499J311_125_1651_n81), .Y(DP_OP_499J311_125_1651_n79) );
INVX2TS U4885 ( .A(n3974), .Y(DP_OP_499J311_125_1651_n73) );
INVX2TS U4886 ( .A(n3976), .Y(DP_OP_499J311_125_1651_n166) );
CLKBUFX2TS U4887 ( .A(n824), .Y(n6009) );
CLKBUFX2TS U4888 ( .A(n6004), .Y(n5964) );
CLKBUFX3TS U4889 ( .A(n5966), .Y(n5505) );
NOR2X2TS U4890 ( .A(n3976), .B(DP_OP_499J311_125_1651_n83), .Y(
DP_OP_499J311_125_1651_n78) );
NAND2X2TS U4891 ( .A(n3982), .B(n3978), .Y(n3980) );
NAND2X1TS U4892 ( .A(Data_1[6]), .B(Data_1[0]), .Y(n5516) );
NAND2X1TS U4893 ( .A(Data_1[7]), .B(Data_1[1]), .Y(n5532) );
NOR2X1TS U4894 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n4735), .Y(n4131) );
NAND2X2TS U4895 ( .A(n4131), .B(n3986), .Y(n5961) );
INVX2TS U4896 ( .A(n5961), .Y(n3993) );
INVX2TS U4897 ( .A(n3993), .Y(n5953) );
CLKBUFX2TS U4898 ( .A(n5953), .Y(n5540) );
INVX2TS U4899 ( .A(Data_2[11]), .Y(n5523) );
INVX2TS U4900 ( .A(Data_1[6]), .Y(n5536) );
INVX2TS U4901 ( .A(Data_2[5]), .Y(n5513) );
INVX2TS U4902 ( .A(Data_1[0]), .Y(n5512) );
INVX2TS U4903 ( .A(Data_2[10]), .Y(n5518) );
INVX2TS U4904 ( .A(Data_1[8]), .Y(n5531) );
INVX2TS U4905 ( .A(Data_2[8]), .Y(n5515) );
INVX2TS U4906 ( .A(Data_1[10]), .Y(n5534) );
INVX2TS U4907 ( .A(Data_2[1]), .Y(n5529) );
INVX2TS U4908 ( .A(Data_1[3]), .Y(n5527) );
INVX2TS U4909 ( .A(Data_1[11]), .Y(n5525) );
INVX2TS U4910 ( .A(Data_2[6]), .Y(n5520) );
INVX2TS U4911 ( .A(Data_2[4]), .Y(n5522) );
INVX2TS U4912 ( .A(Data_1[9]), .Y(n5537) );
INVX2TS U4913 ( .A(Data_1[5]), .Y(n5519) );
INVX2TS U4914 ( .A(Data_1[4]), .Y(n5517) );
INVX2TS U4915 ( .A(Data_2[9]), .Y(n5526) );
INVX2TS U4916 ( .A(Data_2[7]), .Y(n5514) );
BUFX3TS U4917 ( .A(n5953), .Y(n5541) );
BUFX3TS U4918 ( .A(n5952), .Y(n5838) );
NAND2X1TS U4919 ( .A(Data_2[20]), .B(Data_2[14]), .Y(n5581) );
NOR2X1TS U4920 ( .A(Data_2[19]), .B(Data_2[13]), .Y(n3991) );
INVX2TS U4921 ( .A(n3991), .Y(n3987) );
NAND2X1TS U4922 ( .A(Data_2[19]), .B(Data_2[13]), .Y(n3990) );
NAND2X1TS U4923 ( .A(n3987), .B(n3990), .Y(n3988) );
NAND2X1TS U4924 ( .A(Data_2[18]), .B(Data_2[12]), .Y(n3992) );
XOR2X1TS U4925 ( .A(n3988), .B(n3992), .Y(n5572) );
INVX2TS U4926 ( .A(Data_1[17]), .Y(n5562) );
INVX2TS U4927 ( .A(Data_2[12]), .Y(n5564) );
NAND2X1TS U4928 ( .A(n3989), .B(n3992), .Y(DP_OP_497J311_123_1725_n336) );
INVX2TS U4929 ( .A(Data_1[14]), .Y(n5553) );
NOR2BX1TS U4930 ( .AN(Data_2[17]), .B(n5553), .Y(n5579) );
INVX2TS U4931 ( .A(Data_2[17]), .Y(n5550) );
INVX2TS U4932 ( .A(DP_OP_497J311_123_1725_n336), .Y(n5573) );
INVX2TS U4933 ( .A(Data_2[21]), .Y(n5560) );
INVX2TS U4934 ( .A(Data_2[15]), .Y(n5557) );
INVX2TS U4935 ( .A(Data_1[12]), .Y(n5546) );
INVX2TS U4936 ( .A(Data_1[15]), .Y(n5555) );
INVX2TS U4937 ( .A(Data_2[20]), .Y(n5548) );
INVX2TS U4938 ( .A(Data_2[16]), .Y(n5580) );
INVX2TS U4939 ( .A(Data_1[21]), .Y(n5547) );
INVX2TS U4940 ( .A(Data_1[19]), .Y(n5559) );
INVX2TS U4941 ( .A(Data_1[20]), .Y(n5577) );
INVX2TS U4942 ( .A(n3993), .Y(n5954) );
BUFX3TS U4943 ( .A(n5954), .Y(n5583) );
ADDHXLTS U4944 ( .A(Data_1[18]), .B(Data_2[18]), .CO(n5551), .S(n5552) );
BUFX3TS U4945 ( .A(n5952), .Y(n5836) );
BUFX3TS U4946 ( .A(n5836), .Y(n5586) );
CLKBUFX2TS U4947 ( .A(n5953), .Y(n5840) );
CLKBUFX3TS U4948 ( .A(n5840), .Y(n5584) );
CLKBUFX3TS U4949 ( .A(n5836), .Y(n5585) );
CLKBUFX2TS U4950 ( .A(n5954), .Y(n5582) );
NAND2X1TS U4951 ( .A(Data_2[14]), .B(Data_2[2]), .Y(n5595) );
NAND2X1TS U4952 ( .A(Data_2[13]), .B(Data_2[1]), .Y(n5601) );
NAND2X1TS U4953 ( .A(Data_2[12]), .B(Data_2[0]), .Y(n5603) );
NAND2X1TS U4954 ( .A(Data_1[13]), .B(Data_1[1]), .Y(n5605) );
NAND2X1TS U4955 ( .A(Data_2[15]), .B(Data_2[3]), .Y(n5607) );
NOR2BX1TS U4956 ( .AN(Data_2[18]), .B(n5520), .Y(n5611) );
NAND2X1TS U4957 ( .A(Data_2[5]), .B(Data_2[17]), .Y(n5613) );
NAND2X1TS U4958 ( .A(Data_2[16]), .B(Data_2[4]), .Y(n5614) );
NOR2X1TS U4959 ( .A(Data_2[14]), .B(Data_2[2]), .Y(n5604) );
NOR2X1TS U4960 ( .A(Data_2[15]), .B(Data_2[3]), .Y(n5602) );
INVX2TS U4961 ( .A(Data_1[2]), .Y(n5597) );
INVX2TS U4962 ( .A(n4003), .Y(add_x_69_n47) );
INVX2TS U4963 ( .A(n3999), .Y(n4001) );
INVX2TS U4964 ( .A(n4028), .Y(n4004) );
BUFX3TS U4965 ( .A(n5967), .Y(n5700) );
CLKBUFX3TS U4966 ( .A(n5967), .Y(n5697) );
CLKBUFX3TS U4967 ( .A(n5966), .Y(n5696) );
CLKBUFX3TS U4968 ( .A(n5967), .Y(n5699) );
CLKBUFX3TS U4969 ( .A(n5967), .Y(n5695) );
CLKBUFX2TS U4970 ( .A(n5967), .Y(n5698) );
AOI21X4TS U4971 ( .A0(n957), .A1(n4017), .B0(n4016), .Y(add_x_69_n282) );
OAI21X4TS U4972 ( .A0(add_x_69_n282), .A1(n4033), .B0(n4034), .Y(n4023) );
INVX2TS U4973 ( .A(n4020), .Y(n4022) );
NAND2X1TS U4974 ( .A(add_x_69_n95), .B(n3995), .Y(n4024) );
ADDHXLTS U4975 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4036), .CO(n3884),
.S(FPMULT_Adder_M_result_A_adder[21]) );
ADDHXLTS U4976 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n4037), .CO(n4036),
.S(FPMULT_Adder_M_result_A_adder[20]) );
AOI2BB2XLTS U4977 ( .B0(add_x_246_A_1_), .B1(n1189), .A0N(n1189), .A1N(
add_x_246_A_1_), .Y(FPMULT_Adder_M_result_A_adder[1]) );
INVX2TS U4978 ( .A(n4040), .Y(n4469) );
AOI32X1TS U4979 ( .A0(n5718), .A1(n5738), .A2(n4469), .B0(n937), .B1(n4735),
.Y(n4042) );
NOR2X1TS U4980 ( .A(n4042), .B(n5731), .Y(n4039) );
OAI21X2TS U4981 ( .A0(n4735), .A1(n4040), .B0(n5718), .Y(n5187) );
AOI22X1TS U4982 ( .A0(n1020), .A1(FPMULT_Add_result[4]), .B0(n1023), .B1(
FPMULT_Add_result[5]), .Y(n4067) );
NOR2X2TS U4983 ( .A(n5694), .B(n5681), .Y(n4071) );
NOR2BX1TS U4984 ( .AN(n5690), .B(n4071), .Y(n4046) );
NAND2X1TS U4985 ( .A(n4046), .B(n5665), .Y(n4048) );
NAND2X1TS U4986 ( .A(n5694), .B(n5683), .Y(n4070) );
OAI2BB1X1TS U4987 ( .A0N(n4058), .A1N(n4044), .B0(n4070), .Y(n4045) );
AOI21X1TS U4988 ( .A0(n5692), .A1(n4046), .B0(n4045), .Y(n4047) );
NAND2X1TS U4989 ( .A(n4049), .B(n5678), .Y(n4054) );
NAND2X1TS U4990 ( .A(n4050), .B(n4054), .Y(n4051) );
XNOR2X1TS U4991 ( .A(n4052), .B(n4051), .Y(n4074) );
AOI21X1TS U4992 ( .A0(n4058), .A1(n4057), .B0(n4056), .Y(n4059) );
OAI21X1TS U4993 ( .A0(n5659), .A1(n4060), .B0(n4059), .Y(n4061) );
AOI21X1TS U4994 ( .A0(n5654), .A1(n4062), .B0(n4061), .Y(n4196) );
XOR2X1TS U4995 ( .A(n5510), .B(n5474), .Y(n4063) );
NOR2X2TS U4996 ( .A(n4063), .B(n5662), .Y(n4095) );
INVX2TS U4997 ( .A(n4095), .Y(n4064) );
NAND2X1TS U4998 ( .A(n4063), .B(n5661), .Y(n4097) );
NAND2X1TS U4999 ( .A(n4064), .B(n4097), .Y(n4065) );
XOR2X1TS U5000 ( .A(n4425), .B(n4065), .Y(n4106) );
AOI22X1TS U5001 ( .A0(n1044), .A1(n4074), .B0(n1026), .B1(n4106), .Y(n4066)
);
AOI22X1TS U5002 ( .A0(n1019), .A1(FPMULT_Add_result[3]), .B0(n1022), .B1(
FPMULT_Add_result[4]), .Y(n4076) );
NAND2X1TS U5003 ( .A(n5682), .B(n5690), .Y(n4069) );
AOI21X1TS U5004 ( .A0(n5670), .A1(n5690), .B0(n4058), .Y(n4068) );
XNOR2X1TS U5005 ( .A(n4073), .B(n4072), .Y(n4079) );
AOI22X1TS U5006 ( .A0(n1045), .A1(n4079), .B0(n1025), .B1(n4074), .Y(n4075)
);
NAND2X1TS U5007 ( .A(n4076), .B(n4075), .Y(add_x_246_A_3_) );
AOI22X1TS U5008 ( .A0(n1019), .A1(FPMULT_Add_result[2]), .B0(n1022), .B1(
FPMULT_Add_result[3]), .Y(n4081) );
AOI21X1TS U5009 ( .A0(n5692), .A1(n934), .B0(n5680), .Y(n4077) );
XNOR2X1TS U5010 ( .A(n4078), .B(n5666), .Y(n4083) );
AOI22X1TS U5011 ( .A0(n4043), .A1(n4083), .B0(n1025), .B1(n4079), .Y(n4080)
);
NAND2X1TS U5012 ( .A(n4081), .B(n4080), .Y(n6051) );
AOI22X1TS U5013 ( .A0(n1019), .A1(FPMULT_Add_result[1]), .B0(n1022), .B1(
FPMULT_Add_result[2]), .Y(n4085) );
NAND2X1TS U5014 ( .A(n934), .B(n5691), .Y(n4082) );
XNOR2X1TS U5015 ( .A(n5677), .B(n4082), .Y(n4086) );
AOI22X1TS U5016 ( .A0(n4043), .A1(n4086), .B0(n1025), .B1(n4083), .Y(n4084)
);
NAND2X1TS U5017 ( .A(n4085), .B(n4084), .Y(n6050) );
AOI22X1TS U5018 ( .A0(n1019), .A1(FPMULT_Add_result[0]), .B0(n1022), .B1(
FPMULT_Add_result[1]), .Y(n4089) );
XNOR2X1TS U5019 ( .A(n5673), .B(n5674), .Y(n4087) );
AOI22X1TS U5020 ( .A0(n4043), .A1(n4087), .B0(n1025), .B1(n4086), .Y(n4088)
);
NAND2X1TS U5021 ( .A(n4089), .B(n4088), .Y(n6049) );
OR3X1TS U5022 ( .A(n6051), .B(n6050), .C(n6049), .Y(n4124) );
XNOR2X1TS U5023 ( .A(n6052), .B(n4121), .Y(n5708) );
AOI22X1TS U5024 ( .A0(n1020), .A1(FPMULT_Add_result[6]), .B0(n1023), .B1(
FPMULT_Add_result[7]), .Y(n4104) );
NAND2X1TS U5025 ( .A(n5483), .B(n5484), .Y(n4090) );
XNOR2X1TS U5026 ( .A(n4091), .B(n4090), .Y(n4092) );
NOR2X2TS U5027 ( .A(n4092), .B(n5663), .Y(n4098) );
NAND2X1TS U5028 ( .A(n4092), .B(n5664), .Y(n4096) );
XNOR2X1TS U5029 ( .A(n4094), .B(n4093), .Y(n4105) );
NOR2X2TS U5030 ( .A(n4095), .B(n4098), .Y(n4215) );
INVX2TS U5031 ( .A(n4215), .Y(n4099) );
OAI21X1TS U5032 ( .A0(n4098), .A1(n4097), .B0(n4096), .Y(n4242) );
INVX2TS U5033 ( .A(n4242), .Y(n4110) );
INVX2TS U5034 ( .A(n4201), .Y(n4232) );
XNOR2X1TS U5035 ( .A(n4232), .B(n5471), .Y(n4100) );
NOR2X2TS U5036 ( .A(n4100), .B(n5693), .Y(n4214) );
INVX2TS U5037 ( .A(n4214), .Y(n4109) );
NAND2X1TS U5038 ( .A(n4100), .B(n5693), .Y(n4238) );
NAND2X1TS U5039 ( .A(n4109), .B(n4238), .Y(n4101) );
XNOR2X1TS U5040 ( .A(n4102), .B(n4101), .Y(n4118) );
AOI22X1TS U5041 ( .A0(n1044), .A1(n4105), .B0(n1026), .B1(n4118), .Y(n4103)
);
NAND2X1TS U5042 ( .A(n4104), .B(n4103), .Y(add_x_246_A_6_) );
AOI22X1TS U5043 ( .A0(n5189), .A1(FPMULT_Add_result[5]), .B0(n5188), .B1(
FPMULT_Add_result[6]), .Y(n4108) );
AOI22X1TS U5044 ( .A0(n1045), .A1(n4106), .B0(n4053), .B1(n4105), .Y(n4107)
);
AOI22X1TS U5045 ( .A0(n5189), .A1(FPMULT_Add_result[7]), .B0(n1023), .B1(
FPMULT_Add_result[8]), .Y(n4120) );
NAND2X1TS U5046 ( .A(n4215), .B(n4109), .Y(n4112) );
OA21XLTS U5047 ( .A0(n4110), .A1(n4214), .B0(n4238), .Y(n4111) );
AOI21X1TS U5048 ( .A0(n4232), .A1(n5472), .B0(n5473), .Y(n4113) );
XOR2X1TS U5049 ( .A(n4113), .B(n5470), .Y(n4114) );
NOR2X2TS U5050 ( .A(n4114), .B(n5652), .Y(n4239) );
INVX2TS U5051 ( .A(n4239), .Y(n4115) );
NAND2X1TS U5052 ( .A(n4114), .B(n5655), .Y(n4237) );
NAND2X1TS U5053 ( .A(n4115), .B(n4237), .Y(n4116) );
XNOR2X1TS U5054 ( .A(n4117), .B(n4116), .Y(n5191) );
AOI22X1TS U5055 ( .A0(n1045), .A1(n4118), .B0(n1026), .B1(n5191), .Y(n4119)
);
NAND2X1TS U5056 ( .A(n4120), .B(n4119), .Y(add_x_246_A_7_) );
ADDHXLTS U5057 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n4126), .CO(n3883),
.S(FPMULT_Adder_M_result_A_adder[18]) );
ADDHXLTS U5058 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n4127), .CO(n3882),
.S(FPMULT_Adder_M_result_A_adder[16]) );
ADDHXLTS U5059 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n4128), .CO(n3878),
.S(FPMULT_Adder_M_result_A_adder[14]) );
ADDHXLTS U5060 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n4129), .CO(n3879),
.S(FPMULT_Adder_M_result_A_adder[12]) );
ADDHXLTS U5061 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n4130), .CO(n3880),
.S(FPMULT_Adder_M_result_A_adder[10]) );
NAND2BX1TS U5062 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n4308),
.Y(n4366) );
INVX2TS U5063 ( .A(n4444), .Y(n4597) );
INVX2TS U5064 ( .A(n4131), .Y(n4464) );
NOR4X1TS U5065 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n4135) );
NOR4X1TS U5066 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n4134) );
NOR4X1TS U5067 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n4133) );
OAI22X1TS U5068 ( .A0(n4139), .A1(n4138), .B0(n4137), .B1(n4726), .Y(n4140)
);
AOI21X1TS U5069 ( .A0(n4141), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n4140),
.Y(n4142) );
OAI211X1TS U5070 ( .A0(n4144), .A1(n5790), .B0(n4143), .C0(n4142), .Y(
FPADDSUB_LZD_raw_out_EWR[2]) );
NOR2X1TS U5071 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n5058) );
NAND2X1TS U5072 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n5066) );
NAND2X1TS U5073 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n5059) );
OAI21X1TS U5074 ( .A0(n5058), .A1(n5066), .B0(n5059), .Y(n5036) );
NOR2X1TS U5075 ( .A(n5046), .B(n5037), .Y(n4146) );
NAND2X1TS U5076 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n5047) );
NAND2X1TS U5077 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n5038) );
OAI21X1TS U5078 ( .A0(n5037), .A1(n5047), .B0(n5038), .Y(n4145) );
AOI21X2TS U5079 ( .A0(n5036), .A1(n4146), .B0(n4145), .Y(n4795) );
NOR2X1TS U5080 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n5012) );
NOR2X2TS U5081 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n5014) );
NOR2X1TS U5082 ( .A(n5012), .B(n5014), .Y(n4797) );
NOR2X2TS U5083 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n4820) );
NOR2X2TS U5084 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n4798) );
NAND2X1TS U5085 ( .A(n4797), .B(n4148), .Y(n4150) );
NAND2X1TS U5086 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n5024) );
NAND2X1TS U5087 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n5015) );
OAI21X1TS U5088 ( .A0(n5014), .A1(n5024), .B0(n5015), .Y(n4796) );
NAND2X1TS U5089 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n4821) );
NAND2X1TS U5090 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n4799) );
AOI21X1TS U5091 ( .A0(n4796), .A1(n4148), .B0(n4147), .Y(n4149) );
OAI21X4TS U5092 ( .A0(n4795), .A1(n4150), .B0(n4149), .Y(n4834) );
NOR2X1TS U5093 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n4865) );
INVX2TS U5094 ( .A(n4865), .Y(n5002) );
NAND2X1TS U5095 ( .A(n5002), .B(n4867), .Y(n4836) );
NOR2X2TS U5096 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n4837) );
NOR2X1TS U5097 ( .A(n4836), .B(n4837), .Y(n4154) );
INVX2TS U5098 ( .A(n5001), .Y(n4152) );
NAND2X1TS U5099 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n4866) );
INVX2TS U5100 ( .A(n4866), .Y(n4151) );
AOI21X1TS U5101 ( .A0(n4867), .A1(n4152), .B0(n4151), .Y(n4835) );
NAND2X1TS U5102 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n4838) );
OAI21X1TS U5103 ( .A0(n4835), .A1(n4837), .B0(n4838), .Y(n4153) );
NOR2X1TS U5104 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n4850) );
NAND2X1TS U5105 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n4851) );
NAND2X1TS U5106 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n4993) );
INVX2TS U5107 ( .A(n4993), .Y(n4155) );
AOI21X4TS U5108 ( .A0(n4995), .A1(n4994), .B0(n4155), .Y(n4987) );
NOR2X1TS U5109 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n4984) );
NAND2X1TS U5110 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n4985) );
NAND2X1TS U5111 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n4976) );
INVX2TS U5112 ( .A(n4976), .Y(n4156) );
AOI21X4TS U5113 ( .A0(n4978), .A1(n4977), .B0(n4156), .Y(n4970) );
NOR2X1TS U5114 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]),
.Y(n4967) );
NAND2X1TS U5115 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n4968) );
NAND2X1TS U5116 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n4959) );
INVX2TS U5117 ( .A(n4959), .Y(n4157) );
NOR2X1TS U5118 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]),
.Y(n4911) );
NAND2X1TS U5119 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n4912) );
OAI21X4TS U5120 ( .A0(n4914), .A1(n4911), .B0(n4912), .Y(n4905) );
NAND2X1TS U5121 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n4903) );
INVX2TS U5122 ( .A(n4903), .Y(n4158) );
AOI21X4TS U5123 ( .A0(n4905), .A1(n4904), .B0(n4158), .Y(n4881) );
NOR2X1TS U5124 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]),
.Y(n4878) );
NAND2X1TS U5125 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n4879) );
OAI21X4TS U5126 ( .A0(n4881), .A1(n4878), .B0(n4879), .Y(n4922) );
NAND2X1TS U5127 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n4920) );
INVX2TS U5128 ( .A(n4920), .Y(n4159) );
NOR2X1TS U5129 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]),
.Y(n4931) );
NAND2X1TS U5130 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n4932) );
OAI21X4TS U5131 ( .A0(n4934), .A1(n4931), .B0(n4932), .Y(n4944) );
NAND2X1TS U5132 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n4942) );
INVX2TS U5133 ( .A(n4942), .Y(n4160) );
NAND2X1TS U5134 ( .A(n4952), .B(n5833), .Y(n4161) );
BUFX3TS U5135 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n4928) );
NOR2BX1TS U5136 ( .AN(n4161), .B(n4928), .Y(n6042) );
NOR3X1TS U5137 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(n4165), .C(n5773), .Y(
n4720) );
NAND2X1TS U5138 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n4168), .Y(n4169) );
INVX2TS U5139 ( .A(n4172), .Y(n4178) );
INVX2TS U5140 ( .A(n4173), .Y(n4175) );
NAND2X1TS U5141 ( .A(n4175), .B(n4174), .Y(n4176) );
NAND2X1TS U5142 ( .A(n4178), .B(n4177), .Y(n4179) );
XNOR2X1TS U5143 ( .A(n957), .B(n4179), .Y(n4192) );
INVX2TS U5144 ( .A(n4180), .Y(n4604) );
OAI21X1TS U5145 ( .A0(n4604), .A1(n4600), .B0(n4601), .Y(n4185) );
NAND2X1TS U5146 ( .A(n4183), .B(n4182), .Y(n4184) );
NAND2X1TS U5147 ( .A(n4188), .B(n4187), .Y(n4189) );
XOR2X1TS U5148 ( .A(n4189), .B(n4607), .Y(n4190) );
NOR2X2TS U5149 ( .A(n4707), .B(n5800), .Y(n5958) );
NAND2X1TS U5150 ( .A(n4195), .B(n1194), .Y(n4306) );
NOR2X1TS U5151 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[1]), .Y(n4465) );
NAND2X1TS U5152 ( .A(n5709), .B(FPSENCOS_cont_iter_out[3]), .Y(n4305) );
NAND2X1TS U5153 ( .A(n5384), .B(n5709), .Y(n4304) );
INVX2TS U5154 ( .A(n5428), .Y(n865) );
INVX2TS U5155 ( .A(n4305), .Y(n4450) );
NOR2X1TS U5156 ( .A(n4450), .B(n5432), .Y(n5429) );
OAI211X1TS U5157 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n5712), .B0(n5709),
.C0(n5732), .Y(n5431) );
ADDHX1TS U5158 ( .A(n5701), .B(n5702), .CO(n4040), .S(n5185) );
AOI22X1TS U5159 ( .A0(n1020), .A1(FPMULT_Add_result[22]), .B0(n1023), .B1(
n5185), .Y(n4265) );
BUFX3TS U5160 ( .A(n4196), .Y(n4459) );
NOR2X4TS U5161 ( .A(n5494), .B(n5495), .Y(n4229) );
NOR2X2TS U5162 ( .A(n5479), .B(n5480), .Y(n4228) );
INVX2TS U5163 ( .A(n4197), .Y(n4199) );
OAI21X1TS U5164 ( .A0(n5498), .A1(n5500), .B0(n5502), .Y(n4198) );
AOI2BB1X2TS U5165 ( .A0N(n4199), .A1N(n5509), .B0(n4198), .Y(n4200) );
NOR2X2TS U5166 ( .A(n5488), .B(n5489), .Y(n4218) );
NOR2X2TS U5167 ( .A(n5501), .B(n5487), .Y(n4221) );
NOR2X1TS U5168 ( .A(n4218), .B(n4221), .Y(n4207) );
INVX2TS U5169 ( .A(n4207), .Y(n4204) );
NAND2X1TS U5170 ( .A(n5501), .B(n5496), .Y(n4219) );
OAI21X1TS U5171 ( .A0(n4221), .A1(n5497), .B0(n4219), .Y(n4209) );
INVX2TS U5172 ( .A(n4209), .Y(n4203) );
NAND2X1TS U5173 ( .A(n4208), .B(n5499), .Y(n4205) );
CLKXOR2X2TS U5174 ( .A(n4206), .B(n4205), .Y(n4252) );
NAND2X1TS U5175 ( .A(n4207), .B(n4208), .Y(n4211) );
AOI21X1TS U5176 ( .A0(n4209), .A1(n4208), .B0(n5507), .Y(n4210) );
OA21X2TS U5177 ( .A0(n1190), .A1(n4211), .B0(n4210), .Y(n4213) );
NAND2X1TS U5178 ( .A(n5492), .B(n5493), .Y(n4212) );
CLKXOR2X2TS U5179 ( .A(n4213), .B(n4212), .Y(n4253) );
NOR2X2TS U5180 ( .A(n4253), .B(n5646), .Y(n4277) );
NAND2X2TS U5181 ( .A(n5689), .B(n4331), .Y(n4452) );
NOR2X1TS U5182 ( .A(n4452), .B(n5639), .Y(n4255) );
INVX2TS U5183 ( .A(n4218), .Y(n4216) );
XNOR2X1TS U5184 ( .A(n1190), .B(n4217), .Y(n4245) );
NOR2X2TS U5185 ( .A(n4245), .B(n5653), .Y(n4342) );
OR2X2TS U5186 ( .A(n4221), .B(n4220), .Y(n4222) );
NOR2X2TS U5187 ( .A(n4246), .B(n5648), .Y(n4350) );
NOR2X2TS U5188 ( .A(n4342), .B(n4350), .Y(n4248) );
AOI21X1TS U5189 ( .A0(n4232), .A1(n4228), .B0(n5478), .Y(n4227) );
INVX2TS U5190 ( .A(n4229), .Y(n4224) );
NOR2BX1TS U5191 ( .AN(n4224), .B(n5506), .Y(n4225) );
INVX2TS U5192 ( .A(n4225), .Y(n4226) );
XOR2X1TS U5193 ( .A(n4227), .B(n4226), .Y(n4243) );
NOR2X2TS U5194 ( .A(n4243), .B(n5645), .Y(n4403) );
NOR2BX1TS U5195 ( .AN(n4228), .B(n4229), .Y(n4231) );
AOI21X1TS U5196 ( .A0(n4232), .A1(n4231), .B0(n4230), .Y(n4235) );
NOR2BX1TS U5197 ( .AN(n5508), .B(n5503), .Y(n4233) );
INVX2TS U5198 ( .A(n4233), .Y(n4234) );
XOR2X1TS U5199 ( .A(n4235), .B(n4234), .Y(n4244) );
NOR2X2TS U5200 ( .A(n4244), .B(n5651), .Y(n4411) );
NOR2X2TS U5201 ( .A(n4403), .B(n4411), .Y(n4421) );
NAND2X2TS U5202 ( .A(n4248), .B(n4421), .Y(n4250) );
NAND2X1TS U5203 ( .A(n4255), .B(n1035), .Y(n4257) );
AOI21X1TS U5204 ( .A0(n4242), .A1(n4241), .B0(n4240), .Y(n4344) );
NAND2X1TS U5205 ( .A(n4243), .B(n5656), .Y(n4406) );
NAND2X1TS U5206 ( .A(n4244), .B(n5657), .Y(n4412) );
OAI21X1TS U5207 ( .A0(n4411), .A1(n4406), .B0(n4412), .Y(n4345) );
NAND2X1TS U5208 ( .A(n4245), .B(n5658), .Y(n4426) );
NAND2X1TS U5209 ( .A(n4246), .B(n5647), .Y(n4351) );
OAI21X1TS U5210 ( .A0(n4350), .A1(n4426), .B0(n4351), .Y(n4247) );
AOI21X1TS U5211 ( .A0(n4248), .A1(n4345), .B0(n4247), .Y(n4249) );
NAND2X2TS U5212 ( .A(n5689), .B(n4295), .Y(n4453) );
AOI21X1TS U5213 ( .A0(n1036), .A1(n4255), .B0(n4254), .Y(n4256) );
OAI21X1TS U5214 ( .A0(n4459), .A1(n4257), .B0(n4256), .Y(n4258) );
XOR2X1TS U5215 ( .A(n4258), .B(n5627), .Y(n4314) );
NOR2X1TS U5216 ( .A(n4452), .B(n5637), .Y(n4260) );
NAND2X1TS U5217 ( .A(n4260), .B(n4236), .Y(n4262) );
NOR2X1TS U5218 ( .A(n4453), .B(n5631), .Y(n4259) );
AOI21X1TS U5219 ( .A0(n4456), .A1(n4260), .B0(n4259), .Y(n4261) );
OAI21X1TS U5220 ( .A0(n4459), .A1(n4262), .B0(n4261), .Y(n4263) );
XOR2X1TS U5221 ( .A(n4263), .B(n5628), .Y(n5184) );
AOI22X1TS U5222 ( .A0(n1044), .A1(n4314), .B0(n1026), .B1(n5184), .Y(n4264)
);
NAND2X1TS U5223 ( .A(n4265), .B(n4264), .Y(n6067) );
AOI22X1TS U5224 ( .A0(n5189), .A1(FPMULT_Add_result[13]), .B0(n5188), .B1(
FPMULT_Add_result[14]), .Y(n4281) );
INVX2TS U5225 ( .A(n4236), .Y(n4267) );
INVX2TS U5226 ( .A(n4456), .Y(n4266) );
INVX2TS U5227 ( .A(n4268), .Y(n4273) );
NAND2X1TS U5228 ( .A(n4273), .B(n4271), .Y(n4269) );
XNOR2X1TS U5229 ( .A(n4270), .B(n4269), .Y(n4355) );
NAND2X1TS U5230 ( .A(n1035), .B(n4273), .Y(n4275) );
INVX2TS U5231 ( .A(n4271), .Y(n4272) );
AOI21X1TS U5232 ( .A0(n4456), .A1(n4273), .B0(n4272), .Y(n4274) );
OAI21X1TS U5233 ( .A0(n4425), .A1(n4275), .B0(n4274), .Y(n4279) );
XNOR2X1TS U5234 ( .A(n4279), .B(n4278), .Y(n4363) );
AOI22X1TS U5235 ( .A0(n1045), .A1(n4355), .B0(n4053), .B1(n4363), .Y(n4280)
);
NAND2X1TS U5236 ( .A(n4281), .B(n4280), .Y(n6058) );
AOI22X1TS U5237 ( .A0(n5189), .A1(FPMULT_Add_result[19]), .B0(n1023), .B1(
FPMULT_Add_result[20]), .Y(n4294) );
INVX2TS U5238 ( .A(n4452), .Y(n4284) );
NAND2X1TS U5239 ( .A(n4236), .B(n4284), .Y(n4282) );
AOI21X1TS U5240 ( .A0(n4456), .A1(n4284), .B0(n4283), .Y(n4285) );
NAND2X1TS U5241 ( .A(n4286), .B(n4285), .Y(n4287) );
XNOR2X1TS U5242 ( .A(n4287), .B(n933), .Y(n4301) );
NOR2X1TS U5243 ( .A(n4452), .B(n933), .Y(n4289) );
NAND2X1TS U5244 ( .A(n4289), .B(n4236), .Y(n4291) );
NOR2X1TS U5245 ( .A(n4453), .B(n5633), .Y(n4288) );
AOI21X1TS U5246 ( .A0(n4456), .A1(n4289), .B0(n4288), .Y(n4290) );
XNOR2X1TS U5247 ( .A(n4292), .B(n5620), .Y(n4359) );
AOI22X1TS U5248 ( .A0(n1044), .A1(n4301), .B0(n1026), .B1(n4359), .Y(n4293)
);
NAND2X1TS U5249 ( .A(n4294), .B(n4293), .Y(n6064) );
AOI22X1TS U5250 ( .A0(n5189), .A1(FPMULT_Add_result[18]), .B0(n5188), .B1(
FPMULT_Add_result[19]), .Y(n4303) );
INVX2TS U5251 ( .A(n4331), .Y(n4322) );
NOR2X1TS U5252 ( .A(n5641), .B(n4322), .Y(n4297) );
NAND2X1TS U5253 ( .A(n1035), .B(n4297), .Y(n4299) );
INVX2TS U5254 ( .A(n4295), .Y(n4330) );
AOI21X1TS U5255 ( .A0(n4456), .A1(n4297), .B0(n4296), .Y(n4298) );
OAI21X1TS U5256 ( .A0(n4459), .A1(n4299), .B0(n4298), .Y(n4300) );
XOR2X1TS U5257 ( .A(n4300), .B(n5625), .Y(n4338) );
AOI22X1TS U5258 ( .A0(n1045), .A1(n4338), .B0(n1026), .B1(n4301), .Y(n4302)
);
NAND2X1TS U5259 ( .A(n4303), .B(n4302), .Y(n6063) );
OAI31X4TS U5260 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n5712), .B0(n865), .Y(n5430) );
NOR2X1TS U5261 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n4306),
.Y(n4394) );
NAND4X1TS U5262 ( .A(n4308), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.C(n4307), .D(n5784), .Y(n5278) );
NAND2X1TS U5263 ( .A(n4513), .B(n5278), .Y(FPSENCOS_enab_d_ff_RB1) );
AOI22X1TS U5264 ( .A0(n5189), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Add_result[22]), .B1(n1023), .Y(n4316) );
NOR2X1TS U5265 ( .A(n4452), .B(n5640), .Y(n4310) );
NAND2X1TS U5266 ( .A(n4310), .B(n4236), .Y(n4312) );
NOR2X1TS U5267 ( .A(n4453), .B(n5632), .Y(n4309) );
AOI21X1TS U5268 ( .A0(n4456), .A1(n4310), .B0(n4309), .Y(n4311) );
XOR2X1TS U5269 ( .A(n4313), .B(n5626), .Y(n4358) );
AOI22X1TS U5270 ( .A0(n1045), .A1(n4358), .B0(n4314), .B1(n1026), .Y(n4315)
);
NAND2X1TS U5271 ( .A(n4316), .B(n4315), .Y(n6066) );
AOI22X1TS U5272 ( .A0(n1020), .A1(FPMULT_Add_result[16]), .B0(n1023), .B1(
FPMULT_Add_result[17]), .Y(n4329) );
NOR2X1TS U5273 ( .A(n4322), .B(n5643), .Y(n4318) );
NAND2X1TS U5274 ( .A(n1035), .B(n4318), .Y(n4320) );
AOI21X1TS U5275 ( .A0(n4456), .A1(n4318), .B0(n4317), .Y(n4319) );
OAI21X1TS U5276 ( .A0(n4459), .A1(n4320), .B0(n4319), .Y(n4321) );
XOR2X1TS U5277 ( .A(n4321), .B(n5623), .Y(n4335) );
NOR2X1TS U5278 ( .A(n4322), .B(n5642), .Y(n4324) );
NAND2X1TS U5279 ( .A(n1035), .B(n4324), .Y(n4326) );
AOI21X1TS U5280 ( .A0(n4456), .A1(n4324), .B0(n4323), .Y(n4325) );
OAI21X1TS U5281 ( .A0(n4459), .A1(n4326), .B0(n4325), .Y(n4327) );
XOR2X1TS U5282 ( .A(n4327), .B(n5624), .Y(n4339) );
AOI22X1TS U5283 ( .A0(n1044), .A1(n4335), .B0(n1026), .B1(n4339), .Y(n4328)
);
NAND2X1TS U5284 ( .A(n4329), .B(n4328), .Y(n6061) );
AOI22X1TS U5285 ( .A0(n1020), .A1(FPMULT_Add_result[15]), .B0(n5188), .B1(
FPMULT_Add_result[16]), .Y(n4337) );
NAND2X1TS U5286 ( .A(n1035), .B(n4331), .Y(n4333) );
AOI21X1TS U5287 ( .A0(n1036), .A1(n4331), .B0(n4295), .Y(n4332) );
OAI21X1TS U5288 ( .A0(n4459), .A1(n4333), .B0(n4332), .Y(n4334) );
XOR2X1TS U5289 ( .A(n4334), .B(n5622), .Y(n4362) );
AOI22X1TS U5290 ( .A0(n1045), .A1(n4362), .B0(n4053), .B1(n4335), .Y(n4336)
);
NAND2X1TS U5291 ( .A(n4337), .B(n4336), .Y(n6060) );
AOI22X1TS U5292 ( .A0(n1020), .A1(FPMULT_Add_result[17]), .B0(n5188), .B1(
FPMULT_Add_result[18]), .Y(n4341) );
AOI22X1TS U5293 ( .A0(n1044), .A1(n4339), .B0(n4053), .B1(n4338), .Y(n4340)
);
NAND2X1TS U5294 ( .A(n4341), .B(n4340), .Y(n6062) );
AOI22X1TS U5295 ( .A0(n5189), .A1(FPMULT_Add_result[12]), .B0(n1023), .B1(
FPMULT_Add_result[13]), .Y(n4357) );
INVX2TS U5296 ( .A(n4342), .Y(n4427) );
NOR2X1TS U5297 ( .A(n4343), .B(n4342), .Y(n4347) );
INVX2TS U5298 ( .A(n4402), .Y(n4418) );
NAND2X1TS U5299 ( .A(n4347), .B(n4418), .Y(n4349) );
INVX2TS U5300 ( .A(n4344), .Y(n4422) );
INVX2TS U5301 ( .A(n4345), .Y(n4419) );
AOI21X1TS U5302 ( .A0(n4422), .A1(n4347), .B0(n4346), .Y(n4348) );
NAND2X1TS U5303 ( .A(n4352), .B(n4351), .Y(n4353) );
XNOR2X1TS U5304 ( .A(n4354), .B(n4353), .Y(n4430) );
AOI22X1TS U5305 ( .A0(n1045), .A1(n4430), .B0(n4053), .B1(n4355), .Y(n4356)
);
NAND2X1TS U5306 ( .A(n4357), .B(n4356), .Y(n6057) );
AOI22X1TS U5307 ( .A0(n5189), .A1(FPMULT_Add_result[20]), .B0(n5188), .B1(
FPMULT_Add_result[21]), .Y(n4361) );
AOI22X1TS U5308 ( .A0(n1044), .A1(n4359), .B0(n1026), .B1(n4358), .Y(n4360)
);
NAND2X1TS U5309 ( .A(n4361), .B(n4360), .Y(n6065) );
AOI22X1TS U5310 ( .A0(n1020), .A1(FPMULT_Add_result[14]), .B0(n1023), .B1(
FPMULT_Add_result[15]), .Y(n4365) );
AOI22X1TS U5311 ( .A0(n1045), .A1(n4363), .B0(n4053), .B1(n4362), .Y(n4364)
);
NAND2X1TS U5312 ( .A(n4365), .B(n4364), .Y(n6059) );
NOR2X1TS U5313 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n4366),
.Y(n4562) );
NAND3BX1TS U5314 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n4562), .Y(n5274) );
BUFX3TS U5315 ( .A(n4367), .Y(n5427) );
NAND2X1TS U5316 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n4735), .Y(n4730) );
NOR3X2TS U5317 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n937), .C(n4730), .Y(
n5438) );
AOI22X1TS U5318 ( .A0(n5427), .A1(ready_add_subt), .B0(n5438), .B1(n5424),
.Y(n4368) );
OAI2BB1X1TS U5319 ( .A0N(n4369), .A1N(n5425), .B0(n4368), .Y(operation_ready) );
NAND2X1TS U5320 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n4372) );
NAND2X1TS U5321 ( .A(n5302), .B(FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n4371) );
NAND2X1TS U5322 ( .A(n5247), .B(FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n4370) );
NAND3X1TS U5323 ( .A(n4372), .B(n4371), .C(n4370), .Y(n6030) );
CLKBUFX2TS U5324 ( .A(n824), .Y(n6008) );
NAND2X1TS U5325 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n5783), .Y(n4468) );
OAI21XLTS U5326 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n5783), .B0(n4468),
.Y(FPADDSUB_Shift_amount_EXP_EW[0]) );
XNOR2X1TS U5327 ( .A(n5675), .B(n5676), .Y(n4374) );
NOR4BBX1TS U5328 ( .AN(n5955), .BN(n5881), .C(n4374), .D(FPMULT_P_Sgf[19]),
.Y(n4380) );
XNOR2X1TS U5329 ( .A(n5671), .B(n5672), .Y(n4375) );
NOR4X1TS U5330 ( .A(n4375), .B(FPMULT_P_Sgf[5]), .C(FPMULT_P_Sgf[3]), .D(
FPMULT_P_Sgf[0]), .Y(n4379) );
XOR2X1TS U5331 ( .A(n5688), .B(n5669), .Y(n4377) );
XOR2X1TS U5332 ( .A(n5686), .B(n5687), .Y(n4376) );
NOR4X1TS U5333 ( .A(n4377), .B(n4376), .C(FPMULT_P_Sgf[4]), .D(
FPMULT_P_Sgf[1]), .Y(n4378) );
AND4X1TS U5334 ( .A(n6035), .B(n4380), .C(n4379), .D(n4378), .Y(n4381) );
AOI22X1TS U5335 ( .A0(n6036), .A1(n4381), .B0(r_mode[0]), .B1(r_mode[1]),
.Y(n4382) );
OAI221X1TS U5336 ( .A0(n5826), .A1(r_mode[1]), .B0(n6037), .B1(r_mode[0]),
.C0(n4382), .Y(n4732) );
BUFX3TS U5337 ( .A(n4517), .Y(n4589) );
AOI22X1TS U5338 ( .A0(FPSENCOS_d_ff3_sh_x_out[2]), .A1(n4589), .B0(Data_2[2]), .B1(n5290), .Y(n4385) );
AOI22X1TS U5339 ( .A0(n5077), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n4570),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n4384) );
NAND2X1TS U5340 ( .A(n4385), .B(n4384), .Y(add_subt_data2[2]) );
AOI22X1TS U5341 ( .A0(FPSENCOS_d_ff3_sh_x_out[10]), .A1(n4589), .B0(
Data_2[10]), .B1(n5290), .Y(n4387) );
AOI22X1TS U5342 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n4396),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n4386) );
NAND2X1TS U5343 ( .A(n4387), .B(n4386), .Y(add_subt_data2[10]) );
AOI22X1TS U5344 ( .A0(FPSENCOS_d_ff3_sh_x_out[4]), .A1(n4589), .B0(Data_2[4]), .B1(n5290), .Y(n4389) );
AOI22X1TS U5345 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n4396),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n4388) );
NAND2X1TS U5346 ( .A(n4389), .B(n4388), .Y(add_subt_data2[4]) );
AOI22X1TS U5347 ( .A0(FPSENCOS_d_ff3_sh_x_out[8]), .A1(n4589), .B0(Data_2[8]), .B1(n4395), .Y(n4391) );
AOI22X1TS U5348 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n4396),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n4390) );
NAND2X1TS U5349 ( .A(n4391), .B(n4390), .Y(add_subt_data2[8]) );
AOI22X1TS U5350 ( .A0(FPSENCOS_d_ff3_sh_x_out[6]), .A1(n4589), .B0(Data_2[6]), .B1(n5290), .Y(n4393) );
AOI22X1TS U5351 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n5331),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n4392) );
NAND2X1TS U5352 ( .A(n4393), .B(n4392), .Y(add_subt_data2[6]) );
NAND3BX1TS U5353 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n4394),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n5281) );
INVX2TS U5354 ( .A(n5281), .Y(n4736) );
AOI22X1TS U5355 ( .A0(FPSENCOS_d_ff3_sh_x_out[12]), .A1(n4589), .B0(
Data_2[12]), .B1(n4395), .Y(n4398) );
AOI22X1TS U5356 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n5307),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n4397) );
NAND2X1TS U5357 ( .A(n4398), .B(n4397), .Y(add_subt_data2[12]) );
AOI22X1TS U5358 ( .A0(FPSENCOS_d_ff3_sh_x_out[1]), .A1(n5379), .B0(Data_2[1]), .B1(n5290), .Y(n4400) );
AOI22X1TS U5359 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n5307),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n4399) );
NAND2X1TS U5360 ( .A(n4400), .B(n4399), .Y(add_subt_data2[1]) );
AOI22X1TS U5361 ( .A0(n1020), .A1(FPMULT_Add_result[9]), .B0(n5188), .B1(
FPMULT_Add_result[10]), .Y(n4417) );
INVX2TS U5362 ( .A(n4422), .Y(n4401) );
INVX2TS U5363 ( .A(n4403), .Y(n4408) );
NAND2X1TS U5364 ( .A(n4408), .B(n4406), .Y(n4404) );
XNOR2X1TS U5365 ( .A(n4405), .B(n4404), .Y(n5190) );
NAND2X1TS U5366 ( .A(n4418), .B(n4408), .Y(n4410) );
INVX2TS U5367 ( .A(n4406), .Y(n4407) );
AOI21X1TS U5368 ( .A0(n4422), .A1(n4408), .B0(n4407), .Y(n4409) );
INVX2TS U5369 ( .A(n4411), .Y(n4413) );
NAND2X1TS U5370 ( .A(n4413), .B(n4412), .Y(n4414) );
XNOR2X1TS U5371 ( .A(n4415), .B(n4414), .Y(n4434) );
AOI22X1TS U5372 ( .A0(n1044), .A1(n5190), .B0(n4053), .B1(n4434), .Y(n4416)
);
NAND2X1TS U5373 ( .A(n4417), .B(n4416), .Y(n6054) );
AOI22X1TS U5374 ( .A0(n1020), .A1(FPMULT_Add_result[11]), .B0(n5188), .B1(
FPMULT_Add_result[12]), .Y(n4432) );
NAND2X1TS U5375 ( .A(n4418), .B(n4421), .Y(n4424) );
INVX2TS U5376 ( .A(n4419), .Y(n4420) );
AOI21X1TS U5377 ( .A0(n4422), .A1(n4421), .B0(n4420), .Y(n4423) );
NAND2X1TS U5378 ( .A(n4427), .B(n4426), .Y(n4428) );
XNOR2X1TS U5379 ( .A(n4429), .B(n4428), .Y(n4433) );
AOI22X1TS U5380 ( .A0(n1045), .A1(n4433), .B0(n1026), .B1(n4430), .Y(n4431)
);
NAND2X1TS U5381 ( .A(n4432), .B(n4431), .Y(n6056) );
AOI22X1TS U5382 ( .A0(n5189), .A1(FPMULT_Add_result[10]), .B0(n1023), .B1(
FPMULT_Add_result[11]), .Y(n4436) );
AOI22X1TS U5383 ( .A0(n1044), .A1(n4434), .B0(n4053), .B1(n4433), .Y(n4435)
);
NAND2X1TS U5384 ( .A(n4436), .B(n4435), .Y(n6055) );
AOI22X1TS U5385 ( .A0(FPSENCOS_d_ff3_sh_x_out[0]), .A1(n5375), .B0(Data_2[0]), .B1(n5338), .Y(n4438) );
AOI22X1TS U5386 ( .A0(n5372), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n4570),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n4437) );
NAND2X1TS U5387 ( .A(n4438), .B(n4437), .Y(add_subt_data2[0]) );
BUFX3TS U5388 ( .A(n6004), .Y(n5971) );
BUFX3TS U5389 ( .A(n1059), .Y(n5972) );
CLKBUFX3TS U5390 ( .A(n1029), .Y(n4440) );
BUFX3TS U5391 ( .A(n4441), .Y(n5915) );
BUFX3TS U5392 ( .A(n4443), .Y(n5937) );
BUFX3TS U5393 ( .A(n4439), .Y(n5938) );
BUFX3TS U5394 ( .A(n5913), .Y(n5936) );
BUFX3TS U5395 ( .A(n5917), .Y(n5919) );
BUFX3TS U5396 ( .A(n5920), .Y(n5939) );
BUFX3TS U5397 ( .A(n4443), .Y(n5940) );
BUFX3TS U5398 ( .A(n4440), .Y(n5929) );
BUFX3TS U5399 ( .A(n5920), .Y(n5928) );
BUFX3TS U5400 ( .A(n6004), .Y(n5970) );
CLKBUFX3TS U5401 ( .A(n1029), .Y(n4441) );
BUFX3TS U5402 ( .A(n5918), .Y(n5916) );
CLKBUFX2TS U5403 ( .A(n824), .Y(n5963) );
BUFX3TS U5404 ( .A(n5913), .Y(n5934) );
BUFX3TS U5405 ( .A(n5917), .Y(n5935) );
BUFX3TS U5406 ( .A(n6004), .Y(n5969) );
BUFX3TS U5407 ( .A(n6004), .Y(n5968) );
BUFX3TS U5408 ( .A(n6006), .Y(n5988) );
BUFX3TS U5409 ( .A(n6006), .Y(n5989) );
BUFX3TS U5410 ( .A(n6006), .Y(n5990) );
BUFX3TS U5411 ( .A(n6007), .Y(n5991) );
BUFX3TS U5412 ( .A(n6007), .Y(n5993) );
BUFX3TS U5413 ( .A(n6007), .Y(n5994) );
BUFX3TS U5414 ( .A(n5962), .Y(n5995) );
CLKBUFX2TS U5415 ( .A(n824), .Y(n4442) );
BUFX3TS U5416 ( .A(n6008), .Y(n5996) );
BUFX3TS U5417 ( .A(n6009), .Y(n5997) );
BUFX3TS U5418 ( .A(n4442), .Y(n5998) );
BUFX3TS U5419 ( .A(n5918), .Y(n5904) );
BUFX3TS U5420 ( .A(n6005), .Y(n5999) );
CLKBUFX2TS U5421 ( .A(n6009), .Y(n6003) );
CLKBUFX2TS U5422 ( .A(n4442), .Y(n6002) );
BUFX3TS U5423 ( .A(n6002), .Y(n5979) );
BUFX3TS U5424 ( .A(n4439), .Y(n5911) );
BUFX3TS U5425 ( .A(n4441), .Y(n5909) );
BUFX3TS U5426 ( .A(n6005), .Y(n5985) );
BUFX3TS U5427 ( .A(n4443), .Y(n5926) );
BUFX3TS U5428 ( .A(n6006), .Y(n5986) );
BUFX3TS U5429 ( .A(n4439), .Y(n5927) );
BUFX3TS U5430 ( .A(n6006), .Y(n5987) );
BUFX3TS U5431 ( .A(n5913), .Y(n5925) );
BUFX3TS U5432 ( .A(n5917), .Y(n5924) );
BUFX3TS U5433 ( .A(n5914), .Y(n5908) );
BUFX3TS U5434 ( .A(n5918), .Y(n5907) );
BUFX3TS U5435 ( .A(n5914), .Y(n5906) );
BUFX3TS U5436 ( .A(n5918), .Y(n5905) );
BUFX3TS U5437 ( .A(n5914), .Y(n5923) );
BUFX3TS U5438 ( .A(n4440), .Y(n5921) );
INVX2TS U5439 ( .A(n5961), .Y(n5437) );
BUFX3TS U5440 ( .A(n5918), .Y(n5903) );
BUFX3TS U5441 ( .A(n5963), .Y(n6001) );
BUFX3TS U5442 ( .A(n5999), .Y(n6000) );
BUFX3TS U5443 ( .A(n6007), .Y(n5992) );
BUFX3TS U5444 ( .A(n5920), .Y(n5912) );
BUFX3TS U5445 ( .A(n4441), .Y(n5910) );
CLKINVX3TS U5446 ( .A(n5437), .Y(n5944) );
BUFX3TS U5447 ( .A(n4443), .Y(n5932) );
BUFX3TS U5448 ( .A(n4439), .Y(n5933) );
BUFX3TS U5449 ( .A(n5952), .Y(n5839) );
BUFX3TS U5450 ( .A(n5839), .Y(n5837) );
BUFX3TS U5451 ( .A(n5913), .Y(n5931) );
INVX2TS U5452 ( .A(n3993), .Y(n5948) );
CLKBUFX3TS U5453 ( .A(n6004), .Y(n5967) );
INVX2TS U5454 ( .A(n3993), .Y(n5950) );
BUFX3TS U5455 ( .A(n5917), .Y(n5930) );
INVX2TS U5456 ( .A(n3993), .Y(n5949) );
INVX2TS U5457 ( .A(n3993), .Y(n5946) );
NAND2X1TS U5458 ( .A(n5462), .B(n5835), .Y(FPADDSUB__6_net_) );
NAND2X1TS U5459 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n4451), .Y(n4466) );
NAND2X1TS U5460 ( .A(n4470), .B(n4466), .Y(FPMULT_FSM_barrel_shifter_load)
);
AND4X1TS U5461 ( .A(n5513), .B(n5529), .C(n5522), .D(n5564), .Y(n5876) );
INVX2TS U5462 ( .A(Data_1[13]), .Y(n4446) );
INVX2TS U5463 ( .A(Data_1[1]), .Y(n4445) );
AND4X1TS U5464 ( .A(n5517), .B(n4446), .C(n4445), .D(n5519), .Y(n5878) );
INVX2TS U5465 ( .A(Data_2[22]), .Y(n4449) );
INVX2TS U5466 ( .A(Data_2[18]), .Y(n4448) );
INVX2TS U5467 ( .A(Data_2[19]), .Y(n4447) );
AND4X1TS U5468 ( .A(n5548), .B(n4449), .C(n4448), .D(n4447), .Y(n5877) );
INVX2TS U5469 ( .A(n1192), .Y(n5258) );
NAND2X1TS U5470 ( .A(n4516), .B(n5433), .Y(n851) );
NAND2X1TS U5471 ( .A(n5711), .B(n937), .Y(n4596) );
INVX2TS U5472 ( .A(n4596), .Y(n4731) );
NOR2X1TS U5473 ( .A(n4452), .B(n5638), .Y(n4455) );
NAND2X1TS U5474 ( .A(n4455), .B(n4236), .Y(n4458) );
NOR2X1TS U5475 ( .A(n5629), .B(n4453), .Y(n4454) );
AOI21X1TS U5476 ( .A0(n4456), .A1(n4455), .B0(n4454), .Y(n4457) );
XNOR2X1TS U5477 ( .A(n4460), .B(n5621), .Y(n4791) );
INVX2TS U5478 ( .A(n4791), .Y(n4461) );
INVX2TS U5479 ( .A(FPMULT_zero_flag), .Y(n4467) );
AOI22X1TS U5480 ( .A0(n4792), .A1(n4461), .B0(n1034), .B1(n4467), .Y(n4462)
);
BUFX3TS U5481 ( .A(n6005), .Y(n5973) );
BUFX3TS U5482 ( .A(n6005), .Y(n5974) );
BUFX3TS U5483 ( .A(n6005), .Y(n5975) );
BUFX3TS U5484 ( .A(n6005), .Y(n5976) );
BUFX3TS U5485 ( .A(n6005), .Y(n5978) );
BUFX3TS U5486 ( .A(n6005), .Y(n5977) );
BUFX3TS U5487 ( .A(n1029), .Y(n5917) );
CLKBUFX3TS U5488 ( .A(n1029), .Y(n5918) );
CLKBUFX2TS U5489 ( .A(n6002), .Y(n4463) );
BUFX3TS U5490 ( .A(n4463), .Y(n5980) );
BUFX3TS U5491 ( .A(n4463), .Y(n5981) );
BUFX3TS U5492 ( .A(n4463), .Y(n5982) );
BUFX3TS U5493 ( .A(n4463), .Y(n5984) );
BUFX3TS U5494 ( .A(n5920), .Y(n5922) );
BUFX3TS U5495 ( .A(n1029), .Y(n5920) );
BUFX3TS U5496 ( .A(n1029), .Y(n5913) );
BUFX3TS U5497 ( .A(n4463), .Y(n5983) );
NAND2X1TS U5498 ( .A(n5768), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1046_CI) );
NAND2X1TS U5499 ( .A(n5769), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1045_CI) );
INVX2TS U5500 ( .A(intadd_1047_SUM_0_), .Y(FPADDSUB_Shift_amount_EXP_EW[1])
);
INVX2TS U5501 ( .A(intadd_1047_SUM_1_), .Y(FPADDSUB_Shift_amount_EXP_EW[2])
);
INVX2TS U5502 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n4778) );
INVX2TS U5503 ( .A(intadd_1047_SUM_2_), .Y(FPADDSUB_Shift_amount_EXP_EW[3])
);
INVX2TS U5504 ( .A(n4468), .Y(intadd_1047_CI) );
OAI22X1TS U5505 ( .A0(n937), .A1(n4471), .B0(n4470), .B1(n4469), .Y(
FPMULT_FSM_load_second_step) );
AOI22X1TS U5506 ( .A0(n5302), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n5247), .Y(n4472) );
AOI22X1TS U5507 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n5302), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n5247), .Y(n4473) );
NAND2X1TS U5508 ( .A(n5074), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4476) );
NAND2X1TS U5509 ( .A(n5248), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4475) );
NAND2X1TS U5510 ( .A(n4707), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n4474) );
NAND2X1TS U5511 ( .A(n5074), .B(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n4479) );
NAND2X1TS U5512 ( .A(n5248), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n4478) );
NAND2X1TS U5513 ( .A(n4707), .B(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n4477) );
NAND2X1TS U5514 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n4482) );
NAND2X1TS U5515 ( .A(n4501), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n4481) );
NAND2X1TS U5516 ( .A(n4707), .B(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n4480) );
NAND2X1TS U5517 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4485) );
NAND2X1TS U5518 ( .A(n4501), .B(FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n4484) );
NAND2X1TS U5519 ( .A(n4707), .B(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n4483) );
NAND2X1TS U5520 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4488) );
NAND2X1TS U5521 ( .A(n5248), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4487) );
NAND2X1TS U5522 ( .A(n4707), .B(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n4486) );
NAND2X1TS U5523 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4491) );
NAND2X1TS U5524 ( .A(n4501), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4490) );
NAND2X1TS U5525 ( .A(n4707), .B(FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n4489) );
NAND2X1TS U5526 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n4494) );
NAND2X1TS U5527 ( .A(n5248), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4493) );
NAND2X1TS U5528 ( .A(n5247), .B(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n4492) );
NAND2X1TS U5529 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n4497) );
NAND2X1TS U5530 ( .A(n5248), .B(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n4496) );
NAND2X1TS U5531 ( .A(n5247), .B(FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n4495) );
NAND2X1TS U5532 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4500) );
NAND2X1TS U5533 ( .A(n5248), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4499) );
NAND2X1TS U5534 ( .A(n4707), .B(FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n4498) );
NAND2X1TS U5535 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n4504) );
NAND2X1TS U5536 ( .A(n4501), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n4503) );
NAND2X1TS U5537 ( .A(n5247), .B(FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n4502) );
AOI22X1TS U5538 ( .A0(n5074), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n5247), .Y(n4505) );
NOR2X1TS U5539 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_1045_n1), .Y(n5468) );
NOR2X1TS U5540 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_1046_n1), .Y(n5465) );
OR3X1TS U5541 ( .A(FPSENCOS_d_ff2_Y[27]), .B(FPSENCOS_d_ff2_Y[28]), .C(
intadd_1046_n1), .Y(n5464) );
INVX2TS U5542 ( .A(n6030), .Y(n6026) );
NAND2X1TS U5543 ( .A(FPSENCOS_cont_iter_out[2]), .B(n5384), .Y(n5383) );
NOR2X1TS U5544 ( .A(n5710), .B(n5383), .Y(n4515) );
INVX2TS U5545 ( .A(n1192), .Y(n4507) );
NOR4X1TS U5546 ( .A(n4512), .B(n4511), .C(n4510), .D(n4509), .Y(n5880) );
INVX2TS U5547 ( .A(n5960), .Y(n4514) );
OAI21X1TS U5548 ( .A0(n5428), .A1(n5732), .B0(n4516), .Y(n863) );
BUFX3TS U5549 ( .A(n4517), .Y(n4593) );
AOI22X1TS U5550 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n4593),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n4518) );
NAND2X1TS U5551 ( .A(n5331), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n4519) );
AOI22X1TS U5552 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n4593),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n4520) );
OR2X2TS U5553 ( .A(n4638), .B(n4521), .Y(n4637) );
OAI22X1TS U5554 ( .A0(n5849), .A1(n1012), .B0(n5850), .B1(n5872), .Y(n4522)
);
AOI21X1TS U5555 ( .A0(n5764), .A1(n5851), .B0(n4522), .Y(n4523) );
NAND2X2TS U5556 ( .A(FPADDSUB_bit_shift_SHT2), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4662) );
NAND2BX2TS U5557 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4663) );
OAI22X1TS U5558 ( .A0(n5845), .A1(n1012), .B0(n5847), .B1(n5872), .Y(n4524)
);
AOI21X1TS U5559 ( .A0(n5764), .A1(n5857), .B0(n4524), .Y(n4525) );
INVX2TS U5560 ( .A(n4762), .Y(n4526) );
NAND2X1TS U5561 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n5772), .Y(n4546)
);
OAI22X1TS U5562 ( .A0(n4663), .A1(n4526), .B0(n4546), .B1(n5797), .Y(n4527)
);
NAND3X2TS U5563 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n4685), .Y(n4766) );
OAI22X1TS U5564 ( .A0(n5858), .A1(n5870), .B0(n5859), .B1(n5872), .Y(n4529)
);
AOI21X1TS U5565 ( .A0(n5764), .A1(n5860), .B0(n4529), .Y(n4530) );
OAI22X1TS U5566 ( .A0(n5862), .A1(n1012), .B0(n5863), .B1(n1061), .Y(n4531)
);
AOI21X1TS U5567 ( .A0(n5764), .A1(n5864), .B0(n4531), .Y(n4532) );
AOI22X1TS U5568 ( .A0(n4528), .A1(n4758), .B0(n1004), .B1(n4682), .Y(n4540)
);
OAI22X1TS U5569 ( .A0(n5853), .A1(n5870), .B0(n5854), .B1(n1061), .Y(n4533)
);
AOI21X1TS U5570 ( .A0(n5764), .A1(n5866), .B0(n4533), .Y(n4534) );
OAI21X1TS U5571 ( .A0(n5855), .A1(n931), .B0(n4534), .Y(n4681) );
NOR2BX1TS U5572 ( .AN(n4521), .B(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n4535) );
OAI22X1TS U5573 ( .A0(n5856), .A1(n5870), .B0(n5846), .B1(n1011), .Y(n4536)
);
AOI21X1TS U5574 ( .A0(n5868), .A1(n5843), .B0(n4536), .Y(n4537) );
AOI22X1TS U5575 ( .A0(n1007), .A1(n4681), .B0(n1010), .B1(n4538), .Y(n4539)
);
OAI211X1TS U5576 ( .A0(n4680), .A1(n4685), .B0(n4540), .C0(n4539), .Y(n4693)
);
NOR2X2TS U5577 ( .A(n1003), .B(n4738), .Y(n4653) );
AOI21X1TS U5578 ( .A0(n4693), .A1(n4757), .B0(n4653), .Y(n4541) );
OAI22X1TS U5579 ( .A0(n5850), .A1(n5870), .B0(n5852), .B1(n1030), .Y(n4542)
);
AOI21X1TS U5580 ( .A0(n5868), .A1(n5851), .B0(n4542), .Y(n4543) );
OAI22X1TS U5581 ( .A0(n5847), .A1(n1012), .B0(n5848), .B1(n1030), .Y(n4544)
);
AOI21X1TS U5582 ( .A0(n5868), .A1(n5857), .B0(n4544), .Y(n4545) );
INVX2TS U5583 ( .A(n4769), .Y(n4547) );
OAI22X1TS U5584 ( .A0(n4663), .A1(n4547), .B0(n4546), .B1(n974), .Y(n4548)
);
OAI211X1TS U5585 ( .A0(n5846), .A1(n1061), .B0(n5844), .C0(n5888), .Y(n4551)
);
OAI22X1TS U5586 ( .A0(n5859), .A1(n1012), .B0(n5861), .B1(n1030), .Y(n4549)
);
AOI21X1TS U5587 ( .A0(n5868), .A1(n5860), .B0(n4549), .Y(n4550) );
AOI22X1TS U5588 ( .A0(n1010), .A1(n4551), .B0(n4528), .B1(n4763), .Y(n4557)
);
OAI22X1TS U5589 ( .A0(n5854), .A1(n1012), .B0(n5855), .B1(n1011), .Y(n4552)
);
AOI21X1TS U5590 ( .A0(n5868), .A1(n5866), .B0(n4552), .Y(n4553) );
OAI21X1TS U5591 ( .A0(n5856), .A1(n1014), .B0(n4553), .Y(n4665) );
OAI22X1TS U5592 ( .A0(n5863), .A1(n5870), .B0(n5865), .B1(n1011), .Y(n4554)
);
AOI21X1TS U5593 ( .A0(n5868), .A1(n5864), .B0(n4554), .Y(n4555) );
AOI22X1TS U5594 ( .A0(n1007), .A1(n4665), .B0(n1005), .B1(n4666), .Y(n4556)
);
OAI211X1TS U5595 ( .A0(n4692), .A1(n968), .B0(n4557), .C0(n4556), .Y(n4560)
);
AOI21X1TS U5596 ( .A0(n4560), .A1(n1003), .B0(n4653), .Y(n4558) );
AOI21X1TS U5597 ( .A0(n1043), .A1(n4560), .B0(n4559), .Y(n4561) );
INVX2TS U5598 ( .A(n5194), .Y(n5442) );
NAND2X1TS U5599 ( .A(n5282), .B(n5281), .Y(n4563) );
AOI22X1TS U5600 ( .A0(operation[1]), .A1(n4563), .B0(begin_operation), .B1(
n5427), .Y(n5439) );
INVX2TS U5601 ( .A(n5440), .Y(n4564) );
AOI22X1TS U5602 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n4593),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n4565) );
NAND2X1TS U5603 ( .A(n4570), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n4580) );
INVX2TS U5604 ( .A(Data_2[3]), .Y(n4568) );
AOI22X1TS U5605 ( .A0(n4566), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n4517),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n4567) );
NAND2X1TS U5606 ( .A(n4570), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n4578) );
INVX2TS U5607 ( .A(n4569), .Y(add_subt_data2[30]) );
AOI22X1TS U5608 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n4517),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n4571) );
NAND2X1TS U5609 ( .A(n4570), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n4575) );
AOI22X1TS U5610 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n4589),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n4572) );
NAND2X1TS U5611 ( .A(n4396), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n4573) );
AOI22X1TS U5612 ( .A0(n5372), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n4517),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n4574) );
INVX2TS U5613 ( .A(Data_2[13]), .Y(n4577) );
AOI22X1TS U5614 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n4593),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n4576) );
AOI22X1TS U5615 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n4593),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n4579) );
INVX2TS U5616 ( .A(Data_2[14]), .Y(n4582) );
AOI22X1TS U5617 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n4593),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n4581) );
INVX2TS U5618 ( .A(Data_2[29]), .Y(n4584) );
AOI22X1TS U5619 ( .A0(n5372), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n4593),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n4583) );
NAND2X1TS U5620 ( .A(n5331), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n4590) );
AOI22X1TS U5621 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n4589),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n4585) );
NAND2X1TS U5622 ( .A(n5331), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n4594) );
INVX2TS U5623 ( .A(Data_2[28]), .Y(n4587) );
AOI22X1TS U5624 ( .A0(n5372), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n4589),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n4586) );
AOI22X1TS U5625 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n4517),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n4588) );
INVX2TS U5626 ( .A(Data_2[27]), .Y(n4592) );
AOI22X1TS U5627 ( .A0(n5372), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n4589),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n4591) );
AOI22X1TS U5628 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n4593),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n4595) );
NOR2X1TS U5629 ( .A(n4597), .B(n4596), .Y(FPMULT_FSM_adder_round_norm_load)
);
OR4X2TS U5630 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n4598) );
INVX2TS U5631 ( .A(n4600), .Y(n4602) );
NAND2X1TS U5632 ( .A(n4602), .B(n4601), .Y(n4603) );
XOR2X1TS U5633 ( .A(n4604), .B(n4603), .Y(n4612) );
NOR4X1TS U5634 ( .A(n4612), .B(n4611), .C(n4610), .D(n4609), .Y(n5883) );
OAI222X4TS U5635 ( .A0(n1061), .A1(n5842), .B0(n931), .B1(n5847), .C0(n1030),
.C1(n5845), .Y(n4745) );
OAI22X1TS U5636 ( .A0(n5848), .A1(n5870), .B0(n5849), .B1(n5872), .Y(n4613)
);
AOI21X1TS U5637 ( .A0(n5765), .A1(n5851), .B0(n4613), .Y(n4614) );
OAI22X1TS U5638 ( .A0(n5845), .A1(n5872), .B0(n5847), .B1(n1030), .Y(n4615)
);
AOI21X1TS U5639 ( .A0(n5765), .A1(n5857), .B0(n4615), .Y(n4616) );
INVX2TS U5640 ( .A(n4756), .Y(n4741) );
OAI21X1TS U5641 ( .A0(n4663), .A1(n4741), .B0(n4662), .Y(n4617) );
OAI22X1TS U5642 ( .A0(n5852), .A1(n1012), .B0(n5858), .B1(n5872), .Y(n4618)
);
AOI21X1TS U5643 ( .A0(n5765), .A1(n5860), .B0(n4618), .Y(n4619) );
OAI22X1TS U5644 ( .A0(n5861), .A1(n5870), .B0(n5862), .B1(n5872), .Y(n4620)
);
AOI21X1TS U5645 ( .A0(n5765), .A1(n5864), .B0(n4620), .Y(n4621) );
AOI22X1TS U5646 ( .A0(n4528), .A1(n4752), .B0(n1004), .B1(n4739), .Y(n4628)
);
OAI22X1TS U5647 ( .A0(n5865), .A1(n5870), .B0(n5853), .B1(n1061), .Y(n4622)
);
AOI21X1TS U5648 ( .A0(n5765), .A1(n5866), .B0(n4622), .Y(n4623) );
OAI21X1TS U5649 ( .A0(n5854), .A1(n1011), .B0(n4623), .Y(n4673) );
OAI22X1TS U5650 ( .A0(n5855), .A1(n1012), .B0(n5856), .B1(n1061), .Y(n4624)
);
AOI21X1TS U5651 ( .A0(n5764), .A1(n5843), .B0(n4624), .Y(n4625) );
AOI22X1TS U5652 ( .A0(n1006), .A1(n4673), .B0(n1009), .B1(n4626), .Y(n4627)
);
OAI211X1TS U5653 ( .A0(n4672), .A1(n968), .B0(n4628), .C0(n4627), .Y(n4696)
);
AOI21X1TS U5654 ( .A0(n4696), .A1(n4757), .B0(n4653), .Y(n4629) );
OAI21X1TS U5655 ( .A0(n4698), .A1(n4717), .B0(n4629), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[2]) );
AOI22X1TS U5656 ( .A0(n1009), .A1(n4682), .B0(n4528), .B1(n4762), .Y(n4631)
);
AOI22X1TS U5657 ( .A0(n1007), .A1(n4758), .B0(n1004), .B1(n4759), .Y(n4630)
);
OAI211X1TS U5658 ( .A0(n4632), .A1(n968), .B0(n4631), .C0(n4630), .Y(n4690)
);
AOI21X1TS U5659 ( .A0(n4774), .A1(n4690), .B0(n4559), .Y(n4633) );
OAI21X1TS U5660 ( .A0(n4699), .A1(n4692), .B0(n4633), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[16]) );
AOI22X1TS U5661 ( .A0(n1007), .A1(n4763), .B0(n1010), .B1(n4666), .Y(n4635)
);
AOI22X1TS U5662 ( .A0(n4528), .A1(n4769), .B0(n1004), .B1(n4764), .Y(n4634)
);
OAI211X1TS U5663 ( .A0(n4695), .A1(n968), .B0(n4635), .C0(n4634), .Y(n4678)
);
NAND2X1TS U5664 ( .A(n4678), .B(n1003), .Y(n4636) );
INVX2TS U5665 ( .A(n4653), .Y(n4715) );
OAI211X1TS U5666 ( .A0(n4680), .A1(n4717), .B0(n4636), .C0(n4715), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[8]) );
OAI22X1TS U5667 ( .A0(n5848), .A1(n5872), .B0(n5849), .B1(n1011), .Y(n4639)
);
AOI21X1TS U5668 ( .A0(n5867), .A1(n5857), .B0(n4639), .Y(n4640) );
INVX2TS U5669 ( .A(n4745), .Y(n4749) );
OAI21X1TS U5670 ( .A0(n4663), .A1(n4749), .B0(n4662), .Y(n4641) );
OAI22X1TS U5671 ( .A0(n5852), .A1(n5872), .B0(n5858), .B1(n1030), .Y(n4642)
);
AOI21X1TS U5672 ( .A0(n5867), .A1(n5851), .B0(n4642), .Y(n4643) );
OAI22X1TS U5673 ( .A0(n5861), .A1(n1061), .B0(n5862), .B1(n1030), .Y(n4644)
);
AOI21X1TS U5674 ( .A0(n5867), .A1(n5860), .B0(n4644), .Y(n4645) );
AOI22X1TS U5675 ( .A0(n4528), .A1(n4747), .B0(n1004), .B1(n4746), .Y(n4652)
);
OAI22X1TS U5676 ( .A0(n5865), .A1(n1061), .B0(n5853), .B1(n1011), .Y(n4646)
);
AOI21X1TS U5677 ( .A0(n5867), .A1(n5864), .B0(n4646), .Y(n4647) );
OAI21X1TS U5678 ( .A0(n5854), .A1(n1014), .B0(n4647), .Y(n4657) );
OAI22X1TS U5679 ( .A0(n5855), .A1(n1061), .B0(n5856), .B1(n1011), .Y(n4648)
);
AOI21X1TS U5680 ( .A0(n5867), .A1(n5866), .B0(n4648), .Y(n4649) );
AOI22X1TS U5681 ( .A0(n1006), .A1(n4657), .B0(n1010), .B1(n4650), .Y(n4651)
);
OAI211X1TS U5682 ( .A0(n4689), .A1(n4685), .B0(n4652), .C0(n4651), .Y(n4655)
);
AOI21X1TS U5683 ( .A0(n4655), .A1(n4757), .B0(n4653), .Y(n4654) );
OAI21X1TS U5684 ( .A0(n4676), .A1(n4717), .B0(n4654), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[3]) );
AOI21X1TS U5685 ( .A0(n4774), .A1(n4655), .B0(n4559), .Y(n4656) );
OAI21X1TS U5686 ( .A0(n4699), .A1(n4676), .B0(n4656), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[22]) );
AOI22X1TS U5687 ( .A0(n1007), .A1(n4746), .B0(n1010), .B1(n4657), .Y(n4659)
);
AOI22X1TS U5688 ( .A0(n4528), .A1(n4751), .B0(n1004), .B1(n4747), .Y(n4658)
);
OAI211X1TS U5689 ( .A0(n4698), .A1(n968), .B0(n4659), .C0(n4658), .Y(n4670)
);
NAND2X1TS U5690 ( .A(n4670), .B(n4757), .Y(n4660) );
OAI211X1TS U5691 ( .A0(n4672), .A1(n4717), .B0(n4660), .C0(n4715), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[7]) );
OAI21X1TS U5692 ( .A0(n4663), .A1(n974), .B0(n4662), .Y(n4664) );
AOI22X1TS U5693 ( .A0(n4528), .A1(n4764), .B0(n1004), .B1(n4763), .Y(n4668)
);
AOI22X1TS U5694 ( .A0(n1007), .A1(n4666), .B0(n1010), .B1(n4665), .Y(n4667)
);
OAI211X1TS U5695 ( .A0(n4713), .A1(n968), .B0(n4668), .C0(n4667), .Y(n4714)
);
AOI21X1TS U5696 ( .A0(n4774), .A1(n4714), .B0(n4559), .Y(n4669) );
OAI21X1TS U5697 ( .A0(n4699), .A1(n4718), .B0(n4669), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[21]) );
AOI21X1TS U5698 ( .A0(n4774), .A1(n4670), .B0(n4559), .Y(n4671) );
OAI21X1TS U5699 ( .A0(n4699), .A1(n4672), .B0(n4671), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[18]) );
AOI22X1TS U5700 ( .A0(n1007), .A1(n4739), .B0(n4673), .B1(n1010), .Y(n4675)
);
AOI22X1TS U5701 ( .A0(n4753), .A1(n4528), .B0(n4752), .B1(n1004), .Y(n4674)
);
OAI211X1TS U5702 ( .A0(n4676), .A1(n968), .B0(n4675), .C0(n4674), .Y(n4687)
);
AOI21X1TS U5703 ( .A0(n4774), .A1(n4687), .B0(n4559), .Y(n4677) );
OAI21X1TS U5704 ( .A0(n4689), .A1(n4699), .B0(n4677), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[19]) );
AOI21X1TS U5705 ( .A0(n4774), .A1(n4678), .B0(n4559), .Y(n4679) );
OAI21X1TS U5706 ( .A0(n4699), .A1(n4680), .B0(n4679), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[17]) );
AOI22X1TS U5707 ( .A0(n4528), .A1(n4759), .B0(n1005), .B1(n4758), .Y(n4684)
);
AOI22X1TS U5708 ( .A0(n1007), .A1(n4682), .B0(n1010), .B1(n4681), .Y(n4683)
);
OAI211X1TS U5709 ( .A0(n4718), .A1(n968), .B0(n4684), .C0(n4683), .Y(n4711)
);
AOI21X1TS U5710 ( .A0(n4774), .A1(n4711), .B0(n4559), .Y(n4686) );
OAI21X1TS U5711 ( .A0(n4699), .A1(n4713), .B0(n4686), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[20]) );
NAND2X1TS U5712 ( .A(n4687), .B(n1003), .Y(n4688) );
OAI211X1TS U5713 ( .A0(n4689), .A1(n4717), .B0(n4688), .C0(n4715), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[6]) );
NAND2X1TS U5714 ( .A(n4690), .B(n4757), .Y(n4691) );
OAI211X1TS U5715 ( .A0(n4692), .A1(n4717), .B0(n4691), .C0(n4715), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[9]) );
AOI21X1TS U5716 ( .A0(n1043), .A1(n4693), .B0(n4559), .Y(n4694) );
OAI21X1TS U5717 ( .A0(n4699), .A1(n4695), .B0(n4694), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[24]) );
AOI21X1TS U5718 ( .A0(n1043), .A1(n4696), .B0(n4559), .Y(n4697) );
OAI21X1TS U5719 ( .A0(n4699), .A1(n4698), .B0(n4697), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[23]) );
AND4X1TS U5720 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n4700) );
AND3X4TS U5721 ( .A(n4702), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n4701),
.Y(n6041) );
NOR2X2TS U5722 ( .A(n4704), .B(n4703), .Y(n6031) );
INVX2TS U5723 ( .A(n6031), .Y(n6028) );
INVX2TS U5724 ( .A(n6029), .Y(n6034) );
NAND2X1TS U5725 ( .A(n4706), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4710) );
NAND2X1TS U5726 ( .A(n5302), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n4709) );
NAND2X1TS U5727 ( .A(n4707), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n4708) );
NOR4BBX1TS U5728 ( .AN(n4568), .BN(n5550), .C(Data_2[0]), .D(Data_2[2]), .Y(
n5841) );
NAND2X1TS U5729 ( .A(n4711), .B(n4757), .Y(n4712) );
OAI211X1TS U5730 ( .A0(n4713), .A1(n4717), .B0(n4712), .C0(n4715), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[5]) );
NAND2X1TS U5731 ( .A(n4714), .B(n4757), .Y(n4716) );
OAI211X1TS U5732 ( .A0(n4718), .A1(n4717), .B0(n4716), .C0(n4715), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[4]) );
AOI211X1TS U5733 ( .A0(n4723), .A1(n4722), .B0(n4721), .C0(n4720), .Y(n4725)
);
OAI211X1TS U5734 ( .A0(n4727), .A1(n4726), .B0(n4725), .C0(n4724), .Y(
FPADDSUB_LZD_raw_out_EWR[3]) );
OAI21XLTS U5735 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n1027), .B0(n4728),
.Y(n810) );
NOR3XLTS U5736 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n976), .Y(FPSENCOS_enab_d_ff4_Xn) );
NOR3XLTS U5737 ( .A(FPSENCOS_cont_var_out[1]), .B(n5730), .C(n976), .Y(
FPSENCOS_enab_d_ff4_Yn) );
INVX2TS U5738 ( .A(n4729), .Y(n4733) );
AOI22X1TS U5739 ( .A0(n4733), .A1(n4732), .B0(n4731), .B1(n4730), .Y(n4734)
);
NOR2X1TS U5740 ( .A(n5960), .B(n4736), .Y(n5276) );
NAND2X1TS U5741 ( .A(n5276), .B(n976), .Y(n5444) );
INVX2TS U5742 ( .A(n5444), .Y(n5443) );
INVX2TS U5743 ( .A(n4738), .Y(n4768) );
AOI22X1TS U5744 ( .A0(n1006), .A1(n4752), .B0(n1009), .B1(n4739), .Y(n4740)
);
AOI211X1TS U5745 ( .A0(n4753), .A1(n1005), .B0(n4768), .C0(n4742), .Y(n4776)
);
AOI211X1TS U5746 ( .A0(n1005), .A1(n4745), .B0(n4755), .C0(n4744), .Y(n4775)
);
MXI2X1TS U5747 ( .A(n4776), .B(n4775), .S0(n4757), .Y(n5748) );
AOI22X1TS U5748 ( .A0(n1006), .A1(n4747), .B0(n1009), .B1(n4746), .Y(n4748)
);
AOI211X1TS U5749 ( .A0(n1005), .A1(n4751), .B0(n4768), .C0(n4750), .Y(n4773)
);
AOI211X1TS U5750 ( .A0(n4756), .A1(n1005), .B0(n4755), .C0(n4754), .Y(n4772)
);
MXI2X1TS U5751 ( .A(n4773), .B(n4772), .S0(n1003), .Y(n5749) );
AOI22X1TS U5752 ( .A0(n1006), .A1(n4759), .B0(n1009), .B1(n4758), .Y(n4760)
);
AOI211X1TS U5753 ( .A0(n1005), .A1(n4762), .B0(n4768), .C0(n4761), .Y(n4770)
);
AOI22X1TS U5754 ( .A0(n1006), .A1(n4764), .B0(n1009), .B1(n4763), .Y(n4765)
);
AOI211X1TS U5755 ( .A0(n1005), .A1(n4769), .B0(n4768), .C0(n4767), .Y(n4771)
);
MXI2X1TS U5756 ( .A(n4770), .B(n4771), .S0(n1043), .Y(n5750) );
MXI2X1TS U5757 ( .A(n4771), .B(n4770), .S0(n1043), .Y(n5751) );
MXI2X1TS U5758 ( .A(n4773), .B(n4772), .S0(n1043), .Y(n5752) );
MXI2X1TS U5759 ( .A(n4776), .B(n4775), .S0(n1043), .Y(n5753) );
INVX2TS U5760 ( .A(Data_1[18]), .Y(n4777) );
XNOR2X1TS U5761 ( .A(DP_OP_234J311_129_4955_n1), .B(n4778), .Y(
FPMULT_Exp_module_Overflow_A) );
NOR3BX1TS U5762 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n4779) );
XOR2X1TS U5763 ( .A(n1034), .B(n4779), .Y(DP_OP_234J311_129_4955_n15) );
OAI2BB1X1TS U5764 ( .A0N(FPMULT_Op_MY[29]), .A1N(n5733), .B0(n4785), .Y(
n4780) );
XOR2X1TS U5765 ( .A(n1034), .B(n4780), .Y(DP_OP_234J311_129_4955_n16) );
OAI2BB1X1TS U5766 ( .A0N(FPMULT_Op_MY[28]), .A1N(n5733), .B0(n4785), .Y(
n4781) );
XOR2X1TS U5767 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4781), .Y(
DP_OP_234J311_129_4955_n17) );
OAI2BB1X1TS U5768 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5733), .B0(n4785), .Y(
n4782) );
XOR2X1TS U5769 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4782), .Y(
DP_OP_234J311_129_4955_n18) );
OAI2BB1X1TS U5770 ( .A0N(FPMULT_Op_MY[26]), .A1N(n5733), .B0(n4785), .Y(
n4783) );
XOR2X1TS U5771 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4783), .Y(
DP_OP_234J311_129_4955_n19) );
OAI2BB1X1TS U5772 ( .A0N(FPMULT_Op_MY[25]), .A1N(n5733), .B0(n4785), .Y(
n4784) );
XOR2X1TS U5773 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4784), .Y(
DP_OP_234J311_129_4955_n20) );
OAI2BB1X1TS U5774 ( .A0N(FPMULT_Op_MY[24]), .A1N(n5733), .B0(n4785), .Y(
n4786) );
XOR2X1TS U5775 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4786), .Y(
DP_OP_234J311_129_4955_n21) );
NOR2BX1TS U5776 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4787) );
XOR2X1TS U5777 ( .A(n1027), .B(n4787), .Y(DP_OP_26J311_126_1325_n14) );
NOR2BX1TS U5778 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4788) );
XOR2X1TS U5779 ( .A(n1027), .B(n4788), .Y(DP_OP_26J311_126_1325_n15) );
NOR2BX1TS U5780 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4789) );
XOR2X1TS U5781 ( .A(n1027), .B(n4789), .Y(DP_OP_26J311_126_1325_n16) );
NOR2BX1TS U5782 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4790) );
XOR2X1TS U5783 ( .A(n1027), .B(n4790), .Y(DP_OP_26J311_126_1325_n17) );
NOR2X1TS U5784 ( .A(n107), .B(FPMULT_FSM_adder_round_norm_load), .Y(n4793)
);
OAI2BB1X1TS U5785 ( .A0N(FPMULT_FSM_selector_B[1]), .A1N(n4793), .B0(n4794),
.Y(n829) );
OAI2BB1X1TS U5786 ( .A0N(FPMULT_FSM_selector_B[0]), .A1N(n4794), .B0(n4793),
.Y(n830) );
MX2X1TS U5787 ( .A(FPADDSUB_OP_FLAG_SHT2), .B(FPADDSUB_OP_FLAG_SHT1), .S0(
busy), .Y(n813) );
INVX2TS U5788 ( .A(n4795), .Y(n5026) );
AOI21X1TS U5789 ( .A0(n5026), .A1(n4797), .B0(n4796), .Y(n4823) );
NAND2X1TS U5790 ( .A(n4800), .B(n4799), .Y(n4816) );
XNOR2X1TS U5791 ( .A(n4801), .B(n4816), .Y(n4819) );
NAND2X1TS U5792 ( .A(n5744), .B(n5717), .Y(n5068) );
NAND2X1TS U5793 ( .A(n5743), .B(FPADDSUB_DMP_SFG[0]), .Y(n4802) );
NOR2X1TS U5794 ( .A(n5742), .B(FPADDSUB_DMP_SFG[1]), .Y(n5052) );
NOR2X1TS U5795 ( .A(n5737), .B(FPADDSUB_DMP_SFG[2]), .Y(n4805) );
NOR2X1TS U5796 ( .A(n5052), .B(n4805), .Y(n4807) );
NAND2X1TS U5797 ( .A(n5742), .B(FPADDSUB_DMP_SFG[1]), .Y(n5051) );
NAND2X1TS U5798 ( .A(n5737), .B(FPADDSUB_DMP_SFG[2]), .Y(n4804) );
OAI21X1TS U5799 ( .A0(n4805), .A1(n5051), .B0(n4804), .Y(n4806) );
AOI21X2TS U5800 ( .A0(n5050), .A1(n4807), .B0(n4806), .Y(n4824) );
NOR2X1TS U5801 ( .A(n5741), .B(FPADDSUB_DMP_SFG[3]), .Y(n5027) );
NOR2X1TS U5802 ( .A(n5736), .B(FPADDSUB_DMP_SFG[4]), .Y(n4809) );
NOR2X1TS U5803 ( .A(n5027), .B(n4809), .Y(n4826) );
NOR2X1TS U5804 ( .A(n5740), .B(FPADDSUB_DMP_SFG[5]), .Y(n4828) );
NOR2X1TS U5805 ( .A(n5735), .B(FPADDSUB_DMP_SFG[6]), .Y(n4811) );
NAND2X1TS U5806 ( .A(n4826), .B(n4813), .Y(n4815) );
NAND2X1TS U5807 ( .A(n5741), .B(FPADDSUB_DMP_SFG[3]), .Y(n5028) );
NAND2X1TS U5808 ( .A(n5736), .B(FPADDSUB_DMP_SFG[4]), .Y(n4808) );
OAI21X1TS U5809 ( .A0(n4809), .A1(n5028), .B0(n4808), .Y(n4825) );
NAND2X1TS U5810 ( .A(n5740), .B(FPADDSUB_DMP_SFG[5]), .Y(n4827) );
NAND2X1TS U5811 ( .A(n5735), .B(FPADDSUB_DMP_SFG[6]), .Y(n4810) );
AOI21X1TS U5812 ( .A0(n4825), .A1(n4813), .B0(n4812), .Y(n4814) );
OAI21X4TS U5813 ( .A0(n4824), .A1(n4815), .B0(n4814), .Y(n4860) );
INVX2TS U5814 ( .A(n4860), .Y(n5006) );
INVX2TS U5815 ( .A(n4816), .Y(n4817) );
XOR2X1TS U5816 ( .A(n5006), .B(n4817), .Y(n4818) );
NAND2X1TS U5817 ( .A(n4822), .B(n4821), .Y(n4829) );
XOR2X1TS U5818 ( .A(n4823), .B(n4829), .Y(n4833) );
INVX2TS U5819 ( .A(n4824), .Y(n5043) );
AOI21X1TS U5820 ( .A0(n5043), .A1(n4826), .B0(n4825), .Y(n5020) );
INVX2TS U5821 ( .A(n4829), .Y(n4830) );
XNOR2X1TS U5822 ( .A(n4831), .B(n4830), .Y(n4832) );
INVX2TS U5823 ( .A(n4834), .Y(n5003) );
NAND2X1TS U5824 ( .A(n4839), .B(n4838), .Y(n4845) );
XNOR2X1TS U5825 ( .A(n4840), .B(n4845), .Y(n4849) );
NOR2X1TS U5826 ( .A(n5739), .B(FPADDSUB_DMP_SFG[7]), .Y(n5005) );
NAND2X1TS U5827 ( .A(n5739), .B(FPADDSUB_DMP_SFG[7]), .Y(n5004) );
NAND2X1TS U5828 ( .A(n5713), .B(FPADDSUB_DMP_SFG[8]), .Y(n4841) );
AOI21X2TS U5829 ( .A0(n4870), .A1(n4844), .B0(n4843), .Y(n4857) );
INVX2TS U5830 ( .A(n4845), .Y(n4846) );
XNOR2X1TS U5831 ( .A(n4847), .B(n4846), .Y(n4848) );
NAND2X1TS U5832 ( .A(n4852), .B(n4851), .Y(n4861) );
XOR2X1TS U5833 ( .A(n4853), .B(n4861), .Y(n4864) );
NOR2X1TS U5834 ( .A(n5714), .B(FPADDSUB_DMP_SFG[10]), .Y(n4856) );
NAND2X1TS U5835 ( .A(n5714), .B(FPADDSUB_DMP_SFG[10]), .Y(n4855) );
OAI21X1TS U5836 ( .A0(n4857), .A1(n4856), .B0(n4855), .Y(n4858) );
INVX2TS U5837 ( .A(n4861), .Y(n4862) );
XOR2X1TS U5838 ( .A(n4884), .B(n4862), .Y(n4863) );
NAND2X1TS U5839 ( .A(n4867), .B(n4866), .Y(n4873) );
XNOR2X1TS U5840 ( .A(n4868), .B(n4873), .Y(n4877) );
INVX2TS U5841 ( .A(n4873), .Y(n4874) );
XNOR2X1TS U5842 ( .A(n4875), .B(n4874), .Y(n4876) );
INVX2TS U5843 ( .A(n4878), .Y(n4880) );
NAND2X1TS U5844 ( .A(n4880), .B(n4879), .Y(n4899) );
XOR2X1TS U5845 ( .A(n4881), .B(n4899), .Y(n4902) );
NAND2X1TS U5846 ( .A(n5715), .B(FPADDSUB_DMP_SFG[11]), .Y(n4882) );
OR2X1TS U5847 ( .A(n5720), .B(FPADDSUB_DMP_SFG[12]), .Y(n4886) );
AOI21X4TS U5848 ( .A0(n4998), .A1(n4886), .B0(n4885), .Y(n4990) );
NAND2X1TS U5849 ( .A(n5719), .B(FPADDSUB_DMP_SFG[13]), .Y(n4887) );
OR2X1TS U5850 ( .A(n5746), .B(FPADDSUB_DMP_SFG[14]), .Y(n4890) );
NAND2X1TS U5851 ( .A(n5774), .B(FPADDSUB_DMP_SFG[15]), .Y(n4891) );
OR2X1TS U5852 ( .A(n5775), .B(FPADDSUB_DMP_SFG[16]), .Y(n4894) );
NOR2X1TS U5853 ( .A(n5786), .B(FPADDSUB_DMP_SFG[17]), .Y(n4896) );
NAND2X1TS U5854 ( .A(n5786), .B(FPADDSUB_DMP_SFG[17]), .Y(n4895) );
OAI21X4TS U5855 ( .A0(n4917), .A1(n4896), .B0(n4895), .Y(n4908) );
OR2X1TS U5856 ( .A(n5787), .B(FPADDSUB_DMP_SFG[18]), .Y(n4898) );
AOI21X4TS U5857 ( .A0(n4908), .A1(n4898), .B0(n4897), .Y(n4925) );
INVX2TS U5858 ( .A(n4899), .Y(n4900) );
XOR2X1TS U5859 ( .A(n4925), .B(n4900), .Y(n4901) );
NAND2X1TS U5860 ( .A(n4904), .B(n4903), .Y(n4906) );
XNOR2X1TS U5861 ( .A(n4905), .B(n4906), .Y(n4910) );
INVX2TS U5862 ( .A(n4906), .Y(n4907) );
XNOR2X1TS U5863 ( .A(n4908), .B(n4907), .Y(n4909) );
INVX2TS U5864 ( .A(n4911), .Y(n4913) );
NAND2X1TS U5865 ( .A(n4913), .B(n4912), .Y(n4915) );
XOR2X1TS U5866 ( .A(n4914), .B(n4915), .Y(n4919) );
INVX2TS U5867 ( .A(n4915), .Y(n4916) );
XOR2X1TS U5868 ( .A(n4917), .B(n4916), .Y(n4918) );
NAND2X1TS U5869 ( .A(n4921), .B(n4920), .Y(n4926) );
XNOR2X1TS U5870 ( .A(n4922), .B(n4926), .Y(n4930) );
NOR2X1TS U5871 ( .A(n5785), .B(FPADDSUB_DMP_SFG[19]), .Y(n4924) );
NAND2X1TS U5872 ( .A(n5785), .B(FPADDSUB_DMP_SFG[19]), .Y(n4923) );
OAI21X4TS U5873 ( .A0(n4925), .A1(n4924), .B0(n4923), .Y(n4937) );
INVX2TS U5874 ( .A(n4926), .Y(n4927) );
XNOR2X1TS U5875 ( .A(n4937), .B(n4927), .Y(n4929) );
INVX2TS U5876 ( .A(n4931), .Y(n4933) );
NAND2X1TS U5877 ( .A(n4933), .B(n4932), .Y(n4938) );
XOR2X1TS U5878 ( .A(n4934), .B(n4938), .Y(n4941) );
OR2X1TS U5879 ( .A(n5795), .B(FPADDSUB_DMP_SFG[20]), .Y(n4936) );
INVX2TS U5880 ( .A(n4938), .Y(n4939) );
XOR2X1TS U5881 ( .A(n4947), .B(n4939), .Y(n4940) );
BUFX3TS U5882 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n5021) );
NAND2X1TS U5883 ( .A(n4943), .B(n4942), .Y(n4948) );
XNOR2X1TS U5884 ( .A(n4944), .B(n4948), .Y(n4951) );
NAND2X1TS U5885 ( .A(n5793), .B(FPADDSUB_DMP_SFG[21]), .Y(n4945) );
OAI21X2TS U5886 ( .A0(n4947), .A1(n4946), .B0(n4945), .Y(n4955) );
INVX2TS U5887 ( .A(n4948), .Y(n4949) );
XNOR2X1TS U5888 ( .A(n4955), .B(n4949), .Y(n4950) );
XOR2X1TS U5889 ( .A(n4952), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n4958) );
OR2X1TS U5890 ( .A(n5794), .B(FPADDSUB_DMP_SFG[22]), .Y(n4954) );
XOR2X1TS U5891 ( .A(n4956), .B(n5833), .Y(n4957) );
NAND2X1TS U5892 ( .A(n4960), .B(n4959), .Y(n4962) );
XNOR2X1TS U5893 ( .A(n4961), .B(n4962), .Y(n4966) );
INVX2TS U5894 ( .A(n4962), .Y(n4963) );
XNOR2X1TS U5895 ( .A(n4964), .B(n4963), .Y(n4965) );
INVX2TS U5896 ( .A(n4967), .Y(n4969) );
NAND2X1TS U5897 ( .A(n4969), .B(n4968), .Y(n4971) );
XOR2X1TS U5898 ( .A(n4970), .B(n4971), .Y(n4975) );
INVX2TS U5899 ( .A(n4971), .Y(n4972) );
XOR2X1TS U5900 ( .A(n4973), .B(n4972), .Y(n4974) );
NAND2X1TS U5901 ( .A(n4977), .B(n4976), .Y(n4979) );
XNOR2X1TS U5902 ( .A(n4978), .B(n4979), .Y(n4983) );
INVX2TS U5903 ( .A(n4979), .Y(n4980) );
XNOR2X1TS U5904 ( .A(n4981), .B(n4980), .Y(n4982) );
INVX2TS U5905 ( .A(n4984), .Y(n4986) );
NAND2X1TS U5906 ( .A(n4986), .B(n4985), .Y(n4988) );
XOR2X1TS U5907 ( .A(n4987), .B(n4988), .Y(n4992) );
INVX2TS U5908 ( .A(n4988), .Y(n4989) );
XOR2X1TS U5909 ( .A(n4990), .B(n4989), .Y(n4991) );
NAND2X1TS U5910 ( .A(n4994), .B(n4993), .Y(n4996) );
XNOR2X1TS U5911 ( .A(n4995), .B(n4996), .Y(n5000) );
INVX2TS U5912 ( .A(n4996), .Y(n4997) );
XNOR2X1TS U5913 ( .A(n4998), .B(n4997), .Y(n4999) );
NAND2X1TS U5914 ( .A(n5002), .B(n5001), .Y(n5007) );
XOR2X1TS U5915 ( .A(n5003), .B(n5007), .Y(n5011) );
INVX2TS U5916 ( .A(n5007), .Y(n5008) );
XNOR2X1TS U5917 ( .A(n5009), .B(n5008), .Y(n5010) );
AOI21X1TS U5918 ( .A0(n5026), .A1(n5025), .B0(n5013), .Y(n5017) );
NAND2X1TS U5919 ( .A(n5016), .B(n5015), .Y(n5018) );
XOR2X1TS U5920 ( .A(n5017), .B(n5018), .Y(n5023) );
INVX2TS U5921 ( .A(n5018), .Y(n5019) );
XOR2X1TS U5922 ( .A(n5020), .B(n5019), .Y(n5022) );
NAND2X1TS U5923 ( .A(n5025), .B(n5024), .Y(n5031) );
XNOR2X1TS U5924 ( .A(n5026), .B(n5031), .Y(n5035) );
AOI21X1TS U5925 ( .A0(n5043), .A1(n5030), .B0(n5029), .Y(n5033) );
INVX2TS U5926 ( .A(n5031), .Y(n5032) );
XOR2X1TS U5927 ( .A(n5033), .B(n5032), .Y(n5034) );
NAND2X1TS U5928 ( .A(n5039), .B(n5038), .Y(n5041) );
XNOR2X1TS U5929 ( .A(n5040), .B(n5041), .Y(n5045) );
INVX2TS U5930 ( .A(n5041), .Y(n5042) );
XNOR2X1TS U5931 ( .A(n5043), .B(n5042), .Y(n5044) );
NAND2X1TS U5932 ( .A(n5048), .B(n5047), .Y(n5053) );
XOR2X1TS U5933 ( .A(n5049), .B(n5053), .Y(n5057) );
INVX2TS U5934 ( .A(n5050), .Y(n5063) );
INVX2TS U5935 ( .A(n5053), .Y(n5054) );
XNOR2X1TS U5936 ( .A(n5055), .B(n5054), .Y(n5056) );
NAND2X1TS U5937 ( .A(n5060), .B(n5059), .Y(n5061) );
XOR2X1TS U5938 ( .A(n5061), .B(n5066), .Y(n5065) );
INVX2TS U5939 ( .A(n5061), .Y(n5062) );
XOR2X1TS U5940 ( .A(n5063), .B(n5062), .Y(n5064) );
OR2X1TS U5941 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n5067) );
XOR2X1TS U5942 ( .A(n5070), .B(n5068), .Y(n5069) );
XNOR2X1TS U5943 ( .A(FPADDSUB_N60), .B(n5717), .Y(n5072) );
AOI22X1TS U5944 ( .A0(n5074), .A1(FPADDSUB_Raw_mant_NRM_SWR[18]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n5247), .Y(n5073) );
OAI2BB1X1TS U5945 ( .A0N(n5248), .A1N(FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(
n5073), .Y(n6016) );
AOI22X1TS U5946 ( .A0(n5074), .A1(FPADDSUB_Raw_mant_NRM_SWR[1]), .B0(n4501),
.B1(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n6033) );
AOI22X1TS U5947 ( .A0(n6031), .A1(n6030), .B0(n5248), .B1(
FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n6032) );
NOR2BX1TS U5948 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n6041), .Y(
FPADDSUB_formatted_number_W[30]) );
NOR2X1TS U5949 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n5195) );
BUFX3TS U5950 ( .A(n5251), .Y(n5253) );
XOR2X1TS U5951 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(FPADDSUB_DmP_EXP_EWSW[27]), .Y(n5075) );
NOR2BX1TS U5952 ( .AN(operation[0]), .B(n5338), .Y(n6047) );
AOI2BB2XLTS U5953 ( .B0(FPSENCOS_cont_var_out[0]), .B1(
FPSENCOS_d_ff3_sign_out), .A0N(FPSENCOS_d_ff3_sign_out), .A1N(
FPSENCOS_cont_var_out[0]), .Y(n5076) );
INVX2TS U5954 ( .A(n5078), .Y(n5079) );
XNOR2X1TS U5955 ( .A(n5080), .B(n5079), .Y(n5884) );
AOI22X1TS U5956 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n5818), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n5081), .Y(n5085) );
OAI21X1TS U5957 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n5822), .B0(n5082), .Y(
n5143) );
OAI211X1TS U5958 ( .A0(n5085), .A1(n5143), .B0(n5084), .C0(n5083), .Y(n5090)
);
INVX2TS U5959 ( .A(FPADDSUB_intDY_EWSW[29]), .Y(n5244) );
NOR3X1TS U5960 ( .A(n5745), .B(n5086), .C(FPADDSUB_intDY_EWSW[28]), .Y(n5087) );
INVX2TS U5961 ( .A(FPADDSUB_intDX_EWSW[10]), .Y(n5225) );
NOR2X1TS U5962 ( .A(n5815), .B(FPADDSUB_intDX_EWSW[11]), .Y(n5106) );
AOI21X1TS U5963 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n5225), .B0(n5106), .Y(
n5111) );
INVX2TS U5964 ( .A(FPADDSUB_intDX_EWSW[5]), .Y(n5231) );
OAI2BB1X1TS U5965 ( .A0N(n5231), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n5091) );
OAI22X1TS U5966 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n5091), .B0(n5231), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n5103) );
INVX2TS U5967 ( .A(FPADDSUB_intDX_EWSW[7]), .Y(n5235) );
OAI2BB1X1TS U5968 ( .A0N(n5235), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n5092) );
OAI22X1TS U5969 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n5092), .B0(n5235), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n5102) );
INVX2TS U5970 ( .A(FPADDSUB_intDX_EWSW[4]), .Y(n5230) );
INVX2TS U5971 ( .A(FPADDSUB_intDY_EWSW[3]), .Y(n5097) );
OAI2BB2XLTS U5972 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n5093), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n5821), .Y(n5095) );
AOI222X1TS U5973 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n5230), .B0(n5099), .B1(
n5098), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n5231), .Y(n5101) );
INVX2TS U5974 ( .A(FPADDSUB_intDX_EWSW[6]), .Y(n5232) );
AOI22X1TS U5975 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n5235), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n5232), .Y(n5100) );
OAI32X1TS U5976 ( .A0(n5103), .A1(n5102), .A2(n5101), .B0(n5100), .B1(n5102),
.Y(n5122) );
INVX2TS U5977 ( .A(FPADDSUB_intDY_EWSW[12]), .Y(n5236) );
INVX2TS U5978 ( .A(FPADDSUB_intDY_EWSW[15]), .Y(n5114) );
OAI2BB2XLTS U5979 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n5105), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n5808), .Y(n5118) );
AOI22X1TS U5980 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n5815), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n5107), .Y(n5113) );
AOI21X1TS U5981 ( .A0(n5110), .A1(n5109), .B0(n5121), .Y(n5112) );
AOI211X1TS U5982 ( .A0(n5119), .A1(n5118), .B0(n5117), .C0(n5116), .Y(n5120)
);
OAI31X1TS U5983 ( .A0(n5123), .A1(n5122), .A2(n5121), .B0(n5120), .Y(n5126)
);
INVX2TS U5984 ( .A(FPADDSUB_intDX_EWSW[16]), .Y(n5237) );
INVX2TS U5985 ( .A(FPADDSUB_intDY_EWSW[23]), .Y(n5135) );
OAI21X1TS U5986 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n5820), .B0(n5130), .Y(
n5134) );
OAI2BB2XLTS U5987 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n5127), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n5813), .Y(n5139) );
AOI22X1TS U5988 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n5817), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n5129), .Y(n5132) );
OAI32X1TS U5989 ( .A0(n5134), .A1(n5133), .A2(n5132), .B0(n5131), .B1(n5133),
.Y(n5138) );
AOI211X1TS U5990 ( .A0(n5158), .A1(n5139), .B0(n5138), .C0(n5137), .Y(n5145)
);
AOI22X1TS U5991 ( .A0(n5724), .A1(FPADDSUB_intDX_EWSW[29]), .B0(n980), .B1(
FPADDSUB_intDY_EWSW[18]), .Y(n5149) );
AOI22X1TS U5992 ( .A0(n5781), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n5778), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n5150) );
AOI22X1TS U5993 ( .A0(n945), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n983), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n5151) );
AOI22X1TS U5994 ( .A0(n978), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n942), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n5152) );
NOR4X1TS U5995 ( .A(n5156), .B(n5155), .C(n5154), .D(n5153), .Y(n5182) );
AOI22X1TS U5996 ( .A0(n5722), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n5777), .B1(
FPADDSUB_intDY_EWSW[4]), .Y(n5157) );
AOI22X1TS U5997 ( .A0(n977), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n5776), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n5159) );
AOI22X1TS U5998 ( .A0(n973), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n925), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n5160) );
OAI221XLTS U5999 ( .A0(n973), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n925), .B1(
FPADDSUB_intDY_EWSW[8]), .C0(n5160), .Y(n5161) );
NOR4X1TS U6000 ( .A(n5164), .B(n5163), .C(n5162), .D(n5161), .Y(n5181) );
AOI22X1TS U6001 ( .A0(n5782), .A1(FPADDSUB_intDX_EWSW[30]), .B0(n981), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n5165) );
AOI22X1TS U6002 ( .A0(n944), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n982), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n5166) );
OAI22X1TS U6003 ( .A0(n940), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n966), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n5167) );
OAI22X1TS U6004 ( .A0(n5767), .A1(FPADDSUB_intDX_EWSW[12]), .B0(n970), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n5169) );
OAI22X1TS U6005 ( .A0(n5721), .A1(FPADDSUB_intDY_EWSW[7]), .B0(n971), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n5170) );
OAI22X1TS U6006 ( .A0(n5766), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n969), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n5171) );
OAI22X1TS U6007 ( .A0(n972), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n943), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n5172) );
NAND4XLTS U6008 ( .A(n5176), .B(n5175), .C(n5174), .D(n5173), .Y(n5177) );
NOR4X1TS U6009 ( .A(n5179), .B(n5178), .C(n941), .D(n5177), .Y(n5180) );
AOI22X1TS U6012 ( .A0(FPMULT_FSM_selector_C), .A1(n5185), .B0(n5184), .B1(
n5731), .Y(n5186) );
AOI22X1TS U6013 ( .A0(n5738), .A1(n937), .B0(n5187), .B1(n5186), .Y(n6068)
);
AOI22X1TS U6014 ( .A0(n1020), .A1(FPMULT_Add_result[8]), .B0(n5188), .B1(
FPMULT_Add_result[9]), .Y(n5193) );
AOI22X1TS U6015 ( .A0(n1044), .A1(n5191), .B0(n4053), .B1(n5190), .Y(n5192)
);
NAND2X1TS U6016 ( .A(n5193), .B(n5192), .Y(n6053) );
AOI22X1TS U6017 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n5194), .B1(n979),
.Y(n6048) );
XNOR2X1TS U6018 ( .A(Data_2[31]), .B(Data_1[31]), .Y(n5885) );
AOI32X1TS U6019 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n5196), .A2(n5732),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n5196), .Y(
FPSENCOS_data_out_LUT[4]) );
OAI22X1TS U6020 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n5383), .B0(
FPSENCOS_cont_iter_out[2]), .B1(n5384), .Y(FPSENCOS_data_out_LUT[25])
);
NOR4X1TS U6021 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n5203) );
NOR4X1TS U6022 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n5202) );
NOR4X1TS U6023 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n5200) );
NOR4X1TS U6024 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n5198) );
NOR4X1TS U6025 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n5197) );
AND4X1TS U6026 ( .A(n5200), .B(n5199), .C(n5198), .D(n5197), .Y(n5201) );
NOR4BX1TS U6027 ( .AN(n1028), .B(dataB[28]), .C(operation_reg_0_), .D(
dataB[23]), .Y(n5208) );
NOR4X1TS U6028 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n5207) );
NAND4XLTS U6029 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n5205) );
NAND4XLTS U6030 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n5204) );
OR3X1TS U6031 ( .A(n6010), .B(n5205), .C(n5204), .Y(n5209) );
NOR4X1TS U6032 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n5212) );
NOR4X1TS U6033 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n5211) );
NOR4BX1TS U6034 ( .AN(n1028), .B(dataA[31]), .C(operation_reg_0_), .D(n6010),
.Y(n5210) );
NOR2X1TS U6035 ( .A(n1028), .B(n5209), .Y(n5217) );
NAND4XLTS U6036 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n5213) );
OAI31X1TS U6037 ( .A0(n5215), .A1(n5214), .A2(n5213), .B0(dataB[27]), .Y(
n5216) );
OAI2BB2XLTS U6038 ( .B0(n5219), .B1(n5218), .A0N(n5217), .A1N(
operation_reg_0_), .Y(NaN_reg) );
XOR2X1TS U6039 ( .A(n1193), .B(n5220), .Y(n5221) );
AOI22X1TS U6040 ( .A0(n5266), .A1(FPSENCOS_d_ff_Yn[31]), .B0(
FPSENCOS_d_ff_Xn[31]), .B1(n5270), .Y(n5224) );
XNOR2X1TS U6041 ( .A(n5224), .B(n5223), .Y(FPSENCOS_fmtted_Result_31_) );
AOI22X1TS U6042 ( .A0(n5245), .A1(n5824), .B0(n983), .B1(n5239), .Y(
FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U6043 ( .A0(n5245), .A1(n5821), .B0(n945), .B1(n5239), .Y(
FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U6044 ( .A0(n5245), .A1(n5809), .B0(n970), .B1(n5239), .Y(
FPADDSUB_DmP_INIT_EWSW[2]) );
AOI22X1TS U6045 ( .A0(n5245), .A1(n5823), .B0(n942), .B1(n5239), .Y(
FPADDSUB_DmP_INIT_EWSW[3]) );
AOI22X1TS U6046 ( .A0(n5245), .A1(n5807), .B0(n5230), .B1(n5239), .Y(
FPADDSUB_DmP_INIT_EWSW[4]) );
AOI22X1TS U6047 ( .A0(n5245), .A1(n5792), .B0(n5231), .B1(n5239), .Y(
FPADDSUB_DmP_INIT_EWSW[5]) );
AOI22X1TS U6048 ( .A0(n5227), .A1(n5805), .B0(n5232), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U6049 ( .A0(n5227), .A1(n5791), .B0(n5235), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U6050 ( .A0(n5227), .A1(n5819), .B0(n925), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U6051 ( .A0(n5227), .A1(n5811), .B0(n971), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U6052 ( .A0(n5227), .A1(n5804), .B0(n5225), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U6053 ( .A0(n5227), .A1(n5815), .B0(n969), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U6054 ( .A0(n5227), .A1(n5767), .B0(n5803), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[12]) );
AOI22X1TS U6055 ( .A0(n5227), .A1(n5808), .B0(n943), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U6056 ( .A0(n5227), .A1(n5723), .B0(n5780), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U6057 ( .A0(n5227), .A1(n5816), .B0(n972), .B1(n5226), .Y(
FPADDSUB_DmP_INIT_EWSW[15]) );
AOI22X1TS U6058 ( .A0(n5229), .A1(n5806), .B0(n5237), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[16]) );
AOI22X1TS U6059 ( .A0(n5229), .A1(n5817), .B0(n977), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U6060 ( .A0(n5229), .A1(n5820), .B0(n980), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U6061 ( .A0(n5229), .A1(n5725), .B0(n940), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U6062 ( .A0(n5229), .A1(n5814), .B0(n981), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U6063 ( .A0(n5229), .A1(n5813), .B0(n973), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U6064 ( .A0(n5229), .A1(n5726), .B0(n946), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U6065 ( .A0(n5229), .A1(n5830), .B0(n5779), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U6066 ( .A0(n5229), .A1(n5810), .B0(n982), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U6067 ( .A0(n5229), .A1(n5818), .B0(n944), .B1(n5228), .Y(
FPADDSUB_DmP_INIT_EWSW[25]) );
AOI22X1TS U6068 ( .A0(n5241), .A1(n5822), .B0(n978), .B1(n5234), .Y(
FPADDSUB_DmP_INIT_EWSW[26]) );
AOI22X1TS U6069 ( .A0(n5241), .A1(n5812), .B0(n966), .B1(n5234), .Y(
FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U6070 ( .A0(n5241), .A1(n983), .B0(n5824), .B1(n5234), .Y(
FPADDSUB_DMP_INIT_EWSW[0]) );
AOI22X1TS U6071 ( .A0(n5241), .A1(n945), .B0(n5821), .B1(n5234), .Y(
FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U6072 ( .A0(n5241), .A1(n970), .B0(n5809), .B1(n5234), .Y(
FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U6073 ( .A0(n5241), .A1(n942), .B0(n5823), .B1(n5234), .Y(
FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U6074 ( .A0(n5241), .A1(n5230), .B0(n5807), .B1(n5234), .Y(
FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U6075 ( .A0(n5241), .A1(n5231), .B0(n5792), .B1(n5234), .Y(
FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U6076 ( .A0(n5241), .A1(n5232), .B0(n5805), .B1(n5234), .Y(
FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U6077 ( .A0(n5238), .A1(n5235), .B0(n5791), .B1(n5234), .Y(
FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U6078 ( .A0(n5238), .A1(n925), .B0(n5819), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U6079 ( .A0(n5238), .A1(n971), .B0(n5811), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U6080 ( .A0(n5238), .A1(n5766), .B0(n5804), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U6081 ( .A0(n5238), .A1(n969), .B0(n5815), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U6082 ( .A0(n5238), .A1(n5803), .B0(n5236), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U6083 ( .A0(n5238), .A1(n943), .B0(n5808), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[13]) );
AOI22X1TS U6084 ( .A0(n5238), .A1(n5780), .B0(n5723), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[14]) );
AOI22X1TS U6085 ( .A0(n5238), .A1(n972), .B0(n5816), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U6086 ( .A0(n5238), .A1(n5237), .B0(n5806), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U6087 ( .A0(n5243), .A1(n977), .B0(n5817), .B1(n5240), .Y(
FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U6088 ( .A0(n5243), .A1(n980), .B0(n5820), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U6089 ( .A0(n5241), .A1(n940), .B0(n5725), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U6090 ( .A0(n5243), .A1(n981), .B0(n5814), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U6091 ( .A0(n5243), .A1(n973), .B0(n5813), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U6092 ( .A0(n5243), .A1(n946), .B0(n5726), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U6093 ( .A0(n5243), .A1(n5779), .B0(n5830), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U6094 ( .A0(n5243), .A1(n982), .B0(n5810), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U6095 ( .A0(n5243), .A1(n944), .B0(n5818), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U6096 ( .A0(n5243), .A1(n978), .B0(n5822), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U6097 ( .A0(n5243), .A1(n966), .B0(n5812), .B1(n5242), .Y(
FPADDSUB_DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U6098 ( .B0(n5245), .B1(n5781), .A0N(n5245), .A1N(
FPADDSUB_intDX_EWSW[28]), .Y(FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U6099 ( .B0(n5245), .B1(n5244), .A0N(n5148), .A1N(
FPADDSUB_intDX_EWSW[29]), .Y(FPADDSUB_DMP_INIT_EWSW[29]) );
OAI22X1TS U6100 ( .A0(n5747), .A1(n4373), .B0(n6014), .B1(n6027), .Y(
FPADDSUB_Data_array_SWR[0]) );
AOI22X1TS U6101 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n5302), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n5247), .Y(n5249) );
OAI2BB1X1TS U6102 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1N(n5958), .B0(
n5249), .Y(n6023) );
NAND2X1TS U6103 ( .A(n5274), .B(n5283), .Y(FPSENCOS_enab_d_ff5_data_out) );
AND2X2TS U6104 ( .A(n992), .B(FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
FPADDSUB_formatted_number_W[0]) );
AND2X2TS U6105 ( .A(n992), .B(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
FPADDSUB_formatted_number_W[1]) );
AND2X2TS U6106 ( .A(n991), .B(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
FPADDSUB_formatted_number_W[3]) );
AND2X2TS U6107 ( .A(n992), .B(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
FPADDSUB_formatted_number_W[7]) );
AND2X2TS U6108 ( .A(n992), .B(n5751), .Y(FPADDSUB_formatted_number_W[10]) );
AND2X2TS U6109 ( .A(n991), .B(n5750), .Y(FPADDSUB_formatted_number_W[11]) );
AND2X2TS U6110 ( .A(n991), .B(n5748), .Y(FPADDSUB_formatted_number_W[13]) );
AND2X2TS U6111 ( .A(n991), .B(FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
FPADDSUB_formatted_number_W[14]) );
AND2X2TS U6112 ( .A(n991), .B(FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
FPADDSUB_formatted_number_W[15]) );
AND2X2TS U6113 ( .A(n991), .B(FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
FPADDSUB_formatted_number_W[16]) );
AND2X2TS U6114 ( .A(n991), .B(FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
FPADDSUB_formatted_number_W[17]) );
AND2X2TS U6115 ( .A(n992), .B(FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
FPADDSUB_formatted_number_W[18]) );
AND2X2TS U6116 ( .A(n992), .B(FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
FPADDSUB_formatted_number_W[19]) );
AND2X2TS U6117 ( .A(n992), .B(FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
FPADDSUB_formatted_number_W[20]) );
AND2X2TS U6118 ( .A(n992), .B(FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
FPADDSUB_formatted_number_W[21]) );
AND2X2TS U6119 ( .A(n991), .B(FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
FPADDSUB_formatted_number_W[22]) );
CLKAND2X2TS U6120 ( .A(n5251), .B(FPMULT_Sgf_normalized_result[0]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]) );
BUFX3TS U6121 ( .A(n5251), .Y(n5250) );
CLKAND2X2TS U6122 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[1]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]) );
CLKAND2X2TS U6123 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[2]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]) );
CLKAND2X2TS U6124 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[3]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]) );
CLKAND2X2TS U6125 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[4]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]) );
CLKAND2X2TS U6126 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[5]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]) );
CLKAND2X2TS U6127 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[6]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]) );
CLKAND2X2TS U6128 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[7]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]) );
CLKAND2X2TS U6129 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[8]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]) );
CLKAND2X2TS U6130 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[9]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]) );
CLKAND2X2TS U6131 ( .A(n5250), .B(FPMULT_Sgf_normalized_result[10]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]) );
BUFX3TS U6132 ( .A(n5251), .Y(n5252) );
CLKAND2X2TS U6133 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[11]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]) );
CLKAND2X2TS U6134 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[12]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]) );
CLKAND2X2TS U6135 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[13]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]) );
CLKAND2X2TS U6136 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[14]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]) );
CLKAND2X2TS U6137 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[15]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]) );
CLKAND2X2TS U6138 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[16]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]) );
CLKAND2X2TS U6139 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[17]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]) );
CLKAND2X2TS U6140 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[18]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]) );
CLKAND2X2TS U6141 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[19]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]) );
CLKAND2X2TS U6142 ( .A(n5252), .B(FPMULT_Sgf_normalized_result[20]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]) );
CLKAND2X2TS U6143 ( .A(n5253), .B(FPMULT_Sgf_normalized_result[21]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]) );
CLKAND2X2TS U6144 ( .A(n5253), .B(FPMULT_Sgf_normalized_result[22]), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]) );
NOR2BX1TS U6145 ( .AN(FPSENCOS_d_ff_Xn[0]), .B(n5255), .Y(
FPSENCOS_first_mux_X[0]) );
NOR2BX1TS U6146 ( .AN(FPSENCOS_d_ff_Xn[4]), .B(n5255), .Y(
FPSENCOS_first_mux_X[4]) );
NOR2BX1TS U6147 ( .AN(FPSENCOS_d_ff_Xn[8]), .B(n5255), .Y(
FPSENCOS_first_mux_X[8]) );
NOR2BX1TS U6148 ( .AN(FPSENCOS_d_ff_Xn[9]), .B(n5255), .Y(
FPSENCOS_first_mux_X[9]) );
NOR2BX1TS U6149 ( .AN(FPSENCOS_d_ff_Xn[11]), .B(n5255), .Y(
FPSENCOS_first_mux_X[11]) );
NOR2BX1TS U6150 ( .AN(FPSENCOS_d_ff_Xn[15]), .B(n5254), .Y(
FPSENCOS_first_mux_X[15]) );
NOR2BX1TS U6151 ( .AN(FPSENCOS_d_ff_Xn[18]), .B(n5262), .Y(
FPSENCOS_first_mux_X[18]) );
NOR2BX1TS U6152 ( .AN(FPSENCOS_d_ff_Xn[21]), .B(n5265), .Y(
FPSENCOS_first_mux_X[21]) );
NOR2BX1TS U6153 ( .AN(FPSENCOS_d_ff_Xn[22]), .B(n5255), .Y(
FPSENCOS_first_mux_X[22]) );
NOR2BX1TS U6154 ( .AN(FPSENCOS_d_ff_Xn[23]), .B(n5255), .Y(
FPSENCOS_first_mux_X[23]) );
NOR2BX1TS U6155 ( .AN(FPSENCOS_d_ff_Xn[30]), .B(n5262), .Y(
FPSENCOS_first_mux_X[30]) );
INVX2TS U6156 ( .A(n5264), .Y(n5256) );
NOR2BX1TS U6157 ( .AN(FPSENCOS_d_ff_Xn[31]), .B(n5265), .Y(
FPSENCOS_first_mux_X[31]) );
NOR2BX1TS U6158 ( .AN(FPSENCOS_d_ff_Yn[0]), .B(n5263), .Y(
FPSENCOS_first_mux_Y[0]) );
NOR2BX1TS U6159 ( .AN(FPSENCOS_d_ff_Yn[1]), .B(n5254), .Y(
FPSENCOS_first_mux_Y[1]) );
NOR2BX1TS U6160 ( .AN(FPSENCOS_d_ff_Yn[2]), .B(n5262), .Y(
FPSENCOS_first_mux_Y[2]) );
NOR2BX1TS U6161 ( .AN(FPSENCOS_d_ff_Yn[3]), .B(n5263), .Y(
FPSENCOS_first_mux_Y[3]) );
NOR2BX1TS U6162 ( .AN(FPSENCOS_d_ff_Yn[4]), .B(n5265), .Y(
FPSENCOS_first_mux_Y[4]) );
NOR2BX1TS U6163 ( .AN(FPSENCOS_d_ff_Yn[5]), .B(n5254), .Y(
FPSENCOS_first_mux_Y[5]) );
NOR2BX1TS U6164 ( .AN(FPSENCOS_d_ff_Yn[6]), .B(n5255), .Y(
FPSENCOS_first_mux_Y[6]) );
NOR2BX1TS U6165 ( .AN(FPSENCOS_d_ff_Yn[7]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[7]) );
NOR2BX1TS U6166 ( .AN(FPSENCOS_d_ff_Yn[8]), .B(n5263), .Y(
FPSENCOS_first_mux_Y[8]) );
NOR2BX1TS U6167 ( .AN(FPSENCOS_d_ff_Yn[9]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[9]) );
NOR2BX1TS U6168 ( .AN(FPSENCOS_d_ff_Yn[10]), .B(n5255), .Y(
FPSENCOS_first_mux_Y[10]) );
NOR2BX1TS U6169 ( .AN(FPSENCOS_d_ff_Yn[11]), .B(n5262), .Y(
FPSENCOS_first_mux_Y[11]) );
NOR2BX1TS U6170 ( .AN(FPSENCOS_d_ff_Yn[12]), .B(n5265), .Y(
FPSENCOS_first_mux_Y[12]) );
NOR2BX1TS U6171 ( .AN(FPSENCOS_d_ff_Yn[13]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[13]) );
NOR2BX1TS U6172 ( .AN(FPSENCOS_d_ff_Yn[14]), .B(n5263), .Y(
FPSENCOS_first_mux_Y[14]) );
NOR2BX1TS U6173 ( .AN(FPSENCOS_d_ff_Yn[15]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[15]) );
NOR2BX1TS U6174 ( .AN(FPSENCOS_d_ff_Yn[16]), .B(n5254), .Y(
FPSENCOS_first_mux_Y[16]) );
NOR2BX1TS U6175 ( .AN(FPSENCOS_d_ff_Yn[17]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[17]) );
NOR2BX1TS U6176 ( .AN(FPSENCOS_d_ff_Yn[18]), .B(n5262), .Y(
FPSENCOS_first_mux_Y[18]) );
NOR2BX1TS U6177 ( .AN(FPSENCOS_d_ff_Yn[19]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[19]) );
NOR2BX1TS U6178 ( .AN(FPSENCOS_d_ff_Yn[20]), .B(n5265), .Y(
FPSENCOS_first_mux_Y[20]) );
NOR2BX1TS U6179 ( .AN(FPSENCOS_d_ff_Yn[21]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[21]) );
NOR2BX1TS U6180 ( .AN(FPSENCOS_d_ff_Yn[22]), .B(n5263), .Y(
FPSENCOS_first_mux_Y[22]) );
NOR2BX1TS U6181 ( .AN(FPSENCOS_d_ff_Yn[23]), .B(n5255), .Y(
FPSENCOS_first_mux_Y[23]) );
NOR2BX1TS U6182 ( .AN(FPSENCOS_d_ff_Yn[24]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[24]) );
NOR2BX1TS U6183 ( .AN(FPSENCOS_d_ff_Yn[25]), .B(n5262), .Y(
FPSENCOS_first_mux_Y[25]) );
NOR2BX1TS U6184 ( .AN(FPSENCOS_d_ff_Yn[26]), .B(n5254), .Y(
FPSENCOS_first_mux_Y[26]) );
NOR2BX1TS U6185 ( .AN(FPSENCOS_d_ff_Yn[27]), .B(n5265), .Y(
FPSENCOS_first_mux_Y[27]) );
NOR2BX1TS U6186 ( .AN(FPSENCOS_d_ff_Yn[28]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[28]) );
NOR2BX1TS U6187 ( .AN(FPSENCOS_d_ff_Yn[29]), .B(n5263), .Y(
FPSENCOS_first_mux_Y[29]) );
NOR2BX1TS U6188 ( .AN(FPSENCOS_d_ff_Yn[30]), .B(n5257), .Y(
FPSENCOS_first_mux_Y[30]) );
NOR2BX1TS U6189 ( .AN(FPSENCOS_d_ff_Yn[31]), .B(n5254), .Y(
FPSENCOS_first_mux_Y[31]) );
BUFX3TS U6190 ( .A(n5264), .Y(n5260) );
BUFX3TS U6191 ( .A(n5264), .Y(n5261) );
BUFX3TS U6192 ( .A(n5272), .Y(n5267) );
INVX2TS U6193 ( .A(n5269), .Y(n5273) );
AOI21X1TS U6194 ( .A0(n1016), .A1(ack_operation), .B0(n5274), .Y(n5284) );
NOR3X1TS U6195 ( .A(FPSENCOS_enab_RB3), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .C(FPSENCOS_enab_d_ff_RB1),
.Y(n5275) );
NOR2BX1TS U6196 ( .AN(begin_operation), .B(n5338), .Y(n5279) );
OAI22X1TS U6197 ( .A0(n5284), .A1(n5277), .B0(n5279), .B1(n5278), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U6198 ( .AN(n5279), .B(n5278), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U6199 ( .A0(FPSENCOS_enab_d_ff4_Zn), .A1(n5282), .B0(n5281), .B1(
n5280), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U6200 ( .AN(FPSENCOS_enab_d_ff4_Zn), .B(n5282), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
AOI22X1TS U6201 ( .A0(FPSENCOS_d_ff3_sh_x_out[9]), .A1(n5379), .B0(Data_2[9]), .B1(n5290), .Y(n5287) );
AOI22X1TS U6202 ( .A0(n5285), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n5331),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n5286) );
NAND2X1TS U6203 ( .A(n5287), .B(n5286), .Y(add_subt_data2[9]) );
BUFX3TS U6204 ( .A(n5290), .Y(n5314) );
AOI22X1TS U6205 ( .A0(FPSENCOS_d_ff3_sh_x_out[21]), .A1(n5379), .B0(
Data_2[21]), .B1(n5314), .Y(n5289) );
AOI22X1TS U6206 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n5307),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n5288) );
NAND2X1TS U6207 ( .A(n5289), .B(n5288), .Y(add_subt_data2[21]) );
AOI22X1TS U6208 ( .A0(FPSENCOS_d_ff3_sh_x_out[23]), .A1(n5379), .B0(
Data_2[23]), .B1(n5290), .Y(n5293) );
AOI22X1TS U6209 ( .A0(n5291), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n5307),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n5292) );
NAND2X1TS U6210 ( .A(n5293), .B(n5292), .Y(add_subt_data2[23]) );
AOI22X1TS U6211 ( .A0(FPSENCOS_d_ff3_sh_x_out[24]), .A1(n5379), .B0(
Data_2[24]), .B1(n5314), .Y(n5295) );
AOI22X1TS U6212 ( .A0(n5369), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n5307),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n5294) );
NAND2X1TS U6213 ( .A(n5295), .B(n5294), .Y(add_subt_data2[24]) );
AOI22X1TS U6214 ( .A0(FPSENCOS_d_ff3_sh_x_out[25]), .A1(n5379), .B0(
Data_2[25]), .B1(n5314), .Y(n5297) );
AOI22X1TS U6215 ( .A0(n5369), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n5307),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n5296) );
NAND2X1TS U6216 ( .A(n5297), .B(n5296), .Y(add_subt_data2[25]) );
AOI22X1TS U6217 ( .A0(FPSENCOS_d_ff3_sh_x_out[26]), .A1(n5379), .B0(
Data_2[26]), .B1(n5314), .Y(n5299) );
AOI22X1TS U6218 ( .A0(n5077), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n5307),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n5298) );
NAND2X1TS U6219 ( .A(n5299), .B(n5298), .Y(add_subt_data2[26]) );
INVX2TS U6220 ( .A(operation[2]), .Y(n5301) );
AOI22X1TS U6221 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n5379), .B0(Data_1[0]), .B1(
n5314), .Y(n5304) );
AOI22X1TS U6222 ( .A0(n5077), .A1(FPSENCOS_d_ff2_X[0]), .B0(n5307), .B1(
FPSENCOS_d_ff2_Z[0]), .Y(n5303) );
NAND2X1TS U6223 ( .A(n5304), .B(n5303), .Y(add_subt_data1[0]) );
AOI22X1TS U6224 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n5379), .B0(Data_1[1]), .B1(
n5314), .Y(n5306) );
AOI22X1TS U6225 ( .A0(n5077), .A1(FPSENCOS_d_ff2_X[1]), .B0(n5307), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n5305) );
NAND2X1TS U6226 ( .A(n5306), .B(n5305), .Y(add_subt_data1[1]) );
AOI22X1TS U6227 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n5327), .B0(Data_1[2]), .B1(
n5314), .Y(n5309) );
AOI22X1TS U6228 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[2]), .B0(n5307), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n5308) );
NAND2X1TS U6229 ( .A(n5309), .B(n5308), .Y(add_subt_data1[2]) );
AOI22X1TS U6230 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n5327), .B0(Data_1[3]), .B1(
n5314), .Y(n5311) );
AOI22X1TS U6231 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[3]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n5310) );
NAND2X1TS U6232 ( .A(n5311), .B(n5310), .Y(add_subt_data1[3]) );
AOI22X1TS U6233 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n5327), .B0(Data_1[4]), .B1(
n5314), .Y(n5313) );
AOI22X1TS U6234 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[4]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n5312) );
NAND2X1TS U6235 ( .A(n5313), .B(n5312), .Y(add_subt_data1[4]) );
AOI22X1TS U6236 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n5327), .B0(Data_1[5]), .B1(
n5314), .Y(n5316) );
AOI22X1TS U6237 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[5]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n5315) );
NAND2X1TS U6238 ( .A(n5316), .B(n5315), .Y(add_subt_data1[5]) );
BUFX3TS U6239 ( .A(n5338), .Y(n5347) );
AOI22X1TS U6240 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n5327), .B0(Data_1[6]), .B1(
n5347), .Y(n5318) );
AOI22X1TS U6241 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[6]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n5317) );
NAND2X1TS U6242 ( .A(n5318), .B(n5317), .Y(add_subt_data1[6]) );
AOI22X1TS U6243 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n5327), .B0(Data_1[7]), .B1(
n5347), .Y(n5320) );
AOI22X1TS U6244 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[7]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n5319) );
NAND2X1TS U6245 ( .A(n5320), .B(n5319), .Y(add_subt_data1[7]) );
AOI22X1TS U6246 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n5327), .B0(Data_1[8]), .B1(
n5347), .Y(n5322) );
AOI22X1TS U6247 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[8]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n5321) );
NAND2X1TS U6248 ( .A(n5322), .B(n5321), .Y(add_subt_data1[8]) );
AOI22X1TS U6249 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n5327), .B0(Data_1[9]), .B1(
n5347), .Y(n5324) );
AOI22X1TS U6250 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[9]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n5323) );
NAND2X1TS U6251 ( .A(n5324), .B(n5323), .Y(add_subt_data1[9]) );
AOI22X1TS U6252 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n5327), .B0(Data_1[10]),
.B1(n5347), .Y(n5326) );
AOI22X1TS U6253 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[10]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n5325) );
NAND2X1TS U6254 ( .A(n5326), .B(n5325), .Y(add_subt_data1[10]) );
AOI22X1TS U6255 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n5327), .B0(Data_1[11]),
.B1(n5347), .Y(n5330) );
AOI22X1TS U6256 ( .A0(n5328), .A1(FPSENCOS_d_ff2_X[11]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n5329) );
NAND2X1TS U6257 ( .A(n5330), .B(n5329), .Y(add_subt_data1[11]) );
BUFX3TS U6258 ( .A(n4517), .Y(n5352) );
AOI22X1TS U6259 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n5352), .B0(Data_1[12]),
.B1(n5347), .Y(n5333) );
AOI22X1TS U6260 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[12]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n5332) );
NAND2X1TS U6261 ( .A(n5333), .B(n5332), .Y(add_subt_data1[12]) );
AOI22X1TS U6262 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n5352), .B0(Data_1[13]),
.B1(n5347), .Y(n5335) );
AOI22X1TS U6263 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[13]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n5334) );
NAND2X1TS U6264 ( .A(n5335), .B(n5334), .Y(add_subt_data1[13]) );
AOI22X1TS U6265 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n5352), .B0(Data_1[14]),
.B1(n5347), .Y(n5337) );
AOI22X1TS U6266 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[14]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n5336) );
NAND2X1TS U6267 ( .A(n5337), .B(n5336), .Y(add_subt_data1[14]) );
AOI22X1TS U6268 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n5352), .B0(Data_1[15]),
.B1(n1015), .Y(n5340) );
AOI22X1TS U6269 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[15]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n5339) );
NAND2X1TS U6270 ( .A(n5340), .B(n5339), .Y(add_subt_data1[15]) );
AOI22X1TS U6271 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n5352), .B0(Data_1[16]),
.B1(n1015), .Y(n5342) );
AOI22X1TS U6272 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[16]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n5341) );
NAND2X1TS U6273 ( .A(n5342), .B(n5341), .Y(add_subt_data1[16]) );
AOI22X1TS U6274 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n5352), .B0(Data_1[17]),
.B1(n1015), .Y(n5344) );
AOI22X1TS U6275 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[17]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n5343) );
NAND2X1TS U6276 ( .A(n5344), .B(n5343), .Y(add_subt_data1[17]) );
AOI22X1TS U6277 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n5352), .B0(Data_1[18]),
.B1(n1015), .Y(n5346) );
AOI22X1TS U6278 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[18]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n5345) );
NAND2X1TS U6279 ( .A(n5346), .B(n5345), .Y(add_subt_data1[18]) );
AOI22X1TS U6280 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n5352), .B0(Data_1[19]),
.B1(n5347), .Y(n5349) );
AOI22X1TS U6281 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[19]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n5348) );
NAND2X1TS U6282 ( .A(n5349), .B(n5348), .Y(add_subt_data1[19]) );
AOI22X1TS U6283 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n5352), .B0(Data_1[20]),
.B1(n1015), .Y(n5351) );
AOI22X1TS U6284 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[20]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n5350) );
NAND2X1TS U6285 ( .A(n5351), .B(n5350), .Y(add_subt_data1[20]) );
AOI22X1TS U6286 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n5352), .B0(Data_1[21]),
.B1(n1015), .Y(n5356) );
AOI22X1TS U6287 ( .A0(n5354), .A1(FPSENCOS_d_ff2_X[21]), .B0(n5353), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n5355) );
NAND2X1TS U6288 ( .A(n5356), .B(n5355), .Y(add_subt_data1[21]) );
AOI22X1TS U6289 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n5375), .B0(Data_1[22]),
.B1(n1015), .Y(n5358) );
AOI22X1TS U6290 ( .A0(n5369), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4570), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n5357) );
NAND2X1TS U6291 ( .A(n5358), .B(n5357), .Y(add_subt_data1[22]) );
AOI22X1TS U6292 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n5375), .B0(Data_1[23]),
.B1(n5338), .Y(n5360) );
AOI22X1TS U6293 ( .A0(n5077), .A1(FPSENCOS_d_ff2_X[23]), .B0(n5331), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n5359) );
NAND2X1TS U6294 ( .A(n5360), .B(n5359), .Y(add_subt_data1[23]) );
AOI22X1TS U6295 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n5375), .B0(Data_1[24]),
.B1(n5338), .Y(n5362) );
AOI22X1TS U6296 ( .A0(n5369), .A1(FPSENCOS_d_ff2_X[24]), .B0(n4396), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n5361) );
NAND2X1TS U6297 ( .A(n5362), .B(n5361), .Y(add_subt_data1[24]) );
AOI22X1TS U6298 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n5375), .B0(Data_1[25]),
.B1(n4395), .Y(n5364) );
AOI22X1TS U6299 ( .A0(n5369), .A1(FPSENCOS_d_ff2_X[25]), .B0(n4396), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n5363) );
NAND2X1TS U6300 ( .A(n5364), .B(n5363), .Y(add_subt_data1[25]) );
AOI22X1TS U6301 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n5375), .B0(Data_1[26]),
.B1(n5378), .Y(n5366) );
AOI22X1TS U6302 ( .A0(n5369), .A1(FPSENCOS_d_ff2_X[26]), .B0(n4396), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n5365) );
NAND2X1TS U6303 ( .A(n5366), .B(n5365), .Y(add_subt_data1[26]) );
AOI22X1TS U6304 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n5375), .B0(Data_1[27]),
.B1(n5378), .Y(n5368) );
AOI22X1TS U6305 ( .A0(n5372), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4396), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n5367) );
NAND2X1TS U6306 ( .A(n5368), .B(n5367), .Y(add_subt_data1[27]) );
AOI22X1TS U6307 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n5375), .B0(Data_1[28]),
.B1(n5378), .Y(n5371) );
AOI22X1TS U6308 ( .A0(n5369), .A1(FPSENCOS_d_ff2_X[28]), .B0(n4396), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n5370) );
NAND2X1TS U6309 ( .A(n5371), .B(n5370), .Y(add_subt_data1[28]) );
AOI22X1TS U6310 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n5375), .B0(Data_1[29]),
.B1(n5378), .Y(n5374) );
AOI22X1TS U6311 ( .A0(n5372), .A1(FPSENCOS_d_ff2_X[29]), .B0(n4570), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n5373) );
NAND2X1TS U6312 ( .A(n5374), .B(n5373), .Y(add_subt_data1[29]) );
AOI22X1TS U6313 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n5375), .B0(Data_1[30]),
.B1(n5378), .Y(n5377) );
AOI22X1TS U6314 ( .A0(n5077), .A1(FPSENCOS_d_ff2_X[30]), .B0(n4570), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n5376) );
NAND2X1TS U6315 ( .A(n5377), .B(n5376), .Y(add_subt_data1[30]) );
AOI22X1TS U6316 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n5379), .B0(Data_1[31]),
.B1(n5378), .Y(n5382) );
AOI22X1TS U6317 ( .A0(n5372), .A1(FPSENCOS_d_ff2_X[31]), .B0(n5380), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n5381) );
NAND2X1TS U6318 ( .A(n5382), .B(n5381), .Y(add_subt_data1[31]) );
OA21XLTS U6319 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n5384), .B0(n5383), .Y(
FPSENCOS_ITER_CONT_N4) );
AOI22X1TS U6320 ( .A0(n5395), .A1(cordic_result[31]), .B0(n5386), .B1(
mult_result[31]), .Y(n5385) );
OAI2BB1X1TS U6321 ( .A0N(n5427), .A1N(result_add_subt[31]), .B0(n5385), .Y(
op_result[31]) );
AOI22X1TS U6322 ( .A0(n5395), .A1(cordic_result[30]), .B0(n5397), .B1(
mult_result[30]), .Y(n5387) );
OAI2BB1X1TS U6323 ( .A0N(n4367), .A1N(result_add_subt[30]), .B0(n5387), .Y(
op_result[30]) );
AOI22X1TS U6324 ( .A0(n5395), .A1(cordic_result[29]), .B0(n5397), .B1(
mult_result[29]), .Y(n5388) );
OAI2BB1X1TS U6325 ( .A0N(n4367), .A1N(result_add_subt[29]), .B0(n5388), .Y(
op_result[29]) );
AOI22X1TS U6326 ( .A0(n5395), .A1(cordic_result[28]), .B0(n5397), .B1(
mult_result[28]), .Y(n5389) );
OAI2BB1X1TS U6327 ( .A0N(n4367), .A1N(result_add_subt[28]), .B0(n5389), .Y(
op_result[28]) );
AOI22X1TS U6328 ( .A0(n5395), .A1(cordic_result[27]), .B0(n5397), .B1(
mult_result[27]), .Y(n5390) );
OAI2BB1X1TS U6329 ( .A0N(n4367), .A1N(result_add_subt[27]), .B0(n5390), .Y(
op_result[27]) );
BUFX3TS U6330 ( .A(n4367), .Y(n5403) );
AOI22X1TS U6331 ( .A0(n5395), .A1(cordic_result[26]), .B0(n5397), .B1(
mult_result[26]), .Y(n5391) );
OAI2BB1X1TS U6332 ( .A0N(n5403), .A1N(result_add_subt[26]), .B0(n5391), .Y(
op_result[26]) );
AOI22X1TS U6333 ( .A0(n5395), .A1(cordic_result[25]), .B0(n5397), .B1(
mult_result[25]), .Y(n5392) );
OAI2BB1X1TS U6334 ( .A0N(n5403), .A1N(result_add_subt[25]), .B0(n5392), .Y(
op_result[25]) );
AOI22X1TS U6335 ( .A0(n5395), .A1(cordic_result[24]), .B0(n5397), .B1(
mult_result[24]), .Y(n5393) );
OAI2BB1X1TS U6336 ( .A0N(n5403), .A1N(result_add_subt[24]), .B0(n5393), .Y(
op_result[24]) );
AOI22X1TS U6337 ( .A0(n5395), .A1(cordic_result[23]), .B0(n5397), .B1(
mult_result[23]), .Y(n5394) );
OAI2BB1X1TS U6338 ( .A0N(n5403), .A1N(result_add_subt[23]), .B0(n5394), .Y(
op_result[23]) );
AOI22X1TS U6339 ( .A0(n5395), .A1(cordic_result[22]), .B0(n5397), .B1(
mult_result[22]), .Y(n5396) );
OAI2BB1X1TS U6340 ( .A0N(n5403), .A1N(result_add_subt[22]), .B0(n5396), .Y(
op_result[22]) );
AOI22X1TS U6341 ( .A0(n5407), .A1(cordic_result[21]), .B0(n5409), .B1(
mult_result[21]), .Y(n5398) );
OAI2BB1X1TS U6342 ( .A0N(n5403), .A1N(result_add_subt[21]), .B0(n5398), .Y(
op_result[21]) );
AOI22X1TS U6343 ( .A0(n5407), .A1(cordic_result[20]), .B0(n5409), .B1(
mult_result[20]), .Y(n5399) );
OAI2BB1X1TS U6344 ( .A0N(n5403), .A1N(result_add_subt[20]), .B0(n5399), .Y(
op_result[20]) );
AOI22X1TS U6345 ( .A0(n5407), .A1(cordic_result[19]), .B0(n5409), .B1(
mult_result[19]), .Y(n5400) );
OAI2BB1X1TS U6346 ( .A0N(n5403), .A1N(result_add_subt[19]), .B0(n5400), .Y(
op_result[19]) );
AOI22X1TS U6347 ( .A0(n5407), .A1(cordic_result[18]), .B0(n5409), .B1(
mult_result[18]), .Y(n5401) );
OAI2BB1X1TS U6348 ( .A0N(n5403), .A1N(result_add_subt[18]), .B0(n5401), .Y(
op_result[18]) );
AOI22X1TS U6349 ( .A0(n5407), .A1(cordic_result[17]), .B0(n5409), .B1(
mult_result[17]), .Y(n5402) );
OAI2BB1X1TS U6350 ( .A0N(n5403), .A1N(result_add_subt[17]), .B0(n5402), .Y(
op_result[17]) );
BUFX3TS U6351 ( .A(n4367), .Y(n5417) );
AOI22X1TS U6352 ( .A0(n5407), .A1(cordic_result[16]), .B0(n5409), .B1(
mult_result[16]), .Y(n5404) );
OAI2BB1X1TS U6353 ( .A0N(n5417), .A1N(result_add_subt[16]), .B0(n5404), .Y(
op_result[16]) );
AOI22X1TS U6354 ( .A0(n5407), .A1(cordic_result[15]), .B0(n5409), .B1(
mult_result[15]), .Y(n5405) );
OAI2BB1X1TS U6355 ( .A0N(n5417), .A1N(result_add_subt[15]), .B0(n5405), .Y(
op_result[15]) );
AOI22X1TS U6356 ( .A0(n5407), .A1(cordic_result[14]), .B0(n5409), .B1(
mult_result[14]), .Y(n5406) );
OAI2BB1X1TS U6357 ( .A0N(n5417), .A1N(result_add_subt[14]), .B0(n5406), .Y(
op_result[14]) );
AOI22X1TS U6358 ( .A0(n5407), .A1(cordic_result[13]), .B0(n5409), .B1(
mult_result[13]), .Y(n5408) );
OAI2BB1X1TS U6359 ( .A0N(n5417), .A1N(result_add_subt[13]), .B0(n5408), .Y(
op_result[13]) );
AOI22X1TS U6360 ( .A0(n5425), .A1(cordic_result[12]), .B0(n5409), .B1(
mult_result[12]), .Y(n5410) );
OAI2BB1X1TS U6361 ( .A0N(n5417), .A1N(result_add_subt[12]), .B0(n5410), .Y(
op_result[12]) );
AOI22X1TS U6362 ( .A0(n5421), .A1(cordic_result[11]), .B0(n5424), .B1(
mult_result[11]), .Y(n5411) );
OAI2BB1X1TS U6363 ( .A0N(n5417), .A1N(result_add_subt[11]), .B0(n5411), .Y(
op_result[11]) );
AOI22X1TS U6364 ( .A0(n5421), .A1(cordic_result[10]), .B0(n5424), .B1(
mult_result[10]), .Y(n5412) );
OAI2BB1X1TS U6365 ( .A0N(n5417), .A1N(result_add_subt[10]), .B0(n5412), .Y(
op_result[10]) );
AOI22X1TS U6366 ( .A0(n5421), .A1(cordic_result[9]), .B0(n5424), .B1(
mult_result[9]), .Y(n5413) );
OAI2BB1X1TS U6367 ( .A0N(n5417), .A1N(result_add_subt[9]), .B0(n5413), .Y(
op_result[9]) );
AOI22X1TS U6368 ( .A0(n5421), .A1(cordic_result[8]), .B0(n5424), .B1(
mult_result[8]), .Y(n5414) );
OAI2BB1X1TS U6369 ( .A0N(n5417), .A1N(result_add_subt[8]), .B0(n5414), .Y(
op_result[8]) );
AOI22X1TS U6370 ( .A0(n5421), .A1(cordic_result[7]), .B0(n5424), .B1(
mult_result[7]), .Y(n5415) );
OAI2BB1X1TS U6371 ( .A0N(n5427), .A1N(result_add_subt[7]), .B0(n5415), .Y(
op_result[7]) );
AOI22X1TS U6372 ( .A0(n5421), .A1(cordic_result[6]), .B0(n5424), .B1(
mult_result[6]), .Y(n5416) );
OAI2BB1X1TS U6373 ( .A0N(n5417), .A1N(result_add_subt[6]), .B0(n5416), .Y(
op_result[6]) );
AOI22X1TS U6374 ( .A0(n5421), .A1(cordic_result[5]), .B0(n5424), .B1(
mult_result[5]), .Y(n5418) );
OAI2BB1X1TS U6375 ( .A0N(n5427), .A1N(result_add_subt[5]), .B0(n5418), .Y(
op_result[5]) );
AOI22X1TS U6376 ( .A0(n5421), .A1(cordic_result[4]), .B0(n5386), .B1(
mult_result[4]), .Y(n5419) );
OAI2BB1X1TS U6377 ( .A0N(n5427), .A1N(result_add_subt[4]), .B0(n5419), .Y(
op_result[4]) );
AOI22X1TS U6378 ( .A0(n5421), .A1(cordic_result[3]), .B0(n5386), .B1(
mult_result[3]), .Y(n5420) );
OAI2BB1X1TS U6379 ( .A0N(n5427), .A1N(result_add_subt[3]), .B0(n5420), .Y(
op_result[3]) );
AOI22X1TS U6380 ( .A0(n5421), .A1(cordic_result[2]), .B0(n5386), .B1(
mult_result[2]), .Y(n5422) );
OAI2BB1X1TS U6381 ( .A0N(n5427), .A1N(result_add_subt[2]), .B0(n5422), .Y(
op_result[2]) );
AOI22X1TS U6382 ( .A0(n5425), .A1(cordic_result[1]), .B0(n5424), .B1(
mult_result[1]), .Y(n5423) );
OAI2BB1X1TS U6383 ( .A0N(n5427), .A1N(result_add_subt[1]), .B0(n5423), .Y(
op_result[1]) );
AOI22X1TS U6384 ( .A0(n5425), .A1(cordic_result[0]), .B0(n5424), .B1(
mult_result[0]), .Y(n5426) );
OAI2BB1X1TS U6385 ( .A0N(n5427), .A1N(result_add_subt[0]), .B0(n5426), .Y(
op_result[0]) );
AOI22X1TS U6386 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n5430), .B0(n5428),
.B1(n998), .Y(n861) );
AOI22X1TS U6387 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n5430), .B0(n5429),
.B1(n5732), .Y(n853) );
OAI2BB1X1TS U6388 ( .A0N(FPSENCOS_cont_iter_out[1]), .A1N(n851), .B0(n5431),
.Y(n852) );
AOI22X1TS U6389 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n5433), .B0(n5432),
.B1(n5732), .Y(n848) );
INVX2TS U6390 ( .A(n5438), .Y(n5434) );
AOI22X1TS U6391 ( .A0(ack_operation), .A1(n5954), .B0(begin_operation), .B1(
n5434), .Y(n5436) );
OAI22X1TS U6392 ( .A0(n5438), .A1(n5437), .B0(n5436), .B1(n5435), .Y(n846)
);
OAI22X1TS U6393 ( .A0(n5442), .A1(n5441), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n5440), .Y(n844) );
AOI22X1TS U6394 ( .A0(FPSENCOS_cont_var_out[0]), .A1(n5444), .B0(n5443),
.B1(n5730), .Y(n843) );
NOR4X1TS U6395 ( .A(FPMULT_Op_MY[24]), .B(FPMULT_Op_MY[25]), .C(
FPMULT_Op_MY[26]), .D(FPMULT_Op_MY[27]), .Y(n5446) );
NOR4X1TS U6396 ( .A(FPMULT_Op_MY[28]), .B(FPMULT_Op_MY[7]), .C(
FPMULT_Op_MY[29]), .D(FPMULT_Op_MY[30]), .Y(n5445) );
NAND4XLTS U6397 ( .A(n5956), .B(n5727), .C(n5446), .D(n5445), .Y(n5461) );
NOR4BBX1TS U6398 ( .AN(n5898), .BN(n5899), .C(DP_OP_496J311_122_3540_n1476),
.D(FPMULT_Op_MY[10]), .Y(n5448) );
NOR3BXLTS U6399 ( .AN(n5896), .B(DP_OP_496J311_122_3540_n1465), .C(
FPMULT_Op_MY[23]), .Y(n5447) );
NAND4XLTS U6400 ( .A(n5448), .B(n5893), .C(n5897), .D(n5447), .Y(n5460) );
NOR4BBX1TS U6401 ( .AN(n5900), .BN(n5901), .C(FPMULT_Op_MX[16]), .D(
DP_OP_498J311_124_1725_n802), .Y(n5453) );
NOR4X1TS U6402 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[0]), .C(
DP_OP_496J311_122_3540_n1509), .D(DP_OP_496J311_122_3540_n1138), .Y(
n5449) );
NOR4X1TS U6403 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_Op_MX[25]), .C(
FPMULT_Op_MX[26]), .D(FPMULT_Op_MX[27]), .Y(n5452) );
NAND4BBX1TS U6404 ( .AN(FPMULT_Op_MX[28]), .BN(DP_OP_496J311_122_3540_n1498),
.C(n5894), .D(n5895), .Y(n5450) );
INVX2TS U6405 ( .A(n5450), .Y(n5451) );
NAND4XLTS U6406 ( .A(n5453), .B(n5449), .C(n5452), .D(n5451), .Y(n5459) );
NAND4BXLTS U6407 ( .AN(n5454), .B(n5890), .C(n5891), .D(n5892), .Y(n5455) );
INVX2TS U6408 ( .A(n5455), .Y(n5457) );
NOR3XLTS U6409 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[21]), .C(
FPMULT_Op_MX[24]), .Y(n5456) );
NAND4XLTS U6410 ( .A(n5834), .B(n5957), .C(n5457), .D(n5456), .Y(n5458) );
OAI22X1TS U6411 ( .A0(n5461), .A1(n5460), .B0(n5459), .B1(n5458), .Y(n106)
);
XNOR2X1TS U6412 ( .A(FPADDSUB_intDX_EWSW[31]), .B(n6038), .Y(n30) );
NOR2BX1TS U6413 ( .AN(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(FPADDSUB__19_net_) );
XNOR2X1TS U6414 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n5464), .Y(
FPSENCOS_sh_exp_y[6]) );
XNOR2X1TS U6415 ( .A(FPSENCOS_d_ff2_X[29]), .B(n5467), .Y(
FPSENCOS_sh_exp_x[6]) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
|
//======================================================================
//
// m6502_decoder.v
// ---------------
// Instruction decode logic for the MOS 6502 compatible CPU core.
// Note: This is not going to be a cycle accurate model.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module m6502_decoder(
input wire [7 : 0] opcode,
output wire [2 : 0] instr_len,
output wire [2 : 0] opa,
output wire [2 : 0] opb,
output wire [2 : 0] alu_op,
output wire [2 : 0] destination,
output wire update_carry,
output wire update_zero,
output wire update_overflow
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// M6502 Opcodes:
localparam OP_BRK = 8'h00;
localparam OP_CLC = 8'h18;
localparam OP_SEC = 8'h38;
localparam OP_JMP = 8'h4c;
localparam OP_CLI = 8'h58;
localparam OP_RTS = 8'h60;
localparam OP_SEI = 8'h78;
localparam OP_TXA = 8'h8a;
localparam OP_LDA_IMM = 8'ha9;
localparam OP_TAX = 8'haa;
localparam OP_INY = 8'hc8;
localparam OP_DEX = 8'hca;
localparam OP_INX = 8'he8;
localparam OP_NOP = 8'hea;
// Symbolic names for ALU operands.
localparam OP_AREG = 3'h0;
localparam OP_XREG = 3'h1;
localparam OP_YREG = 3'h2;
localparam OP_ONE = 3'h7;
// Symbolic names for ALU operations.
localparam ALU_NONE = 3'h0;
localparam ALU_ADC = 3'h1;
// Symbolic names for destination codes.
localparam DEST_MEM = 3'h0;
localparam DEST_AREG = 3'h1;
localparam DEST_XREG = 3'h2;
localparam DEST_YREG = 3'h3;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [2 : 0] ilen;
reg [2 : 0] dest;
reg [2 : 0] alu;
reg [2 : 0] a;
reg [2 : 0] b;
reg carry;
reg zero;
reg overflow;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign instr_len = ilen;
assign destination = dest;
assign alu_op = alu;
assign opa = a;
assign opb = b;
assign update_carry = carry;
assign update_zero = zero;
assign update_overflow = overflow;
//----------------------------------------------------------------
// decoder
// Instruction decoder. Based on the opcode provides info about
// the operation to perform
//----------------------------------------------------------------
always @*
begin : decoder
ilen = 3'h0;
dest = DEST_MEM;
alu = ALU_NONE;
carry = 0;
zero = 0;
overflow = 0;
case (opcode)
OP_LDA_IMM:
begin
ilen = 3'h2;
dest = DEST_AREG;
alu = ALU_NONE;
end
OP_INY:
begin
ilen = 3'h1;
a = OP_YREG;
b = OP_ONE;
alu = ALU_ADC;
dest = DEST_YREG;
end
OP_INX:
begin
ilen = 3'h1;
a = OP_XREG;
b = OP_ONE;
alu = ALU_ADC;
dest = DEST_XREG;
end
default:
begin
end
endcase // case (opcode)
end // decoder
endmodule // 6502_decoder
//======================================================================
// EOF m6502_decoder.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__BUFBUF_PP_BLACKBOX_V
/**
* bufbuf: Double buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_PP_BLACKBOX_V
|
`timescale 1ns/1ns
module commutator
(input c,
input [15:0] menc_raw,
input [15:0] stator_offset,
input [31:0] amps_float, // float32 magnitude to modulate
output [47:0] current_targets);
wire [10:0] elec_angle_a, elec_angle_b, elec_angle_c;
d1 #(11) elec_angle_a_r
(.c(c), .d(menc_raw[10:0] + stator_offset[10:0] ), .q(elec_angle_a));
d1 #(11) elec_angle_b_r
(.c(c), .d(menc_raw[10:0] + stator_offset[10:0] + 11'd683 ), .q(elec_angle_b));
d1 #(11) elec_angle_c_r
(.c(c), .d(menc_raw[10:0] + stator_offset[10:0] + 11'd1365), .q(elec_angle_c));
// continually look these up and modulate them
wire [1:0] phase_idx;
d1 #(2) phase_idx_r
(.c(c), .d(phase_idx == 2'd2 ? 2'b0 : phase_idx+1'b1), .q(phase_idx));
wire [10:0] elec_angle_z;
gmux #(.DWIDTH(11), .SELWIDTH(2)) angle_mux
(.d({11'h0, elec_angle_c, elec_angle_b, elec_angle_a}),
.sel(phase_idx), .z(elec_angle_z));
wire [31:0] elec_angle_sine;
sine_table_11bit sine_inst
(.c(c), .angle(elec_angle_z), .sine(elec_angle_sine));
wire [31:0] target;
mult mult_inst
(.clock(c),
.dataa(elec_angle_sine),
.datab(amps_float),
.result(target));
wire [31:0] tgt_int32;
wire fpconv_nan;
fpconv fpconv_inst
(.clock(c), .dataa(target),
.nan(fpconv_nan),
.result(tgt_int32));
wire [15:0] tgt = tgt_int32[15:0] + 16'h4000;
wire [15:0] a_tgt, b_tgt, c_tgt;
r #(16) a_tgt_r
(.c(c), .rst(1'b0), .en(phase_idx == 2'h0), .d(tgt), .q(a_tgt));
r #(16) b_tgt_r
(.c(c), .rst(1'b0), .en(phase_idx == 2'h1), .d(tgt), .q(b_tgt));
r #(16) c_tgt_r
(.c(c), .rst(1'b0), .en(phase_idx == 2'h2), .d(tgt), .q(c_tgt));
assign current_targets = { c_tgt, b_tgt, a_tgt };
/*
wire [10:0] elec_angle;
r #(11) elec_angle_r
(.c(c), .rst(1'b0), .en(1'b1),
.d(menc_int32
*/
endmodule
`ifdef TEST_COMMUTATOR
module tb();
reg [15:0] menc_raw;
reg [15:0] stator_offset;
wire [47:0] current_targets;
wire [15:0] a_tgt = current_targets[15:0];
wire [15:0] b_tgt = current_targets[31:16];
wire [15:0] c_tgt = current_targets[47:32];
reg [31:0] amps_float;
wire c;
sim_clk #(125) clk_125(c);
commutator dut(.*);
initial begin
$dumpfile("commutator.lxt");
$dumpvars();
menc_raw = 16'd0;
stator_offset = 16'h0;
wait(~c);
wait(c);
wait(~c);
wait(c);
menc_raw = 16'd300;
amps_float = 32'h3f800000;
#200;
$finish();
end
endmodule
`endif
|
module c432_wrap(in,out,clk);
input [0:35] in;
output [0:6] out;
input clk;
DFFX1 in0 (.CLK(clk), .D(in[0]), .Q(N1));
DFFX1 in1 (.CLK(clk), .D(in[1]), .Q(N4));
DFFX1 in2 (.CLK(clk), .D(in[2]), .Q(N8));
DFFX1 in3 (.CLK(clk), .D(in[3]), .Q(N11));
DFFX1 in4 (.CLK(clk), .D(in[4]), .Q(N14));
DFFX1 in5 (.CLK(clk), .D(in[5]), .Q(N17));
DFFX1 in6 (.CLK(clk), .D(in[6]), .Q(N21));
DFFX1 in7 (.CLK(clk), .D(in[7]), .Q(N24));
DFFX1 in8 (.CLK(clk), .D(in[8]), .Q(N27));
DFFX1 in9 (.CLK(clk), .D(in[9]), .Q(N30));
DFFX1 in10 (.CLK(clk), .D(in[10]), .Q(N34));
DFFX1 in11 (.CLK(clk), .D(in[11]), .Q(N37));
DFFX1 in12 (.CLK(clk), .D(in[12]), .Q(N40));
DFFX1 in13 (.CLK(clk), .D(in[13]), .Q(N43));
DFFX1 in14 (.CLK(clk), .D(in[14]), .Q(N47));
DFFX1 in15 (.CLK(clk), .D(in[15]), .Q(N50));
DFFX1 in16 (.CLK(clk), .D(in[16]), .Q(N53));
DFFX1 in17 (.CLK(clk), .D(in[17]), .Q(N56));
DFFX1 in18 (.CLK(clk), .D(in[18]), .Q(N60));
DFFX1 in19 (.CLK(clk), .D(in[19]), .Q(N63));
DFFX1 in20 (.CLK(clk), .D(in[20]), .Q(N66));
DFFX1 in21 (.CLK(clk), .D(in[21]), .Q(N69));
DFFX1 in22 (.CLK(clk), .D(in[22]), .Q(N73));
DFFX1 in23 (.CLK(clk), .D(in[23]), .Q(N76));
DFFX1 in24 (.CLK(clk), .D(in[24]), .Q(N79));
DFFX1 in25 (.CLK(clk), .D(in[25]), .Q(N82));
DFFX1 in26 (.CLK(clk), .D(in[26]), .Q(N86));
DFFX1 in27 (.CLK(clk), .D(in[27]), .Q(N89));
DFFX1 in28 (.CLK(clk), .D(in[28]), .Q(N92));
DFFX1 in29 (.CLK(clk), .D(in[29]), .Q(N95));
DFFX1 in30 (.CLK(clk), .D(in[30]), .Q(N99));
DFFX1 in31 (.CLK(clk), .D(in[31]), .Q(N102));
DFFX1 in32 (.CLK(clk), .D(in[32]), .Q(N105));
DFFX1 in33 (.CLK(clk), .D(in[33]), .Q(N108));
DFFX1 in34 (.CLK(clk), .D(in[34]), .Q(N112));
DFFX1 in35 (.CLK(clk), .D(in[35]), .Q(N115));
c432 DUT ( N1, N4, N8, N11, N14, N17, N21, N24, N27, N30, N34, N37, N40,
N43, N47, N50, N53, N56, N60, N63, N66, N69, N73, N76, N79, N82, N86,
N89, N92, N95, N99, N102, N105, N108, N112, N115,
N223, N329, N370, N421, N430, N431, N432
);
DFFX1 out0 (.CLK(clk), .Q(out[0]), .D(N223));
DFFX1 out1 (.CLK(clk), .Q(out[1]), .D(N329));
DFFX1 out2 (.CLK(clk), .Q(out[2]), .D(N370));
DFFX1 out3 (.CLK(clk), .Q(out[3]), .D(N421));
DFFX1 out4 (.CLK(clk), .Q(out[4]), .D(N430));
DFFX1 out5 (.CLK(clk), .Q(out[5]), .D(N431));
DFFX1 out6 (.CLK(clk), .Q(out[6]), .D(N432));
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone master mem bus
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (DRT) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//audio buffer master bus
wire audio_we_o;
wire audio_cyc_o;
wire [31:0] audio_dat_o;
wire audio_stb_o;
wire [3:0] audio_sel_o;
wire audio_ack_i;
wire [31:0] audio_dat_i;
wire [31:0] audio_adr_o;
wire audio_int_i;
//wishbone slave 0 signals
wire mem0_we_o;
wire mem0_cyc_o;
wire [31:0] mem0_dat_o;
wire mem0_stb_o;
wire [3:0] mem0_sel_o;
wire mem0_ack_i;
wire [31:0] mem0_dat_i;
wire [31:0] mem0_adr_o;
wire mem0_int_i;
wire sdram_clk;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_ras;
wire sdram_cas;
wire sdram_we;
wire [11:0] sdram_addr;
wire [1:0] sdram_bank;
wire [15:0] sdram_data;
wire [1:0] sdram_data_mask;
wire sdram_ready;
reg [15:0] sdram_in_data;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 4'h0;
localparam IDLE = 4'h1;
localparam EXECUTE = 4'h2;
localparam RESET = 4'h3;
localparam PING_RESPONSE = 4'h4;
localparam WRITE_DATA = 4'h5;
localparam WRITE_RESPONSE = 4'h6;
localparam GET_WRITE_DATA = 4'h7;
localparam READ_RESPONSE = 4'h8;
localparam READ_MORE_DATA = 4'h9;
localparam FINISHED = 4'hA;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
wire lcd_mem_o_stb;
wire lcd_mem_o_cyc;
wire lcd_mem_o_we;
wire [3:0] lcd_mem_o_sel;
wire [31:0] lcd_mem_o_dat;
wire [31:0] lcd_mem_o_adr;
wire [31:0] lcd_mem_i_dat;
wire lcd_mem_i_ack;
wire lcd_mem_i_int;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
reg start = 0;
wire w_backlight_enable;
wire w_register_data_sel;
reg r_tearing_effect;
wire w_write_n;
wire w_read_n;
wire [7:0] w_data;
wire w_cs_n;
wire w_reset_n;
wire w_display_on;
reg [31:0] r_tear_count;
reg [7:0] r_tear_status;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
wb_nh_lcd s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int ),
.mem_o_cyc (lcd_mem_o_cyc ),
.mem_o_stb (lcd_mem_o_stb ),
.mem_o_we (lcd_mem_o_we ),
.mem_i_ack (lcd_mem_i_ack ),
.mem_o_sel (lcd_mem_o_sel ),
.mem_o_adr (lcd_mem_o_adr ),
.mem_o_dat (lcd_mem_o_dat ),
.mem_i_dat (lcd_mem_i_dat ),
.mem_i_int (lcd_mem_i_int ),
.o_backlight_enable (w_backlight_enable ),
.i_tearing_effect (r_tearing_effect ),
.o_register_data_sel (w_register_data_sel ),
.o_write_n (w_write_n ),
.o_read_n (w_read_n ),
.io_data (w_data ),
.o_cs_n (w_cs_n ),
.o_reset_n (w_reset_n ),
.o_display_on (w_display_on )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
mt48lc4m16
//#(
// tdevice_TRCD = 10
//)
ram (
.A11 (sdram_addr[11]),
.A10 (sdram_addr[10]),
.A9 (sdram_addr[9]),
.A8 (sdram_addr[8]),
.A7 (sdram_addr[7]),
.A6 (sdram_addr[6]),
.A5 (sdram_addr[5]),
.A4 (sdram_addr[4]),
.A3 (sdram_addr[3]),
.A2 (sdram_addr[2]),
.A1 (sdram_addr[1]),
.A0 (sdram_addr[0]),
.DQ15 (sdram_data[15]),
.DQ14 (sdram_data[14]),
.DQ13 (sdram_data[13]),
.DQ12 (sdram_data[12]),
.DQ11 (sdram_data[11]),
.DQ10 (sdram_data[10]),
.DQ9 (sdram_data[9]),
.DQ8 (sdram_data[8]),
.DQ7 (sdram_data[7]),
.DQ6 (sdram_data[6]),
.DQ5 (sdram_data[5]),
.DQ4 (sdram_data[4]),
.DQ3 (sdram_data[3]),
.DQ2 (sdram_data[2]),
.DQ1 (sdram_data[1]),
.DQ0 (sdram_data[0]),
.BA0 (sdram_bank[0]),
.BA1 (sdram_bank[1]),
.DQMH (sdram_data_mask[1]),
.DQML (sdram_data_mask[0]),
.CLK (sdram_clk),
.CKE (sdram_cke),
.WENeg (sdram_we),
.RASNeg (sdram_ras),
.CSNeg (sdram_cs_n),
.CASNeg (sdram_cas)
);
//mem 0
wb_sdram m0 (
.clk(clk),
.rst(rst),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int ),
.o_sdram_clk(sdram_clk ),
.o_sdram_cke(sdram_cke ),
.o_sdram_cs_n(sdram_cs_n ),
.o_sdram_ras(sdram_ras ),
.o_sdram_cas(sdram_cas ),
.o_sdram_we(sdram_we ),
.o_sdram_addr(sdram_addr ),
.o_sdram_bank(sdram_bank ),
.io_sdram_data(sdram_data ),
.o_sdram_data_mask(sdram_data_mask ),
.o_sdram_ready(sdram_ready)
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (rst ),
//masters
.i_m0_we (lcd_mem_o_we ),
.i_m0_stb (lcd_mem_o_stb ),
.i_m0_cyc (lcd_mem_o_cyc ),
.i_m0_sel (lcd_mem_o_sel ),
.i_m0_dat (lcd_mem_o_dat ),
.i_m0_adr (lcd_mem_o_adr ),
.o_m0_dat (lcd_mem_i_dat ),
.o_m0_ack (lcd_mem_i_ack ),
.o_m0_int (lcd_mem_i_int ),
.i_m1_we (w_sm0_i_wbs_we ),
.i_m1_stb (w_sm0_i_wbs_stb ),
.i_m1_cyc (w_sm0_i_wbs_cyc ),
.i_m1_sel (w_sm0_i_wbs_sel ),
.i_m1_dat (w_sm0_i_wbs_dat ),
.i_m1_adr (w_sm0_i_wbs_adr ),
.o_m1_dat (w_sm0_o_wbs_dat ),
.o_m1_ack (w_sm0_o_wbs_ack ),
.o_m1_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign w_data = (!w_read_n) ? r_tear_status: 8'hZZ;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
$display ("");
end
else begin
$display ("Error unrecognized line: %h" % ch);
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
$display ("Sleep for %h Clock cycles", r_in_data_count);
`SLEEP_CLK(r_in_data_count);
$display ("Sleep Finished");
end
else begin
$display ("Error: read_count = %h != 4", read_count);
$display ("Character: %h", ch);
end
end
else begin
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
$display ("TB: reading a new double word: %h", r_in_data);
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
execute_command <= 1;
end //while command is not finished
while (command_finished) begin
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
$display ("TB: finished command");
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
start <= 1;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
start <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count > 0 && sdram_ready) begin
timeout_count <= timeout_count - 1;
end
if (execute_command && timeout_count == 0 && sdram_ready) begin
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
state <= IDLE;
timeout_count <= `TIMEOUT_COUNT;
data_write_count <= 1;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
if (start) begin
$display ("-------------------------------");
$display ("Waiting for SDRAM to initialize");
$display ("-------------------------------");
r_in_ready <= 0;
end
if (sdram_ready) begin
state <= IDLE;
end
end
IDLE: begin
if (execute_command & ~command_finished) begin
$display ("TB: #:C:A:D = %h:%h:%h:%h", r_in_data_count, r_in_command, r_in_address, r_in_data);
timeout_count <= `TIMEOUT_COUNT;
state <= EXECUTE;
end
end
EXECUTE: begin
if (w_master_ready) begin
//send the command over
r_in_ready <= 1;
case (r_in_command & 32'h0000FFFF)
0: begin
//ping
state <= PING_RESPONSE;
end
1: begin
//write
if (r_in_data_count > 1) begin
$display ("TB: \tWrote double word %d: %h", data_write_count, r_in_data);
state <= WRITE_DATA;
timeout_count <= `TIMEOUT_COUNT;
data_write_count <= data_write_count + 1;
end
else begin
if (data_write_count > 1) begin
$display ("TB: \tWrote double word %d: %h", data_write_count, r_in_data);
end
state <= WRITE_RESPONSE;
end
end
2: begin
//read
state <= READ_RESPONSE;
end
3: begin
//reset
state <= RESET;
end
endcase
end
end
RESET: begin
//reset the system
r_ih_reset <= 1;
state <= FINISHED;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status == (~(32'h00000000))) begin
$display ("TB: Read a successful ping reponse");
end
else begin
$display ("TB: Ping response is incorrect!");
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
if (w_out_en) begin
if (w_out_status == (~(32'h00000001))) begin
$display ("TB: Read a successful write reponse");
end
else begin
$display ("TB: Write response is incorrect!");
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
//XXX: should request more data be a strobe?
request_more_data <= 0;
r_in_ready <= 1;
r_in_data_count <= r_in_data_count -1;
state <= EXECUTE;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status == (~(32'h00000002))) begin
$display ("TB: Read a successful read response");
if (w_out_data_count > 0) begin
state <= READ_MORE_DATA;
//reset the NACK timeout
timeout_count <= `TIMEOUT_COUNT;
end
else begin
state <= FINISHED;
end
end
else begin
$display ("TB: Read response is incorrect");
state <= FINISHED;
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
r_out_ready <= 0;
if (w_out_status == (~(32'h00000002))) begin
$display ("TB: Read a 32bit data packet");
$display ("Tb: \tRead Data: %h", w_out_data);
end
else begin
$display ("TB: Read reponse is incorrect");
end
//read the output data count to determine if there is more data
if (w_out_data_count == 0) begin
state <= FINISHED;
end
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
command_finished <= 0;
state <= IDLE;
end
end
default: begin
$display ("TB: state is wrong");
state <= IDLE;
end //somethine wrong here
endcase //state machine
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
$display("TB: Output Handler Recieved interrupt");
$display("TB:\tcommand: %h", w_out_status);
$display("TB:\taddress: %h", w_out_address);
$display("TB:\tdata: %h", w_out_data);
end
end//not reset
end
always @ (posedge clk) begin
if (rst) begin
r_tear_count <= 0;
r_tear_status <= 8'h00;
r_tearing_effect <= 0;
end
else begin
if (r_tear_count < 800) begin
r_tear_count <= r_tear_count + 1;
end
else begin
if (r_tear_status == 8'h00) begin
r_tear_status <= 8'h80;
r_tearing_effect <= 1;
end
else begin
r_tear_status <= 8'h00;
r_tearing_effect <= 0;
end
r_tear_count <= 0;
end
end
end
endmodule
|
// MBT 7/7/2016
//
// 1 read-port, 1 write-port ram
//
// reads are synchronous
`define bsg_mem_1r1w_sync_macro_rf(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc180_2rf_lg``lgEls``_w``bits``_m``mux``_bit mem \
( \
.CLKA (clk_i ) \
,.AA (r_addr_i) \
,.CENA(~r_v_i ) \
,.QA (r_data_o) \
\
,.CLKB(clk_i ) \
,.CENB(~w_v_i) \
,.WENB(~w_mask_i) \
,.AB (w_addr_i) \
,.DB (w_data_i) \
); \
end
module bsg_mem_1r1w_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
)
(input clk_i
, input reset_i
, input w_v_i
, input [width_p-1:0] w_mask_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
`bsg_mem_1r1w_sync_macro_rf(256,128,8,1) else
`bsg_mem_1r1w_sync_macro_rf(64,88,6,1) else
bsg_mem_1r1w_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p (els_p )
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
//synopsys translate_off
/*
always_ff @(negedge clk_i)
begin
if (reset_i!==1'b1 & (r_v_i | w_v_i))
$display("@@ w=%b w_addr=%x w_data=%x w_mask=%x r=%b r_addr=%x (%m)",w_v_i,w_addr_i,w_data_i,w_mask_i,r_v_i,r_addr_i);
end
*/
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
else
begin
$error("%m: Attempt to read and write same address (reset_i %b, %x <= %x (mask %x)",reset_i, w_addr_i,w_data_i,w_mask_i);
//$finish();
end
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p, harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_mask_write_bit)
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
//
// Copyright YOUR COMPANY, THE YEAR
// All Rights Reserved
// UNPUBLISHED, LICENSED SOFTWARE.
//
// CONFIDENTIAL AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF your company.
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 06/14/2014 at 20:26
// Component: CD32Shifter
module CD32Shifter (
output db9_6_out,
output db9_9_oe,
output db9_9_out,
input clock,
input db9_5_in,
input db9_6_in
);
//`#start body` -- edit after this line, do not edit this line
// Your code goes here
localparam OPERATION_SHIFT=3'b000;
localparam OPERATION_NOP=3'b001;
localparam OPERATION_LOAD=3'b010;
localparam OPERATION_LOADSHIFT=3'b011;
reg[2:0] operation;
localparam STATE_IDLE=2'b00;
localparam STATE_SHIFT1=2'b01;
localparam STATE_SHIFT2=2'b11;
reg[1:0] shiftstate;
wire mode;
assign mode=db9_5_in; // Shift register enable signal on DB9 pin 5.
wire shift;
assign shift=db9_6_in; // Shift register clock signal on DB9 pin 6.
wire firebutton; // Gets its value from the DataPath z1 signal (1 when A1=0).
// If the mode signal is high, then buttons 0 and 1 are passed through to DB9 pins 6 and 9, respectively
// If the mode signal is low, then the output of the shifter is passed to DB9 pin 9,
// while pin 6 becomes a clock signal.
wire shifted_data;
assign db9_9_out = shifted_data;
assign db9_6_out = mode ? firebutton : 1'b1;
// Need to use strong drive on pin 9 for speed, so for safety we avoid driving the
// pin high when not actively shifting.
assign db9_9_oe = ((shiftstate!=STATE_IDLE) | shifted_data==1'b0);
// FIXME - do we need more filtering on DB9_6_in?
always @(posedge clock)
begin
if(shiftstate==STATE_IDLE)
begin
shiftstate<=STATE_IDLE;
// Contintually load the current button status into the shift register while idle.
// This allows the first button's status to reach the s0 signal.
operation<=OPERATION_LOAD;
// Wait for mode signal to drop. When it does, start shifting.
if(mode==1'b0 && shift==1'b0)
begin
shiftstate<=STATE_SHIFT1;
end
end
else if(shiftstate==STATE_SHIFT1)
begin
operation<=OPERATION_NOP;
// Wait for posedge of the shift signal, shift data on transition.
if(shift==1'b1)
begin
shiftstate<=STATE_SHIFT2;
operation<=OPERATION_SHIFT;
end
if(mode==1'b1)
shiftstate<=STATE_IDLE;
end
else if(shiftstate==STATE_SHIFT2)
begin
operation<=OPERATION_NOP;
// Wait for negedge of the shift signal.
if(shift==1'b0)
begin
shiftstate<=STATE_SHIFT1;
end
if(mode==1'b1)
shiftstate<=STATE_IDLE;
end
else
shiftstate<=STATE_IDLE;
end
cy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: SHIFT*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: NOP*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: LOAD*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: LOADSHIFT*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'hFF, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) CD32Shifter_DP(
/* input */ .reset(1'b0),
/* input */ .clk(clock),
/* input [02:00] */ .cs_addr(operation),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(firebutton), // We use A1 to bring the fire button's status into the component
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(shifted_data),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_SIO_MACRO_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_SIO_MACRO_PP_SYMBOL_V
/**
* top_sio_macro: sky130_fd_io__sio_macro consists of two SIO cells
* and a reference generator cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_sio_macro (
//# {{data|Data Signals}}
input DFT_REFGEN ,
input [1:0] SLOW ,
output [1:0] IN ,
input [1:0] INP_DIS ,
output [1:0] IN_H ,
input [1:0] OUT ,
inout [1:0] PAD ,
inout [1:0] PAD_A_ESD_0_H ,
inout [1:0] PAD_A_ESD_1_H ,
inout [1:0] PAD_A_NOESD_H ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input [2:0] DM0 ,
input [2:0] DM1 ,
input ENABLE_H ,
input ENABLE_VDDA_H ,
input [1:0] HLD_H_N ,
input HLD_H_N_REFGEN ,
input [1:0] HLD_OVR ,
input [1:0] IBUF_SEL ,
input IBUF_SEL_REFGEN ,
input [1:0] OE_N ,
//# {{power|Power}}
input [2:0] VOH_SEL ,
input [1:0] VREF_SEL ,
input [1:0] VREG_EN ,
input VREG_EN_REFGEN ,
input [1:0] VTRIP_SEL ,
input VTRIP_SEL_REFGEN,
inout VSWITCH ,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
inout VINREF_DFT ,
input VOHREF ,
inout VOUTREF_DFT ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q ,
output [1:0] TIE_LO_ESD
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_SIO_MACRO_PP_SYMBOL_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: acv_hard_memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR3_DS = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = (FAST_SIM_MODEL && (FAST_SIM_CALIBRATION != "true") ? SKIP_CALIBRATION_STEPS : 7'b1000000);
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
lpddr2_cntrlr_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
lpddr2_cntrlr_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
lpddr2_cntrlr_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "false";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_cycle";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
lpddr2_cntrlr_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
/*
File: ewrapper_io_tx_slow.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_io_tx_slow (/*AUTOARG*/
// Outputs
DATA_OUT_TO_PINS_P, DATA_OUT_TO_PINS_N, LCLK_OUT_TO_PINS_P,
LCLK_OUT_TO_PINS_N,
// Inputs
CLK_IN, CLK_IN_90, CLK_DIV_IN, CLK_RESET, IO_RESET,
DATA_OUT_FROM_DEVICE
);
//###########
//# INPUTS
//###########
input CLK_IN; // Fast clock input from PLL/MMCM
input CLK_IN_90; // Fast clock input with 90deg phase shift
input CLK_DIV_IN; // Slow clock input from PLL/MMCM
input CLK_RESET;
input IO_RESET;
input [71:0] DATA_OUT_FROM_DEVICE;
//#############
//# OUTPUTS
//#############
output [8:0] DATA_OUT_TO_PINS_P;
output [8:0] DATA_OUT_TO_PINS_N;
output LCLK_OUT_TO_PINS_P;
output LCLK_OUT_TO_PINS_N;
//############
//# REGS
//############
reg [1:0] clk_cnt;
reg tx_coreclock_del_45;
reg tx_coreclock_del_135;
reg [8:0] clk_even_reg;
reg [8:0] clk_odd_reg;
reg [71:0] tx_in_sync;
//############
//# WIRES
//############
wire txo_lclk;
wire txo_lclk90;
wire tx_coreclock;
wire reset;
wire tx_pedge_first;
wire [8:0] clk_even;
wire [8:0] clk0_even;
wire [8:0] clk1_even;
wire [8:0] clk2_even;
wire [8:0] clk3_even;
wire [8:0] clk_odd;
wire [8:0] clk0_odd;
wire [8:0] clk1_odd;
wire [8:0] clk2_odd;
wire [8:0] clk3_odd;
wire cycle_sel_0;
wire cycle_sel_1;
wire cycle_sel_2;
wire cycle_sel_3;
wire [71:0] tx_in;
wire [8:0] tx_out;
wire tx_lclk_out;
wire [8:0] DATA_OUT_TO_PINS_P;
wire [8:0] DATA_OUT_TO_PINS_N;
wire LCLK_OUT_TO_PINS_P;
wire LCLK_OUT_TO_PINS_N;
wire [8:0] oddr_data_d1;
wire [8:0] oddr_data_d2;
wire oddr_clk_d1;
wire oddr_clk_d2;
/*AUTOINPUT*/
/*AUTOWIRE*/
`ifdef EP64
assign oddr_data_d1[8:0] = ~clk_even_reg[8:0];
assign oddr_data_d2[8:0] = ~clk_odd_reg[8:0];
assign oddr_clk_d1 = 1'b0;
assign oddr_clk_d2 = 1'b1;
`else
assign oddr_data_d1[8:0] = clk_even_reg[8:0];
assign oddr_data_d2[8:0] = clk_odd_reg[8:0];
assign oddr_clk_d1 = 1'b1;
assign oddr_clk_d2 = 1'b0;
`endif
assign reset = CLK_RESET;
assign tx_in[71:0] = DATA_OUT_FROM_DEVICE[71:0];
assign txo_lclk = CLK_IN;
assign txo_lclk90 = CLK_IN_90;
assign tx_coreclock = CLK_DIV_IN;
//#################################################
//# Synchronize incoming data to fast clock domain
//#################################################
always @ (posedge txo_lclk or posedge reset)
if(reset)
tx_in_sync[71:0] <= {(72){1'b0}};
else if(tx_pedge_first)
tx_in_sync[71:0] <= tx_in[71:0];
//################################
//# Output Buffers Instantiation
//################################
genvar pin_count;
generate
for (pin_count = 0; pin_count < 9; pin_count = pin_count + 1) begin: pins
OBUFDS #(.IOSTANDARD (`IOSTND)) obufds_inst
(.O (DATA_OUT_TO_PINS_P[pin_count]),
.OB (DATA_OUT_TO_PINS_N[pin_count]),
.I (tx_out[pin_count]));
end
endgenerate
OBUFDS #(.IOSTANDARD (`IOSTND)) obufds_lclk_inst
(.O (LCLK_OUT_TO_PINS_P),
.OB (LCLK_OUT_TO_PINS_N),
.I (tx_lclk_out));
//#############################
//# ODDR instantiation
//#############################
genvar oddr_cnt;
generate
for (oddr_cnt = 0; oddr_cnt < 9; oddr_cnt = oddr_cnt + 1) begin: oddrs
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_inst (
.Q (tx_out[oddr_cnt]),
.C (txo_lclk),
.CE (1'b1),
.D1 (oddr_data_d1[oddr_cnt]),
.D2 (oddr_data_d2[oddr_cnt]),
.R (reset),
.S (1'b0));
end
endgenerate
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_lclk_inst (
.Q (tx_lclk_out),
.C (txo_lclk90),
.CE (1'b1),
.D1 (oddr_clk_d1),
.D2 (oddr_clk_d2),
.R (reset),
.S (1'b0));
//########################
//# Data Serialization
//########################
always @ (posedge txo_lclk or posedge reset)
if(reset)
begin
clk_even_reg[8:0] <= {(9){1'b0}};
clk_odd_reg[8:0] <= {(9){1'b0}};
end
else
begin
clk_even_reg[8:0] <= clk_even[8:0];
clk_odd_reg[8:0] <= clk_odd[8:0];
end
mux4 #(18) mux4(// Outputs
.out ({clk_even[8:0],clk_odd[8:0]}),
// Inputs
.in0 ({clk0_even[8:0],clk0_odd[8:0]}), .sel0 (cycle_sel_0),
.in1 ({clk1_even[8:0],clk1_odd[8:0]}), .sel1 (cycle_sel_1),
.in2 ({clk2_even[8:0],clk2_odd[8:0]}), .sel2 (cycle_sel_2),
.in3 ({clk3_even[8:0],clk3_odd[8:0]}), .sel3 (cycle_sel_3));
//#################################
//# Serialization Cycle Counter
//#################################
assign cycle_sel_0 = (clk_cnt[1:0] == 2'b00);
assign cycle_sel_1 = (clk_cnt[1:0] == 2'b01);
assign cycle_sel_2 = (clk_cnt[1:0] == 2'b10);
assign cycle_sel_3 = (clk_cnt[1:0] == 2'b11);
always @ (posedge txo_lclk or posedge reset)
if(reset)
clk_cnt[1:0] <= 2'b00;
else if(tx_pedge_first)
clk_cnt[1:0] <= 2'b00;
else
clk_cnt[1:0] <= clk_cnt[1:0] + 2'b01;
//################################################################
//# Posedge Detection of the Slow Clock in the Fast Clock Domain
//################################################################
always @ (negedge txo_lclk)
tx_coreclock_del_45 <= tx_coreclock;
always @ (negedge txo_lclk)
tx_coreclock_del_135 <= tx_coreclock_del_45;
assign tx_pedge_first = tx_coreclock_del_45 & ~tx_coreclock_del_135;
//##################################
//# Data Alignment Channel-to-Byte
//##################################
assign clk0_even[8:0] ={tx_in_sync[71],tx_in_sync[63],tx_in_sync[55],
tx_in_sync[47],tx_in_sync[39],tx_in_sync[31],
tx_in_sync[23],tx_in_sync[15],tx_in_sync[7]};
assign clk0_odd[8:0] ={tx_in_sync[70],tx_in_sync[62],tx_in_sync[54],
tx_in_sync[46],tx_in_sync[38],tx_in_sync[30],
tx_in_sync[22],tx_in_sync[14],tx_in_sync[6]};
assign clk1_even[8:0] ={tx_in_sync[69],tx_in_sync[61],tx_in_sync[53],
tx_in_sync[45],tx_in_sync[37],tx_in_sync[29],
tx_in_sync[21],tx_in_sync[13],tx_in_sync[5]};
assign clk1_odd[8:0] ={tx_in_sync[68],tx_in_sync[60],tx_in_sync[52],
tx_in_sync[44],tx_in_sync[36],tx_in_sync[28],
tx_in_sync[20],tx_in_sync[12],tx_in_sync[4]};
assign clk2_even[8:0] ={tx_in_sync[67],tx_in_sync[59],tx_in_sync[51],
tx_in_sync[43],tx_in_sync[35],tx_in_sync[27],
tx_in_sync[19],tx_in_sync[11],tx_in_sync[3]};
assign clk2_odd[8:0] ={tx_in_sync[66],tx_in_sync[58],tx_in_sync[50],
tx_in_sync[42],tx_in_sync[34],tx_in_sync[26],
tx_in_sync[18],tx_in_sync[10],tx_in_sync[2]};
assign clk3_even[8:0] ={tx_in_sync[65],tx_in_sync[57],tx_in_sync[49],
tx_in_sync[41],tx_in_sync[33],tx_in_sync[25],
tx_in_sync[17],tx_in_sync[9], tx_in_sync[1]};
assign clk3_odd[8:0] ={tx_in_sync[64],tx_in_sync[56],tx_in_sync[48],
tx_in_sync[40],tx_in_sync[32],tx_in_sync[24],
tx_in_sync[16],tx_in_sync[8], tx_in_sync[0]};
endmodule // ewrapper_io_tx_slow
|
///////////////////////////////////////////////////////////////////////////////
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// Module block_sync_sm
// Generated by Xilinx Aurora 64B66B
`timescale 1 ps / 1 ps
`define DLY #1
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_BLOCK_SYNC_SM #
(
parameter SH_CNT_MAX = 16'd64,
parameter SH_INVALID_CNT_MAX = 10'd16
)
(
// User Interface
BLOCKSYNC_OUT,
RXGEARBOXSLIP_OUT,
RXHEADER_IN,
RXHEADERVALID_IN,
// System Interface
USER_CLK,
SYSTEM_RESET
);
//***********************************Port Declarations*******************************
// User Interface
output BLOCKSYNC_OUT;
output RXGEARBOXSLIP_OUT;
input [1:0] RXHEADER_IN;
input RXHEADERVALID_IN;
// System Interface
input USER_CLK;
input SYSTEM_RESET;
//***************************External Register Declarations***************************
reg BLOCKSYNC_OUT;
reg RXGEARBOXSLIP_OUT;
//**************************** Wire Declarations ******************************
reg next_begin_c;
reg next_sh_invalid_c;
reg next_sh_valid_c;
reg next_slip_c;
reg next_sync_done_c;
reg next_test_sh_c;
wire sh_count_equals_max_i;
wire sh_invalid_cnt_equals_max_i;
wire sh_invalid_cnt_equals_zero_i;
wire slip_done_i;
wire sync_found_i;
//***************************External Register Declarations***************************
reg begin_r;
reg sh_invalid_r;
reg sh_valid_r;
reg [15:0] slip_count_i;
reg slip_r;
reg sync_done_r;
reg [15:0] sync_header_count_i;
reg [9:0] sync_header_invalid_count_i;
reg test_sh_r;
reg system_reset_r;
reg system_reset_r2;
//**************************** Main Body of Code *******************************
assign sync_found_i = (RXHEADER_IN == 2'b01) || (RXHEADER_IN == 2'b10);
// Double Synchronize SYSTEM_RESET wrt USER_CLK
always @(posedge USER_CLK)
begin
system_reset_r <= `DLY SYSTEM_RESET;
system_reset_r2 <= `DLY system_reset_r;
end
//________________________________ State machine __________________________
// State registers
always @(posedge USER_CLK)
if(system_reset_r2)
{begin_r,test_sh_r,sh_valid_r,sh_invalid_r,slip_r,sync_done_r} <= `DLY 6'b100000;
else
begin
begin_r <= `DLY next_begin_c;
test_sh_r <= `DLY next_test_sh_c;
sh_valid_r <= `DLY next_sh_valid_c;
sh_invalid_r <= `DLY next_sh_invalid_c;
slip_r <= `DLY next_slip_c;
sync_done_r <= `DLY next_sync_done_c;
end
/*
// Next state logic
assign next_begin_c = sync_done_r
| (slip_r && slip_done_i)
| (sh_valid_r && sh_count_equals_max_i && !sh_invalid_cnt_equals_max_i)
| (sh_invalid_r && sh_count_equals_max_i && !sh_invalid_cnt_equals_max_i && BLOCKSYNC_OUT);
assign next_test_sh_c = begin_r
| (test_sh_r && !RXHEADERVALID_IN)
| (sh_valid_r && !sh_count_equals_max_i)
| (sh_invalid_r && !sh_count_equals_max_i && !sh_invalid_cnt_equals_max_i && BLOCKSYNC_OUT);
assign next_sh_valid_c = (test_sh_r && RXHEADERVALID_IN && sync_found_i);
assign next_sh_invalid_c = (test_sh_r && RXHEADERVALID_IN && !sync_found_i);
assign next_slip_c = (sh_invalid_r && (sh_invalid_cnt_equals_max_i || !BLOCKSYNC_OUT))
| (slip_r && !slip_done_i);
assign next_sync_done_c = (sh_valid_r && sh_count_equals_max_i && sh_invalid_cnt_equals_zero_i);
*/
// FSM is same as above, but recoded as priority muxes
localparam BEGIN_R_ST = 6'b100000,
TEST_SH_ST = 6'b010000,
SH_VALID_ST = 6'b001000,
SH_INVALID_ST = 6'b000100,
SLIP_R_ST = 6'b000010,
SYNC_DONE_R_ST = 6'b000001;
always @(*)
begin
{next_begin_c,next_test_sh_c,next_sh_valid_c,next_sh_invalid_c,next_slip_c,next_sync_done_c} = 6'b000000;
case({begin_r,test_sh_r,sh_valid_r,sh_invalid_r,slip_r,sync_done_r})
BEGIN_R_ST:
begin
next_test_sh_c = 1'b1;
end
TEST_SH_ST:
begin
if(RXHEADERVALID_IN)
begin
if(sync_found_i)
next_sh_valid_c = 1'b1;
else
next_sh_invalid_c = 1'b1;
end
else
next_test_sh_c = 1'b1;
end
SH_VALID_ST:
begin
if(sh_count_equals_max_i)
begin
if(sh_invalid_cnt_equals_zero_i)
next_sync_done_c = 1'b1;
else if((sh_invalid_cnt_equals_max_i | !BLOCKSYNC_OUT))
next_slip_c = 1'b1;
else
next_begin_c = 1'b1;
end
//check_me if(sh_count_equals_max_i)
//check_me begin
//check_me if(sh_invalid_cnt_equals_zero_i)
//check_me next_sync_done_c = 1'b1;
//check_me else if(!sh_invalid_cnt_equals_max_i)
//check_me next_begin_c = 1'b1;
//check_me end
else
next_test_sh_c = 1'b1;
end
SH_INVALID_ST:
begin
if(sh_invalid_cnt_equals_max_i)
next_slip_c = 1'b1;
else
begin
if(!BLOCKSYNC_OUT)
next_slip_c = 1'b1;
else if(sh_count_equals_max_i)
next_begin_c = 1'b1;
else
next_test_sh_c = 1'b1;
end
end
SLIP_R_ST:
begin
if(slip_done_i)
next_begin_c =1'b1;
else
next_slip_c = 1'b1;
end
SYNC_DONE_R_ST:
begin
next_begin_c = 1'b1;
end
default:
begin
next_begin_c = 1'b1;
end
endcase
end
//________________ Counter keep track of sync headers counted _____________
always @(posedge USER_CLK)
if(begin_r)
begin
sync_header_count_i <= `DLY 16'd0;
end
else if (sh_valid_r || sh_invalid_r)
begin
sync_header_count_i <= `DLY sync_header_count_i + 16'd1;
end
assign sh_count_equals_max_i = (sync_header_count_i==SH_CNT_MAX);
//________________ Counter keep track of invalid sync headers ____________
always @(posedge USER_CLK)
if(begin_r)
begin
sync_header_invalid_count_i <= `DLY 10'd0;
end
else if (sh_invalid_r)
begin
sync_header_invalid_count_i <= `DLY sync_header_invalid_count_i + 10'd1;
end
// signal to indicate max number of invalid sync headers has been reached
assign sh_invalid_cnt_equals_max_i = (sync_header_invalid_count_i==SH_INVALID_CNT_MAX);
// signal to indicate no invalid sync headers
assign sh_invalid_cnt_equals_zero_i = (sync_header_invalid_count_i==0);
//_______ Counter wait for 16 cycles to ensure that slip is complete _______
wire slip_pulse_i = next_slip_c && !slip_r;
always @(posedge USER_CLK)
RXGEARBOXSLIP_OUT <= slip_pulse_i;
//_____________ Ouput assignment to indicate block sync complete _________
always @(posedge USER_CLK)
if(!slip_r) slip_count_i <= `DLY 16'h0000;
else slip_count_i <= `DLY {slip_count_i[14:0],RXGEARBOXSLIP_OUT};
assign slip_done_i = slip_count_i[15];
//_____________ Pulse GEARBOXSLIP port to slip the data by 1 bit _________
always @(posedge USER_CLK)
if(system_reset_r2 || slip_r) BLOCKSYNC_OUT <= `DLY 1'b0;
else if (sync_done_r) BLOCKSYNC_OUT <= `DLY 1'b1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A311O_FUNCTIONAL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_FUNCTIONAL_V |
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_F_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test F (2 PM)
*/
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @ (clk) begin
if ($time % 15 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 2 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_1_V
`define SKY130_FD_SC_HD__DLCLKP_1_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_1 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVPWRVGND_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__TAPVPWRVGND_FUNCTIONAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVPWRVGND_FUNCTIONAL_PP_V |
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* This is a modified PicoSoC example which has removed the requirement
* for an external SPI flash. The PicoRV32 program is stored in ROM implemented
* as a number of case statements. The ROM file is generated using an external
* script.
*
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifndef PICORV32_REGS
`ifdef PICORV32_V
`error "picosoc.v must be read before picorv32.v!"
`endif
`define PICORV32_REGS picosoc_regs
`endif
module picosoc_noflash (
input clk,
input resetn,
output iomem_valid,
input iomem_ready,
output [ 3:0] iomem_wstrb,
output [31:0] iomem_addr,
output [31:0] iomem_wdata,
input [31:0] iomem_rdata,
input irq_5,
input irq_6,
input irq_7,
output ser_tx,
input ser_rx
);
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
reg [31:0] irq;
wire irq_stall = 0;
wire irq_uart = 0;
always @* begin
irq = 0;
irq[3] = irq_stall;
irq[4] = irq_uart;
irq[5] = irq_5;
irq[6] = irq_6;
irq[7] = irq_7;
end
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire progmem_ready;
wire [31:0] progmem_rdata;
reg ram_ready;
wire [31:0] ram_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
wire [31:0] simpleuart_reg_div_do;
wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
wire [31:0] simpleuart_reg_dat_do;
wire simpleuart_reg_dat_wait;
assign mem_ready =
(iomem_valid && iomem_ready) || progmem_ready || ram_ready || spimemio_cfgreg_sel ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
assign mem_rdata =
(iomem_valid && iomem_ready) ? iomem_rdata :
progmem_ready ? progmem_rdata :
ram_ready ? ram_rdata :
spimemio_cfgreg_sel ? 32'h0000_0000 : // Mockup, will always read 0
simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
`ifdef SIMULATION
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
`endif
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(1),
.COMPRESSED_ISA(1),
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
`ifdef SIMULATION
.ENABLE_IRQ_QREGS(0),
.ENABLE_TRACE(1)
`else
.ENABLE_IRQ_QREGS(0)
`endif
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
`ifdef SIMULATION
.irq (irq ),
.trace_valid (trace_valid),
.trace_data (trace_data )
`else
.irq (irq )
`endif
);
// This it the program ROM memory for the PicoRV32
progmem progmem (
.clk (clk),
.rstn (resetn),
.valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
.ready (progmem_ready),
.addr (mem_addr),
.rdata (progmem_rdata)
);
simpleuart simpleuart (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
.reg_div_di (mem_wdata),
.reg_div_do (simpleuart_reg_div_do),
.reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
.reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
.reg_dat_di (mem_wdata),
.reg_dat_do (simpleuart_reg_dat_do),
.reg_dat_wait(simpleuart_reg_dat_wait)
);
always @(posedge clk)
ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
picosoc_mem #(.WORDS(MEM_WORDS)) memory (
.clk(clk),
.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
.addr(mem_addr[23:2]),
.wdata(mem_wdata),
.rdata(ram_rdata)
);
// Simulation debug
`ifdef SIMULATION
always @(posedge clk)
if (resetn) begin
if ( mem_instr && mem_valid && mem_ready)
$display("Inst rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata);
if (!mem_instr && mem_valid && mem_ready)
$display("Data rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata);
end
// Trace
initial begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while(1) begin
@(posedge clk)
if (resetn && trace_valid)
$fwrite(trace_file, "%x\n", trace_data);
$fflush(trace_file);
//$display("Trace : %09X", trace_data);
end
end
`endif // SIMULATION
endmodule
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
(* ram_style = "distributed" *) reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
module picosoc_mem #(
parameter integer WORDS = 256
) (
input clk,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output reg [31:0] rdata
);
(* ram_style = "distributed" *) reg [31:0] mem [0:WORDS-1];
always @(posedge clk) begin
rdata <= mem[addr];
if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
if (wen[2]) mem[addr][23:16] <= wdata[23:16];
if (wen[3]) mem[addr][31:24] <= wdata[31:24];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFXBP_PP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_PP_SYMBOL_V
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Generated by Quartus II Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
// Created on Sun May 22 00:06:14 2016
// synthesis message_off 10175
`timescale 1ns/1ns
module key_logic_fsm (
clock,reset,k[3:0],lcd_busy,reg_busy,
run_timer,reset_timer,insert_value,clear_value);
input clock;
input reset;
input [3:0] k;
input lcd_busy;
input reg_busy;
tri0 reset;
tri0 [3:0] k;
tri0 lcd_busy;
tri0 reg_busy;
output run_timer;
output reset_timer;
output insert_value;
output clear_value;
reg run_timer;
reg reset_timer;
reg insert_value;
reg clear_value;
reg [10:0] fstate;
reg [10:0] reg_fstate;
parameter s_pre_start=0,s_run=1,s_pre_pause=2,s_pause=3,s_idle=4,s_pre_reset=5,s_reset=6,s_retrieve=7,s_save=8,s_pre_clear=9,s_clear=10;
always @(posedge clock)
begin
if (clock) begin
fstate <= reg_fstate;
end
end
always @(fstate or reset or k or lcd_busy or reg_busy)
begin
if (reset) begin
reg_fstate <= s_idle;
run_timer <= 1'b0;
reset_timer <= 1'b0;
insert_value <= 1'b0;
clear_value <= 1'b0;
end
else begin
run_timer <= 1'b0;
reset_timer <= 1'b0;
insert_value <= 1'b0;
clear_value <= 1'b0;
case (fstate)
s_pre_start: begin
if ((k[3:0] != 4'b0000))
reg_fstate <= s_pre_start;
else if ((k[3:0] == 4'b0000))
reg_fstate <= s_run;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pre_start;
run_timer <= 1'b1;
end
s_run: begin
if ((k[3:0] == 4'b0000))
reg_fstate <= s_run;
else if ((k[3:0] == 4'b1000))
reg_fstate <= s_pre_pause;
else if ((k[3:0] == 4'b0100))
reg_fstate <= s_retrieve;
else if ((k[3:0] == 4'b0010))
reg_fstate <= s_pre_reset;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_run;
run_timer <= 1'b1;
end
s_pre_pause: begin
if ((k[3:0] != 4'b0000))
reg_fstate <= s_pre_pause;
else if ((k[3:0] == 4'b0000))
reg_fstate <= s_pause;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pre_pause;
end
s_pause: begin
if ((k[3:0] == 4'b0000))
reg_fstate <= s_pause;
else if ((k[3:0] == 4'b1000))
reg_fstate <= s_pre_start;
else if ((k[3:0] == 4'b0010))
reg_fstate <= s_pre_reset;
else if ((k[3:0] == 4'b0001))
reg_fstate <= s_pre_clear;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pause;
end
s_idle: begin
if ((k[3:0] == 4'b0000))
reg_fstate <= s_idle;
else if ((k[3:0] == 4'b1000))
reg_fstate <= s_pre_start;
else if ((k[3:0] == 4'b0010))
reg_fstate <= s_pre_reset;
else if ((k[3:0] == 4'b0001))
reg_fstate <= s_pre_clear;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_idle;
end
s_pre_reset: begin
if ((k[3:0] != 4'b0000))
reg_fstate <= s_pre_reset;
else if ((k[3:0] == 4'b0000))
reg_fstate <= s_reset;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pre_reset;
end
s_reset: begin
if (reg_busy)
reg_fstate <= s_reset;
else if (~(reg_busy))
reg_fstate <= s_idle;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_reset;
reset_timer <= 1'b1;
end
s_retrieve: begin
reg_fstate <= s_save;
insert_value <= 1'b1;
end
s_save: begin
if ((lcd_busy | (k[3:0] != 4'b0000)))
reg_fstate <= s_save;
else if ((~(lcd_busy) & (k[3:0] == 4'b0000)))
reg_fstate <= s_run;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_save;
run_timer <= 1'b1;
end
s_pre_clear: begin
if ((k[3:0] != 4'b0000))
reg_fstate <= s_pre_clear;
else if ((k[3:0] == 4'b0000))
reg_fstate <= s_clear;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_pre_clear;
end
s_clear: begin
if (lcd_busy)
reg_fstate <= s_clear;
else if (~(lcd_busy))
reg_fstate <= s_pause;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= s_clear;
clear_value <= 1'b1;
end
default: begin
run_timer <= 1'bx;
reset_timer <= 1'bx;
insert_value <= 1'bx;
clear_value <= 1'bx;
$display ("Reach undefined state");
end
endcase
end
end
endmodule // key_logic_fsm
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`ifdef BASIL_SBUS
`define SPLIT_BUS
`elsif BASIL_TOPSBUS
`define SPLIT_BUS
`endif
`ifndef BASIL_SBUS
`include "utils/bus_to_ip.v"
`include "utils/cdc_syncfifo.v"
`include "utils/fifo_8_to_32.v"
`include "utils/generic_fifo.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`else
$fatal("Sbus modules not implemented yet");
`endif
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
`ifndef SPLIT_BUS
inout wire [31:0] BUS_DATA,
`else
input wire [31:0] BUS_DATA_IN,
output wire [31:0] BUS_DATA_OUT,
`endif
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000 - 1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000-1;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
// Connect tb internal bus to external split bus
`ifdef BASIL_TOPSBUS
wire [31:0] BUS_DATA;
assign BUS_DATA = BUS_DATA_IN;
assign BUS_DATA_OUT = BUS_DATA;
`elsif BASIL_SBUS
wire [31:0] BUS_DATA_OUT_1;
assign BUS_DATA_OUT = BUS_DATA_OUT_1;
`endif
wire FIFO_READ_RX;
wire FIFO_EMPTY_RX;
wire [31:0] FIFO_DATA_RX;
wire cdc_fifo_write;
assign cdc_fifo_write = (BUS_ADD >= 32'h1000 && BUS_ADD < 32'h8000) & BUS_WR;
wire fifo_full, cdc_fifo_empty;
wire [7:0] cdc_data_out;
`ifndef BASIL_SBUS
cdc_syncfifo #(
`else
cdc_syncfifo_sbus #(
`endif
.DSIZE(8),
.ASIZE(3)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(),
.rempty(cdc_fifo_empty),
`ifndef BASIL_SBUS
.wdata(BUS_DATA),
`else
.wdata(BUS_DATA_IN),
`endif
.winc(cdc_fifo_write), .wclk(BUS_CLK), .wrst(BUS_RST),
.rinc(!fifo_full), .rclk(BUS_CLK), .rrst(BUS_RST)
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
`ifndef BASIL_SBUS
fifo_8_to_32 #(
`else
fifo_8_to_32_sbus #(
`endif
.DEPTH(1024)
) fifo_8_to_32_i (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE(!cdc_fifo_empty),
.READ(FIFO_READ),
.DATA_IN(cdc_data_out),
.FULL(fifo_full),
.EMPTY(FIFO_EMPTY),
.DATA_OUT(FIFO_DATA)
);
`ifndef BASIL_SBUS
bram_fifo #(
`else
bram_fifo_sbus #(
`endif
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA),
`else
.BUS_DATA_IN(BUS_DATA_IN),
.BUS_DATA_OUT(BUS_DATA_OUT_1),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
`ifndef VERILATOR_SIM
initial begin
$dumpfile("test_SimFifo8to32.vcd");
$dumpvars(0);
end
`endif
endmodule
|
`include "timescale.v"
// UART Protocol Layer
module uart_if (/*AUTOARG*/
// Outputs
uart_dout, uart_addr, uart_mem_we, uart_mem_re, reg_we, uart_tx,
// Inputs
uart_mem_i, uart_reg_i, clk, arst_n, uart_rx
);
output [23:0] uart_dout;
output [13:0] uart_addr;
output uart_mem_we;
output uart_mem_re;
output reg_we;
output uart_tx;
input [23:0] uart_mem_i;
input [23:0] uart_reg_i;
input clk;
input arst_n;
input uart_rx;
reg [15:0] cmd;
reg [23:0] uart_dout;
parameter stIdle = 0;
parameter stCmd1 = 1;
parameter stCmd2 = 2;
parameter stData1 = 3;
parameter stData2 = 4;
parameter stData3 = 5;
parameter stWr = 6;
parameter stRd = 7;
reg [2:0] state;
reg [7:0] din_i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] dout_o; // From uart_ of sasc_top.v
wire empty_o; // From uart_ of sasc_top.v
wire full_o; // From uart_ of sasc_top.v
wire sio_ce; // From baud_ of sasc_brg.v
wire sio_ce_x4; // From baud_ of sasc_brg.v
// End of automatics
wire cmdRd;
wire cmdMem;
reg re_i;
reg we_i;
sasc_top uart_ (// Outputs
.txd_o (uart_tx),
.rts_o (),
// Inputs
.rxd_i (uart_rx),
.cts_i (1'b0),
.rst_n (arst_n),
/*AUTOINST*/
// Outputs
.dout_o (dout_o[7:0]),
.full_o (full_o),
.empty_o (empty_o),
// Inputs
.clk (clk),
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
.din_i (din_i[7:0]),
.re_i (re_i),
.we_i (we_i));
sasc_brg baud_ (/*AUTOINST*/
// Outputs
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
// Inputs
.clk (clk),
.arst_n (arst_n));
always @ (posedge clk or negedge arst_n)
if (~arst_n)
state <= stIdle;
else
case (state)
stIdle : if (~empty_o) state <= stCmd1;
stCmd1 : if (~empty_o) state <= stCmd2;
stCmd2 : if (cmdRd) state <= stRd; // read
else if (~empty_o) state <= stData1; // write
stData1: if (cmdRd) state <= stData2; // read
else if (~empty_o) state <= stData2; // write
stData2: if (cmdRd) state <= stData3; // read
else if (~empty_o) state <= stData3; // write
stData3: if (cmdRd) state <= stIdle; // read done
else state <= stWr; // write commit
stWr: state <= stIdle;
stRd: state <= stData1;
endcase // case(state)
// --------------- Command Word Capture ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n) cmd <= 0;
else
begin
if (state==stIdle) cmd[15:8] <= dout_o[7:0];
if (state==stCmd1) cmd[7:0] <= dout_o[7:0];
end
assign cmdRd = ~cmd[15];
assign cmdMem = cmd[14];
assign uart_addr = cmd[13:0];
// --------------- Write Command ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n)
uart_dout <= 0;
else
begin
if (state==stCmd2 & ~cmdRd) uart_dout[23:16] <= dout_o[7:0];
if (state==stData1 & ~cmdRd) uart_dout[15:8] <= dout_o[7:0];
if (state==stData2 & ~cmdRd) uart_dout[7:0] <= dout_o[7:0];
end
always @ (/*AS*/cmdRd or empty_o or state)
case (state)
stIdle : re_i = ~empty_o;
stCmd1 : re_i = ~empty_o;
stCmd2 : re_i = ~empty_o & ~cmdRd;
stData1: re_i = ~empty_o & ~cmdRd;
stData2: re_i = ~empty_o & ~cmdRd;
default: re_i = 0;
endcase // case(state)
assign uart_mem_we = (state==stWr) & cmdMem;
assign reg_we = (state==stWr) & ~cmdMem;
// --------------- Read Command ----------------- //
always @ (/*AS*/cmdMem or state or uart_mem_i or uart_reg_i)
case (state)
stData2: din_i[7:0] = cmdMem ? uart_mem_i[15:8] : uart_reg_i[15:8];
stData3: din_i[7:0] = cmdMem ? uart_mem_i[7:0] : uart_reg_i[7:0];
default: din_i[7:0] = cmdMem ? uart_mem_i[23:16] : uart_reg_i[23:16];
endcase // case(state)
always @ (/*AS*/cmdRd or state)
case (state)
stData1: we_i = cmdRd;
stData2: we_i = cmdRd;
stData3: we_i = cmdRd;
default: we_i = 0;
endcase // case(state)
assign uart_mem_re = (state==stRd);
endmodule // uart_if
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__MUX2_BEHAVIORAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__mux2 (
VPWR,
VGND,
X ,
A0 ,
A1 ,
S
);
// Module ports
input VPWR;
input VGND;
output X ;
input A0 ;
input A1 ;
input S ;
// Local signals
wire u_mux_20_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (u_mux_20_out_X , A0, A1, S );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, u_mux_20_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2OI_TB_V
`define SKY130_FD_SC_MS__A2BB2OI_TB_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2bb2oi.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ms__a2bb2oi dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2OI_TB_V
|
/*
*******************************************************************************
* File Name : ada_hazard.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 10th, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright (c) 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Hazard detection and forwarding control.
* Also, controls the pipeline registers for proper functioning
*******************************************************************************
*/
`include "ada_defines.v"
module ada_hazard(
input [4:0] id_gpr_port_a, // GPR address A: ID stage
input [4:0] id_gpr_port_b, // GPR address B: ID stage
input [4:0] ex_gpr_wa, // GPR write address: EX stage
input [4:0] mem_gpr_wa, // GPR write address: MEM stage
input [4:0] wb_gpr_wa, // GPR write address: WB stage
input ex_gpr_we, // GPR write enable: EX stage
input mem_gpr_we, // GPR write enable: MEM stage
input wb_gpr_we, // GPR write enable: WB stage
input if_mem_request_stall, // Request stall IF stage from memory decoder unit.
input ex_data_read, // Memory load: EX stage
input mem_request_stall, // Request stall MEM stage from memory decoder unit.
input if_exception_stall, // Request stall IF stage from exception controller.
input id_exception_stall, // Request stall ID stage from exception controller.
input ex_exception_stall, // Request stall EX stage from exception controller.
input mem_exception_stall, // Request stall MEM stage from exception controller.
input ex_exu_stall, // Hazard from EX stage
output [1:0] forward_port_a_select, // forwarding selector: port A
output [1:0] forward_port_b_select, // forwarding selector: port B
output if_stall, // Stall IF stage
output id_stall, // Stall ID stage
output ex_stall, // Stall EX stage
output mem_stall, // Stall MEM stage
output wb_stall // Stall WB stage
);
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
// no forwarding if reading register zero
wire id_port_a_is_zero;
wire id_port_b_is_zero;
// verify match: register address and write address (EX, MEM & WB)
wire id_ex_port_a_match;
wire id_ex_port_b_match;
wire id_mem_port_a_match;
wire id_mem_port_b_match;
wire id_wb_port_a_match;
wire id_wb_port_b_match;
// ID stall: EX
wire id_stall_1;
wire id_stall_2;
// ID forwarding: EX
wire id_forward_1;
wire id_forward_2;
// ID forwarding: MEM
wire id_forward_3;
wire id_forward_4;
// ID forwarding: WB
wire id_forward_5;
wire id_forward_6;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign id_port_a_is_zero = (id_gpr_port_a == 5'b0);
assign id_port_b_is_zero = (id_gpr_port_b == 5'b0);
// perform address check
assign id_ex_port_a_match = (id_gpr_port_a == ex_gpr_wa) & (~id_port_a_is_zero) & ex_gpr_we;
assign id_mem_port_a_match = (id_gpr_port_a == mem_gpr_wa) & (~id_port_a_is_zero) & mem_gpr_we;
assign id_wb_port_a_match = (id_gpr_port_a == wb_gpr_wa) & (~id_port_a_is_zero) & wb_gpr_we;
assign id_ex_port_b_match = (id_gpr_port_b == ex_gpr_wa) & (~id_port_b_is_zero) & ex_gpr_we;
assign id_mem_port_b_match = (id_gpr_port_b == mem_gpr_wa) & (~id_port_b_is_zero) & mem_gpr_we;
assign id_wb_port_b_match = (id_gpr_port_b == wb_gpr_wa) & (~id_port_b_is_zero) & wb_gpr_we;
// stall on ID if EX match and memory access (Load instruction on EX stage -> create Delay Slot).
assign id_stall_1 = id_ex_port_a_match & ex_data_read;
assign id_stall_2 = id_ex_port_b_match & ex_data_read;
// forward from EX if match (and if EX instruction isn't a load instruction. Store doesn't affect here)
assign id_forward_1 = id_ex_port_a_match & ~ex_data_read;
assign id_forward_2 = id_ex_port_b_match & ~ex_data_read;
//forward from MEM if match and no memory write.
// using ~mem_data_write here is redundant, because mem_data_write = ~mem_gpr_we.
assign id_forward_3 = id_mem_port_a_match;
assign id_forward_4 = id_mem_port_b_match;
// forward from WB
assign id_forward_5 = id_wb_port_a_match;
assign id_forward_6 = id_wb_port_b_match;
//--------------------------------------------------------------------------
// Assign stall signals
//--------------------------------------------------------------------------
assign wb_stall = mem_stall; // this can be 0 (never stall)
assign mem_stall = mem_exception_stall | mem_request_stall;
assign ex_stall = ex_exception_stall | ex_exu_stall | mem_stall;
assign id_stall = id_exception_stall | id_stall_1 | id_stall_2 | ex_stall ;
assign if_stall = if_exception_stall | if_mem_request_stall | id_stall;
//--------------------------------------------------------------------------
// forwarding control signals
// 00 -> ID (no forwarding)
// 01 -> EX
// 10 -> MEM
// 11 -> WB
//--------------------------------------------------------------------------
assign forward_port_a_select = (id_forward_1) ? 2'b01 : ((id_forward_3) ? 2'b10 : ((id_forward_5) ? 2'b11 : 2'b00));
assign forward_port_b_select = (id_forward_2) ? 2'b01 : ((id_forward_4) ? 2'b10 : ((id_forward_6) ? 2'b11 : 2'b00));
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 625 MHz (in range)
// Divide by 5 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(5),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire [15:0] pcspma_status_vector;
wire pcspma_status_link_status = pcspma_status_vector[0];
wire pcspma_status_link_synchronization = pcspma_status_vector[1];
wire pcspma_status_rudi_c = pcspma_status_vector[2];
wire pcspma_status_rudi_i = pcspma_status_vector[3];
wire pcspma_status_rudi_invalid = pcspma_status_vector[4];
wire pcspma_status_rxdisperr = pcspma_status_vector[5];
wire pcspma_status_rxnotintable = pcspma_status_vector[6];
wire pcspma_status_phy_link_status = pcspma_status_vector[7];
wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8];
wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10];
wire pcspma_status_duplex = pcspma_status_vector[12];
wire pcspma_status_remote_fault = pcspma_status_vector[13];
wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14];
wire [4:0] pcspma_config_vector;
assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign pcspma_config_vector[3] = 1'b0; // isolate
assign pcspma_config_vector[2] = 1'b0; // power down
assign pcspma_config_vector[1] = 1'b0; // loopback enable
assign pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] pcspma_an_config_vector;
assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign pcspma_an_config_vector[9] = 1'b0; // reserved
assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign pcspma_an_config_vector[6] = 1'b0; // reserved
assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
eth_pcspma (
// SGMII
.txp (phy_sgmii_tx_p),
.txn (phy_sgmii_tx_n),
.rxp (phy_sgmii_rx_p),
.rxn (phy_sgmii_rx_n),
// Ref clock from PHY
.refclk625_p (phy_sgmii_clk_p),
.refclk625_n (phy_sgmii_clk_n),
// async reset
.reset (rst_125mhz_int),
// clock and reset outputs
.clk125_out (phy_gmii_clk_int),
.clk625_out (),
.clk312_out (),
.rst_125_out (phy_gmii_rst_int),
.idelay_rdy_out (),
.mmcm_locked_out (),
// MAC clocking
.sgmii_clk_r (),
.sgmii_clk_f (),
.sgmii_clk_en (phy_gmii_clk_en_int),
// Speed control
.speed_is_10_100 (pcspma_status_speed != 2'b10),
.speed_is_100 (pcspma_status_speed == 2'b01),
// Internal GMII
.gmii_txd (phy_gmii_txd_int),
.gmii_tx_en (phy_gmii_tx_en_int),
.gmii_tx_er (phy_gmii_tx_er_int),
.gmii_rxd (phy_gmii_rxd_int),
.gmii_rx_dv (phy_gmii_rx_dv_int),
.gmii_rx_er (phy_gmii_rx_er_int),
.gmii_isolate (),
// Configuration
.configuration_vector (pcspma_config_vector),
.an_interrupt (),
.an_adv_config_vector (pcspma_an_config_vector),
.an_restart_config (1'b0),
// Status
.status_vector (pcspma_status_vector),
.signal_detect (1'b1)
);
wire [7:0] led_int;
// SGMII interface debug:
// SW12:4 (sw[0]) off for payload byte, on for status vector
// SW12:3 (sw[1]) off for LSB of status vector, on for MSB
assign led = sw[0] ? (sw[1] ? pcspma_status_vector[15:8] : pcspma_status_vector[7:0]) : led_int;
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
`resetall
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module nexys_video_demo (
input clk,
output tx,
input rx,
input [7:0] sw,
output [7:0] led
);
// Input 100MHz clock through a BUFG
wire clk100;
BUFG bufg100 (.I(clk), .O(clk100));
// Reset generator
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk100) begin
reset_cnt <= reset_cnt + !resetn;
end
// A simple GPIO peripheral connected to LEDs
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[7:0];
always @(posedge clk100) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {gpio[31:24], sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
// The picosoc
picosoc_noflash soc (
.clk (clk100),
.resetn (resetn ),
.ser_tx (tx),
.ser_rx (rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__TAP_PP_BLACKBOX_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tap (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
/*
module OpDecoder(clk, );
// we: Write Enable
input clk, we;
input [15:0]addr;
input [31:0]wdata;
output [31:0]data;
reg [3:0] state;
assign data = rom[addr];
always @ (posedge clk)
begin
if(we == 1) begin
rom[addr] = wdata;
end
end
initial
begin
$readmemh("rom.hex", rom);
end
endmodule
*/
`timescale 1ns / 1ps
// timescale [単位時間] / [丸め精度]
/*
module testbench();
reg clk;
// regは値を保持してくれる。
// wireは値を保持してくれない。
reg [15:0] counter;
reg [31:0] wdata;
reg we;
reg PCinc;
wire [31:0] data;
memory mem(clk, counter, data, wdata, we);
initial
begin
// 初期化ブロック。
// 出力する波形ファイルをここで指定する。
$dumpfile("memory.vcd");
$dumpvars(0, testbench);
PCinc = 0;
#1;
counter = 0;
#3;
PCinc = 1;
end
always // 常に実行される。
begin
// クロックを生成する。
// #1; は、1クロック待機する。
clk <= 1; #1;
clk <= 0; #1;
end
always @ (posedge clk)
begin
if(PCinc == 1) begin
counter = counter + 1;
end
if(counter === 1000) begin
$display ("Simulation end");
$finish;
end
end
endmodule
*/
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_vc709.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: RIFFA wrapper for the VC709 Development board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_vc709
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
// 4-Byte Name for this FPGA
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "V709")
(//Interface: CQ Ultrascale (RXR)
input M_AXIS_CQ_TVALID,
input M_AXIS_CQ_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
output M_AXIS_CQ_TREADY,
//Interface: RC Ultrascale (RXC)
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
//Interface: CC Ultrascale (TXC)
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
//Interface: RQ Ultrascale (TXR)
input S_AXIS_RQ_TREADY,
output S_AXIS_RQ_TVALID,
output S_AXIS_RQ_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
input USER_CLK,
input USER_RESET,
output [3:0] CFG_INTERRUPT_INT,
output [1:0] CFG_INTERRUPT_PENDING,
input [1:0] CFG_INTERRUPT_MSI_ENABLE,
input CFG_INTERRUPT_MSI_MASK_UPDATE,
input [31:0] CFG_INTERRUPT_MSI_DATA,
output [3:0] CFG_INTERRUPT_MSI_SELECT,
output [31:0] CFG_INTERRUPT_MSI_INT,
output [63:0] CFG_INTERRUPT_MSI_PENDING_STATUS,
input CFG_INTERRUPT_MSI_SENT,
input CFG_INTERRUPT_MSI_FAIL,
output [2:0] CFG_INTERRUPT_MSI_ATTR,
output CFG_INTERRUPT_MSI_TPH_PRESENT,
output [1:0] CFG_INTERRUPT_MSI_TPH_TYPE,
output [8:0] CFG_INTERRUPT_MSI_TPH_ST_TAG,
output [2:0] CFG_INTERRUPT_MSI_FUNCTION_NUMBER,
input [7:0] CFG_FC_CPLH,
input [11:0] CFG_FC_CPLD,
output [2:0] CFG_FC_SEL,
input [3:0] CFG_NEGOTIATED_WIDTH, // CONFIG_LINK_WIDTH
input [2:0] CFG_CURRENT_SPEED, // CONFIG_LINK_RATE
input [2:0] CFG_MAX_PAYLOAD, // CONFIG_MAX_PAYLOAD
input [2:0] CFG_MAX_READ_REQ, // CONFIG_MAX_READ_REQUEST
input [7:0] CFG_FUNCTION_STATUS, // [2] = CONFIG_BUS_MASTER_ENABLE
input [1:0] CFG_RCB_STATUS,
output PCIE_CQ_NP_REQ,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
// ALTERA, XILINX or ULTRASCALE
localparam C_VENDOR = "ULTRASCALE";
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Unconnected Wires (Used in classic interface)
wire wRxTlpReady_nc;
wire [C_PCI_DATA_WIDTH-1:0] wRxTlp_nc = 0;
wire wRxTlpEndFlag_nc = 0;
wire [`SIG_OFFSET_W-1:0] wRxTlpEndOffset_nc = 0;
wire wRxTlpStartFlag_nc = 0;
wire [`SIG_OFFSET_W-1:0] wRxTlpStartOffset_nc = 0;
wire wRxTlpValid_nc = 0;
wire [`SIG_BARDECODE_W-1:0] wRxTlpBarDecode_nc = 0;
wire wTxTlpReady_nc = 0;
wire [C_PCI_DATA_WIDTH-1:0] wTxTlp_nc;
wire wTxTlpEndFlag_nc;
wire [`SIG_OFFSET_W-1:0] wTxTlpEndOffset_nc;
wire wTxTlpStartFlag_nc;
wire [`SIG_OFFSET_W-1:0] wTxTlpStartOffset_nc;
wire wTxTlpValid_nc;
//--------------------------------------------------------------------------
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
assign clk = USER_CLK;
assign rst_in = USER_RESET;
assign config_completer_id = 0; // Not used in ULTRASCALE implementation
assign config_bus_master_enable = CFG_FUNCTION_STATUS[2];
assign config_link_width = {2'b00,CFG_NEGOTIATED_WIDTH}; // CONFIG_LINK_WIDTH
assign config_link_rate = CFG_CURRENT_SPEED[2]? 2'b11 : CFG_CURRENT_SPEED[2] ? 2'b10 : 2'b01;
assign config_max_payload_size = CFG_MAX_PAYLOAD; // CONFIG_MAX_PAYLOAD
assign config_max_read_request_size = CFG_MAX_READ_REQ; // CONFIG_MAX_READ_REQUEST
assign config_cpl_boundary_sel = CFG_RCB_STATUS[0];
assign config_interrupt_msienable = CFG_INTERRUPT_MSI_ENABLE[0];
assign config_max_cpl_data = CFG_FC_CPLD;
assign config_max_cpl_hdr = CFG_FC_CPLH;
assign CFG_FC_SEL = 3'b001; // Always display credit maximum for the signals below
assign CFG_INTERRUPT_MSI_INT = {31'b0,intr_msi_request};
assign CFG_INTERRUPT_MSI_SELECT = 0;
assign CFG_INTERRUPT_INT = 0;
assign CFG_INTERRUPT_PENDING = 0;
assign CFG_INTERRUPT_MSI_SELECT = 0;
assign CFG_INTERRUPT_MSI_PENDING_STATUS = {63'b0,intr_msi_request};
assign CFG_INTERRUPT_MSI_ATTR = 0;
assign CFG_INTERRUPT_MSI_TPH_PRESENT = 0;
assign CFG_INTERRUPT_MSI_TPH_ST_TAG = 0;
assign CFG_INTERRUPT_MSI_TPH_TYPE = 0;
assign CFG_INTERRUPT_MSI_FUNCTION_NUMBER = 0;
assign intr_msi_rdy = CFG_INTERRUPT_MSI_SENT & ~CFG_INTERRUPT_MSI_FAIL;
assign PCIE_CQ_NP_REQ = 1;
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (wTxTlp_nc),
.TX_TLP_VALID (wTxTlpValid_nc),
.TX_TLP_START_FLAG (wTxTlpStartFlag_nc),
.TX_TLP_START_OFFSET (wTxTlpStartOffset_nc),
.TX_TLP_END_FLAG (wTxTlpEndFlag_nc),
.TX_TLP_END_OFFSET (wTxTlpEndOffset_nc),
.RX_TLP_READY (wRxTlpReady_nc),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (wRxTlp_nc),
.RX_TLP_VALID (wRxTlpValid_nc),
.RX_TLP_START_FLAG (wRxTlpStartFlag_nc),
.RX_TLP_START_OFFSET (wRxTlpStartOffset_nc),
.RX_TLP_END_FLAG (wRxTlpEndFlag_nc),
.RX_TLP_END_OFFSET (wRxTlpEndOffset_nc),
.RX_TLP_BAR_DECODE (wRxTlpBarDecode_nc),
.TX_TLP_READY (wTxTlpReady_nc),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rstsudo),
/*AUTOINST*/
// Outputs
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID),
.M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST),
.M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (M_AXIS_RC_TVALID),
.M_AXIS_RC_TLAST (M_AXIS_RC_TLAST),
.M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY));
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data MMU top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of all DMMU blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dmmu_top.v,v $
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.7.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.7 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/14 15:34:02 simons
// Lapsus fixed.
//
// Revision 1.4 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/17 08:03:35 lampret
// *** empty log message ***
//
// Revision 1.2 2001/07/22 03:31:53 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
//
// Data MMU
//
module or1200_dmmu_top(
// Rst and clk
clk, rst,
// CPU i/f
dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i,
dcpu_tag_o, dcpu_err_o,
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// DC i/f
qmemdmmu_err_i, qmemdmmu_tag_i, qmemdmmu_adr_o, qmemdmmu_cycstb_o, qmemdmmu_ci_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// CPU I/F
//
input dc_en;
input dmmu_en;
input supv;
input [aw-1:0] dcpu_adr_i;
input dcpu_cycstb_i;
input dcpu_we_i;
output [3:0] dcpu_tag_o;
output dcpu_err_o;
//
// SPR access
//
input spr_cs;
input spr_write;
input [aw-1:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// DC I/F
//
input qmemdmmu_err_i;
input [3:0] qmemdmmu_tag_i;
output [aw-1:0] qmemdmmu_adr_o;
output qmemdmmu_cycstb_o;
output qmemdmmu_ci_o;
//
// Internal wires and regs
//
wire dtlb_spr_access;
wire [31:`OR1200_DMMU_PS] dtlb_ppn;
wire dtlb_hit;
wire dtlb_uwe;
wire dtlb_ure;
wire dtlb_swe;
wire dtlb_sre;
wire [31:0] dtlb_dat_o;
wire dtlb_en;
wire dtlb_ci;
wire fault;
wire miss;
`ifdef OR1200_NO_DMMU
`else
reg dtlb_done;
reg [31:`OR1200_DMMU_PS] dcpu_vpn_r;
`endif
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-10 v 0
// dtlbwYtrX: ppn 31-10 swe 9 sre 8 uwe 7 ure 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
// 1 bit for cache inhibit
`ifdef OR1200_NO_DMMU
//
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign qmemdmmu_adr_o = dcpu_adr_i;
assign dcpu_tag_o = qmemdmmu_tag_i;
assign qmemdmmu_cycstb_o = dcpu_cycstb_i;
assign dcpu_err_o = qmemdmmu_err_i;
assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// DTLB SPR access
//
// 0A00 - 0AFF dtlbmr w0
// 0A00 - 0A3F dtlbmr w0 [63:0]
//
// 0B00 - 0BFF dtlbtr w0
// 0B00 - 0B3F dtlbtr w0 [63:0]
//
assign dtlb_spr_access = spr_cs;
//
// Tags:
//
// OR1200_DTAG_TE - TLB miss Exception
// OR1200_DTAG_PE - Page fault Exception
//
assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemdmmu_tag_i;
//
// dcpu_err_o
//
assign dcpu_err_o = miss | fault | qmemdmmu_err_i;
//
// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.
//
always @(posedge clk or posedge rst)
if (rst)
dtlb_done <= #1 1'b0;
else if (dtlb_en)
dtlb_done <= #1 dcpu_cycstb_i;
else
dtlb_done <= #1 1'b0;
//
// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.
//
assign qmemdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;
//assign qmemdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
//
// Cache Inhibit
//
assign qmemdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
//
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
//
always @(posedge clk or posedge rst)
if (rst)
dcpu_vpn_r <= #1 {31-`OR1200_DMMU_PS{1'b0}};
else
dcpu_vpn_r <= #1 dcpu_adr_i[31:`OR1200_DMMU_PS];
//
// Physical address is either translated virtual address or
// simply equal when DMMU is disabled
//
// assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
//
// Output to SPRS unit
//
assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
//
// Page fault exception logic
//
assign fault = dtlb_done &
( (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled
|| (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled
|| (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled
|| (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled
//
// TLB Miss exception logic
//
assign miss = dtlb_done & !dtlb_hit;
//
// DTLB Enable
//
assign dtlb_en = dmmu_en & dcpu_cycstb_i;
//
// Instantiation of DTLB
//
or1200_dmmu_tlb or1200_dmmu_tlb(
// Rst and clk
.clk(clk),
.rst(rst),
// I/F for translation
.tlb_en(dtlb_en),
.vaddr(dcpu_adr_i),
.hit(dtlb_hit),
.ppn(dtlb_ppn),
.uwe(dtlb_uwe),
.ure(dtlb_ure),
.swe(dtlb_swe),
.sre(dtlb_sre),
.ci(dtlb_ci),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// SPR access
.spr_cs(dtlb_spr_access),
.spr_write(spr_write),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_i),
.spr_dat_o(dtlb_dat_o)
);
`endif
endmodule
|
//
// usb 3.0 protocol layer
//
// Copyright (c) 2013 Marshall H.
// All rights reserved.
// This code is released under the terms of the simplified BSD license.
// See LICENSE.TXT for details.
//
module usb3_protocol (
input wire slow_clk,
input wire local_clk,
input wire ext_clk,
input wire reset_n,
input wire [4:0] ltssm_state,
// link interface
input wire rx_tp,
input wire rx_tp_hosterr,
input wire rx_tp_retry,
input wire rx_tp_pktpend,
input wire [3:0] rx_tp_subtype,
input wire [3:0] rx_tp_endp,
input wire [4:0] rx_tp_nump,
input wire [4:0] rx_tp_seq,
input wire [15:0] rx_tp_stream,
input wire rx_dph,
input wire rx_dph_eob,
input wire rx_dph_setup,
input wire rx_dph_pktpend,
input wire [3:0] rx_dph_endp,
input wire [4:0] rx_dph_seq,
input wire [15:0] rx_dph_len,
input wire rx_dpp_start,
input wire rx_dpp_done,
input wire rx_dpp_crcgood,
output reg tx_tp_a,
output reg tx_tp_a_retry,
output reg tx_tp_a_dir,
output reg [3:0] tx_tp_a_subtype,
output reg [3:0] tx_tp_a_endp,
output reg [4:0] tx_tp_a_nump,
output reg [4:0] tx_tp_a_seq,
output reg [15:0] tx_tp_a_stream,
input wire tx_tp_a_ack,
output reg tx_tp_b,
output reg tx_tp_b_retry,
output reg tx_tp_b_dir,
output reg [3:0] tx_tp_b_subtype,
output reg [3:0] tx_tp_b_endp,
output reg [4:0] tx_tp_b_nump,
output reg [4:0] tx_tp_b_seq,
output reg [15:0] tx_tp_b_stream,
input wire tx_tp_b_ack,
output reg tx_tp_c,
output reg tx_tp_c_retry,
output reg tx_tp_c_dir,
output reg [3:0] tx_tp_c_subtype,
output reg [3:0] tx_tp_c_endp,
output reg [4:0] tx_tp_c_nump,
output reg [4:0] tx_tp_c_seq,
output reg [15:0] tx_tp_c_stream,
input wire tx_tp_c_ack,
output reg tx_dph,
output reg tx_dph_eob,
output reg tx_dph_dir,
output reg [3:0] tx_dph_endp,
output reg [4:0] tx_dph_seq,
output reg [15:0] tx_dph_len,
input wire tx_dpp_ack,
input wire tx_dpp_done,
input wire [8:0] buf_in_addr,
input wire [31:0] buf_in_data,
input wire buf_in_wren,
output wire buf_in_ready,
input wire buf_in_commit,
input wire [10:0] buf_in_commit_len,
output wire buf_in_commit_ack,
input wire [8:0] buf_out_addr,
output wire [31:0] buf_out_q,
output wire [10:0] buf_out_len,
output wire buf_out_hasdata,
input wire buf_out_arm,
output wire buf_out_arm_ack,
// external interface
input wire [8:0] ext_buf_in_addr,
input wire [31:0] ext_buf_in_data,
input wire ext_buf_in_wren,
output reg ext_buf_in_request,
output wire ext_buf_in_ready,
input wire ext_buf_in_commit,
input wire [10:0] ext_buf_in_commit_len,
output wire ext_buf_in_commit_ack,
input wire [8:0] ext_buf_out_addr,
output wire [31:0] ext_buf_out_q,
output wire [10:0] ext_buf_out_len,
output wire ext_buf_out_hasdata,
input wire ext_buf_out_arm,
output wire ext_buf_out_arm_ack,
output wire [1:0] endp_mode_rx,
output wire [1:0] endp_mode_tx,
output wire vend_req_act,
output wire [7:0] vend_req_request,
output wire [15:0] vend_req_val,
output wire [6:0] dev_addr,
output wire configured,
output reg err_miss_rx,
output reg err_miss_tx,
output reg err_tp_subtype,
output reg err_missed_dpp_start,
output reg err_missed_dpp_done
);
`include "usb3_const.v"
// mux bram signals
wire [8:0] ep0_buf_in_addr = rx_endp == SEL_ENDP0 ? buf_in_addr : 'h0;
wire [31:0] ep0_buf_in_data = rx_endp == SEL_ENDP0 ? buf_in_data : 'h0;
wire ep0_buf_in_wren = rx_endp == SEL_ENDP0 ? buf_in_wren : 'h0;
wire ep0_buf_in_ready;
wire ep0_buf_in_commit = rx_endp == SEL_ENDP0 ? buf_in_commit : 'h0;
wire [10:0] ep0_buf_in_commit_len = rx_endp == SEL_ENDP0 ? buf_in_commit_len : 'h0;
wire ep0_buf_in_commit_ack;
wire [8:0] ep0_buf_out_addr = tx_endp == SEL_ENDP0 ? buf_out_addr : 'h0;
wire [31:0] ep0_buf_out_q;
wire [10:0] ep0_buf_out_len;
wire ep0_buf_out_hasdata;
wire ep0_buf_out_arm = tx_endp == SEL_ENDP0 ? buf_out_arm : 'h0;
wire ep0_buf_out_arm_ack;
wire [8:0] ep1_buf_out_addr = tx_endp == SEL_ENDP1 ? buf_out_addr : 'h0;
wire [31:0] ep1_buf_out_q;
wire [10:0] ep1_buf_out_len;
wire ep1_buf_out_hasdata;
wire ep1_buf_out_arm = tx_endp == SEL_ENDP1 ? buf_out_arm : 'h0;
wire ep1_buf_out_arm_ack;
wire [8:0] ep2_buf_in_addr = rx_endp == SEL_ENDP2 ? buf_in_addr : 'h0;
wire [31:0] ep2_buf_in_data = rx_endp == SEL_ENDP2 ? buf_in_data : 'h0;
wire ep2_buf_in_wren = rx_endp == SEL_ENDP2 ? buf_in_wren : 'h0;
wire ep2_buf_in_ready;
wire ep2_buf_in_commit = rx_endp == SEL_ENDP2 ? buf_in_commit : 'h0;
wire [10:0] ep2_buf_in_commit_len = rx_endp == SEL_ENDP2 ? buf_in_commit_len : 'h0;
wire ep2_buf_in_commit_ack;
assign buf_in_ready = rx_endp == SEL_ENDP0 ? ep0_buf_in_ready :
rx_endp == SEL_ENDP2 ? ep2_buf_in_ready : 'h0;
assign buf_in_commit_ack = rx_endp == SEL_ENDP0 ? ep0_buf_in_commit_ack :
rx_endp == SEL_ENDP2 ? ep2_buf_in_commit_ack : 'h0;
assign buf_out_q = tx_endp == SEL_ENDP0 ? ep0_buf_out_q :
tx_endp == SEL_ENDP1 ? ep1_buf_out_q : 'h0;
assign buf_out_len = tx_endp == SEL_ENDP0 ? ep0_buf_out_len :
tx_endp == SEL_ENDP1 ? ep1_buf_out_len : 'h0;
assign buf_out_hasdata = tx_endp == SEL_ENDP0 ? ep0_buf_out_hasdata :
tx_endp == SEL_ENDP1 ? ep1_buf_out_hasdata : 'h0;
assign buf_out_arm_ack = tx_endp == SEL_ENDP0 ? ep0_buf_out_arm_ack :
tx_endp == SEL_ENDP1 ? ep1_buf_out_arm_ack : 'h0;
assign endp_mode_tx = tx_endp == SEL_ENDP1 ? EP1_MODE :
tx_endp == SEL_ENDP2 ? EP2_MODE : EP_MODE_CONTROL;
assign endp_mode_rx = rx_endp == SEL_ENDP1 ? EP1_MODE :
rx_endp == SEL_ENDP2 ? EP2_MODE : EP_MODE_CONTROL;
parameter [3:0] SEL_ENDP0 = 4'd0,
SEL_ENDP1 = 4'd1,
SEL_ENDP2 = 4'd2,
SEL_ENDP3 = 4'd3,
SEL_ENDP4 = 4'd4,
SEL_ENDP5 = 4'd5,
SEL_ENDP6 = 4'd6,
SEL_ENDP7 = 4'd7;
parameter [1:0] EP_MODE_CONTROL = 2'd0,
EP_MODE_ISOCH = 2'd1,
EP_MODE_BULK = 2'd2,
EP_MODE_INTERRUPT = 2'd3;
// assign endpoint modes here and also
// in the descriptor strings
wire [1:0] EP1_MODE = EP_MODE_BULK;
wire [1:0] EP2_MODE = EP_MODE_BULK;
reg [4:0] rx_state;
parameter [4:0] RX_RESET = 'd0,
RX_IDLE = 'd1,
RX_0 = 'd2,
RX_1 = 'd3,
RX_2 = 'd4,
RX_TP_0 = 'd10,
RX_TP_1 = 'd11,
RX_TP_2 = 'd12,
RX_DPH_0 = 'd20,
RX_DPH_1 = 'd21,
RX_DPH_2 = 'd22;
reg [4:0] tx_state;
parameter [4:0] TX_RESET = 'd0,
TX_IDLE = 'd1,
TX_DP_WAITDATA = 'd2,
TX_DP_0 = 'd3,
TX_DP_1 = 'd4,
TX_DP_2 = 'd5,
TX_DP_3 = 'd6,
TX_DP_NRDY = 'd7,
TX_DP_ERDY = 'd8;
reg [4:0] in_dpp_seq /* synthesis noprune */;
reg [4:0] out_dpp_seq /* synthesis noprune */;
wire reset_dp_seq;
reg [15:0] out_length;
reg [4:0] out_nump;
reg do_send_dpp;
reg [10:0] recv_count;
reg [10:0] dc;
reg [3:0] rx_endp;
reg [3:0] tx_endp;
always @(posedge local_clk) begin
tx_tp_a <= 0;
tx_tp_b <= 0;
tx_tp_c <= 0;
tx_dph <= 0;
do_send_dpp <= 0;
ext_buf_in_request <= 0;
`INC(dc);
`INC(recv_count);
case(rx_state)
RX_RESET: rx_state <= RX_IDLE;
RX_IDLE: begin
if(rx_dph) begin
// receiving data packet header, link layer is stuffing payload
// into the endpoint buffer
in_dpp_seq <= rx_dph_seq;
rx_endp <= rx_dph_endp;
rx_state <= RX_DPH_0;
recv_count <= 0;
end else
if(rx_tp) begin
// receving transaction packet, could be ACK or something else
rx_state <= RX_TP_0;
end
end
RX_DPH_0: begin
if(rx_dpp_start) begin
// received DPP start ordered set
rx_state <= RX_DPH_1;
end
if(ltssm_state != LT_U0 || recv_count == 20) begin
// we waited too long for DPP start and it hasn't come yet
err_missed_dpp_start <= 1;
rx_state <= RX_DPH_2;
end
end
RX_DPH_1: begin
if(rx_dpp_done) begin
if(rx_dpp_crcgood) `INC(in_dpp_seq);
err_missed_dpp_start <= 0;
err_missed_dpp_done <= 0;
rx_state <= RX_DPH_2;
end
if(ltssm_state != LT_U0 || recv_count == 270) begin
err_missed_dpp_done <= 1;
rx_state <= RX_DPH_2;
end
end
RX_DPH_2: begin
// send ACK
tx_tp_a <= 1'b1;
tx_tp_a_retry <= ( rx_dpp_crcgood &&
!err_missed_dpp_start &&
!err_missed_dpp_done
) ? LP_TP_NORETRY : LP_TP_RETRY;
tx_tp_a_dir <= LP_TP_HOSTTODEVICE;
tx_tp_a_subtype <= LP_TP_SUB_ACK;
tx_tp_a_endp <= rx_dph_endp;
tx_tp_a_nump <= 5'h1;
tx_tp_a_seq <= in_dpp_seq;
tx_tp_a_stream <= 16'h0;
if(tx_tp_a_ack) rx_state <= RX_IDLE;
end
RX_TP_0: begin
// unless otherwise directed, immediately return
rx_state <= RX_IDLE;
case(rx_tp_subtype)
LP_TP_SUB_ACK: begin
if(rx_tp_pktpend && rx_tp_nump > 0) begin
// IN, expecting us to send data
// switch endpoint mux
tx_endp <= rx_tp_endp;
out_nump <= rx_tp_nump;
out_dpp_seq <= rx_tp_seq;
do_send_dpp <= 1;
end else begin
// ACK from a previously sent packet
end
end
LP_TP_SUB_NRDY: begin
end
LP_TP_SUB_ERDY: begin
end
LP_TP_SUB_STATUS: begin
// for control transfers
tx_tp_b <= 1'b1;
tx_tp_b_retry <= LP_TP_NORETRY;
tx_tp_b_dir <= LP_TP_HOSTTODEVICE;
tx_tp_b_subtype <= LP_TP_SUB_ACK;
tx_tp_b_endp <= rx_tp_endp;
tx_tp_b_nump <= 5'h0;
tx_tp_b_seq <= in_dpp_seq;
tx_tp_b_stream <= 16'h0;
if(!tx_tp_b_ack) rx_state <= rx_state;
end
LP_TP_SUB_PING: begin
end
default: begin
// invalid subtype
err_tp_subtype <= 1;
end
endcase
end
RX_0: begin
end
RX_1: begin
end
endcase
case(tx_state)
TX_RESET: tx_state <= TX_IDLE;
TX_IDLE: begin
if(do_send_dpp) begin
// if you had multiple IN endpoints you would rewrite this part
if(tx_endp == SEL_ENDP1) ext_buf_in_request <= 1;
if(buf_out_hasdata) begin
// data is already in EP buffer
// note: overall transfer length
out_length <= buf_out_len;
tx_state <= TX_DP_0;
end else begin
// no data is ready yet, send NRDY and wait
tx_state <= TX_DP_NRDY;
end
end
end
TX_DP_NRDY: begin
tx_tp_c <= 1'b1;
tx_tp_c_retry <= LP_TP_NORETRY;
tx_tp_c_dir <= LP_TP_HOSTTODEVICE;
tx_tp_c_subtype <= LP_TP_SUB_NRDY;
tx_tp_c_endp <= tx_endp;
tx_tp_c_nump <= 5'h0;
tx_tp_c_seq <= 5'h0;
tx_tp_c_stream <= 16'h0;
if(tx_tp_c_ack) tx_state <= TX_DP_WAITDATA;
end
TX_DP_WAITDATA: begin
if(tx_endp == SEL_ENDP1) ext_buf_in_request <= 1;
if(buf_out_hasdata) begin
// data is already in EP buffer
// note: overall transfer length
out_length <= buf_out_len;
tx_state <= TX_DP_ERDY;
end
end
TX_DP_ERDY: begin
tx_tp_c <= 1'b1;
tx_tp_c_retry <= LP_TP_NORETRY;
tx_tp_c_dir <= LP_TP_HOSTTODEVICE;
tx_tp_c_subtype <= LP_TP_SUB_ERDY;
tx_tp_c_endp <= tx_endp;
tx_tp_c_nump <= 5'h1;
tx_tp_c_seq <= 5'h0;
tx_tp_c_stream <= 16'h0;
if(tx_tp_c_ack) tx_state <= TX_DP_0;
end
TX_DP_0: begin
tx_dph <= 1'b1;
tx_dph_eob <= 0; // TODO
tx_dph_dir <= tx_endp == 0 ? 0 : LP_TP_DEVICETOHOST; // rx_tp_endp
tx_dph_endp <= tx_endp;
tx_dph_seq <= out_dpp_seq;
tx_dph_len <= out_length; // TODO
dc <= 0;
if(tx_dpp_ack) tx_state <= TX_DP_1;
end
TX_DP_1: begin
if(tx_dpp_done) tx_state <= TX_IDLE;
end
endcase
if(rx_state != RX_IDLE) begin
// missed an incoming transaction!
if(rx_dph || rx_tp) err_miss_rx <= 1;
end
if(tx_state != TX_IDLE) begin
if(do_send_dpp) err_miss_tx <= 1;
end
if(~reset_n) begin
rx_state <= RX_RESET;
tx_state <= TX_RESET;
end
if(~reset_n) begin
err_miss_rx <= 0;
err_miss_tx <= 0;
err_tp_subtype <= 0;
err_missed_dpp_start <= 0;
err_missed_dpp_done <= 0;
end
end
////////////////////////////////////////////////////////////
//
// ENDPOINT 0 IN/OUT
//
////////////////////////////////////////////////////////////
usb3_ep0 iu3ep0 (
.slow_clk ( slow_clk ),
.local_clk ( local_clk ),
.reset_n ( reset_n ),
.buf_in_addr ( ep0_buf_in_addr ),
.buf_in_data ( ep0_buf_in_data ),
.buf_in_wren ( ep0_buf_in_wren ),
.buf_in_ready ( ep0_buf_in_ready ),
.buf_in_commit ( ep0_buf_in_commit ),
.buf_in_commit_len ( ep0_buf_in_commit_len ),
.buf_in_commit_ack ( ep0_buf_in_commit_ack ),
.buf_out_addr ( ep0_buf_out_addr ),
.buf_out_q ( ep0_buf_out_q ),
.buf_out_len ( ep0_buf_out_len ),
.buf_out_hasdata ( ep0_buf_out_hasdata ),
.buf_out_arm ( ep0_buf_out_arm ),
.buf_out_arm_ack ( ep0_buf_out_arm_ack ),
.vend_req_act ( vend_req_act ),
.vend_req_request ( vend_req_request ),
.vend_req_val ( vend_req_val ),
.dev_addr ( dev_addr ),
.configured ( configured ),
.reset_dp_seq ( reset_dp_seq )
//.err_setup_pkt ( err_setup_pkt )
);
////////////////////////////////////////////////////////////
//
// ENDPOINT 1 IN (DATA TO PC)
//
////////////////////////////////////////////////////////////
usb3_ep iu3ep1 (
.slow_clk ( slow_clk ),
.local_clk ( local_clk ),
.rd_clk ( local_clk ),
.wr_clk ( ext_clk ),
.reset_n ( reset_n ),
.buf_in_addr ( ext_buf_in_addr ),
.buf_in_data ( ext_buf_in_data ),
.buf_in_wren ( ext_buf_in_wren ),
.buf_in_ready ( ext_buf_in_ready ),
.buf_in_commit ( ext_buf_in_commit ),
.buf_in_commit_len ( ext_buf_in_commit_len ),
.buf_in_commit_ack ( ext_buf_in_commit_ack ),
.buf_out_addr ( ep1_buf_out_addr ),
.buf_out_q ( ep1_buf_out_q ),
.buf_out_len ( ep1_buf_out_len ),
.buf_out_hasdata ( ep1_buf_out_hasdata ),
.buf_out_arm ( ep1_buf_out_arm ),
.buf_out_arm_ack ( ep1_buf_out_arm_ack ),
.mode ( EP1_MODE )
);
////////////////////////////////////////////////////////////
//
// ENDPOINT 2 OUT (DATA FROM PC)
//
////////////////////////////////////////////////////////////
usb3_ep iu3ep2 (
.slow_clk ( slow_clk ),
.local_clk ( local_clk ),
.rd_clk ( ext_clk ),
.wr_clk ( local_clk ),
.reset_n ( reset_n ),
.buf_in_addr ( ep2_buf_in_addr ),
.buf_in_data ( ep2_buf_in_data ),
.buf_in_wren ( ep2_buf_in_wren ),
.buf_in_ready ( ep2_buf_in_ready ),
.buf_in_commit ( ep2_buf_in_commit ),
.buf_in_commit_len ( ep2_buf_in_commit_len ),
.buf_in_commit_ack ( ep2_buf_in_commit_ack ),
.buf_out_addr ( ext_buf_out_addr ),
.buf_out_q ( ext_buf_out_q ),
.buf_out_len ( ext_buf_out_len ),
.buf_out_hasdata ( ext_buf_out_hasdata ),
.buf_out_arm ( ext_buf_out_arm ),
.buf_out_arm_ack ( ext_buf_out_arm_ack ),
.mode ( EP2_MODE )
);
endmodule
|
// A simple top module
module game_graph_simple_top
(
input wire clk, reset,
input wire [1:0] btn,
input wire [1:0] sw,
output wire hsync, vsync,
output wire [2:0] rgb
);
// signal declaration
wire [9:0] pixel_x, pixel_y;
wire video_on, pixel_tick;
reg [2:0] rgb_reg;
wire [2:0] rgb_next;
// body
// instantiate vga sync circuit
vga_sync vsync_unit
(.clk(clk), .reset(reset), .hsync(hsync), .vsync(vsync),
.video_on(video_on), .p_tick(pixel_tick),
.pixel_x(pixel_x), .pixel_y(pixel_y));
// instantiate graphic generator
game_graph_simple game_graph_simple_unit
(.clk(clk), .reset(reset), .btn(btn), .sw(sw),
.video_on(video_on), .pix_x(pixel_x),
.pix_y(pixel_y), .graph_rgb(rgb_next));
// A buffer must be added !!!
// IMPORTTANT
// This is different from the chinese guide
// rgb buffer
always @(posedge clk)
if (pixel_tick)
rgb_reg <= rgb_next;
// final output
assign rgb = rgb_reg;
endmodule
|
module block #(
parameter M = 8
) (
input [M-1:0] in,
input clk,
input start,
output [M-1:0] out
);
if (`CONFIG_BERLEKAMP) begin
reg [M-2:0] b = 0;
reg i = 0;
reg s = 0;
always @(posedge clk) begin
s <= start;
if (start) begin
b <= b[M-2:0];
i <= in[M-1:0];
end else begin
i <= in[M-2];
b <= b << 1;
end
end
berlekamp_inverter #(M) inv(
.clk(clk),
.start(s),
.standard_in(i),
.standard_out(out)
);
end else
fermat_inverter #(M) inv(
.clk(clk),
.start(start),
.standard_in(in),
.dual_out(out)
);
endmodule
module xilinx_inverter #(
parameter M = 8
) (
input [M-1:0] data_in,
input clk_in,
input start,
output [M-1:0] data_out
);
wire [M-1:0] data_in0;
wire start0;
wire [M-1:0] data_out0;
BUFG u_bufg (
.I(clk_in),
.O(clk)
);
pipeline #(2) u_output [M-1:0] (
.clk(clk),
.i({data_out0}),
.o({data_out})
);
pipeline #(2) u_input [M:0] (
.clk(clk),
.i({data_in, start}),
.o({data_in0, start0})
);
genvar i;
for (i = 0; i < 100; i = i + 1) begin : FOO
wire [M-1:0] out;
if (i == 0)
block #(M) inv(
.clk(clk),
.start(start0),
.in(data_in0),
.out(out)
);
else
block #(M) inv(
.clk(clk),
.start(start0),
.in(FOO[i-1].out),
.out(out)
);
end
assign data_out0 = FOO[99].out;
endmodule
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_7 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4,
read_5,
write_5,
EN_write_5,
read_6,
write_6,
EN_write_6
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
output [DATA_SZ-1:0] read_5;
input [DATA_SZ-1:0] write_5;
input EN_write_5;
output [DATA_SZ-1:0] read_6;
input [DATA_SZ-1:0] write_6;
input EN_write_6;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
wire [DATA_SZ-1:0] wire_6;
wire [DATA_SZ-1:0] wire_7;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign wire_6 = EN_write_5 ? write_5 : wire_5;
assign wire_7 = EN_write_6 ? write_6 : wire_6;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
assign read_5 = wire_5;
assign read_6 = wire_6;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_7;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:18:55 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_0/bram_1024_0_sim_netlist.v
// Design : bram_1024_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bram_1024_0,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bram_1024_0
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [19:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [19:0]douta;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [19:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [19:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bram_1024_0.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_0.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *)
(* C_READ_DEPTH_B = "1024" *)
(* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "20" *)
(* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
bram_1024_0_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[19:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[19:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bram_1024_0_blk_mem_gen_generic_cstr
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bram_1024_0_blk_mem_gen_prim_width
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_0_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bram_1024_0_blk_mem_gen_prim_wrapper_init
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000001D0000001900000015000000110000000D000000090000000500000001),
.INIT_01(256'h0000011D0000011900000115000001110000010D000001090000010500000101),
.INIT_02(256'h0000021D0000021900000215000002110000020D000002090000020500000201),
.INIT_03(256'h0000031D0000031900000315000003110000030D000003090000030500000301),
.INIT_04(256'h0000041D0000041900000415000004110000040D000004090000040500000401),
.INIT_05(256'h0000051D0000051900000515000005110000050D000005090000050500000501),
.INIT_06(256'h0000061D0000061900000615000006110000060D000006090000060500000601),
.INIT_07(256'h0000071D0000071900000715000007110000070D000007090000070500000701),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,dina[19:15],1'b0,1'b0,1'b0,dina[14:10],1'b0,1'b0,1'b0,dina[9:5],1'b0,1'b0,1'b0,dina[4:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ,douta[19:15],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ,douta[14:10],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ,douta[9:5],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ,douta[4:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bram_1024_0_blk_mem_gen_top
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bram_1024_0.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_0.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "20" *) (* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bram_1024_0_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [19:0]dinb;
output [19:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [19:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [19:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bram_1024_0_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bram_1024_0_blk_mem_gen_v8_3_5_synth
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_0_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// can_register_asyn.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/03/20 16:58:50 mohor
// unix.
//
// Revision 1.4 2003/03/11 16:32:34 mohor
// timescale.v is used for simulation only.
//
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register_asyn
( data_in,
data_out,
we,
clk,
rst
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ (posedge clk or posedge rst)
begin
if (rst) // asynchronous reset
data_out<=#1 RESET_VALUE;
else if (we) // write
data_out<=#1 data_in;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Apr 14 18:39:27 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top bd_auto_cc_0 -prefix
// bd_auto_cc_0_ bd_auto_cc_0_sim_netlist.v
// Design : bd_auto_cc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_ARADDR_RIGHT = "29" *) (* C_ARADDR_WIDTH = "32" *) (* C_ARBURST_RIGHT = "16" *)
(* C_ARBURST_WIDTH = "2" *) (* C_ARCACHE_RIGHT = "11" *) (* C_ARCACHE_WIDTH = "4" *)
(* C_ARID_RIGHT = "61" *) (* C_ARID_WIDTH = "4" *) (* C_ARLEN_RIGHT = "21" *)
(* C_ARLEN_WIDTH = "8" *) (* C_ARLOCK_RIGHT = "15" *) (* C_ARLOCK_WIDTH = "1" *)
(* C_ARPROT_RIGHT = "8" *) (* C_ARPROT_WIDTH = "3" *) (* C_ARQOS_RIGHT = "0" *)
(* C_ARQOS_WIDTH = "4" *) (* C_ARREGION_RIGHT = "4" *) (* C_ARREGION_WIDTH = "4" *)
(* C_ARSIZE_RIGHT = "18" *) (* C_ARSIZE_WIDTH = "3" *) (* C_ARUSER_RIGHT = "0" *)
(* C_ARUSER_WIDTH = "0" *) (* C_AR_WIDTH = "65" *) (* C_AWADDR_RIGHT = "29" *)
(* C_AWADDR_WIDTH = "32" *) (* C_AWBURST_RIGHT = "16" *) (* C_AWBURST_WIDTH = "2" *)
(* C_AWCACHE_RIGHT = "11" *) (* C_AWCACHE_WIDTH = "4" *) (* C_AWID_RIGHT = "61" *)
(* C_AWID_WIDTH = "4" *) (* C_AWLEN_RIGHT = "21" *) (* C_AWLEN_WIDTH = "8" *)
(* C_AWLOCK_RIGHT = "15" *) (* C_AWLOCK_WIDTH = "1" *) (* C_AWPROT_RIGHT = "8" *)
(* C_AWPROT_WIDTH = "3" *) (* C_AWQOS_RIGHT = "0" *) (* C_AWQOS_WIDTH = "4" *)
(* C_AWREGION_RIGHT = "4" *) (* C_AWREGION_WIDTH = "4" *) (* C_AWSIZE_RIGHT = "18" *)
(* C_AWSIZE_WIDTH = "3" *) (* C_AWUSER_RIGHT = "0" *) (* C_AWUSER_WIDTH = "0" *)
(* C_AW_WIDTH = "65" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_IS_ACLK_ASYNC = "1" *) (* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_BID_RIGHT = "2" *)
(* C_BID_WIDTH = "4" *) (* C_BRESP_RIGHT = "0" *) (* C_BRESP_WIDTH = "2" *)
(* C_BUSER_RIGHT = "0" *) (* C_BUSER_WIDTH = "0" *) (* C_B_WIDTH = "6" *)
(* C_FAMILY = "artix7" *) (* C_FIFO_AR_WIDTH = "65" *) (* C_FIFO_AW_WIDTH = "65" *)
(* C_FIFO_B_WIDTH = "6" *) (* C_FIFO_R_WIDTH = "39" *) (* C_FIFO_W_WIDTH = "37" *)
(* C_M_AXI_ACLK_RATIO = "2" *) (* C_RDATA_RIGHT = "3" *) (* C_RDATA_WIDTH = "32" *)
(* C_RID_RIGHT = "35" *) (* C_RID_WIDTH = "4" *) (* C_RLAST_RIGHT = "0" *)
(* C_RLAST_WIDTH = "1" *) (* C_RRESP_RIGHT = "1" *) (* C_RRESP_WIDTH = "2" *)
(* C_RUSER_RIGHT = "0" *) (* C_RUSER_WIDTH = "0" *) (* C_R_WIDTH = "39" *)
(* C_SYNCHRONIZER_STAGE = "3" *) (* C_S_AXI_ACLK_RATIO = "1" *) (* C_WDATA_RIGHT = "5" *)
(* C_WDATA_WIDTH = "32" *) (* C_WID_RIGHT = "37" *) (* C_WID_WIDTH = "0" *)
(* C_WLAST_RIGHT = "0" *) (* C_WLAST_WIDTH = "1" *) (* C_WSTRB_RIGHT = "1" *)
(* C_WSTRB_WIDTH = "4" *) (* C_WUSER_RIGHT = "0" *) (* C_WUSER_WIDTH = "0" *)
(* C_W_WIDTH = "37" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ACLK_RATIO = "2" *)
(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *)
(* P_FULLY_REG = "1" *) (* P_LIGHT_WT = "0" *) (* P_LUTRAM_ASYNC = "12" *)
(* P_ROUNDING_OFFSET = "0" *) (* P_SI_LT_MI = "1'b1" *)
module bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
(* keep = "true" *) input s_axi_aclk;
(* keep = "true" *) input s_axi_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [3:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
(* keep = "true" *) input m_axi_aclk;
(* keep = "true" *) input m_axi_aresetn;
output [3:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [3:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [3:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [3:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [3:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire async_conv_reset_n;
(* RTL_KEEP = "true" *) wire m_axi_aclk;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
(* RTL_KEEP = "true" *) wire m_axi_aresetn;
wire [3:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [3:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [3:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [3:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
(* RTL_KEEP = "true" *) wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
(* RTL_KEEP = "true" *) wire s_axi_aresetn;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [3:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [3:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED ;
wire [10:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED ;
wire [10:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED ;
wire [10:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED ;
wire [9:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED ;
wire [17:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED ;
wire [3:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED ;
wire [7:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED ;
wire [3:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED ;
wire [9:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED ;
wire [9:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "18" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "65" *)
(* C_DIN_WIDTH_RDCH = "39" *)
(* C_DIN_WIDTH_WACH = "65" *)
(* C_DIN_WIDTH_WDCH = "37" *)
(* C_DIN_WIDTH_WRCH = "6" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "18" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "1" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "11" *)
(* C_IMPLEMENTATION_TYPE_RACH = "12" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "12" *)
(* C_IMPLEMENTATION_TYPE_WACH = "12" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "12" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "12" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "2" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "4kx4" *)
(* C_PRIM_FIFO_TYPE_AXIS = "512x36" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1021" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "13" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "15" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "3" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "16" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "16" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "4" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "4" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
bd_auto_cc_0_fifo_generator_v13_1_3 \gen_clock_conv.gen_async_conv.asyncfifo_axi
(.almost_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED ),
.almost_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED ),
.axi_ar_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED [4:0]),
.axi_ar_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED ),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED ),
.axi_ar_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED ),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED ),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED [4:0]),
.axi_ar_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED ),
.axi_ar_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED ),
.axi_ar_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED [4:0]),
.axi_aw_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED [4:0]),
.axi_aw_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED ),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED ),
.axi_aw_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED ),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED ),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED [4:0]),
.axi_aw_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED ),
.axi_aw_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED ),
.axi_aw_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED [4:0]),
.axi_b_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED [4:0]),
.axi_b_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED ),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED ),
.axi_b_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED ),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED ),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED [4:0]),
.axi_b_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED ),
.axi_b_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED ),
.axi_b_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED [4:0]),
.axi_r_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED [4:0]),
.axi_r_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED ),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED ),
.axi_r_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED ),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED ),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED [4:0]),
.axi_r_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED ),
.axi_r_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED ),
.axi_r_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED [4:0]),
.axi_w_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED [4:0]),
.axi_w_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED ),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED ),
.axi_w_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED ),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED ),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED [4:0]),
.axi_w_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED ),
.axi_w_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED ),
.axi_w_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED [4:0]),
.axis_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED [10:0]),
.axis_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED ),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED ),
.axis_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED ),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED ),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED [10:0]),
.axis_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED ),
.axis_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED ),
.axis_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED [10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED [9:0]),
.dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED ),
.din({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dout(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED [17:0]),
.empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED ),
.full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED ),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(m_axi_aclk),
.m_aclk_en(1'b1),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED [0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED [0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED [3:0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED [0]),
.m_axi_wvalid(m_axi_wvalid),
.m_axis_tdata(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED [7:0]),
.m_axis_tdest(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED [0]),
.m_axis_tid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED [0]),
.m_axis_tkeep(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED [0]),
.m_axis_tlast(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED ),
.m_axis_tready(1'b0),
.m_axis_tstrb(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED [0]),
.m_axis_tuser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED [3:0]),
.m_axis_tvalid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED ),
.overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED ),
.prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED ),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED ),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED [9:0]),
.rd_en(1'b0),
.rd_rst(1'b0),
.rd_rst_busy(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED ),
.rst(1'b0),
.s_aclk(s_axi_aclk),
.s_aclk_en(1'b1),
.s_aresetn(async_conv_reset_n),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED [0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED [0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED ),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED ),
.sleep(1'b0),
.srst(1'b0),
.underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED ),
.valid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED ),
.wr_ack(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED ),
.wr_clk(1'b0),
.wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED [9:0]),
.wr_en(1'b0),
.wr_rst(1'b0),
.wr_rst_busy(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED ));
LUT2 #(
.INIT(4'h8))
\gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1
(.I0(s_axi_aresetn),
.I1(m_axi_aresetn),
.O(async_conv_reset_n));
endmodule
(* CHECK_LICENSE_TYPE = "bd_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bd_auto_cc_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [3:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [3:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [3:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [3:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *) input m_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *) input m_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output [3:0]m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [7:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output [0:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output [3:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output [3:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input [3:0]m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output [3:0]m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input [3:0]m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire m_axi_aclk;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire m_axi_aresetn;
wire [3:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [3:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [3:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [3:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [3:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [3:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_ARADDR_RIGHT = "29" *)
(* C_ARADDR_WIDTH = "32" *)
(* C_ARBURST_RIGHT = "16" *)
(* C_ARBURST_WIDTH = "2" *)
(* C_ARCACHE_RIGHT = "11" *)
(* C_ARCACHE_WIDTH = "4" *)
(* C_ARID_RIGHT = "61" *)
(* C_ARID_WIDTH = "4" *)
(* C_ARLEN_RIGHT = "21" *)
(* C_ARLEN_WIDTH = "8" *)
(* C_ARLOCK_RIGHT = "15" *)
(* C_ARLOCK_WIDTH = "1" *)
(* C_ARPROT_RIGHT = "8" *)
(* C_ARPROT_WIDTH = "3" *)
(* C_ARQOS_RIGHT = "0" *)
(* C_ARQOS_WIDTH = "4" *)
(* C_ARREGION_RIGHT = "4" *)
(* C_ARREGION_WIDTH = "4" *)
(* C_ARSIZE_RIGHT = "18" *)
(* C_ARSIZE_WIDTH = "3" *)
(* C_ARUSER_RIGHT = "0" *)
(* C_ARUSER_WIDTH = "0" *)
(* C_AR_WIDTH = "65" *)
(* C_AWADDR_RIGHT = "29" *)
(* C_AWADDR_WIDTH = "32" *)
(* C_AWBURST_RIGHT = "16" *)
(* C_AWBURST_WIDTH = "2" *)
(* C_AWCACHE_RIGHT = "11" *)
(* C_AWCACHE_WIDTH = "4" *)
(* C_AWID_RIGHT = "61" *)
(* C_AWID_WIDTH = "4" *)
(* C_AWLEN_RIGHT = "21" *)
(* C_AWLEN_WIDTH = "8" *)
(* C_AWLOCK_RIGHT = "15" *)
(* C_AWLOCK_WIDTH = "1" *)
(* C_AWPROT_RIGHT = "8" *)
(* C_AWPROT_WIDTH = "3" *)
(* C_AWQOS_RIGHT = "0" *)
(* C_AWQOS_WIDTH = "4" *)
(* C_AWREGION_RIGHT = "4" *)
(* C_AWREGION_WIDTH = "4" *)
(* C_AWSIZE_RIGHT = "18" *)
(* C_AWSIZE_WIDTH = "3" *)
(* C_AWUSER_RIGHT = "0" *)
(* C_AWUSER_WIDTH = "0" *)
(* C_AW_WIDTH = "65" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_IS_ACLK_ASYNC = "1" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_BID_RIGHT = "2" *)
(* C_BID_WIDTH = "4" *)
(* C_BRESP_RIGHT = "0" *)
(* C_BRESP_WIDTH = "2" *)
(* C_BUSER_RIGHT = "0" *)
(* C_BUSER_WIDTH = "0" *)
(* C_B_WIDTH = "6" *)
(* C_FAMILY = "artix7" *)
(* C_FIFO_AR_WIDTH = "65" *)
(* C_FIFO_AW_WIDTH = "65" *)
(* C_FIFO_B_WIDTH = "6" *)
(* C_FIFO_R_WIDTH = "39" *)
(* C_FIFO_W_WIDTH = "37" *)
(* C_M_AXI_ACLK_RATIO = "2" *)
(* C_RDATA_RIGHT = "3" *)
(* C_RDATA_WIDTH = "32" *)
(* C_RID_RIGHT = "35" *)
(* C_RID_WIDTH = "4" *)
(* C_RLAST_RIGHT = "0" *)
(* C_RLAST_WIDTH = "1" *)
(* C_RRESP_RIGHT = "1" *)
(* C_RRESP_WIDTH = "2" *)
(* C_RUSER_RIGHT = "0" *)
(* C_RUSER_WIDTH = "0" *)
(* C_R_WIDTH = "39" *)
(* C_SYNCHRONIZER_STAGE = "3" *)
(* C_S_AXI_ACLK_RATIO = "1" *)
(* C_WDATA_RIGHT = "5" *)
(* C_WDATA_WIDTH = "32" *)
(* C_WID_RIGHT = "37" *)
(* C_WID_WIDTH = "0" *)
(* C_WLAST_RIGHT = "0" *)
(* C_WLAST_WIDTH = "1" *)
(* C_WSTRB_RIGHT = "1" *)
(* C_WSTRB_WIDTH = "4" *)
(* C_WUSER_RIGHT = "0" *)
(* C_WUSER_WIDTH = "0" *)
(* C_W_WIDTH = "37" *)
(* P_ACLK_RATIO = "2" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_FULLY_REG = "1" *)
(* P_LIGHT_WT = "0" *)
(* P_LUTRAM_ASYNC = "12" *)
(* P_ROUNDING_OFFSET = "0" *)
(* P_SI_LT_MI = "1'b1" *)
(* downgradeipidentifiedwarnings = "yes" *)
bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter inst
(.m_axi_aclk(m_axi_aclk),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[3:0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module bd_auto_cc_0_clk_x_pntrs
(out,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_full_fb_i_reg_1,
Q,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
m_aclk,
AR,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
output ram_empty_i_reg;
output [3:0]ram_empty_i_reg_0;
input ram_full_fb_i_reg_1;
input [3:0]Q;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [2:0]\gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input m_aclk;
input [0:0]AR;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire [3:0]ram_empty_i_reg_0;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2_n_0;
wire ram_full_i_i_4_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
bd_auto_cc_0_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.m_aclk(m_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized4 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized5 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.m_aclk(m_aclk),
.out(p_8_out));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(ram_empty_i_reg_0[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(ram_empty_i_reg_0[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(ram_empty_i_reg_0[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(ram_empty_i_reg_0[3]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__2
(.I0(ram_empty_i_reg_0[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(ram_empty_i_reg_0[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(ram_empty_i_reg_0[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1
(.I0(ram_full_i_i_2_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(Q[3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4
(.I0(p_23_out[2]),
.I1(Q[2]),
.I2(p_23_out[1]),
.I3(Q[1]),
.I4(Q[0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module bd_auto_cc_0_clk_x_pntrs_27
(out,
ram_empty_i_reg,
Q,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
D,
\gc0.count_reg[2] ,
ram_full_fb_i_reg_1,
\gic0.gc0.count_d1_reg[3] ,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
s_aclk,
AR,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
\gc0.count_d1_reg[2] );
output [3:0]out;
output ram_empty_i_reg;
output [3:0]Q;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
input [0:0]D;
input [2:0]\gc0.count_reg[2] ;
input ram_full_fb_i_reg_1;
input [3:0]\gic0.gc0.count_d1_reg[3] ;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input s_aclk;
input [0:0]AR;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]\gc0.count_d1_reg[2] ;
wire [0:0]AR;
wire [0:0]D;
wire [3:0]Q;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [2:0]\gc0.count_d1_reg[2] ;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire [1:1]gray2bin;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire p_0_out;
wire [2:0]p_23_out_1;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__1_n_0;
wire ram_full_i_i_4__1_n_0;
wire [3:0]rd_pntr_gc;
wire s_aclk;
wire [3:0]wr_pntr_gc;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(gray2bin));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
bd_auto_cc_0_synchronizer_ff__parameterized0_42 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
bd_auto_cc_0_synchronizer_ff__parameterized1_43 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q(rd_pntr_gc),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized2_44 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
bd_auto_cc_0_synchronizer_ff__parameterized3_45 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized4_46 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(p_0_out),
.\Q_reg_reg[3]_0 (p_5_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out));
bd_auto_cc_0_synchronizer_ff__parameterized5_47 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.out(p_8_out),
.s_aclk(s_aclk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out_1[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out_1[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out_1[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[2] [0]),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[2] [1]),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[2] [2]),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_out),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(Q[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(wr_pntr_gc[3]));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4
(.I0(Q[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(Q[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(Q[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__1
(.I0(ram_full_i_i_2__1_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(\gic0.gc0.count_d1_reg[3] [3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__1_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__1
(.I0(p_23_out_1[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out_1[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out_1[0]),
.O(ram_full_i_i_2__1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__1
(.I0(p_23_out_1[2]),
.I1(\gic0.gc0.count_d1_reg[3] [2]),
.I2(p_23_out_1[1]),
.I3(\gic0.gc0.count_d1_reg[3] [1]),
.I4(\gic0.gc0.count_d1_reg[3] [0]),
.I5(p_23_out_1[0]),
.O(ram_full_i_i_4__1_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module bd_auto_cc_0_clk_x_pntrs_48
(out,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_full_fb_i_reg_1,
Q,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
m_aclk,
AR,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
output ram_empty_i_reg;
output [3:0]ram_empty_i_reg_0;
input ram_full_fb_i_reg_1;
input [3:0]Q;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [2:0]\gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input m_aclk;
input [0:0]AR;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire [3:0]ram_empty_i_reg_0;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__0_n_0;
wire ram_full_i_i_4__0_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
bd_auto_cc_0_synchronizer_ff__parameterized0_63 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized1_64 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized2_65 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized3_66 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.m_aclk(m_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized4_67 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized5_68 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.m_aclk(m_aclk),
.out(p_8_out));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(ram_empty_i_reg_0[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(ram_empty_i_reg_0[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(ram_empty_i_reg_0[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(ram_empty_i_reg_0[3]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__3
(.I0(ram_empty_i_reg_0[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(ram_empty_i_reg_0[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(ram_empty_i_reg_0[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__0
(.I0(ram_full_i_i_2__0_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(Q[3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__0_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__0
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__0
(.I0(p_23_out[2]),
.I1(Q[2]),
.I2(p_23_out[1]),
.I3(Q[1]),
.I4(Q[0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4__0_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module bd_auto_cc_0_clk_x_pntrs_6
(out,
ram_empty_i_reg,
Q,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
\gc0.count_reg[2] ,
ram_full_fb_i_reg_1,
\gic0.gc0.count_d1_reg[3] ,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
s_aclk,
AR,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_empty_i_reg;
output [3:0]Q;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
input [2:0]\gc0.count_reg[2] ;
input ram_full_fb_i_reg_1;
input [3:0]\gic0.gc0.count_d1_reg[3] ;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input s_aclk;
input [0:0]AR;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__2_n_0;
wire ram_full_i_i_4__2_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
bd_auto_cc_0_synchronizer_ff__parameterized0_21 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
bd_auto_cc_0_synchronizer_ff__parameterized1_22 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized2_23 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
bd_auto_cc_0_synchronizer_ff__parameterized3_24 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized4_25 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out));
bd_auto_cc_0_synchronizer_ff__parameterized5_26 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.out(p_8_out),
.s_aclk(s_aclk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(Q[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__0
(.I0(Q[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(Q[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(Q[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__2
(.I0(ram_full_i_i_2__2_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(\gic0.gc0.count_d1_reg[3] [3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__2_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__2
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2__2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__2
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_d1_reg[3] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_d1_reg[3] [1]),
.I4(\gic0.gc0.count_d1_reg[3] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4__2_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module bd_auto_cc_0_clk_x_pntrs_70
(out,
ram_empty_i_reg,
Q,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
\gc0.count_reg[2] ,
ram_full_fb_i_reg_1,
\gic0.gc0.count_d1_reg[3] ,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
s_aclk,
AR,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_empty_i_reg;
output [3:0]Q;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
input [2:0]\gc0.count_reg[2] ;
input ram_full_fb_i_reg_1;
input [3:0]\gic0.gc0.count_d1_reg[3] ;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input s_aclk;
input [0:0]AR;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__3_n_0;
wire ram_full_i_i_4__3_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
bd_auto_cc_0_synchronizer_ff__parameterized0_87 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
bd_auto_cc_0_synchronizer_ff__parameterized1_88 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized2_89 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
bd_auto_cc_0_synchronizer_ff__parameterized3_90 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff__parameterized4_91 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out));
bd_auto_cc_0_synchronizer_ff__parameterized5_92 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.out(p_8_out),
.s_aclk(s_aclk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(Q[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__1
(.I0(Q[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(Q[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(Q[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__3
(.I0(ram_full_i_i_2__3_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(\gic0.gc0.count_d1_reg[3] [3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__3_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__3
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2__3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__3
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_d1_reg[3] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_d1_reg[3] [1]),
.I4(\gic0.gc0.count_d1_reg[3] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4__3_n_0));
endmodule
module bd_auto_cc_0_dmem
(dout_i,
s_aclk,
ram_full_fb_i_reg,
DI,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk);
output [64:0]dout_i;
input s_aclk;
input [0:0]ram_full_fb_i_reg;
input [64:0]DI;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
wire [64:0]DI;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_59_n_0;
wire RAM_reg_0_15_54_59_n_1;
wire RAM_reg_0_15_54_59_n_2;
wire RAM_reg_0_15_54_59_n_3;
wire RAM_reg_0_15_54_59_n_4;
wire RAM_reg_0_15_54_59_n_5;
wire RAM_reg_0_15_60_64_n_0;
wire RAM_reg_0_15_60_64_n_1;
wire RAM_reg_0_15_60_64_n_2;
wire RAM_reg_0_15_60_64_n_3;
wire RAM_reg_0_15_60_64_n_5;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire [64:0]dout_i;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]ram_full_fb_i_reg;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED;
wire [1:1]NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[1:0]),
.DIB(DI[3:2]),
.DIC(DI[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[13:12]),
.DIB(DI[15:14]),
.DIC(DI[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[19:18]),
.DIB(DI[21:20]),
.DIC(DI[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[25:24]),
.DIB(DI[27:26]),
.DIC(DI[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[31:30]),
.DIB(DI[33:32]),
.DIC(DI[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[37:36]),
.DIB(DI[39:38]),
.DIC(DI[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[43:42]),
.DIB(DI[45:44]),
.DIC(DI[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[49:48]),
.DIB(DI[51:50]),
.DIC(DI[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_59
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[55:54]),
.DIB(DI[57:56]),
.DIC(DI[59:58]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_59_n_0,RAM_reg_0_15_54_59_n_1}),
.DOB({RAM_reg_0_15_54_59_n_2,RAM_reg_0_15_54_59_n_3}),
.DOC({RAM_reg_0_15_54_59_n_4,RAM_reg_0_15_54_59_n_5}),
.DOD(NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_60_64
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[61:60]),
.DIB(DI[63:62]),
.DIC({1'b0,DI[64]}),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_60_64_n_0,RAM_reg_0_15_60_64_n_1}),
.DOB({RAM_reg_0_15_60_64_n_2,RAM_reg_0_15_60_64_n_3}),
.DOC({NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED[1],RAM_reg_0_15_60_64_n_5}),
.DOD(NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[7:6]),
.DIB(DI[9:8]),
.DIC(DI[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(dout_i[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(dout_i[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(dout_i[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(dout_i[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(dout_i[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(dout_i[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(dout_i[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(dout_i[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(dout_i[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(dout_i[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(dout_i[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(dout_i[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(dout_i[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(dout_i[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(dout_i[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(dout_i[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(dout_i[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(dout_i[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(dout_i[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(dout_i[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(dout_i[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(dout_i[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(dout_i[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(dout_i[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(dout_i[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(dout_i[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(dout_i[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(dout_i[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(dout_i[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(dout_i[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(dout_i[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(dout_i[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(dout_i[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(dout_i[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(dout_i[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(dout_i[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(dout_i[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(dout_i[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(dout_i[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(dout_i[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(dout_i[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(dout_i[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(dout_i[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(dout_i[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(dout_i[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(dout_i[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(dout_i[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(dout_i[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(dout_i[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_1),
.Q(dout_i[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_0),
.Q(dout_i[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_3),
.Q(dout_i[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_2),
.Q(dout_i[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[58]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_5),
.Q(dout_i[58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[59]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_4),
.Q(dout_i[59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(dout_i[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[60]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_1),
.Q(dout_i[60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[61]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_0),
.Q(dout_i[61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[62]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_3),
.Q(dout_i[62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[63]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_2),
.Q(dout_i[63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[64]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_5),
.Q(dout_i[64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(dout_i[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(dout_i[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(dout_i[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(dout_i[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module bd_auto_cc_0_dmem_81
(Q,
s_aclk,
E,
I123,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk);
output [64:0]Q;
input s_aclk;
input [0:0]E;
input [64:0]I123;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
wire [0:0]E;
wire [64:0]I123;
wire [64:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_59_n_0;
wire RAM_reg_0_15_54_59_n_1;
wire RAM_reg_0_15_54_59_n_2;
wire RAM_reg_0_15_54_59_n_3;
wire RAM_reg_0_15_54_59_n_4;
wire RAM_reg_0_15_54_59_n_5;
wire RAM_reg_0_15_60_64_n_0;
wire RAM_reg_0_15_60_64_n_1;
wire RAM_reg_0_15_60_64_n_2;
wire RAM_reg_0_15_60_64_n_3;
wire RAM_reg_0_15_60_64_n_5;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED;
wire [1:1]NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[1:0]),
.DIB(I123[3:2]),
.DIC(I123[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[13:12]),
.DIB(I123[15:14]),
.DIC(I123[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[19:18]),
.DIB(I123[21:20]),
.DIC(I123[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[25:24]),
.DIB(I123[27:26]),
.DIC(I123[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[31:30]),
.DIB(I123[33:32]),
.DIC(I123[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[37:36]),
.DIB(I123[39:38]),
.DIC(I123[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[43:42]),
.DIB(I123[45:44]),
.DIC(I123[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[49:48]),
.DIB(I123[51:50]),
.DIC(I123[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_59
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[55:54]),
.DIB(I123[57:56]),
.DIC(I123[59:58]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_59_n_0,RAM_reg_0_15_54_59_n_1}),
.DOB({RAM_reg_0_15_54_59_n_2,RAM_reg_0_15_54_59_n_3}),
.DOC({RAM_reg_0_15_54_59_n_4,RAM_reg_0_15_54_59_n_5}),
.DOD(NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_60_64
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[61:60]),
.DIB(I123[63:62]),
.DIC({1'b0,I123[64]}),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_60_64_n_0,RAM_reg_0_15_60_64_n_1}),
.DOB({RAM_reg_0_15_60_64_n_2,RAM_reg_0_15_60_64_n_3}),
.DOC({NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED[1],RAM_reg_0_15_60_64_n_5}),
.DOD(NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[7:6]),
.DIB(I123[9:8]),
.DIC(I123[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_1),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_0),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_3),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_2),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[58]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_5),
.Q(Q[58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[59]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_4),
.Q(Q[59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[60]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_1),
.Q(Q[60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[61]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_0),
.Q(Q[61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[62]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_3),
.Q(Q[62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[63]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_2),
.Q(Q[63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[64]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_64_n_5),
.Q(Q[64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module bd_auto_cc_0_dmem__parameterized0
(Q,
s_aclk,
E,
I115,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk);
output [36:0]Q;
input s_aclk;
input [0:0]E;
input [36:0]I115;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
wire [0:0]E;
wire [36:0]I115;
wire [36:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_36_n_1;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:1]NLW_RAM_reg_0_15_36_36_DOA_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_36_DOB_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_36_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_36_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[1:0]),
.DIB(I115[3:2]),
.DIC(I115[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[13:12]),
.DIB(I115[15:14]),
.DIC(I115[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[19:18]),
.DIB(I115[21:20]),
.DIC(I115[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[25:24]),
.DIB(I115[27:26]),
.DIC(I115[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[31:30]),
.DIB(I115[33:32]),
.DIC(I115[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_36
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA({1'b0,I115[36]}),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({NLW_RAM_reg_0_15_36_36_DOA_UNCONNECTED[1],RAM_reg_0_15_36_36_n_1}),
.DOB(NLW_RAM_reg_0_15_36_36_DOB_UNCONNECTED[1:0]),
.DOC(NLW_RAM_reg_0_15_36_36_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_36_36_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[7:6]),
.DIB(I115[9:8]),
.DIC(I115[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_36_n_1),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module bd_auto_cc_0_dmem__parameterized1
(Q,
m_aclk,
E,
m_axi_bresp,
m_axi_bid,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk);
output [5:0]Q;
input m_aclk;
input [0:0]E;
input [1:0]m_axi_bresp;
input [3:0]m_axi_bid;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
wire [0:0]E;
wire [5:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [3:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(m_axi_bresp),
.DIB(m_axi_bid[1:0]),
.DIC(m_axi_bid[3:2]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module bd_auto_cc_0_dmem__parameterized2
(Q,
m_aclk,
E,
I127,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk);
output [38:0]Q;
input m_aclk;
input [0:0]E;
input [38:0]I127;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
wire [0:0]E;
wire [38:0]I127;
wire [38:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_38_n_0;
wire RAM_reg_0_15_36_38_n_1;
wire RAM_reg_0_15_36_38_n_3;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:1]NLW_RAM_reg_0_15_36_38_DOB_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_38_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_38_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[1:0]),
.DIB(I127[3:2]),
.DIC(I127[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[13:12]),
.DIB(I127[15:14]),
.DIC(I127[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[19:18]),
.DIB(I127[21:20]),
.DIC(I127[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[25:24]),
.DIB(I127[27:26]),
.DIC(I127[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[31:30]),
.DIB(I127[33:32]),
.DIC(I127[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_38
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[37:36]),
.DIB({1'b0,I127[38]}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_38_n_0,RAM_reg_0_15_36_38_n_1}),
.DOB({NLW_RAM_reg_0_15_36_38_DOB_UNCONNECTED[1],RAM_reg_0_15_36_38_n_3}),
.DOC(NLW_RAM_reg_0_15_36_38_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_36_38_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[7:6]),
.DIB(I127[9:8]),
.DIC(I127[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_38_n_1),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_38_n_0),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_38_n_3),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(Q[9]),
.R(1'b0));
endmodule
module bd_auto_cc_0_fifo_generator_ramfifo
(s_axi_awready,
m_axi_awvalid,
Q,
m_aclk,
s_aclk,
inverted_reset,
m_axi_awready,
s_axi_awvalid,
DI);
output s_axi_awready;
output m_axi_awvalid;
output [64:0]Q;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_awready;
input s_axi_awvalid;
input [64:0]DI;
wire [64:0]DI;
wire [64:0]Q;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire [0:0]gray2bin;
wire inverted_reset;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire [3:0]p_0_out_0;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire p_23_out;
wire [3:3]p_23_out_1;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
wire [2:0]wr_pntr_plus2;
wire [1:0]wr_rst_i;
bd_auto_cc_0_clk_x_pntrs_27 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D(gray2bin),
.Q(p_22_out),
.\gc0.count_d1_reg[2] ({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.\gc0.count_d1_reg[3] (p_0_out_0[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[3] (p_13_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (p_23_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_fb_i_reg_0(p_23_out_1),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(gray2bin));
bd_auto_cc_0_rd_logic_28 \gntv_or_sync_fifo.gl0.rd
(.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[2] ({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out_0),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[64] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.out({rd_rst_i[2],rd_rst_i[0]}));
bd_auto_cc_0_wr_logic_29 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out_1),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
bd_auto_cc_0_memory \gntv_or_sync_fifo.mem
(.DI(DI),
.E(\gntv_or_sync_fifo.gl0.rd_n_4 ),
.Q(Q),
.\gc0.count_d1_reg[3] (p_0_out_0),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.ram_full_fb_i_reg(p_18_out),
.s_aclk(s_aclk));
bd_auto_cc_0_reset_blk_ramfifo_30 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(p_23_out),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module bd_auto_cc_0_fifo_generator_ramfifo_69
(s_axi_arready,
m_axi_arvalid,
\m_axi_arid[3] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_arready,
s_axi_arvalid,
I123);
output s_axi_arready;
output m_axi_arvalid;
output [64:0]\m_axi_arid[3] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_arready;
input s_axi_arvalid;
input [64:0]I123;
wire [64:0]I123;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire inverted_reset;
wire m_aclk;
wire [64:0]\m_axi_arid[3] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]wr_pntr_plus2;
wire wr_rst_busy_rach;
wire [1:0]wr_rst_i;
bd_auto_cc_0_clk_x_pntrs_70 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_22_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[3] (p_13_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_rach),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
bd_auto_cc_0_rd_logic_71 \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[64] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.m_aclk(m_aclk),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.out({rd_rst_i[2],rd_rst_i[0]}));
bd_auto_cc_0_wr_logic_72 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
bd_auto_cc_0_memory_73 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.I123(I123),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.\m_axi_arid[3] (\m_axi_arid[3] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk));
bd_auto_cc_0_reset_blk_ramfifo_74 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(wr_rst_busy_rach),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module bd_auto_cc_0_fifo_generator_ramfifo__parameterized0
(s_axi_wready,
m_axi_wvalid,
\m_axi_wdata[31] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_wready,
s_axi_wvalid,
I115);
output s_axi_wready;
output m_axi_wvalid;
output [36:0]\m_axi_wdata[31] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_wready;
input s_axi_wvalid;
input [36:0]I115;
wire [36:0]I115;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire inverted_reset;
wire m_aclk;
wire [36:0]\m_axi_wdata[31] ;
wire m_axi_wready;
wire m_axi_wvalid;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_15_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
wire [2:0]wr_pntr_plus2;
wire [1:0]wr_rst_i;
bd_auto_cc_0_clk_x_pntrs_6 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_22_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[3] (p_13_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (p_15_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
bd_auto_cc_0_rd_logic_7 \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[36] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.m_aclk(m_aclk),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.out({rd_rst_i[2],rd_rst_i[0]}));
bd_auto_cc_0_wr_logic_8 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
bd_auto_cc_0_memory__parameterized0 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.I115(I115),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.\m_axi_wdata[31] (\m_axi_wdata[31] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk));
bd_auto_cc_0_reset_blk_ramfifo_9 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(p_15_out),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module bd_auto_cc_0_fifo_generator_ramfifo__parameterized1
(s_axi_bvalid,
m_axi_bready,
\s_axi_bid[3] ,
s_aclk,
m_aclk,
inverted_reset,
m_axi_bresp,
m_axi_bid,
m_axi_bvalid,
s_axi_bready);
output s_axi_bvalid;
output m_axi_bready;
output [5:0]\s_axi_bid[3] ;
input s_aclk;
input m_aclk;
input inverted_reset;
input [1:0]m_axi_bresp;
input [3:0]m_axi_bid;
input m_axi_bvalid;
input s_axi_bready;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire inverted_reset;
wire m_aclk;
wire [3:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire [5:0]\s_axi_bid[3] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [2:0]wr_pntr_plus2;
wire wr_rst_busy_wrch;
wire [1:0]wr_rst_i;
bd_auto_cc_0_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_13_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_wrch),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.ram_empty_i_reg_0(p_22_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
bd_auto_cc_0_rd_logic \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[5] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.out({rd_rst_i[2],rd_rst_i[0]}),
.s_aclk(s_aclk),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid));
bd_auto_cc_0_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.m_aclk(m_aclk),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ));
bd_auto_cc_0_memory__parameterized1 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk),
.\s_axi_bid[3] (\s_axi_bid[3] ));
bd_auto_cc_0_reset_blk_ramfifo rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(wr_rst_busy_wrch),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module bd_auto_cc_0_fifo_generator_ramfifo__parameterized2
(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ,
s_axi_rvalid,
m_axi_rready,
\s_axi_rid[3] ,
s_aclk,
m_aclk,
m_axi_rvalid,
s_axi_rready,
s_aresetn,
I127);
output \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ;
output s_axi_rvalid;
output m_axi_rready;
output [38:0]\s_axi_rid[3] ;
input s_aclk;
input m_aclk;
input m_axi_rvalid;
input s_axi_rready;
input s_aresetn;
input [38:0]I127;
wire [38:0]I127;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_aresetn;
wire [38:0]\s_axi_rid[3] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [2:0]wr_pntr_plus2;
wire wr_rst_busy_rdch;
wire [1:0]wr_rst_i;
bd_auto_cc_0_clk_x_pntrs_48 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_13_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_rdch),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.ram_empty_i_reg_0(p_22_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
bd_auto_cc_0_rd_logic_49 \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[38] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.out({rd_rst_i[2],rd_rst_i[0]}),
.s_aclk(s_aclk),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
bd_auto_cc_0_wr_logic_50 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ));
bd_auto_cc_0_memory__parameterized2 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.I127(I127),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk),
.\s_axi_rid[3] (\s_axi_rid[3] ));
bd_auto_cc_0_reset_blk_ramfifo_51 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 (\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ),
.out(wr_rst_i),
.ram_full_fb_i_reg(wr_rst_busy_rdch),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn));
endmodule
module bd_auto_cc_0_fifo_generator_top
(s_axi_arready,
m_axi_arvalid,
\m_axi_arid[3] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_arready,
s_axi_arvalid,
I123);
output s_axi_arready;
output m_axi_arvalid;
output [64:0]\m_axi_arid[3] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_arready;
input s_axi_arvalid;
input [64:0]I123;
wire [64:0]I123;
wire inverted_reset;
wire m_aclk;
wire [64:0]\m_axi_arid[3] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
bd_auto_cc_0_fifo_generator_ramfifo_69 \grf.rf
(.I123(I123),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_arid[3] (\m_axi_arid[3] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module bd_auto_cc_0_fifo_generator_top_0
(s_axi_awready,
m_axi_awvalid,
Q,
m_aclk,
s_aclk,
inverted_reset,
m_axi_awready,
s_axi_awvalid,
DI);
output s_axi_awready;
output m_axi_awvalid;
output [64:0]Q;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_awready;
input s_axi_awvalid;
input [64:0]DI;
wire [64:0]DI;
wire [64:0]Q;
wire inverted_reset;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
bd_auto_cc_0_fifo_generator_ramfifo \grf.rf
(.DI(DI),
.Q(Q),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module bd_auto_cc_0_fifo_generator_top__parameterized0
(s_axi_wready,
m_axi_wvalid,
\m_axi_wdata[31] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_wready,
s_axi_wvalid,
I115);
output s_axi_wready;
output m_axi_wvalid;
output [36:0]\m_axi_wdata[31] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_wready;
input s_axi_wvalid;
input [36:0]I115;
wire [36:0]I115;
wire inverted_reset;
wire m_aclk;
wire [36:0]\m_axi_wdata[31] ;
wire m_axi_wready;
wire m_axi_wvalid;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
bd_auto_cc_0_fifo_generator_ramfifo__parameterized0 \grf.rf
(.I115(I115),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_wdata[31] (\m_axi_wdata[31] ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module bd_auto_cc_0_fifo_generator_top__parameterized1
(s_axi_bvalid,
m_axi_bready,
\s_axi_bid[3] ,
s_aclk,
m_aclk,
inverted_reset,
m_axi_bresp,
m_axi_bid,
m_axi_bvalid,
s_axi_bready);
output s_axi_bvalid;
output m_axi_bready;
output [5:0]\s_axi_bid[3] ;
input s_aclk;
input m_aclk;
input inverted_reset;
input [1:0]m_axi_bresp;
input [3:0]m_axi_bid;
input m_axi_bvalid;
input s_axi_bready;
wire inverted_reset;
wire m_aclk;
wire [3:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire s_aclk;
wire [5:0]\s_axi_bid[3] ;
wire s_axi_bready;
wire s_axi_bvalid;
bd_auto_cc_0_fifo_generator_ramfifo__parameterized1 \grf.rf
(.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.s_aclk(s_aclk),
.\s_axi_bid[3] (\s_axi_bid[3] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module bd_auto_cc_0_fifo_generator_top__parameterized2
(inverted_reset,
s_axi_rvalid,
m_axi_rready,
\s_axi_rid[3] ,
s_aclk,
m_aclk,
m_axi_rvalid,
s_axi_rready,
s_aresetn,
I127);
output inverted_reset;
output s_axi_rvalid;
output m_axi_rready;
output [38:0]\s_axi_rid[3] ;
input s_aclk;
input m_aclk;
input m_axi_rvalid;
input s_axi_rready;
input s_aresetn;
input [38:0]I127;
wire [38:0]I127;
wire inverted_reset;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire s_aclk;
wire s_aresetn;
wire [38:0]\s_axi_rid[3] ;
wire s_axi_rready;
wire s_axi_rvalid;
bd_auto_cc_0_fifo_generator_ramfifo__parameterized2 \grf.rf
(.I127(I127),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg (inverted_reset),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.\s_axi_rid[3] (\s_axi_rid[3] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "4" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "18" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "65" *) (* C_DIN_WIDTH_RDCH = "39" *)
(* C_DIN_WIDTH_WACH = "65" *) (* C_DIN_WIDTH_WDCH = "37" *) (* C_DIN_WIDTH_WRCH = "6" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "18" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "1" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "11" *) (* C_IMPLEMENTATION_TYPE_RACH = "12" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "12" *) (* C_IMPLEMENTATION_TYPE_WACH = "12" *) (* C_IMPLEMENTATION_TYPE_WDCH = "12" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "12" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "2" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "4kx4" *)
(* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1021" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "13" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "13" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "13" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "15" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "15" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "15" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "3" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "16" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "16" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "4" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "4" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
module bd_auto_cc_0_fifo_generator_v13_1_3
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [17:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [17:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [3:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [3:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [3:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [3:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [3:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [3:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [3:0]axi_w_prog_full_thresh;
input [3:0]axi_w_prog_empty_thresh;
output [4:0]axi_w_data_count;
output [4:0]axi_w_wr_data_count;
output [4:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [3:0]axi_r_prog_full_thresh;
input [3:0]axi_r_prog_empty_thresh;
output [4:0]axi_r_data_count;
output [4:0]axi_r_wr_data_count;
output [4:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire m_aclk;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire [3:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [3:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [3:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [3:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [3:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [3:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const0> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const0> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const0> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const0> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const0> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const0> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign dout[17] = \<const0> ;
assign dout[16] = \<const0> ;
assign dout[15] = \<const0> ;
assign dout[14] = \<const0> ;
assign dout[13] = \<const0> ;
assign dout[12] = \<const0> ;
assign dout[11] = \<const0> ;
assign dout[10] = \<const0> ;
assign dout[9] = \<const0> ;
assign dout[8] = \<const0> ;
assign dout[7] = \<const0> ;
assign dout[6] = \<const0> ;
assign dout[5] = \<const0> ;
assign dout[4] = \<const0> ;
assign dout[3] = \<const0> ;
assign dout[2] = \<const0> ;
assign dout[1] = \<const0> ;
assign dout[0] = \<const0> ;
assign empty = \<const0> ;
assign full = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
bd_auto_cc_0_fifo_generator_v13_1_3_synth inst_fifo_gen
(.DI({s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awqos,s_axi_awregion}),
.I115({s_axi_wdata,s_axi_wstrb,s_axi_wlast}),
.I123({s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arregion}),
.I127({m_axi_rid,m_axi_rdata,m_axi_rresp,m_axi_rlast}),
.Q({m_axi_awid,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awqos,m_axi_awregion}),
.m_aclk(m_aclk),
.\m_axi_arid[3] ({m_axi_arid,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arqos,m_axi_arregion}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.\m_axi_wdata[31] ({m_axi_wdata,m_axi_wstrb,m_axi_wlast}),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[3] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[3] ({s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module bd_auto_cc_0_fifo_generator_v13_1_3_synth
(Q,
\m_axi_wdata[31] ,
\s_axi_bid[3] ,
\m_axi_arid[3] ,
\s_axi_rid[3] ,
s_axi_awready,
s_axi_wready,
s_axi_bvalid,
m_axi_awvalid,
m_axi_wvalid,
m_axi_bready,
s_axi_arready,
s_axi_rvalid,
m_axi_arvalid,
m_axi_rready,
m_aclk,
s_aclk,
I115,
m_axi_bresp,
m_axi_bid,
I123,
I127,
DI,
m_axi_awready,
m_axi_wready,
m_axi_bvalid,
m_axi_arready,
m_axi_rvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_bready,
s_axi_arvalid,
s_axi_rready,
s_aresetn);
output [64:0]Q;
output [36:0]\m_axi_wdata[31] ;
output [5:0]\s_axi_bid[3] ;
output [64:0]\m_axi_arid[3] ;
output [38:0]\s_axi_rid[3] ;
output s_axi_awready;
output s_axi_wready;
output s_axi_bvalid;
output m_axi_awvalid;
output m_axi_wvalid;
output m_axi_bready;
output s_axi_arready;
output s_axi_rvalid;
output m_axi_arvalid;
output m_axi_rready;
input m_aclk;
input s_aclk;
input [36:0]I115;
input [1:0]m_axi_bresp;
input [3:0]m_axi_bid;
input [64:0]I123;
input [38:0]I127;
input [64:0]DI;
input m_axi_awready;
input m_axi_wready;
input m_axi_bvalid;
input m_axi_arready;
input m_axi_rvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_bready;
input s_axi_arvalid;
input s_axi_rready;
input s_aresetn;
wire [64:0]DI;
wire [36:0]I115;
wire [64:0]I123;
wire [38:0]I127;
wire [64:0]Q;
wire inverted_reset;
wire m_aclk;
wire [64:0]\m_axi_arid[3] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire m_axi_awready;
wire m_axi_awvalid;
wire [3:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire [36:0]\m_axi_wdata[31] ;
wire m_axi_wready;
wire m_axi_wvalid;
wire s_aclk;
wire s_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire s_axi_awready;
wire s_axi_awvalid;
wire [5:0]\s_axi_bid[3] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [38:0]\s_axi_rid[3] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
bd_auto_cc_0_fifo_generator_top \gaxi_full_lite.gread_ch.grach2.axi_rach
(.I123(I123),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_arid[3] (\m_axi_arid[3] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
bd_auto_cc_0_fifo_generator_top__parameterized2 \gaxi_full_lite.gread_ch.grdch2.axi_rdch
(.I127(I127),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.\s_axi_rid[3] (\s_axi_rid[3] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
bd_auto_cc_0_fifo_generator_top_0 \gaxi_full_lite.gwrite_ch.gwach2.axi_wach
(.DI(DI),
.Q(Q),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
bd_auto_cc_0_fifo_generator_top__parameterized0 \gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch
(.I115(I115),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_wdata[31] (\m_axi_wdata[31] ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
bd_auto_cc_0_fifo_generator_top__parameterized1 \gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch
(.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.s_aclk(s_aclk),
.\s_axi_bid[3] (\s_axi_bid[3] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid));
endmodule
module bd_auto_cc_0_memory
(Q,
E,
m_aclk,
s_aclk,
ram_full_fb_i_reg,
DI,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] );
output [64:0]Q;
input [0:0]E;
input m_aclk;
input s_aclk;
input [0:0]ram_full_fb_i_reg;
input [64:0]DI;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire [64:0]DI;
wire [0:0]E;
wire [64:0]Q;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_58 ;
wire \gdm.dm_gen.dm_n_59 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_60 ;
wire \gdm.dm_gen.dm_n_61 ;
wire \gdm.dm_gen.dm_n_62 ;
wire \gdm.dm_gen.dm_n_63 ;
wire \gdm.dm_gen.dm_n_64 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_9 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]ram_full_fb_i_reg;
wire s_aclk;
bd_auto_cc_0_dmem \gdm.dm_gen.dm
(.DI(DI),
.dout_i({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 ,\gdm.dm_gen.dm_n_58 ,\gdm.dm_gen.dm_n_59 ,\gdm.dm_gen.dm_n_60 ,\gdm.dm_gen.dm_n_61 ,\gdm.dm_gen.dm_n_62 ,\gdm.dm_gen.dm_n_63 ,\gdm.dm_gen.dm_n_64 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_64 ),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_63 ),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_62 ),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_61 ),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_60 ),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[58]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(Q[58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[59]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(Q[59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_59 ),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[60]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(Q[60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[61]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(Q[61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[62]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(Q[62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[63]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(Q[63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[64]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(Q[64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_58 ),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module bd_auto_cc_0_memory_73
(\m_axi_arid[3] ,
s_aclk,
E,
I123,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [64:0]\m_axi_arid[3] ;
input s_aclk;
input [0:0]E;
input [64:0]I123;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [64:0]I123;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_58 ;
wire \gdm.dm_gen.dm_n_59 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_60 ;
wire \gdm.dm_gen.dm_n_61 ;
wire \gdm.dm_gen.dm_n_62 ;
wire \gdm.dm_gen.dm_n_63 ;
wire \gdm.dm_gen.dm_n_64 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_9 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [64:0]\m_axi_arid[3] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
bd_auto_cc_0_dmem_81 \gdm.dm_gen.dm
(.E(E),
.I123(I123),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 ,\gdm.dm_gen.dm_n_58 ,\gdm.dm_gen.dm_n_59 ,\gdm.dm_gen.dm_n_60 ,\gdm.dm_gen.dm_n_61 ,\gdm.dm_gen.dm_n_62 ,\gdm.dm_gen.dm_n_63 ,\gdm.dm_gen.dm_n_64 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_64 ),
.Q(\m_axi_arid[3] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(\m_axi_arid[3] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(\m_axi_arid[3] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(\m_axi_arid[3] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(\m_axi_arid[3] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(\m_axi_arid[3] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(\m_axi_arid[3] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(\m_axi_arid[3] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(\m_axi_arid[3] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(\m_axi_arid[3] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(\m_axi_arid[3] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_63 ),
.Q(\m_axi_arid[3] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(\m_axi_arid[3] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(\m_axi_arid[3] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(\m_axi_arid[3] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(\m_axi_arid[3] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(\m_axi_arid[3] [24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(\m_axi_arid[3] [25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(\m_axi_arid[3] [26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(\m_axi_arid[3] [27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(\m_axi_arid[3] [28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(\m_axi_arid[3] [29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_62 ),
.Q(\m_axi_arid[3] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(\m_axi_arid[3] [30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(\m_axi_arid[3] [31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(\m_axi_arid[3] [32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(\m_axi_arid[3] [33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(\m_axi_arid[3] [34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(\m_axi_arid[3] [35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(\m_axi_arid[3] [36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(\m_axi_arid[3] [37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(\m_axi_arid[3] [38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(\m_axi_arid[3] [39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_61 ),
.Q(\m_axi_arid[3] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(\m_axi_arid[3] [40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(\m_axi_arid[3] [41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(\m_axi_arid[3] [42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(\m_axi_arid[3] [43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(\m_axi_arid[3] [44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(\m_axi_arid[3] [45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(\m_axi_arid[3] [46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(\m_axi_arid[3] [47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(\m_axi_arid[3] [48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(\m_axi_arid[3] [49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_60 ),
.Q(\m_axi_arid[3] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(\m_axi_arid[3] [50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(\m_axi_arid[3] [51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(\m_axi_arid[3] [52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(\m_axi_arid[3] [53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(\m_axi_arid[3] [54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(\m_axi_arid[3] [55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(\m_axi_arid[3] [56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(\m_axi_arid[3] [57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[58]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(\m_axi_arid[3] [58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[59]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\m_axi_arid[3] [59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_59 ),
.Q(\m_axi_arid[3] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[60]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\m_axi_arid[3] [60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[61]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\m_axi_arid[3] [61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[62]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\m_axi_arid[3] [62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[63]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\m_axi_arid[3] [63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[64]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\m_axi_arid[3] [64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_58 ),
.Q(\m_axi_arid[3] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(\m_axi_arid[3] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(\m_axi_arid[3] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(\m_axi_arid[3] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module bd_auto_cc_0_memory__parameterized0
(\m_axi_wdata[31] ,
s_aclk,
E,
I115,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [36:0]\m_axi_wdata[31] ;
input s_aclk;
input [0:0]E;
input [36:0]I115;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [36:0]I115;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_9 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [36:0]\m_axi_wdata[31] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
bd_auto_cc_0_dmem__parameterized0 \gdm.dm_gen.dm
(.E(E),
.I115(I115),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(\m_axi_wdata[31] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(\m_axi_wdata[31] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(\m_axi_wdata[31] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(\m_axi_wdata[31] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(\m_axi_wdata[31] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(\m_axi_wdata[31] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(\m_axi_wdata[31] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(\m_axi_wdata[31] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(\m_axi_wdata[31] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(\m_axi_wdata[31] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(\m_axi_wdata[31] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(\m_axi_wdata[31] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(\m_axi_wdata[31] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(\m_axi_wdata[31] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(\m_axi_wdata[31] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(\m_axi_wdata[31] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(\m_axi_wdata[31] [24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(\m_axi_wdata[31] [25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(\m_axi_wdata[31] [26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(\m_axi_wdata[31] [27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(\m_axi_wdata[31] [28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(\m_axi_wdata[31] [29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(\m_axi_wdata[31] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(\m_axi_wdata[31] [30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\m_axi_wdata[31] [31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\m_axi_wdata[31] [32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\m_axi_wdata[31] [33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\m_axi_wdata[31] [34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\m_axi_wdata[31] [35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\m_axi_wdata[31] [36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(\m_axi_wdata[31] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(\m_axi_wdata[31] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(\m_axi_wdata[31] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(\m_axi_wdata[31] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(\m_axi_wdata[31] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(\m_axi_wdata[31] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(\m_axi_wdata[31] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module bd_auto_cc_0_memory__parameterized1
(\s_axi_bid[3] ,
m_aclk,
E,
m_axi_bresp,
m_axi_bid,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [5:0]\s_axi_bid[3] ;
input m_aclk;
input [0:0]E;
input [1:0]m_axi_bresp;
input [3:0]m_axi_bid;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_5 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [3:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
wire [5:0]\s_axi_bid[3] ;
bd_auto_cc_0_dmem__parameterized1 \gdm.dm_gen.dm
(.E(E),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\s_axi_bid[3] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\s_axi_bid[3] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\s_axi_bid[3] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\s_axi_bid[3] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\s_axi_bid[3] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\s_axi_bid[3] [5]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module bd_auto_cc_0_memory__parameterized2
(\s_axi_rid[3] ,
m_aclk,
E,
I127,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [38:0]\s_axi_rid[3] ;
input m_aclk;
input [0:0]E;
input [38:0]I127;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [38:0]I127;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_9 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
wire [38:0]\s_axi_rid[3] ;
bd_auto_cc_0_dmem__parameterized2 \gdm.dm_gen.dm
(.E(E),
.I127(I127),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(\s_axi_rid[3] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(\s_axi_rid[3] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(\s_axi_rid[3] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(\s_axi_rid[3] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(\s_axi_rid[3] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(\s_axi_rid[3] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(\s_axi_rid[3] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(\s_axi_rid[3] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(\s_axi_rid[3] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(\s_axi_rid[3] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(\s_axi_rid[3] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(\s_axi_rid[3] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(\s_axi_rid[3] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(\s_axi_rid[3] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(\s_axi_rid[3] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(\s_axi_rid[3] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(\s_axi_rid[3] [24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(\s_axi_rid[3] [25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(\s_axi_rid[3] [26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(\s_axi_rid[3] [27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(\s_axi_rid[3] [28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(\s_axi_rid[3] [29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(\s_axi_rid[3] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(\s_axi_rid[3] [30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(\s_axi_rid[3] [31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(\s_axi_rid[3] [32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\s_axi_rid[3] [33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\s_axi_rid[3] [34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\s_axi_rid[3] [35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\s_axi_rid[3] [36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\s_axi_rid[3] [37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\s_axi_rid[3] [38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(\s_axi_rid[3] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(\s_axi_rid[3] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(\s_axi_rid[3] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(\s_axi_rid[3] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(\s_axi_rid[3] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(\s_axi_rid[3] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(\s_axi_rid[3] [9]),
.R(1'b0));
endmodule
module bd_auto_cc_0_rd_bin_cntr
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
s_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire [0:0]out;
wire [3:0]plusOp__6;
wire ram_empty_i_i_2__2_n_0;
wire ram_empty_i_i_3__2_n_0;
wire ram_empty_i_reg;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__2
(.I0(Q[0]),
.O(plusOp__6[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__6[1]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__6[2]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__2
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__6[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.D(plusOp__6[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__6[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__6[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__6[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__2
(.I0(ram_empty_i_i_2__2_n_0),
.I1(ram_empty_i_i_3__2_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__2_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module bd_auto_cc_0_rd_bin_cntr_20
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
m_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]out;
wire [3:0]plusOp__0;
wire ram_empty_i_i_2__0_n_0;
wire ram_empty_i_i_3__0_n_0;
wire ram_empty_i_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__0
(.I0(Q[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__0
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__0[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.D(plusOp__0[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__0[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__0[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__0[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__0
(.I0(ram_empty_i_i_2__0_n_0),
.I1(ram_empty_i_i_3__0_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__0_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module bd_auto_cc_0_rd_bin_cntr_41
(Q,
ram_empty_i_reg,
\gnxpm_cdc.rd_pntr_gc_reg[2] ,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
m_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]out;
wire [0:0]E;
wire [3:0]Q;
wire [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]out;
wire [3:0]plusOp;
wire ram_empty_i_i_2_n_0;
wire ram_empty_i_i_3_n_0;
wire ram_empty_i_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.D(plusOp[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(\gnxpm_cdc.rd_pntr_gc_reg[2] [0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(\gnxpm_cdc.rd_pntr_gc_reg[2] [1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(\gnxpm_cdc.rd_pntr_gc_reg[2] [2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1
(.I0(ram_empty_i_i_2_n_0),
.I1(ram_empty_i_i_3_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module bd_auto_cc_0_rd_bin_cntr_62
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
s_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire [0:0]out;
wire [3:0]plusOp__8;
wire ram_empty_i_i_2__3_n_0;
wire ram_empty_i_i_3__3_n_0;
wire ram_empty_i_reg;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__3
(.I0(Q[0]),
.O(plusOp__8[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__3
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__8[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__3
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__8[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__3
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__8[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.D(plusOp__8[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__8[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__8[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__8[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__3
(.I0(ram_empty_i_i_2__3_n_0),
.I1(ram_empty_i_i_3__3_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__3_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module bd_auto_cc_0_rd_bin_cntr_86
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
m_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]out;
wire [3:0]plusOp__2;
wire ram_empty_i_i_2__1_n_0;
wire ram_empty_i_i_3__1_n_0;
wire ram_empty_i_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__1
(.I0(Q[0]),
.O(plusOp__2[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__2[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__2[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__2[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.D(plusOp__2[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__2[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__2[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__2[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__1
(.I0(ram_empty_i_i_2__1_n_0),
.I1(ram_empty_i_i_3__1_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__1_n_0));
endmodule
module bd_auto_cc_0_rd_fwft
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[5] ,
s_axi_bvalid,
s_aclk,
out,
s_axi_bready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[5] ;
output s_axi_bvalid;
input s_aclk;
input [1:0]out;
input s_axi_bready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[5] ;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire s_aclk;
wire s_axi_bready;
wire s_axi_bvalid;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__2
(.I0(ram_empty_fb_i_reg),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__2
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_bready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__2
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_bready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__2
(.I0(curr_fwft_state[1]),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[5]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_bready),
.O(\goreg_dm.dout_i_reg[5] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__2
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(s_axi_bready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__2
(.I0(curr_fwft_state[1]),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__2
(.I0(curr_fwft_state[1]),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
LUT1 #(
.INIT(2'h1))
s_axi_bvalid_INST_0
(.I0(empty_fwft_i),
.O(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module bd_auto_cc_0_rd_fwft_18
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[36] ,
m_axi_wvalid,
m_aclk,
out,
m_axi_wready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[36] ;
output m_axi_wvalid;
input m_aclk;
input [1:0]out;
input m_axi_wready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[36] ;
wire m_aclk;
wire m_axi_wready;
wire m_axi_wvalid;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__0
(.I0(ram_empty_fb_i_reg),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__0
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_wready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__0
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_wready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__0
(.I0(curr_fwft_state[1]),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[36]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_wready),
.O(\goreg_dm.dout_i_reg[36] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__0
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(m_axi_wready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__0
(.I0(curr_fwft_state[1]),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT1 #(
.INIT(2'h1))
m_axi_wvalid_INST_0
(.I0(empty_fwft_i),
.O(m_axi_wvalid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__0
(.I0(curr_fwft_state[1]),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module bd_auto_cc_0_rd_fwft_39
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[64] ,
m_axi_awvalid,
m_aclk,
out,
m_axi_awready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[64] ;
output m_axi_awvalid;
input m_aclk;
input [1:0]out;
input m_axi_awready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[64] ;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1
(.I0(ram_empty_fb_i_reg),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_awready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_awready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1
(.I0(curr_fwft_state[1]),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[64]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_awready),
.O(\goreg_dm.dout_i_reg[64] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(m_axi_awready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(curr_fwft_state[1]),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT1 #(
.INIT(2'h1))
m_axi_awvalid_INST_0
(.I0(empty_fwft_i),
.O(m_axi_awvalid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5
(.I0(curr_fwft_state[1]),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module bd_auto_cc_0_rd_fwft_60
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[38] ,
s_axi_rvalid,
s_aclk,
out,
s_axi_rready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[38] ;
output s_axi_rvalid;
input s_aclk;
input [1:0]out;
input s_axi_rready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[38] ;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire s_aclk;
wire s_axi_rready;
wire s_axi_rvalid;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__3
(.I0(ram_empty_fb_i_reg),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__3
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_rready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__3
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_rready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__3
(.I0(curr_fwft_state[1]),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[38]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_rready),
.O(\goreg_dm.dout_i_reg[38] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__3
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(s_axi_rready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__3
(.I0(curr_fwft_state[1]),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__3
(.I0(curr_fwft_state[1]),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
LUT1 #(
.INIT(2'h1))
s_axi_rvalid_INST_0
(.I0(empty_fwft_i),
.O(s_axi_rvalid));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module bd_auto_cc_0_rd_fwft_84
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[64] ,
m_axi_arvalid,
m_aclk,
out,
m_axi_arready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[64] ;
output m_axi_arvalid;
input m_aclk;
input [1:0]out;
input m_axi_arready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[64] ;
wire m_aclk;
wire m_axi_arready;
wire m_axi_arvalid;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__1
(.I0(ram_empty_fb_i_reg),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__1
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_arready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__1
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_arready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__1
(.I0(curr_fwft_state[1]),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[64]_i_1__0
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_arready),
.O(\goreg_dm.dout_i_reg[64] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(m_axi_arready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__1
(.I0(curr_fwft_state[1]),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT1 #(
.INIT(2'h1))
m_axi_arvalid_INST_0
(.I0(empty_fwft_i),
.O(m_axi_arvalid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__1
(.I0(curr_fwft_state[1]),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
endmodule
module bd_auto_cc_0_rd_logic
(Q,
E,
\goreg_dm.dout_i_reg[5] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
s_axi_bvalid,
s_aclk,
out,
s_axi_bready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[5] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output s_axi_bvalid;
input s_aclk;
input [1:0]out;
input s_axi_bready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[5] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
wire s_aclk;
wire s_axi_bready;
wire s_axi_bvalid;
bd_auto_cc_0_rd_fwft \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[5] (\goreg_dm.dout_i_reg[5] ),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ),
.s_aclk(s_aclk),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid));
bd_auto_cc_0_rd_status_flags_as \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out),
.s_aclk(s_aclk));
bd_auto_cc_0_rd_bin_cntr rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module bd_auto_cc_0_rd_logic_28
(Q,
E,
\goreg_dm.dout_i_reg[64] ,
\gnxpm_cdc.rd_pntr_gc_reg[2] ,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
m_axi_awvalid,
m_aclk,
out,
m_axi_awready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[64] ;
output [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output m_axi_awvalid;
input m_aclk;
input [1:0]out;
input m_axi_awready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]E;
wire [2:0]Q;
wire [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[64] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
bd_auto_cc_0_rd_fwft_39 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[64] (\goreg_dm.dout_i_reg[64] ),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ));
bd_auto_cc_0_rd_status_flags_as_40 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out));
bd_auto_cc_0_rd_bin_cntr_41 rpntr
(.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[2] (\gnxpm_cdc.rd_pntr_gc_reg[2] ),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.m_aclk(m_aclk),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module bd_auto_cc_0_rd_logic_49
(Q,
E,
\goreg_dm.dout_i_reg[38] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
s_axi_rvalid,
s_aclk,
out,
s_axi_rready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[38] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output s_axi_rvalid;
input s_aclk;
input [1:0]out;
input s_axi_rready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[38] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
wire s_aclk;
wire s_axi_rready;
wire s_axi_rvalid;
bd_auto_cc_0_rd_fwft_60 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[38] (\goreg_dm.dout_i_reg[38] ),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ),
.s_aclk(s_aclk),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
bd_auto_cc_0_rd_status_flags_as_61 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out),
.s_aclk(s_aclk));
bd_auto_cc_0_rd_bin_cntr_62 rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module bd_auto_cc_0_rd_logic_7
(Q,
E,
\goreg_dm.dout_i_reg[36] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
m_axi_wvalid,
m_aclk,
out,
m_axi_wready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[36] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output m_axi_wvalid;
input m_aclk;
input [1:0]out;
input m_axi_wready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[36] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire m_aclk;
wire m_axi_wready;
wire m_axi_wvalid;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
bd_auto_cc_0_rd_fwft_18 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[36] (\goreg_dm.dout_i_reg[36] ),
.m_aclk(m_aclk),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ));
bd_auto_cc_0_rd_status_flags_as_19 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out));
bd_auto_cc_0_rd_bin_cntr_20 rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.m_aclk(m_aclk),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module bd_auto_cc_0_rd_logic_71
(Q,
E,
\goreg_dm.dout_i_reg[64] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
m_axi_arvalid,
m_aclk,
out,
m_axi_arready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[64] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output m_axi_arvalid;
input m_aclk;
input [1:0]out;
input m_axi_arready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[64] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire m_aclk;
wire m_axi_arready;
wire m_axi_arvalid;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
bd_auto_cc_0_rd_fwft_84 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[64] (\goreg_dm.dout_i_reg[64] ),
.m_aclk(m_aclk),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ));
bd_auto_cc_0_rd_status_flags_as_85 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out));
bd_auto_cc_0_rd_bin_cntr_86 rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.m_aclk(m_aclk),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4));
endmodule
module bd_auto_cc_0_rd_status_flags_as
(out,
\gc0.count_d1_reg[2] ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire s_aclk;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module bd_auto_cc_0_rd_status_flags_as_19
(out,
\gc0.count_d1_reg[2] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module bd_auto_cc_0_rd_status_flags_as_40
(out,
\gc0.count_d1_reg[2] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module bd_auto_cc_0_rd_status_flags_as_61
(out,
\gc0.count_d1_reg[2] ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire s_aclk;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module bd_auto_cc_0_rd_status_flags_as_85
(out,
\gc0.count_d1_reg[2] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
module bd_auto_cc_0_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
s_aclk,
m_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input s_aclk;
input m_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
bd_auto_cc_0_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
bd_auto_cc_0_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_3 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
bd_auto_cc_0_synchronizer_ff_4 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_5 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.m_aclk(m_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module bd_auto_cc_0_reset_blk_ramfifo_30
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
m_aclk,
s_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input m_aclk;
input s_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
bd_auto_cc_0_synchronizer_ff_31 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
bd_auto_cc_0_synchronizer_ff_32 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_33 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
bd_auto_cc_0_synchronizer_ff_34 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_35 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.m_aclk(m_aclk));
bd_auto_cc_0_synchronizer_ff_36 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.s_aclk(s_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module bd_auto_cc_0_reset_blk_ramfifo_51
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ,
s_aclk,
m_aclk,
s_aresetn);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
output \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ;
input s_aclk;
input m_aclk;
input s_aresetn;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire s_aresetn;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
bd_auto_cc_0_synchronizer_ff_52 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_53 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
bd_auto_cc_0_synchronizer_ff_54 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_55 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
bd_auto_cc_0_synchronizer_ff_56 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_57 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.m_aclk(m_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_rd_reg2));
LUT1 #(
.INIT(2'h1))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1
(.I0(s_aresetn),
.O(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module bd_auto_cc_0_reset_blk_ramfifo_74
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
m_aclk,
s_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input m_aclk;
input s_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
bd_auto_cc_0_synchronizer_ff_75 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
bd_auto_cc_0_synchronizer_ff_76 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_77 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
bd_auto_cc_0_synchronizer_ff_78 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_79 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.m_aclk(m_aclk));
bd_auto_cc_0_synchronizer_ff_80 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.s_aclk(s_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module bd_auto_cc_0_reset_blk_ramfifo_9
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
m_aclk,
s_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input m_aclk;
input s_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
bd_auto_cc_0_synchronizer_ff_10 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
bd_auto_cc_0_synchronizer_ff_11 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_12 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
bd_auto_cc_0_synchronizer_ff_13 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
bd_auto_cc_0_synchronizer_ff_14 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.m_aclk(m_aclk));
bd_auto_cc_0_synchronizer_ff_15 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.s_aclk(s_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
module bd_auto_cc_0_synchronizer_ff
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_1
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_10
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_11
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_12
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_13
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_14
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_15
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_2
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_3
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_31
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_32
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_33
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_34
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_35
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_36
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_4
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_5
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_52
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_53
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_54
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__3
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_55
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__3
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_56
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_57
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_75
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_76
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_77
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__2
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_78
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__2
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_79
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff_80
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized0
(D,
Q,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized0_21
(D,
Q,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized0_42
(D,
Q,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized0_63
(D,
Q,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized0_87
(D,
Q,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized1
(D,
Q,
m_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized1_22
(D,
Q,
s_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized1_43
(D,
Q,
s_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized1_64
(D,
Q,
m_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized1_88
(D,
Q,
s_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized2
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized2_23
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized2_44
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized2_65
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized2_89
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized3
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized3_24
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized3_45
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized3_66
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized3_90
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized4
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized4_25
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized4_46
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized4_67
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__3
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized4_91
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__2
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized5
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized5_26
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized5_47
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized5_68
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__3
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module bd_auto_cc_0_synchronizer_ff__parameterized5_92
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__2
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
module bd_auto_cc_0_wr_bin_cntr
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
m_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire [3:0]plusOp__1;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__1[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__1[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__1[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.D(plusOp__1[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__1[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__1[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module bd_auto_cc_0_wr_bin_cntr_17
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire [3:0]plusOp__5;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__2
(.I0(Q[0]),
.O(plusOp__5[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__5[1]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__5[2]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__2
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__5[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__5[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.D(plusOp__5[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__5[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__5[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module bd_auto_cc_0_wr_bin_cntr_38
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire [3:0]plusOp__4;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__1
(.I0(Q[0]),
.O(plusOp__4[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__4[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__4[2]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__4[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__4[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.D(plusOp__4[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__4[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__4[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module bd_auto_cc_0_wr_bin_cntr_59
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
m_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire [3:0]plusOp__3;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__0
(.I0(Q[0]),
.O(plusOp__3[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__3[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__3[2]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__0
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__3[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__3[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.D(plusOp__3[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__3[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__3[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module bd_auto_cc_0_wr_bin_cntr_83
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire [3:0]plusOp__7;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__3
(.I0(Q[0]),
.O(plusOp__7[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__3
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__7[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__3
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__7[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__3
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__7[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__7[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.D(plusOp__7[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__7[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__7[3]),
.Q(Q[3]));
endmodule
module bd_auto_cc_0_wr_logic
(Q,
ram_full_fb_i_reg,
E,
m_axi_bready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_bvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output m_axi_bready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_bvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire m_axi_bready;
wire m_axi_bvalid;
wire out;
wire ram_full_fb_i_reg;
wire [3:3]wr_pntr_plus2;
bd_auto_cc_0_wr_status_flags_as \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.m_aclk(m_aclk),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg));
bd_auto_cc_0_wr_bin_cntr wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.m_aclk(m_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module bd_auto_cc_0_wr_logic_29
(Q,
ram_full_fb_i_reg,
E,
s_axi_awready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_awvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output s_axi_awready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_awvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire out;
wire ram_full_fb_i_reg;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
wire [3:3]wr_pntr_plus2;
bd_auto_cc_0_wr_status_flags_as_37 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
bd_auto_cc_0_wr_bin_cntr_38 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module bd_auto_cc_0_wr_logic_50
(Q,
ram_full_fb_i_reg,
E,
m_axi_rready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_rvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output m_axi_rready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_rvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire out;
wire ram_full_fb_i_reg;
wire [3:3]wr_pntr_plus2;
bd_auto_cc_0_wr_status_flags_as_58 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg));
bd_auto_cc_0_wr_bin_cntr_59 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.m_aclk(m_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module bd_auto_cc_0_wr_logic_72
(Q,
ram_full_fb_i_reg,
E,
s_axi_arready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_arvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output s_axi_arready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_arvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire out;
wire ram_full_fb_i_reg;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
wire [3:3]wr_pntr_plus2;
bd_auto_cc_0_wr_status_flags_as_82 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
bd_auto_cc_0_wr_bin_cntr_83 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module bd_auto_cc_0_wr_logic_8
(Q,
ram_full_fb_i_reg,
E,
s_axi_wready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_wvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output s_axi_wready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_wvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire out;
wire ram_full_fb_i_reg;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
wire [3:3]wr_pntr_plus2;
bd_auto_cc_0_wr_status_flags_as_16 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
bd_auto_cc_0_wr_bin_cntr_17 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.s_aclk(s_aclk));
endmodule
module bd_auto_cc_0_wr_status_flags_as
(ram_full_fb_i_reg_0,
E,
m_axi_bready,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_bvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output m_axi_bready;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_bvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire m_aclk;
wire m_axi_bready;
wire m_axi_bvalid;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1
(.I0(m_axi_bvalid),
.I1(ram_full_fb_i),
.O(E));
LUT1 #(
.INIT(2'h1))
m_axi_bready_INST_0
(.I0(ram_full_i),
.O(m_axi_bready));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3
(.I0(ram_full_fb_i),
.I1(m_axi_bvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module bd_auto_cc_0_wr_status_flags_as_16
(ram_full_fb_i_reg_0,
E,
s_axi_wready,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_wvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output s_axi_wready;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_wvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__2
(.I0(s_axi_wvalid),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__2
(.I0(ram_full_fb_i),
.I1(s_axi_wvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
LUT1 #(
.INIT(2'h1))
s_axi_wready_INST_0
(.I0(ram_full_i),
.O(s_axi_wready));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module bd_auto_cc_0_wr_status_flags_as_37
(ram_full_fb_i_reg_0,
E,
s_axi_awready,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_awvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output s_axi_awready;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_awvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__1
(.I0(s_axi_awvalid),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__1
(.I0(ram_full_fb_i),
.I1(s_axi_awvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
LUT1 #(
.INIT(2'h1))
s_axi_awready_INST_0
(.I0(ram_full_i),
.O(s_axi_awready));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module bd_auto_cc_0_wr_status_flags_as_58
(ram_full_fb_i_reg_0,
E,
m_axi_rready,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_rvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output m_axi_rready;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_rvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__0
(.I0(m_axi_rvalid),
.I1(ram_full_fb_i),
.O(E));
LUT1 #(
.INIT(2'h1))
m_axi_rready_INST_0
(.I0(ram_full_i),
.O(m_axi_rready));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__0
(.I0(ram_full_fb_i),
.I1(m_axi_rvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module bd_auto_cc_0_wr_status_flags_as_82
(ram_full_fb_i_reg_0,
E,
s_axi_arready,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_arvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output s_axi_arready;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_arvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__3
(.I0(s_axi_arvalid),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__3
(.I0(ram_full_fb_i),
.I1(s_axi_arvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
LUT1 #(
.INIT(2'h1))
s_axi_arready_INST_0
(.I0(ram_full_i),
.O(s_axi_arready));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_1_V
`define SKY130_FD_SC_HDLL__OR4_1_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_2_V
`define SKY130_FD_SC_LP__SDFSBP_2_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_2_V
|
`timescale 1 ns / 100 ps
module tb_radar_top();
reg [11:0] adc_in;
reg [15:0] counter;
reg clk, reset_n;
reg [11:0] input_vector [0:16383];
wire fft_next_out, next_data, data, serial_clk;
wire [11:0] mag_out1, mag_out2;
integer file, j, m;
initial clk = 0;
always #25 clk = ~clk; //20 MHz
Radar_top radar_inst(.clk(clk), .reset_n(reset_n),
.mag_out1(mag_out1), .mag_out2(mag_out2),
.fft_next_out(fft_next_out),
.adc_in(adc_in),
.next_data(next_data), .data(data), .clk_div_16(serial_clk));
initial counter = 0;
always @(posedge serial_clk) begin
counter <= counter+1;
if(counter % 1000 == 0)
$display("Counter = %d.", counter/2);
end
initial begin
adc_in <= 0;
reset_n <= 1;
@(posedge clk);
$readmemb("FFT_Input_54k_96k.txt", input_vector);
for (j=0; j < 16384; j = j+1) begin
adc_in <= input_vector[j];
@(posedge clk);
@(posedge clk);
end
$display("Done input vector, counter = %d", counter);
end
initial begin
@(posedge serial_clk);
@(posedge serial_clk);
@(posedge serial_clk);
@(posedge next_data);
@(posedge serial_clk);
@(posedge serial_clk);
@(posedge serial_clk); #100;
$display("--- begin output ---");
file = $fopen("Serial_output_final.txt") ;
for(m = 0; m < 2048 * 12; m = m + 1) begin
if(m % 12 == 0) begin
$fwrite(file, "\n");
//$write("\ndata=");
end
$fwrite(file, "%b", data);
//$write("%b", data);
@(posedge serial_clk);
@(posedge serial_clk);#100;
end
$fdisplay(file, "%b", data);
$fclose(file);
$display("--- done output ---");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND3_FUNCTIONAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand3 (
VPWR,
VGND,
Y ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_FUNCTIONAL_PP_V |
(** * Gen: Generalizing Induction Hypotheses *)
(* $Date: 2011-06-07 16:49:17 -0400 (Tue, 07 Jun 2011) $ *)
Require Export Poly.
(** In the previous chapter, we saw a proof that the [double] function
is injective. The way we _start_ this proof is a little bit
delicate: if we begin it with
[[
intros n. induction n.
]]
all is well. But if we begin it with
[[
intros n m. induction n.
]]
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck. We need the assertion in order to
rewrite the final goal (subgoal 2 at this point) to an
identity. But the induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the assertion is not provable. *)
Admitted.
(** What went wrong here?
The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context
-- intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we can prove
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.)
To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective' : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for *every* [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O". inversion eq. (* The 0 case is trivial *)
SCase "m = S m'".
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
assert (n' = m') as H.
SSCase "Proof of assertion". apply IHn'.
inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** So what we've learned is that we need to be careful about
using induction to try to prove something too specific: If
we're proving a property of [n] and [m] by induction on [n],
we may need to leave [m] generic.
However, this strategy doesn't always apply directly;
sometimes a little rearrangement is needed. Suppose, for
example, that we had decided we wanted to prove
[double_injective] by induction on [m] instead of [n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck again, just like before. *)
Admitted.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) What can we do about this?
One possibility is to rewrite the statement of the lemma so
that [m] is quantified before [n]. This will work, but it's
not nice: We don't want to have to mangle the statements of
lemmas to fit the needs of a particular strategy for proving
them -- we want to state them in the most clear and natural
way.
What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
apply IHm'. inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that the
proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Carry out this proof by induction on [m]. *)
Theorem plus_n_n_injective_take2 : forall n m,
n + n = m + m ->
n = m.
Proof.
(* FILL IN HERE *) Admitted.
(** Now prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index (S n) l = None.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_opt) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_TB_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_TB_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlybuf4s15kapwr.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg KAPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 KAPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 KAPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__dlybuf4s15kapwr dut (.A(A), .VPWR(VPWR), .VGND(VGND), .KAPWR(KAPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_TB_V
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Generated by harness_gen.py
* From: simpleuart.v
*/
module top(input wire clk, input wire stb, input wire di, output wire do);
localparam integer DIN_N = 72;
localparam integer DOUT_N = 66;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
simpleuart dut(
.clk(clk),
.resetn(din[0]),
.ser_tx(dout[0]),
.ser_rx(din[1]),
.reg_div_we(din[5:2]),
.reg_div_di(din[37:6]),
.reg_div_do(dout[32:1]),
.reg_dat_we(din[38]),
.reg_dat_re(din[39]),
.reg_dat_di(din[71:40]),
.reg_dat_do(dout[64:33]),
.reg_dat_wait(dout[65])
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: IPpllGenerator.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.0.0 Build 614 04/24/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module IPpllGenerator (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [4:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 6,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 5,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 4,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=IPpllGenerator",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "60.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "60.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "IPpllGenerator.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL IPpllGenerator.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPpllGenerator.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPpllGenerator.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPpllGenerator.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPpllGenerator.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPpllGenerator_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL IPpllGenerator_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*****************************************************************************
* Copyright (c) 2015 by Daniel Grabowski.
*
* This file is part of FrSim.
*
* FrSim is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* FrSim is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with FrSim. If not, see <http://www.gnu.org/licenses/>.
*
* Created by: Daniel Grabowski, Andrew Worcester
*
*****************************************************************************/
`timescale 1ns/1ns
module ivltest();
reg clk;
reg val;
reg c2;
initial
begin
clk <= 0;
val <= 0;
c2 <= 0;
forever
#10 clk <= ~clk;
end
initial
$dumpvars;
initial
#1000 $finish;
initial
begin
$frsim_system;
end
always @ (posedge clk)
c2 <= ~c2;
endmodule // ivltest
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_common (
// reset and clocks
qpll_ref_clk_in,
qpll_rst,
qpll_clk,
qpll_ref_clk,
qpll_locked,
// drp interface
up_clk,
up_drp_sel,
up_drp_addr,
up_drp_wr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready);
// parameters
parameter integer GTH_OR_GTX_N = 0;
parameter integer QPLL_ENABLE = 1;
parameter integer QPLL_REFCLK_DIV = 2;
parameter [26:0] QPLL_CFG = 27'h06801C1;
parameter integer QPLL_FBDIV_RATIO = 1'b1;
parameter [ 9:0] QPLL_FBDIV = 10'b0000110000;
// reset and clocks
input qpll_ref_clk_in;
input qpll_rst;
output qpll_clk;
output qpll_ref_clk;
output qpll_locked;
// drp interface
input up_clk;
input up_drp_sel;
input [11:0] up_drp_addr;
input up_drp_wr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
// instantiations
generate
if (QPLL_ENABLE == 0) begin
assign qpll_clk = 1'd0;
assign qpll_ref_clk = 1'd0;
assign qpll_locked = 1'd0;
assign up_drp_rdata = 16'd0;
assign up_drp_ready = 1'd0;
end
if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 0)) begin
GTXE2_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("3.0"),
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
i_gtxe2_common (
.DRPCLK (up_clk),
.DRPEN (up_drp_sel),
.DRPADDR (up_drp_addr[7:0]),
.DRPWE (up_drp_wr),
.DRPDI (up_drp_wdata),
.DRPDO (up_drp_rdata),
.DRPRDY (up_drp_ready),
.GTGREFCLK (1'd0),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTREFCLK0 (qpll_ref_clk_in),
.GTREFCLK1 (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.QPLLDMONITOR (),
.QPLLOUTCLK (qpll_clk),
.QPLLOUTREFCLK (qpll_ref_clk),
.REFCLKOUTMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (qpll_locked),
.QPLLLOCKDETCLK (up_clk),
.QPLLLOCKEN (1'd1),
.QPLLOUTRESET (1'd0),
.QPLLPD (1'd0),
.QPLLREFCLKLOST (),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (qpll_rst),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (1'd1));
end
if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 1)) begin
GTHE3_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_VERSION (2),
.SARC_EN (1'b1),
.SARC_SEL (1'b0),
.SDM0_DATA_PIN_SEL (1'b0),
.SDM0_WIDTH_PIN_SEL (1'b0),
.SDM1_DATA_PIN_SEL (1'b0),
.SDM1_WIDTH_PIN_SEL (1'b0),
.BIAS_CFG0 (16'b0000000000000000),
.BIAS_CFG1 (16'b0000000000000000),
.BIAS_CFG2 (16'b0000000000000000),
.BIAS_CFG3 (16'b0000000001000000),
.BIAS_CFG4 (16'b0000000000000000),
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
.POR_CFG (16'b0000000000000100),
.QPLL0_CFG0 (16'b0011000000011100),
.QPLL0_CFG1 (16'b0000000000011000),
.QPLL0_CFG1_G3 (16'b0000000000011000),
.QPLL0_CFG2 (16'b0000000001001000),
.QPLL0_CFG2_G3 (16'b0000000001001000),
.QPLL0_CFG3 (16'b0000000100100000),
.QPLL0_CFG4 (16'b0000000000001001),
.QPLL0_INIT_CFG0 (16'b0000000000000000),
.QPLL0_LOCK_CFG (16'b0010010111101000),
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL0_SDM_CFG0 (16'b0000000000000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1_CFG0 (16'b0011000000011100),
.QPLL1_CFG1 (16'b0000000000011000),
.QPLL1_CFG1_G3 (16'b0000000000011000),
.QPLL1_CFG2 (16'b0000000001000000),
.QPLL1_CFG2_G3 (16'b0000000001000000),
.QPLL1_CFG3 (16'b0000000100100000),
.QPLL1_CFG4 (16'b0000000000001001),
.QPLL1_INIT_CFG0 (16'b0000000000000000),
.QPLL1_LOCK_CFG (16'b0010010111101000),
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL1_SDM_CFG0 (16'b0000000000000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'b0000000000000000),
.RSVD_ATTR1 (16'b0000000000000000),
.RSVD_ATTR2 (16'b0000000000000000),
.RSVD_ATTR3 (16'b0000000000000000),
.SDM0DATA1_0 (16'b0000000000000000),
.SDM0INITSEED0_0 (16'b0000000000000000),
.SDM1DATA1_0 (16'b0000000000000000),
.SDM1INITSEED0_0 (16'b0000000000000000),
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.QPLL0_INIT_CFG1 (8'b00000000),
.QPLL1_INIT_CFG1 (8'b00000000),
.SDM0DATA1_1 (9'b000000000),
.SDM0INITSEED0_1 (9'b000000000),
.SDM1DATA1_1 (9'b000000000),
.SDM1INITSEED0_1 (9'b000000000),
.BIAS_CFG_RSVD (10'b0000000000),
.QPLL0_CP (10'b0000011111),
.QPLL0_CP_G3 (10'b1111111111),
.QPLL0_LPF (10'b1111111111),
.QPLL0_LPF_G3 (10'b0000010101),
.QPLL1_CP (10'b0000011111),
.QPLL1_CP_G3 (10'b1111111111),
.QPLL1_LPF (10'b1111111111),
.QPLL1_LPF_G3 (10'b0000010101),
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (80),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV))
i_gthe3_common (
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b11111),
.BGRCALOVRDENB (1'd1),
.DRPADDR (up_drp_addr[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_drp_wdata),
.DRPEN (up_drp_sel),
.DRPWE (up_drp_wr),
.GTGREFCLK0 (1'd0),
.GTGREFCLK1 (1'd0),
.GTNORTHREFCLK00 (1'd0),
.GTNORTHREFCLK01 (1'd0),
.GTNORTHREFCLK10 (1'd0),
.GTNORTHREFCLK11 (1'd0),
.GTREFCLK00 (qpll_ref_clk_in),
.GTREFCLK01 (1'd0),
.GTREFCLK10 (1'd0),
.GTREFCLK11 (1'd0),
.GTSOUTHREFCLK00 (1'd0),
.GTSOUTHREFCLK01 (1'd0),
.GTSOUTHREFCLK10 (1'd0),
.GTSOUTHREFCLK11 (1'd0),
.PMARSVD0 (8'd0),
.PMARSVD1 (8'd0),
.QPLLRSVD1 (8'd0),
.QPLLRSVD2 (5'd0),
.QPLLRSVD3 (5'd0),
.QPLLRSVD4 (8'd0),
.QPLL0CLKRSVD0 (1'd0),
.QPLL0CLKRSVD1 (1'd0),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'd1),
.QPLL0PD (1'd0),
.QPLL0REFCLKSEL (3'b001),
.QPLL0RESET (qpll_rst),
.QPLL1CLKRSVD0 (1'd0),
.QPLL1CLKRSVD1 (1'd0),
.QPLL1LOCKDETCLK (1'd0),
.QPLL1LOCKEN (1'd0),
.QPLL1PD (1'd1),
.QPLL1REFCLKSEL (3'b001),
.QPLL1RESET (1'd1),
.RCALENB (1'd1),
.DRPDO (up_drp_rdata),
.DRPRDY (up_drp_ready),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.QPLL0FBCLKLOST (),
.QPLL0LOCK (qpll_locked),
.QPLL0OUTCLK (qpll_clk),
.QPLL0OUTREFCLK (qpll_ref_clk),
.QPLL0REFCLKLOST (),
.QPLL1FBCLKLOST (),
.QPLL1LOCK (),
.QPLL1OUTCLK (),
.QPLL1OUTREFCLK (),
.QPLL1REFCLKLOST (),
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0_SEL (),
.RXRECCLK1_SEL ());
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
module lab5(CLK, RESET, IOA, IOB, IOC, EN_L, PC, NextPC, Iin, DataA, DataB, DataC, DataD, Din, MW, IOD, IOE, IOF, IOG);
input CLK;
input RESET;
input [7:0] IOA;
input [7:0] IOB;
input [7:0] IOC;
input EN_L;
output [7:0] PC;
output [7:0] NextPC;
output [15:0] Iin;
output [7:0] DataA;
output [7:0] DataB;
output [7:0] DataC;
output [7:0] DataD;
output [7:0] Din;
output MW;
output [7:0] IOD;
output [7:0] IOE;
output [7:0] IOF;
output [7:0] IOG;
cpu proc(
.CLK(CLK),
.RESET(RESET),
.PC(PC),
.NextPC(NextPC),
.Iin(Iin),
.DataA(DataA),
.DataB(DataB),
.DataC(DataC),
.DataD(DataD),
.Din(Din),
.MW(MW),
.EN_L(EN_L)
);
// BELOW IS THE ONLY LINE YOU SHOULD HAVE TO MODIFY IN THIS FILE
lab5iram1B program2run(
.CLK(CLK),
.RESET(RESET),
.ADDR(PC),
.Q(Iin)
);
lab5dram memory(
.CLK(CLK),
.RESET(RESET),
.ADDR(DataD),
.DATA(DataB),
.MW(MW),
.Q(Din),
.IOA(IOA),
.IOB(IOB),
.IOC(IOC),
.IOD(IOD),
.IOE(IOE),
.IOF(IOF),
.IOG(IOG)
);
endmodule
|
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBN_BLACKBOX_V
`define SKY130_FD_SC_LS__DLXBN_BLACKBOX_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBN_BLACKBOX_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Maintain_Range_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Maintain_Range_block1
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Maintain_Range
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Maintain_Range_block1
(
In1,
Out1
);
input signed [35:0] In1; // sfix36_En46
output signed [17:0] Out1; // sfix18_En28
wire signed [17:0] Data_Type_Conversion_out1; // sfix18_En28
// <S28>/Data Type Conversion
assign Data_Type_Conversion_out1 = In1[35:18];
assign Out1 = Data_Type_Conversion_out1;
endmodule // velocityControlHdl_Maintain_Range_block1
|
`include "bch_defs.vh"
module xilinx_error_dec #(
parameter T = 2,
parameter DATA_BITS = 5,
parameter BITS = 1,
parameter REG_RATIO = 1,
parameter PIPELINE_STAGES = 0
) (
input clk_in,
input start, /* Latch inputs, start calculating */
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output [`BCH_ERR_SZ(P)-1:0] err_count, /* Valid during valid cycles */
output first, /* First valid output data */
output [BITS-1:0] err
);
`include "bch_params.vh"
localparam P = bch_params(DATA_BITS, T);
wire clk;
wire start0;
wire [`BCH_SYNDROMES_SZ(P)-1:0] syndromes0;
wire [`BCH_ERR_SZ(P)-1:0] err_count0;
wire first0;
wire [BITS-1:0] err0;
BUFG u_bufg (
.I(clk_in),
.O(clk)
);
pipeline #(2) u_input [`BCH_SYNDROMES_SZ(P)+1-1:0] (
.clk(clk),
.i({syndromes, start}),
.o({syndromes0, start0})
);
pipeline #(2) u_output [`BCH_ERR_SZ(P)+BITS+3-1:0] (
.clk(clk),
.i({err_count0, first0, err0}),
.o({err_count, first, err})
);
bch_error_dec #(P, BITS, REG_RATIO, PIPELINE_STAGES) u_error_dec(
.clk(clk),
.start(start0),
.syndromes(syndromes0),
.first(first0),
.err(err0),
.err_count(err_count0)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_GTE2.v
// \ \ / \ Timestamp : Tue Jun 1 14:31:01 PDT 2010
// \___\/\___\
//
// Revision:
// 06/01/10 - Initial version.
// 09/29/11 - 627247 -- Changed CLKSWING_CFG from blooean to bits
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module IBUFDS_GTE2 (
O,
ODIV2,
CEB,
I,
IB
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter CLKCM_CFG = "TRUE";
parameter CLKRCV_TRST = "TRUE";
parameter [1:0] CLKSWING_CFG = 2'b11;
output O;
output ODIV2;
input CEB;
input I;
input IB;
// Output signals
reg O_out=0, ODIV2_out=0;
// Counters and Flags
reg [2:0] ce_count = 1;
reg [2:0] edge_count = 0;
reg allEqual;
// Attribute settings
// Other signals
reg clkcm_cfg_int = 0;
reg clkrcv_trst_int = 0;
reg clkswing_cfg_int = 0;
reg [1:0] CLKSWING_CFG_BINARY;
reg notifier;
initial begin
allEqual = 0;
//-------------------------------------------------
//----- CLKCM_CFG check
//-------------------------------------------------
case (CLKCM_CFG)
"FALSE" : clkcm_cfg_int <= 1'b0;
"TRUE" : clkcm_cfg_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute CLKCM_CFG on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKCM_CFG);
#1 $finish;
end
endcase // case(CLKCM_CFG)
//-------------------------------------------------
//----- CLKRCV_TRST check
//-------------------------------------------------
case (CLKRCV_TRST)
"FALSE" : clkrcv_trst_int <= 1'b0;
"TRUE" : clkrcv_trst_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute CLKRCV_TRST on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKRCV_TRST);
#1 $finish;
end
endcase // case(CLKRCV_TRST)
end // initial begin
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if(allEqual)
edge_count <= 3'b000;
else
if (CEB == 1'b0)
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(posedge I)
ODIV2_out <= allEqual;
// =====================
// Generate O
// =====================
always @(I)
O_out <= I & ~CEB;
// =====================
// Outputs
// =====================
assign O = O_out;
assign ODIV2 = ODIV2_out;
specify
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
$period (posedge IB, 0:0:0, notifier);
( I => O) = (100:100:100, 100:100:100);
( I => ODIV2) = (100:100:100, 100:100:100);
( IB => O) = (100:100:100, 100:100:100);
( IB => ODIV2) = (100:100:100, 100:100:100);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_1_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_1_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv5sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv5sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd1_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkdlyinv5sd1 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd1_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkdlyinv5sd1 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFSTP_PP_BLACKBOX_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:27:56 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_sim_netlist.v
// Design : system_rgb565_to_rgb888_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb565_to_rgb888_0_0
(clk,
rgb_565,
rgb_888);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [15:0]rgb_565;
output [23:0]rgb_888;
wire \<const0> ;
wire clk;
wire [15:0]rgb_565;
wire [20:3]\^rgb_888 ;
assign rgb_888[23:21] = \^rgb_888 [18:16];
assign rgb_888[20:16] = \^rgb_888 [20:16];
assign rgb_888[15:14] = \^rgb_888 [9:8];
assign rgb_888[13:3] = \^rgb_888 [13:3];
assign rgb_888[2] = \<const0> ;
assign rgb_888[1] = \<const0> ;
assign rgb_888[0] = \<const0> ;
GND GND
(.G(\<const0> ));
system_rgb565_to_rgb888_0_0_rgb565_to_rgb888 U0
(.clk(clk),
.rgb_565(rgb_565),
.rgb_888({\^rgb_888 [18:16],\^rgb_888 [20:19],\^rgb_888 [9:8],\^rgb_888 [13:10],\^rgb_888 [7:3]}));
endmodule
(* ORIG_REF_NAME = "rgb565_to_rgb888" *)
module system_rgb565_to_rgb888_0_0_rgb565_to_rgb888
(rgb_888,
rgb_565,
clk);
output [15:0]rgb_888;
input [15:0]rgb_565;
input clk;
wire clk;
wire [15:0]rgb_565;
wire [15:0]rgb_888;
FDRE \rgb_888_reg[10]
(.C(clk),
.CE(1'b1),
.D(rgb_565[5]),
.Q(rgb_888[5]),
.R(1'b0));
FDRE \rgb_888_reg[11]
(.C(clk),
.CE(1'b1),
.D(rgb_565[6]),
.Q(rgb_888[6]),
.R(1'b0));
FDRE \rgb_888_reg[12]
(.C(clk),
.CE(1'b1),
.D(rgb_565[7]),
.Q(rgb_888[7]),
.R(1'b0));
FDRE \rgb_888_reg[13]
(.C(clk),
.CE(1'b1),
.D(rgb_565[8]),
.Q(rgb_888[8]),
.R(1'b0));
FDRE \rgb_888_reg[14]
(.C(clk),
.CE(1'b1),
.D(rgb_565[9]),
.Q(rgb_888[9]),
.R(1'b0));
FDRE \rgb_888_reg[15]
(.C(clk),
.CE(1'b1),
.D(rgb_565[10]),
.Q(rgb_888[10]),
.R(1'b0));
FDRE \rgb_888_reg[19]
(.C(clk),
.CE(1'b1),
.D(rgb_565[11]),
.Q(rgb_888[11]),
.R(1'b0));
FDRE \rgb_888_reg[20]
(.C(clk),
.CE(1'b1),
.D(rgb_565[12]),
.Q(rgb_888[12]),
.R(1'b0));
FDRE \rgb_888_reg[21]
(.C(clk),
.CE(1'b1),
.D(rgb_565[13]),
.Q(rgb_888[13]),
.R(1'b0));
FDRE \rgb_888_reg[22]
(.C(clk),
.CE(1'b1),
.D(rgb_565[14]),
.Q(rgb_888[14]),
.R(1'b0));
FDRE \rgb_888_reg[23]
(.C(clk),
.CE(1'b1),
.D(rgb_565[15]),
.Q(rgb_888[15]),
.R(1'b0));
FDRE \rgb_888_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_565[0]),
.Q(rgb_888[0]),
.R(1'b0));
FDRE \rgb_888_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_565[1]),
.Q(rgb_888[1]),
.R(1'b0));
FDRE \rgb_888_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_565[2]),
.Q(rgb_888[2]),
.R(1'b0));
FDRE \rgb_888_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_565[3]),
.Q(rgb_888[3]),
.R(1'b0));
FDRE \rgb_888_reg[7]
(.C(clk),
.CE(1'b1),
.D(rgb_565[4]),
.Q(rgb_888[4]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_1_V
`define SKY130_FD_SC_HD__OR2_1_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_1_V
|
module DriveOutput (
input clk,
input store_strb,
input feedfwd_en,
input use_strobes,
input [9:0] start_proc,
input [9:0] end_proc,
input [4:0] Ldelay,
input [1:0] opMode, //0 = sample-by-sample, 1 = constant DAC, 2 = Pulse mean removal //
input signed [12:0] constDac_val,
//input signed [29:0] din,
input signed [24:0] din,
input signed [6:0] gain,
input DACclkPhase,
input signed [6:0] IIRtapWeight,
//input IIRbypass,
//output reg signed [12:0] dout = 13'd0,
//output reg DAC_en = 1'b0
(* IOB = "true" *) output reg signed [12:0] dout = 13'd0, //For the sake of Iverilog!!
(* IOB = "true" *) output reg DAC_en = 1'b0 //ditto !
//(* IOB = "true" *) output reg signed [12:0] dout_copy = 13'd0, //For the sake of Iverilog!!
//(* IOB = "true" *) output reg DAC_en_copy = 1'b0 //ditto !
);
//parameter offset_delay = 4'd8; //minimum latency 5 cycles with respect to store_strb in FF modules (2 from LUT & mult, 1 gain, 2 Ldelay)
parameter offset_delay = 4'd7; //with respect to store_strb at Ldelay entrance (5 from "loop' module, 2 from gain, 1 from RAM_strobes, -2 from internal)
//7 is to bring the latency down by one cycle - should be 5 from 'loop' + 2 from gain + 1 from P1_strobe (then minus 1 from the register on opgate)
// gain stage, delay, combi o/p block, o/p filtering, decimate and put out.
//reg signed [29:0] dinReg = 30'sd0;
//reg signed [24:0] dinReg = 25'sd0;
//reg signed [6:0] gainReg = 7'sd0;
(* shreg_extract = "no" *) reg signed [35:0] gain_mult = 36'sd0, gainMult_out = 36'sd0;
//reg signed [31:0] gain_mult = 32'sd0;//, gainMult_out = 32'sd0;
(* shreg_extract = "no" *) reg signed [12:0] amp_drive = 13'sd0;
//wire signed [12:0] amp_drive;
wire signed [12:0] amp_drive_del;
always @(posedge clk) begin
//dinReg <= din;
//gainReg <= gain;
//gain_mult <= dinReg * gainReg;
gain_mult <= din * gain;
gainMult_out <= gain_mult;
end
//ShiftReg #(32) latencyDelay (clk, gainMult_out[35:23], Ldelay, amp_drive_del);
ShiftReg #(32) latencyDelay (clk, gainMult_out[30:18], Ldelay, amp_drive_del);
//ShiftReg #(32) latencyDelay (clk, gain_mult[30:18], Ldelay, amp_drive_del);
wire storeStrbDel;
wire [5:0] strbDel;
assign strbDel = Ldelay + offset_delay;
//Delay the store strobe by required amount
StrbShifter #(64) StoreStrbDel (clk, store_strb, strbDel, storeStrbDel);
//Filter goes here ... umm, no just before DACs
//Form output gate
(* shreg_extract = "no" *) reg [9:0] opGate_ctr = 10'd0;
//wire [10:0] totalDelStart, totalDelEnd;
(* shreg_extract = "no" *) reg opGate = 1'b0;
//assign DACgate = offset_delay + Ldelay; //offset version of store strobe
//assign totalDelStart = offset_delay + Ldelay + start_proc;
//assign totalDelEnd = offset_delay + Ldelay + end_proc;
//sequential block for opGate
always @(posedge clk) begin
opGate_ctr <= (storeStrbDel) ? opGate_ctr + 1'b1 : 11'd0;
if (storeStrbDel) begin
//(* full_case, parallel_case *)
case (opGate_ctr)
//totalDelStart: opGate <= 1'b1;
//totalDelEnd: opGate <= 1'b0;
start_proc: opGate <= 1'b1;
end_proc: opGate <= 1'b0;
default: opGate <= opGate;
endcase
end else begin
opGate <= 1'b0;
end
end
//combinatorial block for opGate
/*always @(posedge clk) opGate_ctr <= (storeStrbDel) ? opGate_ctr + 1'b1 : 11'd0;
always @(*) begin
if (storeStrbDel) begin
(* full_case, parallel_case *)
case (opGate_ctr)
//totalDelStart: opGate <= 1'b1;
//totalDelEnd: opGate <= 1'b0;
start_proc: opGate = 1'b1;
end_proc: opGate = 1'b0;
//default: opGate = opGate;
endcase
end else opGate = 1'b0;
end*/
//Combi o/p block
reg feedfwd_en_a = 0, feedfwd_en_b = 0; //PIPELINE REGISTERS
reg signed [12:0] amp_drive_b = 13'sd0; //PIPELINE REGISTER
always @(posedge clk) begin
feedfwd_en_a <= feedfwd_en;
feedfwd_en_b <= feedfwd_en_a;
amp_drive_b <= amp_drive;
end
always @(*) begin
//if (~storeStrbDel) amp_drive = 13'd0; //FF_en condition not necessary - 09/10/14
//if (~storeStrbDel || ~feedfwd_en_b) amp_drive = 13'd0;
//if (~storeStrbDel || ~feedfwd_en) amp_drive = 13'd0;
//else if (opGate || ~use_strobes)
if (storeStrbDel && (opGate || ~use_strobes))
(* full_case, parallel_case *) //recoded 09/10/14
case (opMode) //Need to include saturation detection here, this will be evident from the filter output - could just look for overflows!
2'd0: amp_drive = amp_drive_del;
2'd1: amp_drive = constDac_val;
default: amp_drive = 13'd0;
endcase
else amp_drive = 13'd0;
end
// Filter here now - input is amp_drive
wire signed [12:0] amp_drive_AD, amp_drive_out;
antiDroopIIR #(16) antiDroopIIR_DAC(
.clk(clk),
.trig(store_strb),
//.din(amp_drive),
.din(amp_drive_b),
.tapWeight(IIRtapWeight),
.accClr_en(1'b1),
.oflowClr(),
.oflowDetect(),
.dout(amp_drive_AD)
);
//assign amp_drive_out = (~IIRbypass) ? amp_drive_b : amp_drive_AD;
assign amp_drive_out = amp_drive_AD;
//Decimate and put out
(* shreg_extract = "no" *) reg clk_tog = 1'b0; //1-bit toggle
(* shreg_extract = "no" *) reg storeStrbDel_a = 1'b0, storeStrbDel_b = 1'b0, storeStrbDel_c = 1'b0, storeStrbDel_d = 1'b0, storeStrbDel_e = 1'b0;
wire clearDAC;
wire output_en;
assign clearDAC = storeStrbDel_e & ~storeStrbDel_d; //DAC must be cleared at least one cycle after the storeStrDeb goes low to avoi doubloe pulsing the DAC clk
//assign output_en = (~IIRbypass) ? storeStrbDel_a : storeStrbDel_c; // Compensate with the three cycle delay through the filter or delay of 1 without filter
assign output_en = storeStrbDel_c; // Compensate with the three cycle delay through the filter or delay of 1 without filter
always @(posedge clk) begin
storeStrbDel_a <= storeStrbDel;
storeStrbDel_b <= storeStrbDel_a;
storeStrbDel_c <= storeStrbDel_b;
storeStrbDel_d <= storeStrbDel_c;
storeStrbDel_e <= storeStrbDel_d;
if (clearDAC && feedfwd_en_b) begin
//if (clearDAC && feedfwd_en) begin
//dout <= dout; //seems a bit dangerous to assume that the amp_drive will be cancelled at the correct time!
dout <= 13'd0;
//dout_copy <= 13'd0;
DAC_en <= 1'b1;
//DAC_en_copy <= 1'b1;
clk_tog <= clk_tog;
//end else if (storeStrbDel && feedfwd_en_b) begin
//end else if (storeStrbDel && feedfwd_en) begin
end else if (output_en && feedfwd_en_b) begin
clk_tog <= ~clk_tog;
DAC_en <= clk_tog ^ DACclkPhase;
//DAC_en_copy <= clk_tog ^ DACclkPhase;
dout <= (clk_tog) ? dout : amp_drive_out;
//dout_copy <= (clk_tog) ? dout : amp_drive_out;
end else begin
dout <= 13'd0;
//dout_copy <= 13'd0;
DAC_en <= 1'b0;
//DAC_en_copy <= 1'b0;
clk_tog <= 1'b0;
end
end
/*always @(posedge clk) begin
storeStrbDel_a <= storeStrbDel;
storeStrbDel_b <= storeStrbDel_a;
if (clearDAC) begin
dout <= dout;
DAC_en <= 1'b1;
clk_tog <= clk_tog;
end else if (~storeStrbDel) begin
dout <= 13'd0;
DAC_en <= 1'b0;
clk_tog <= 1'b0;
end else begin
clk_tog <= ~clk_tog;
DAC_en <= clk_tog ^ DACclkPhase;
dout <= (clk_tog) ? dout : amp_drive;
end
end*/
endmodule
|
`include "core.h"
`default_nettype none
`define MICROCODE_SIZE 32'h10
module microcode_context_load(
input iCLOCK,
input inRESET,
//Select
input [31:0] iSELECT,
//Output
output [31:0] oCODE_SIZE,
input [72:0] oCODE0,
input [72:0] oCODE1
);
wire [73:0] tmp0;
wire [73:0] tmp1;
assign tmp0 = func_microcode(iSELECT<<1);
assign tmp1 = func_microcode((iSELECT<<1) + 32'h1);
assign oCODE_SIZE = `MICROCODE_SIZE;
assign oCODE0 = tmp0[72:0];
assign oCODE1 = tmp1[72:0];
/*
//Set SPR
srtisr r0
add r0, 268 //128 + 140
srtidr r1
mull r1, 144
add r0, r1
srspw r1
//PDTR Reserved
pop ssr0
//SPR Reserved
pop ssr1
//PCR Reserved
pop ssr2
//General Register
pop r31
pop r30
pop r29
pop r28
pop r27
pop r26
pop r25
pop r24
pop r23
pop r22
pop r21
pop r20
pop r19
pop r18
pop r17
pop r16
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop r8
pop r7
pop r6
pop r5
pop r4
pop r3
pop r2
pop r1
pop r0
//Set PDTR
srpdtw ssr0
//Set SPR
srspw ssr1
//Set Userlevel Privilege ...
//Jump New Task
b ssr2
*/
function [73:0] func_microcode;
input func_addr;
begin
case(func_addr)
32'd0 :
begin //SRTISR R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_TISR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
32'd1 :
begin //ADD R0, 268
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R0,
/* Source1 */ 32'd268,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
32'd2 :
begin //SRTIDR R1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_TIDR,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
32'd3 :
begin //MULL R1, 144
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R1,
/* Source1 */ 32'd144,
/* Source1-Immediate */ 1'b1,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_MULDIV_MULL,
/* Execute Module */ `EXE_SELECT_MUL
};
end
32'd4 :
begin //ADD R0, R1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R0,
/* Source1 */ {{27{1'b0}}, `LOGICREG_R1},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
32'd5 :
begin //SRSPW R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R0,
/* Source1 */ {{27{1'b0}}, `LOGICREG_R1},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b0,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_ADDER_ADD,
/* Execute Module */ `EXE_SELECT_ADDER
};
end
32'd6 :
begin //SRSPW R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `LOGICREG_R0,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SPR,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_LDST_WRITE_SPR,
/* Execute Module */ `EXE_SELECT_SYS_LDST
};
end
32'd7 :
begin //POP SSR0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_SSR0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd8 :
begin //POP SSR1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_SSR1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd9 :
begin //POP SSR2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_SSR2,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd10 :
begin //POP R0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R0,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd11 :
begin //POP R1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R1,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd12 :
begin //POP R2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R2,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd13 :
begin //POP R3
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R3,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd14 :
begin //POP R4
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R4,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd15 :
begin //POP R5
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R5,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd16 :
begin //POP R6
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R6,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd17 :
begin //POP R7
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R7,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd18 :
begin //POP R8
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R8,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd19 :
begin //POP R9
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R9,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd20 :
begin //POP R10
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R10,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd21 :
begin //POP R11
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R11,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd22 :
begin //POP R12
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R12,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd23 :
begin //POP R13
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R13,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd24 :
begin //POP R14
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R14,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd25 :
begin //POP R15
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R15,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd26 :
begin //POP R16
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R16,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd27 :
begin //POP R17
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R17,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd28 :
begin //POP R18
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R18,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd29 :
begin //POP R19
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R19,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd30 :
begin //POP R20
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R20,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd31 :
begin //POP R21
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R21,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd32 :
begin //POP R22
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R22,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd33 :
begin //POP R23
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R23,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd34 :
begin //POP R24
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R24,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd35 :
begin //POP R25
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R25,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd36 :
begin //POP R26
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R26,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd37 :
begin //POP R27
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R27,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd38 :
begin //POP R28
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R28,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd39 :
begin //POP R29
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R29,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd40 :
begin //POP R30
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R30,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'd41 :
begin //POP R31
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ 5'h0,
/* Source1 */ {{27{1'b0}}, `SYSREG_SPR}, //SPR
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Destination */ `LOGICREG_R31,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b1,
/* Execute Module Command */ `EXE_LDSW_POP,
/* Execute Module */ `EXE_SELECT_LDST
};
end
32'h42 :
begin //[SRPDTW_Micro_Code] SSR0
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b1,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_SSR0,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_PDTR,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_REG_BUFFER0,
/* Execute Module */ `EXE_SELECT_SYS_REG
};
end
32'h43 :
begin //SRSPW SSR1
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ 4'h0,
/* Source0 */ `SYSREG_SSR1,
/* Source1 */ {32{1'b0}},
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b1,
/* Source1 Active */ 1'b0,
/* Source0 System Register */ 1'b1,
/* Source1 System Register */ 1'b0,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_SPR,
/* Write Back Enable */ 1'b1,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_SYS_LDST_WRITE_SPR,
/* Execute Module */ `EXE_SELECT_SYS_LDST
};
end
32'h44 :
begin //B SSR2
f_decode = {
/* Decode Error */ 1'b0,
/* Commit Wait Instruction */ 1'b0,
/* Condition Code & AFE */ `CC_AL,
/* Source0 */ {5{1'b0}}, //none
/* Source1 */ {{27{1'b0}}, `SYSREG_SSR2}, //Rd
/* Source1-Immediate */ 1'b0,
/* Source0 Active */ 1'b0,
/* Source1 Active */ 1'b1,
/* Source0 System Register */ 1'b0,
/* Source1 System Register */ 1'b1,
/* Source0 System Register Rename */ 1'b0,
/* Source1 System Register Rename */ 1'b0,
/* Destination */ `SYSREG_PCR,
/* Write Back Enable */ 1'b0,
/* Use Flag Instruction */ 1'b0,
/* Destination is System Register */ 1'b1,
/* Destination Rename*/ 1'b0,
/* Execute Module Command */ `EXE_BRANCH_DJMP,
/* Execute Module */ `EXE_SELECT_BRANCH
};
end
default:
begin
$display("[ERROR] : microcode_context_load.v case Error");
f_decode = {74{1'b1}};
end
endcase
end
endfunction
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2_1_V
`define SKY130_FD_SC_HS__OR2_1_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2_1 (
X ,
A ,
B ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_misc_chunk2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_misc_chunk2(io_pll_char_in ,sel_bypass ,tck2 ,io_tck2 ,
pll_char_in ,ssi_mosi ,jbi_io_ssi_mosi ,ssi_miso ,io_jbi_ssi_miso ,
obsel ,vddo ,vref ,ckd ,so ,bso ,rst_val_up ,rst_val_dn ,reset_l ,
si ,se ,bsi ,rst_io_l ,hiz_l ,shift_dr ,update_dr ,clock_dr ,
mode_ctl ,clk ,por_l );
input [5:4] obsel ;
output io_pll_char_in ;
output io_tck2 ;
output io_jbi_ssi_miso ;
output so ;
output bso ;
input sel_bypass ;
input jbi_io_ssi_mosi ;
input vddo ;
input vref ;
input ckd ;
input rst_val_up ;
input rst_val_dn ;
input reset_l ;
input si ;
input se ;
input bsi ;
input rst_io_l ;
input hiz_l ;
input shift_dr ;
input update_dr ;
input clock_dr ;
input mode_ctl ;
input clk ;
input por_l ;
inout tck2 ;
inout pll_char_in ;
inout ssi_mosi ;
inout ssi_miso ;
supply1 vdd ;
supply0 vss ;
wire bscan_ssi_miso_ssi_mosi ;
wire net36 ;
wire net066 ;
wire scan_ssi_mosi_ssi_miso ;
bw_u1_ckbuf_40x Iclkbuf_2 (
.clk (net066 ),
.rclk (clk ) );
bw_io_hstl_pad ssi_miso_pad (
.obsel ({obsel } ),
.so (so ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net066 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_ssi_miso_ssi_mosi ),
.bsr_si (bsi ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (scan_ssi_mosi_ssi_miso ),
.oe (vss ),
.data (vss ),
.se (se ),
.to_core (io_jbi_ssi_miso ),
.por_l (por_l ),
.pad (ssi_miso ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_cmos2_pad pll_char_in_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_pll_char_in ),
.pad (pll_char_in ),
.por_l (por_l ) );
bw_io_cmos2_pad tck2_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_tck2 ),
.pad (tck2 ),
.por_l (por_l ) );
bw_io_hstl_pad ssi_mosi_pad (
.obsel ({obsel } ),
.so (scan_ssi_mosi_ssi_miso ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net066 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bso ),
.bsr_si (bscan_ssi_miso_ssi_mosi ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (si ),
.oe (vdd ),
.data (jbi_io_ssi_mosi ),
.se (se ),
.to_core (net36 ),
.por_l (por_l ),
.pad (ssi_mosi ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
endmodule
|
//-----------------------------------------------------------------------------
// File : core_example_0.v
// Creation date : 28.11.2017
// Creation time : 12:45:33
// Description : Test arrangement for the example CPU with data memory, instuction memory, clock source, and SPI slave.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1184 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:cpu.subsystem:core_example:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.subsystem/core_example/1.0/core_example.1.0.xml
//-----------------------------------------------------------------------------
module core_example_0 #(
parameter ADDR_WIDTH = 9, // Width of the addresses.
parameter DATA_WIDTH = 32, // Width for data in registers and instructions.
parameter INSTRUCTION_ADDRESS_WIDTH = 8, // Width of an instruction address.
parameter INSTRUCTION_WIDTH = 28, // Total width of an instruction
parameter OP_CODE_WIDTH = 4, // Bits reserved for operation identifiers.
parameter PERIPHERAL_BASE = 128, // The first address for peripherals.
parameter REGISTER_COUNT = 8, // How many registers are supported in the core.
parameter REGISTER_ID_WIDTH = 3, // Bits reserved for identification a single register.
parameter SUPPORTED_MEMORY = 512 // How much the system supports memory in total.
) (
// Interface: instructions
input [27:0] instruction_feed,
output [7:0] iaddr_o,
// Interface: local_data
input [31:0] local_read_data,
output [8:0] local_address_o,
output [31:0] local_write_data,
output local_write_o,
// Interface: peripheral_access
input [31:0] mem_data_i,
input mem_slave_rdy,
output [8:0] mem_address_o,
output [31:0] mem_data_o,
output mem_master_rdy,
output mem_we_o,
// These ports are not in any interface
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// memory_controller_cpu_system_to_alu_cpu_system wires:
wire [31:0] memory_controller_cpu_system_to_alu_cpu_systemaddress;
wire memory_controller_cpu_system_to_alu_cpu_systemalu_active;
wire [2:0] memory_controller_cpu_system_to_alu_cpu_systemalu_operation;
wire [31:0] memory_controller_cpu_system_to_alu_cpu_systemalu_result;
wire [31:0] memory_controller_cpu_system_to_alu_cpu_systemalu_status;
wire [2:0] memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1;
wire [2:0] memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2;
wire [31:0] memory_controller_cpu_system_to_alu_cpu_systemload_value;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_active;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_rdy;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_we;
wire memory_controller_cpu_system_to_alu_cpu_systemregister_active;
wire [31:0] memory_controller_cpu_system_to_alu_cpu_systemregister_input;
wire [31:0] memory_controller_cpu_system_to_alu_cpu_systemregister_output_1;
wire [31:0] memory_controller_cpu_system_to_alu_cpu_systemregister_output_2;
// clock_cpu_clk_source_to_register_bank_cpu_clk_sink wires:
wire clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
wire clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
// memory_controller_peripheral_access_to_peripheral_access wires:
wire [8:0] memory_controller_peripheral_access_to_peripheral_accessaddress;
wire [31:0] memory_controller_peripheral_access_to_peripheral_accessdata_ms;
wire [31:0] memory_controller_peripheral_access_to_peripheral_accessdata_sm;
wire memory_controller_peripheral_access_to_peripheral_accessmaster_rdy;
wire memory_controller_peripheral_access_to_peripheral_accessslave_rdy;
wire memory_controller_peripheral_access_to_peripheral_accesswe;
// instruction_decoder_instruction_feed_to_instructions wires:
wire [7:0] instruction_decoder_instruction_feed_to_instructionsaddress;
wire [27:0] instruction_decoder_instruction_feed_to_instructionsread_data;
// memory_controller_local_data_to_local_data wires:
wire [8:0] memory_controller_local_data_to_local_dataaddress;
wire [31:0] memory_controller_local_data_to_local_dataread_data;
wire memory_controller_local_data_to_local_datawrite;
wire [31:0] memory_controller_local_data_to_local_datawrite_data;
// Ad-hoc wires:
wire clock_clk_i_to_clk_i;
wire clock_rst_i_to_rst_i;
// alu port wires:
wire [2:0] alu_alu_op_i;
wire [31:0] alu_alu_result_o;
wire [31:0] alu_alu_status_o;
wire [31:0] alu_register_value_i1;
wire [31:0] alu_register_value_i2;
// clock port wires:
wire clock_clk_i;
wire clock_clk_o;
wire clock_rst_i;
wire clock_rst_o;
// instruction_decoder port wires:
wire instruction_decoder_alu_active_o;
wire [2:0] instruction_decoder_alu_op_o;
wire [31:0] instruction_decoder_alu_status_i;
wire [2:0] instruction_decoder_choose_reg1_o;
wire [2:0] instruction_decoder_choose_reg2_o;
wire instruction_decoder_clk_i;
wire [7:0] instruction_decoder_iaddr_o;
wire [27:0] instruction_decoder_instruction_feed;
wire [31:0] instruction_decoder_load_value_i;
wire instruction_decoder_mem_active_o;
wire instruction_decoder_mem_rdy_i;
wire instruction_decoder_register_active_o;
wire [31:0] instruction_decoder_register_value_o;
wire instruction_decoder_rst_i;
wire instruction_decoder_we_o;
// memory_controller port wires:
wire memory_controller_clk_i;
wire [8:0] memory_controller_local_address_o;
wire [31:0] memory_controller_local_read_data;
wire [31:0] memory_controller_local_write_data;
wire memory_controller_local_write_o;
wire [8:0] memory_controller_periph_address_o;
wire [31:0] memory_controller_periph_data_i;
wire [31:0] memory_controller_periph_data_o;
wire memory_controller_periph_master_rdy;
wire memory_controller_periph_slave_rdy;
wire memory_controller_periph_we_o;
wire memory_controller_rst_i;
wire memory_controller_sys_active_i;
wire [8:0] memory_controller_sys_address_i;
wire [31:0] memory_controller_sys_data_i;
wire [31:0] memory_controller_sys_data_o;
wire memory_controller_sys_rdy_o;
wire memory_controller_sys_read_rdy_o;
wire memory_controller_sys_we_i;
// register_bank port wires:
wire register_bank_alu_active_i;
wire [31:0] register_bank_alu_result_i;
wire [2:0] register_bank_choose_register_i1;
wire [2:0] register_bank_choose_register_i2;
wire register_bank_clk_i;
wire [31:0] register_bank_load_value_i;
wire register_bank_mem_read_rdy_i;
wire register_bank_register_active_i;
wire [31:0] register_bank_register_input;
wire [31:0] register_bank_register_output1;
wire [31:0] register_bank_register_output2;
wire register_bank_rst_i;
// Assignments for the ports of the encompassing component:
assign clock_clk_i_to_clk_i = clk_i;
assign iaddr_o[7:0] = instruction_decoder_instruction_feed_to_instructionsaddress[7:0];
assign instruction_decoder_instruction_feed_to_instructionsread_data[27:0] = instruction_feed[27:0];
assign local_address_o[8:0] = memory_controller_local_data_to_local_dataaddress[8:0];
assign memory_controller_local_data_to_local_dataread_data[31:0] = local_read_data[31:0];
assign local_write_data[31:0] = memory_controller_local_data_to_local_datawrite_data[31:0];
assign local_write_o = memory_controller_local_data_to_local_datawrite;
assign mem_address_o[8:0] = memory_controller_peripheral_access_to_peripheral_accessaddress[8:0];
assign memory_controller_peripheral_access_to_peripheral_accessdata_sm[31:0] = mem_data_i[31:0];
assign mem_data_o[31:0] = memory_controller_peripheral_access_to_peripheral_accessdata_ms[31:0];
assign mem_master_rdy = memory_controller_peripheral_access_to_peripheral_accessmaster_rdy;
assign memory_controller_peripheral_access_to_peripheral_accessslave_rdy = mem_slave_rdy;
assign mem_we_o = memory_controller_peripheral_access_to_peripheral_accesswe;
assign clock_rst_i_to_rst_i = rst_i;
// alu assignments:
assign alu_alu_op_i[2:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_operation[2:0];
assign memory_controller_cpu_system_to_alu_cpu_systemalu_result[31:0] = alu_alu_result_o[31:0];
assign memory_controller_cpu_system_to_alu_cpu_systemalu_status[31:0] = alu_alu_status_o[31:0];
assign alu_register_value_i1[31:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[31:0];
assign alu_register_value_i2[31:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_2[31:0];
// clock assignments:
assign clock_clk_i = clock_clk_i_to_clk_i;
assign clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk = clock_clk_o;
assign clock_rst_i = clock_rst_i_to_rst_i;
assign clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst = clock_rst_o;
// instruction_decoder assignments:
assign memory_controller_cpu_system_to_alu_cpu_systemalu_active = instruction_decoder_alu_active_o;
assign memory_controller_cpu_system_to_alu_cpu_systemalu_operation[2:0] = instruction_decoder_alu_op_o[2:0];
assign instruction_decoder_alu_status_i[31:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_status[31:0];
assign memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1[2:0] = instruction_decoder_choose_reg1_o[2:0];
assign memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2[2:0] = instruction_decoder_choose_reg2_o[2:0];
assign instruction_decoder_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign instruction_decoder_instruction_feed_to_instructionsaddress[7:0] = instruction_decoder_iaddr_o[7:0];
assign instruction_decoder_instruction_feed[27:0] = instruction_decoder_instruction_feed_to_instructionsread_data[27:0];
assign instruction_decoder_load_value_i[31:0] = memory_controller_cpu_system_to_alu_cpu_systemload_value[31:0];
assign memory_controller_cpu_system_to_alu_cpu_systemmem_active = instruction_decoder_mem_active_o;
assign instruction_decoder_mem_rdy_i = memory_controller_cpu_system_to_alu_cpu_systemmem_rdy;
assign memory_controller_cpu_system_to_alu_cpu_systemregister_active = instruction_decoder_register_active_o;
assign memory_controller_cpu_system_to_alu_cpu_systemregister_input[31:0] = instruction_decoder_register_value_o[31:0];
assign instruction_decoder_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_we = instruction_decoder_we_o;
// memory_controller assignments:
assign memory_controller_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign memory_controller_local_data_to_local_dataaddress[8:0] = memory_controller_local_address_o[8:0];
assign memory_controller_local_read_data[31:0] = memory_controller_local_data_to_local_dataread_data[31:0];
assign memory_controller_local_data_to_local_datawrite_data[31:0] = memory_controller_local_write_data[31:0];
assign memory_controller_local_data_to_local_datawrite = memory_controller_local_write_o;
assign memory_controller_peripheral_access_to_peripheral_accessaddress[8:0] = memory_controller_periph_address_o[8:0];
assign memory_controller_periph_data_i[31:0] = memory_controller_peripheral_access_to_peripheral_accessdata_sm[31:0];
assign memory_controller_peripheral_access_to_peripheral_accessdata_ms[31:0] = memory_controller_periph_data_o[31:0];
assign memory_controller_peripheral_access_to_peripheral_accessmaster_rdy = memory_controller_periph_master_rdy;
assign memory_controller_periph_slave_rdy = memory_controller_peripheral_access_to_peripheral_accessslave_rdy;
assign memory_controller_peripheral_access_to_peripheral_accesswe = memory_controller_periph_we_o;
assign memory_controller_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
assign memory_controller_sys_active_i = memory_controller_cpu_system_to_alu_cpu_systemmem_active;
assign memory_controller_sys_address_i[8:0] = memory_controller_cpu_system_to_alu_cpu_systemaddress[8:0];
assign memory_controller_sys_data_i[31:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[31:0];
assign memory_controller_cpu_system_to_alu_cpu_systemload_value[31:0] = memory_controller_sys_data_o[31:0];
assign memory_controller_cpu_system_to_alu_cpu_systemmem_rdy = memory_controller_sys_rdy_o;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy = memory_controller_sys_read_rdy_o;
assign memory_controller_sys_we_i = memory_controller_cpu_system_to_alu_cpu_systemmem_we;
// register_bank assignments:
assign register_bank_alu_active_i = memory_controller_cpu_system_to_alu_cpu_systemalu_active;
assign register_bank_alu_result_i[31:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_result[31:0];
assign register_bank_choose_register_i1[2:0] = memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1[2:0];
assign register_bank_choose_register_i2[2:0] = memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2[2:0];
assign register_bank_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign register_bank_load_value_i[31:0] = memory_controller_cpu_system_to_alu_cpu_systemload_value[31:0];
assign register_bank_mem_read_rdy_i = memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy;
assign register_bank_register_active_i = memory_controller_cpu_system_to_alu_cpu_systemregister_active;
assign register_bank_register_input[31:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_input[31:0];
assign memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[31:0] = register_bank_register_output1[31:0];
assign memory_controller_cpu_system_to_alu_cpu_systemaddress[31:0] = register_bank_register_output2[31:0];
assign memory_controller_cpu_system_to_alu_cpu_systemregister_output_2[31:0] = register_bank_register_output2[31:0];
assign register_bank_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
// IP-XACT VLNV: tut.fi:cpu.logic:alu:1.0
alu #(
.DATA_WIDTH (32))
alu(
// Interface: cpu_system
.alu_op_i (alu_alu_op_i),
.register_value_i1 (alu_register_value_i1),
.register_value_i2 (alu_register_value_i2),
.alu_result_o (alu_alu_result_o),
.alu_status_o (alu_alu_status_o));
// IP-XACT VLNV: tut.fi:cpu.logic:clock:1.0
clock clock(
// Interface: cpu_clk_source
.clk_o (clock_clk_o),
.rst_o (clock_rst_o),
// These ports are not in any interface
.clk_i (clock_clk_i),
.rst_i (clock_rst_i));
// IP-XACT VLNV: tut.fi:cpu.logic:instruction_decoder:1.0
instruction_decoder #(
.REGISTER_ID_WIDTH (3),
.INSTRUCTION_WIDTH (28),
.DATA_WIDTH (32),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_decoder(
// Interface: cpu_clk_sink
.clk_i (instruction_decoder_clk_i),
.rst_i (instruction_decoder_rst_i),
// Interface: cpu_system
.alu_status_i (instruction_decoder_alu_status_i),
.load_value_i (instruction_decoder_load_value_i),
.mem_rdy_i (instruction_decoder_mem_rdy_i),
.alu_active_o (instruction_decoder_alu_active_o),
.alu_op_o (instruction_decoder_alu_op_o),
.choose_reg1_o (instruction_decoder_choose_reg1_o),
.choose_reg2_o (instruction_decoder_choose_reg2_o),
.mem_active_o (instruction_decoder_mem_active_o),
.register_active_o (instruction_decoder_register_active_o),
.register_value_o (instruction_decoder_register_value_o),
.we_o (instruction_decoder_we_o),
// Interface: instructions
.instruction_feed (instruction_decoder_instruction_feed),
.iaddr_o (instruction_decoder_iaddr_o));
// IP-XACT VLNV: tut.fi:cpu.logic:memory_controller:1.0
memory_controller #(
.DATA_WIDTH (32),
.ADDR_WIDTH (9),
.MEMORY_SIZE (512),
.PERIPHERAL_BASE (128),
.REGISTER_COUNT (8))
memory_controller(
// Interface: cpu_clk_sink
.clk_i (memory_controller_clk_i),
.rst_i (memory_controller_rst_i),
// Interface: cpu_system
.sys_active_i (memory_controller_sys_active_i),
.sys_address_i (memory_controller_sys_address_i),
.sys_data_i (memory_controller_sys_data_i),
.sys_we_i (memory_controller_sys_we_i),
.sys_data_o (memory_controller_sys_data_o),
.sys_rdy_o (memory_controller_sys_rdy_o),
.sys_read_rdy_o (memory_controller_sys_read_rdy_o),
// Interface: local_data
.local_read_data (memory_controller_local_read_data),
.local_address_o (memory_controller_local_address_o),
.local_write_data (memory_controller_local_write_data),
.local_write_o (memory_controller_local_write_o),
// Interface: peripheral_access
.periph_data_i (memory_controller_periph_data_i),
.periph_slave_rdy (memory_controller_periph_slave_rdy),
.periph_address_o (memory_controller_periph_address_o),
.periph_data_o (memory_controller_periph_data_o),
.periph_master_rdy (memory_controller_periph_master_rdy),
.periph_we_o (memory_controller_periph_we_o));
// IP-XACT VLNV: tut.fi:cpu.logic:register_bank:1.0
register_bank #(
.DATA_WIDTH (32),
.REGISTER_ID_WIDTH (3),
.REGISTER_COUNT (8))
register_bank(
// Interface: cpu_clk_sink
.clk_i (register_bank_clk_i),
.rst_i (register_bank_rst_i),
// Interface: cpu_system
.alu_active_i (register_bank_alu_active_i),
.alu_result_i (register_bank_alu_result_i),
.choose_register_i1 (register_bank_choose_register_i1),
.choose_register_i2 (register_bank_choose_register_i2),
.load_value_i (register_bank_load_value_i),
.mem_read_rdy_i (register_bank_mem_read_rdy_i),
.register_active_i (register_bank_register_active_i),
.register_input (register_bank_register_input),
.register_output1 (register_bank_register_output1),
.register_output2 (register_bank_register_output2));
endmodule
|
module decoder(INST, DR, SA, SB, IMM, MB, FS, MD, LD, MW, BS, OFF, HALT);
input [15:0] INST;
output [2:0] DR;
output [2:0] SA;
output [2:0] SB;
output [5:0] IMM;
output MB;
output [2:0] FS;
output MD;
output LD;
output MW;
output [2:0] BS;
output [5:0] OFF;
output HALT;
reg [2:0] DR;
reg [2:0] SA;
reg [2:0] SB;
reg MB;
reg [2:0] FS;
reg MD;
reg LD;
reg MW;
reg [2:0] BS;
reg [5:0] OFF;
reg HALT;
reg [5:0] IMM;
wire [3:0] OP;
wire [2:0] RS;
wire [2:0] RT;
wire [2:0] RD;
wire [2:0] FUNCT;
wire [5:0] IMM_INST;
assign OP = INST[15:12];
assign RS = INST[11:9];
assign RT = INST[8:6];
assign RD = INST[5:3];
assign FUNCT = INST[2:0];
assign IMM_INST = INST[5:0];
always @(*) begin
case (OP)
4'b0000: begin
DR = 3'b0;
SA = 3'b0;
SB = 3'b0;
MB = 1'b0;
FS = 3'b0;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = (FUNCT == 3'b001) ? 1'b1 : 1'b0;
IMM = IMM_INST;
end
4'b0010: begin
DR = RT;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b000;
MD = 1'b1;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b0100: begin
DR = 3'b0;
SA = RS;
SB = RT;
MB = 1'b1;
FS = 3'b000;
MD = 1'b0;
LD = 1'b0;
MW = 1'b1;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b0101: begin
DR = RT;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b000;
MD = 1'b0;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b0110: begin
DR = RT;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b101;
MD = 1'b0;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b0111: begin
DR = RT;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b110;
MD = 1'b0;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b1000: begin
DR = 3'b0;
SA = RS;
SB = RT;
MB = 1'b0;
FS = 3'b001;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b000;
OFF = IMM_INST;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b1001: begin
DR = 3'b0;
SA = RS;
SB = RT;
MB = 1'b0;
FS = 3'b001;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b001;
OFF = IMM_INST;
HALT = 1'b0;
IMM = IMM_INST;
end
4'b1010: begin
DR = 3'b0;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b000;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b010;
OFF = IMM_INST;
HALT = 1'b0;
IMM = 6'b0;
end
4'b1011: begin
DR = 3'b0;
SA = RS;
SB = 3'b0;
MB = 1'b1;
FS = 3'b000;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b011;
OFF = IMM_INST;
HALT = 1'b0;
IMM = 6'b0;
end
4'b1111: begin
DR = RD;
SA = RS;
SB = RT;
MB = 1'b0;
FS = FUNCT;
MD = 1'b0;
LD = 1'b1;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
default: begin
DR = 3'b0;
SA = 3'b0;
SB = 3'b0;
MB = 1'b0;
FS = 3'b0;
MD = 1'b0;
LD = 1'b0;
MW = 1'b0;
BS = 3'b100;
OFF = 6'b0;
HALT = 1'b0;
IMM = IMM_INST;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_1_V
`define SKY130_FD_SC_LS__BUF_1_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__buf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_1_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine ALU
// File : dex_alu.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dex_alu
(
input de_clk, /* clock input */
input rstn, /* reset input */
input [4:0] aluop, /* alu operation select */
input [15:0] ax, /* alu ax input */
input [15:0] bx, /* alu bx input */
input [15:0] ay, /* alu ay input */
input [15:0] by, /* alu by input */
input [4:0] ksel, /* alu constant select */
input load_actvn, /* load active command. */
input ps32_2, /* pixel size 32. */
input ps16_2, /* pixel size 16. */
input local_sol, /* Local start of line. */
input mod8, /* Modulo 8 operation. */
input mod32, /* Modulo 32 operation. */
input pad8_2, /* 8 bit padding. */
input read_2, /* reads are enabled. */
input b_cin,
output [15:0] fx, /* alu fx output */
output [15:0] fy, /* alu fy output */
output xeqz, /* alu fx equals zero */
output yeqz, /* alu fy equals zero */
output [1:0] frst8, /* first 8 flag output. */
output [3:0] fx_1, /* prepipe line fx output for the word count register. */
output signx, /* alu fx sign bit */
output signy, /* alu fy sign bit */
output reg src_lte_dst /* source pointer to the left of dstination pointer. */
);
reg [15:0] ik_r;
wire [15:0] k_r;
reg [15:0] new_fx,
new_fy,
new_ax,
new_bx,
new_ay,
new_by;
reg cinx, n_cinx;
reg ciny, n_ciny;
reg [15:0] n_new_ax, n_new_ay, n_new_bx, n_new_by;
reg n_ldfrst8, n_ldfrst8_s, n_ldsngl;
reg ld_frst8; /* load first 8 register. */
reg ld_frst8_s; /* load first 8 register. */
reg ld_sngl; /* load single bit. */
reg frst81; /* first 8 register. */
reg frst80; /* first 8 register. */
reg mod32_sel; /* modulo 32 select delayed. */
reg mod8_sel; /* modulo 8 select delayed. */
wire [1:0] wadj; /* word adjustment. */
wire [1:0] wadj1; /* word adjustment. */
wire [1:0] wadj2; /* word adjustment. */
wire [2:0] sum4m;
wire [3:0] sum8m;
wire [4:0] sum16m;
reg [2:0] badj;
reg cin_i;
wire cin_d;
assign frst8 = {frst81,frst80};
/* include the global parameters */
//`include "de_param.h"
parameter zero = 5'h0,
one = 5'h1,
two = 5'h2,
three = 5'h3,
four = 5'h4,
five = 5'hc,
seven = 5'h5,
eight = 5'h6,
D256 = 5'h7,
D16 = 5'h8,
Hfff0 = 5'hb,
D24 = 5'hd, // not used
D48 = 5'he, // not used
// D49 = 5'hf, // not used
D95 = 5'h10,
D64 = 5'h11,
D94 = 5'h12,
D96 = 5'h13,
D112 = 5'h14,
D128 = 5'h15,
D896 = 5'h16,
D512 = 5'h17,
D1024 = 5'h9,
D2048 = 5'ha,
abs = 5'h0, // |bx|, |by|
add = 5'h1, // ax + bx, ay + by
addnib = 5'h2, // ax + bx(nibble)
addx = 5'h3, // ay + bx, ax + by
amcn = 5'h4, // ax-k, ay-k
movmod = 5'h5, // ay + by mod 8 or 32.
apcn = 5'h6, // ax+k, ay+k
cmp_add = 5'h7, // -bx + ax, -by + ay
apcn_d = 5'h8, // {ax + const, ax + const}
pad_x = 5'h9, // pad to 32 or 8 bits.
div16 = 5'ha, // bx/16 + wadj.
// div8 = 5'hb, // bx/32 + wadj.
err_inc = 5'hc, // ax<<1, ay <<1 - by
mov = 5'hd, // bx--> fx, by--> fy
mov_k = 5'he, // move constant.
movx = 5'hf, // bx--> fy, by--> fx
c_m_bnib = 5'h10, // K - b nibble.
nib = 5'h11, // nibble.
sub = 5'h12, // ax - bx, ay - by
subx = 5'h13, // ay - bx, ax - by
amcn_d = 5'h14, // {ax - const,ax - const}
X4 = 5'h15, // X * 4 (ax<<2)
div128 = 5'h16, // bx/128 + wadj128.
sub_d = 5'h17, // {ax - bx,ax - bx}
X8 = 5'h18, // X * 8 (ax<<3)
X16 = 5'h19, // X * 16 (ax<<3)
// zm_ofs = 5'h1a, // spare
addlin = 5'h1b, //
sublin = 5'h1c, //
div4l = 5'h1d, // bx/4 + linear wadj.
div8l = 5'h1e, // bx/8 + linear wadj.
div16l = 5'h1f; // bx/16 + linear wadj.
/* memory word count */
assign fx_1 = (aluop==mov) ? bx[3:0] :
(aluop==movx) ? by[3:0] :
(aluop==mov_k) ? k_r[3:0] : fx[3:0]; // new_fx[3:0];
always @(posedge de_clk)mod32_sel <= mod32;
always @(posedge de_clk)mod8_sel <= mod8;
always @(posedge de_clk)cin_i <= b_cin;
assign cin_d = cin_i;
/************************************************************************/
/* constant generator */
/************************************************************************/
always @(posedge de_clk) /* constant to be defined later */
begin
case(ksel) // synopsys parallel_case
zero: ik_r <= 16'h0;
one: ik_r <= 16'h1;
two: ik_r <= 16'h2;
three: ik_r <= 16'h3;
four: ik_r <= 16'h4;
five: ik_r <= 16'h5;
seven: ik_r <= 16'h7;
eight: ik_r <= 16'h8;
D256: ik_r <= 16'h100;
D16: ik_r <= 16'h10;
Hfff0: ik_r <= 16'hfff0;
D24: ik_r <= 16'h18;
D48: ik_r <= 16'h30;
// D49: ik_r <= 16'h30;
D95: ik_r <= 16'h5F;
D64: ik_r <= 16'h40;
D94: ik_r <= 16'h5E;
D96: ik_r <= 16'h60;
D112: ik_r <= 16'h70;
D128: ik_r <= 16'h80;
D896: ik_r <= 16'h380;
D512: ik_r <= 16'h200;
D1024: ik_r <= 16'h400;
D2048: ik_r <= 16'h800;
endcase
end
assign k_r = ik_r;
/************************************************************************/
/* ALU BLOCK */
/************************************************************************/
always @(posedge de_clk) begin
ld_frst8 <= n_ldfrst8;
ld_frst8_s <= n_ldfrst8_s;
ld_sngl <= n_ldsngl;
new_ax <= n_new_ax;
new_ay <= n_new_ay;
new_bx <= n_new_bx;
new_by <= n_new_by;
cinx <= n_cinx;
ciny <= n_ciny;
end
always @* begin
n_ldfrst8 = 1'b0;
n_ldfrst8_s = 1'b0;
n_ldsngl = 1'b0;
n_new_ax = 16'b0;
n_new_ay = 16'b0;
n_new_bx = 16'b0;
n_new_by = 16'b0;
n_cinx = 1'b0;
n_ciny = 1'b0;
case(aluop) // synopsys parallel_case
abs: begin
if(bx[15]) begin
n_new_bx = ~bx;
n_cinx = 1'b1;
end else n_new_bx = bx;
if(by[15]) begin
n_new_by = ~by;
n_ciny = 1'b1;
end else n_new_by = by;
end
add: begin
n_new_ax = ax;
n_new_bx = bx;
n_new_ay = ay;
n_new_by = by;
n_cinx=cin_d;
n_ciny=cin_d;
end
addlin: begin
n_new_ax = ax[9:0];
n_new_bx = {by[12:3],3'b000};
end
sublin: begin
if(read_2)n_new_ax[6:0] = ax[6:0];
else n_new_ax[9:0] = ax[9:0];
begin
if(ps32_2)n_new_bx = {14'h3fff,~bx[3:2]};
else if(ps16_2)n_new_bx = {13'h1fff,~bx[3:1]};
else n_new_bx = {12'hfff,~bx[3:0]};
end
n_cinx=1'b1;
n_ldfrst8_s=1'b1;
end
addnib: begin
n_new_bx = bx;
n_new_ax = ax;
n_new_by = bx;
n_new_ay = ax;
n_cinx=cin_d;
n_ciny=cin_d;
end
addx: begin
n_new_ax = ax;
n_new_bx = by;
n_new_ay = ay;
n_new_by = bx;
end
amcn: begin /* a port minus constant */
n_new_ax = ax;
n_new_bx = ~k_r;
n_new_ay = ay;
n_new_by = ~k_r;
n_cinx=1'b1;
n_ciny=1'b1;
end
movmod: begin /* constant minus a port */
if(mod8)n_new_ay = ay[2:0];
if(mod32)n_new_ay = ay[4:0];
end
apcn: begin
n_new_ax = ax;
n_new_bx = k_r;
n_new_ay = ay;
n_new_by = k_r;
end
cmp_add: begin
n_new_bx = ~bx;
n_new_ax = ay;
n_cinx=1;
end
apcn_d: begin // a plus constant double
n_new_ax = ax;
n_new_bx = k_r;
n_new_ay = ax;
n_new_by = k_r;
end
pad_x: begin
if(pad8_2)n_new_ay = {ax[15:3],3'h0};
else n_new_ay = {ax[15:5],5'h0};
if(pad8_2)n_new_by = {12'h0,|ax[2:0],3'h0};
else n_new_by = {10'h0,|ax[4:0],5'h0};
end
div16: begin
n_new_bx = (bx>>4);
n_new_ax = {14'h0,wadj};
n_ldsngl=1'b1;
end
div128: begin
n_new_bx = (bx>>7);
n_new_ax = {14'h0,wadj1};
n_ldsngl=1'b1;
end
/*
div8: begin
n_new_bx = (bx>>3);
n_new_ax = {13'h0,badj};
end
*/
div4l: begin
n_new_bx = (bx>>2'd2);
n_new_ax = {15'h0,sum4m[2]};
end
div8l: begin
n_new_bx = (bx>>2'd3);
n_new_ax = {15'h0,sum8m[3]};
end
div16l: begin
n_new_bx = (bx>>3'd4);
n_new_ax = {15'h0,sum16m[4]};
end
err_inc: begin
n_new_ax = (ax << 1'b1);
n_new_bx = ~(ay << 1'b1);
n_new_ay = ay << 1'b1;
n_cinx=1;
end
default: begin
// mov: begin
n_new_bx = bx;
n_new_by = by;
end
mov_k: begin
n_new_bx = k_r;
n_new_by = k_r;
end
movx: begin
n_new_bx = by;
n_new_ay = ax;
end
c_m_bnib: begin
n_new_bx = ~bx[3:0];
n_new_ax = k_r;
n_cinx=1;
end
nib: begin
n_new_ax = {12'b0,ax[3:0]};
n_new_bx = ~{12'b0,bx[3:0]};
n_cinx=1'b1;
n_ldfrst8=1'b1;
end
sub: begin
n_new_ax = ax;
n_new_bx = ~bx;
n_new_ay = ay;
n_new_by = ~by;
n_cinx=1'b1;
n_ciny=1'b1;
end
subx: begin
n_new_ax = ax;
n_new_bx = ~by;
n_cinx=1'b1;
end
amcn_d: begin /* a port minus constant */
n_new_ax = ax;
n_new_bx = ~k_r;
n_new_ay = ax;
n_new_by = ~k_r;
n_cinx=1'b1;
n_ciny=1'b1;
end
sub_d: begin
n_new_ax = ax;
n_new_bx = ~bx;
n_new_ay = ax;
n_new_by = ~bx;
n_cinx=1'b1;
n_ciny=1'b1;
end
X4: n_new_ax = (ax << 2);
X8: n_new_ax = (ax << 3);
X16: begin
n_new_ax = (ax << 4);
if(local_sol) begin
n_new_bx = ~({12'h0,bx[3:0]});
n_cinx=1'b1;
end
end
endcase
end
/************************************************************************/
/* This is the DUAL 16 bit adder. */
always @*
begin
new_fx=new_ax + new_bx + cinx;
new_fy=new_ay + new_by + ciny;
end
assign fx = new_fx;
assign fy = (mod32_sel) ? {new_ay[15:5],new_fy[4:0]} :
(mod8_sel) ? {new_ay[15:3],new_fy[2:0]} : new_fy;
wire new_ld_frst8;
wire new_ld_frst8_s;
wire new_ld_sngl;
assign new_ld_frst8 =ld_frst8;
assign new_ld_frst8_s =ld_frst8_s;
assign new_ld_sngl =ld_sngl;
always @(posedge de_clk or negedge rstn) begin
if (!rstn) src_lte_dst <= 1'b0;
else if (new_ld_frst8) src_lte_dst <= (new_fx[4] | (~|new_fx[3:0]));
else if (!load_actvn) src_lte_dst <= 1'b0;
end
always @(posedge de_clk or negedge rstn) begin
if (!rstn) frst81 <= 1'b0;
else if (new_ld_frst8) frst81 <= new_fx[4];
else if (new_ld_frst8_s) frst81 <= new_fx[5];
else if (!load_actvn) frst81 <= 1'b0;
end
always @(posedge de_clk or negedge rstn) begin
if (!rstn) frst80 <= 1'b0;
else if (new_ld_sngl) frst80 <= ~|new_fx[11:1];
else if (!load_actvn) frst80 <= 1'b0;
end
assign xeqz = (new_fx == 16'h0);
assign yeqz = (new_fy == 16'h0);
assign signx = new_fx[15];
assign signy = new_fy[15];
/****************************************************************/
/* WADJ */
wire [4:0] sum;
wire [3:0] ain;
wire sum_or;
assign ain = ax[3:0];
assign sum = ain[3:0] + bx[3:0];
assign sum_or = | sum[3:0];
assign wadj[1] = (sum[4] && sum_or);
assign wadj[0] = (sum[4] ^ sum_or);
/****************************************************************/
/* WADJ128 */
wire [7:0] sum1;
wire [6:0] ain1;
wire sum_or1;
assign ain1 = ax[6:0];
assign sum1 = ain1[6:0] + bx[6:0];
assign sum_or1 = | sum1[6:0];
assign wadj1[1] = (sum1[7] && sum_or1);
assign wadj1[0] = (sum1[7] ^ sum_or1);
/****************************************************************/
// div??m;
assign sum16m = ax[3:0] + bx[3:0];
assign sum8m = ax[2:0] + bx[2:0];
assign sum4m = ax[1:0] + bx[1:0];
/****************************************************************/
/* BADJ
always @(ax or bx)
begin
case({ax[4:3],|ax[2:0],|bx[2:0]}) // synopsys full_case parallel_case
4'b0000:badj=3'h0;
4'b0001:badj=3'h1;
4'b0010:badj=3'h1;
4'b0011:badj=3'h2;
4'b0100:badj=3'h2;
4'b0101:badj=3'h3;
4'b0110:badj=3'h2;
4'b0111:badj=3'h3;
4'b1000:badj=3'h3;
4'b1001:badj=3'h4;
4'b1010:badj=3'h3;
4'b1011:badj=3'h4;
4'b1100:badj=3'h4;
4'b1101:badj=3'h5;
4'b1110:badj=3'h4;
4'b1111:badj=3'h5;
endcase
end
****************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_MS__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_ms__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_MUX_4TO2_TB_V
|
// DE2_70_flash_word_tester //
module DE2_70_flash_word_tester (
input TIME_OUT,
input iCLK_28,
input iSTART,
output reg oEND,
output reg oERASE_STATUS,
output oSTATUS,
inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
output [25:0] oFLASH_A, // FLASH Address bus 26 Bits
output oFLASH_WE_N, // FLASH Write Enable
output oFLASH_RST_N, // FLASH Reset
output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
input iFLASH_RY_N, // FLASH Ready/Busy output
output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
output oFLASH_OE_N, // FLASH Output Enable
output oFLASH_CE_N , // FLASH Chip Enable
//TEST//
output reg ERASE,
output reg PROG,
output reg READ,
output reg RESET,
output reg OK ,
output reg FAIL,
output VERIFY_TIME,
output [21:0]flash_addr,
output [3:0] flash_cmd
);
wire WR_END;
reg [5:0]ST;
reg [1:0]SW;
reg [31:0]disp_cnt ;
always @(posedge iCLK_28) disp_cnt <= disp_cnt + 1;
always @( posedge disp_cnt[24]) begin
if (!iSTART) begin
ST = 30;
ERASE=0;
oERASE_STATUS = 0;
PROG =0;
READ =0;
OK =0;
FAIL =0;
RESET=1;//reset trigger on//
oEND =0;
end
else begin
if ( ( TIME_OUT ) && ( !oEND ) ) begin oEND = 1; FAIL = 1; ST = 5; end
case (ST)
30:begin
ST = 27;//ST-1;
RESET = 0; //reset trigger off//
end
29:begin
ST = ST-1;
end
28:begin
ST = ST-1;
end
27:begin
ST = 24;//ST-1;
ERASE = 1;//erase trigger on//
end
26:begin
ST = ST-1;
end
25:begin
ST = ST-1;
end
24:begin
ST = 21;//ST-1;
ERASE = 0;//erase trigger off//
end
23:begin
ST = ST-1;
end
22:begin
ST = ST-1;
end
21:begin
if ( flash_ready ) ST = 18;//ST-1;
end
20:begin
ST = ST-1;
end
19:begin
ST = ST-1;
end
18:begin
if ( iFLASH_RY_N ) begin
oERASE_STATUS = 1;
ST = ST-1;
end
end
17:begin
ST = ST-1;
READ = 1;//READ trigger on//
SW = 3;
end
16:begin
ST = ST-1;
READ = 0;//READ trigger on//
end
15:begin
if (WR_END) ST=ST-1;
end
14:begin
ST = 12;//ST-1;
PROG = 1;//PROGRAM trigger on//
SW = 2; //<<
end
13:begin
ST = ST-1;
end
12:begin
ST = 10;//ST-1;
PROG = 0;//PROGRAM trigger on//
end
11:begin
ST = ST-1;
end
10:begin
if (WR_END) ST=ST-1;
end
9:begin
ST = ST-1;
READ = 1;//READ trigger on//
SW = 2; //<<
end
8:begin
ST = ST-1;
READ = 0;//READ trigger on//
end
7:begin
if (WR_END) ST=ST-1;
end
6:begin
oEND = 1;
ST=4;//ST-1;
if ( oSTATUS ) OK = 1; else FAIL = 1;
end
5:begin
ST=ST-1;
end
4:begin
OK = 0;
FAIL = 0;
end
endcase
end
end
//FLASH CONTROLLER//
wire [15:0]flash_data;
wire flash_tr;
wire flash_ready;
assign flash_data = (//program data
( SW[1:0] ==0)? flash_addr[15:0]: (
( SW[1:0] ==1)? 16'haaaa: (
( SW[1:0] ==2)? 16'h0000: 16'hffff
)));
reg error ; //<< oSTATUS
always @(posedge RESET or posedge oFLASH_OE_N) begin
if ( RESET ) error = 1;
else if ((VERIFY_TIME ) && (error))
error = ~( { FLASH_DQ15_AM1 , FLASH_DQ } != flash_data ) ;
end
wire WE_CLK;
wire p_ready;
flash_writer f1(
.WE_CLK(WE_CLK),
.p_ready(p_ready),
.iFLASH_RY_N ( iFLASH_RY_N ), // for program
.iOSC_28 ( iCLK_28 ),
.iERASE ( ERASE ),
.iPROGRAM ( PROG ),
.iVERIFY ( READ ),
.iOK(OK),
.iFAIL(FAIL),
.iRESET_N ( RESET ),
.oREAD_PRO_END (WR_END),
.oVERIFY_TIME(VERIFY_TIME),//1 active
.oFLASH_ADDR ( flash_addr),
.oFLASH_CMD ( flash_cmd ),
.oFLASH_TR ( flash_tr )
);
// FLASH Controller //
wire FL_CE_o;
Flash_Controller u5(
.p_ready(p_ready),
.iFLASH_RY_N (iFLASH_RY_N ),
.iCLK ( iCLK_28 ),
.iRST_n ( 1'b1 ),
.iStart ( flash_tr ), //<< iSTART
.iDATA ( flash_data ),
.iADDR ( flash_addr ),
.iCMD ( flash_cmd ),
.oReady ( flash_ready ),
.WE_CLK(WE_CLK),
.FL_DQ ( { FLASH_DQ15_AM1 , FLASH_DQ } ) , //<< FLASH side
.FL_ADDR ( oFLASH_A[21:0] ), //<< FLASH side
.FL_WE_n ( oFLASH_WE_N ), //<< FLASH side
.FL_CE_n ( oFLASH_CE_N ), //<< FLASH side
.FL_OE_n ( oFLASH_OE_N ) //<< FLASH side
);
assign oFLASH_RST_N = ~RESET;
assign oFLASH_WP_N = 1; // FLASH Write Protect /Programming Acceleration
assign oFLASH_BYTE_N = 1; // FLASH Byte/Word Mode Configuration
assign oSTATUS = error;
endmodule |
/*###########################################################################
# Function: Clock and reset generator
#
# tx_lclk_div4 - Parallel data clock (125Mhz)
#
# tx_lclk - DDR data clock (500MHz)
#
# tx_lclk90 - DDR "Clock" for IO (500MHz)
#
# rx_lclk - High speed RX clock for IO (300MHz phase shifted)
#
# rx_lclk_div4 - Low speed RX clock for logic (75MHz)
############################################################################
*/
`include "elink_constants.v"
module eclocks (/*AUTOARG*/
// Outputs
tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk, rx_lclk_div4, e_cclk_p,
e_cclk_n, elink_reset, e_resetb,
// Inputs
reset, elink_en, sys_clk, rx_clkin
);
//TODO: change to parameter
`ifdef SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Frequency Settings (Mhz)
parameter FREQ_SYSCLK = 100;
parameter FREQ_RXCLK = 300;
parameter FREQ_TXCLK = 300;
parameter FREQ_IDELAY = 200;
parameter FREQ_CCLK = 600;
parameter TXCLK_PHASE = 90; //txclk phase shift
parameter RXCLK_PHASE = 0; //270; //-90 deg rxclk phase shift
//VCO multiplers
parameter MMCM_VCO_MULT = 12; //TX + CCLK
parameter PLL_VCO_MULT = 4; //RX
//Input clock, reset, config interface
input reset; // async input reset
input elink_en; // elink enable (from pin or register)
//Main input clocks
input sys_clk; // always on input clk cclk/TX MMCM
input rx_clkin; // input clk for RX only PLL
//TX Clocks
output tx_lclk; // tx clock for DDR IO
output tx_lclk90; // tx output clock shifted by 90 degrees
output tx_lclk_div4; // tx slow clock for logic
//RX Clocks
output rx_lclk; // rx high speed clock for DDR IO
output rx_lclk_div4; // rx slow clock for logic
//Epiphany "free running" clock
output e_cclk_p, e_cclk_n;
//Reset
output elink_reset; // reset for elink logic & IO
output e_resetb; // reset fpr Epiphany chip
//Don't touch these! (derived parameters)
localparam real SYSCLK_PERIOD = 1000.000000/FREQ_SYSCLK;
localparam real RXCLK_PERIOD = 1000.000000/FREQ_RXCLK;
localparam integer TXCLK_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_TXCLK;
localparam integer CCLK_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_CCLK;
localparam integer IREF_DIVIDE = MMCM_VCO_MULT*FREQ_SYSCLK/FREQ_IDELAY;
localparam integer RXCLK_DIVIDE = PLL_VCO_MULT;
//############
//# WIRES
//############
//CCLK
wire cclk_reset;
wire cclk_i;
wire cclk_bufio;
wire cclk_oddr;
//Idelay controller
wire idelay_reset;
wire idelay_ready; //ignore this?
wire idelay_ref_clk_i;
wire idelay_ref_clk;
//RX
wire rx_lclk_i;
wire rx_lclk_div4_i;
//TX
wire tx_lclk_i;
wire tx_lclk90_i;
wire tx_lckl_div4_i;
//MMCM & PLL
wire cclk_fb_in;
wire cclk_fb_out;
wire lclk_fb_i;
wire pll_reset;
wire cclk_locked;
wire lclk_fb_in;
wire lclk_fb_out;
reg cclk_locked_reg;
reg cclk_locked_sync;
reg rx_locked_reg;
reg rx_locked_sync;
wire lclk_locked;
//###########################
// RESET STATE MACHINE
//###########################
reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
reg heartbeat;
wire reset_in;
reg reset_sync;
reg [2:0] reset_state;
//wrap around counter that generates a 1 cycle heartbeat
//free running counter...
always @ (posedge sys_clk)
begin
reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
heartbeat <= ~(|reset_counter[RCW-1:0]);
end
//two clock synchronizer
always @ (posedge sys_clk)
begin
//TODO: Does rx_lclk always run when cclk does? Restb ?
rx_locked_reg <= lclk_locked;
rx_locked_sync <= rx_locked_reg;
cclk_locked_reg <= cclk_locked; // & clk_locked
cclk_locked_sync <= cclk_locked_reg;
end
`define RESET_ALL 3'b000
`define START_CCLK 3'b001
`define STOP_CCLK 3'b010
`define START_EPIPHANY 3'b011
`define HOLD_IT 3'b100
`define TX_ACTIVE 3'b101
`define ACTIVE 3'b110
//Reset sequence state machine
always @ (posedge sys_clk or posedge reset)
if(reset)
reset_state[2:0] <= `RESET_ALL;
else if(heartbeat)
case(reset_state[2:0])
`RESET_ALL :
reset_state[2:0] <= `START_CCLK;
`START_CCLK :
if(cclk_locked_sync)
reset_state[2:0] <= `STOP_CCLK;
`STOP_CCLK :
reset_state[2:0] <= `START_EPIPHANY;
`START_EPIPHANY :
reset_state[2:0] <= `HOLD_IT;
`HOLD_IT :
if(cclk_locked_sync)
reset_state[2:0] <= `TX_ACTIVE;
`TX_ACTIVE :
reset_state[2:0] <= `ACTIVE;
`ACTIVE:
if(~elink_en)
reset_state[2:0] <= `RESET_ALL; //stay there until nex reset
endcase // case (reset_state[2:0])
//reset PLL during 'reset' and during quiet time around reset edge
//TODO: this is a bug if the RX gets a clock that is not a turnaround from TX
assign pll_reset = (reset_state[2:0] != `ACTIVE);
assign idelay_reset = (reset_state[2:0]==`RESET_ALL) |
(reset_state[2:0]==`START_CCLK) |
reset;
assign cclk_reset = (reset_state[2:0]==`RESET_ALL) |
(reset_state[2:0]==`STOP_CCLK) |
(reset_state[2:0]==`START_EPIPHANY) |
reset
;
assign e_resetb = (reset_state[2:0]==`START_EPIPHANY) |
(reset_state[2:0]==`HOLD_IT) |
(reset_state[2:0]==`ACTIVE) |
(reset_state[2:0]==`TX_ACTIVE)
;
assign elink_reset = reset |
~((reset_state[2:0] == `TX_ACTIVE) |
(reset_state[2:0] == `ACTIVE));
`ifdef TARGET_XILINX
//###########################
// MMCM FOR TXCLK + CCLK
//###########################
MMCME2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(MMCM_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(SYSCLK_PERIOD),
.CLKOUT0_DIVIDE_F(CCLK_DIVIDE), //cclk_c
.CLKOUT1_DIVIDE(TXCLK_DIVIDE), //tx_lclk
.CLKOUT2_DIVIDE(TXCLK_DIVIDE), //tx_lclk90
.CLKOUT3_DIVIDE(TXCLK_DIVIDE*4), //tx_lclk_div4
.CLKOUT4_DIVIDE(IREF_DIVIDE), //idelay_refclk
.CLKOUT5_DIVIDE(128), //
.CLKOUT6_DIVIDE(128), //
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(TXCLK_PHASE),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) mmcm_cclk
(
.CLKOUT0(cclk_i),
.CLKOUT0B(),
.CLKOUT1(tx_lclk_i),
.CLKOUT1B(),
.CLKOUT2(tx_lclk90_i),
.CLKOUT2B(),
.CLKOUT3(tx_lclk_div4_i),
.CLKOUT3B(),
.CLKOUT4(idelay_ref_clk_i),
.CLKOUT5(),
.CLKOUT6(),
.PWRDWN(1'b0),
.RST(cclk_reset), //reset
.CLKFBIN(cclk_fb_in),
.CLKFBOUT(cclk_fb_out), //feedback clock
.CLKIN1(sys_clk), //input clock
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),
.DO(),
.LOCKED(cclk_locked), //locked indicator
.PSCLK(1'b0),
.PSEN(1'b0),
.PSDONE(),
.PSINCDEC(1'b0),
.CLKFBSTOPPED(),
.CLKINSTOPPED()
);
//Idelay ref clock buffer
BUFG idelay_ref_bufg_i(.I(idelay_ref_clk_i), .O(idelay_ref_clk));
//Feedback buffer
BUFG cclk_fb_bufg_i(.I(cclk_fb_out), .O(cclk_fb_in));
//Tx clock buffers
BUFG tx_lclk_bufg_i (.I(tx_lclk_i), .O(tx_lclk));
BUFG tx_lclk_div4_bufg_i (.I(tx_lclk_div4_i), .O(tx_lclk_div4));
BUFG tx_lclk90_bufg_i (.I(tx_lclk90_i), .O(tx_lclk90));
//###########################
// PLL RX
//###########################
PLLE2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(PLL_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(RXCLK_PERIOD),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(128),
.CLKOUT2_DIVIDE(128),
.CLKOUT3_DIVIDE(128),
.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(RXCLK_PHASE),
.CLKOUT5_PHASE(RXCLK_PHASE/4),
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_rx
(
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(rx_lclk_i),
.CLKOUT5(rx_lclk_div4_i),
.PWRDWN(1'b0),
.RST(pll_reset),
.CLKFBIN(lclk_fb_in),//lclk_fb_in
.CLKFBOUT(lclk_fb_out),
.CLKIN1(rx_clkin),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),
.DO(),
.LOCKED(lclk_locked)
);
//Rx clock buffers
BUFG rx_lclk_bufg_i(.I(rx_lclk_i), .O(rx_lclk)); //goes to erx_io
BUFG rx_lclk_div4_bufg_i(.I(rx_lclk_div4_i), .O(rx_lclk_div4)); //goes to erx_io
//Feedback buffers
BUFG lclk_fb_bufg_i0(.I(rx_lclk), .O(lclk_fb_in)); //.I(lclk_fb_in),
//###########################
// CCLK
//###########################
//CCLK differential buffer
OBUFDS cclk_obuf (.O (e_cclk_p),
.OB (e_cclk_n),
.I (cclk_oddr)
);
//CCLK oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"),
.SRTYPE("ASYNC"))
oddr_lclk (
.Q (cclk_oddr),
.C (cclk_bufio),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (1'b0),
.S (1'b0));
//CCLK bufio
BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_i));
//###########################
// Idelay controller
//###########################
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYCTRL idelayctrl_inst
(
.RDY(idelay_ready), // check ready flag in reset sequence?
.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
.RST(idelay_reset));
`endif // `ifdef TARGET_XILINX
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
Contributed by Gunnar Hillerstrom
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
(** printing Not %\ensuremath\neg% #~# *)
(** printing CNot %\ensuremath\neg% #~# *)
(** printing Iff %\ensuremath\Leftrightarrow% #⇔# *)
(** printing CFalse %\ensuremath\bot% #⊥# *)
(** printing False %\ensuremath\bot% #⊥# *)
(** printing CTrue %\ensuremath\top% *)
(** printing True %\ensuremath\top% *)
(** printing or %\ensuremath{\mathrel\vee}% *)
(** printing and %\ensuremath{\mathrel\wedge}% *)
Require Export Coq.Arith.Compare_dec.
Require Export CoRN.logic.CornBasics.
Require Export Coq.ZArith.ZArith.
Require Export Coq.setoid_ring.ZArithRing.
Require Export Coq.Arith.Div2.
Require Export Coq.Arith.Wf_nat.
From Coq Require Import Lia.
Set Automatic Introduction.
(**
* Extending the Coq Logic
Because notions of apartness and order have computational meaning, we
will have to define logical connectives in [Type]. In order to
keep a syntactic distinction between types of terms, we define [CProp]
as an alias for [Type], to be used as type of (computationally meaningful)
propositions.
Falsehood and negation will typically not be needed in [CProp], as
they are used to refer to negative statements, which carry no
computational meaning. Therefore, we will simply define a negation
operator from [Type] to [Prop] .
Conjunction, disjunction and existential quantification will have to come in
multiple varieties. For conjunction, we will need four operators of type
[s1->s2->s3], where [s3] is [Prop] if both [s1] and [s2]
are [Prop] and [CProp] otherwise.
We here take advantage of the inclusion of [Prop] in [Type].
Disjunction is slightly different, as it will always return a value in [CProp] even
if both arguments are propositions. This is because in general
it may be computationally important to know which of the two branches of the
disjunction actually holds.
Existential quantification will similarly always return a value in [CProp].
- [CProp]-valued conjuction will be denoted as [and];
- [Crop]-valued conjuction will be denoted as [or];
- Existential quantification will be written as [{x:A & B}] or [{x:A | B}],
according to whether [B] is respectively of type [CProp] or [Prop].
In a few specific situations we do need truth, false and negation in [CProp],
so we will also introduce them; this should be a temporary option.
Finally, for other formulae that might occur in our [CProp]-valued
propositions, such as [(le m n)], we have to introduce a [CProp]-valued
version.
*)
Notation "'CProp'":= Type.
Section Basics.
(**
** Basics
Here we treat conversion from [Prop] to [CProp] and vice versa,
and some basic connectives in [CProp].
*)
Definition True_constr := I.
(* The name I is occasionally used for other things, hiding True's constructor. *)
Definition Not (P : CProp) := P -> False.
Definition Iff (A B : CProp) : CProp := prod (A -> B) (B -> A).
Definition proj1_sigT (A : Type) (P : A -> CProp) (e : sigT P) :=
match e with
| existT _ a b => a
end.
Definition proj2_sigT (A : Type) (P : A -> CProp) (e : sigT P) :=
match e return (P (proj1_sigT A P e)) with
| existT _ a b => b
end.
Inductive sig2T (A : Type) (P Q : A -> CProp) : CProp :=
exist2T : forall x : A, P x -> Q x -> sig2T A P Q.
Definition proj1_sig2T (A : Type) (P Q : A -> CProp) (e : sig2T A P Q) :=
match e with
| exist2T _ _ _ a b c => a
end.
Definition proj2a_sig2T (A : Type) (P Q : A -> CProp) (e : sig2T A P Q) :=
match e return (P (proj1_sig2T A P Q e)) with
| exist2T _ _ _ a b c => b
end.
Definition proj2b_sig2T (A : Type) (P Q : A -> CProp) (e : sig2T A P Q) :=
match e return (Q (proj1_sig2T A P Q e)) with
| exist2T _ _ _ a b c => c
end.
End Basics.
(* begin hide *)
Infix "or" := sum (at level 85, right associativity).
Infix "and" := prod (at level 80, right associativity).
Notation "A 'IFF' B" := (Iff A B) (at level 95, no associativity).
Notation ProjT1 := (proj1_sigT _ _).
Notation ProjT2 := (proj2_sigT _ _).
(* end hide *)
(**
Some lemmas to make it possible to use [Step]
when reasoning with bi-implications. *)
Lemma Iff_left :
forall (A B C : CProp),
(A IFF B) -> (A IFF C) -> (C IFF B).
Proof.
unfold Iff.
intuition.
Qed.
Lemma Iff_right:
forall (A B C : CProp),
(A IFF B) -> (A IFF C) -> (B IFF C).
Proof.
unfold Iff.
intuition.
Qed.
Lemma Iff_refl : forall (A : CProp), (A IFF A).
Proof.
unfold Iff.
intuition.
Qed.
Lemma Iff_sym :
forall (A B : CProp),(A IFF B) -> (B IFF A).
Proof.
unfold Iff.
intuition.
Qed.
Lemma Iff_trans :
forall (A B C : CProp),
(prod (A IFF B) (B IFF C)) -> (A IFF C).
Proof.
unfold Iff.
intuition.
Qed.
Lemma Iff_imp_imp :
forall (A B : CProp),
(A IFF B) -> (prod (A->B) (B->A)).
Proof.
unfold Iff.
intuition.
Qed.
Declare Right Step Iff_right.
Declare Left Step Iff_left.
Hint Resolve Iff_trans Iff_sym Iff_refl Iff_right Iff_left Iff_imp_imp : algebra.
Lemma not_r_cor_rect :
forall (A B : CProp) (S : Type) (l r : S),
Not B ->
forall H : A or B,
@sum_rect A B (fun _ : A or B => S) (fun x : A => l) (fun x : B => r) H = l.
Proof.
intros. elim H0.
intros. reflexivity.
intro. elim H. assumption.
Qed.
Lemma not_l_cor_rect :
forall (A B : CProp) (S : Type) (l r : S),
Not A ->
forall H : A or B,
@sum_rect A B (fun _ : A or B => S) (fun x : A => l) (fun x : B => r) H = r.
Proof.
intros. elim H0.
intro. elim H. assumption.
intros. reflexivity.
Qed.
(* begin hide *)
(** This notation is incompatible with [Program]. It should be avoided *)
Notation "{ x : A | P }" := (sigT (fun x : A => P):CProp)
(at level 0, x at level 99) : type_scope.
Notation "{ x : A | P | Q }" :=
(sig2T A (fun x : A => P) (fun x : A => Q)) (at level 0, x at level 99) :
type_scope.
(* end hide *)
Hint Resolve pair inl inr existT exist2T : core.
Section Choice.
(* **Choice
Let [P] be a predicate on $\NN^2$#N times N#.
*)
Variable P : nat -> nat -> Prop.
Lemma choice :
(forall n : nat, {m : nat | P n m}) ->
{d : nat -> nat | forall n : nat, P n (d n)}.
Proof.
intro H.
exists (fun i : nat => proj1_sigT _ _ (H i)).
apply (fun i : nat => proj2_sigT _ _ (H i)).
Qed.
End Choice.
Section Logical_Remarks.
(** We prove a few logical results which are helpful to have as lemmas
when [A], [B] and [C] are non trivial.
*)
Lemma CNot_Not_or : forall A B C : CProp,
(A -> Not C) -> (B -> Not C) -> ~ Not (A or B) -> Not C.
Proof.
intros A B C H H0 H1.
intro H2.
apply H1.
intro H3.
elim H3.
intro; apply H; auto.
intro; apply H0; auto.
Qed.
Lemma CdeMorgan_ex_all : forall (A : Type) (P : A -> CProp) (X : Type),
(sigT P -> X) -> forall a : A, P a -> X.
Proof.
intros A P X H a H0.
eauto.
Qed.
End Logical_Remarks.
Section CRelation_Definition.
(**
** [CProp]-valued Relations
Similar to Relations.v in Coq's standard library.
%\begin{convention}% Let [A:Type] and [R:Crelation].
%\end{convention}%
*)
Variable A : Type.
Definition Crelation := A -> A -> CProp.
Variable R : Crelation.
Definition Creflexive : CProp :=
forall x : A, R x x.
Definition Ctransitive : CProp :=
forall x y z : A, R x y -> R y z -> R x z.
Definition Csymmetric : CProp :=
forall x y : A, R x y -> R y x.
Record Cequivalence : CProp :=
{Cequiv_refl : Creflexive;
Cequiv_symm : Csymmetric;
Cequiv_trans : Ctransitive}.
Definition Cdecidable (P:CProp):= P or Not P.
End CRelation_Definition.
Fixpoint member (A : Type) (n : A) (l : list A) {struct l} : CProp :=
match l with
| nil => False
| cons y m => member A n m or y = n
end.
Arguments member [A].
Section TRelation_Definition.
(**
** [Prop]-valued Relations
Analogous.
%\begin{convention}% Let [A:Type] and [R:Trelation].
%\end{convention}%
*)
Variable A : Type.
Definition Trelation := A -> A -> Prop.
Variable R : Trelation.
Definition Treflexive : CProp := forall x : A, R x x.
Definition Ttransitive : CProp := forall x y z : A, R x y -> R y z -> R x z.
Definition Tsymmetric : CProp := forall x y : A, R x y -> R y x.
Definition Tequiv : CProp := Treflexive and Ttransitive and Tsymmetric.
End TRelation_Definition.
Section le_odd.
(**
** The relation [le], [lt], [odd] and [even] in [CProp]
*)
Inductive Cle (n : nat) : nat -> CProp :=
| Cle_n : Cle n n
| Cle_S : forall m : nat, Cle n m -> Cle n (S m).
Theorem Cnat_double_ind : forall R : nat -> nat -> CProp,
(forall n : nat, R 0 n) -> (forall n : nat, R (S n) 0) ->
(forall n m : nat, R n m -> R (S n) (S m)) -> forall n m : nat, R n m.
Proof.
simple induction n; auto.
simple induction m; auto.
Qed.
Theorem my_Cle_ind : forall (n : nat) (P : nat -> CProp),
P n -> (forall m : nat, Cle n m -> P m -> P (S m)) ->
forall n0 : nat, Cle n n0 -> P n0.
Proof.
intros n P.
generalize (Cle_rect n (fun (n0 : nat) (H : Cle n n0) => P n0)); intro.
assumption.
Qed.
Theorem Cle_n_S : forall n m : nat, Cle n m -> Cle (S n) (S m).
Proof.
intros n m H.
pattern m in |- *.
apply (my_Cle_ind n).
apply Cle_n.
intros.
apply Cle_S.
assumption.
assumption.
Qed.
Lemma toCle : forall m n : nat, m <= n -> Cle m n.
Proof.
intros m.
induction m as [| m Hrecm].
simple induction n.
intro H.
apply Cle_n.
intros n0 H H0.
apply Cle_S.
apply H.
apply le_O_n.
simple induction n.
intro.
elimtype False.
inversion H.
intros n0 H H0.
generalize (le_S_n _ _ H0); intro H1.
generalize (Hrecm _ H1); intro H2.
apply Cle_n_S.
assumption.
Qed.
Hint Resolve toCle.
Lemma Cle_to : forall m n : nat, Cle m n -> m <= n.
Proof.
intros m n H.
elim H.
apply le_n.
intros m0 s H0.
apply le_S.
assumption.
Qed.
Definition Clt (m n : nat) : CProp := Cle (S m) n.
Lemma toCProp_lt : forall m n : nat, m < n -> Clt m n.
Proof.
unfold lt in |- *.
unfold Clt in |- *.
intros m n H.
apply toCle.
assumption.
Qed.
Lemma Clt_to : forall m n : nat, Clt m n -> m < n.
Proof.
unfold lt in |- *.
unfold Clt in |- *.
intros m n H.
apply Cle_to.
assumption.
Qed.
Lemma Cle_le_S_eq : forall p q : nat, p <= q -> {S p <= q} + {p = q}.
Proof.
intros p q H.
elim (gt_eq_gt_dec p q); intro H0.
elim H0; auto.
elimtype False.
apply lt_not_le with q p; auto.
Qed.
Lemma Cnat_total_order : forall m n : nat, m <> n -> {m < n} + {n < m}.
Proof.
intros m n H.
elim (gt_eq_gt_dec m n).
intro H0.
elim H0; intros.
left; auto.
elimtype False.
auto.
auto.
Qed.
Inductive Codd : nat -> CProp :=
Codd_S : forall n : nat, Ceven n -> Codd (S n)
with Ceven : nat -> CProp :=
| Ceven_O : Ceven 0
| Ceven_S : forall n : nat, Codd n -> Ceven (S n).
Lemma Codd_even_to : forall n : nat, (Codd n -> odd n) /\ (Ceven n -> even n).
Proof.
simple induction n.
split.
intro H.
inversion H.
intro.
apply even_O.
intros n0 H.
elim H; intros H0 H1.
split.
intro H2.
inversion H2.
apply odd_S.
apply H1.
assumption.
intro H2.
inversion H2.
apply even_S.
apply H0.
assumption.
Qed.
Lemma Codd_to : forall n : nat, Codd n -> odd n.
Proof.
intros n H.
elim (Codd_even_to n); auto.
Qed.
Lemma Ceven_to : forall n : nat, Ceven n -> even n.
Proof.
intros n H.
elim (Codd_even_to n); auto.
Qed.
Lemma to_Codd_even : forall n : nat, (odd n -> Codd n) and (even n -> Ceven n).
Proof.
simple induction n.
split.
intro H.
elimtype False.
inversion H.
intro H.
apply Ceven_O.
intros n0 H.
elim H; intros H0 H1.
split.
intro H2.
apply Codd_S.
apply H1.
inversion H2.
assumption.
intro H2.
apply Ceven_S.
apply H0.
inversion H2.
assumption.
Qed.
Lemma to_Codd : forall n : nat, odd n -> Codd n.
Proof.
intros.
elim (to_Codd_even n); auto.
Qed.
Lemma to_Ceven : forall n : nat, even n -> Ceven n.
Proof.
intros.
elim (to_Codd_even n); auto.
Qed.
End le_odd.
Section Misc.
(**
** Miscellaneous
*)
Lemma CZ_exh : forall z : Z, {n : nat | z = n} or {n : nat | z = (- n)%Z}.
Proof.
intro z.
elim z.
left.
exists 0.
auto.
intro p.
left.
exists (nat_of_P p).
rewrite convert_is_POS.
reflexivity.
intro p.
right.
exists (nat_of_P p).
rewrite min_convert_is_NEG.
reflexivity.
Qed.
Lemma Cnats_Z_ind : forall P : Z -> CProp,
(forall n : nat, P n) -> (forall n : nat, P (- n)%Z) -> forall z : Z, P z.
Proof.
intros P H H0 z.
elim (CZ_exh z); intros H1.
elim H1; intros n H2.
rewrite H2.
apply H.
elim H1; intros n H2.
rewrite H2.
apply H0.
Qed.
Lemma Cdiff_Z_ind : forall P : Z -> CProp,
(forall m n : nat, P (m - n)%Z) -> forall z : Z, P z.
Proof.
intros P H z.
apply Cnats_Z_ind.
intro n.
replace (Z_of_nat n) with (n - 0%nat)%Z.
apply H.
simpl in |- *.
auto with zarith.
intro n.
replace (- n)%Z with (0%nat - n)%Z.
apply H.
simpl in |- *.
reflexivity.
Qed.
Lemma Cpred_succ_Z_ind : forall P : Z -> CProp,
P 0%Z -> (forall n : Z, P n -> P (n + 1)%Z) ->
(forall n : Z, P n -> P (n - 1)%Z) -> forall z : Z, P z.
Proof.
intros P H H0 H1 z.
apply Cnats_Z_ind.
intro n.
elim n.
exact H.
intros n0 H2.
replace (S n0:Z) with (n0 + 1)%Z.
apply H0.
assumption.
rewrite Znat.inj_S.
reflexivity.
intro n.
elim n.
exact H.
intros n0 H2.
replace (- S n0)%Z with (- n0 - 1)%Z.
apply H1.
assumption.
rewrite Znat.inj_S.
unfold Z.succ in |- *.
rewrite Zopp_plus_distr.
reflexivity.
Qed.
Lemma not_r_sum_rec : forall (A B S : Set) (l r : S), Not B -> forall H : A + B,
sum_rec (fun _ : A + B => S) (fun x : A => l) (fun x : B => r) H = l.
Proof.
intros A B S l r H H0. elim H0.
intro a. reflexivity.
intro b. elim H. assumption.
Qed.
Lemma not_l_sum_rec : forall (A B S : Set) (l r : S), Not A -> forall H : A + B,
sum_rec (fun _ : A + B => S) (fun x : A => l) (fun x : B => r) H = r.
Proof.
intros A B S l r H H0. elim H0.
intro a. elim H. assumption.
intros. reflexivity.
Qed.
(**
%\begin{convention}%
Let [M:Type].
%\end{convention}%
*)
Variable M : Type.
Lemma member_app :
forall (x : M) (l k : (list M)),
(Iff (member x (app k l))
((member x k) or (member x l))).
Proof.
induction k; firstorder.
Qed.
End Misc.
(**
** Results about the natural numbers
We now define a class of predicates on a finite subset of natural
numbers that will be important throughout all our work. Essentially,
these are simply setoid predicates, but for clarity we will never
write them in that form but we will single out the preservation of the
setoid equality.
*)
Definition nat_less_n_pred (n : nat) (P : forall i : nat, i < n -> CProp) :=
forall i j : nat, i = j -> forall (H : i < n) (H' : j < n), P i H -> P j H'.
Definition nat_less_n_pred' (n : nat) (P : forall i : nat, i <= n -> CProp) :=
forall i j : nat, i = j -> forall (H : i <= n) (H' : j <= n), P i H -> P j H'.
Arguments nat_less_n_pred [n].
Arguments nat_less_n_pred' [n].
Section Odd_and_Even.
(**
For our work we will many times need to distinguish cases between even or odd numbers.
We begin by proving that this case distinction is decidable.
Next, we prove the usual results about sums of even and odd numbers:
*)
Lemma even_plus_n_n : forall n : nat, even (n + n).
Proof.
intro n; induction n as [| n Hrecn].
auto with arith.
replace (S n + S n) with (S (S (n + n))).
apply even_S; apply odd_S; apply Hrecn.
rewrite plus_n_Sm; simpl in |- *; auto.
Qed.
Lemma even_or_odd_plus : forall k : nat, {j : nat & {k = j + j} + {k = S (j + j)}}.
Proof.
intro k.
elim (even_odd_dec k); intro H.
elim (even_2n k H); intros j Hj; exists j; auto.
elim (odd_S2n k H); intros j Hj; exists j; auto.
Qed.
(** Finally, we prove that an arbitrary natural number can be written in some canonical way.
*)
Lemma even_or_odd_plus_gt : forall i j : nat,
i <= j -> {k : nat & {j = i + (k + k)} + {j = i + S (k + k)}}.
Proof.
intros i j H.
elim (even_or_odd_plus (j - i)).
intros k Hk.
elim Hk; intro H0.
exists k; left; rewrite <- H0; auto with arith.
exists k; right; rewrite <- H0; auto with arith.
Qed.
End Odd_and_Even.
Hint Resolve even_plus_n_n: arith.
Hint Resolve toCle: core.
Section Natural_Numbers.
(**
** Algebraic Properties
We now present a series of trivial things proved with [Lia] that are
stated as lemmas to make proofs shorter and to aid in auxiliary
definitions. Giving a name to these results allows us to use them in
definitions keeping conciseness.
*)
Lemma Clt_le_weak : forall i j : nat, Clt i j -> Cle i j.
Proof.
intros.
apply toCle; apply lt_le_weak; apply Clt_to; assumption.
Qed.
Lemma lt_5 : forall i n : nat, i < n -> pred i < n.
Proof.
intros; apply le_lt_trans with (pred n).
apply le_pred; auto with arith.
apply lt_pred_n_n; apply le_lt_trans with i; auto with arith.
Qed.
Lemma lt_8 : forall m n : nat, m < pred n -> m < n.
Proof.
intros; apply lt_le_trans with (pred n); auto with arith.
Qed.
Lemma pred_lt : forall m n : nat, m < pred n -> S m < n.
Proof.
intros; apply le_lt_trans with (pred n); auto with arith.
apply lt_pred_n_n; apply le_lt_trans with m.
auto with arith.
apply lt_le_trans with (pred n); auto with arith.
Qed.
Lemma lt_10 : forall i m n : nat,
0 < i -> i < pred (m + n) -> pred i < pred m + pred n.
Proof.
intros; lia.
Qed.
Lemma lt_pred' : forall m n : nat, 0 < m -> m < n -> pred m < pred n.
Proof.
intros m n H H0; red in |- *.
destruct n.
inversion H0.
rewrite <- (S_pred m 0); auto.
simpl in |- *.
auto with arith.
Qed.
Lemma le_1 : forall m n : nat, Cle m n -> pred m <= n.
Proof.
intros.
cut (m <= n); [ intro | apply Cle_to; assumption ].
apply le_trans with (pred n); auto with arith.
apply le_pred; auto.
Qed.
Lemma le_2 : forall i j : nat, i < j -> i <= pred j.
Proof.
intros; lia.
Qed.
Lemma plus_eq_one_imp_eq_zero : forall m n : nat,
m + n <= 1 -> {m = 0} + {n = 0}.
Proof.
intros m n H.
elim (le_lt_dec m 0); intro.
left; auto with arith.
right; lia.
Qed.
Lemma not_not_lt : forall i j : nat, ~ ~ i < j -> i < j.
Proof.
intros; lia.
Qed.
Lemma plus_pred_pred_plus :
forall i j k,
k <= pred i + pred j ->
k <= pred (i + j).
Proof.
intros; lia.
Qed.
(** We now prove some properties of functions on the natural numbers.
%\begin{convention}% Let [H:nat->nat].
%\end{convention}%
*)
Variable h : nat -> nat.
(**
First we characterize monotonicity by a local condition: if [h(n) < h(n+1)]
for every natural number [n] then [h] is monotonous. An analogous result
holds for weak monotonicity.
*)
Lemma nat_local_mon_imp_mon :
(forall i : nat, h i < h (S i)) ->
forall i j : nat, i < j -> h i < h j.
Proof.
intros H i j H0.
induction j as [| j Hrecj].
elimtype False; lia.
cut (i <= j); [ intro H1 | auto with arith ].
elim (le_lt_eq_dec _ _ H1); intro H2.
cut (h i < h j); [ intro | apply Hrecj; assumption ].
cut (h j < h (S j)); [ intro | apply H ].
apply lt_trans with (h j); auto.
rewrite H2; apply H.
Qed.
Lemma nat_local_mon_imp_mon_le :
(forall i : nat, h i <= h (S i)) ->
forall i j : nat, i <= j -> h i <= h j.
Proof.
intros H i j H0.
induction j as [| j Hrecj].
cut (i = 0); [ intro H1 | auto with arith ].
rewrite H1; apply le_n.
elim (le_lt_eq_dec _ _ H0); intro H1.
cut (h i <= h j); [ intro | apply Hrecj; auto with arith ].
cut (h j <= h (S j)); [ intro | apply H ].
apply le_trans with (h j); auto.
rewrite H1; apply le_n.
Qed.
(** A strictly increasing function is injective: *)
Lemma nat_mon_imp_inj : (forall i j : nat, i < j -> h i < h j) ->
forall i j : nat, h i = h j -> i = j.
Proof.
intros H i j H0.
cut (~ i <> j); [ lia | intro H1 ].
cut (i < j \/ j < i); [ intro H2 | lia ].
inversion_clear H2.
cut (h i < h j); [ rewrite H0; apply lt_irrefl | apply H; assumption ].
cut (h j < h i); [ rewrite H0; apply lt_irrefl | apply H; assumption ].
Qed.
(** And (not completely trivial) a function that preserves [lt] also preserves [le]. *)
Lemma nat_mon_imp_mon' : (forall i j : nat, i < j -> h i < h j) ->
forall i j : nat, i <= j -> h i <= h j.
Proof.
intros H i j H0.
elim (le_lt_eq_dec _ _ H0); intro H1.
apply lt_le_weak; apply H; assumption.
rewrite H1; apply le_n.
Qed.
(**
The last lemmas in this section state that a monotonous function in the
natural numbers completely covers the natural numbers, that is, for every
natural number [n] there is an [i] such that [h(i) <= n<(n+1) <= h(i+1)].
These are useful for integration.
*)
Lemma mon_fun_covers : (forall i j, i < j -> h i < h j) -> h 0 = 0 ->
forall n, {k : nat | S n <= h k} -> {i : nat | h i <= n | S n <= h (S i)}.
Proof.
intros H H0 n H1.
elim H1; intros k Hk.
induction k as [| k Hreck].
exists 0.
rewrite H0; auto with arith.
cut (h 0 < h 1); [ intro; apply le_trans with (h 0); auto with arith | apply H; apply lt_n_Sn ].
cut (h k < h (S k)); [ intro H2 | apply H; apply lt_n_Sn ].
elim (le_lt_dec (S n) (h k)); intro H3.
elim (Hreck H3); intros i Hi.
exists i; assumption.
exists k; auto with arith.
Qed.
Lemma weird_mon_covers : forall n (f : nat -> nat), (forall i, f i < n -> f i < f (S i)) ->
{m : nat | n <= f m | forall i, i < m -> f i < n}.
Proof.
intros; induction n as [| n Hrecn].
exists 0.
auto with arith.
intros; inversion H0.
elim Hrecn.
2: auto.
intros m Hm Hm'.
elim (le_lt_eq_dec _ _ Hm); intro.
exists m.
assumption.
auto with arith.
exists (S m).
apply le_lt_trans with (f m).
rewrite b; auto with arith.
apply H.
rewrite b; apply lt_n_Sn.
intros.
elim (le_lt_eq_dec _ _ H0); intro.
auto with arith.
cut (i = m); [ intro | auto ].
rewrite b; rewrite <- H1.
apply lt_n_Sn.
Qed.
End Natural_Numbers.
(**
Useful for the Fundamental Theorem of Algebra.
*)
Lemma kseq_prop :
forall (k : nat -> nat) (n : nat),
(forall i : nat, 1 <= k i /\ k i <= n) ->
(forall i : nat, k (S i) <= k i) ->
{j : nat | S j < 2 * n /\ k j = k (S j) /\ k (S j) = k (S (S j))}.
Proof.
intros k n.
generalize k; clear k.
induction n as [| n Hrecn]; intros k H H0.
elim (H 0); intros H1 H2.
generalize (le_trans _ _ _ H1 H2); intro H3.
elimtype False.
inversion H3.
elim (eq_nat_dec (k 0) (k 2)).
intro H1.
exists 0.
cut (k 0 = k 1).
intro H2.
repeat split.
lia.
assumption.
rewrite <- H1.
auto.
apply le_antisym.
rewrite H1.
apply H0.
apply H0.
intro H1.
elim (Hrecn (fun m : nat => k (S (S m)))).
3: intro; apply H0.
intros m Hm.
exists (S (S m)); lia.
intro i.
split.
elim (H (S (S i))); auto.
elim (lt_eq_lt_dec (k 0) (k 2)); intro H2.
elim H2; intro H3.
generalize (H0 0); intro H4.
generalize (H0 1); intro H5.
lia.
tauto.
generalize (H 0); intro H3.
elim H3; intros H4 H5.
generalize (lt_le_trans _ _ _ H2 H5); intro H6.
cut (k 2 <= n).
2: lia.
intro H7.
induction i as [| i Hreci].
assumption.
apply le_trans with (k (S (S i))); auto.
Qed.
Section Predicates_to_CProp.
(**
** Logical Properties
This section contains lemmas that aid in logical reasoning with
natural numbers. First, we present some principles of induction, both
for [CProp]- and [Prop]-valued predicates. We begin by presenting the
results for [CProp]-valued predicates:
*)
Lemma even_induction :
forall P : nat -> CProp,
P 0 ->
(forall n, even n -> P n -> P (S (S n))) ->
forall n, even n -> P n.
Proof.
intros P H H0 n.
pattern n in |- *; apply lt_wf_rect.
clear n.
intros n H1 H2.
induction n as [| n Hrecn].
auto.
induction n as [| n Hrecn0].
elimtype False; inversion H2; inversion H4.
apply H0.
inversion H2; inversion H4; auto.
apply H1.
auto with arith.
inversion H2; inversion H4; auto.
Qed.
Lemma odd_induction :
forall P : nat -> CProp,
P 1 ->
(forall n, odd n -> P n -> P (S (S n))) ->
forall n, odd n -> P n.
Proof.
intros P H H0 n; case n.
intro H1; elimtype False; inversion H1.
clear n; intros n H1.
pattern n in |- *; apply even_induction; auto.
intros n0 H2 H3; auto with arith.
inversion H1; auto.
Qed.
Lemma four_induction :
forall P : nat -> CProp,
P 0 -> P 1 -> P 2 -> P 3 ->
(forall n, P n -> P (S (S (S (S n))))) ->
forall n, P n.
Proof.
intros.
apply lt_wf_rect.
intro m.
case m; auto.
clear m; intro m.
case m; auto.
clear m; intro m.
case m; auto.
clear m; intro m.
case m; auto with arith.
Qed.
Lemma nat_complete_double_induction : forall P : nat -> nat -> CProp,
(forall m n, (forall m' n', m' < m -> n' < n -> P m' n') -> P m n) -> forall m n, P m n.
Proof.
intros P H m.
pattern m in |- *; apply lt_wf_rect; auto with arith.
Qed.
Lemma odd_double_ind : forall P : nat -> CProp, (forall n, odd n -> P n) ->
(forall n, 0 < n -> P n -> P (double n)) -> forall n, 0 < n -> P n.
Proof.
cut (forall n : nat, 0 < double n -> 0 < n). intro.
intro. intro H0. intro H1. intro n.
pattern n in |- *.
apply lt_wf_rect. intros n0 H2 H3.
generalize (even_odd_dec n0). intro H4. elim H4.
intro.
rewrite (even_double n0).
apply H1.
apply H.
rewrite <- (even_double n0). assumption.
assumption.
apply H2.
apply lt_div2. assumption.
rewrite (even_double n0) in H3.
apply H. assumption.
assumption.
assumption.
exact (H0 n0).
unfold double in |- *. intros.
case (zerop n). intro.
absurd (0 < n + n).
rewrite e. auto with arith.
assumption.
intro. assumption.
Qed.
(** For subsetoid predicates in the natural numbers we can eliminate
disjunction (and existential quantification) as follows.
*)
Lemma finite_or_elim :
forall (n : nat) (P Q : forall i, i <= n -> CProp),
nat_less_n_pred' P ->
nat_less_n_pred' Q ->
(forall i H, P i H or Q i H) ->
{m : nat | {Hm : m <= n | P m Hm}} or (forall i H, Q i H).
Proof.
intro n; induction n as [| n Hrecn].
intros P Q HP HQ H.
elim (H _ (le_n 0)); intro H0.
left; exists 0; exists (le_n 0); assumption.
right; intros i H1.
apply HQ with (H := le_n 0); auto with arith.
intros P Q H H0 H1.
elim (H1 _ (le_n (S n))); intro H2.
left; exists (S n); exists (le_n (S n)); assumption.
set (P' := fun (i : nat) (H : i <= n) => P i (le_S _ _ H)) in *.
set (Q' := fun (i : nat) (H : i <= n) => Q i (le_S _ _ H)) in *.
cut ({m : nat | {Hm : m <= n | P' m Hm}} or (forall (i : nat) (H : i <= n), Q' i H)).
intro H3; elim H3; intro H4.
left.
elim H4; intros m Hm; elim Hm; clear H4 Hm; intros Hm Hm'.
exists m.
unfold P' in Hm'.
exists (le_S _ _ Hm).
eapply H with (i := m); [ lia | apply Hm' ].
right.
intros i H5.
unfold Q' in H4.
elim (le_lt_eq_dec _ _ H5); intro H6.
cut (i <= n); [ intro | auto with arith ].
eapply H0 with (i := i); [ auto with arith | apply (H4 i H7) ].
eapply H0 with (i := S n); [ auto with arith | apply H2 ].
apply Hrecn.
intro i; intros j H3 H4 H5 H6.
unfold P' in |- *.
exact (H _ _ H3 _ _ H6).
intro i; intros j H3 H4 H5 H6.
unfold Q' in |- *.
exact (H0 _ _ H3 _ _ H6).
intros i H3.
unfold P', Q' in |- *; apply H1.
Qed.
Lemma str_finite_or_elim :
forall (n : nat) (P Q : forall i, i <= n -> CProp),
nat_less_n_pred' P ->
nat_less_n_pred' Q ->
(forall i H, P i H or Q i H) ->
{j : nat | {Hj : j <= n | P j Hj and (forall j' Hj', j' < j -> Q j' Hj')}}
or (forall i H, Q i H).
Proof.
intro n; induction n as [| n Hrecn].
intros P Q H H0 H1.
elim (H1 0 (le_n 0)); intro HPQ.
left.
exists 0; exists (le_n 0).
split.
apply H with (H := le_n 0); auto.
intros; elimtype False; inversion H2.
right; intros.
apply H0 with (H := le_n 0); auto with arith.
intros P Q H H0 H1.
set (P' := fun (i : nat) (H : i <= n) => P i (le_S _ _ H)) in *.
set (Q' := fun (i : nat) (H : i <= n) => Q i (le_S _ _ H)) in *.
elim (Hrecn P' Q').
intro H2.
left.
elim H2; intros m Hm; elim Hm; clear H2 Hm; intros Hm Hm'.
exists m.
unfold P' in Hm'.
exists (le_S _ _ Hm).
elim Hm'; clear Hm'; intros Hm' Hj.
split.
eapply H with (i := m); [ auto with arith | apply Hm' ].
unfold Q' in Hj; intros j' Hj' H2.
cut (j' <= n); [ intro H4 | apply le_trans with m; auto with arith ].
apply H0 with (H := le_S _ _ H4); [ auto | apply Hj; assumption ].
elim (H1 (S n) (le_n (S n))); intro H1'.
intro H2.
left; exists (S n); exists (le_n (S n)); split.
assumption.
intros j' Hj' H3; unfold Q' in H1'.
cut (j' <= n); [ intro H4 | auto with arith ].
unfold Q' in H2.
apply H0 with (H := le_S _ _ H4); auto.
intro H2.
right; intros i H3.
unfold Q' in H1'.
elim (le_lt_eq_dec _ _ H3); intro H4.
cut (i <= n); [ intro H5 | auto with arith ].
unfold Q' in H2.
apply H0 with (H := le_S _ _ H5); auto.
apply H0 with (H := le_n (S n)); auto.
intro i; intros j H2 H3 H4 H5.
unfold P' in |- *.
exact (H _ _ H2 _ _ H5).
intro i; intros j H2 H3 H4 H5.
unfold Q' in |- *.
exact (H0 _ _ H2 _ _ H5).
intros i H2.
unfold P', Q' in |- *.
apply H1.
Qed.
End Predicates_to_CProp.
Section Predicates_to_Prop.
(** Finally, analogous results for [Prop]-valued predicates are presented for
completeness's sake.
*)
Lemma even_ind : forall P : nat -> Prop,
P 0 -> (forall n, even n -> P n -> P (S (S n))) -> forall n, even n -> P n.
Proof.
intros P H H0 n.
pattern n in |- *; apply lt_wf_ind.
clear n.
intros n H1 H2.
induction n as [| n Hrecn].
auto.
induction n as [| n Hrecn0].
elimtype False; inversion H2; inversion H4.
apply H0.
inversion H2; inversion H4; auto.
apply H1.
auto with arith.
inversion H2; inversion H4; auto.
Qed.
Lemma odd_ind : forall P : nat -> Prop,
P 1 -> (forall n, P n -> P (S (S n))) -> forall n, odd n -> P n.
Proof.
intros P H H0 n; case n.
intro H1; elimtype False; inversion H1.
clear n; intros n H1.
pattern n in |- *; apply even_ind; auto.
inversion H1; auto.
Qed.
Lemma nat_complete_double_ind :
forall P : nat -> nat -> Prop,
(forall m n, (forall m' n', m' < m -> n' < n -> P m' n') -> P m n) ->
forall m n, P m n.
Proof.
intros P H m.
pattern m in |- *; apply lt_wf_ind; auto.
Qed.
Lemma four_ind :
forall P : nat -> Prop,
P 0 -> P 1 -> P 2 -> P 3 ->
(forall n, P n -> P (S (S (S (S n))))) -> forall n, P n.
Proof.
intros.
apply lt_wf_ind.
intro m.
case m; auto.
clear m; intro m.
case m; auto.
clear m; intro m.
case m; auto.
clear m; intro m.
case m; auto with arith.
Qed.
End Predicates_to_Prop.
(**
** Integers
Similar results for integers.
*)
(* begin hide *)
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
(* end hide *)
Definition Zlts (x y : Z) := eq (A:=Datatypes.comparison) (x ?= y)%Z Datatypes.Lt.
Lemma toCProp_Zlt : forall x y : Z, (x < y)%Z -> Zlts x y.
Proof.
intros x y H.
unfold Zlts in |- *.
unfold Z.lt in H.
auto.
Qed.
Lemma CZlt_to : forall x y : Z, Zlts x y -> (x < y)%Z.
Proof.
intros x y H.
unfold Z.lt in |- *.
inversion H.
auto.
Qed.
Lemma Zsgn_1 : forall x : Z, {Z.sgn x = 0%Z} + {Z.sgn x = 1%Z} + {Z.sgn x = (-1)%Z}.
Proof.
intro x.
case x.
left.
left.
unfold Z.sgn in |- *.
reflexivity.
intro p.
simpl in |- *.
left.
right.
reflexivity.
intro p.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Z.sgn x = 0%Z -> x = 0%Z.
Proof.
intro x.
case x.
intro H.
reflexivity.
intros p H.
inversion H.
intros p H.
inversion H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Z.sgn x <> 0%Z.
Proof.
intro x.
case x.
intro H.
elim H.
reflexivity.
intros p H.
simpl in |- *.
discriminate.
intros p H.
simpl in |- *.
discriminate.
Qed.
(** The following have unusual names, in line with the series of lemmata in
fast_integers.v.
*)
Lemma ZL4' : forall y : positive, {h : nat | nat_of_P y = S h}.
Proof.
simple induction y; [ intros p H; elim H; intros x H1; exists (S x + S x);
unfold nat_of_P in |- *; simpl in |- *; rewrite ZL0;
rewrite Pmult_nat_r_plus_morphism; unfold nat_of_P in H1; rewrite H1; auto with arith
| intros p H1; elim H1; intros x H2; exists (x + S x);
unfold nat_of_P in |- *; simpl in |- *; rewrite ZL0;
rewrite Pmult_nat_r_plus_morphism; unfold nat_of_P in H2; rewrite H2; auto with arith
| exists 0; auto with arith ].
Qed.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p.
Proof.
intro p.
elim (ZL4 p).
intros x H0.
rewrite H0.
unfold Z_of_nat in |- *.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro H1.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Pos.pred (Pos.succ p) = Pos.pred (P_of_succ_nat (S x))).
intro H2.
rewrite Pos.pred_succ in H2.
simpl in H2.
rewrite Pos.pred_succ in H2.
auto.
apply f_equal with (A := positive) (B := positive) (f := Pos.pred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Z.sgn a * Z.abs_nat a)%Z.
Proof.
intro a.
case a.
simpl in |- *.
reflexivity.
intro p.
unfold Z.sgn in |- *.
unfold Z.abs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intro p.
unfold Z.sgn in |- *.
unfold Z.abs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 : forall a b x y : Z, x <> 0%Z -> y <> 0%Z ->
(Z.sgn a * x)%Z = (Z.sgn b * y)%Z -> (Z.sgn a * y)%Z = (Z.sgn b * x)%Z.
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro p.
unfold Z.sgn in |- *.
intro H1.
rewrite Zmult_1_l in H1.
simpl in H1.
elim H0.
auto.
intro p.
unfold Z.sgn in |- *.
intro H1.
elim H0.
apply Z.opp_inj.
simpl in |- *.
transitivity (-1 * y)%Z; auto.
intro p.
unfold Z.sgn at 1 in |- *.
unfold Z.sgn at 2 in |- *.
intro H1.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Z.sgn b * (Z.sgn b * y))%Z.
case (Zsgn_1 b).
intro H2.
case H2.
intro H3.
elim H.
rewrite H3 in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro H3.
rewrite H3.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro H2.
rewrite H2.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro p.
unfold Z.sgn at 1 in |- *.
unfold Z.sgn at 2 in |- *.
intro H1.
transitivity (Z.sgn b * (-1 * (Z.sgn b * y)))%Z.
case (Zsgn_1 b).
intro H2.
case H2.
intro H3.
elim H.
apply Z.opp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Z.opp in |- *.
rewrite H3 in H1.
transitivity (0 * y)%Z; auto.
intro H3.
rewrite H3.
ring.
intro H2.
rewrite H2.
ring.
rewrite <- H1.
ring.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z.
Proof.
intros m n.
apply Z.lt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro H.
cut (0 < Z_of_nat n + 1)%Z.
intro H0.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
auto.
apply Zlt_reg_mult_l; auto.
change (0 < Z.succ (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Z.lt_gt.
change (0 < Z.succ (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m.
Proof.
intros m H.
symmetry in |- *.
apply S_pred with 0.
lia.
Qed.
Lemma absolu_1 : forall x : Z, Z.abs_nat x = 0 -> x = 0%Z.
Proof.
intros x H.
case (dec_eq x 0).
auto.
intro H0.
apply False_ind.
ElimCompare x 0%Z.
intro H2.
apply H0.
elim (Zcompare_Eq_iff_eq x 0%nat).
intros H3 H4.
auto.
intro H2.
cut (exists h : nat, Z.abs_nat x = S h).
intro H3.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
set (H3 := Z.lt_gt _ _ H2) in *.
elim (Zcompare_Gt_spec _ _ H3).
intros x0 H5.
cut (exists q : positive, x = Zneg q).
intro H6.
case H6.
intros x1 H7.
rewrite H7.
unfold Z.abs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro H6.
exists x0.
assumption.
rewrite <- (Z.opp_involutive x).
exact (f_equal Z.opp H5).
intro H2.
cut (exists h : nat, Z.abs_nat x = S h).
intro H3.
case H3.
rewrite H.
exact O_S.
elim (Zcompare_Gt_spec _ _ H2).
simpl in |- *.
rewrite Zplus_0_r.
intros x0 H4.
rewrite H4.
unfold Z.abs_nat in |- *.
generalize x0.
exact ZL4.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Z.abs_nat x <> 0.
Proof.
intros x H.
intro H0.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l : forall a x y : Z,
(a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z.
Proof.
intros a x y H H0.
case (dec_eq x y).
intro H1.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro H1.
case (not_Zeq x y H1).
trivial.
intro H2.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l : forall a x y : Z,
(a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z.
Proof.
intros a x y H H0.
cut (- a < - (0))%Z.
rewrite <- (Z.opp_involutive a) in H.
rewrite <- (Z.opp_involutive 0) in H.
simpl in |- *.
intro H1.
rewrite <- (Z.opp_involutive x).
rewrite <- (Z.opp_involutive y).
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zopp_mult_distr_l_reverse.
rewrite Zopp_mult_distr_l_reverse.
apply Zlt_opp.
rewrite <- Zopp_mult_distr_r.
rewrite <- Zopp_mult_distr_r.
apply Z.gt_lt.
apply Zlt_opp.
apply Z.gt_lt.
assumption.
lia.
Qed.
Lemma Zmult_Sm_Sn : forall m n : Z,
((m + 1) * (n + 1))%Z = (m * n + (m + n) + 1)%Z.
Proof.
intros.
ring.
Qed.
Definition CForall {A: Type} (P: A -> Type): list A -> Type :=
fold_right (fun x => prod (P x)) True.
Definition CForall_prop {A: Type} (P: A -> Prop) (l: list A):
(forall x, In x l -> P x) IFF CForall P l.
Proof with firstorder. induction l... subst... Qed.
Lemma CForall_indexed {A} (P: A -> Type) (l: list A): CForall P l ->
forall i (d: A), (i < length l)%nat -> P (nth i l d).
Proof.
intros X i.
revert l X.
induction i; destruct l; simpl in *; intuition; exfalso; inversion H.
Qed.
Lemma CForall_map {A B} (P: B -> Type) (f: A -> B) (l: list A):
CForall P (map f l) IFF CForall (fun x => P (f x)) l.
Proof. induction l; firstorder. Qed.
Lemma CForall_weak {A} (P Q: A -> Type):
(forall x, P x -> Q x) ->
(forall l, CForall P l -> CForall Q l).
Proof. induction l; firstorder. Qed.
Fixpoint CNoDup {T: Type} (R: T -> T -> Type) (l: list T): Type :=
match l with
| nil => True
| h :: t => prod (CNoDup R t) (CForall (R h) t)
end.
Lemma CNoDup_weak {A: Type} (Ra Rb: A -> A -> Type) (l: list A):
(forall x y, Ra x y -> Rb x y) ->
CNoDup Ra l -> CNoDup Rb l.
Proof with auto.
induction l... firstorder.
apply CForall_weak with (Ra a)...
Qed.
Lemma CNoDup_indexed {T} (R: T -> T -> Type) (Rsym: Csymmetric _ R) (l: list T) (d: T): CNoDup R l ->
forall i j, (i < length l)%nat -> (j < length l)%nat -> i <> j -> R (nth i l d) (nth j l d).
Proof with intuition.
induction l; simpl...
exfalso...
destruct i.
destruct j...
apply (CForall_indexed (R a) l)...
destruct j...
apply Rsym.
apply (CForall_indexed (R a) l)...
Qed.
Lemma CNoDup_map {A B: Type} (R: B -> B -> Type) (f: A -> B):
forall l, CNoDup (fun x y => R (f x) (f y)) l IFF CNoDup R (map f l).
Proof with auto; intuition.
induction l; simpl...
split; intro; split.
apply IHl, X.
apply CForall_map...
apply IHl, X.
apply CForall_map...
Qed.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/07/2016 09:24:55 AM
// Design Name:
// Module Name: Deslinealizador
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DESLINEALIZADOR#(parameter P = 32)(
input wire CLK, //system clock
input wire [P-1:0] T, //VALOR DEL ARGUMENTO DEL EXPONENCIAL QUE SE DESEA CALCULAR
input wire RST_EX, //system reset
input wire Begin_FSM_EX, //INICIAL EL CALCULO
output wire ACK_EX, //INDICA QUE EL CALCULO FUE REALIZADO
output wire ACK_SUMX,
output wire ACK_SUMY,
output wire ACK_SUMZ,
output wire O_FX, //BANDERA DE OVER FLOW X
output wire O_FY, //BANDERA DE OVER FLOW Y
output wire O_FZ, //BANDERA DE OVER FLOW Z
output wire U_FX, //BANDERA DE UNDER FLOW X
output wire U_FY, //BANDERA DE UNDER FLOW Y
output wire U_FZ, //BANDERA DE UNDER FLOW Z
output wire [P-1:0] RESULT //RESULTADO FINAL
);
wire [4:0] CONT_ITERA;
wire RST;
wire MS_1;
wire EN_REG3;
//wire EN_REGMult;
wire ADD_SUBT;
wire Begin_SUMX;
wire Begin_SUMY;
wire Begin_SUMZ;
wire EN_REG1X;
wire EN_REG1Y;
wire EN_REG1Z;
wire MS_2;
wire EN_REG2;
wire CLK_CDIR;
wire EN_REG2XYZ;
// wire ACK_SUMX;
// wire ACK_SUMY;
// wire ACK_SUMZ;
// wire ACK_MULTX,
// wire ACK_MULTY,
wire EN_MS1;
wire EN_MS2;
wire EN_ADDSUBT;
wire MS_1_reg;
wire MS_2_reg;
wire ADD_SUBT_reg;
assign BeginSUMX = Begin_SUMX;
assign BeginSUMY = Begin_SUMY;
assign BeginSUMZ = Begin_SUMZ;
Coprocesador_CORDIC C_CORDIC_EX (
.T(T),
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST),
.MS_1(MS_1_reg),
.EN_REG3(EN_REG3),
//.EN_REGMult(EN_REGMult),
.ADD_SUBT(ADD_SUBT_reg),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.EN_REG1X(EN_REG1X),
.EN_REG1Y(EN_REG1Y),
.EN_REG1Z(EN_REG1Z),
.MS_2(MS_2_reg),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_SUMX(ACK_SUMX),
.ACK_SUMY(ACK_SUMY),
.ACK_SUMZ(ACK_SUMZ),
.O_FX(O_FX),
.U_FX(U_FX),
.O_FY(O_FY),
.U_FY(U_FY),
.O_FZ(O_FZ),
.U_FZ(U_FZ),
.RESULT(RESULT),
.CONT_ITERA(CONT_ITERA)
);
FF_D #(.P(1)) REG_ADDSUBTL( //#(.P(1))
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_ADDSUBT), //ENABLE
.D(ADD_SUBT), //ENTRADA
.Q(ADD_SUBT_reg) //SALIDA
);
FF_D #(.P(1)) REG_MS_1(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS1), //ENABLE
.D(MS_1), //ENTRADA
.Q(MS_1_reg) //SALIDA
);
FF_D #(.P(1)) REG_MS_2(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS2), //ENABLE
.D(MS_2), //ENTRADA
.Q(MS_2_reg) //SALIDA
);
FSM_C_CORDIC M_E_EX (
.CLK(CLK), //RELOJ DEL SISTEMA
.RST_EX(RST_EX), //system reset
.ACK_ADD_SUBTX(ACK_SUMX),
.ACK_ADD_SUBTY(ACK_SUMY),
.ACK_ADD_SUBTZ(ACK_SUMZ),
.Begin_FSM_EX(Begin_FSM_EX),
.CONT_ITER(CONT_ITERA),
.RST(RST),
.MS_1(MS_1),
.EN_REG3(EN_REG3),
//.EN_REGMult(EN_REGMult),
.ADD_SUBT(ADD_SUBT),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.EN_REG1X(EN_REG1X),
.EN_REG1Y(EN_REG1Y),
.EN_REG1Z(EN_REG1Z),
.MS_2(MS_2),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_EX(ACK_EX),
.EN_ADDSUBT(EN_ADDSUBT),
.EN_MS1(EN_MS1),
.EN_MS2(EN_MS2)
);
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_tck the_TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_sysclk the_TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// TimeHoldOver_Qsys_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
module progmem (
// Closk & reset
input wire clk,
input wire rstn,
// PicoRV32 bus interface
input wire valid,
output wire ready,
input wire [31:0] addr,
output wire [31:0] rdata
);
// ============================================================================
localparam MEM_SIZE_BITS = 10; // In 32-bit words
localparam MEM_SIZE = 1 << MEM_SIZE_BITS;
localparam MEM_ADDR_MASK = 32'h0010_0000;
// ============================================================================
wire [MEM_SIZE_BITS-1:0] mem_addr;
reg [ 31:0] mem_data;
reg [ 31:0] mem [0:MEM_SIZE];
initial begin
mem['h0000] <= 32'h00000093;
mem['h0001] <= 32'h00000193;
mem['h0002] <= 32'h00000213;
mem['h0003] <= 32'h00000293;
mem['h0004] <= 32'h00000313;
mem['h0005] <= 32'h00000393;
mem['h0006] <= 32'h00000413;
mem['h0007] <= 32'h00000493;
mem['h0008] <= 32'h00000513;
mem['h0009] <= 32'h00000593;
mem['h000A] <= 32'h00000613;
mem['h000B] <= 32'h00000693;
mem['h000C] <= 32'h00000713;
mem['h000D] <= 32'h00000793;
mem['h000E] <= 32'h00000813;
mem['h000F] <= 32'h00000893;
mem['h0010] <= 32'h00000913;
mem['h0011] <= 32'h00000993;
mem['h0012] <= 32'h00000A13;
mem['h0013] <= 32'h00000A93;
mem['h0014] <= 32'h00000B13;
mem['h0015] <= 32'h00000B93;
mem['h0016] <= 32'h00000C13;
mem['h0017] <= 32'h00000C93;
mem['h0018] <= 32'h00000D13;
mem['h0019] <= 32'h00000D93;
mem['h001A] <= 32'h00000E13;
mem['h001B] <= 32'h00000E93;
mem['h001C] <= 32'h00000F13;
mem['h001D] <= 32'h00000F93;
mem['h001E] <= 32'h03000537;
mem['h001F] <= 32'h00100593;
mem['h0020] <= 32'h00B52023;
mem['h0021] <= 32'h00000513;
mem['h0022] <= 32'h00A52023;
mem['h0023] <= 32'h00450513;
mem['h0024] <= 32'hFE254CE3;
mem['h0025] <= 32'h03000537;
mem['h0026] <= 32'h00300593;
mem['h0027] <= 32'h00B52023;
mem['h0028] <= 32'h00001517;
mem['h0029] <= 32'hB4050513;
mem['h002A] <= 32'h00000593;
mem['h002B] <= 32'h00000613;
mem['h002C] <= 32'h00C5DC63;
mem['h002D] <= 32'h00052683;
mem['h002E] <= 32'h00D5A023;
mem['h002F] <= 32'h00450513;
mem['h0030] <= 32'h00458593;
mem['h0031] <= 32'hFEC5C8E3;
mem['h0032] <= 32'h03000537;
mem['h0033] <= 32'h00700593;
mem['h0034] <= 32'h00B52023;
mem['h0035] <= 32'h00000513;
mem['h0036] <= 32'h00000593;
mem['h0037] <= 32'h00B55863;
mem['h0038] <= 32'h00052023;
mem['h0039] <= 32'h00450513;
mem['h003A] <= 32'hFEB54CE3;
mem['h003B] <= 32'h03000537;
mem['h003C] <= 32'h00F00593;
mem['h003D] <= 32'h00B52023;
mem['h003E] <= 32'h015000EF;
mem['h003F] <= 32'h0000006F;
mem['h0040] <= 32'h020002B7;
mem['h0041] <= 32'h12000313;
mem['h0042] <= 32'h00629023;
mem['h0043] <= 32'h000281A3;
mem['h0044] <= 32'h02060863;
mem['h0045] <= 32'h00800F13;
mem['h0046] <= 32'h0FF67393;
mem['h0047] <= 32'h0073DE93;
mem['h0048] <= 32'h01D28023;
mem['h0049] <= 32'h010EEE93;
mem['h004A] <= 32'h01D28023;
mem['h004B] <= 32'h00139393;
mem['h004C] <= 32'h0FF3F393;
mem['h004D] <= 32'hFFFF0F13;
mem['h004E] <= 32'hFE0F12E3;
mem['h004F] <= 32'h00628023;
mem['h0050] <= 32'h04058663;
mem['h0051] <= 32'h00800F13;
mem['h0052] <= 32'h00054383;
mem['h0053] <= 32'h0073DE93;
mem['h0054] <= 32'h01D28023;
mem['h0055] <= 32'h010EEE93;
mem['h0056] <= 32'h01D28023;
mem['h0057] <= 32'h0002CE83;
mem['h0058] <= 32'h002EFE93;
mem['h0059] <= 32'h001EDE93;
mem['h005A] <= 32'h00139393;
mem['h005B] <= 32'h01D3E3B3;
mem['h005C] <= 32'h0FF3F393;
mem['h005D] <= 32'hFFFF0F13;
mem['h005E] <= 32'hFC0F1AE3;
mem['h005F] <= 32'h00750023;
mem['h0060] <= 32'h00150513;
mem['h0061] <= 32'hFFF58593;
mem['h0062] <= 32'hFB9FF06F;
mem['h0063] <= 32'h08000313;
mem['h0064] <= 32'h006281A3;
mem['h0065] <= 32'h00008067;
mem['h0066] <= 32'hFE010113;
mem['h0067] <= 32'h00112E23;
mem['h0068] <= 32'h00812C23;
mem['h0069] <= 32'h02010413;
mem['h006A] <= 32'h00050793;
mem['h006B] <= 32'hFEF407A3;
mem['h006C] <= 32'hFEF44703;
mem['h006D] <= 32'h00A00793;
mem['h006E] <= 32'h00F71663;
mem['h006F] <= 32'h00D00513;
mem['h0070] <= 32'hFD9FF0EF;
mem['h0071] <= 32'h020007B7;
mem['h0072] <= 32'h00878793;
mem['h0073] <= 32'hFEF44703;
mem['h0074] <= 32'h00E7A023;
mem['h0075] <= 32'h00000013;
mem['h0076] <= 32'h01C12083;
mem['h0077] <= 32'h01812403;
mem['h0078] <= 32'h02010113;
mem['h0079] <= 32'h00008067;
mem['h007A] <= 32'hFE010113;
mem['h007B] <= 32'h00112E23;
mem['h007C] <= 32'h00812C23;
mem['h007D] <= 32'h02010413;
mem['h007E] <= 32'hFEA42623;
mem['h007F] <= 32'h01C0006F;
mem['h0080] <= 32'hFEC42783;
mem['h0081] <= 32'h00178713;
mem['h0082] <= 32'hFEE42623;
mem['h0083] <= 32'h0007C783;
mem['h0084] <= 32'h00078513;
mem['h0085] <= 32'hF85FF0EF;
mem['h0086] <= 32'hFEC42783;
mem['h0087] <= 32'h0007C783;
mem['h0088] <= 32'hFE0790E3;
mem['h0089] <= 32'h00000013;
mem['h008A] <= 32'h01C12083;
mem['h008B] <= 32'h01812403;
mem['h008C] <= 32'h02010113;
mem['h008D] <= 32'h00008067;
mem['h008E] <= 32'hFD010113;
mem['h008F] <= 32'h02112623;
mem['h0090] <= 32'h02812423;
mem['h0091] <= 32'h03010413;
mem['h0092] <= 32'hFCA42E23;
mem['h0093] <= 32'hFCB42C23;
mem['h0094] <= 32'h00700793;
mem['h0095] <= 32'hFEF42623;
mem['h0096] <= 32'h06C0006F;
mem['h0097] <= 32'hFEC42783;
mem['h0098] <= 32'h00279793;
mem['h0099] <= 32'hFDC42703;
mem['h009A] <= 32'h00F757B3;
mem['h009B] <= 32'h00F7F713;
mem['h009C] <= 32'h001017B7;
mem['h009D] <= 32'hA8078793;
mem['h009E] <= 32'h00F707B3;
mem['h009F] <= 32'h0007C783;
mem['h00A0] <= 32'hFEF405A3;
mem['h00A1] <= 32'hFEB44703;
mem['h00A2] <= 32'h03000793;
mem['h00A3] <= 32'h00F71863;
mem['h00A4] <= 32'hFEC42703;
mem['h00A5] <= 32'hFD842783;
mem['h00A6] <= 32'h00F75E63;
mem['h00A7] <= 32'hFEB44783;
mem['h00A8] <= 32'h00078513;
mem['h00A9] <= 32'hEF5FF0EF;
mem['h00AA] <= 32'hFEC42783;
mem['h00AB] <= 32'hFCF42C23;
mem['h00AC] <= 32'h0080006F;
mem['h00AD] <= 32'h00000013;
mem['h00AE] <= 32'hFEC42783;
mem['h00AF] <= 32'hFFF78793;
mem['h00B0] <= 32'hFEF42623;
mem['h00B1] <= 32'hFEC42783;
mem['h00B2] <= 32'hF807DAE3;
mem['h00B3] <= 32'h00000013;
mem['h00B4] <= 32'h02C12083;
mem['h00B5] <= 32'h02812403;
mem['h00B6] <= 32'h03010113;
mem['h00B7] <= 32'h00008067;
mem['h00B8] <= 32'hFE010113;
mem['h00B9] <= 32'h00112E23;
mem['h00BA] <= 32'h00812C23;
mem['h00BB] <= 32'h02010413;
mem['h00BC] <= 32'hFEA42623;
mem['h00BD] <= 32'hFEC42703;
mem['h00BE] <= 32'h06300793;
mem['h00BF] <= 32'h00E7FA63;
mem['h00C0] <= 32'h001017B7;
mem['h00C1] <= 32'hA9478513;
mem['h00C2] <= 32'hEE1FF0EF;
mem['h00C3] <= 32'h28C0006F;
mem['h00C4] <= 32'hFEC42703;
mem['h00C5] <= 32'h05900793;
mem['h00C6] <= 32'h00E7FE63;
mem['h00C7] <= 32'h03900513;
mem['h00C8] <= 32'hE79FF0EF;
mem['h00C9] <= 32'hFEC42783;
mem['h00CA] <= 32'hFA678793;
mem['h00CB] <= 32'hFEF42623;
mem['h00CC] <= 32'h1200006F;
mem['h00CD] <= 32'hFEC42703;
mem['h00CE] <= 32'h04F00793;
mem['h00CF] <= 32'h00E7FE63;
mem['h00D0] <= 32'h03800513;
mem['h00D1] <= 32'hE55FF0EF;
mem['h00D2] <= 32'hFEC42783;
mem['h00D3] <= 32'hFB078793;
mem['h00D4] <= 32'hFEF42623;
mem['h00D5] <= 32'h0FC0006F;
mem['h00D6] <= 32'hFEC42703;
mem['h00D7] <= 32'h04500793;
mem['h00D8] <= 32'h00E7FE63;
mem['h00D9] <= 32'h03700513;
mem['h00DA] <= 32'hE31FF0EF;
mem['h00DB] <= 32'hFEC42783;
mem['h00DC] <= 32'hFBA78793;
mem['h00DD] <= 32'hFEF42623;
mem['h00DE] <= 32'h0D80006F;
mem['h00DF] <= 32'hFEC42703;
mem['h00E0] <= 32'h03B00793;
mem['h00E1] <= 32'h00E7FE63;
mem['h00E2] <= 32'h03600513;
mem['h00E3] <= 32'hE0DFF0EF;
mem['h00E4] <= 32'hFEC42783;
mem['h00E5] <= 32'hFC478793;
mem['h00E6] <= 32'hFEF42623;
mem['h00E7] <= 32'h0B40006F;
mem['h00E8] <= 32'hFEC42703;
mem['h00E9] <= 32'h03100793;
mem['h00EA] <= 32'h00E7FE63;
mem['h00EB] <= 32'h03500513;
mem['h00EC] <= 32'hDE9FF0EF;
mem['h00ED] <= 32'hFEC42783;
mem['h00EE] <= 32'hFCE78793;
mem['h00EF] <= 32'hFEF42623;
mem['h00F0] <= 32'h0900006F;
mem['h00F1] <= 32'hFEC42703;
mem['h00F2] <= 32'h02700793;
mem['h00F3] <= 32'h00E7FE63;
mem['h00F4] <= 32'h03400513;
mem['h00F5] <= 32'hDC5FF0EF;
mem['h00F6] <= 32'hFEC42783;
mem['h00F7] <= 32'hFD878793;
mem['h00F8] <= 32'hFEF42623;
mem['h00F9] <= 32'h06C0006F;
mem['h00FA] <= 32'hFEC42703;
mem['h00FB] <= 32'h01D00793;
mem['h00FC] <= 32'h00E7FE63;
mem['h00FD] <= 32'h03300513;
mem['h00FE] <= 32'hDA1FF0EF;
mem['h00FF] <= 32'hFEC42783;
mem['h0100] <= 32'hFE278793;
mem['h0101] <= 32'hFEF42623;
mem['h0102] <= 32'h0480006F;
mem['h0103] <= 32'hFEC42703;
mem['h0104] <= 32'h01300793;
mem['h0105] <= 32'h00E7FE63;
mem['h0106] <= 32'h03200513;
mem['h0107] <= 32'hD7DFF0EF;
mem['h0108] <= 32'hFEC42783;
mem['h0109] <= 32'hFEC78793;
mem['h010A] <= 32'hFEF42623;
mem['h010B] <= 32'h0240006F;
mem['h010C] <= 32'hFEC42703;
mem['h010D] <= 32'h00900793;
mem['h010E] <= 32'h00E7FC63;
mem['h010F] <= 32'h03100513;
mem['h0110] <= 32'hD59FF0EF;
mem['h0111] <= 32'hFEC42783;
mem['h0112] <= 32'hFF678793;
mem['h0113] <= 32'hFEF42623;
mem['h0114] <= 32'hFEC42703;
mem['h0115] <= 32'h00800793;
mem['h0116] <= 32'h00E7FE63;
mem['h0117] <= 32'h03900513;
mem['h0118] <= 32'hD39FF0EF;
mem['h0119] <= 32'hFEC42783;
mem['h011A] <= 32'hFF778793;
mem['h011B] <= 32'hFEF42623;
mem['h011C] <= 32'h1280006F;
mem['h011D] <= 32'hFEC42703;
mem['h011E] <= 32'h00700793;
mem['h011F] <= 32'h00E7FE63;
mem['h0120] <= 32'h03800513;
mem['h0121] <= 32'hD15FF0EF;
mem['h0122] <= 32'hFEC42783;
mem['h0123] <= 32'hFF878793;
mem['h0124] <= 32'hFEF42623;
mem['h0125] <= 32'h1040006F;
mem['h0126] <= 32'hFEC42703;
mem['h0127] <= 32'h00600793;
mem['h0128] <= 32'h00E7FE63;
mem['h0129] <= 32'h03700513;
mem['h012A] <= 32'hCF1FF0EF;
mem['h012B] <= 32'hFEC42783;
mem['h012C] <= 32'hFF978793;
mem['h012D] <= 32'hFEF42623;
mem['h012E] <= 32'h0E00006F;
mem['h012F] <= 32'hFEC42703;
mem['h0130] <= 32'h00500793;
mem['h0131] <= 32'h00E7FE63;
mem['h0132] <= 32'h03600513;
mem['h0133] <= 32'hCCDFF0EF;
mem['h0134] <= 32'hFEC42783;
mem['h0135] <= 32'hFFA78793;
mem['h0136] <= 32'hFEF42623;
mem['h0137] <= 32'h0BC0006F;
mem['h0138] <= 32'hFEC42703;
mem['h0139] <= 32'h00400793;
mem['h013A] <= 32'h00E7FE63;
mem['h013B] <= 32'h03500513;
mem['h013C] <= 32'hCA9FF0EF;
mem['h013D] <= 32'hFEC42783;
mem['h013E] <= 32'hFFB78793;
mem['h013F] <= 32'hFEF42623;
mem['h0140] <= 32'h0980006F;
mem['h0141] <= 32'hFEC42703;
mem['h0142] <= 32'h00300793;
mem['h0143] <= 32'h00E7FE63;
mem['h0144] <= 32'h03400513;
mem['h0145] <= 32'hC85FF0EF;
mem['h0146] <= 32'hFEC42783;
mem['h0147] <= 32'hFFC78793;
mem['h0148] <= 32'hFEF42623;
mem['h0149] <= 32'h0740006F;
mem['h014A] <= 32'hFEC42703;
mem['h014B] <= 32'h00200793;
mem['h014C] <= 32'h00E7FE63;
mem['h014D] <= 32'h03300513;
mem['h014E] <= 32'hC61FF0EF;
mem['h014F] <= 32'hFEC42783;
mem['h0150] <= 32'hFFD78793;
mem['h0151] <= 32'hFEF42623;
mem['h0152] <= 32'h0500006F;
mem['h0153] <= 32'hFEC42703;
mem['h0154] <= 32'h00100793;
mem['h0155] <= 32'h00E7FE63;
mem['h0156] <= 32'h03200513;
mem['h0157] <= 32'hC3DFF0EF;
mem['h0158] <= 32'hFEC42783;
mem['h0159] <= 32'hFFE78793;
mem['h015A] <= 32'hFEF42623;
mem['h015B] <= 32'h02C0006F;
mem['h015C] <= 32'hFEC42783;
mem['h015D] <= 32'h00078E63;
mem['h015E] <= 32'h03100513;
mem['h015F] <= 32'hC1DFF0EF;
mem['h0160] <= 32'hFEC42783;
mem['h0161] <= 32'hFFF78793;
mem['h0162] <= 32'hFEF42623;
mem['h0163] <= 32'h00C0006F;
mem['h0164] <= 32'h03000513;
mem['h0165] <= 32'hC05FF0EF;
mem['h0166] <= 32'h01C12083;
mem['h0167] <= 32'h01812403;
mem['h0168] <= 32'h02010113;
mem['h0169] <= 32'h00008067;
mem['h016A] <= 32'hFD010113;
mem['h016B] <= 32'h02112623;
mem['h016C] <= 32'h02812423;
mem['h016D] <= 32'h03010413;
mem['h016E] <= 32'hFCA42E23;
mem['h016F] <= 32'hFFF00793;
mem['h0170] <= 32'hFEF42623;
mem['h0171] <= 32'hC00027F3;
mem['h0172] <= 32'hFEF42423;
mem['h0173] <= 32'h030007B7;
mem['h0174] <= 32'hFFF00713;
mem['h0175] <= 32'h00E7A023;
mem['h0176] <= 32'hFDC42783;
mem['h0177] <= 32'h08078A63;
mem['h0178] <= 32'hFDC42503;
mem['h0179] <= 32'hC05FF0EF;
mem['h017A] <= 32'h0880006F;
mem['h017B] <= 32'hC00027F3;
mem['h017C] <= 32'hFEF42223;
mem['h017D] <= 32'hFE442703;
mem['h017E] <= 32'hFE842783;
mem['h017F] <= 32'h40F707B3;
mem['h0180] <= 32'hFEF42023;
mem['h0181] <= 32'hFE042703;
mem['h0182] <= 32'h00B727B7;
mem['h0183] <= 32'hB0078793;
mem['h0184] <= 32'h04E7F863;
mem['h0185] <= 32'hFDC42783;
mem['h0186] <= 32'h00078663;
mem['h0187] <= 32'hFDC42503;
mem['h0188] <= 32'hBC9FF0EF;
mem['h0189] <= 32'hFE442783;
mem['h018A] <= 32'hFEF42423;
mem['h018B] <= 32'h030007B7;
mem['h018C] <= 32'h0007A783;
mem['h018D] <= 32'h00179713;
mem['h018E] <= 32'h030007B7;
mem['h018F] <= 32'h0007A783;
mem['h0190] <= 32'h0017D793;
mem['h0191] <= 32'h0017F793;
mem['h0192] <= 32'h0017B793;
mem['h0193] <= 32'h0FF7F793;
mem['h0194] <= 32'h00078693;
mem['h0195] <= 32'h030007B7;
mem['h0196] <= 32'h00D76733;
mem['h0197] <= 32'h00E7A023;
mem['h0198] <= 32'h020007B7;
mem['h0199] <= 32'h00878793;
mem['h019A] <= 32'h0007A783;
mem['h019B] <= 32'hFEF42623;
mem['h019C] <= 32'hFEC42703;
mem['h019D] <= 32'hFFF00793;
mem['h019E] <= 32'hF6F70AE3;
mem['h019F] <= 32'h030007B7;
mem['h01A0] <= 32'h0007A023;
mem['h01A1] <= 32'hFEC42783;
mem['h01A2] <= 32'h0FF7F793;
mem['h01A3] <= 32'h00078513;
mem['h01A4] <= 32'h02C12083;
mem['h01A5] <= 32'h02812403;
mem['h01A6] <= 32'h03010113;
mem['h01A7] <= 32'h00008067;
mem['h01A8] <= 32'hFF010113;
mem['h01A9] <= 32'h00112623;
mem['h01AA] <= 32'h00812423;
mem['h01AB] <= 32'h01010413;
mem['h01AC] <= 32'h00000513;
mem['h01AD] <= 32'hEF5FF0EF;
mem['h01AE] <= 32'h00050793;
mem['h01AF] <= 32'h00078513;
mem['h01B0] <= 32'h00C12083;
mem['h01B1] <= 32'h00812403;
mem['h01B2] <= 32'h01010113;
mem['h01B3] <= 32'h00008067;
mem['h01B4] <= 32'hEB010113;
mem['h01B5] <= 32'h14112623;
mem['h01B6] <= 32'h14812423;
mem['h01B7] <= 32'h15010413;
mem['h01B8] <= 32'h00050793;
mem['h01B9] <= 32'hEAB42C23;
mem['h01BA] <= 32'hEAF40FA3;
mem['h01BB] <= 32'hEC040793;
mem['h01BC] <= 32'hFCF42A23;
mem['h01BD] <= 32'h12B9B7B7;
mem['h01BE] <= 32'h0A178793;
mem['h01BF] <= 32'hFEF42623;
mem['h01C0] <= 32'hC00027F3;
mem['h01C1] <= 32'hFCF42823;
mem['h01C2] <= 32'hC02027F3;
mem['h01C3] <= 32'hFCF42623;
mem['h01C4] <= 32'hFE042423;
mem['h01C5] <= 32'h1200006F;
mem['h01C6] <= 32'hFE042223;
mem['h01C7] <= 32'h0640006F;
mem['h01C8] <= 32'hFEC42783;
mem['h01C9] <= 32'h00D79793;
mem['h01CA] <= 32'hFEC42703;
mem['h01CB] <= 32'h00F747B3;
mem['h01CC] <= 32'hFEF42623;
mem['h01CD] <= 32'hFEC42783;
mem['h01CE] <= 32'h0117D793;
mem['h01CF] <= 32'hFEC42703;
mem['h01D0] <= 32'h00F747B3;
mem['h01D1] <= 32'hFEF42623;
mem['h01D2] <= 32'hFEC42783;
mem['h01D3] <= 32'h00579793;
mem['h01D4] <= 32'hFEC42703;
mem['h01D5] <= 32'h00F747B3;
mem['h01D6] <= 32'hFEF42623;
mem['h01D7] <= 32'hFEC42783;
mem['h01D8] <= 32'h0FF7F713;
mem['h01D9] <= 32'hFE442783;
mem['h01DA] <= 32'hFF040693;
mem['h01DB] <= 32'h00F687B3;
mem['h01DC] <= 32'hECE78823;
mem['h01DD] <= 32'hFE442783;
mem['h01DE] <= 32'h00178793;
mem['h01DF] <= 32'hFEF42223;
mem['h01E0] <= 32'hFE442703;
mem['h01E1] <= 32'h0FF00793;
mem['h01E2] <= 32'hF8E7DCE3;
mem['h01E3] <= 32'hFE042023;
mem['h01E4] <= 32'hFC042E23;
mem['h01E5] <= 32'h0440006F;
mem['h01E6] <= 32'hFE042783;
mem['h01E7] <= 32'hFF040713;
mem['h01E8] <= 32'h00F707B3;
mem['h01E9] <= 32'hED07C783;
mem['h01EA] <= 32'h02078263;
mem['h01EB] <= 32'hFDC42783;
mem['h01EC] <= 32'h00178713;
mem['h01ED] <= 32'hFCE42E23;
mem['h01EE] <= 32'hFE042703;
mem['h01EF] <= 32'h0FF77713;
mem['h01F0] <= 32'hFF040693;
mem['h01F1] <= 32'h00F687B3;
mem['h01F2] <= 32'hECE78823;
mem['h01F3] <= 32'hFE042783;
mem['h01F4] <= 32'h00178793;
mem['h01F5] <= 32'hFEF42023;
mem['h01F6] <= 32'hFE042703;
mem['h01F7] <= 32'h0FF00793;
mem['h01F8] <= 32'hFAE7DCE3;
mem['h01F9] <= 32'hFC042C23;
mem['h01FA] <= 32'hFC042023;
mem['h01FB] <= 32'h0300006F;
mem['h01FC] <= 32'hFD842783;
mem['h01FD] <= 32'h00279793;
mem['h01FE] <= 32'hFD442703;
mem['h01FF] <= 32'h00F707B3;
mem['h0200] <= 32'h0007A783;
mem['h0201] <= 32'hFEC42703;
mem['h0202] <= 32'h00F747B3;
mem['h0203] <= 32'hFEF42623;
mem['h0204] <= 32'hFD842783;
mem['h0205] <= 32'h00178793;
mem['h0206] <= 32'hFCF42C23;
mem['h0207] <= 32'hFD842703;
mem['h0208] <= 32'h03F00793;
mem['h0209] <= 32'hFCE7D6E3;
mem['h020A] <= 32'hFE842783;
mem['h020B] <= 32'h00178793;
mem['h020C] <= 32'hFEF42423;
mem['h020D] <= 32'hFE842703;
mem['h020E] <= 32'h01300793;
mem['h020F] <= 32'hECE7DEE3;
mem['h0210] <= 32'hC00027F3;
mem['h0211] <= 32'hFCF42423;
mem['h0212] <= 32'hC02027F3;
mem['h0213] <= 32'hFCF42223;
mem['h0214] <= 32'hEBF44783;
mem['h0215] <= 32'h06078E63;
mem['h0216] <= 32'h001017B7;
mem['h0217] <= 32'hA9C78513;
mem['h0218] <= 32'h989FF0EF;
mem['h0219] <= 32'hFC842703;
mem['h021A] <= 32'hFD042783;
mem['h021B] <= 32'h40F707B3;
mem['h021C] <= 32'h00800593;
mem['h021D] <= 32'h00078513;
mem['h021E] <= 32'h9C1FF0EF;
mem['h021F] <= 32'h00A00513;
mem['h0220] <= 32'h919FF0EF;
mem['h0221] <= 32'h001017B7;
mem['h0222] <= 32'hAA878513;
mem['h0223] <= 32'h95DFF0EF;
mem['h0224] <= 32'hFC442703;
mem['h0225] <= 32'hFCC42783;
mem['h0226] <= 32'h40F707B3;
mem['h0227] <= 32'h00800593;
mem['h0228] <= 32'h00078513;
mem['h0229] <= 32'h995FF0EF;
mem['h022A] <= 32'h00A00513;
mem['h022B] <= 32'h8EDFF0EF;
mem['h022C] <= 32'h001017B7;
mem['h022D] <= 32'hAB478513;
mem['h022E] <= 32'h931FF0EF;
mem['h022F] <= 32'h00800593;
mem['h0230] <= 32'hFEC42503;
mem['h0231] <= 32'h975FF0EF;
mem['h0232] <= 32'h00A00513;
mem['h0233] <= 32'h8CDFF0EF;
mem['h0234] <= 32'hEB842783;
mem['h0235] <= 32'h00078C63;
mem['h0236] <= 32'hFC442703;
mem['h0237] <= 32'hFCC42783;
mem['h0238] <= 32'h40F70733;
mem['h0239] <= 32'hEB842783;
mem['h023A] <= 32'h00E7A023;
mem['h023B] <= 32'hFC842703;
mem['h023C] <= 32'hFD042783;
mem['h023D] <= 32'h40F707B3;
mem['h023E] <= 32'h00078513;
mem['h023F] <= 32'h14C12083;
mem['h0240] <= 32'h14812403;
mem['h0241] <= 32'h15010113;
mem['h0242] <= 32'h00008067;
mem['h0243] <= 32'hFE010113;
mem['h0244] <= 32'h00112E23;
mem['h0245] <= 32'h00812C23;
mem['h0246] <= 32'h02010413;
mem['h0247] <= 32'h030007B7;
mem['h0248] <= 32'h01F00713;
mem['h0249] <= 32'h00E7A023;
mem['h024A] <= 32'h020007B7;
mem['h024B] <= 32'h00478793;
mem['h024C] <= 32'h0D900713;
mem['h024D] <= 32'h00E7A023;
mem['h024E] <= 32'h001017B7;
mem['h024F] <= 32'hAC078513;
mem['h0250] <= 32'h8A9FF0EF;
mem['h0251] <= 32'h030007B7;
mem['h0252] <= 32'h03F00713;
mem['h0253] <= 32'h00E7A023;
mem['h0254] <= 32'h030007B7;
mem['h0255] <= 32'h07F00713;
mem['h0256] <= 32'h00E7A023;
mem['h0257] <= 32'h00000013;
mem['h0258] <= 32'h001017B7;
mem['h0259] <= 32'hACC78513;
mem['h025A] <= 32'hC41FF0EF;
mem['h025B] <= 32'h00050793;
mem['h025C] <= 32'h00078713;
mem['h025D] <= 32'h00D00793;
mem['h025E] <= 32'hFEF714E3;
mem['h025F] <= 32'h001017B7;
mem['h0260] <= 32'hAE878513;
mem['h0261] <= 32'h865FF0EF;
mem['h0262] <= 32'h001017B7;
mem['h0263] <= 32'hAEC78513;
mem['h0264] <= 32'h859FF0EF;
mem['h0265] <= 32'h001017B7;
mem['h0266] <= 32'hB1478513;
mem['h0267] <= 32'h84DFF0EF;
mem['h0268] <= 32'h001017B7;
mem['h0269] <= 32'hB3C78513;
mem['h026A] <= 32'h841FF0EF;
mem['h026B] <= 32'h001017B7;
mem['h026C] <= 32'hB6078513;
mem['h026D] <= 32'h835FF0EF;
mem['h026E] <= 32'h001017B7;
mem['h026F] <= 32'hB8878513;
mem['h0270] <= 32'h829FF0EF;
mem['h0271] <= 32'h001017B7;
mem['h0272] <= 32'hAE878513;
mem['h0273] <= 32'h81DFF0EF;
mem['h0274] <= 32'h001017B7;
mem['h0275] <= 32'hAE878513;
mem['h0276] <= 32'h811FF0EF;
mem['h0277] <= 32'h001017B7;
mem['h0278] <= 32'hBB078513;
mem['h0279] <= 32'h805FF0EF;
mem['h027A] <= 32'h001017B7;
mem['h027B] <= 32'hAE878513;
mem['h027C] <= 32'hFF8FF0EF;
mem['h027D] <= 32'h00A00793;
mem['h027E] <= 32'hFEF42623;
mem['h027F] <= 32'h0780006F;
mem['h0280] <= 32'h001017B7;
mem['h0281] <= 32'hBD478513;
mem['h0282] <= 32'hFE0FF0EF;
mem['h0283] <= 32'hC95FF0EF;
mem['h0284] <= 32'h00050793;
mem['h0285] <= 32'hFEF405A3;
mem['h0286] <= 32'hFEB44703;
mem['h0287] <= 32'h02000793;
mem['h0288] <= 32'h00E7FE63;
mem['h0289] <= 32'hFEB44703;
mem['h028A] <= 32'h07E00793;
mem['h028B] <= 32'h00E7E863;
mem['h028C] <= 32'hFEB44783;
mem['h028D] <= 32'h00078513;
mem['h028E] <= 32'hF60FF0EF;
mem['h028F] <= 32'h001017B7;
mem['h0290] <= 32'hAE878513;
mem['h0291] <= 32'hFA4FF0EF;
mem['h0292] <= 32'hFEB44703;
mem['h0293] <= 32'h03900793;
mem['h0294] <= 32'h00F71C63;
mem['h0295] <= 32'h00000593;
mem['h0296] <= 32'h00100513;
mem['h0297] <= 32'hC75FF0EF;
mem['h0298] <= 32'h00000013;
mem['h0299] <= 32'h0180006F;
mem['h029A] <= 32'hFEC42783;
mem['h029B] <= 32'hFFF78793;
mem['h029C] <= 32'hFEF42623;
mem['h029D] <= 32'hFEC42783;
mem['h029E] <= 32'hF8F044E3;
mem['h029F] <= 32'hF49FF06F;
mem['h02A0] <= 32'h33323130;
mem['h02A1] <= 32'h37363534;
mem['h02A2] <= 32'h62613938;
mem['h02A3] <= 32'h66656463;
mem['h02A4] <= 32'h00000000;
mem['h02A5] <= 32'h30313D3E;
mem['h02A6] <= 32'h00000030;
mem['h02A7] <= 32'h6C637943;
mem['h02A8] <= 32'h203A7365;
mem['h02A9] <= 32'h00007830;
mem['h02AA] <= 32'h74736E49;
mem['h02AB] <= 32'h203A736E;
mem['h02AC] <= 32'h00007830;
mem['h02AD] <= 32'h736B6843;
mem['h02AE] <= 32'h203A6D75;
mem['h02AF] <= 32'h00007830;
mem['h02B0] <= 32'h746F6F42;
mem['h02B1] <= 32'h2E676E69;
mem['h02B2] <= 32'h00000A2E;
mem['h02B3] <= 32'h73657250;
mem['h02B4] <= 32'h4E452073;
mem['h02B5] <= 32'h20524554;
mem['h02B6] <= 32'h63206F74;
mem['h02B7] <= 32'h69746E6F;
mem['h02B8] <= 32'h2E65756E;
mem['h02B9] <= 32'h00000A2E;
mem['h02BA] <= 32'h0000000A;
mem['h02BB] <= 32'h5F5F2020;
mem['h02BC] <= 32'h20205F5F;
mem['h02BD] <= 32'h2020205F;
mem['h02BE] <= 32'h20202020;
mem['h02BF] <= 32'h5F202020;
mem['h02C0] <= 32'h205F5F5F;
mem['h02C1] <= 32'h20202020;
mem['h02C2] <= 32'h20202020;
mem['h02C3] <= 32'h5F5F5F5F;
mem['h02C4] <= 32'h0000000A;
mem['h02C5] <= 32'h20207C20;
mem['h02C6] <= 32'h285C205F;
mem['h02C7] <= 32'h5F20295F;
mem['h02C8] <= 32'h5F205F5F;
mem['h02C9] <= 32'h202F5F5F;
mem['h02CA] <= 32'h7C5F5F5F;
mem['h02CB] <= 32'h5F5F2020;
mem['h02CC] <= 32'h2F20205F;
mem['h02CD] <= 32'h5F5F5F20;
mem['h02CE] <= 32'h00000A7C;
mem['h02CF] <= 32'h7C207C20;
mem['h02D0] <= 32'h7C20295F;
mem['h02D1] <= 32'h202F7C20;
mem['h02D2] <= 32'h202F5F5F;
mem['h02D3] <= 32'h5F5C205F;
mem['h02D4] <= 32'h5C205F5F;
mem['h02D5] <= 32'h5F202F20;
mem['h02D6] <= 32'h207C5C20;
mem['h02D7] <= 32'h00000A7C;
mem['h02D8] <= 32'h20207C20;
mem['h02D9] <= 32'h7C2F5F5F;
mem['h02DA] <= 32'h28207C20;
mem['h02DB] <= 32'h28207C5F;
mem['h02DC] <= 32'h7C20295F;
mem['h02DD] <= 32'h20295F5F;
mem['h02DE] <= 32'h5F28207C;
mem['h02DF] <= 32'h207C2029;
mem['h02E0] <= 32'h5F5F5F7C;
mem['h02E1] <= 32'h0000000A;
mem['h02E2] <= 32'h7C5F7C20;
mem['h02E3] <= 32'h7C202020;
mem['h02E4] <= 32'h5F5C7C5F;
mem['h02E5] <= 32'h5F5C5F5F;
mem['h02E6] <= 32'h5F2F5F5F;
mem['h02E7] <= 32'h2F5F5F5F;
mem['h02E8] <= 32'h5F5F5C20;
mem['h02E9] <= 32'h5C202F5F;
mem['h02EA] <= 32'h5F5F5F5F;
mem['h02EB] <= 32'h00000A7C;
mem['h02EC] <= 32'h5B202020;
mem['h02ED] <= 32'h52205D39;
mem['h02EE] <= 32'h73206E75;
mem['h02EF] <= 32'h6C706D69;
mem['h02F0] <= 32'h69747369;
mem['h02F1] <= 32'h65622063;
mem['h02F2] <= 32'h6D68636E;
mem['h02F3] <= 32'h0A6B7261;
mem['h02F4] <= 32'h00000000;
mem['h02F5] <= 32'h6D6D6F43;
mem['h02F6] <= 32'h3E646E61;
mem['h02F7] <= 32'h00000020;
end
always @(posedge clk) mem_data <= mem[mem_addr];
// ============================================================================
reg o_ready;
always @(posedge clk or negedge rstn)
if (!rstn) o_ready <= 1'd0;
else o_ready <= valid && ((addr & MEM_ADDR_MASK) != 0);
// Output connectins
assign ready = o_ready;
assign rdata = mem_data;
assign mem_addr = addr[MEM_SIZE_BITS+1:2];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog wrapper for lpflow_clkbufkapwr with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkbufkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkbufkapwr_8 (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkbufkapwr_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkbufkapwr base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8_V
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: oq_regs_eval_empty.v
// Project: NF2.1
// Description: Evaluates whether a queue is empty
//
// Currently looks at the number of packets in the queue
//
///////////////////////////////////////////////////////////////////////////////
module oq_regs_eval_empty
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH),
parameter MAX_PKT = 2048/CTRL_WIDTH, // allow for 2K bytes,
parameter MIN_PKT = 60/CTRL_WIDTH + 1,
parameter PKTS_IN_RAM_WIDTH = log2((2**SRAM_ADDR_WIDTH)/MIN_PKT)
)
(
// --- Inputs from dst update ---
input dst_update,
input [NUM_OQ_WIDTH-1:0] dst_oq,
input [PKTS_IN_RAM_WIDTH-1:0] dst_num_pkts_in_q,
input dst_num_pkts_in_q_done,
// --- Inputs from src update ---
input src_update,
input [NUM_OQ_WIDTH-1:0] src_oq,
input [PKTS_IN_RAM_WIDTH-1:0] src_num_pkts_in_q,
input src_num_pkts_in_q_done,
// --- Clear the flag ---
input initialize,
input [NUM_OQ_WIDTH-1:0] initialize_oq,
output reg [NUM_OUTPUT_QUEUES-1:0] empty,
// --- Misc
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
// ------------- Wires/reg ------------------
wire src_empty;
wire dst_empty;
reg dst_empty_held;
reg [NUM_OQ_WIDTH-1:0] dst_oq_held;
reg [NUM_OQ_WIDTH-1:0] src_oq_held;
reg dst_num_pkts_in_q_done_held;
// ------------- Logic ------------------
assign src_empty = src_num_pkts_in_q == 'h0;
assign dst_empty = dst_num_pkts_in_q == 'h0;
always @(posedge clk)
begin
if (reset) begin
empty <= {NUM_OUTPUT_QUEUES{1'b1}};
end
else begin
if (dst_update) begin
dst_oq_held <= dst_oq;
end
if (src_update) begin
src_oq_held <= src_oq;
end
// Update the empty status giving preference to removes over stores
// since we don't want to accidentally try removing from an empty
// queue
if (src_num_pkts_in_q_done) begin
empty[src_oq_held] <= src_empty;
dst_num_pkts_in_q_done_held <= dst_num_pkts_in_q_done;
dst_empty_held <= dst_empty;
end
else if (dst_num_pkts_in_q_done) begin
empty[dst_oq_held] <= dst_empty;
end
else if (dst_num_pkts_in_q_done_held) begin
empty[dst_oq_held] <= dst_empty_held;
end
else if (initialize) begin
empty[initialize_oq] <= 1'b1;
end
end
end
endmodule // oq_regs_eval_empty
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ZC706_Gen1x4If64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx ZC706 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "tlp.vh"
`include "xilinx.vh"
`timescale 1ps / 1ps
module ZC706_Gen1x4If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 4,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [3:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
wire pcie_refclk;
wire pcie_reset_n;
wire user_clk;
wire user_reset;
wire user_lnk_up;
wire user_app_rdy;
wire s_axis_tx_tready;
wire [C_PCI_DATA_WIDTH-1 : 0] s_axis_tx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1 : 0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
wire [`SIG_XIL_TX_TUSER_W : 0] s_axis_tx_tuser;
wire [C_PCI_DATA_WIDTH-1 : 0] m_axis_rx_tdata;
wire [(C_PCI_DATA_WIDTH/8)-1 : 0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [`SIG_XIL_RX_TUSER_W - 1 : 0] m_axis_rx_tuser;
wire tx_cfg_gnt;
wire rx_np_ok;
wire rx_np_req;
wire cfg_turnoff_ok;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [63:0] cfg_dsn;
wire [11 : 0] fc_cpld;
wire [7 : 0] fc_cplh;
wire [11 : 0] fc_npd;
wire [7 : 0] fc_nph;
wire [11 : 0] fc_pd;
wire [7 : 0] fc_ph;
wire [2 : 0] fc_sel;
wire [15 : 0] cfg_status;
wire [15 : 0] cfg_command;
wire [15 : 0] cfg_dstatus;
wire [15 : 0] cfg_dcommand;
wire [15 : 0] cfg_lstatus;
wire [15 : 0] cfg_lcommand;
wire [15 : 0] cfg_dcommand2;
wire [2 : 0] cfg_pcie_link_state;
wire cfg_pmcsr_pme_en;
wire [1 : 0] cfg_pmcsr_powerstate;
wire cfg_pmcsr_pme_status;
wire cfg_received_func_lvl_rst;
wire [4 : 0] cfg_pciecap_interrupt_msgnum;
wire cfg_to_turnoff;
wire [7 : 0] cfg_bus_number;
wire [4 : 0] cfg_device_number;
wire [2 : 0] cfg_function_number;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7 : 0] cfg_interrupt_di;
wire [7 : 0] cfg_interrupt_do;
wire [2 : 0] cfg_interrupt_mmenable;
wire cfg_interrupt_msien;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
assign cfg_turnoff_ok = 0;
assign cfg_trn_pending = 0;
assign cfg_pm_halt_aspm_l0s = 0;
assign cfg_pm_halt_aspm_l1 = 0;
assign cfg_pm_force_state_en = 0;
assign cfg_pm_force_state = 0;
assign cfg_dsn = 0;
assign cfg_interrupt_assert = 0;
assign cfg_interrupt_di = 0;
assign cfg_interrupt_stat = 0;
assign cfg_pciecap_interrupt_msgnum = 0;
assign cfg_turnoff_ok = 0;
assign cfg_pm_wake = 0;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
// Core Top Level Wrapper
PCIeGen1x4If64 PCIeGen1x4If64_i
(
//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
// Tx
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
// Rx
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI-S Interface
//---------------------------------------------------------------------
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( user_app_rdy ),
// TX
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_dsn ( cfg_dsn ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_pm_wake ( cfg_pm_wake ),
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
//---------------------------------------------------------------------
// Flow Control Interface
//---------------------------------------------------------------------
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.cfg_device_number ( cfg_device_number ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_status ( cfg_status ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msien ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
//---------------------------------------------------------------------
// System (SYS) Interface
//---------------------------------------------------------------------
.sys_clk ( pcie_refclk ),
.sys_rst_n ( pcie_reset_n )
);
riffa_wrapper_zc706
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.CFG_INTERRUPT (cfg_interrupt),
.M_AXIS_RX_TREADY (m_axis_rx_tready),
.S_AXIS_TX_TDATA (s_axis_tx_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (s_axis_tx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (s_axis_tx_tlast),
.S_AXIS_TX_TVALID (s_axis_tx_tvalid),
.S_AXIS_TX_TUSER (s_axis_tx_tuser[`SIG_XIL_TX_TUSER_W-1:0]),
.FC_SEL (fc_sel[`SIG_FC_SEL_W-1:0]),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_RX_TDATA (m_axis_rx_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (m_axis_rx_tkeep[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (m_axis_rx_tlast),
.M_AXIS_RX_TVALID (m_axis_rx_tvalid),
.M_AXIS_RX_TUSER (m_axis_rx_tuser[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (s_axis_tx_tready),
.CFG_BUS_NUMBER (cfg_bus_number[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (cfg_device_number[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (cfg_function_number[`SIG_FNID_W-1:0]),
.CFG_COMMAND (cfg_command[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (cfg_dcommand[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (cfg_lstatus[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (cfg_lcommand[`SIG_CFGREG_W-1:0]),
.FC_CPLD (fc_cpld[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (fc_cplh[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (cfg_interrupt_msien),
.CFG_INTERRUPT_RDY (cfg_interrupt_rdy),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]),
.RX_NP_OK (rx_np_ok),
.RX_NP_REQ (rx_np_req),
.TX_CFG_GNT (tx_cfg_gnt)
/*AUTOINST*/);
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFXTP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfxtp (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_BLACKBOX_V
|
/*------------------------------------------------------------------------------
Purpose
Control Wishbone interface to memory.
------------------------------------------------------------------------------*/
module mips_memctrl #(parameter ADDR_RESET=32'hBFC0_0000)
(
input clk,
input rst,
input pl_pcpause,
input pcreg_wen,
input[31:2] pcreg_wdata,
output reg[31:2] pcreg_crntcmd,
output reg[31:2] pcreg_nextcmd,
input exception,
input pmem_stall_i,
input pmem_ack_i,
input[31:0] pmem_dat_i,
output[31:2] pmem_adr_o,
output reg pmem_stb_o,
output reg pmem_cyc_o,
output pmem_branch_ended,
output fifocmd_empty,
output[31:0] fifocmd_rdata,
input dmem_wen,
input[31:2] dmem_waddr,
input[31:0] dmem_wdata,
input[3:0] dmem_wbytesel,
input dmem_wrw,
input[5:0] dmem_wloadinstr,
input[4:0] dmem_wgregbusy,
input[1:0] dmem_wbytesel_int,
output reg[1:0] dmem_rreq,
output reg[1:0] dmem_rmemdir,
output reg[4:0] dmem_rgregbusy_queued,
output reg[4:0] dmem_rgregbusy,
output reg[5:0] dmem_rloadinstr,
output reg[1:0] dmem_rbytesel,
input dmem_stall_i,
input dmem_ack_i,
output reg[31:2] dmem_adr_o,
output reg[31:0] dmem_dat_o,
output reg dmem_cyc_o,
output reg dmem_stb_o,
output reg dmem_we_o,
output reg[3:0] dmem_sel_o
);
reg[1:0] pmem_rreq;
wire pmem_maxwaitreq;
reg[31:2] pcreg;
wire pcreg_pause;
reg pcreg_wen_hold;
reg[31:2] pcreg_wdata_hold;
reg[31:2] pcreg_before_branch;
wire fifocmd_wr;
wire fifocmd_rd;
wire fifopc_wr;
wire fifopc_rd;
wire[31:2] fifopc_rdata;
reg[5:0] dmem_rloadinstr_queued;
reg[1:0] dmem_rbytesel_queued;
/*-----------------------------------------------------------------------------
PROGRAM MEMORY
------------------------------------------------------------------------------*/
assign pcreg_pause= !pmem_cyc_o | //INITIAL
pmem_stall_i | //WISHBONE STALL
pmem_maxwaitreq | //MAX WAITING REQ
pl_pcpause; //PIPELINE WAIT
assign pmem_adr_o= pcreg;
assign pmem_maxwaitreq= pmem_rreq[1] & !pmem_ack_i & fifocmd_empty;
assign pmem_branch_ended= pcreg_before_branch==pcreg_crntcmd;
assign fifocmd_wr= (pl_pcpause | !pmem_stb_o) & pmem_ack_i;
assign fifocmd_rd= !fifocmd_empty & !pl_pcpause;
assign fifopc_wr= !pcreg_pause | !pmem_cyc_o;
assign fifopc_rd= ~(pmem_stall_i | pl_pcpause |(!pmem_ack_i & fifocmd_empty));
always @(posedge clk)
if(rst)
begin
pcreg<= ADDR_RESET[31:2];
pcreg_crntcmd<= ADDR_RESET[31:2];
pcreg_nextcmd<= ADDR_RESET[31:2];
pmem_stb_o<= 1'b0;
pmem_cyc_o<= 1'b0;
pmem_rreq<= 2'd0;
pcreg_wen_hold<= 1'b0;
pcreg_wdata_hold<= 30'd0;
pcreg_before_branch<= 30'd0;
end
else
begin
pmem_cyc_o<= 1'b1;
pmem_stb_o<= (pmem_maxwaitreq) |
(!pmem_stall_i & pl_pcpause) ? 1'b0 : 1'b1;
pmem_rreq<= !(pmem_stall_i | pmem_maxwaitreq | pl_pcpause) &
!pmem_ack_i & fifocmd_empty ? {pmem_rreq[0],1'b1} :
!pl_pcpause & (pmem_stall_i | pmem_maxwaitreq) &
(pmem_ack_i | !fifocmd_empty) ? {1'b0,pmem_rreq[1]} :
pmem_rreq;
if(pcreg_pause)
begin
pcreg_wen_hold<= pcreg_wen ? 1'b1 : pcreg_wen_hold;
pcreg<= pcreg;
end
else if(pcreg_wen_hold)
begin
pcreg_wen_hold<= 1'b0;
pcreg<= pcreg_wdata_hold;
end
else if(pcreg_wen)
begin
pcreg_wen_hold<= 1'b0;
pcreg<= pcreg_wdata;
end
else
begin
pcreg_wen_hold<= 1'b0;
pcreg<= pcreg+1'b1;
end
pcreg_wdata_hold<= pcreg_wen ? pcreg_wdata :
pcreg_wdata_hold;
pcreg_before_branch<= pcreg_wen ? pcreg : pcreg_before_branch;
if(!pmem_cyc_o & pmem_stall_i | pl_pcpause | (!pmem_ack_i & fifocmd_empty))
begin
pcreg_crntcmd<= pcreg_crntcmd;
pcreg_nextcmd<= pcreg_nextcmd;
end
else
begin
pcreg_crntcmd<= fifopc_rdata;
pcreg_nextcmd<= fifopc_rdata+1'b1;
end
end
mips_fifosync #(.S_WORD(30), .SPOWER2_MEM(1))
i_fifopc (
.clk(clk),
.rst(rst),
.wr_en(fifopc_wr),
.wr_data(pcreg_wen_hold ? pcreg_wdata_hold :
pcreg_wen ? pcreg_wdata :
pmem_cyc_o ? pcreg+1'b1 : 30'd0),
.rd_en(fifopc_rd),
.rd_data(fifopc_rdata),
.fifo_full(),
.fifo_empty()
);
mips_fifosync #(.S_WORD(32), .SPOWER2_MEM(1))
i_fifocmd (
.clk(clk),
.rst(rst),
.wr_en(fifocmd_wr),
.wr_data(pmem_dat_i),
.rd_en(fifocmd_rd),
.rd_data(fifocmd_rdata),
.fifo_full(),
.fifo_empty(fifocmd_empty)
);
/*------------------------------------------------------------------------------
DATA MEMORY
------------------------------------------------------------------------------*/
always @(posedge clk)
if(rst)
begin
dmem_rmemdir<= 2'd0;
dmem_rreq<= 2'd0;
dmem_rgregbusy_queued<= 5'd0;
dmem_rloadinstr_queued<= 6'd0;
dmem_rbytesel_queued<= 2'd0;
dmem_rgregbusy<= 5'd0;
dmem_rloadinstr<= 6'd0;
dmem_rbytesel<= 2'd0;
dmem_cyc_o<= 1'b0;
dmem_stb_o<= 1'b0;
dmem_adr_o<= 30'd0;
dmem_dat_o<= 32'd0;
dmem_sel_o<= 4'd0;
dmem_we_o<= 1'b0;
end
else
begin
if(!(dmem_rreq[1] & !dmem_ack_i))//ACTIVE STATE
begin
//EXTERNAL SIGNALS
dmem_stb_o<= !dmem_stall_i ? dmem_wen : dmem_stb_o;
if(dmem_wen)
begin
dmem_cyc_o<= 1'b1;
dmem_adr_o<= dmem_waddr;
dmem_dat_o<= dmem_wdata;
dmem_sel_o<= dmem_wbytesel;
dmem_we_o<= dmem_wrw;
end
else if(!dmem_rreq[1] & dmem_rreq[0] & dmem_ack_i) dmem_cyc_o<= 1'b0;
//INTERNAL CONTROL
if(dmem_wen & !dmem_rreq[0])//ZERO REQUEST
begin
dmem_rmemdir[0]<= dmem_wrw;
dmem_rreq[0]<= 1'b1;
if(!dmem_wrw)
begin
dmem_rgregbusy<= dmem_wgregbusy;
dmem_rloadinstr<= dmem_wloadinstr;
dmem_rbytesel<= dmem_wbytesel_int;
end
end
else if(dmem_wen & !dmem_rreq[1] & !dmem_ack_i)//ONE REQUEST
begin
dmem_rmemdir[1]<= dmem_wrw;
dmem_rreq[1]<= 1'b1;
if(!dmem_wrw)
begin
if(dmem_rloadinstr==0)//QUEUE HAS NO READ REQUEST
begin
dmem_rgregbusy<= dmem_wgregbusy;
dmem_rloadinstr<= dmem_wloadinstr;
dmem_rbytesel<= dmem_wbytesel_int;
end
else//QUEUE HAS ONE READ REQUEST
begin
dmem_rgregbusy_queued<= dmem_wgregbusy;
dmem_rloadinstr_queued<= dmem_wloadinstr;
dmem_rbytesel_queued<= dmem_wbytesel_int;
end
end
end
else if(dmem_wen & !dmem_rreq[1] & dmem_ack_i)//ONE REQUEST
begin
dmem_rmemdir[0]<= dmem_wrw;
dmem_rreq[0]<= 1'b1;
if(!dmem_wrw)
begin
dmem_rgregbusy<= dmem_wgregbusy;
dmem_rloadinstr<= dmem_wloadinstr;
dmem_rbytesel<= dmem_wbytesel_int;
end
end
else if(dmem_wen & dmem_rreq[1] & dmem_ack_i)//TWO REQUESTS
begin
dmem_rmemdir[1]<= dmem_wrw;
dmem_rmemdir[0]<= dmem_rmemdir[1];
dmem_rreq[1]<= 1'b1;
if(!dmem_wrw)
begin
if(dmem_rloadinstr==0 | //QUEUE HAS NO READ REQUEST OR
dmem_rmemdir[1]) //QUEUE HAS ONE READ REQUEST
//WHICH IS ACKING
begin
dmem_rgregbusy<= dmem_wgregbusy;
dmem_rloadinstr<= dmem_wloadinstr;
dmem_rbytesel<= dmem_wbytesel_int;
end
else if(dmem_rmemdir[0])//QUEUE HAS ONE READ REQUEST
//AND WRITE REQUEST IS ACKING
begin
dmem_rgregbusy_queued<= dmem_wgregbusy;
dmem_rloadinstr_queued<= dmem_wloadinstr;
dmem_rbytesel_queued<= dmem_wbytesel_int;
end
else//QUEUE HAS TWO READ REQUEST FIRST IS ACKING
begin
dmem_rgregbusy_queued<= dmem_wgregbusy;
dmem_rloadinstr_queued<= dmem_wloadinstr;
dmem_rbytesel_queued<= dmem_wbytesel_int;
dmem_rgregbusy<= dmem_rgregbusy_queued;
dmem_rloadinstr<= dmem_rloadinstr_queued;
dmem_rbytesel<= dmem_rbytesel_queued;
end
end
end
else if(!dmem_wen & dmem_ack_i)
begin
dmem_rmemdir[1]<= 1'b0;
dmem_rmemdir[0]<= dmem_rmemdir[1];
dmem_rreq[1]<= 1'b0;
dmem_rreq[0]<= dmem_rreq[1];
if(!dmem_rmemdir[0])
begin
dmem_rgregbusy_queued<= 0;
dmem_rloadinstr_queued<= 0;
dmem_rbytesel_queued<= 0;
dmem_rgregbusy<= dmem_rgregbusy_queued;
dmem_rloadinstr<= dmem_rloadinstr_queued;
dmem_rbytesel<= dmem_rbytesel_queued;
end
end
//ELSE - ALL IS HOLDING
end
else if(dmem_rreq[1] & !dmem_ack_i & !dmem_stall_i)//WAIT STATE
//WITH !DMEM_ACK_I
dmem_stb_o<= 1'b0;
//ELSE WAIT STATE WITH !DMEM_STALL_I - ALL IS HOLDING
end
endmodule
|
//SLX 8/24/2016
//
// 3 read-port, 1 write-port ram
//
// reads are asynchronous
//
`include "bsg_defines.v"
module bsg_mem_3r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r2_data_o
);
bsg_mem_3r1w_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
) synth
(.*);
//synopsys translate_off
always_ff @(negedge w_clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (!(r0_addr_i == w_addr_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
assert (!(r1_addr_i == w_addr_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
assert (!(r2_addr_i == w_addr_i && r2_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
end
initial
begin
$display("## bsg_mem_3r1w: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d (%m)",width_p,els_p,read_write_same_addr_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_3r1w)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S2S_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYMETAL6S2S_BLACKBOX_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s2s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S2S_BLACKBOX_V
|
//---------------------------------------------------------------------//
// Name: am_put_fpga.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Top-level file for implementing the American Put in an FPGA.
//---------------------------------------------------------------------//
module amer_put(
clk_fast,
clk_slow,
nrst,
start_s1,
start_s2,
p_up,
p_down,
log_lambda_up,
log_lambda_down,
K_over_S,
result
);
input clk_fast;
input clk_slow;
input nrst;
input start_s1;
input start_s2;
input [63:0] p_up;
input [63:0] p_down;
input [63:0] log_lambda_up;
input [63:0] log_lambda_down;
input [63:0] K_over_S;
output [63:0] result;
//---------------------------------------------------------------------//
// Wires
//---------------------------------------------------------------------//
wire [63:0] c0_memout;
wire [63:0] c1_memout;
wire [63:0] c2_memout;
wire [63:0] c3_memout;
wire [63:0] c0_up;
wire [63:0] c1_up;
wire [63:0] c2_up;
wire [63:0] c3_up;
wire [63:0] c0_down;
wire [63:0] c1_down;
wire [63:0] c2_down;
wire [63:0] c3_down;
wire [63:0] c0_vex;
wire [63:0] c1_vex;
wire [63:0] c2_vex;
wire [63:0] c3_vex;
wire [63:0] c0_result;
wire [63:0] c1_result;
wire [63:0] c2_result;
wire [63:0] c3_result;
wire [9:0] rdaddr;
wire [9:0] wraddr;
wire [12:0] vexaddr;
wire done_init;
wire wren;
//---------------------------------------------------------------------//
// Assignments.
//---------------------------------------------------------------------//
assign result = c0_memout;
//---------------------------------------------------------------------//
// Instantiations
//---------------------------------------------------------------------//
addrgen addrgen_inst(
.clk(clk_fast),
.nrst(nrst),
.start(done_s1),
.readout(start_s2),
.n(16'd4000),
.wraddr(wraddr),
.wren(wren),
.rdaddr(rdaddr),
.vexaddr(vexaddr)
);
value_membank value_membank_inst(
.clk(clk_fast),
.nrst(nrst),
.wren(wren),
.rdaddr(rdaddr),
.wraddr(wraddr),
.start_init(start_s1),
.done_init(done_init),
.c0_in(c0_result),
.c1_in(c1_result),
.c2_in(c2_result),
.c3_in(c3_result),
.c0_out(c0_memout),
.c1_out(c1_memout),
.c2_out(c2_memout),
.c3_out(c3_memout)
);
value_buffer value_buffer_inst(
.clk(clk_fast),
.c0_in(c0_memout),
.c1_in(c1_memout),
.c2_in(c2_memout),
.c3_in(c3_memout),
.c0_up(c0_up),
.c1_up(c1_up),
.c2_up(c2_up),
.c3_up(c3_up),
.c0_down(c0_down),
.c1_down(c1_down),
.c2_down(c2_down),
.c3_down(c3_down)
);
// Compute value at the current node.
eval_node c0_eval_node(
.clk(clk_fast),
.nrst(nrst),
.p_up(p_up),
.p_down(p_down),
.v_up(c0_up),
.v_down(c0_down),
.v_ex(c0_vex),
.result(c0_result)
);
eval_node c1_eval_node(
.clk(clk_fast),
.nrst(nrst),
.p_up(p_up),
.p_down(p_down),
.v_up(c1_up),
.v_down(c1_down),
.v_ex(c1_vex),
.result(c1_result)
);
eval_node c2_eval_node(
.clk(clk_fast),
.nrst(nrst),
.p_up(p_up),
.p_down(p_down),
.v_up(c2_up),
.v_down(c2_down),
.v_ex(c2_vex),
.result(c2_result)
);
eval_node c3_eval_node(
.clk(clk_fast),
.nrst(nrst),
.p_up(p_up),
.p_down(p_down),
.v_up(c3_up),
.v_down(c3_down),
.v_ex(c3_vex),
.result(c3_result)
);
// Vex Lookup.
vex vex_inst(
.clk_slow(clk_slow),
.clk_fast(clk_fast),
.nrst(nrst),
.start_s1(start_s1),
.start_s2(done_s1),
.log_lambda_up(log_lambda_up),
.log_lambda_down(log_lambda_down),
.K_over_S(K_over_S),
.chan0(c0_vex),
.chan1(c1_vex),
.chan2(c2_vex),
.chan3(c3_vex),
.done_s1(done_s1),
.vexaddr(vexaddr)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_SYMBOL_V
`define SKY130_FD_SC_HD__A2111O_SYMBOL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2111o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: top_nto1_pll_diff_rx.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: June 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: Example differential input receiver for clock and data using PLL
// Serdes factor and number of data lines are set by constants in the code
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
//
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module top_nto1_pll_diff_rx (
input reset, // reset (active high)
//input [3:0] rx_data_in_fix, // lvds data inputs
input [1:0] rx_data_in_fix, // lvds data inputs
input x_clk, // lvds clock input
//output [27:0] data_out) ; // dummy outputs
output [13:0] data_out) ; // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 7 ; // Set the serdes factor to 8
parameter integer D = 4 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire rst ;
wire [DS:0] rxd ; // Data from serdeses
reg [DS:0] rxr ; // Registered Data from serdeses
reg state ;
reg bslip ;
reg [3:0] count ;
wire [6:0] clk_iserdes_data ;
assign rst = reset ; // active high reset pin
assign data_out = rxr ;
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_pll_s8_diff #(
.S (S),
.CLKIN_PERIOD (50.000),
.PLLD (1),
.PLLX (S),
.BS ("TRUE")) // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
inst_clkin (
.x_clk(x_clk),
.rxioclk (rx_bufpll_clk_xn),
.pattern1 (7'b1100001), // default values for 7:1 video applications
.pattern2 (7'b1100011),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.bitslip (bitslip),
.reset (rst),
.datain (clk_iserdes_data),
.rx_pll_lckd (), // PLL locked - only used if a 2nd BUFPLL is required
.rx_pllout_xs (), // Multiplied PLL clock - only used if a 2nd BUFPLL is required
.rx_bufpll_lckd (rx_bufpll_lckd)) ;
// Data Inputs
assign not_bufpll_lckd = ~rx_bufpll_lckd ;
serdes_1_to_n_data_s8_diff #(
.S (S),
.D (D))
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.rx_data_in_fix(rx_data_in_fix),
.rxioclk (rx_bufpll_clk_xn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bitslip),
.reset (not_bufpll_lckd),
.data_out (rxd),
.debug_in (2'b00),
.debug ());
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd ;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_4_V
`define SKY130_FD_SC_HS__INV_4_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__inv_4 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__inv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_4_V
|
// soc_system_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.01.06.14:12:55
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_1 (
output wire [7:0] hps_0_f2h_axi_slave_awid, // hps_0_f2h_axi_slave.awid
output wire [31:0] hps_0_f2h_axi_slave_awaddr, // .awaddr
output wire [3:0] hps_0_f2h_axi_slave_awlen, // .awlen
output wire [2:0] hps_0_f2h_axi_slave_awsize, // .awsize
output wire [1:0] hps_0_f2h_axi_slave_awburst, // .awburst
output wire [1:0] hps_0_f2h_axi_slave_awlock, // .awlock
output wire [3:0] hps_0_f2h_axi_slave_awcache, // .awcache
output wire [2:0] hps_0_f2h_axi_slave_awprot, // .awprot
output wire [4:0] hps_0_f2h_axi_slave_awuser, // .awuser
output wire hps_0_f2h_axi_slave_awvalid, // .awvalid
input wire hps_0_f2h_axi_slave_awready, // .awready
output wire [7:0] hps_0_f2h_axi_slave_wid, // .wid
output wire [127:0] hps_0_f2h_axi_slave_wdata, // .wdata
output wire [15:0] hps_0_f2h_axi_slave_wstrb, // .wstrb
output wire hps_0_f2h_axi_slave_wlast, // .wlast
output wire hps_0_f2h_axi_slave_wvalid, // .wvalid
input wire hps_0_f2h_axi_slave_wready, // .wready
input wire [7:0] hps_0_f2h_axi_slave_bid, // .bid
input wire [1:0] hps_0_f2h_axi_slave_bresp, // .bresp
input wire hps_0_f2h_axi_slave_bvalid, // .bvalid
output wire hps_0_f2h_axi_slave_bready, // .bready
output wire [7:0] hps_0_f2h_axi_slave_arid, // .arid
output wire [31:0] hps_0_f2h_axi_slave_araddr, // .araddr
output wire [3:0] hps_0_f2h_axi_slave_arlen, // .arlen
output wire [2:0] hps_0_f2h_axi_slave_arsize, // .arsize
output wire [1:0] hps_0_f2h_axi_slave_arburst, // .arburst
output wire [1:0] hps_0_f2h_axi_slave_arlock, // .arlock
output wire [3:0] hps_0_f2h_axi_slave_arcache, // .arcache
output wire [2:0] hps_0_f2h_axi_slave_arprot, // .arprot
output wire [4:0] hps_0_f2h_axi_slave_aruser, // .aruser
output wire hps_0_f2h_axi_slave_arvalid, // .arvalid
input wire hps_0_f2h_axi_slave_arready, // .arready
input wire [7:0] hps_0_f2h_axi_slave_rid, // .rid
input wire [127:0] hps_0_f2h_axi_slave_rdata, // .rdata
input wire [1:0] hps_0_f2h_axi_slave_rresp, // .rresp
input wire hps_0_f2h_axi_slave_rlast, // .rlast
input wire hps_0_f2h_axi_slave_rvalid, // .rvalid
output wire hps_0_f2h_axi_slave_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset, // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
input wire hps_only_master_clk_reset_reset_bridge_in_reset_reset, // hps_only_master_clk_reset_reset_bridge_in_reset.reset
input wire hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
input wire [31:0] hps_only_master_master_address, // hps_only_master_master.address
output wire hps_only_master_master_waitrequest, // .waitrequest
input wire [3:0] hps_only_master_master_byteenable, // .byteenable
input wire hps_only_master_master_read, // .read
output wire [31:0] hps_only_master_master_readdata, // .readdata
output wire hps_only_master_master_readdatavalid, // .readdatavalid
input wire hps_only_master_master_write, // .write
input wire [31:0] hps_only_master_master_writedata // .writedata
);
wire hps_only_master_master_translator_avalon_universal_master_0_waitrequest; // hps_only_master_master_agent:av_waitrequest -> hps_only_master_master_translator:uav_waitrequest
wire [31:0] hps_only_master_master_translator_avalon_universal_master_0_readdata; // hps_only_master_master_agent:av_readdata -> hps_only_master_master_translator:uav_readdata
wire hps_only_master_master_translator_avalon_universal_master_0_debugaccess; // hps_only_master_master_translator:uav_debugaccess -> hps_only_master_master_agent:av_debugaccess
wire [31:0] hps_only_master_master_translator_avalon_universal_master_0_address; // hps_only_master_master_translator:uav_address -> hps_only_master_master_agent:av_address
wire hps_only_master_master_translator_avalon_universal_master_0_read; // hps_only_master_master_translator:uav_read -> hps_only_master_master_agent:av_read
wire [3:0] hps_only_master_master_translator_avalon_universal_master_0_byteenable; // hps_only_master_master_translator:uav_byteenable -> hps_only_master_master_agent:av_byteenable
wire hps_only_master_master_translator_avalon_universal_master_0_readdatavalid; // hps_only_master_master_agent:av_readdatavalid -> hps_only_master_master_translator:uav_readdatavalid
wire hps_only_master_master_translator_avalon_universal_master_0_lock; // hps_only_master_master_translator:uav_lock -> hps_only_master_master_agent:av_lock
wire hps_only_master_master_translator_avalon_universal_master_0_write; // hps_only_master_master_translator:uav_write -> hps_only_master_master_agent:av_write
wire [31:0] hps_only_master_master_translator_avalon_universal_master_0_writedata; // hps_only_master_master_translator:uav_writedata -> hps_only_master_master_agent:av_writedata
wire [2:0] hps_only_master_master_translator_avalon_universal_master_0_burstcount; // hps_only_master_master_translator:uav_burstcount -> hps_only_master_master_agent:av_burstcount
wire hps_only_master_master_agent_cp_valid; // hps_only_master_master_agent:cp_valid -> router:sink_valid
wire [119:0] hps_only_master_master_agent_cp_data; // hps_only_master_master_agent:cp_data -> router:sink_data
wire hps_only_master_master_agent_cp_ready; // router:sink_ready -> hps_only_master_master_agent:cp_ready
wire hps_only_master_master_agent_cp_startofpacket; // hps_only_master_master_agent:cp_startofpacket -> router:sink_startofpacket
wire hps_only_master_master_agent_cp_endofpacket; // hps_only_master_master_agent:cp_endofpacket -> router:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_write_rp_valid; // hps_0_f2h_axi_slave_agent:write_rp_valid -> router_001:sink_valid
wire [227:0] hps_0_f2h_axi_slave_agent_write_rp_data; // hps_0_f2h_axi_slave_agent:write_rp_data -> router_001:sink_data
wire hps_0_f2h_axi_slave_agent_write_rp_ready; // router_001:sink_ready -> hps_0_f2h_axi_slave_agent:write_rp_ready
wire hps_0_f2h_axi_slave_agent_write_rp_startofpacket; // hps_0_f2h_axi_slave_agent:write_rp_startofpacket -> router_001:sink_startofpacket
wire hps_0_f2h_axi_slave_agent_write_rp_endofpacket; // hps_0_f2h_axi_slave_agent:write_rp_endofpacket -> router_001:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_read_rp_valid; // hps_0_f2h_axi_slave_agent:read_rp_valid -> router_002:sink_valid
wire [227:0] hps_0_f2h_axi_slave_agent_read_rp_data; // hps_0_f2h_axi_slave_agent:read_rp_data -> router_002:sink_data
wire hps_0_f2h_axi_slave_agent_read_rp_ready; // router_002:sink_ready -> hps_0_f2h_axi_slave_agent:read_rp_ready
wire hps_0_f2h_axi_slave_agent_read_rp_startofpacket; // hps_0_f2h_axi_slave_agent:read_rp_startofpacket -> router_002:sink_startofpacket
wire hps_0_f2h_axi_slave_agent_read_rp_endofpacket; // hps_0_f2h_axi_slave_agent:read_rp_endofpacket -> router_002:sink_endofpacket
wire router_src_valid; // router:src_valid -> hps_only_master_master_limiter:cmd_sink_valid
wire [119:0] router_src_data; // router:src_data -> hps_only_master_master_limiter:cmd_sink_data
wire router_src_ready; // hps_only_master_master_limiter:cmd_sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> hps_only_master_master_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> hps_only_master_master_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> hps_only_master_master_limiter:cmd_sink_endofpacket
wire [119:0] hps_only_master_master_limiter_cmd_src_data; // hps_only_master_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire hps_only_master_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> hps_only_master_master_limiter:cmd_src_ready
wire [1:0] hps_only_master_master_limiter_cmd_src_channel; // hps_only_master_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire hps_only_master_master_limiter_cmd_src_startofpacket; // hps_only_master_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire hps_only_master_master_limiter_cmd_src_endofpacket; // hps_only_master_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_only_master_master_limiter:rsp_sink_valid
wire [119:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_only_master_master_limiter:rsp_sink_data
wire rsp_mux_src_ready; // hps_only_master_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_only_master_master_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_only_master_master_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_only_master_master_limiter:rsp_sink_endofpacket
wire hps_only_master_master_limiter_rsp_src_valid; // hps_only_master_master_limiter:rsp_src_valid -> hps_only_master_master_agent:rp_valid
wire [119:0] hps_only_master_master_limiter_rsp_src_data; // hps_only_master_master_limiter:rsp_src_data -> hps_only_master_master_agent:rp_data
wire hps_only_master_master_limiter_rsp_src_ready; // hps_only_master_master_agent:rp_ready -> hps_only_master_master_limiter:rsp_src_ready
wire [1:0] hps_only_master_master_limiter_rsp_src_channel; // hps_only_master_master_limiter:rsp_src_channel -> hps_only_master_master_agent:rp_channel
wire hps_only_master_master_limiter_rsp_src_startofpacket; // hps_only_master_master_limiter:rsp_src_startofpacket -> hps_only_master_master_agent:rp_startofpacket
wire hps_only_master_master_limiter_rsp_src_endofpacket; // hps_only_master_master_limiter:rsp_src_endofpacket -> hps_only_master_master_agent:rp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [119:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [119:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [1:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [119:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [119:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [1:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_valid
wire [119:0] cmd_mux_src_data; // cmd_mux:src_data -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_data
wire cmd_mux_src_ready; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_valid -> hps_0_f2h_axi_slave_agent:write_cp_valid
wire [227:0] hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_data -> hps_0_f2h_axi_slave_agent:write_cp_data
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready; // hps_0_f2h_axi_slave_agent:write_cp_ready -> hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_channel -> hps_0_f2h_axi_slave_agent:write_cp_channel
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_startofpacket -> hps_0_f2h_axi_slave_agent:write_cp_startofpacket
wire hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_wr_cmd_width_adapter:out_endofpacket -> hps_0_f2h_axi_slave_agent:write_cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_valid
wire [119:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_data
wire cmd_mux_001_src_ready; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire [1:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_valid -> hps_0_f2h_axi_slave_agent:read_cp_valid
wire [227:0] hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_data -> hps_0_f2h_axi_slave_agent:read_cp_data
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready; // hps_0_f2h_axi_slave_agent:read_cp_ready -> hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_channel -> hps_0_f2h_axi_slave_agent:read_cp_channel
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_startofpacket -> hps_0_f2h_axi_slave_agent:read_cp_startofpacket
wire hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_rd_cmd_width_adapter:out_endofpacket -> hps_0_f2h_axi_slave_agent:read_cp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_valid
wire [227:0] router_001_src_data; // router_001:src_data -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_data
wire router_001_src_ready; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire [119:0] hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_wr_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_valid
wire [227:0] router_002_src_data; // router_002:src_data -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_data
wire router_002_src_ready; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:in_endofpacket
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire [119:0] hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_ready
wire [1:0] hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket; // hps_0_f2h_axi_slave_rd_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire [1:0] hps_only_master_master_limiter_cmd_valid_data; // hps_only_master_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) hps_only_master_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hps_only_master_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (hps_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (hps_only_master_master_translator_avalon_universal_master_0_read), // .read
.uav_write (hps_only_master_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (hps_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (hps_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (hps_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (hps_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (hps_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (hps_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (hps_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (hps_only_master_master_address), // avalon_anti_master_0.address
.av_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.av_byteenable (hps_only_master_master_byteenable), // .byteenable
.av_read (hps_only_master_master_read), // .read
.av_readdata (hps_only_master_master_readdata), // .readdata
.av_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.av_write (hps_only_master_master_write), // .write
.av_writedata (hps_only_master_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_QOS_H (104),
.PKT_QOS_L (104),
.PKT_DATA_SIDEBAND_H (102),
.PKT_DATA_SIDEBAND_L (102),
.PKT_ADDR_SIDEBAND_H (101),
.PKT_ADDR_SIDEBAND_L (97),
.PKT_BURST_TYPE_H (96),
.PKT_BURST_TYPE_L (95),
.PKT_CACHE_H (114),
.PKT_CACHE_L (111),
.PKT_THREAD_ID_H (107),
.PKT_THREAD_ID_L (107),
.PKT_BURST_SIZE_H (94),
.PKT_BURST_SIZE_L (92),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (103),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (91),
.PKT_BURSTWRAP_L (83),
.PKT_BYTE_CNT_H (82),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (105),
.PKT_SRC_ID_L (105),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (106),
.ST_DATA_W (120),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (511),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hps_only_master_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (hps_only_master_master_translator_avalon_universal_master_0_address), // av.address
.av_write (hps_only_master_master_translator_avalon_universal_master_0_write), // .write
.av_read (hps_only_master_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (hps_only_master_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (hps_only_master_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (hps_only_master_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (hps_only_master_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (hps_only_master_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (hps_only_master_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (hps_only_master_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (hps_only_master_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (hps_only_master_master_agent_cp_valid), // cp.valid
.cp_data (hps_only_master_master_agent_cp_data), // .data
.cp_startofpacket (hps_only_master_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (hps_only_master_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (hps_only_master_master_agent_cp_ready), // .ready
.rp_valid (hps_only_master_master_limiter_rsp_src_valid), // rp.valid
.rp_data (hps_only_master_master_limiter_rsp_src_data), // .data
.rp_channel (hps_only_master_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (hps_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (hps_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (hps_only_master_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_axi_slave_ni #(
.PKT_QOS_H (212),
.PKT_QOS_L (212),
.PKT_THREAD_ID_H (215),
.PKT_THREAD_ID_L (215),
.PKT_RESPONSE_STATUS_H (224),
.PKT_RESPONSE_STATUS_L (223),
.PKT_BEGIN_BURST (211),
.PKT_CACHE_H (222),
.PKT_CACHE_L (219),
.PKT_DATA_SIDEBAND_H (210),
.PKT_DATA_SIDEBAND_L (210),
.PKT_ADDR_SIDEBAND_H (209),
.PKT_ADDR_SIDEBAND_L (205),
.PKT_BURST_TYPE_H (204),
.PKT_BURST_TYPE_L (203),
.PKT_PROTECTION_H (218),
.PKT_PROTECTION_L (216),
.PKT_BURST_SIZE_H (202),
.PKT_BURST_SIZE_L (200),
.PKT_BURSTWRAP_H (199),
.PKT_BURSTWRAP_L (191),
.PKT_BYTE_CNT_H (190),
.PKT_BYTE_CNT_L (182),
.PKT_ADDR_H (175),
.PKT_ADDR_L (144),
.PKT_TRANS_EXCLUSIVE (181),
.PKT_TRANS_LOCK (180),
.PKT_TRANS_COMPRESSED_READ (176),
.PKT_TRANS_POSTED (177),
.PKT_TRANS_WRITE (178),
.PKT_TRANS_READ (179),
.PKT_DATA_H (127),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (143),
.PKT_BYTEEN_L (128),
.PKT_SRC_ID_H (213),
.PKT_SRC_ID_L (213),
.PKT_DEST_ID_H (214),
.PKT_DEST_ID_L (214),
.PKT_ORI_BURST_SIZE_L (225),
.PKT_ORI_BURST_SIZE_H (227),
.ADDR_USER_WIDTH (5),
.DATA_USER_WIDTH (1),
.ST_DATA_W (228),
.ADDR_WIDTH (32),
.RDATA_WIDTH (128),
.WDATA_WIDTH (128),
.ST_CHANNEL_W (2),
.AXI_SLAVE_ID_W (8),
.PASS_ID_TO_SLAVE (0),
.AXI_VERSION ("AXI3"),
.WRITE_ACCEPTANCE_CAPABILITY (8),
.READ_ACCEPTANCE_CAPABILITY (8)
) hps_0_f2h_axi_slave_agent (
.aclk (clk_0_clk_clk), // clock_sink.clk
.aresetn (~hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // reset_sink.reset_n
.read_cp_valid (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid), // read_cp.valid
.read_cp_ready (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready), // .ready
.read_cp_data (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data), // .data
.read_cp_channel (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel), // .channel
.read_cp_startofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket), // .endofpacket
.write_cp_ready (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready), // write_cp.ready
.write_cp_valid (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid), // .valid
.write_cp_data (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data), // .data
.write_cp_channel (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel), // .channel
.write_cp_startofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket), // .endofpacket
.read_rp_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // read_rp.ready
.read_rp_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.read_rp_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.read_rp_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.write_rp_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // write_rp.ready
.write_rp_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.write_rp_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.write_rp_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.awid (hps_0_f2h_axi_slave_awid), // altera_axi_master.awid
.awaddr (hps_0_f2h_axi_slave_awaddr), // .awaddr
.awlen (hps_0_f2h_axi_slave_awlen), // .awlen
.awsize (hps_0_f2h_axi_slave_awsize), // .awsize
.awburst (hps_0_f2h_axi_slave_awburst), // .awburst
.awlock (hps_0_f2h_axi_slave_awlock), // .awlock
.awcache (hps_0_f2h_axi_slave_awcache), // .awcache
.awprot (hps_0_f2h_axi_slave_awprot), // .awprot
.awuser (hps_0_f2h_axi_slave_awuser), // .awuser
.awvalid (hps_0_f2h_axi_slave_awvalid), // .awvalid
.awready (hps_0_f2h_axi_slave_awready), // .awready
.wid (hps_0_f2h_axi_slave_wid), // .wid
.wdata (hps_0_f2h_axi_slave_wdata), // .wdata
.wstrb (hps_0_f2h_axi_slave_wstrb), // .wstrb
.wlast (hps_0_f2h_axi_slave_wlast), // .wlast
.wvalid (hps_0_f2h_axi_slave_wvalid), // .wvalid
.wready (hps_0_f2h_axi_slave_wready), // .wready
.bid (hps_0_f2h_axi_slave_bid), // .bid
.bresp (hps_0_f2h_axi_slave_bresp), // .bresp
.bvalid (hps_0_f2h_axi_slave_bvalid), // .bvalid
.bready (hps_0_f2h_axi_slave_bready), // .bready
.arid (hps_0_f2h_axi_slave_arid), // .arid
.araddr (hps_0_f2h_axi_slave_araddr), // .araddr
.arlen (hps_0_f2h_axi_slave_arlen), // .arlen
.arsize (hps_0_f2h_axi_slave_arsize), // .arsize
.arburst (hps_0_f2h_axi_slave_arburst), // .arburst
.arlock (hps_0_f2h_axi_slave_arlock), // .arlock
.arcache (hps_0_f2h_axi_slave_arcache), // .arcache
.arprot (hps_0_f2h_axi_slave_arprot), // .arprot
.aruser (hps_0_f2h_axi_slave_aruser), // .aruser
.arvalid (hps_0_f2h_axi_slave_arvalid), // .arvalid
.arready (hps_0_f2h_axi_slave_arready), // .arready
.rid (hps_0_f2h_axi_slave_rid), // .rid
.rdata (hps_0_f2h_axi_slave_rdata), // .rdata
.rresp (hps_0_f2h_axi_slave_rresp), // .rresp
.rlast (hps_0_f2h_axi_slave_rlast), // .rlast
.rvalid (hps_0_f2h_axi_slave_rvalid), // .rvalid
.rready (hps_0_f2h_axi_slave_rready) // .rready
);
soc_system_mm_interconnect_1_router router (
.sink_ready (hps_only_master_master_agent_cp_ready), // sink.ready
.sink_valid (hps_only_master_master_agent_cp_valid), // .valid
.sink_data (hps_only_master_master_agent_cp_data), // .data
.sink_startofpacket (hps_only_master_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_only_master_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_001 router_001 (
.sink_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_001 router_002 (
.sink_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (106),
.PKT_SRC_ID_H (105),
.PKT_SRC_ID_L (105),
.PKT_BYTE_CNT_H (82),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (16),
.PIPELINED (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (1),
.REORDER (0)
) hps_only_master_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_only_master_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_only_master_master_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_only_master_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_only_master_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_only_master_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_only_master_master_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_only_master_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_only_master_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_only_master_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_only_master_master_limiter_cmd_valid_data) // cmd_valid.data
);
soc_system_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_only_master_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_only_master_master_limiter_cmd_src_channel), // .channel
.sink_data (hps_only_master_master_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_only_master_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_only_master_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_only_master_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel), // .channel
.sink_data (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel), // .channel
.sink_data (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_only_master_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (82),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (91),
.IN_PKT_BURSTWRAP_L (83),
.IN_PKT_BURST_SIZE_H (94),
.IN_PKT_BURST_SIZE_L (92),
.IN_PKT_RESPONSE_STATUS_H (116),
.IN_PKT_RESPONSE_STATUS_L (115),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (96),
.IN_PKT_BURST_TYPE_L (95),
.IN_PKT_ORI_BURST_SIZE_L (117),
.IN_PKT_ORI_BURST_SIZE_H (119),
.IN_ST_DATA_W (120),
.OUT_PKT_ADDR_H (175),
.OUT_PKT_ADDR_L (144),
.OUT_PKT_DATA_H (127),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (143),
.OUT_PKT_BYTEEN_L (128),
.OUT_PKT_BYTE_CNT_H (190),
.OUT_PKT_BYTE_CNT_L (182),
.OUT_PKT_TRANS_COMPRESSED_READ (176),
.OUT_PKT_BURST_SIZE_H (202),
.OUT_PKT_BURST_SIZE_L (200),
.OUT_PKT_RESPONSE_STATUS_H (224),
.OUT_PKT_RESPONSE_STATUS_L (223),
.OUT_PKT_TRANS_EXCLUSIVE (181),
.OUT_PKT_BURST_TYPE_H (204),
.OUT_PKT_BURST_TYPE_L (203),
.OUT_PKT_ORI_BURST_SIZE_L (225),
.OUT_PKT_ORI_BURST_SIZE_H (227),
.OUT_ST_DATA_W (228),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_wr_cmd_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_wr_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (82),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (91),
.IN_PKT_BURSTWRAP_L (83),
.IN_PKT_BURST_SIZE_H (94),
.IN_PKT_BURST_SIZE_L (92),
.IN_PKT_RESPONSE_STATUS_H (116),
.IN_PKT_RESPONSE_STATUS_L (115),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (96),
.IN_PKT_BURST_TYPE_L (95),
.IN_PKT_ORI_BURST_SIZE_L (117),
.IN_PKT_ORI_BURST_SIZE_H (119),
.IN_ST_DATA_W (120),
.OUT_PKT_ADDR_H (175),
.OUT_PKT_ADDR_L (144),
.OUT_PKT_DATA_H (127),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (143),
.OUT_PKT_BYTEEN_L (128),
.OUT_PKT_BYTE_CNT_H (190),
.OUT_PKT_BYTE_CNT_L (182),
.OUT_PKT_TRANS_COMPRESSED_READ (176),
.OUT_PKT_BURST_SIZE_H (202),
.OUT_PKT_BURST_SIZE_L (200),
.OUT_PKT_RESPONSE_STATUS_H (224),
.OUT_PKT_RESPONSE_STATUS_L (223),
.OUT_PKT_TRANS_EXCLUSIVE (181),
.OUT_PKT_BURST_TYPE_H (204),
.OUT_PKT_BURST_TYPE_L (203),
.OUT_PKT_ORI_BURST_SIZE_L (225),
.OUT_PKT_ORI_BURST_SIZE_H (227),
.OUT_ST_DATA_W (228),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_rd_cmd_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_rd_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (175),
.IN_PKT_ADDR_L (144),
.IN_PKT_DATA_H (127),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (143),
.IN_PKT_BYTEEN_L (128),
.IN_PKT_BYTE_CNT_H (190),
.IN_PKT_BYTE_CNT_L (182),
.IN_PKT_TRANS_COMPRESSED_READ (176),
.IN_PKT_BURSTWRAP_H (199),
.IN_PKT_BURSTWRAP_L (191),
.IN_PKT_BURST_SIZE_H (202),
.IN_PKT_BURST_SIZE_L (200),
.IN_PKT_RESPONSE_STATUS_H (224),
.IN_PKT_RESPONSE_STATUS_L (223),
.IN_PKT_TRANS_EXCLUSIVE (181),
.IN_PKT_BURST_TYPE_H (204),
.IN_PKT_BURST_TYPE_L (203),
.IN_PKT_ORI_BURST_SIZE_L (225),
.IN_PKT_ORI_BURST_SIZE_H (227),
.IN_ST_DATA_W (228),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (82),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (94),
.OUT_PKT_BURST_SIZE_L (92),
.OUT_PKT_RESPONSE_STATUS_H (116),
.OUT_PKT_RESPONSE_STATUS_L (115),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (96),
.OUT_PKT_BURST_TYPE_L (95),
.OUT_PKT_ORI_BURST_SIZE_L (117),
.OUT_PKT_ORI_BURST_SIZE_H (119),
.OUT_ST_DATA_W (120),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_wr_rsp_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_wr_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (175),
.IN_PKT_ADDR_L (144),
.IN_PKT_DATA_H (127),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (143),
.IN_PKT_BYTEEN_L (128),
.IN_PKT_BYTE_CNT_H (190),
.IN_PKT_BYTE_CNT_L (182),
.IN_PKT_TRANS_COMPRESSED_READ (176),
.IN_PKT_BURSTWRAP_H (199),
.IN_PKT_BURSTWRAP_L (191),
.IN_PKT_BURST_SIZE_H (202),
.IN_PKT_BURST_SIZE_L (200),
.IN_PKT_RESPONSE_STATUS_H (224),
.IN_PKT_RESPONSE_STATUS_L (223),
.IN_PKT_TRANS_EXCLUSIVE (181),
.IN_PKT_BURST_TYPE_H (204),
.IN_PKT_BURST_TYPE_L (203),
.IN_PKT_ORI_BURST_SIZE_L (225),
.IN_PKT_ORI_BURST_SIZE_H (227),
.IN_ST_DATA_W (228),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (82),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (94),
.OUT_PKT_BURST_SIZE_L (92),
.OUT_PKT_RESPONSE_STATUS_H (116),
.OUT_PKT_RESPONSE_STATUS_L (115),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (96),
.OUT_PKT_BURST_TYPE_L (95),
.OUT_PKT_ORI_BURST_SIZE_L (117),
.OUT_PKT_ORI_BURST_SIZE_H (119),
.OUT_ST_DATA_W (120),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) hps_0_f2h_axi_slave_rd_rsp_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_data), // .data
.out_channel (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_channel), // .channel
.out_valid (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_valid), // .valid
.out_ready (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (hps_0_f2h_axi_slave_rd_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A221OI_TB_V
`define SKY130_FD_SC_HDLL__A221OI_TB_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a221oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hdll__a221oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A221OI_TB_V
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