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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_1_V
`define SKY130_FD_SC_LS__A221OI_1_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_1_V
|
`define bsg_mul_booth_gen_macro(name,blocks,S_above,dot_bar,b_vec,one_vec) \
if ( blocks == blocks_p && S_above == S_above_vec_p \
&& dot_bar == dot_bar_vec_p && b_vec == B_vec_p && one_vec == one_vec_p) \
begin : macro \
name``_b``blocks b4b (.*); \
end
module bsg_mul_booth_4_block_rep #(parameter [31:0] blocks_p=1
,parameter S_above_vec_p=0
,parameter dot_bar_vec_p=0
,parameter B_vec_p=0
,parameter one_vec_p=0
)
( input [4:0][2:0] SDN_i
, input cr_i
, input [blocks_p-1:0][3:0][1:0] y_vec_i
, output cl_o
, output [blocks_p-1:0] c_o
, output [blocks_p-1:0] s_o
);
genvar i;
wire [blocks_p:0] ci_local;
`bsg_mul_booth_gen_macro(bsg_rp_tsmc_250_booth_4_block,5,0,0,0,0)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_250_booth_4_block,6,0,0,0,0)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_250_booth_4_block,7,0,0,0,0)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_250_booth_4_block,8,0,0,0,0)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_250_booth_4_block_cornice,8,32'b0000_1000_0000_0100_0000_0010_0000_0001,32'b0000_0000_0000_0000_0000_0000_0000_0000,32'b1000_0000_1100_1000_1110_1100_1111_1110,32'b0000_0000_0000_0000_0000_0000_0000_0000)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_250_booth_4_block_cornice,6,24'b0000_1000_0000_0100_0000_0010,24'b0000_0000_0000_0000_0000_0000,24'b1000_0000_1100_1000_1110_1100,24'b0000_0000_0000_0000_0000_0000)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_250_booth_4_block_end_cornice,7,28'b0000_0000_0000_0000_0000_0000_0000,28'b1000_0000_0100_0000_0010_0000_0001,28'b0111_0011_0011_0001_0001_0000_0000,28'b0000_0100_0000_0010_0000_0001_0000)
else `bsg_mul_booth_gen_macro(bsg_rp_tsmc_250_booth_4_block_end_cornice,8,32'b0000_0000_0000_0000_0000_0000_0000_0000,32'b0000_1000_0000_0100_0000_0010_0000_0001,32'b0111_0111_0011_0011_0001_0001_0000_0000,32'b1000_0000_0100_0000_0010_0000_0001_0000)
else
// some cases are too complex to spend time on handling;
// so we fall back to some default code.
// warning: this code has some replication with
// the main line bsg_mul code.
begin: notmacro
for (i = 0; i < blocks_p; i=i+1)
begin: rof
localparam S_above_vec_tmp = (S_above_vec_p >> (i << 2)) & 4'hf;
localparam S_dot_bar_vec_tmp = (dot_bar_vec_p >> (i << 2)) & 4'hf;
localparam B_vec_tmp = (B_vec_p >> (i << 2)) & 4'hf;
localparam one_vec_tmp = (one_vec_p >> (i << 2)) & 4'hf;
bsg_mul_booth_4_block #(
.S_above_vec_p(S_above_vec_tmp)
,.dot_bar_vec_p(S_dot_bar_vec_tmp)
,.B_vec_p(B_vec_tmp)
,.one_vec_p(one_vec_tmp)
)
b4b (.SDN_i(SDN_i), .y_i (y_vec_i[i])
, .cr_i(ci_local[i]), .cl_o(ci_local[i+1]), .c_o (c_o[i]), .s_o (s_o[i]));
end // block: rof
assign ci_local[0] = cr_i;
assign cl_o = ci_local[blocks_p];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_2_V
`define SKY130_FD_SC_HD__DLXTN_2_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxtn_2 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxtn_2 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:50:03 03/02/2016
// Design Name:
// Module Name: Control_visualizador_numerico
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Control_visualizador_numerico
(
input wire [3:0] cuenta_frec,
input wire [3:0] cuenta_CT,
input wire clock,
input wire reset,
input wire funct_select,
output wire [7:0] code_digitos_decimal, //secuencia para mostrar el digito correcto
output wire [3:0] code_7seg //secuencia para encender el 7 segmentos correcto
);
wire [3:0] OutFSM_InConversorBCD; //Conexion entre la maquina de estados y el conversor BCD a 7 segmentos
FSM Instancia_FSM
(
.clk(clock),
.rst(reset),
.Funct_Select(funct_select),
.Count_CT(cuenta_CT),
.Count_F(cuenta_frec),
.C_Digit(OutFSM_InConversorBCD),
.C_7Seg(code_7seg)
);
Conversor_BCD_7seg Instancia_Conversor_BCD_7seg
(
.Valor_Decimal(OutFSM_InConversorBCD),
.Code_7seg(code_digitos_decimal)
);
endmodule
|
module simple_alu(clk, reset_n, opcode_valid, opcode, data, done, result, overflow);
parameter DATA_WIDTH = 8;
input clk;
input reset_n;
input opcode_valid;
input opcode;
input [DATA_WIDTH-1:0] data;
output done;
output [DATA_WIDTH-1:0] result;
output overflow;
reg overflow;
wire overflow_buf;
reg done;
reg [DATA_WIDTH-1:0] result;
parameter ON = 1'b1;
parameter OFF = 1'b0;
parameter
RESET = 4'b0000,
IDLE = 4'b0001,
DATA_A = 4'b0010,
DATA_B = 4'b0011,
ADD = 4'b0100,
SUB = 4'b0101,
PAR = 4'b0110,
COMP = 4'b0111,
DONE = 4'b1000;
//parameter
// ADD = 2'b00,
// SUB = 2'b01,
// PAR = 2'b10,
// COMP = 2'b11;
reg [3:0] State, NextState;
reg [DATA_WIDTH-1:0] A_Data, B_Data;
reg [1:0] opcode_def;
reg store_a_def, store_b_def;
wire [DATA_WIDTH-1:0] result_def;
reg [1:0] opcode_buf;
reg store_a, store_b;
reg start;
wire alu_done;
reg first;
always @(posedge clk or reset_n)
begin
if(!reset_n)
begin
State = RESET;
end
else
begin
State = NextState;
end
end
always @(State or opcode_valid or reset_n or alu_done)
begin
case(State)
RESET:
begin
if(reset_n)
begin
NextState = IDLE;
end
else
begin
NextState = RESET;
end
end
IDLE:
begin
if(opcode_valid)
begin
NextState = DATA_A;
end
else
begin
NextState = IDLE;
end
end
DATA_A:
begin
if(opcode_valid)
begin
NextState = DATA_B;
opcode_buf[0] = opcode;
end
else
begin
NextState = IDLE;
end
end
DATA_B:
begin
opcode_buf[1] = opcode;
if(opcode_valid)
begin
case(opcode_buf)
2'b00:
begin
NextState = ADD;
end
2'b01:
begin
NextState = SUB;
end
2'b10:
begin
NextState = PAR;
end
2'b11:
begin
NextState = COMP;
end
endcase
end
else
begin
NextState = IDLE;
end
end
ADD:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = ADD;
end
end
SUB:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = SUB;
end
end
PAR:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = PAR;
end
end
COMP:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = COMP;
end
end
DONE:
begin
NextState = IDLE;
end
endcase
end
always @(State)
begin
case(State)
RESET:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = ADD;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
IDLE:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = ADD;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
DATA_A:
begin
store_a_def = ON;
store_b_def = OFF;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
DATA_B:
begin
store_a_def = OFF;
store_b_def = ON;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
ADD:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = ADD;
start = 1'b1;
result = 0;
done = OFF;
overflow = OFF;
end
SUB:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = SUB;
start = ON;
result = 0;
done = OFF;
overflow = OFF;
end
PAR:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = PAR;
start = ON;
result = 0;
done = OFF;
overflow = OFF;
end
COMP:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = COMP;
start = ON;
result = 0;
done = OFF;
overflow = OFF;
end
DONE:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = 2'b00;
start = OFF;
result = result_def;
done = ON;
overflow = overflow_buf;
end
endcase
end
alu_datapath #(DATA_WIDTH) alu_datapath (
.clk(clk),
.alu_data(data),
.opcode_value(opcode_def),
.store_a(store_a_def),
.store_b(store_b_def),
.start(start),
.alu_done(alu_done),
.result(result_def),
.overflow_def(overflow_buf)
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: VGA_Audio_PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.1 Build 156 04/30/2007 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module VGA_Audio_PLL (
areset,
inclk0,
c0,
c1,
c2);
input areset;
input inclk0;
output c0;
output c1;
output c2;
wire [5:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.areset (areset),
.clk (sub_wire0),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b1),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 15,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 14,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 3,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 15,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 14,
altpll_component.clk2_phase_shift = "-9921",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "6"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.20000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.20000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "15"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-9921"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL_wave*.jpg FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRBP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFRBP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRBP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_FUNCTIONAL_PP_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:22:22 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
shift_value_SHT2_EWR_4_, left_right_SHT2, SIGN_FLAG_SHT2,
OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n494,
n499, n512, n513, n514, n515, n516, n517, n518, n519, n520, n521,
n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532,
n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578,
n579, n580, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n769, n770,
n795, n797, n798, n799, n800, n801, n802, n803, n804, n805, n806,
n807, n808, n809, n810, n811, n812, n813, n814, n815, n816, n817,
n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828,
n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839,
n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850,
n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n861,
n862, n863, n864, n865, n866, n868, n869, n870, n871, n872, n878,
n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n898, n900, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n913, n914, n915, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1036, n1037, n1038, n1039, n1040, n1041, n1042,
n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052,
n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062,
n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072,
n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082,
n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092,
n1093, n1094, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103,
n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1264, n1265, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346,
n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396,
n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406,
n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426,
n1427, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628,
n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638,
n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648,
n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718,
n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758,
n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768,
n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778,
n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788,
n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798,
n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808,
n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818,
n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828,
n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838,
n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848,
n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858,
n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868,
n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878,
n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888,
n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898,
n1899, n1900, n1901, n1902, n1904, n1905, n1906, n1907, n1908, n1909,
n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919,
n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929,
n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939,
n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949,
n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959,
n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969,
n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979,
n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989,
n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999,
n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009,
n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079,
n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089,
n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099,
n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109,
n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119,
n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129,
n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139,
n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149,
n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159,
n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169,
n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179,
n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189,
n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209,
n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219,
n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229,
n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239,
n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259,
n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269,
n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279,
n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289,
n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299,
n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309,
n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319,
n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369,
n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379,
n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389,
n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399,
n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409,
n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419,
n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2429, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2751, n2752, n2753, n2754, n2755, n2756,
n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766,
n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776,
n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786,
n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796,
n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806,
n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816,
n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826,
n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836,
n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846,
n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856,
n2857, n2858, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867,
n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877,
n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887,
n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897,
n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907,
n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917,
n2918, n2919, n2920, n2921, n2922, n2924, n2925, n2926, n2927, n2928,
n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938,
n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948,
n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958,
n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968,
n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978,
n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988,
n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998,
n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008,
n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018,
n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028,
n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038,
n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048,
n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058,
n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [27:1] DMP_EXP_EWSW;
wire [27:1] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [11:8] DmP_mant_SFG_SWR_signed;
wire [10:9] Raw_mant_SGF;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n2919), .Q(
Shift_reg_FLAGS_7_6), .QN(n2640) );
DFFRX2TS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n2917), .Q(
Shift_reg_FLAGS_7[3]), .QN(n2532) );
DFFRX2TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n2902),
.Q(Shift_amount_SHT1_EWR[1]), .QN(n2655) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n2903),
.Q(Shift_amount_SHT1_EWR[4]), .QN(n2614) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n2904), .Q(
DMP_EXP_EWSW[1]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n2907), .Q(
DMP_EXP_EWSW[9]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n2910), .Q(
DMP_EXP_EWSW[13]) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1420), .Q(
OP_FLAG_EXP) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n2888), .Q(
ZERO_FLAG_EXP), .QN(n2611) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n2903), .Q(
DMP_SHT1_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n2903), .Q(
DMP_SHT2_EWSW[0]), .QN(n2535) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n2903), .Q(
DMP_SFG[0]), .QN(n2618) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n2904), .Q(
DMP_SHT1_EWSW[1]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n2904), .Q(
DMP_SHT2_EWSW[1]), .QN(n2534) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n2904), .Q(
DMP_SFG[1]), .QN(n2619) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n2904), .Q(
DMP_SHT1_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n2904), .Q(
DMP_SHT2_EWSW[2]), .QN(n2533) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n2904), .Q(
DMP_SFG[2]), .QN(n2617) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n2905), .Q(
DMP_SHT1_EWSW[3]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n2898), .Q(
DMP_SHT2_EWSW[3]), .QN(n2555) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n2896), .Q(
DMP_SHT1_EWSW[4]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n2696), .Q(
DMP_SHT2_EWSW[4]), .QN(n2554) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n2896), .Q(
DMP_SFG[4]), .QN(n2631) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n2887), .Q(
DMP_SHT1_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n2910), .Q(
DMP_SHT2_EWSW[5]), .QN(n2553) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n2887), .Q(
DMP_SFG[5]), .QN(n2674) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n2887), .Q(
DMP_SHT1_EWSW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1420), .Q(
DMP_SHT2_EWSW[6]), .QN(n2552) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1420), .Q(
DMP_SFG[6]), .QN(n2689) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n2906), .Q(
DMP_SHT1_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n2895), .Q(
DMP_SHT2_EWSW[7]), .QN(n2551) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n2906), .Q(
DMP_SFG[7]), .QN(n2693) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n2898), .Q(
DMP_SHT1_EWSW[8]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n2898), .Q(
DMP_SFG[8]), .QN(n2692) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n2907), .Q(
DMP_SHT1_EWSW[9]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n2907), .Q(
DMP_SHT2_EWSW[9]), .QN(n2550) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n2907), .Q(
DMP_SHT1_EWSW[10]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n2907), .Q(
DMP_SHT2_EWSW[10]), .QN(n2549) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n2907), .Q(
DMP_SFG[10]), .QN(n2630) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n2699), .Q(
DMP_SHT1_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n2907), .Q(
DMP_SHT2_EWSW[11]), .QN(n2548) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n2702), .Q(
DMP_SHT1_EWSW[12]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n2702), .Q(
DMP_SHT2_EWSW[12]), .QN(n2547) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n2908), .Q(
DMP_SHT1_EWSW[13]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1409), .Q(
DMP_SFG[13]), .QN(n2677) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n2891), .Q(
DMP_SHT1_EWSW[14]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n2891), .Q(
DMP_SHT2_EWSW[14]), .QN(n2563) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n2891), .Q(
DMP_SFG[14]), .QN(n2634) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n2892), .Q(
DMP_SHT1_EWSW[15]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n2891), .Q(
DMP_SHT2_EWSW[15]), .QN(n2562) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n2891), .Q(
DMP_SFG[15]), .QN(n2638) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n2892), .Q(
DMP_SHT1_EWSW[16]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n2892), .Q(
DMP_SHT2_EWSW[16]), .QN(n2561) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n2892), .Q(
DMP_SFG[16]), .QN(n2635) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n2892), .Q(
DMP_SHT1_EWSW[17]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n2892), .Q(
DMP_SHT2_EWSW[17]), .QN(n2560) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n2892), .Q(
DMP_SFG[17]), .QN(n2637) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n2893), .Q(
DMP_SHT1_EWSW[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n2893), .Q(
DMP_SFG[18]), .QN(n2633) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n2893), .Q(
DMP_SHT1_EWSW[19]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n2893), .Q(
DMP_SHT2_EWSW[19]), .QN(n2558) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n2893), .Q(
DMP_SFG[19]), .QN(n2676) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n2894), .Q(
DMP_SHT1_EWSW[20]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n2893), .Q(
DMP_SHT2_EWSW[20]), .QN(n2557) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n2893), .Q(
DMP_SFG[20]), .QN(n2636) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n2894), .Q(
DMP_SHT1_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n2894), .Q(
DMP_SHT2_EWSW[21]), .QN(n2556) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n2894), .Q(
DMP_SFG[21]), .QN(n2675) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n2894), .Q(
DMP_SHT1_EWSW[22]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n2894), .Q(
DMP_SHT2_EWSW[22]), .QN(n2536) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n2894), .Q(
DMP_SFG[22]), .QN(n2615) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n2909), .Q(
DMP_SHT1_EWSW[23]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n2909), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n2909), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1304) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n2905), .Q(
DMP_SHT1_EWSW[24]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n2909), .Q(
DMP_SHT2_EWSW[24]), .QN(n2544) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n2909), .Q(
DMP_exp_NRM_EW[1]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n2909), .Q(
DMP_exp_NRM2_EW[1]), .QN(n2879) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n2898), .Q(
DMP_exp_NRM_EW[2]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n2911), .Q(
DMP_SHT1_EWSW[26]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n2911), .Q(
DMP_SHT2_EWSW[26]), .QN(n2543) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n2696), .Q(
DMP_exp_NRM_EW[3]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n2911), .Q(
DMP_SHT1_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n2911), .Q(
DMP_SHT2_EWSW[27]), .QN(n2542) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n2911), .Q(
DMP_exp_NRM_EW[4]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n2912), .Q(
DMP_SHT1_EWSW[28]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n2912), .Q(
DMP_exp_NRM_EW[5]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n2912), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n2913), .Q(
DMP_SHT1_EWSW[29]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n2912), .Q(
DMP_SHT2_EWSW[29]), .QN(n2540) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n2912), .Q(
DMP_exp_NRM_EW[6]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n2912), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1644) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n2913), .Q(
DMP_SHT1_EWSW[30]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n2913), .Q(
DMP_SHT2_EWSW[30]), .QN(n2539) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n2913), .Q(
DMP_exp_NRM_EW[7]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n2913), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1421), .Q(
DmP_mant_SHT1_SW[0]), .QN(n2610) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1421), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1421), .Q(
DmP_mant_SHT1_SW[2]), .QN(n2608) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1437), .Q(
DmP_mant_SHT1_SW[3]), .QN(n2598) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n2906), .Q(
DmP_EXP_EWSW[6]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1435), .Q(
DmP_mant_SHT1_SW[6]), .QN(n2609) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1424), .Q(
DmP_mant_SHT1_SW[7]), .QN(n2603) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n2704), .Q(
DmP_mant_SHT1_SW[8]), .QN(n2628) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1421), .Q(
DmP_mant_SHT1_SW[11]), .QN(n2641) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1406), .Q(
DmP_EXP_EWSW[12]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1408), .Q(
DmP_mant_SHT1_SW[12]), .QN(n2604) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n2902), .Q(
DmP_mant_SHT1_SW[16]), .QN(n2602) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n2917), .Q(
DmP_mant_SHT1_SW[19]), .QN(n2629) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n3068), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n2903), .Q(
DmP_EXP_EWSW[27]) );
DFFRX4TS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n2888), .Q(
overflow_flag) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n2898), .Q(
ZERO_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n2895), .Q(
ZERO_FLAG_SHT2), .QN(n2564) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n2887), .Q(
ZERO_FLAG_NRM) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n550), .CK(clk), .RN(n1420), .Q(
OP_FLAG_SHT2), .QN(n2567) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n2897), .Q(
SIGN_FLAG_SHT1) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n3068), .Q(
SIGN_FLAG_NRM) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n2902), .Q(
Raw_mant_NRM_SWR[4]), .QN(n2529) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n2902), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1308) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n2902), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1309) );
DFFRXLTS R_135 ( .D(n480), .CK(clk), .RN(n1436), .QN(n2623) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n2890), .Q(
DmP_mant_SFG_SWR[19]), .QN(n2659) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n2891), .Q(
DmP_mant_SFG_SWR[22]), .QN(n2658) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n2891), .Q(
DmP_mant_SFG_SWR[25]), .QN(n2613) );
DFFRX4TS R_306 ( .D(n2377), .CK(clk), .RN(n1420), .Q(n2920), .QN(n1401) );
DFFRXLTS R_8 ( .D(n474), .CK(clk), .RN(n1437), .QN(n2625) );
DFFSX2TS R_15 ( .D(n3012), .CK(clk), .SN(n2702), .Q(n2871) );
DFFSX2TS R_16 ( .D(n3011), .CK(clk), .SN(n928), .Q(n2870) );
DFFSX2TS R_18 ( .D(n3010), .CK(clk), .SN(n2896), .Q(n2869) );
DFFSX2TS R_21 ( .D(n2947), .CK(clk), .SN(n1409), .Q(n2867) );
DFFSX2TS R_37 ( .D(n2928), .CK(clk), .SN(n1424), .QN(n957) );
DFFSX1TS R_40 ( .D(n3023), .CK(clk), .SN(n1410), .Q(n2858) );
DFFSX2TS R_41 ( .D(n3022), .CK(clk), .SN(n930), .Q(n2857) );
DFFSX1TS R_46 ( .D(n3017), .CK(clk), .SN(n2702), .Q(n2854) );
DFFSX2TS R_49 ( .D(n3015), .CK(clk), .SN(n2908), .Q(n2852) );
DFFSX2TS R_47 ( .D(n3016), .CK(clk), .SN(n1436), .Q(n2853) );
DFFSX1TS R_63 ( .D(n2970), .CK(clk), .SN(n2705), .Q(n2845) );
DFFSX1TS R_65 ( .D(n2968), .CK(clk), .SN(n2705), .Q(n2843) );
DFFSX2TS R_67 ( .D(n2954), .CK(clk), .SN(n3068), .Q(n2842) );
DFFSX2TS R_68 ( .D(n2953), .CK(clk), .SN(n1408), .Q(n2841) );
DFFSX2TS R_69 ( .D(n2952), .CK(clk), .SN(n1409), .Q(n2840) );
DFFSX1TS R_71 ( .D(n2958), .CK(clk), .SN(n2919), .Q(n2839) );
DFFSX2TS R_72 ( .D(n2957), .CK(clk), .SN(n1406), .Q(n2838) );
DFFSX1TS R_77 ( .D(n2983), .CK(clk), .SN(n2705), .Q(n2834) );
DFFSX2TS R_83 ( .D(n2978), .CK(clk), .SN(n1406), .Q(n2831) );
DFFSX2TS R_85 ( .D(n2977), .CK(clk), .SN(n1406), .Q(n2830) );
DFFSX4TS R_88 ( .D(n2886), .CK(clk), .SN(n2899), .Q(n2827), .QN(n953) );
DFFRX4TS R_87 ( .D(n532), .CK(clk), .RN(n2899), .Q(n2828) );
DFFSX4TS R_91 ( .D(n1429), .CK(clk), .SN(n2899), .Q(n2823) );
DFFRX4TS R_90 ( .D(n533), .CK(clk), .RN(n2902), .Q(n2824) );
DFFSX1TS R_74 ( .D(n2943), .CK(clk), .SN(n1422), .Q(n2836) );
DFFSX1TS R_103 ( .D(n2931), .CK(clk), .SN(n1424), .Q(n2817) );
DFFRX1TS R_109 ( .D(n2934), .CK(clk), .RN(n2704), .Q(n2813) );
DFFSX2TS R_111 ( .D(n2933), .CK(clk), .SN(n2702), .Q(n2812) );
DFFSX2TS R_112 ( .D(n2932), .CK(clk), .SN(n2695), .Q(n2811) );
DFFSX1TS R_117 ( .D(n2988), .CK(clk), .SN(n2705), .Q(n2808) );
DFFRX4TS R_120 ( .D(n2377), .CK(clk), .RN(n1420), .Q(n2921), .QN(n2525) );
DFFSX2TS R_121 ( .D(n3002), .CK(clk), .SN(n1405), .Q(n2806) );
DFFSX1TS R_127 ( .D(n2975), .CK(clk), .SN(n1405), .Q(n2801) );
DFFSX2TS R_129 ( .D(n2974), .CK(clk), .SN(n1406), .QN(n1331) );
DFFRXLTS R_137 ( .D(n478), .CK(clk), .RN(n2703), .QN(n2621) );
DFFSX1TS R_144 ( .D(n2962), .CK(clk), .SN(n1419), .Q(n2794) );
DFFSX1TS R_145 ( .D(n2961), .CK(clk), .SN(n1427), .Q(n2793) );
DFFSX2TS R_148 ( .D(n2966), .CK(clk), .SN(n1406), .QN(n1327) );
DFFSX2TS R_158 ( .D(n3007), .CK(clk), .SN(n1437), .Q(n2786) );
DFFSX2TS R_159 ( .D(n3006), .CK(clk), .SN(n1437), .Q(n2785) );
DFFSX2TS R_161 ( .D(n3005), .CK(clk), .SN(n1435), .Q(n2784) );
DFFSX2TS R_162 ( .D(n2998), .CK(clk), .SN(n1436), .Q(n2783) );
DFFSX2TS R_163 ( .D(n2997), .CK(clk), .SN(n1437), .Q(n2782) );
DFFSX2TS R_165 ( .D(n2996), .CK(clk), .SN(n1437), .Q(n2781) );
DFFSX1TS R_172 ( .D(n2939), .CK(clk), .SN(n1416), .Q(n2777) );
DFFSX1TS R_173 ( .D(n2938), .CK(clk), .SN(n1416), .Q(n2776) );
DFFSX2TS R_176 ( .D(n2964), .CK(clk), .SN(n2919), .Q(n2775) );
DFFSX2TS R_177 ( .D(n2963), .CK(clk), .SN(n2906), .Q(n2774) );
DFFSX2TS R_180 ( .D(n2944), .CK(clk), .SN(n1422), .Q(n2772) );
DFFSX1TS R_210 ( .D(n2993), .CK(clk), .SN(n1407), .Q(n2765) );
DFFSX1TS R_211 ( .D(n2992), .CK(clk), .SN(n1407), .Q(n2764) );
DFFRX1TS R_221 ( .D(n2929), .CK(clk), .RN(n942), .Q(n2760) );
DFFSX2TS R_222 ( .D(n3013), .CK(clk), .SN(n2902), .Q(n2759) );
DFFRX1TS R_225 ( .D(n2941), .CK(clk), .RN(n1422), .Q(n2758) );
DFFSX2TS R_226 ( .D(n2994), .CK(clk), .SN(n1406), .Q(n2757) );
DFFRX1TS R_229 ( .D(n2937), .CK(clk), .RN(n1417), .Q(n2756) );
DFFRX1TS R_231 ( .D(n2986), .CK(clk), .RN(n2703), .Q(n2755) );
DFFSX2TS R_235 ( .D(n3003), .CK(clk), .SN(n2705), .Q(n2754) );
DFFSX2TS R_242 ( .D(n2940), .CK(clk), .SN(n1422), .QN(n945) );
DFFSX2TS R_247 ( .D(n2989), .CK(clk), .SN(n1408), .Q(n2745) );
DFFSX1TS R_253 ( .D(n2990), .CK(clk), .SN(n1407), .Q(n2742) );
DFFRX2TS R_316 ( .D(n2927), .CK(clk), .RN(n1423), .Q(n2711) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n2906), .Q(
ZERO_FLAG_SFG), .QN(n2691) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n2705), .Q(
SIGN_FLAG_SFG), .QN(n2690) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n2909), .Q(
DMP_SFG[23]), .QN(n2688) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n2909), .Q(
DMP_SFG[24]), .QN(n2687) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n2910), .Q(
DMP_SFG[25]), .QN(n2686) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n2911), .Q(
DMP_SFG[26]), .QN(n2685) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n2911), .Q(
DMP_SFG[27]), .QN(n2684) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n2912), .Q(
DMP_SFG[28]), .QN(n2683) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n2912), .Q(
DMP_SFG[29]), .QN(n2682) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n2895), .Q(
final_result_ieee[19]), .QN(n2673) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n2889),
.Q(Shift_amount_SHT1_EWR[3]), .QN(n2654) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n2697), .Q(
final_result_ieee[4]), .QN(n2672) );
DFFRXLTS R_4 ( .D(underflow_flag), .CK(clk), .RN(n2898), .Q(n2874) );
DFFRXLTS R_133 ( .D(final_result_ieee[3]), .CK(clk), .RN(n2697), .Q(n2799)
);
DFFRXLTS R_157 ( .D(final_result_ieee[10]), .CK(clk), .RN(n2887), .Q(n2787)
);
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n2703), .Q(
DmP_mant_SFG_SWR[0]), .QN(n2660) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n2889), .Q(
DmP_mant_SFG_SWR[1]), .QN(n2678) );
DFFSX2TS R_26 ( .D(n3050), .CK(clk), .SN(n2905), .Q(n2864) );
DFFSX2TS R_30 ( .D(n3044), .CK(clk), .SN(n2896), .Q(n2862) );
DFFSX2TS R_34 ( .D(n3056), .CK(clk), .SN(n2695), .Q(n2860) );
DFFSX2TS R_45 ( .D(n3033), .CK(clk), .SN(n2697), .Q(n2855) );
DFFSX2TS R_53 ( .D(n3058), .CK(clk), .SN(n2895), .Q(n2850) );
DFFSX2TS R_57 ( .D(n3054), .CK(clk), .SN(n2695), .Q(n2848) );
DFFSX2TS R_61 ( .D(n3028), .CK(clk), .SN(n2697), .Q(n2846) );
DFFSX2TS R_95 ( .D(n3037), .CK(clk), .SN(n2695), .Q(n2820) );
DFFSX2TS R_108 ( .D(n3042), .CK(clk), .SN(n2695), .Q(n2814) );
DFFSX2TS R_116 ( .D(n3031), .CK(clk), .SN(n2698), .Q(n2809) );
DFFSX2TS R_142 ( .D(n3048), .CK(clk), .SN(n2896), .Q(n2795) );
DFFSX2TS R_153 ( .D(n3060), .CK(clk), .SN(n2895), .Q(n2789) );
DFFSX2TS R_171 ( .D(n3039), .CK(clk), .SN(n1410), .Q(n2778) );
DFFSX2TS R_184 ( .D(n3062), .CK(clk), .SN(n2887), .Q(n2770) );
DFFSX2TS R_188 ( .D(n3026), .CK(clk), .SN(n2699), .Q(n2768) );
DFFSX2TS R_192 ( .D(n3024), .CK(clk), .SN(n2699), .Q(n2766) );
DFFSX2TS R_313 ( .D(n3046), .CK(clk), .SN(n1409), .Q(n2713) );
DFFSX2TS R_320 ( .D(n3035), .CK(clk), .SN(n2699), .Q(n2709) );
DFFSX2TS R_327 ( .D(n3052), .CK(clk), .SN(n1409), .Q(n2706) );
DFFSX2TS R_131 ( .D(n3030), .CK(clk), .SN(n2698), .Q(n2800) );
DFFSX2TS R_155 ( .D(n3041), .CK(clk), .SN(n3068), .Q(n2788) );
DFFSX2TS R_24 ( .D(n3051), .CK(clk), .SN(n2705), .Q(n2865) );
DFFSX2TS R_32 ( .D(n3057), .CK(clk), .SN(n1409), .Q(n2861) );
DFFSX2TS R_43 ( .D(n3034), .CK(clk), .SN(n2697), .Q(n2856) );
DFFSX2TS R_51 ( .D(n3059), .CK(clk), .SN(n1406), .Q(n2851) );
DFFSX2TS R_55 ( .D(n3055), .CK(clk), .SN(n2695), .Q(n2849) );
DFFSX2TS R_59 ( .D(n3029), .CK(clk), .SN(n2698), .Q(n2847) );
DFFSX2TS R_93 ( .D(n3038), .CK(clk), .SN(n2695), .Q(n2821) );
DFFSX2TS R_106 ( .D(n3043), .CK(clk), .SN(n2896), .Q(n2815) );
DFFSX2TS R_114 ( .D(n3032), .CK(clk), .SN(n2698), .Q(n2810) );
DFFSX2TS R_140 ( .D(n3049), .CK(clk), .SN(n2887), .Q(n2796) );
DFFSX2TS R_151 ( .D(n3061), .CK(clk), .SN(n1435), .Q(n2790) );
DFFSX2TS R_169 ( .D(n3040), .CK(clk), .SN(n1409), .Q(n2779) );
DFFSX2TS R_182 ( .D(n3063), .CK(clk), .SN(n927), .Q(n2771) );
DFFSX2TS R_186 ( .D(n3027), .CK(clk), .SN(n2699), .Q(n2769) );
DFFSX2TS R_190 ( .D(n3025), .CK(clk), .SN(n2699), .Q(n2767) );
DFFSX2TS R_311 ( .D(n3047), .CK(clk), .SN(n1410), .Q(n2714) );
DFFSX2TS R_318 ( .D(n3036), .CK(clk), .SN(n2700), .Q(n2710) );
DFFSX2TS R_325 ( .D(n3053), .CK(clk), .SN(n2695), .Q(n2707) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n2700), .Q(
final_result_ieee[30]) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1416), .Q(
final_result_ieee[31]) );
DFFSX2TS R_81 ( .D(n3066), .CK(clk), .SN(n2700), .Q(n2832) );
DFFSX1TS R_126 ( .D(n3065), .CK(clk), .SN(n2906), .Q(n2802) );
DFFSX2TS R_167 ( .D(n3064), .CK(clk), .SN(n2910), .Q(n2780) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n2888), .Q(
zero_flag) );
DFFSX2TS R_258 ( .D(n3008), .CK(clk), .SN(n1422), .Q(n2740) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1417), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1417), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1417), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n2705), .Q(
final_result_ieee[26]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n2902),
.Q(Shift_amount_SHT1_EWR[0]), .QN(n2537) );
DFFSX2TS R_243 ( .D(n2936), .CK(clk), .SN(n2917), .Q(n2749) );
DFFSX2TS R_245 ( .D(n2985), .CK(clk), .SN(n1408), .Q(n2747) );
DFFSX2TS R_308 ( .D(n2950), .CK(clk), .SN(n1408), .Q(n2716) );
DFFSX2TS R_294 ( .D(n3020), .CK(clk), .SN(n2908), .Q(n2724) );
DFFSX2TS R_244 ( .D(n2935), .CK(clk), .SN(n2917), .Q(n2748) );
DFFSX2TS R_246 ( .D(n2984), .CK(clk), .SN(n1408), .Q(n2746) );
DFFSX2TS R_309 ( .D(n2949), .CK(clk), .SN(n1437), .Q(n2715) );
DFFSX2TS R_279 ( .D(n2694), .CK(clk), .SN(n1406), .Q(n2731) );
DFFSX2TS R_295 ( .D(n3019), .CK(clk), .SN(n2695), .Q(n2723) );
DFFSX2TS R_240 ( .D(n3021), .CK(clk), .SN(n2905), .Q(n2751) );
DFFSX2TS R_296 ( .D(n3018), .CK(clk), .SN(n1424), .Q(n2722) );
DFFSX2TS R_219 ( .D(n2955), .CK(clk), .SN(n1423), .Q(n2761) );
DFFSX2TS R_256 ( .D(n2976), .CK(clk), .SN(n1408), .Q(n2741) );
DFFRXLTS R_264 ( .D(n2995), .CK(clk), .RN(n1422), .Q(n2738) );
DFFSX2TS R_301 ( .D(n2734), .CK(clk), .SN(n1407), .Q(n2719) );
DFFSX2TS R_300 ( .D(n2980), .CK(clk), .SN(n2897), .Q(n2720) );
DFFSX2TS R_237 ( .D(Raw_mant_NRM_SWR[4]), .CK(clk), .SN(n2702), .Q(n2753) );
DFFSX2TS R_122 ( .D(n3001), .CK(clk), .SN(n2698), .Q(n2805) );
DFFSX2TS R_123 ( .D(n3000), .CK(clk), .SN(n1436), .Q(n2804) );
DFFSX2TS R_124 ( .D(n2999), .CK(clk), .SN(n1436), .Q(n2803) );
DFFSX2TS R_289 ( .D(n532), .CK(clk), .SN(n2703), .Q(n2727) );
DFFSX2TS R_288 ( .D(n1502), .CK(clk), .SN(n1408), .Q(n2728) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n2918), .Q(
intDX_EWSW[1]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n2916), .Q(
intDX_EWSW[6]), .QN(n1397) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n2917),
.Q(intDX_EWSW[28]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n2908), .Q(
DmP_mant_SFG_SWR[12]), .QN(n2666) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n2890), .Q(
DmP_mant_SFG_SWR[16]), .QN(n2671) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n2911), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n2899),
.Q(intDX_EWSW[29]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n2918), .Q(
intDX_EWSW[0]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n2901), .Q(
Raw_mant_NRM_SWR[21]), .QN(n2877) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n2917),
.Q(intDX_EWSW[30]) );
DFFRX4TS R_101 ( .D(n2818), .CK(clk), .RN(n1419), .Q(
DmP_mant_SFG_SWR_signed[9]) );
DFFSX4TS R_86 ( .D(Raw_mant_SGF[10]), .CK(clk), .SN(n2899), .Q(n2829) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n2890), .Q(
LZD_output_NRM2_EW[4]), .QN(n1655) );
DFFRX4TS R_138 ( .D(n2797), .CK(clk), .RN(n1419), .Q(
DmP_mant_SFG_SWR_signed[10]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n2697), .Q(
DmP_mant_SFG_SWR[13]), .QN(n2665) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1435), .QN(
n2568) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n2890), .Q(
LZD_output_NRM2_EW[2]), .QN(n1658) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n2916), .Q(
intDX_EWSW[9]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n2917),
.Q(intDX_EWSW[25]), .QN(n952) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n2702),
.Q(intDX_EWSW[13]), .QN(n1314) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n2887), .Q(
Raw_mant_NRM_SWR[1]), .QN(n2565) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n2908),
.Q(intDX_EWSW[19]), .QN(n1376) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n2697), .Q(
LZD_output_NRM2_EW[0]), .QN(n1319) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n2890), .Q(
LZD_output_NRM2_EW[3]), .QN(n1656) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n929), .Q(
Raw_mant_NRM_SWR[5]), .QN(n2612) );
DFFRX4TS R_136 ( .D(n2798), .CK(clk), .RN(n1420), .Q(
DmP_mant_SFG_SWR_signed[8]) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n3068), .Q(
Shift_reg_FLAGS_7[0]), .QN(n2607) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n2910), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n2695),
.Q(intDX_EWSW[17]) );
DFFSX4TS R_89 ( .D(Raw_mant_SGF[9]), .CK(clk), .SN(n2899), .Q(n2825) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n2907), .Q(
DMP_SFG[9]), .QN(n2880) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n929), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1660) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n2902), .Q(
shift_value_SHT2_EWR_4_), .QN(n2569) );
DFFRX2TS R_290 ( .D(n2883), .CK(clk), .RN(n2703), .Q(n2726) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n929), .Q(
Raw_mant_NRM_SWR[18]), .QN(n2530) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n2905), .Q(
DMP_exp_NRM2_EW[2]), .QN(n2878) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n3068), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n2644) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1416),
.Q(intDY_EWSW[26]), .QN(n2587) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1406),
.Q(intDX_EWSW[18]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n2901), .Q(
Raw_mant_NRM_SWR[17]), .QN(n2528) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n2914), .Q(
intDY_EWSW[9]), .QN(n2574) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n2915),
.Q(intDY_EWSW[13]), .QN(n2592) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n2890), .Q(
Raw_mant_NRM_SWR[20]), .QN(n2527) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n2915),
.Q(intDY_EWSW[19]), .QN(n2591) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1416),
.Q(intDY_EWSW[25]), .QN(n2596) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n2918),
.Q(intDY_EWSW[29]), .QN(n2590) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n2901), .Q(
Raw_mant_NRM_SWR[14]), .QN(n2826) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n2901), .Q(
n1650), .QN(n1651) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n2915),
.Q(intDY_EWSW[20]), .QN(n2594) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n2915),
.Q(intDY_EWSW[17]), .QN(n2579) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n2918),
.Q(intDY_EWSW[28]), .QN(n2573) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n929), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1649) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n2901), .Q(
Raw_mant_NRM_SWR[25]), .QN(n2566) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n2696), .Q(
Shift_reg_FLAGS_7[1]), .QN(n1646) );
DFFRX2TS R_269 ( .D(n2646), .CK(clk), .RN(n1436), .Q(n2736) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n2903), .Q(
left_right_SHT2), .QN(n1433) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n2916), .Q(
intDX_EWSW[2]), .QN(n917) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n929), .Q(
Raw_mant_NRM_SWR[11]), .QN(n2822) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n2901), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1647) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n928), .Q(
intDX_EWSW[15]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n2916),
.Q(intDX_EWSW[11]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1423),
.Q(intDX_EWSW[14]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n2914), .Q(
intDY_EWSW[6]), .QN(n2589) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n2899),
.Q(intDY_EWSW[30]), .QN(n2575) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n2916),
.Q(intDX_EWSW[10]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n2916), .Q(
intDX_EWSW[8]) );
DFFSRHQX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .SN(1'b1),
.RN(n1427), .Q(SIGN_FLAG_SHT1SHT2) );
DFFSRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .SN(1'b1),
.RN(n1427), .Q(DmP_mant_SHT1_SW[20]) );
DFFRHQX4TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1416), .Q(
OP_FLAG_SHT1) );
DFFRX4TS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n2919), .QN(
n2653) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n2919),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRHQX2TS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1427), .Q(
n2521) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n3068),
.QN(n2600) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n2906), .Q(
DMP_SHT2_EWSW[8]), .QN(n2538) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n2698), .Q(
DmP_mant_SFG_SWR[3]), .QN(n2656) );
DFFSX1TS R_22 ( .D(n2946), .CK(clk), .SN(n1407), .Q(n2866) );
DFFSX1TS R_149 ( .D(n2965), .CK(clk), .SN(n1407), .Q(n2791) );
DFFSX1TS R_212 ( .D(n2991), .CK(clk), .SN(n1407), .Q(n2763) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n2913), .Q(
DMP_SFG[30]), .QN(n2681) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n2916), .Q(
intDX_EWSW[5]), .QN(n1312) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n2916), .Q(
intDX_EWSW[4]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n2899),
.Q(intDX_EWSW[23]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n2917),
.Q(intDX_EWSW[22]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n2899),
.Q(intDX_EWSW[27]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n2916), .Q(
intDX_EWSW[7]), .QN(n1400) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n2914),
.Q(intDY_EWSW[10]), .QN(n2588) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n2916), .Q(
intDX_EWSW[3]), .QN(n1399) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n2898), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2648) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1435), .Q(
DmP_mant_SFG_SWR[7]), .QN(n2662) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n2699),
.Q(intDX_EWSW[12]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n2917),
.Q(intDX_EWSW[26]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1435), .Q(
DmP_mant_SFG_SWR[4]), .QN(n2661) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n2908), .Q(
DMP_SFG[12]), .QN(n2679) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1408),
.Q(intDX_EWSW[16]) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n2704), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n2643) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1410),
.Q(intDX_EWSW[20]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n927), .Q(
intDX_EWSW[21]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n2904), .Q(
DMP_SFG[3]), .QN(n2680) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n2914), .Q(
intDY_EWSW[8]), .QN(n2584) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n2914), .Q(
intDY_EWSW[2]), .QN(n2586) );
DFFRX4TS R_274 ( .D(n2762), .CK(clk), .RN(n1419), .Q(n2875) );
DFFSX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n948), .CK(clk), .SN(n1436), .Q(
n2925), .QN(n2924) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n2899),
.Q(intDX_EWSW[24]), .QN(n1378) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n2914), .Q(
intDY_EWSW[4]), .QN(n2585) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n2901), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1657) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n2914),
.Q(intDY_EWSW[11]), .QN(n2581) );
DFFRX4TS R_276 ( .D(n2645), .CK(clk), .RN(n2704), .Q(n2733) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n2914), .Q(
intDY_EWSW[7]), .QN(n2582) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n2915),
.Q(intDY_EWSW[12]), .QN(n2583) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n2915),
.Q(intDY_EWSW[15]), .QN(n2580) );
DFFRX4TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1419), .Q(
intAS) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1419),
.Q(intDY_EWSW[31]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n928), .Q(
Raw_mant_NRM_SWR[3]), .QN(n965) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n2914), .Q(
intDY_EWSW[5]), .QN(n2593) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n2915),
.Q(intDY_EWSW[14]), .QN(n2572) );
DFFRX4TS R_277 ( .D(n3009), .CK(clk), .RN(n2908), .Q(n2732) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n2919), .Q(
Shift_reg_FLAGS_7[2]), .QN(n2651) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n2913), .Q(
intDY_EWSW[0]), .QN(n2597) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n2703), .Q(
Raw_mant_NRM_SWR[0]), .QN(n2531) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1416),
.Q(intDY_EWSW[22]), .QN(n2571) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1416),
.Q(intDY_EWSW[24]), .QN(n2570) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1416),
.Q(intDY_EWSW[23]), .QN(n2577) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n2915),
.Q(intDY_EWSW[21]), .QN(n2578) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n929), .Q(
Raw_mant_NRM_SWR[2]), .QN(n2694) );
DFFRX4TS R_307 ( .D(n2377), .CK(clk), .RN(n1419), .Q(n2876) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1416),
.Q(intDY_EWSW[27]), .QN(n2576) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n2915),
.Q(intDY_EWSW[16]), .QN(n2595) );
DFFRXLTS R_263 ( .D(n2647), .CK(clk), .RN(n1436), .Q(n2739) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1435), .Q(
Raw_mant_NRM_SWR[8]), .QN(n872) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n2891), .QN(
n2616) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n2915),
.Q(n1395) );
DFFRHQX8TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n2897),
.Q(n1393) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n2913),
.Q(n1391) );
DFFRHQX4TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n2704), .Q(
n1387) );
DFFRX4TS R_82 ( .D(n2979), .CK(clk), .RN(n2703), .QN(n1313) );
DFFRHQX4TS R_9 ( .D(n2873), .CK(clk), .RN(n1419), .Q(n1375) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n2911), .Q(
n1374) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n2892), .Q(
n1369) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1424), .Q(
n1368) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n2893), .Q(
n1367) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n2894), .Q(
n1366) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n2914),
.Q(n1362) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n2913), .Q(
n1360) );
DFFSX2TS R_293 ( .D(n2926), .CK(clk), .SN(n1407), .QN(n1359) );
DFFSX2TS R_292 ( .D(n2531), .CK(clk), .SN(n1405), .Q(n2725) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n2894), .Q(
n1357) );
DFFRX1TS R_302 ( .D(n1167), .CK(clk), .RN(n2700), .Q(n2718) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n2901),
.Q(n1306) );
DFFRHQX8TS R_10 ( .D(n770), .CK(clk), .RN(n1410), .Q(n1389) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n2893), .Q(
n1303) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n2913), .Q(
n1302) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n2892), .Q(
DMP_EXP_EWSW[16]) );
DFFRHQX2TS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n2889), .Q(
n1299) );
DFFRXLTS R_100 ( .D(n479), .CK(clk), .RN(n1436), .QN(n2622) );
DFFRX1TS R_214 ( .D(n483), .CK(clk), .RN(n1422), .Q(n962) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1421), .Q(n1301) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1421), .Q(
n1297) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n926), .Q(
DmP_EXP_EWSW[10]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n2888), .Q(
DMP_EXP_EWSW[7]) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1421), .Q(n1296) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n2911), .Q(
DMP_EXP_EWSW[27]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n2898), .Q(
DMP_EXP_EWSW[3]) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n2895), .Q(
n1295) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n2896), .Q(
n1294) );
DFFSX2TS R_328 ( .D(n1596), .CK(clk), .SN(n927), .Q(n1292) );
DFFSX2TS R_329 ( .D(n1595), .CK(clk), .SN(n928), .Q(n1291) );
DFFSX2TS R_330 ( .D(n2064), .CK(clk), .SN(n927), .Q(n1290) );
DFFSX2TS R_331 ( .D(n2187), .CK(clk), .SN(n929), .Q(n1289) );
DFFSX2TS R_332 ( .D(n2186), .CK(clk), .SN(n929), .Q(n1288) );
DFFSX2TS R_333 ( .D(n2185), .CK(clk), .SN(n929), .Q(n1287) );
DFFSX2TS R_335 ( .D(n2174), .CK(clk), .SN(n930), .Q(n1285) );
DFFSX2TS R_336 ( .D(n2173), .CK(clk), .SN(n930), .Q(n1284) );
DFFSX2TS R_334 ( .D(n2175), .CK(clk), .SN(n942), .Q(n1286) );
DFFSX2TS R_337 ( .D(n2172), .CK(clk), .SN(n942), .Q(n1283) );
DFFSX2TS R_338 ( .D(n2171), .CK(clk), .SN(n942), .Q(n1282) );
DFFSX2TS R_339 ( .D(n2170), .CK(clk), .SN(n942), .Q(n1281) );
DFFSX2TS R_341 ( .D(n2165), .CK(clk), .SN(n1424), .Q(n1279) );
DFFSX2TS R_342 ( .D(n2164), .CK(clk), .SN(n1424), .Q(n1278) );
DFFSX2TS R_340 ( .D(n2166), .CK(clk), .SN(n1424), .Q(n1280) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n2891), .Q(
DmP_mant_SFG_SWR[23]), .QN(n2657) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n926), .Q(
DmP_mant_SFG_SWR[2]), .QN(n2663) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n2907), .Q(
DMP_SFG[11]), .QN(n2632) );
DFFSX2TS R_349 ( .D(n2881), .CK(clk), .SN(n2699), .Q(n1277) );
DFFSX2TS R_350 ( .D(n974), .CK(clk), .SN(n2699), .Q(n1276) );
DFFSX2TS R_351 ( .D(n2881), .CK(clk), .SN(n2697), .Q(n1275) );
DFFSX4TS R_352 ( .D(n1167), .CK(clk), .SN(n1437), .Q(n1274) );
DFFRX4TS R_284 ( .D(DmP_mant_SHT1_SW[21]), .CK(clk), .RN(n2704), .QN(n1273)
);
DFFSX2TS R_353 ( .D(n974), .CK(clk), .SN(n1410), .Q(n1267) );
DFFSX2TS R_354 ( .D(n3067), .CK(clk), .SN(n2888), .Q(n1266) );
DFFSX2TS R_355 ( .D(n2881), .CK(clk), .SN(n1409), .Q(n1265) );
DFFSX2TS R_356 ( .D(n2922), .CK(clk), .SN(n1427), .Q(n1264), .QN(ready) );
DFFSX4TS R_357 ( .D(n988), .CK(clk), .SN(n2919), .Q(n1262), .QN(n1261) );
DFFSX4TS R_358 ( .D(n1412), .CK(clk), .SN(n1405), .Q(n1260), .QN(n1259) );
DFFSX2TS R_359 ( .D(n974), .CK(clk), .SN(n2699), .Q(n1257) );
DFFSX2TS R_360 ( .D(n1868), .CK(clk), .SN(n1424), .Q(n1256) );
DFFSX4TS R_361 ( .D(n2973), .CK(clk), .SN(n1405), .Q(n1255), .QN(n950) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n2903), .Q(
n1252) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n2912), .Q(
n1251) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n2897), .Q(
n1250) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n2904), .Q(n1249) );
DFFRHQX4TS R_11_IP ( .D(n770), .CK(clk), .RN(n1410), .Q(n2520) );
DFFSX2TS R_73 ( .D(n2956), .CK(clk), .SN(n2897), .Q(n2837) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n2908), .Q(
DMP_SHT2_EWSW[13]), .QN(n2546) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n2893), .Q(
DMP_SHT2_EWSW[18]), .QN(n2559) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n2909), .Q(
DMP_SHT2_EWSW[23]), .QN(n2545) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n2912), .Q(
DMP_SHT2_EWSW[28]), .QN(n2541) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n2888), .Q(
DmP_mant_SHT1_SW[4]), .QN(n2627) );
DFFRX1TS R_323 ( .D(DmP_mant_SHT1_SW[14]), .CK(clk), .RN(n1421), .Q(n2708)
);
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n2894), .Q(
n1300) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n2903), .Q(
DmP_EXP_EWSW[23]), .QN(n2649) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n2908), .Q(n923)
);
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n2891), .Q(n922) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n2906), .Q(n921)
);
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n2919), .Q(n920) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n2887), .Q(n919)
);
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n2902), .Q(n918) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n3068), .Q(
DmP_EXP_EWSW[8]) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n3068), .Q(n915)
);
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n2910), .Q(n914)
);
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n2900), .Q(n913) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1421), .Q(
DmP_EXP_EWSW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1409), .Q(
DmP_mant_SHT1_SW[9]), .QN(n2642) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1407), .Q(n910)
);
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n2704), .Q(n909) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n2903), .Q(n906) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n2907), .Q(n905) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n2903), .Q(n903) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n2904), .Q(n902)
);
DFFSX2TS R_64 ( .D(n2969), .CK(clk), .SN(n2703), .Q(n2844) );
DFFSX2TS R_179 ( .D(n2945), .CK(clk), .SN(n1422), .Q(n2773) );
DFFSX2TS R_118 ( .D(n2987), .CK(clk), .SN(n1405), .Q(n2807) );
DFFSX2TS R_14 ( .D(n2951), .CK(clk), .SN(n2704), .Q(n2872) );
DFFSX2TS R_104 ( .D(n2930), .CK(clk), .SN(n942), .Q(n2816) );
DFFSX2TS R_75 ( .D(n2942), .CK(clk), .SN(n1422), .Q(n2835) );
DFFRX4TS R_97 ( .D(n2819), .CK(clk), .RN(n1420), .Q(
DmP_mant_SFG_SWR_signed[11]) );
DFFSX4TS R_217 ( .D(n2959), .CK(clk), .SN(n1436), .QN(n951) );
DFFRX1TS R_19 ( .D(n2948), .CK(clk), .RN(n2900), .Q(n2868) );
DFFSX2TS R_146 ( .D(n2960), .CK(clk), .SN(n2704), .Q(n2792) );
DFFSX2TS R_79 ( .D(n2982), .CK(clk), .SN(n1405), .Q(n2833) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n2901), .Q(
Raw_mant_NRM_SWR[19]), .QN(n2526) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n2890), .Q(
DmP_mant_SFG_SWR[17]), .QN(n2670) );
DFFRHQX4TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n2697),
.Q(n1310) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n2901),
.Q(n1385) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n2890), .Q(
DmP_mant_SFG_SWR[18]), .QN(n2669) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n2702), .Q(
DmP_mant_SFG_SWR[15]), .QN(n2664) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n2890), .Q(
DmP_mant_SFG_SWR[20]), .QN(n2668) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n2890), .Q(
DmP_mant_SFG_SWR[21]), .QN(n2667) );
DFFRX1TS R_270 ( .D(n3014), .CK(clk), .RN(n926), .Q(n2735) );
DFFRX2TS R_305 ( .D(DmP_mant_SHT1_SW[18]), .CK(clk), .RN(n1423), .Q(n2717)
);
DFFRX2TS R_238 ( .D(n1868), .CK(clk), .RN(n2702), .Q(n2752) );
DFFRX2TS R_315 ( .D(Raw_mant_NRM_SWR[2]), .CK(clk), .RN(n1423), .Q(n2712) );
DFFRX2TS R_280 ( .D(n2972), .CK(clk), .RN(n2703), .Q(n2730) );
DFFRX2TS R_287 ( .D(DmP_mant_SHT1_SW[17]), .CK(clk), .RN(n2897), .Q(n2729)
);
DFFSX2TS R_232 ( .D(n2967), .CK(clk), .SN(n942), .QN(n1364) );
DFFSX2TS R_251 ( .D(n2981), .CK(clk), .SN(n1408), .Q(n2743) );
DFFSX2TS R_249 ( .D(n2971), .CK(clk), .SN(n942), .Q(n2744) );
DFFSX2TS R_233 ( .D(n2884), .CK(clk), .SN(n942), .QN(n1365) );
DFFRX2TS R_267 ( .D(n3004), .CK(clk), .RN(n1435), .QN(n1270) );
DFFRX1TS R_266 ( .D(n2652), .CK(clk), .RN(n1437), .Q(n2737) );
DFFRX1TS R_298 ( .D(n2882), .CK(clk), .RN(n2700), .Q(n2721) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n2909), .Q(
n1370) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n2705), .Q(
n1372) );
DFFRHQX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1427),
.Q(DmP_mant_SHT1_SW[5]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1419),
.Q(intDX_EWSW[31]), .QN(n2626) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n929), .Q(
DmP_mant_SHT1_SW[13]), .QN(n2639) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n2704), .Q(
Shift_reg_FLAGS_7_5), .QN(n2650) );
DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1427),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n942), .Q(
DmP_mant_SHT1_SW[10]), .QN(n2601) );
DFFSHQX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1645), .CK(clk), .SN(n1427),
.Q(n2605) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1420), .Q(
DMP_EXP_EWSW[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n2892), .Q(
DMP_EXP_EWSW[17]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n2895), .Q(
DMP_EXP_EWSW[8]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n2696), .Q(
DMP_EXP_EWSW[4]) );
DFFSX1TS R_28 ( .D(n3045), .CK(clk), .SN(n2896), .Q(n2863) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1423), .Q(
DmP_mant_SHT1_SW[17]), .QN(n2599) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1423), .Q(
DmP_mant_SHT1_SW[18]), .QN(n2606) );
DFFRX2TS R_96 ( .D(n477), .CK(clk), .RN(n2703), .QN(n2620) );
DFFRHQX4TS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1419), .Q(
SIGN_FLAG_SHT2) );
DFFSRHQX2TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .SN(1'b1),
.RN(n1405), .Q(ZERO_FLAG_SHT1SHT2) );
MX2X2TS U897 ( .A(Data_X[9]), .B(intDX_EWSW[9]), .S0(n2518), .Y(n853) );
CLKINVX2TS U898 ( .A(n925), .Y(n927) );
CLKINVX1TS U899 ( .A(n925), .Y(n926) );
CLKINVX2TS U900 ( .A(n925), .Y(n928) );
INVX3TS U901 ( .A(n941), .Y(n929) );
CLKINVX3TS U902 ( .A(n941), .Y(n942) );
OAI2BB1X2TS U903 ( .A0N(n2384), .A1N(n2967), .B0(n1167), .Y(n2968) );
NAND2X2TS U904 ( .A(n978), .B(intDX_EWSW[17]), .Y(n2174) );
CLKMX2X3TS U905 ( .A(Data_X[21]), .B(intDX_EWSW[21]), .S0(n2517), .Y(n841)
);
CLKMX2X3TS U906 ( .A(Data_X[23]), .B(intDX_EWSW[23]), .S0(n2519), .Y(n839)
);
CLKMX2X3TS U907 ( .A(Data_Y[5]), .B(intDY_EWSW[5]), .S0(n2514), .Y(n823) );
MXI2X2TS U908 ( .A(n2028), .B(n2568), .S0(n900), .Y(n482) );
NAND2X2TS U909 ( .A(n1189), .B(n2882), .Y(n2938) );
NAND3X6TS U910 ( .A(n1955), .B(n1956), .C(n1954), .Y(n749) );
CLKBUFX2TS U911 ( .A(n2700), .Y(n2900) );
NAND2X2TS U912 ( .A(n886), .B(intDY_EWSW[21]), .Y(n2091) );
NAND2X2TS U913 ( .A(n978), .B(intDY_EWSW[28]), .Y(n2244) );
NAND2X2TS U914 ( .A(n1512), .B(intDY_EWSW[16]), .Y(n2184) );
NAND2X1TS U915 ( .A(n2886), .B(n1385), .Y(n1516) );
NAND2X2TS U916 ( .A(n886), .B(intDY_EWSW[20]), .Y(n2079) );
NAND2X2TS U917 ( .A(n998), .B(intDX_EWSW[25]), .Y(n2133) );
OAI21X2TS U918 ( .A0(n2397), .A1(n2291), .B0(n2290), .Y(n2294) );
NAND2X6TS U919 ( .A(n1480), .B(intDX_EWSW[5]), .Y(n2099) );
NAND2X2TS U920 ( .A(n2222), .B(intDX_EWSW[30]), .Y(n2238) );
AND2X6TS U921 ( .A(n1166), .B(n2305), .Y(n1167) );
INVX8TS U922 ( .A(n2650), .Y(n2437) );
NAND2X1TS U923 ( .A(n1429), .B(Raw_mant_NRM_SWR[7]), .Y(n1137) );
NAND3X1TS U924 ( .A(n1289), .B(n1288), .C(n1287), .Y(n584) );
NAND3X1TS U925 ( .A(n1286), .B(n1285), .C(n1284), .Y(n576) );
NAND3X1TS U926 ( .A(n1280), .B(n1279), .C(n1278), .Y(n574) );
NAND2X2TS U927 ( .A(n1512), .B(intDY_EWSW[20]), .Y(n2215) );
NAND2X1TS U928 ( .A(n1593), .B(intDX_EWSW[14]), .Y(n2198) );
NAND2X1TS U929 ( .A(n1593), .B(intDY_EWSW[26]), .Y(n1780) );
NAND2X1TS U930 ( .A(n1593), .B(intDY_EWSW[19]), .Y(n2085) );
AND2X6TS U931 ( .A(n2316), .B(n2315), .Y(n3051) );
NAND2X2TS U932 ( .A(n886), .B(intDX_EWSW[20]), .Y(n2214) );
OAI2BB1X2TS U933 ( .A0N(n2240), .A1N(n1571), .B0(n2239), .Y(n1635) );
NAND2XLTS U934 ( .A(n2119), .B(DMP_EXP_EWSW[4]), .Y(n1954) );
NAND2XLTS U935 ( .A(n2640), .B(n922), .Y(n2074) );
BUFX16TS U936 ( .A(n1189), .Y(n1003) );
NAND2X1TS U937 ( .A(n2451), .B(n1366), .Y(n2086) );
NAND2X1TS U938 ( .A(n2481), .B(Raw_mant_NRM_SWR[17]), .Y(n1641) );
NAND2XLTS U939 ( .A(n2451), .B(n1296), .Y(n2158) );
NAND2X2TS U940 ( .A(n2383), .B(n2369), .Y(n2370) );
AND2X2TS U941 ( .A(n2885), .B(n1385), .Y(n1325) );
NAND2XLTS U942 ( .A(n2233), .B(n915), .Y(n2234) );
AND2X2TS U943 ( .A(n1593), .B(intDY_EWSW[29]), .Y(n1384) );
NAND2XLTS U944 ( .A(n2224), .B(DmP_EXP_EWSW[6]), .Y(n2225) );
NAND2X6TS U945 ( .A(n977), .B(intDY_EWSW[13]), .Y(n2067) );
NOR2X1TS U946 ( .A(n974), .B(overflow_flag), .Y(n2382) );
NAND2X2TS U947 ( .A(n998), .B(intDY_EWSW[30]), .Y(n2237) );
NAND2XLTS U948 ( .A(n2886), .B(Raw_mant_NRM_SWR[6]), .Y(n1140) );
NAND2XLTS U949 ( .A(n2378), .B(n1360), .Y(n2241) );
NAND2XLTS U950 ( .A(n2224), .B(n921), .Y(n2188) );
NAND2XLTS U951 ( .A(n2119), .B(DMP_EXP_EWSW[5]), .Y(n2098) );
NAND2XLTS U952 ( .A(n2224), .B(n914), .Y(n2216) );
NAND2XLTS U953 ( .A(n2224), .B(n923), .Y(n2176) );
NAND2XLTS U954 ( .A(n2224), .B(n920), .Y(n2213) );
NAND2XLTS U955 ( .A(n2378), .B(n909), .Y(n2100) );
NAND2XLTS U956 ( .A(n2119), .B(n905), .Y(n2095) );
NAND2XLTS U957 ( .A(n2119), .B(n919), .Y(n2061) );
NAND2XLTS U958 ( .A(n2119), .B(n902), .Y(n2104) );
AOI22X1TS U959 ( .A0(n2489), .A1(DmP_mant_SHT1_SW[3]), .B0(n2319), .B1(n2500), .Y(n2269) );
NAND2X1TS U960 ( .A(n2415), .B(n2248), .Y(n1563) );
NAND2X4TS U961 ( .A(n1361), .B(n1497), .Y(n2122) );
INVX4TS U962 ( .A(n1402), .Y(n1404) );
NAND2XLTS U963 ( .A(n2233), .B(n918), .Y(n2182) );
NAND2XLTS U964 ( .A(n2233), .B(n913), .Y(n2197) );
OAI22X1TS U965 ( .A0(n1432), .A1(n2605), .B0(n2466), .B1(n1403), .Y(n2467)
);
NAND2XLTS U966 ( .A(n934), .B(n1213), .Y(n1212) );
INVX1TS U967 ( .A(n1456), .Y(n1377) );
INVX2TS U968 ( .A(n2377), .Y(n984) );
AND2X4TS U969 ( .A(n1874), .B(n1873), .Y(n2028) );
AOI21X2TS U970 ( .A0(n2489), .A1(DmP_mant_SHT1_SW[19]), .B0(n1186), .Y(n1185) );
NAND2X2TS U971 ( .A(n1195), .B(intDX_EWSW[2]), .Y(n2220) );
NAND2X2TS U972 ( .A(n1195), .B(intDY_EWSW[23]), .Y(n2381) );
NAND2X2TS U973 ( .A(n1630), .B(n1187), .Y(n995) );
XOR2X2TS U974 ( .A(n2397), .B(n2396), .Y(n2398) );
XOR2X2TS U975 ( .A(n2037), .B(n2154), .Y(n2038) );
NAND2X1TS U976 ( .A(n1593), .B(intDY_EWSW[14]), .Y(n2076) );
NAND3X6TS U977 ( .A(n1338), .B(n1639), .C(n1638), .Y(n2981) );
NAND2X2TS U978 ( .A(n1480), .B(intDY_EWSW[11]), .Y(n2193) );
XNOR2X1TS U979 ( .A(n1006), .B(n1342), .Y(n1517) );
NAND3XLTS U980 ( .A(n1646), .B(Shift_amount_SHT1_EWR[4]), .C(busy), .Y(n2148) );
AND2X2TS U981 ( .A(n2885), .B(n2882), .Y(n1322) );
AND2X4TS U982 ( .A(n1000), .B(n991), .Y(n1320) );
CLKBUFX3TS U983 ( .A(n2429), .Y(n933) );
INVX2TS U984 ( .A(n1425), .Y(n941) );
INVX2TS U985 ( .A(n2701), .Y(n925) );
AND2X4TS U986 ( .A(n1803), .B(n1802), .Y(n3043) );
AND2X4TS U987 ( .A(n1854), .B(n1853), .Y(n3041) );
AND2X6TS U988 ( .A(n1630), .B(Raw_mant_NRM_SWR[12]), .Y(n1329) );
AND2X6TS U989 ( .A(n1630), .B(Raw_mant_NRM_SWR[14]), .Y(n1321) );
AND2X2TS U990 ( .A(n1594), .B(intDX_EWSW[7]), .Y(n1298) );
AOI22X1TS U991 ( .A0(n2355), .A1(n2023), .B0(n936), .B1(n2483), .Y(n1853) );
OAI22X2TS U992 ( .A0(n2497), .A1(n2470), .B0(n1861), .B1(n1403), .Y(n1186)
);
INVX2TS U993 ( .A(n2254), .Y(n2475) );
NAND2X1TS U994 ( .A(n2309), .B(n1434), .Y(n2312) );
NAND2X1TS U995 ( .A(n988), .B(DmP_mant_SHT1_SW[10]), .Y(n1548) );
AND2X6TS U996 ( .A(n1910), .B(n974), .Y(n2383) );
OR2X6TS U997 ( .A(n1631), .B(n970), .Y(n1338) );
BUFX16TS U998 ( .A(n1821), .Y(n1432) );
AND2X6TS U999 ( .A(n1865), .B(n1866), .Y(n1169) );
BUFX6TS U1000 ( .A(n2206), .Y(n2119) );
BUFX16TS U1001 ( .A(n1418), .Y(n978) );
BUFX6TS U1002 ( .A(n2206), .Y(n2378) );
BUFX6TS U1003 ( .A(n2206), .Y(n2224) );
BUFX16TS U1004 ( .A(n1183), .Y(n1195) );
INVX2TS U1005 ( .A(n1532), .Y(n1530) );
OAI21X2TS U1006 ( .A0(n2408), .A1(n2297), .B0(n1623), .Y(n2301) );
AOI22X1TS U1007 ( .A0(n2355), .A1(n2483), .B0(n936), .B1(n2023), .Y(n1802)
);
CLKINVX1TS U1008 ( .A(n1927), .Y(n985) );
OAI21X1TS U1009 ( .A0(n1654), .A1(n2509), .B0(n2508), .Y(n2510) );
NOR2X1TS U1010 ( .A(n2035), .B(n2153), .Y(n2037) );
NAND2XLTS U1011 ( .A(n2395), .B(n2394), .Y(n2396) );
NOR2X1TS U1012 ( .A(n1413), .B(n2416), .Y(n1562) );
OAI2BB1X2TS U1013 ( .A0N(n2419), .A1N(n1576), .B0(n1574), .Y(n1573) );
NAND2X1TS U1014 ( .A(n2313), .B(n1434), .Y(n2316) );
AND3X6TS U1015 ( .A(n1127), .B(n1073), .C(n976), .Y(n1075) );
INVX2TS U1016 ( .A(n1538), .Y(n1537) );
BUFX4TS U1017 ( .A(n977), .Y(n878) );
BUFX12TS U1018 ( .A(n1630), .Y(n1502) );
NAND2XLTS U1019 ( .A(n1838), .B(n1837), .Y(n1659) );
NOR2BX2TS U1020 ( .AN(n2258), .B(n2259), .Y(n1142) );
CLKAND2X2TS U1021 ( .A(n2375), .B(n983), .Y(n2376) );
CLKBUFX2TS U1022 ( .A(n2888), .Y(n2701) );
INVX2TS U1023 ( .A(n1426), .Y(n1425) );
NOR2X2TS U1024 ( .A(n1128), .B(n1094), .Y(n1093) );
NAND2BXLTS U1025 ( .AN(n1727), .B(n1543), .Y(n1531) );
NAND2X2TS U1026 ( .A(n2885), .B(Raw_mant_NRM_SWR[22]), .Y(n1855) );
BUFX4TS U1027 ( .A(n2206), .Y(n2233) );
NAND2X6TS U1028 ( .A(n1043), .B(Raw_mant_NRM_SWR[4]), .Y(n1967) );
CLKBUFX2TS U1029 ( .A(Raw_mant_NRM_SWR[20]), .Y(n991) );
BUFX8TS U1030 ( .A(n1166), .Y(n1164) );
CLKAND2X2TS U1031 ( .A(n2443), .B(n2621), .Y(n1176) );
BUFX8TS U1032 ( .A(n1480), .Y(n885) );
INVX3TS U1033 ( .A(n1091), .Y(n1083) );
AOI22X1TS U1034 ( .A0(n1800), .A1(n2453), .B0(n1414), .B1(n2455), .Y(n2326)
);
CLKBUFX2TS U1035 ( .A(n2429), .Y(n935) );
BUFX8TS U1036 ( .A(n1361), .Y(n884) );
BUFX8TS U1037 ( .A(n2497), .Y(n1411) );
BUFX8TS U1038 ( .A(n1594), .Y(n998) );
NAND2X2TS U1039 ( .A(n1232), .B(n1231), .Y(n1230) );
NOR2X2TS U1040 ( .A(n1090), .B(n1082), .Y(n1081) );
OAI21X2TS U1041 ( .A0(n1540), .A1(n983), .B0(n1344), .Y(n1092) );
AOI22X1TS U1042 ( .A0(n2439), .A1(DmP_mant_SHT1_SW[2]), .B0(n1969), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1317) );
NAND4X2TS U1043 ( .A(n2014), .B(n2013), .C(n2012), .D(n2011), .Y(n2034) );
NAND2XLTS U1044 ( .A(n2481), .B(n1650), .Y(n1608) );
BUFX3TS U1045 ( .A(n2429), .Y(n934) );
NAND2X2TS U1046 ( .A(n1078), .B(n976), .Y(n1077) );
MXI2X4TS U1047 ( .A(n2567), .B(n2525), .S0(n2444), .Y(n2377) );
NOR2X1TS U1048 ( .A(n1371), .B(DmP_EXP_EWSW[23]), .Y(n2435) );
NAND2X2TS U1049 ( .A(n1630), .B(Raw_mant_NRM_SWR[18]), .Y(n1945) );
INVX2TS U1050 ( .A(n1542), .Y(n1540) );
NAND2BX1TS U1051 ( .AN(n1647), .B(n2494), .Y(n1860) );
INVX2TS U1052 ( .A(n1545), .Y(n983) );
INVX4TS U1053 ( .A(n1402), .Y(n1403) );
NAND2X6TS U1054 ( .A(n2493), .B(n1114), .Y(n1109) );
INVX4TS U1055 ( .A(n1433), .Y(n1434) );
NAND2X1TS U1056 ( .A(n2335), .B(n1800), .Y(n1231) );
AND2X2TS U1057 ( .A(n2402), .B(n1962), .Y(n1965) );
INVX3TS U1058 ( .A(n2374), .Y(n1128) );
BUFX4TS U1059 ( .A(n2651), .Y(n2481) );
CLKAND2X2TS U1060 ( .A(n2304), .B(n2303), .Y(n1293) );
AOI21X2TS U1061 ( .A0(n1172), .A1(n1343), .B0(n1001), .Y(n1161) );
NAND2X2TS U1062 ( .A(n1862), .B(n2356), .Y(n1458) );
NAND2X4TS U1063 ( .A(n1544), .B(n1539), .Y(n1538) );
CLKAND2X2TS U1064 ( .A(n2338), .B(n2419), .Y(n1305) );
NAND2X6TS U1065 ( .A(n1107), .B(Raw_mant_NRM_SWR[0]), .Y(n1026) );
INVX4TS U1066 ( .A(n1653), .Y(n988) );
NAND2X2TS U1067 ( .A(n1542), .B(n2375), .Y(n1094) );
NOR2X2TS U1068 ( .A(n1615), .B(n2494), .Y(n1610) );
NOR2X2TS U1069 ( .A(n1374), .B(n904), .Y(n2153) );
CLKINVX1TS U1070 ( .A(n2473), .Y(n1248) );
OR2X4TS U1071 ( .A(n1062), .B(n982), .Y(n944) );
AND2X4TS U1072 ( .A(n1616), .B(n1543), .Y(n1336) );
NAND2X1TS U1073 ( .A(n1469), .B(n1859), .Y(n1459) );
INVX3TS U1074 ( .A(n880), .Y(n879) );
BUFX6TS U1075 ( .A(n2444), .Y(n2443) );
INVX2TS U1076 ( .A(n2335), .Y(n2457) );
NAND2X1TS U1077 ( .A(n904), .B(n1374), .Y(n2152) );
INVX2TS U1078 ( .A(n2404), .Y(n1105) );
AND2X6TS U1079 ( .A(n2329), .B(n2348), .Y(n1209) );
BUFX3TS U1080 ( .A(n2501), .Y(n1000) );
OAI2BB1X1TS U1081 ( .A0N(DmP_mant_SHT1_SW[22]), .A1N(n1560), .B0(n1653), .Y(
n2058) );
INVX6TS U1082 ( .A(n2402), .Y(n1158) );
NOR2X2TS U1083 ( .A(n1157), .B(n2399), .Y(n1156) );
INVX2TS U1084 ( .A(n2494), .Y(n976) );
NOR2BX2TS U1085 ( .AN(n2139), .B(n2135), .Y(n1963) );
AND2X2TS U1086 ( .A(n980), .B(n2041), .Y(n1615) );
NAND2X1TS U1087 ( .A(n1028), .B(n1961), .Y(n1962) );
NAND2X1TS U1088 ( .A(n1913), .B(n2486), .Y(n1914) );
NAND2X4TS U1089 ( .A(n1627), .B(n1617), .Y(n1616) );
BUFX16TS U1090 ( .A(n1006), .Y(n1194) );
NAND2BX2TS U1091 ( .AN(n2372), .B(n2373), .Y(n1078) );
INVX4TS U1092 ( .A(n1819), .Y(n2461) );
INVX12TS U1093 ( .A(n1243), .Y(n936) );
INVX1TS U1094 ( .A(n2375), .Y(n1533) );
INVX2TS U1095 ( .A(n1062), .Y(n1007) );
NAND2X4TS U1096 ( .A(n1353), .B(n1352), .Y(n1351) );
NAND2X2TS U1097 ( .A(n1430), .B(n2483), .Y(n1917) );
AND2X4TS U1098 ( .A(n972), .B(n1859), .Y(n1460) );
NAND2X4TS U1099 ( .A(n972), .B(n1066), .Y(n1065) );
NAND2X4TS U1100 ( .A(n1453), .B(n972), .Y(n880) );
NAND2X2TS U1101 ( .A(n2024), .B(n969), .Y(n1792) );
NOR2X6TS U1102 ( .A(n1009), .B(n1063), .Y(n1008) );
NAND2X2TS U1103 ( .A(n1015), .B(n2462), .Y(n1916) );
NAND2X2TS U1104 ( .A(n2024), .B(n2365), .Y(n1828) );
AOI21X1TS U1105 ( .A0(n1028), .A1(Raw_mant_NRM_SWR[12]), .B0(n1571), .Y(
n1964) );
BUFX2TS U1106 ( .A(n2429), .Y(n932) );
NAND2X6TS U1107 ( .A(n1858), .B(n1859), .Y(n1090) );
INVX2TS U1108 ( .A(n982), .Y(n1098) );
BUFX6TS U1109 ( .A(n2420), .Y(n1061) );
NOR2X1TS U1110 ( .A(n2476), .B(n2474), .Y(n1143) );
NAND2X4TS U1111 ( .A(n2136), .B(n2135), .Y(n2141) );
INVX2TS U1112 ( .A(n1836), .Y(n1858) );
CLKINVX6TS U1113 ( .A(n2420), .Y(n1453) );
BUFX2TS U1114 ( .A(n2341), .Y(n1014) );
INVX6TS U1115 ( .A(n2040), .Y(n1627) );
AND2X6TS U1116 ( .A(n1214), .B(n1672), .Y(n947) );
INVX2TS U1117 ( .A(n532), .Y(n2135) );
NOR2X6TS U1118 ( .A(Shift_amount_SHT1_EWR[0]), .B(n1431), .Y(n1969) );
BUFX4TS U1119 ( .A(n2425), .Y(n1062) );
NOR2X4TS U1120 ( .A(n1929), .B(DMP_SFG[1]), .Y(n2249) );
NAND2X2TS U1121 ( .A(n986), .B(n2483), .Y(n1845) );
NAND2X6TS U1122 ( .A(n1831), .B(n1830), .Y(n2318) );
INVX2TS U1123 ( .A(n1431), .Y(n1560) );
INVX4TS U1124 ( .A(n1724), .Y(n1066) );
NAND2X2TS U1125 ( .A(n1808), .B(n981), .Y(n1352) );
XNOR2X2TS U1126 ( .A(n1391), .B(n1497), .Y(n1976) );
XNOR2X2TS U1127 ( .A(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n1991) );
XNOR2X2TS U1128 ( .A(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1985) );
XNOR2X2TS U1129 ( .A(intDY_EWSW[15]), .B(intDX_EWSW[15]), .Y(n1997) );
NAND2X4TS U1130 ( .A(n2023), .B(n986), .Y(n1018) );
XNOR2X2TS U1131 ( .A(intDY_EWSW[4]), .B(intDX_EWSW[4]), .Y(n1995) );
XNOR2X2TS U1132 ( .A(n889), .B(intDX_EWSW[2]), .Y(n1996) );
XNOR2X1TS U1133 ( .A(intDY_EWSW[5]), .B(intDX_EWSW[5]), .Y(n2002) );
INVX12TS U1134 ( .A(n1243), .Y(n1414) );
NAND2X1TS U1135 ( .A(n1913), .B(n2465), .Y(n1672) );
NAND2X1TS U1136 ( .A(n1937), .B(n1387), .Y(n1831) );
AND2X6TS U1137 ( .A(n1328), .B(n2348), .Y(n1940) );
OR2X4TS U1138 ( .A(n2345), .B(n2358), .Y(n1243) );
NAND2X6TS U1139 ( .A(n971), .B(n2040), .Y(n1071) );
INVX12TS U1140 ( .A(n1857), .Y(n972) );
AND2X4TS U1141 ( .A(n1691), .B(n1703), .Y(n964) );
NAND4X6TS U1142 ( .A(n1670), .B(n2765), .C(n2764), .D(n2763), .Y(n2453) );
CLKINVX6TS U1143 ( .A(n1170), .Y(n1030) );
NAND2X2TS U1144 ( .A(n1927), .B(n1430), .Y(n1466) );
NOR2X2TS U1145 ( .A(n1961), .B(n1959), .Y(n1960) );
INVX6TS U1146 ( .A(n980), .Y(n888) );
NOR2X2TS U1147 ( .A(n2361), .B(n2391), .Y(n1886) );
NOR2X2TS U1148 ( .A(n973), .B(n2137), .Y(n1570) );
CLKINVX6TS U1149 ( .A(n1363), .Y(n1059) );
NAND2X1TS U1150 ( .A(n1704), .B(n1957), .Y(n1706) );
AND2X2TS U1151 ( .A(n2776), .B(n2777), .Y(n1227) );
AND2X2TS U1152 ( .A(n2807), .B(n2808), .Y(n1354) );
INVX6TS U1153 ( .A(n1718), .Y(n971) );
NAND2X6TS U1154 ( .A(n1120), .B(n1190), .Y(n1591) );
NAND2X6TS U1155 ( .A(n1933), .B(DMP_SFG[4]), .Y(n2258) );
NAND2X6TS U1156 ( .A(n2375), .B(n2422), .Y(n1857) );
NAND3X2TS U1157 ( .A(n1271), .B(n1262), .C(n2708), .Y(n1268) );
INVX3TS U1158 ( .A(n1383), .Y(n1869) );
NAND2X6TS U1159 ( .A(n1640), .B(n1318), .Y(n1170) );
INVX4TS U1160 ( .A(n1957), .Y(n2137) );
NAND2X6TS U1161 ( .A(n2139), .B(n1674), .Y(n1705) );
XNOR2X2TS U1162 ( .A(n1319), .B(DMP_exp_NRM2_EW[0]), .Y(n2391) );
INVX2TS U1163 ( .A(n1931), .Y(n2477) );
BUFX6TS U1164 ( .A(n1718), .Y(n1063) );
NOR3X4TS U1165 ( .A(n1688), .B(n1347), .C(n1695), .Y(n1691) );
INVX2TS U1166 ( .A(n2248), .Y(n1571) );
AND4X4TS U1167 ( .A(n2806), .B(n2805), .C(n2804), .D(n2803), .Y(n1383) );
AND3X2TS U1168 ( .A(n2724), .B(n2723), .C(n2722), .Y(n908) );
INVX8TS U1169 ( .A(n956), .Y(n982) );
AND2X6TS U1170 ( .A(n1719), .B(DMP_SFG[18]), .Y(n1545) );
AND2X6TS U1171 ( .A(n1237), .B(n1238), .Y(n1122) );
NOR2X4TS U1172 ( .A(n1655), .B(DMP_exp_NRM2_EW[4]), .Y(n2509) );
INVX2TS U1173 ( .A(n1112), .Y(n1110) );
NAND2X6TS U1174 ( .A(n1938), .B(n2569), .Y(n1812) );
CLKINVX6TS U1175 ( .A(n1698), .Y(n1188) );
INVX2TS U1176 ( .A(n2421), .Y(n1721) );
AND2X2TS U1177 ( .A(n1759), .B(n1758), .Y(n1192) );
AND2X4TS U1178 ( .A(n1701), .B(n1472), .Y(n963) );
INVX4TS U1179 ( .A(n2356), .Y(n989) );
NOR2X4TS U1180 ( .A(n1242), .B(n1240), .Y(n1190) );
NAND2X2TS U1181 ( .A(n1881), .B(n1891), .Y(n1882) );
INVX2TS U1182 ( .A(n1893), .Y(n1881) );
INVX2TS U1183 ( .A(n1889), .Y(n1876) );
OR2X6TS U1184 ( .A(n1716), .B(DMP_SFG[16]), .Y(n956) );
NAND2X1TS U1185 ( .A(n1389), .B(n1393), .Y(n1666) );
NAND2X4TS U1186 ( .A(n1658), .B(DMP_exp_NRM2_EW[2]), .Y(n1892) );
NOR2X4TS U1187 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .Y(n1347)
);
NAND2X2TS U1188 ( .A(n1723), .B(DMP_SFG[21]), .Y(n1837) );
OR2X4TS U1189 ( .A(n1714), .B(DMP_SFG[14]), .Y(n1454) );
NAND2X1TS U1190 ( .A(DMP_SFG[12]), .B(n1375), .Y(n2409) );
NAND2X4TS U1191 ( .A(n1236), .B(n1505), .Y(n1235) );
NOR2X6TS U1192 ( .A(n1242), .B(n1241), .Y(n1237) );
NOR2X4TS U1193 ( .A(n1394), .B(n1389), .Y(n1938) );
INVX8TS U1194 ( .A(n2342), .Y(n1258) );
INVX12TS U1195 ( .A(n2460), .Y(n967) );
NOR2X6TS U1196 ( .A(n990), .B(n1470), .Y(n1472) );
INVX8TS U1197 ( .A(n1215), .Y(n2418) );
NAND2X4TS U1198 ( .A(n1097), .B(n2427), .Y(n1115) );
NAND2XLTS U1199 ( .A(n2575), .B(intDX_EWSW[30]), .Y(n1757) );
INVX12TS U1200 ( .A(n1260), .Y(n2342) );
NAND2X2TS U1201 ( .A(DmP_mant_SFG_SWR_signed[11]), .B(DMP_SFG[9]), .Y(n2052)
);
NAND2X4TS U1202 ( .A(n1749), .B(n1741), .Y(n1241) );
NOR2X6TS U1203 ( .A(n2416), .B(n1393), .Y(n1937) );
INVX8TS U1204 ( .A(n1174), .Y(n1328) );
NAND2X6TS U1205 ( .A(n1731), .B(n1758), .Y(n1242) );
CLKINVX6TS U1206 ( .A(n1162), .Y(n1550) );
INVX4TS U1207 ( .A(n1038), .Y(n1315) );
NOR2X6TS U1208 ( .A(n1038), .B(n1308), .Y(n1037) );
AND2X4TS U1209 ( .A(n1679), .B(n1642), .Y(n1118) );
NOR2X6TS U1210 ( .A(n1510), .B(n1509), .Y(n1508) );
NAND3X6TS U1211 ( .A(n1150), .B(n1151), .C(n1684), .Y(n1112) );
INVX3TS U1212 ( .A(n1510), .Y(n1505) );
OR2X4TS U1213 ( .A(n1710), .B(n2292), .Y(n1527) );
INVX4TS U1214 ( .A(n1154), .Y(n973) );
NAND2X4TS U1215 ( .A(n1597), .B(n1773), .Y(n1509) );
OR4X6TS U1216 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[6]), .C(
Raw_mant_NRM_SWR[5]), .D(Raw_mant_NRM_SWR[7]), .Y(n1324) );
NAND2X1TS U1217 ( .A(n2591), .B(intDX_EWSW[19]), .Y(n1734) );
NAND2X4TS U1218 ( .A(n1687), .B(n1307), .Y(n1038) );
INVX2TS U1219 ( .A(n2576), .Y(n1198) );
INVX2TS U1220 ( .A(n2596), .Y(n1203) );
NAND2X4TS U1221 ( .A(n1714), .B(DMP_SFG[14]), .Y(n2338) );
NAND2X4TS U1222 ( .A(n1311), .B(DMP_exp_NRM2_EW[1]), .Y(n1887) );
NAND2X2TS U1223 ( .A(n2587), .B(intDX_EWSW[26]), .Y(n1199) );
NAND2X2TS U1224 ( .A(n2572), .B(intDX_EWSW[14]), .Y(n1776) );
NAND2X2TS U1225 ( .A(n2594), .B(intDX_EWSW[20]), .Y(n1743) );
NAND2X4TS U1226 ( .A(n1773), .B(n1506), .Y(n1379) );
NAND2X4TS U1227 ( .A(n1685), .B(n1686), .Y(n1698) );
AND3X2TS U1228 ( .A(n1634), .B(n2877), .C(n1660), .Y(n1642) );
NAND2X2TS U1229 ( .A(n1697), .B(n1660), .Y(n1699) );
NAND2X4TS U1230 ( .A(n1486), .B(n1485), .Y(n1484) );
NAND2X2TS U1231 ( .A(n2570), .B(intDX_EWSW[24]), .Y(n1204) );
NAND2X6TS U1232 ( .A(n1559), .B(n1450), .Y(n1510) );
NOR2X2TS U1233 ( .A(n2530), .B(Raw_mant_NRM_SWR[19]), .Y(n1684) );
INVX2TS U1234 ( .A(intDX_EWSW[27]), .Y(n1197) );
NAND2X2TS U1235 ( .A(n2580), .B(intDX_EWSW[15]), .Y(n1775) );
OR2X4TS U1236 ( .A(n2575), .B(intDX_EWSW[30]), .Y(n1758) );
NAND2X2TS U1237 ( .A(n2571), .B(intDX_EWSW[22]), .Y(n1746) );
INVX2TS U1238 ( .A(n1710), .Y(n1525) );
INVX2TS U1239 ( .A(n1649), .Y(n1132) );
CLKINVX2TS U1240 ( .A(n1395), .Y(n1396) );
NOR2X2TS U1241 ( .A(n2882), .B(n2826), .Y(n1685) );
NOR2X6TS U1242 ( .A(Raw_mant_NRM_SWR[14]), .B(n1385), .Y(n1693) );
NOR2X6TS U1243 ( .A(n2596), .B(intDX_EWSW[25]), .Y(n1752) );
NOR2X6TS U1244 ( .A(n2579), .B(intDX_EWSW[17]), .Y(n1760) );
CLKAND2X2TS U1245 ( .A(n2822), .B(Raw_mant_NRM_SWR[8]), .Y(n1134) );
NAND2X2TS U1246 ( .A(DmP_mant_SFG_SWR_signed[9]), .B(DMP_SFG[7]), .Y(n2279)
);
NAND2X2TS U1247 ( .A(n2588), .B(intDX_EWSW[10]), .Y(n1771) );
NOR2X4TS U1248 ( .A(n1306), .B(Raw_mant_NRM_SWR[25]), .Y(n1607) );
INVX2TS U1249 ( .A(n1310), .Y(n1311) );
INVX3TS U1250 ( .A(Raw_mant_NRM_SWR[15]), .Y(n1634) );
NOR2X6TS U1251 ( .A(n1772), .B(n1599), .Y(n1773) );
NOR2X4TS U1252 ( .A(n1774), .B(n1451), .Y(n1450) );
NOR2X4TS U1253 ( .A(n2587), .B(intDX_EWSW[26]), .Y(n1200) );
NOR2X4TS U1254 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR_signed[11]), .Y(n1710)
);
AND2X4TS U1255 ( .A(n1222), .B(n1473), .Y(n961) );
NOR2X4TS U1256 ( .A(n1769), .B(n1598), .Y(n1597) );
CLKINVX6TS U1257 ( .A(n1005), .Y(n1036) );
NAND2X4TS U1258 ( .A(n1222), .B(n872), .Y(n1034) );
OR2X4TS U1259 ( .A(intDY_EWSW[2]), .B(n917), .Y(n1763) );
NAND2BX2TS U1260 ( .AN(n1362), .B(intDX_EWSW[3]), .Y(n1762) );
NOR2X6TS U1261 ( .A(n2586), .B(intDX_EWSW[2]), .Y(n1440) );
NAND2X2TS U1262 ( .A(n1392), .B(intDX_EWSW[1]), .Y(n1490) );
NAND2X4TS U1263 ( .A(n2585), .B(intDX_EWSW[4]), .Y(n1217) );
INVX4TS U1264 ( .A(n1306), .Y(n1307) );
BUFX16TS U1265 ( .A(Raw_mant_NRM_SWR[25]), .Y(n898) );
NAND2X8TS U1266 ( .A(n1361), .B(intDY_EWSW[23]), .Y(n2128) );
NAND2X6TS U1267 ( .A(intDY_EWSW[6]), .B(n1480), .Y(n2227) );
NAND2X4TS U1268 ( .A(n882), .B(n1512), .Y(n2235) );
AOI21X2TS U1269 ( .A0(n2461), .A1(n969), .B0(n2489), .Y(n2926) );
NAND2X4TS U1270 ( .A(n969), .B(n1940), .Y(n1016) );
NAND2X4TS U1271 ( .A(n1321), .B(n1164), .Y(n1949) );
NAND2X2TS U1272 ( .A(n1565), .B(n1321), .Y(n2984) );
XNOR2X2TS U1273 ( .A(n2301), .B(n2300), .Y(n2302) );
MXI2X4TS U1274 ( .A(n3032), .B(n2662), .S0(n934), .Y(n481) );
NAND2X4TS U1275 ( .A(n1565), .B(n1322), .Y(n2991) );
NAND2X4TS U1276 ( .A(n1565), .B(n1329), .Y(n2940) );
NAND2X4TS U1277 ( .A(n1565), .B(n1326), .Y(n3020) );
NAND2X4TS U1278 ( .A(n1565), .B(n1325), .Y(n2935) );
NAND2X4TS U1279 ( .A(n1565), .B(n1323), .Y(n2999) );
AND2X8TS U1280 ( .A(n2312), .B(n2311), .Y(n3049) );
XNOR2X4TS U1281 ( .A(n2412), .B(n2411), .Y(n2413) );
OAI21X4TS U1282 ( .A0(n2408), .A1(n2407), .B0(n2406), .Y(n2412) );
AOI2BB2X4TS U1283 ( .B0(n2472), .B1(DmP_mant_SHT1_SW[17]), .A0N(n1411),
.A1N(n2606), .Y(n3018) );
BUFX20TS U1284 ( .A(n2501), .Y(n2885) );
MXI2X4TS U1285 ( .A(n3029), .B(n2661), .S0(n933), .Y(n484) );
AND2X8TS U1286 ( .A(n1924), .B(n1923), .Y(n3029) );
AOI21X2TS U1287 ( .A0(n2472), .A1(DmP_mant_SHT1_SW[12]), .B0(n2467), .Y(
n2982) );
CLKINVX12TS U1288 ( .A(n890), .Y(n2397) );
NAND2X4TS U1289 ( .A(n3003), .B(n2883), .Y(n3007) );
NAND2X2TS U1290 ( .A(n2994), .B(n2883), .Y(n2998) );
NAND2X4TS U1291 ( .A(n2883), .B(n1320), .Y(n2932) );
NAND2X8TS U1292 ( .A(n1960), .B(n992), .Y(n2402) );
AND2X6TS U1293 ( .A(n2321), .B(n2320), .Y(n3057) );
INVX16TS U1294 ( .A(n2884), .Y(n1565) );
AND2X4TS U1295 ( .A(n1000), .B(Raw_mant_NRM_SWR[7]), .Y(n1323) );
NAND2X8TS U1296 ( .A(n1823), .B(n1969), .Y(n1648) );
NAND4X2TS U1297 ( .A(n1984), .B(n1983), .C(n1982), .D(n1981), .Y(n1990) );
NAND2X4TS U1298 ( .A(n1480), .B(intDY_EWSW[26]), .Y(n2131) );
INVX16TS U1299 ( .A(n1648), .Y(n2489) );
NAND4X2TS U1300 ( .A(n1988), .B(n1987), .C(n1986), .D(n1985), .Y(n1989) );
BUFX6TS U1301 ( .A(n1028), .Y(n992) );
NAND4X2TS U1302 ( .A(n1994), .B(n1993), .C(n1992), .D(n1991), .Y(n2000) );
NOR2X4TS U1303 ( .A(n2383), .B(n2382), .Y(n558) );
INVX8TS U1304 ( .A(n1269), .Y(n1786) );
MXI2X4TS U1305 ( .A(n3047), .B(n2664), .S0(n935), .Y(n473) );
AND2X8TS U1306 ( .A(n2327), .B(n2326), .Y(n3047) );
OAI21X2TS U1307 ( .A0(n2397), .A1(n2393), .B0(n2394), .Y(n2282) );
NAND2X6TS U1308 ( .A(n956), .B(n2427), .Y(n1718) );
NAND2X6TS U1309 ( .A(n2317), .B(n1415), .Y(n1600) );
NAND2X8TS U1310 ( .A(n1930), .B(DMP_SFG[2]), .Y(n2473) );
AOI21X2TS U1311 ( .A0(n1274), .A1(n2733), .B0(n2732), .Y(n1807) );
XOR2X4TS U1312 ( .A(n2475), .B(n2256), .Y(n2257) );
CLKINVX12TS U1313 ( .A(n1812), .Y(n1430) );
NAND3X6TS U1314 ( .A(n1498), .B(n1636), .C(n1965), .Y(n2239) );
NAND2X6TS U1315 ( .A(n2146), .B(n1431), .Y(n2308) );
NAND4BX4TS U1316 ( .AN(n2145), .B(n2144), .C(n2143), .D(n2142), .Y(n2146) );
NAND3X4TS U1317 ( .A(n2118), .B(n2117), .C(n2116), .Y(n753) );
NAND3X4TS U1318 ( .A(n2091), .B(n2090), .C(n2089), .Y(n732) );
NAND2X8TS U1319 ( .A(n1697), .B(n1386), .Y(n1690) );
BUFX20TS U1320 ( .A(n986), .Y(n1015) );
NAND3X4TS U1321 ( .A(n2237), .B(n2238), .C(n2236), .Y(n723) );
AO21X4TS U1322 ( .A0(n2254), .A1(n2255), .B0(n1248), .Y(n2480) );
NAND3X4TS U1323 ( .A(n2079), .B(n2078), .C(n2077), .Y(n733) );
NAND2X8TS U1324 ( .A(n1603), .B(n1602), .Y(n1922) );
NAND3X4TS U1325 ( .A(n2134), .B(n2133), .C(n2132), .Y(n562) );
NAND2X4TS U1326 ( .A(n978), .B(intDX_EWSW[24]), .Y(n2124) );
NAND3X4TS U1327 ( .A(n1936), .B(n1935), .C(n1934), .Y(n738) );
CLKINVX12TS U1328 ( .A(n2341), .Y(n986) );
OAI2BB1X4TS U1329 ( .A0N(n2453), .A1N(n986), .B0(n1872), .Y(n1234) );
AND3X8TS U1330 ( .A(n1439), .B(n1816), .C(n1438), .Y(n3045) );
NAND2X4TS U1331 ( .A(n1502), .B(n2883), .Y(n2973) );
NAND2X8TS U1332 ( .A(n1524), .B(n1305), .Y(n1523) );
NAND2X2TS U1333 ( .A(n3013), .B(n1565), .Y(n3017) );
NAND2X8TS U1334 ( .A(n1867), .B(n1169), .Y(n3013) );
NAND3X4TS U1335 ( .A(n2181), .B(n2180), .C(n2179), .Y(n566) );
BUFX20TS U1336 ( .A(n2232), .Y(n886) );
NAND3X8TS U1337 ( .A(n1076), .B(n958), .C(n1074), .Y(n518) );
NAND3X4TS U1338 ( .A(n2368), .B(n2367), .C(n2366), .Y(n2929) );
NAND2X8TS U1339 ( .A(n1326), .B(n1164), .Y(n2368) );
NAND3X4TS U1340 ( .A(n1953), .B(n1952), .C(n1951), .Y(n2986) );
NAND2X6TS U1341 ( .A(n1329), .B(n1164), .Y(n1953) );
NAND3X4TS U1342 ( .A(n1949), .B(n1948), .C(n1947), .Y(n2937) );
NAND4X8TS U1343 ( .A(n1182), .B(n1181), .C(n1180), .D(n1179), .Y(n1178) );
NAND3X8TS U1344 ( .A(n1459), .B(n1051), .C(n1050), .Y(n1052) );
INVX12TS U1345 ( .A(n1689), .Y(n2136) );
MXI2X4TS U1346 ( .A(n3043), .B(n2665), .S0(n934), .Y(n475) );
INVX16TS U1347 ( .A(n2495), .Y(n1413) );
AOI22X4TS U1348 ( .A0(n1414), .A1(n2319), .B0(n2330), .B1(n2318), .Y(n1832)
);
CLKINVX12TS U1349 ( .A(n1109), .Y(n1643) );
MXI2X4TS U1350 ( .A(n3041), .B(n2666), .S0(n933), .Y(n476) );
NAND2X8TS U1351 ( .A(n980), .B(n971), .Y(n2420) );
NAND2X6TS U1352 ( .A(n1805), .B(n1804), .Y(n2990) );
NAND2X4TS U1353 ( .A(n1135), .B(Raw_mant_NRM_SWR[14]), .Y(n1805) );
INVX12TS U1354 ( .A(n1822), .Y(n1823) );
NAND3X4TS U1355 ( .A(n2245), .B(n2244), .C(n2243), .Y(n725) );
NAND3X4TS U1356 ( .A(n2196), .B(n2195), .C(n2194), .Y(n572) );
BUFX20TS U1357 ( .A(n1162), .Y(n1172) );
NAND2X2TS U1358 ( .A(n1108), .B(Raw_mant_NRM_SWR[3]), .Y(n3023) );
NAND3X8TS U1359 ( .A(n1086), .B(n1084), .C(n1080), .Y(n520) );
OR2X8TS U1360 ( .A(n1085), .B(n1089), .Y(n1084) );
NAND2X6TS U1361 ( .A(n1005), .B(n1042), .Y(n1041) );
AOI21X2TS U1362 ( .A0(n2489), .A1(DmP_mant_SHT1_SW[14]), .B0(n2488), .Y(
n2959) );
NAND2X8TS U1363 ( .A(n1791), .B(n1604), .Y(n1941) );
AOI22X4TS U1364 ( .A0(n1928), .A1(n1434), .B0(n1927), .B1(n936), .Y(n3061)
);
NAND3X6TS U1365 ( .A(n1008), .B(n1006), .C(n1007), .Y(n1449) );
NAND3X6TS U1366 ( .A(n1083), .B(n1081), .C(n1085), .Y(n1080) );
NOR2X2TS U1367 ( .A(n2341), .B(n2019), .Y(n2022) );
BUFX20TS U1368 ( .A(n2921), .Y(n993) );
NOR2X6TS U1369 ( .A(n1650), .B(n1306), .Y(n1150) );
CLKINVX12TS U1370 ( .A(n1471), .Y(n990) );
NAND3X4TS U1371 ( .A(n2044), .B(n2043), .C(n2042), .Y(n728) );
INVX3TS U1372 ( .A(n1630), .Y(n1631) );
NAND2X2TS U1373 ( .A(n1495), .B(intDX_EWSW[22]), .Y(n2180) );
NAND3X2TS U1374 ( .A(n1495), .B(n2030), .C(n2034), .Y(n2018) );
INVX12TS U1375 ( .A(n1106), .Y(n1107) );
NAND2X4TS U1376 ( .A(n1107), .B(Raw_mant_NRM_SWR[21]), .Y(n996) );
OR2X4TS U1377 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[25]), .Y(n1184) );
INVX12TS U1378 ( .A(n1194), .Y(n1524) );
INVX16TS U1379 ( .A(n1102), .Y(n1006) );
NAND3X8TS U1380 ( .A(n1523), .B(n1573), .C(n1522), .Y(n1579) );
NAND2X4TS U1381 ( .A(n2640), .B(DMP_EXP_EWSW[17]), .Y(n2080) );
NAND2X8TS U1382 ( .A(n2222), .B(intDX_EWSW[9]), .Y(n2093) );
BUFX20TS U1383 ( .A(n1102), .Y(n1072) );
NAND2X4TS U1384 ( .A(n2494), .B(n991), .Y(n1622) );
NAND2X8TS U1385 ( .A(n979), .B(n879), .Y(n1085) );
XOR2X4TS U1386 ( .A(n1293), .B(n1148), .Y(n1147) );
NAND2X6TS U1387 ( .A(n1147), .B(n1146), .Y(n1145) );
BUFX20TS U1388 ( .A(n2920), .Y(n1503) );
NAND2X8TS U1389 ( .A(n1195), .B(n1391), .Y(n2121) );
XNOR2X4TS U1390 ( .A(n881), .B(DMP_exp_NRM2_EW[5]), .Y(n2505) );
OAI21X4TS U1391 ( .A0(n1654), .A1(n2509), .B0(n2506), .Y(n881) );
NAND2X8TS U1392 ( .A(n1361), .B(n883), .Y(n1955) );
BUFX16TS U1393 ( .A(n2103), .Y(n1361) );
NAND2X8TS U1394 ( .A(n2222), .B(intDX_EWSW[27]), .Y(n2150) );
CLKBUFX2TS U1395 ( .A(intDY_EWSW[7]), .Y(n882) );
NAND3X6TS U1396 ( .A(n2226), .B(n2227), .C(n2225), .Y(n598) );
NAND3X6TS U1397 ( .A(n2209), .B(n2208), .C(n2207), .Y(n594) );
OAI21X4TS U1398 ( .A0(n1441), .A1(n1763), .B0(n1762), .Y(n1488) );
AND2X8TS U1399 ( .A(n1399), .B(n1362), .Y(n1441) );
CLKBUFX2TS U1400 ( .A(intDX_EWSW[4]), .Y(n883) );
NOR2X8TS U1401 ( .A(n1215), .B(n2338), .Y(n1621) );
NOR2X8TS U1402 ( .A(n1715), .B(DMP_SFG[15]), .Y(n1215) );
INVX8TS U1403 ( .A(n1932), .Y(n1933) );
NAND2X8TS U1404 ( .A(n1060), .B(n1059), .Y(n1058) );
NAND2X8TS U1405 ( .A(n887), .B(n1627), .Y(n1613) );
NAND2X8TS U1406 ( .A(n1617), .B(n888), .Y(n887) );
NOR2X6TS U1407 ( .A(n1740), .B(n1747), .Y(n1749) );
OR2X8TS U1408 ( .A(n979), .B(n1611), .Y(n1334) );
BUFX6TS U1409 ( .A(intDY_EWSW[2]), .Y(n889) );
AO21X4TS U1410 ( .A0(n2048), .A1(n2047), .B0(n2046), .Y(n890) );
NOR2X4TS U1411 ( .A(DMP_SFG[3]), .B(n2875), .Y(n2476) );
AND2X4TS U1412 ( .A(n1682), .B(n2400), .Y(n1569) );
NAND2X6TS U1413 ( .A(n2139), .B(n1674), .Y(n891) );
INVX12TS U1414 ( .A(n2493), .Y(n1456) );
NAND2X4TS U1415 ( .A(n1003), .B(n533), .Y(n2969) );
NAND2X4TS U1416 ( .A(n1003), .B(Raw_mant_NRM_SWR[5]), .Y(n3022) );
NAND2X4TS U1417 ( .A(n1003), .B(Raw_mant_NRM_SWR[19]), .Y(n2933) );
NAND2X4TS U1418 ( .A(n1003), .B(Raw_mant_NRM_SWR[2]), .Y(n2978) );
NOR2X6TS U1419 ( .A(n1695), .B(n1702), .Y(n1159) );
BUFX20TS U1420 ( .A(n2443), .Y(n900) );
NAND2X2TS U1421 ( .A(n1480), .B(intDY_EWSW[24]), .Y(n2125) );
NAND3X6TS U1422 ( .A(n2405), .B(n2410), .C(n1521), .Y(n1520) );
BUFX12TS U1423 ( .A(n2223), .Y(n2232) );
NAND2X8TS U1424 ( .A(n2222), .B(intDX_EWSW[8]), .Y(n2108) );
NAND3X6TS U1425 ( .A(n1446), .B(n1445), .C(n1444), .Y(n517) );
INVX16TS U1426 ( .A(n1054), .Y(n1127) );
NAND2X4TS U1427 ( .A(intDX_EWSW[10]), .B(n2222), .Y(n2096) );
NAND2X6TS U1428 ( .A(n2222), .B(intDY_EWSW[8]), .Y(n2209) );
NAND2X4TS U1429 ( .A(n2232), .B(intDY_EWSW[17]), .Y(n2082) );
NAND2X4TS U1430 ( .A(n2232), .B(intDY_EWSW[4]), .Y(n1956) );
NAND2X4TS U1431 ( .A(n2232), .B(intDX_EWSW[8]), .Y(n2208) );
NAND2X2TS U1432 ( .A(n1418), .B(intDX_EWSW[5]), .Y(n2177) );
NAND2X2TS U1433 ( .A(n1593), .B(intDX_EWSW[10]), .Y(n2168) );
NAND2X2TS U1434 ( .A(n1593), .B(intDX_EWSW[26]), .Y(n2130) );
NAND2X2TS U1435 ( .A(n1593), .B(intDX_EWSW[16]), .Y(n2183) );
NAND2X2TS U1436 ( .A(n1593), .B(intDY_EWSW[6]), .Y(n2063) );
NAND2X4TS U1437 ( .A(intDX_EWSW[3]), .B(n1513), .Y(n2111) );
NAND2X4TS U1438 ( .A(n1513), .B(intDY_EWSW[10]), .Y(n2169) );
INVX6TS U1439 ( .A(n903), .Y(n904) );
INVX6TS U1440 ( .A(n906), .Y(n907) );
NAND4X8TS U1441 ( .A(n908), .B(n1783), .C(n2858), .D(n2857), .Y(n2454) );
NAND2X8TS U1442 ( .A(n2526), .B(n1154), .Y(n1162) );
NAND2X8TS U1443 ( .A(n1348), .B(n2633), .Y(n2375) );
NAND2X4TS U1444 ( .A(n1132), .B(n1697), .Y(n1131) );
NAND2X4TS U1445 ( .A(n1398), .B(intDY_EWSW[0]), .Y(n2160) );
NAND2X4TS U1446 ( .A(intDX_EWSW[22]), .B(n1398), .Y(n2087) );
NAND3X8TS U1447 ( .A(n1026), .B(n1504), .C(n1025), .Y(n2976) );
INVX12TS U1448 ( .A(n1129), .Y(n1046) );
BUFX12TS U1449 ( .A(n2103), .Y(n1512) );
BUFX20TS U1450 ( .A(n2103), .Y(n1513) );
NAND3X6TS U1451 ( .A(n2230), .B(n2229), .C(n2228), .Y(n608) );
INVX6TS U1452 ( .A(n1114), .Y(n1106) );
NAND2X1TS U1453 ( .A(n1189), .B(n1306), .Y(n2945) );
NAND2X1TS U1454 ( .A(n1189), .B(Raw_mant_NRM_SWR[6]), .Y(n3002) );
BUFX20TS U1455 ( .A(n2441), .Y(n924) );
CLKMX2X4TS U1456 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n924),
.Y(n694) );
CLKMX2X4TS U1457 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n924),
.Y(n691) );
CLKMX2X4TS U1458 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n924),
.Y(n629) );
CLKMX2X4TS U1459 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n924),
.Y(n709) );
CLKMX2X4TS U1460 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n924),
.Y(n706) );
CLKMX2X4TS U1461 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n924),
.Y(n688) );
CLKMX2X4TS U1462 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n924),
.Y(n697) );
CLKMX2X4TS U1463 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n924),
.Y(n703) );
CLKMX2X4TS U1464 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n924),
.Y(n685) );
CLKMX2X4TS U1465 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n2441),
.Y(n700) );
NAND2X4TS U1466 ( .A(n1593), .B(intDY_EWSW[22]), .Y(n2088) );
CLKINVX1TS U1467 ( .A(rst), .Y(n930) );
MXI2X2TS U1468 ( .A(n2536), .B(n2615), .S0(n935), .Y(n651) );
BUFX8TS U1469 ( .A(n2444), .Y(n2429) );
AOI22X2TS U1470 ( .A0(n936), .A1(n2339), .B0(n2330), .B1(n1922), .Y(n1923)
);
NAND2X1TS U1471 ( .A(n2233), .B(DmP_EXP_EWSW[23]), .Y(n2126) );
INVX2TS U1472 ( .A(n2622), .Y(n937) );
INVX2TS U1473 ( .A(n937), .Y(n938) );
INVX2TS U1474 ( .A(n2623), .Y(n939) );
INVX2TS U1475 ( .A(n939), .Y(n940) );
BUFX3TS U1476 ( .A(n2889), .Y(n2700) );
INVX2TS U1477 ( .A(n1391), .Y(n1392) );
NAND2X2TS U1478 ( .A(n2584), .B(intDX_EWSW[8]), .Y(n1455) );
NAND2X2TS U1479 ( .A(n1396), .B(intDX_EWSW[18]), .Y(n1735) );
CLKINVX6TS U1480 ( .A(Raw_mant_NRM_SWR[8]), .Y(n1042) );
AND2X2TS U1481 ( .A(n1676), .B(Raw_mant_NRM_SWR[11]), .Y(n1318) );
OA21X2TS U1482 ( .A0(n2137), .A1(n965), .B0(n2612), .Y(n1157) );
AND2X4TS U1483 ( .A(n2361), .B(n2391), .Y(n1908) );
XNOR2X1TS U1484 ( .A(intDY_EWSW[11]), .B(intDX_EWSW[11]), .Y(n1993) );
NAND2X2TS U1485 ( .A(n2742), .B(n1259), .Y(n1847) );
NAND4X1TS U1486 ( .A(n1998), .B(n1997), .C(n1996), .D(n1995), .Y(n1999) );
NOR2X4TS U1487 ( .A(n1431), .B(Shift_amount_SHT1_EWR[1]), .Y(n1820) );
NAND2X4TS U1488 ( .A(DmP_mant_SFG_SWR_signed[8]), .B(DMP_SFG[6]), .Y(n2394)
);
NAND2X1TS U1489 ( .A(n1418), .B(intDX_EWSW[0]), .Y(n2159) );
NAND2X1TS U1490 ( .A(n2481), .B(Raw_mant_NRM_SWR[15]), .Y(n1144) );
OR2X1TS U1491 ( .A(n1653), .B(n2039), .Y(n1638) );
NAND2X2TS U1492 ( .A(n998), .B(intDX_EWSW[21]), .Y(n2171) );
XOR2X2TS U1493 ( .A(n478), .B(n2377), .Y(n2797) );
AND2X4TS U1494 ( .A(n1502), .B(Raw_mant_NRM_SWR[17]), .Y(n946) );
CLKMX2X2TS U1495 ( .A(n975), .B(n2925), .S0(n2503), .Y(n948) );
NAND2X2TS U1496 ( .A(n1594), .B(intDY_EWSW[5]), .Y(n949) );
OR2X6TS U1497 ( .A(Raw_mant_NRM_SWR[22]), .B(Raw_mant_NRM_SWR[20]), .Y(n954)
);
OA21X4TS U1498 ( .A0(n1396), .A1(intDX_EWSW[18]), .B0(n1557), .Y(n955) );
OA21X4TS U1499 ( .A0(n1077), .A1(n1127), .B0(n1608), .Y(n958) );
AND3X6TS U1500 ( .A(n2528), .B(n2400), .C(n1385), .Y(n959) );
AND2X8TS U1501 ( .A(n1152), .B(n1112), .Y(n960) );
INVX2TS U1502 ( .A(n1167), .Y(n1412) );
AND2X6TS U1503 ( .A(n1195), .B(intDY_EWSW[24]), .Y(n966) );
INVX12TS U1504 ( .A(n967), .Y(n968) );
CLKINVX12TS U1505 ( .A(n967), .Y(n969) );
MXI2X8TS U1506 ( .A(n3040), .B(n2620), .S0(n900), .Y(n477) );
NAND3X4TS U1507 ( .A(n2159), .B(n2160), .C(n2158), .Y(n610) );
NAND3X2TS U1508 ( .A(n2308), .B(n2148), .C(n2147), .Y(n767) );
NAND2X4TS U1509 ( .A(n2355), .B(n2455), .Y(n1179) );
NOR2X4TS U1510 ( .A(n1158), .B(n1156), .Y(n1155) );
NAND2X2TS U1511 ( .A(n1921), .B(n1415), .Y(n1924) );
NAND2X2TS U1512 ( .A(n936), .B(n2331), .Y(n1475) );
NAND2X4TS U1513 ( .A(n1414), .B(n2453), .Y(n1180) );
INVX2TS U1514 ( .A(n936), .Y(n1381) );
INVX8TS U1515 ( .A(n1363), .Y(n1618) );
INVX6TS U1516 ( .A(n1254), .Y(n2419) );
AND2X4TS U1517 ( .A(n986), .B(n2331), .Y(n1809) );
INVX2TS U1518 ( .A(n1605), .Y(n2406) );
NAND2X6TS U1519 ( .A(n970), .B(n1134), .Y(n1700) );
NOR2X4TS U1520 ( .A(n1761), .B(n1240), .Y(n1238) );
CLKMX2X2TS U1521 ( .A(Data_X[27]), .B(intDX_EWSW[27]), .S0(n2519), .Y(n835)
);
CLKMX2X2TS U1522 ( .A(Data_X[28]), .B(intDX_EWSW[28]), .S0(n2519), .Y(n834)
);
NOR2X4TS U1523 ( .A(n1131), .B(n1580), .Y(n1130) );
NAND2X4TS U1524 ( .A(n1941), .B(n1328), .Y(n1603) );
NAND2X1TS U1525 ( .A(n1149), .B(n2299), .Y(n2300) );
INVX2TS U1526 ( .A(n2058), .Y(n1025) );
INVX2TS U1527 ( .A(n1454), .Y(n1578) );
NAND2X1TS U1528 ( .A(n2233), .B(n584), .Y(n2185) );
INVX12TS U1529 ( .A(n1819), .Y(n2500) );
NAND2X1TS U1530 ( .A(n2378), .B(n741), .Y(n2064) );
INVX12TS U1531 ( .A(n975), .Y(n2452) );
NAND2X2TS U1532 ( .A(n2378), .B(n1370), .Y(n2379) );
INVX3TS U1533 ( .A(n1723), .Y(n1126) );
INVX4TS U1534 ( .A(n1389), .Y(n1390) );
INVX4TS U1535 ( .A(n2925), .Y(busy) );
BUFX12TS U1536 ( .A(n2651), .Y(n1429) );
NOR2X4TS U1537 ( .A(n2573), .B(intDX_EWSW[28]), .Y(n1730) );
NAND2X2TS U1538 ( .A(n1868), .B(Raw_mant_NRM_SWR[0]), .Y(n2974) );
NAND2X2TS U1539 ( .A(n1868), .B(n1385), .Y(n3005) );
NAND2X4TS U1540 ( .A(n2989), .B(n2883), .Y(n2954) );
NAND2X4TS U1541 ( .A(n1013), .B(n1167), .Y(n3001) );
OAI21X2TS U1542 ( .A0(n1404), .A1(n1394), .B0(n1635), .Y(n769) );
NAND3X6TS U1543 ( .A(n1835), .B(n1834), .C(n1833), .Y(n2994) );
NAND2X2TS U1544 ( .A(n1164), .B(n1547), .Y(n2936) );
NOR2X6TS U1545 ( .A(n1632), .B(n1168), .Y(n1818) );
NAND2X6TS U1546 ( .A(n1075), .B(n1079), .Y(n1074) );
NAND2X4TS U1547 ( .A(n1502), .B(Raw_mant_NRM_SWR[3]), .Y(n1564) );
OAI2BB1X2TS U1548 ( .A0N(final_result_ieee[30]), .A1N(n2607), .B0(n2370),
.Y(n754) );
INVX2TS U1549 ( .A(n1178), .Y(n3038) );
NAND2X6TS U1550 ( .A(n1194), .B(n1577), .Y(n1522) );
MXI2X4TS U1551 ( .A(n2322), .B(n2667), .S0(n2448), .Y(n467) );
MX2X2TS U1552 ( .A(n2413), .B(Raw_mant_NRM_SWR[14]), .S0(n2886), .Y(n528) );
NAND2X4TS U1553 ( .A(n2374), .B(n972), .Y(n1069) );
INVX2TS U1554 ( .A(n2355), .Y(n1211) );
NAND2X2TS U1555 ( .A(n2472), .B(DmP_mant_SHT1_SW[16]), .Y(n2265) );
MX2X2TS U1556 ( .A(n2398), .B(Raw_mant_NRM_SWR[8]), .S0(n1429), .Y(n534) );
NAND2X6TS U1557 ( .A(n1618), .B(n1063), .Y(n1556) );
NAND2X6TS U1558 ( .A(n1010), .B(n972), .Y(n1009) );
INVX6TS U1559 ( .A(n1553), .Y(n1111) );
NAND2X4TS U1560 ( .A(n2419), .B(n1578), .Y(n1575) );
NAND3X6TS U1561 ( .A(n1553), .B(n1171), .C(n1112), .Y(n1029) );
INVX2TS U1562 ( .A(n1089), .Y(n1088) );
INVX3TS U1563 ( .A(n1469), .Y(n1070) );
NOR2X2TS U1564 ( .A(n1549), .B(n1548), .Y(n1547) );
NAND2X4TS U1565 ( .A(n1090), .B(n976), .Y(n1089) );
OAI22X2TS U1566 ( .A0(n2034), .A1(n2450), .B0(Shift_reg_FLAGS_7_6), .B1(
n2611), .Y(n721) );
NAND2X6TS U1567 ( .A(n989), .B(n981), .Y(n1175) );
CLKMX2X2TS U1568 ( .A(Data_X[29]), .B(intDX_EWSW[29]), .S0(n2519), .Y(n833)
);
CLKMX2X2TS U1569 ( .A(Data_X[12]), .B(intDX_EWSW[12]), .S0(n2517), .Y(n850)
);
CLKMX2X2TS U1570 ( .A(Data_Y[14]), .B(intDY_EWSW[14]), .S0(n2513), .Y(n814)
);
CLKMX2X2TS U1571 ( .A(Data_X[3]), .B(intDX_EWSW[3]), .S0(n2518), .Y(n859) );
NAND2X6TS U1572 ( .A(n1023), .B(n1130), .Y(n2401) );
CLKMX2X2TS U1573 ( .A(Data_X[7]), .B(intDX_EWSW[7]), .S0(n2518), .Y(n855) );
CLKMX2X2TS U1574 ( .A(Data_Y[22]), .B(intDY_EWSW[22]), .S0(n2515), .Y(n806)
);
CLKMX2X2TS U1575 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n2515), .Y(n804)
);
CLKMX2X2TS U1576 ( .A(Data_Y[21]), .B(intDY_EWSW[21]), .S0(n2513), .Y(n807)
);
CLKMX2X2TS U1577 ( .A(Data_Y[23]), .B(intDY_EWSW[23]), .S0(n2515), .Y(n805)
);
CLKMX2X2TS U1578 ( .A(Data_X[22]), .B(intDX_EWSW[22]), .S0(n2519), .Y(n840)
);
NAND2X6TS U1579 ( .A(n1454), .B(n2418), .Y(n2425) );
NAND2X4TS U1580 ( .A(n2486), .B(n1328), .Y(n1586) );
CLKMX2X2TS U1581 ( .A(Data_X[15]), .B(intDX_EWSW[15]), .S0(n2517), .Y(n847)
);
CLKMX2X2TS U1582 ( .A(Data_X[20]), .B(intDX_EWSW[20]), .S0(n2517), .Y(n842)
);
CLKMX2X2TS U1583 ( .A(Data_X[19]), .B(intDX_EWSW[19]), .S0(n2517), .Y(n843)
);
CLKMX2X2TS U1584 ( .A(Data_X[13]), .B(intDX_EWSW[13]), .S0(n2517), .Y(n849)
);
CLKMX2X2TS U1585 ( .A(Data_X[16]), .B(intDX_EWSW[16]), .S0(n2517), .Y(n846)
);
CLKMX2X2TS U1586 ( .A(Data_X[11]), .B(intDX_EWSW[11]), .S0(n2518), .Y(n851)
);
CLKMX2X2TS U1587 ( .A(Data_X[26]), .B(intDX_EWSW[26]), .S0(n2519), .Y(n836)
);
CLKMX2X2TS U1588 ( .A(Data_X[24]), .B(intDX_EWSW[24]), .S0(n2519), .Y(n838)
);
CLKMX2X2TS U1589 ( .A(Data_Y[15]), .B(intDY_EWSW[15]), .S0(n2513), .Y(n813)
);
CLKMX2X2TS U1590 ( .A(Data_Y[12]), .B(intDY_EWSW[12]), .S0(n2513), .Y(n816)
);
CLKMX2X2TS U1591 ( .A(Data_X[1]), .B(n1497), .S0(n2515), .Y(n861) );
INVX2TS U1592 ( .A(n2310), .Y(n1226) );
AND2X4TS U1593 ( .A(n2439), .B(DmP_mant_SHT1_SW[4]), .Y(n2645) );
INVX2TS U1594 ( .A(n1941), .Y(n1861) );
INVX8TS U1595 ( .A(n1002), .Y(n1023) );
NAND2X4TS U1596 ( .A(n987), .B(n973), .Y(n1682) );
NAND2X2TS U1597 ( .A(n932), .B(n962), .Y(n1224) );
NAND2X4TS U1598 ( .A(n2468), .B(n1937), .Y(n1583) );
NAND2X4TS U1599 ( .A(n1519), .B(n2303), .Y(n1012) );
AND2X4TS U1600 ( .A(n988), .B(DmP_mant_SHT1_SW[8]), .Y(n2652) );
NAND2X6TS U1601 ( .A(n1126), .B(n2675), .Y(n1838) );
INVX2TS U1602 ( .A(n976), .Y(n1082) );
NAND2X6TS U1603 ( .A(n1675), .B(n1686), .Y(n1961) );
NAND2X1TS U1604 ( .A(n2224), .B(n576), .Y(n2173) );
INVX12TS U1605 ( .A(n1652), .Y(n2024) );
NAND2X1TS U1606 ( .A(n2224), .B(n568), .Y(n2170) );
NOR2X2TS U1607 ( .A(n2031), .B(n2451), .Y(n2032) );
NAND2X1TS U1608 ( .A(n2224), .B(n574), .Y(n2164) );
INVX2TS U1609 ( .A(n1837), .Y(n1628) );
CLKMX2X3TS U1610 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[28]), .S0(n1543), .Y(
n622) );
NAND3X4TS U1611 ( .A(n1271), .B(n1262), .C(n2717), .Y(n1789) );
NAND2X6TS U1612 ( .A(n1753), .B(n1729), .Y(n1240) );
INVX8TS U1613 ( .A(n2451), .Y(n1589) );
CLKMX2X2TS U1614 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[30]), .S0(n1543), .Y(
n612) );
INVX6TS U1615 ( .A(n533), .Y(n970) );
INVX2TS U1616 ( .A(n1347), .Y(n1704) );
BUFX12TS U1617 ( .A(n1875), .Y(n2922) );
NAND2X1TS U1618 ( .A(n1340), .B(n2292), .Y(n2293) );
NOR3X6TS U1619 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[22]), .C(n898), .Y(n1165) );
BUFX16TS U1620 ( .A(n2206), .Y(n2451) );
OAI22X2TS U1621 ( .A0(n1265), .A1(n2769), .B0(n1257), .B1(n2768), .Y(
final_result_ieee[1]) );
OAI22X2TS U1622 ( .A0(n1275), .A1(n2849), .B0(n1267), .B1(n2848), .Y(
final_result_ieee[17]) );
NAND2X4TS U1623 ( .A(n2593), .B(intDX_EWSW[5]), .Y(n1216) );
OAI22X2TS U1624 ( .A0(n1275), .A1(n2796), .B0(n1267), .B1(n2795), .Y(
final_result_ieee[14]) );
AND2X4TS U1625 ( .A(intDY_EWSW[24]), .B(n1378), .Y(n1728) );
NAND2X2TS U1626 ( .A(n2573), .B(intDX_EWSW[28]), .Y(n1755) );
NAND2X6TS U1627 ( .A(n1376), .B(intDY_EWSW[19]), .Y(n1557) );
BUFX20TS U1628 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1431) );
BUFX20TS U1629 ( .A(left_right_SHT2), .Y(n2358) );
OR2X4TS U1630 ( .A(n1375), .B(DMP_SFG[12]), .Y(n2410) );
INVX8TS U1631 ( .A(n2925), .Y(n2441) );
OAI22X2TS U1632 ( .A0(n1277), .A1(n2861), .B0(n1267), .B1(n2860), .Y(
final_result_ieee[18]) );
NAND2X4TS U1633 ( .A(n1024), .B(n1566), .Y(n795) );
NAND2X4TS U1634 ( .A(n2976), .B(n1124), .Y(n1024) );
NAND3X6TS U1635 ( .A(n996), .B(n1855), .C(n1317), .Y(n3008) );
MX2X2TS U1636 ( .A(n1377), .B(n1310), .S0(n1571), .Y(n513) );
MX2X2TS U1637 ( .A(n2415), .B(LZD_output_NRM2_EW[2]), .S0(n1646), .Y(n514)
);
INVX16TS U1638 ( .A(n1124), .Y(n2884) );
NAND2X4TS U1639 ( .A(n1537), .B(n1536), .Y(n1535) );
NOR2X4TS U1640 ( .A(n1093), .B(n1092), .Y(n1534) );
NAND2X4TS U1641 ( .A(n1145), .B(n1144), .Y(n527) );
NOR2X4TS U1642 ( .A(n1105), .B(n1103), .Y(n1337) );
AND2X4TS U1643 ( .A(n1600), .B(n1832), .Y(n3030) );
NAND4X4TS U1644 ( .A(n2404), .B(n1707), .C(n1708), .D(n1170), .Y(n1709) );
AND2X4TS U1645 ( .A(n1920), .B(n1919), .Y(n2322) );
NAND2X4TS U1646 ( .A(n2324), .B(n2356), .Y(n1181) );
MX2X2TS U1647 ( .A(n2296), .B(Raw_mant_NRM_SWR[12]), .S0(n2886), .Y(n530) );
NAND4X4TS U1648 ( .A(n1018), .B(n1020), .C(n1016), .D(n1942), .Y(n2309) );
NAND2X2TS U1649 ( .A(n1476), .B(n1475), .Y(n1474) );
NAND2X4TS U1650 ( .A(n2365), .B(n1328), .Y(n1244) );
NAND2X4TS U1651 ( .A(n2365), .B(n1430), .Y(n1020) );
MX2X2TS U1652 ( .A(n2253), .B(Raw_mant_NRM_SWR[3]), .S0(n1429), .Y(n539) );
NAND2X4TS U1653 ( .A(n1810), .B(n1465), .Y(n2324) );
INVX12TS U1654 ( .A(n1175), .Y(n1800) );
NAND2X4TS U1655 ( .A(n2325), .B(n989), .Y(n1182) );
NAND2X2TS U1656 ( .A(n1015), .B(n1950), .Y(n1785) );
NAND2X4TS U1657 ( .A(n1922), .B(n2348), .Y(n1229) );
NAND2X4TS U1658 ( .A(n2333), .B(n2348), .Y(n1355) );
CLKINVX6TS U1659 ( .A(n1664), .Y(n1214) );
CLKMX2X2TS U1660 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n2371), .Y(n831)
);
CLKMX2X2TS U1661 ( .A(Data_Y[4]), .B(intDY_EWSW[4]), .S0(n2514), .Y(n824) );
CLKMX2X2TS U1662 ( .A(Data_Y[2]), .B(n889), .S0(n2514), .Y(n826) );
CLKMX2X2TS U1663 ( .A(Data_Y[8]), .B(intDY_EWSW[8]), .S0(n2514), .Y(n820) );
CLKMX2X3TS U1664 ( .A(Data_Y[1]), .B(n1391), .S0(n2371), .Y(n827) );
INVX2TS U1665 ( .A(n1858), .Y(n1053) );
CLKMX2X2TS U1666 ( .A(Data_Y[3]), .B(n1362), .S0(n2514), .Y(n825) );
CLKMX2X2TS U1667 ( .A(Data_Y[0]), .B(intDY_EWSW[0]), .S0(n2371), .Y(n828) );
CLKMX2X2TS U1668 ( .A(Data_Y[31]), .B(intDY_EWSW[31]), .S0(n2371), .Y(n797)
);
CLKMX2X2TS U1669 ( .A(add_subt), .B(intAS), .S0(n2371), .Y(n830) );
AND2X4TS U1670 ( .A(n2423), .B(n1543), .Y(n1542) );
CLKMX2X2TS U1671 ( .A(Data_Y[11]), .B(intDY_EWSW[11]), .S0(n2514), .Y(n817)
);
CLKMX2X2TS U1672 ( .A(Data_Y[10]), .B(intDY_EWSW[10]), .S0(n2514), .Y(n818)
);
INVX2TS U1673 ( .A(n1078), .Y(n1073) );
BUFX12TS U1674 ( .A(n2516), .Y(n2514) );
INVX2TS U1675 ( .A(n2499), .Y(n2344) );
INVX2TS U1676 ( .A(n2338), .Y(n1576) );
AND2X4TS U1677 ( .A(n2439), .B(DmP_mant_SHT1_SW[7]), .Y(n2647) );
BUFX12TS U1678 ( .A(n2516), .Y(n2517) );
BUFX12TS U1679 ( .A(n2516), .Y(n2519) );
BUFX12TS U1680 ( .A(n2516), .Y(n2518) );
BUFX12TS U1681 ( .A(n2516), .Y(n2515) );
CLKMX2X2TS U1682 ( .A(DmP_mant_SHT1_SW[18]), .B(n574), .S0(n2452), .Y(n573)
);
NAND2X4TS U1683 ( .A(n1717), .B(DMP_SFG[17]), .Y(n2426) );
AND2X4TS U1684 ( .A(n2439), .B(DmP_mant_SHT1_SW[3]), .Y(n2646) );
INVX2TS U1685 ( .A(n532), .Y(n1168) );
CLKMX2X2TS U1686 ( .A(DmP_mant_SHT1_SW[17]), .B(n576), .S0(n2452), .Y(n575)
);
NAND2X4TS U1687 ( .A(n1153), .B(n2566), .Y(n1152) );
NAND2X2TS U1688 ( .A(n2378), .B(DMP_EXP_EWSW[13]), .Y(n2065) );
NOR2X4TS U1689 ( .A(n1245), .B(n2760), .Y(n1021) );
INVX2TS U1690 ( .A(n1860), .Y(n1087) );
NAND2X6TS U1691 ( .A(n1827), .B(n1227), .Y(n2310) );
NAND2X2TS U1692 ( .A(n2119), .B(DMP_EXP_EWSW[1]), .Y(n2120) );
INVX4TS U1693 ( .A(n1571), .Y(n1171) );
MXI2X1TS U1694 ( .A(n2492), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X2TS U1695 ( .A(n2233), .B(DmP_EXP_EWSW[27]), .Y(n2210) );
BUFX20TS U1696 ( .A(n2356), .Y(n1415) );
INVX4TS U1697 ( .A(n1719), .Y(n1348) );
INVX2TS U1698 ( .A(n2292), .Y(n2049) );
NOR2X4TS U1699 ( .A(n1349), .B(n2730), .Y(n1673) );
CLKMX2X2TS U1700 ( .A(n2246), .B(DMP_exp_NRM_EW[2]), .S0(n2248), .Y(n636) );
INVX16TS U1701 ( .A(n2922), .Y(n974) );
INVX12TS U1702 ( .A(n2650), .Y(n2431) );
INVX12TS U1703 ( .A(n2650), .Y(n2432) );
NAND2X6TS U1704 ( .A(n1307), .B(n1647), .Y(n1388) );
INVX12TS U1705 ( .A(n2650), .Y(n2433) );
INVX2TS U1706 ( .A(n1429), .Y(n1146) );
NOR2X2TS U1707 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[13]), .Y(
n1676) );
AND2X4TS U1708 ( .A(n2794), .B(n2793), .Y(n1588) );
OAI22X2TS U1709 ( .A0(n1265), .A1(n2714), .B0(n1276), .B1(n2713), .Y(
final_result_ieee[13]) );
OAI22X2TS U1710 ( .A0(n1275), .A1(n2847), .B0(n1257), .B1(n2846), .Y(
final_result_ieee[2]) );
INVX2TS U1711 ( .A(SIGN_FLAG_SHT2), .Y(n2449) );
BUFX16TS U1712 ( .A(Shift_reg_FLAGS_7[1]), .Y(n2248) );
NAND2X2TS U1713 ( .A(n2817), .B(n2816), .Y(n1245) );
NAND2X2TS U1714 ( .A(n2781), .B(n2783), .Y(n1207) );
INVX2TS U1715 ( .A(n1370), .Y(n1371) );
INVX8TS U1716 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1875) );
AND2X4TS U1717 ( .A(n1308), .B(n1309), .Y(n1701) );
AND2X4TS U1718 ( .A(n2831), .B(n2830), .Y(n1333) );
OAI22X2TS U1719 ( .A0(n1277), .A1(n2767), .B0(n1257), .B1(n2766), .Y(
final_result_ieee[0]) );
INVX2TS U1720 ( .A(SIGN_FLAG_SHT1SHT2), .Y(n1911) );
INVX12TS U1721 ( .A(Shift_reg_FLAGS_7_5), .Y(n975) );
OAI22X2TS U1722 ( .A0(n1265), .A1(n2771), .B0(n1267), .B1(n2770), .Y(
final_result_ieee[22]) );
NAND2X2TS U1723 ( .A(n907), .B(n1294), .Y(n2275) );
OAI2BB2X2TS U1724 ( .B0(n1265), .B1(n2788), .A0N(n1264), .A1N(n2787), .Y(
final_result_ieee[10]) );
INVX2TS U1725 ( .A(n1372), .Y(n1373) );
INVX2TS U1726 ( .A(DmP_mant_SHT1_SW[15]), .Y(n2039) );
NOR2X4TS U1727 ( .A(DmP_mant_SFG_SWR_signed[8]), .B(DMP_SFG[6]), .Y(n2393)
);
INVX8TS U1728 ( .A(n1393), .Y(n1394) );
OAI2BB2X2TS U1729 ( .B0(n1277), .B1(n2800), .A0N(n1264), .A1N(n2799), .Y(
final_result_ieee[3]) );
INVX2TS U1730 ( .A(DmP_mant_SHT1_SW[21]), .Y(n2272) );
NAND2X4TS U1731 ( .A(n3008), .B(n1124), .Y(n3012) );
NAND2X4TS U1732 ( .A(n2981), .B(n2883), .Y(n2961) );
NAND2X4TS U1733 ( .A(n1565), .B(n946), .Y(n2950) );
NAND2X4TS U1734 ( .A(n1013), .B(n2883), .Y(n2957) );
NAND2X4TS U1735 ( .A(n1563), .B(n1561), .Y(n770) );
INVX8TS U1736 ( .A(n1298), .Y(n999) );
BUFX20TS U1737 ( .A(n1183), .Y(n977) );
NAND2X6TS U1738 ( .A(n2885), .B(Raw_mant_NRM_SWR[11]), .Y(n2323) );
NAND3X6TS U1739 ( .A(n1337), .B(n1161), .C(n1155), .Y(n2415) );
CLKINVX6TS U1740 ( .A(n2143), .Y(n1637) );
NAND2X6TS U1741 ( .A(n1069), .B(n1070), .Y(n1091) );
BUFX20TS U1742 ( .A(n1006), .Y(n979) );
NAND2X6TS U1743 ( .A(n964), .B(n1570), .Y(n1033) );
MX2X2TS U1744 ( .A(n2302), .B(Raw_mant_NRM_SWR[13]), .S0(n1429), .Y(n529) );
NAND2X4TS U1745 ( .A(n2056), .B(n1543), .Y(n2057) );
NAND2BX2TS U1746 ( .AN(n1576), .B(n1575), .Y(n1574) );
NAND3X6TS U1747 ( .A(n1229), .B(n1828), .C(n1225), .Y(n2317) );
NAND2X6TS U1748 ( .A(n1233), .B(n1871), .Y(n2332) );
MX2X2TS U1749 ( .A(n2257), .B(Raw_mant_NRM_SWR[4]), .S0(n2886), .Y(n538) );
XOR2X2TS U1750 ( .A(n1518), .B(n2408), .Y(n2296) );
MX2X2TS U1751 ( .A(n2482), .B(Raw_mant_NRM_SWR[5]), .S0(n2481), .Y(n537) );
NAND2X4TS U1752 ( .A(n2333), .B(n2334), .Y(n1232) );
NAND4X4TS U1753 ( .A(n1845), .B(n1844), .C(n1843), .D(n1842), .Y(n2313) );
INVX2TS U1754 ( .A(n2401), .Y(n1001) );
XOR2X2TS U1755 ( .A(n2252), .B(n2386), .Y(n2253) );
OR2X4TS U1756 ( .A(n2341), .B(n2457), .Y(n1665) );
NAND2X6TS U1757 ( .A(n1569), .B(n1683), .Y(n1708) );
CLKMX2X2TS U1758 ( .A(Data_X[30]), .B(intDX_EWSW[30]), .S0(n2519), .Y(n832)
);
CLKMX2X2TS U1759 ( .A(Data_Y[18]), .B(n1395), .S0(n2513), .Y(n810) );
NAND2X4TS U1760 ( .A(n1681), .B(n1332), .Y(n1683) );
CLKMX2X2TS U1761 ( .A(Data_Y[16]), .B(intDY_EWSW[16]), .S0(n2513), .Y(n812)
);
INVX8TS U1762 ( .A(n2425), .Y(n980) );
CLKMX2X2TS U1763 ( .A(Data_X[6]), .B(intDX_EWSW[6]), .S0(n2518), .Y(n856) );
CLKMX2X2TS U1764 ( .A(Data_X[0]), .B(intDX_EWSW[0]), .S0(n2515), .Y(n862) );
CLKMX2X2TS U1765 ( .A(Data_X[5]), .B(intDX_EWSW[5]), .S0(n2518), .Y(n857) );
CLKMX2X2TS U1766 ( .A(Data_X[25]), .B(intDX_EWSW[25]), .S0(n2519), .Y(n837)
);
CLKMX2X2TS U1767 ( .A(Data_X[17]), .B(intDX_EWSW[17]), .S0(n2517), .Y(n845)
);
CLKMX2X2TS U1768 ( .A(Data_X[14]), .B(intDX_EWSW[14]), .S0(n2517), .Y(n848)
);
INVX6TS U1769 ( .A(n1790), .Y(n1022) );
CLKMX2X2TS U1770 ( .A(Data_X[10]), .B(intDX_EWSW[10]), .S0(n2518), .Y(n852)
);
CLKMX2X2TS U1771 ( .A(Data_X[18]), .B(intDX_EWSW[18]), .S0(n2517), .Y(n844)
);
NAND2X4TS U1772 ( .A(n955), .B(n1581), .Y(n1761) );
BUFX12TS U1773 ( .A(n2516), .Y(n2513) );
MXI2X2TS U1774 ( .A(n2553), .B(n2674), .S0(n1443), .Y(n702) );
INVX8TS U1775 ( .A(n968), .Y(n1358) );
CLKMX2X3TS U1776 ( .A(DmP_mant_SHT1_SW[21]), .B(n568), .S0(n2452), .Y(n567)
);
CLKINVX12TS U1777 ( .A(n2345), .Y(n981) );
CLKMX2X3TS U1778 ( .A(DmP_mant_SHT1_SW[15]), .B(n1368), .S0(n2452), .Y(n579)
);
MXI2X2TS U1779 ( .A(n2547), .B(n2679), .S0(n2446), .Y(n681) );
CLKMX2X3TS U1780 ( .A(DmP_mant_SHT1_SW[5]), .B(n923), .S0(n2452), .Y(n599)
);
MXI2X2TS U1781 ( .A(n2554), .B(n2631), .S0(n1443), .Y(n705) );
NAND2X6TS U1782 ( .A(n1379), .B(n1380), .Y(n1236) );
INVX12TS U1783 ( .A(n1125), .Y(n1859) );
BUFX6TS U1784 ( .A(n2516), .Y(n2371) );
CLKMX2X3TS U1785 ( .A(DMP_SHT1_EWSW[15]), .B(n1369), .S0(n2437), .Y(n674) );
CLKMX2X3TS U1786 ( .A(DmP_mant_SHT1_SW[7]), .B(n915), .S0(n2432), .Y(n595)
);
CLKMX2X3TS U1787 ( .A(DmP_mant_SHT1_SW[9]), .B(n910), .S0(n2432), .Y(n591)
);
CLKMX2X3TS U1788 ( .A(DmP_mant_SHT1_SW[2]), .B(n1301), .S0(n2432), .Y(n605)
);
CLKMX2X3TS U1789 ( .A(DMP_SHT1_EWSW[17]), .B(DMP_EXP_EWSW[17]), .S0(n2437),
.Y(n668) );
CLKMX2X3TS U1790 ( .A(DMP_SHT1_EWSW[0]), .B(n1249), .S0(n2433), .Y(n719) );
NAND2X8TS U1791 ( .A(n2502), .B(beg_OP), .Y(n2516) );
CLKMX2X3TS U1792 ( .A(DmP_mant_SHT1_SW[19]), .B(n1250), .S0(n2433), .Y(n571)
);
CLKMX2X3TS U1793 ( .A(DMP_SHT1_EWSW[20]), .B(n1357), .S0(n2432), .Y(n659) );
CLKMX2X3TS U1794 ( .A(DMP_SHT1_EWSW[14]), .B(n922), .S0(n2437), .Y(n677) );
CLKMX2X3TS U1795 ( .A(DmP_mant_SHT1_SW[11]), .B(n1297), .S0(n2432), .Y(n587)
);
NAND2X6TS U1796 ( .A(n1782), .B(n1354), .Y(n1950) );
CLKMX2X3TS U1797 ( .A(DMP_SHT1_EWSW[21]), .B(n1300), .S0(n2432), .Y(n656) );
CLKMX2X3TS U1798 ( .A(DMP_SHT1_EWSW[22]), .B(n1366), .S0(n2432), .Y(n653) );
CLKMX2X3TS U1799 ( .A(DMP_SHT1_EWSW[19]), .B(n1303), .S0(n2437), .Y(n662) );
NAND3X4TS U1800 ( .A(n2343), .B(n2775), .C(n2774), .Y(n2499) );
BUFX8TS U1801 ( .A(n2444), .Y(n1443) );
CLKMX2X3TS U1802 ( .A(DMP_SHT1_EWSW[18]), .B(n1367), .S0(n2437), .Y(n665) );
AND2X2TS U1803 ( .A(n1938), .B(n1387), .Y(n1939) );
NAND2X6TS U1804 ( .A(n1619), .B(n2637), .Y(n2427) );
OAI21X1TS U1805 ( .A0(n2287), .A1(n2490), .B0(n2491), .Y(n870) );
CLKMX2X3TS U1806 ( .A(DMP_SHT1_EWSW[16]), .B(DMP_EXP_EWSW[16]), .S0(n2437),
.Y(n671) );
CLKMX2X3TS U1807 ( .A(DmP_mant_SHT1_SW[13]), .B(n584), .S0(n2433), .Y(n583)
);
CLKMX2X3TS U1808 ( .A(DMP_SHT1_EWSW[2]), .B(n902), .S0(n2433), .Y(n713) );
NOR2X2TS U1809 ( .A(n1990), .B(n1989), .Y(n2013) );
CLKMX2X3TS U1810 ( .A(DMP_SHT1_EWSW[30]), .B(n1302), .S0(n2437), .Y(n615) );
CLKMX2X3TS U1811 ( .A(DmP_mant_SHT1_SW[0]), .B(n1296), .S0(n2432), .Y(n609)
);
CLKMX2X3TS U1812 ( .A(DmP_mant_SHT1_SW[16]), .B(n918), .S0(n2433), .Y(n577)
);
CLKMX2X3TS U1813 ( .A(DmP_mant_SHT1_SW[1]), .B(DmP_EXP_EWSW[1]), .S0(n2432),
.Y(n607) );
CLKMX2X3TS U1814 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(n2431), .Y(n551)
);
NAND2BX2TS U1815 ( .AN(n2494), .B(n1727), .Y(n1532) );
CLKMX2X3TS U1816 ( .A(SIGN_FLAG_SHT1), .B(n1299), .S0(n2437), .Y(n548) );
INVX8TS U1817 ( .A(n1652), .Y(n1913) );
CLKMX2X3TS U1818 ( .A(DmP_mant_SHT1_SW[20]), .B(n920), .S0(n2433), .Y(n569)
);
INVX12TS U1819 ( .A(n1388), .Y(n987) );
CLKMX2X2TS U1820 ( .A(DMP_SHT1_EWSW[23]), .B(n1370), .S0(Shift_reg_FLAGS_7_5), .Y(n650) );
CLKMX2X2TS U1821 ( .A(DMP_SHT1_EWSW[27]), .B(DMP_EXP_EWSW[27]), .S0(
Shift_reg_FLAGS_7_5), .Y(n630) );
CLKMX2X2TS U1822 ( .A(DMP_SHT1_EWSW[26]), .B(n1374), .S0(Shift_reg_FLAGS_7_5), .Y(n635) );
NAND2X6TS U1823 ( .A(n1390), .B(n1394), .Y(n1174) );
CLKMX2X2TS U1824 ( .A(DMP_SHT1_EWSW[24]), .B(n1294), .S0(Shift_reg_FLAGS_7_5), .Y(n645) );
INVX8TS U1825 ( .A(n2494), .Y(n1543) );
NAND2X1TS U1826 ( .A(n2494), .B(n2424), .Y(n1344) );
NAND2X2TS U1827 ( .A(n2886), .B(n1306), .Y(n1839) );
INVX4TS U1828 ( .A(n1557), .Y(n1736) );
NAND2X2TS U1829 ( .A(n2286), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n2491) );
NAND2X6TS U1830 ( .A(n1713), .B(DMP_SFG[13]), .Y(n2303) );
INVX2TS U1831 ( .A(n2663), .Y(n1213) );
OAI2BB1X2TS U1832 ( .A0N(n2874), .A1N(n1264), .B0(n1266), .Y(underflow_flag)
);
MXI2X2TS U1833 ( .A(n2644), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n1662) );
NAND3X2TS U1834 ( .A(n1292), .B(n1291), .C(n1290), .Y(n741) );
NOR2X6TS U1835 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2648), .Y(n2490) );
NAND2X6TS U1836 ( .A(n1655), .B(DMP_exp_NRM2_EW[4]), .Y(n2506) );
NAND2X4TS U1837 ( .A(n2838), .B(n2761), .Y(n1585) );
NOR2X2TS U1838 ( .A(n2643), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1661) );
INVX2TS U1839 ( .A(n2529), .Y(n1187) );
NAND2X2TS U1840 ( .A(n2590), .B(intDX_EWSW[29]), .Y(n1754) );
INVX2TS U1841 ( .A(n2521), .Y(n2445) );
INVX4TS U1842 ( .A(n2605), .Y(DmP_mant_SHT1_SW[14]) );
NAND3X8TS U1843 ( .A(n2150), .B(n2151), .C(n2149), .Y(n726) );
NAND2X6TS U1844 ( .A(n977), .B(intDX_EWSW[12]), .Y(n2162) );
NAND2X6TS U1845 ( .A(n977), .B(intDX_EWSW[27]), .Y(n2211) );
BUFX20TS U1846 ( .A(n2223), .Y(n1593) );
NAND2X2TS U1847 ( .A(n2640), .B(DMP_EXP_EWSW[16]), .Y(n2071) );
NAND2X4TS U1848 ( .A(n1593), .B(intDY_EWSW[27]), .Y(n2151) );
NAND3X6TS U1849 ( .A(n2108), .B(n2109), .C(n2107), .Y(n745) );
OAI21X4TS U1850 ( .A0(n1888), .A1(n1889), .B0(n1887), .Y(n1896) );
AND2X8TS U1851 ( .A(n1304), .B(LZD_output_NRM2_EW[0]), .Y(n1888) );
NAND2X8TS U1852 ( .A(n1043), .B(Raw_mant_NRM_SWR[22]), .Y(n1867) );
NOR2X6TS U1853 ( .A(n954), .B(n1184), .Y(n1151) );
NAND3X4TS U1854 ( .A(n2190), .B(n2188), .C(n2189), .Y(n602) );
NAND3X6TS U1855 ( .A(n2066), .B(n2067), .C(n2065), .Y(n740) );
NAND3X6TS U1856 ( .A(n2163), .B(n2162), .C(n2161), .Y(n586) );
NAND3X4TS U1857 ( .A(n2111), .B(n2112), .C(n2110), .Y(n750) );
MXI2X8TS U1858 ( .A(n3036), .B(n938), .S0(n900), .Y(n479) );
OR2X8TS U1859 ( .A(n1582), .B(n1939), .Y(n2349) );
BUFX20TS U1860 ( .A(n2223), .Y(n1418) );
NAND3X8TS U1861 ( .A(n2114), .B(n2115), .C(n2113), .Y(n746) );
INVX16TS U1862 ( .A(n1632), .Y(n1868) );
NAND2X8TS U1863 ( .A(n1166), .B(n1630), .Y(n1632) );
NAND4X8TS U1864 ( .A(n1629), .B(n960), .C(n1104), .D(n1171), .Y(n1048) );
NAND3X8TS U1865 ( .A(n1551), .B(n1550), .C(n1315), .Y(n1568) );
BUFX20TS U1866 ( .A(n1513), .Y(n1398) );
NOR2X8TS U1867 ( .A(n1039), .B(n1702), .Y(n1551) );
INVX12TS U1868 ( .A(n1096), .Y(n2040) );
NAND2X8TS U1869 ( .A(n1056), .B(n994), .Y(n1054) );
NAND3X8TS U1870 ( .A(n1556), .B(n1058), .C(n1725), .Y(n994) );
XOR2X4TS U1871 ( .A(n2921), .B(DmP_mant_SFG_SWR[16]), .Y(n1714) );
AND2X8TS U1872 ( .A(n1708), .B(n1707), .Y(n1032) );
OAI21X4TS U1873 ( .A0(n2884), .A1(n995), .B0(n1185), .Y(n2927) );
NAND2X8TS U1874 ( .A(n2231), .B(intDX_EWSW[7]), .Y(n2114) );
NAND2X6TS U1875 ( .A(n1043), .B(Raw_mant_NRM_SWR[12]), .Y(n1601) );
AOI21X4TS U1876 ( .A0(n1256), .A1(n2721), .B0(n1846), .Y(n1848) );
NAND2X4TS U1877 ( .A(intDX_EWSW[29]), .B(n1398), .Y(n2242) );
CLKINVX12TS U1878 ( .A(n1568), .Y(n2139) );
NAND3BX4TS U1879 ( .AN(n1384), .B(n2242), .C(n2241), .Y(n724) );
NAND2X4TS U1880 ( .A(intDX_EWSW[25]), .B(n1398), .Y(n2043) );
NAND3X4TS U1881 ( .A(n949), .B(n2099), .C(n2098), .Y(n748) );
CLKINVX12TS U1882 ( .A(n1044), .Y(n1114) );
NAND3X6TS U1883 ( .A(n1629), .B(n1104), .C(n960), .Y(n1133) );
NAND2X6TS U1884 ( .A(n1043), .B(Raw_mant_NRM_SWR[17]), .Y(n1496) );
NOR2X8TS U1885 ( .A(n2882), .B(Raw_mant_NRM_SWR[17]), .Y(n1697) );
NAND2X4TS U1886 ( .A(intDX_EWSW[2]), .B(n885), .Y(n2105) );
OAI2BB1X4TS U1887 ( .A0N(n1271), .A1N(n2737), .B0(n1270), .Y(n1269) );
NAND4X2TS U1888 ( .A(n1976), .B(n1975), .C(n1974), .D(n1973), .Y(n1980) );
NOR4X4TS U1889 ( .A(n1980), .B(n1979), .C(n1978), .D(n1977), .Y(n2014) );
AOI22X4TS U1890 ( .A0(n1972), .A1(n1434), .B0(n936), .B1(n2270), .Y(n3059)
);
MXI2X4TS U1891 ( .A(n3059), .B(n2658), .S0(n2448), .Y(n466) );
NAND3X6TS U1892 ( .A(n1592), .B(n1590), .C(n1591), .Y(n1514) );
NAND2X4TS U1893 ( .A(n1495), .B(intDY_EWSW[9]), .Y(n2094) );
INVX12TS U1894 ( .A(n2298), .Y(n1149) );
OAI21X4TS U1895 ( .A0(n2261), .A1(n2258), .B0(n2262), .Y(n2046) );
NAND2X8TS U1896 ( .A(n2231), .B(intDY_EWSW[27]), .Y(n2212) );
OR3X8TS U1897 ( .A(n1448), .B(n1447), .C(n1531), .Y(n1446) );
NOR2X8TS U1898 ( .A(n1933), .B(DMP_SFG[4]), .Y(n2259) );
NAND3X6TS U1899 ( .A(n997), .B(n1235), .C(n1239), .Y(n1123) );
NAND2X6TS U1900 ( .A(n1511), .B(n1508), .Y(n997) );
NOR2X4TS U1901 ( .A(n2571), .B(intDX_EWSW[22]), .Y(n1740) );
NAND3X8TS U1902 ( .A(n999), .B(n2235), .C(n2234), .Y(n596) );
OAI21X2TS U1903 ( .A0(n2598), .A1(n1411), .B0(n2268), .Y(n2948) );
OAI21X2TS U1904 ( .A0(n2627), .A1(n1411), .B0(n2269), .Y(n2934) );
NOR2X4TS U1905 ( .A(n1014), .B(n2340), .Y(n2347) );
NAND3X8TS U1906 ( .A(n1045), .B(n1624), .C(n1703), .Y(n1104) );
AND2X8TS U1907 ( .A(n532), .B(n1043), .Y(n2980) );
OR2X8TS U1908 ( .A(n2145), .B(n1709), .Y(n2493) );
NOR2X8TS U1909 ( .A(n1961), .B(n1002), .Y(n1640) );
NAND3X8TS U1910 ( .A(n1154), .B(n1150), .C(n1165), .Y(n1002) );
INVX16TS U1911 ( .A(n1004), .Y(n1189) );
NAND2X8TS U1912 ( .A(n1456), .B(n1114), .Y(n1004) );
NOR2X8TS U1913 ( .A(n1097), .B(n982), .Y(n2041) );
NAND2X8TS U1914 ( .A(n1005), .B(n1222), .Y(n533) );
NAND2X8TS U1915 ( .A(n1027), .B(n2825), .Y(n1005) );
NAND2X8TS U1916 ( .A(n987), .B(n959), .Y(n1552) );
NOR2X8TS U1917 ( .A(n1650), .B(n898), .Y(n2400) );
NAND2X8TS U1918 ( .A(n1011), .B(n1012), .Y(n1102) );
NOR2X8TS U1919 ( .A(n2372), .B(n1724), .Y(n1010) );
NAND3X8TS U1920 ( .A(n1136), .B(n1520), .C(n1221), .Y(n1011) );
NAND2X2TS U1921 ( .A(n2024), .B(n1387), .Y(n1797) );
OR2X8TS U1922 ( .A(n1666), .B(n2348), .Y(n1652) );
BUFX20TS U1923 ( .A(n2103), .Y(n2222) );
NAND2X6TS U1924 ( .A(n2222), .B(n1391), .Y(n2230) );
NAND2X4TS U1925 ( .A(intDX_EWSW[16]), .B(n1513), .Y(n2072) );
NAND2X8TS U1926 ( .A(n1968), .B(n1967), .Y(n1013) );
NAND2X8TS U1927 ( .A(n2569), .B(n1937), .Y(n2341) );
OR2X8TS U1928 ( .A(n1359), .B(n1017), .Y(n2460) );
NOR2BX4TS U1929 ( .AN(n950), .B(n2725), .Y(n1017) );
NAND2X8TS U1930 ( .A(n1019), .B(n1268), .Y(n2023) );
NOR2X8TS U1931 ( .A(n1228), .B(n945), .Y(n1019) );
NAND2X8TS U1932 ( .A(n1022), .B(n1021), .Y(n2365) );
NAND2X6TS U1933 ( .A(n1188), .B(n1023), .Y(n1707) );
NAND2X6TS U1934 ( .A(n2823), .B(n2824), .Y(n1222) );
CLKINVX12TS U1935 ( .A(n2823), .Y(n1027) );
NOR2X8TS U1936 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1154) );
NAND2X8TS U1937 ( .A(n1049), .B(n1028), .Y(n1629) );
NOR2X8TS U1938 ( .A(n1172), .B(n1696), .Y(n1028) );
NOR2X8TS U1939 ( .A(n1030), .B(n1029), .Y(n1031) );
NAND2X8TS U1940 ( .A(n1166), .B(n1822), .Y(n1124) );
NAND4X8TS U1941 ( .A(n1033), .B(n1032), .C(n1031), .D(n891), .Y(n1166) );
NOR2X8TS U1942 ( .A(n1036), .B(n1034), .Y(n1689) );
NAND4X8TS U1943 ( .A(n2138), .B(n1551), .C(n1550), .D(n1037), .Y(n1047) );
NOR2X8TS U1944 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[12]), .Y(
n1687) );
NAND3X8TS U1945 ( .A(n1680), .B(n1693), .C(n1634), .Y(n1039) );
NAND2X8TS U1946 ( .A(n1218), .B(n1959), .Y(n1702) );
NOR2X8TS U1947 ( .A(n1692), .B(Raw_mant_NRM_SWR[7]), .Y(n2138) );
NAND2X8TS U1948 ( .A(n961), .B(n1040), .Y(n1692) );
NOR2X8TS U1949 ( .A(n990), .B(n1041), .Y(n1040) );
BUFX20TS U1950 ( .A(n1114), .Y(n1043) );
NAND2X8TS U1951 ( .A(n1043), .B(Raw_mant_NRM_SWR[8]), .Y(n1639) );
OAI21X4TS U1952 ( .A0(n1133), .A1(n1817), .B0(n1431), .Y(n1044) );
AND2X8TS U1953 ( .A(n1716), .B(DMP_SFG[16]), .Y(n1097) );
NOR2X8TS U1954 ( .A(n2136), .B(n1690), .Y(n1703) );
NOR3X8TS U1955 ( .A(n1172), .B(n1324), .C(n1695), .Y(n1045) );
NAND4X8TS U1956 ( .A(n1046), .B(n2401), .C(n1553), .D(n1047), .Y(n1817) );
NOR2X8TS U1957 ( .A(n1048), .B(n1817), .Y(n2501) );
OAI21X4TS U1958 ( .A0(n1700), .A1(n1699), .B0(n1698), .Y(n1049) );
NAND2X8TS U1959 ( .A(n1116), .B(n1118), .Y(n1553) );
NAND3X8TS U1960 ( .A(n979), .B(n1453), .C(n1460), .Y(n1050) );
AOI21X4TS U1961 ( .A0(n1460), .A1(n2374), .B0(n1053), .Y(n1051) );
XOR2X4TS U1962 ( .A(n1052), .B(n1659), .Y(n1840) );
INVX12TS U1963 ( .A(n2040), .Y(n1060) );
INVX6TS U1964 ( .A(n1055), .Y(n1056) );
AOI21X4TS U1965 ( .A0(n1545), .A1(n2422), .B0(n1721), .Y(n1856) );
NOR2X8TS U1966 ( .A(n1127), .B(n2372), .Y(n1447) );
OAI21X4TS U1967 ( .A0(n1856), .A1(n1724), .B0(n1057), .Y(n1055) );
AOI21X4TS U1968 ( .A0(n1836), .A1(n1838), .B0(n1628), .Y(n1057) );
NAND2X8TS U1969 ( .A(n1859), .B(n1838), .Y(n1724) );
CLKXOR2X4TS U1970 ( .A(DmP_mant_SFG_SWR[15]), .B(n2920), .Y(n1713) );
NAND2X8TS U1971 ( .A(n1194), .B(n1064), .Y(n1079) );
NOR2X4TS U1972 ( .A(n1061), .B(n1065), .Y(n1064) );
OAI21X4TS U1973 ( .A0(n1067), .A1(n1429), .B0(n1501), .Y(n523) );
XOR2X4TS U1974 ( .A(n1068), .B(n1345), .Y(n1067) );
OAI21X4TS U1975 ( .A0(n1072), .A1(n944), .B0(n1101), .Y(n1068) );
NAND2X8TS U1976 ( .A(n1071), .B(n1618), .Y(n2374) );
AOI21X4TS U1977 ( .A0(n2374), .A1(n2375), .B0(n1545), .Y(n1544) );
NOR2X8TS U1978 ( .A(n1857), .B(n1724), .Y(n1725) );
OR2X8TS U1979 ( .A(n1079), .B(n1077), .Y(n1076) );
NOR2X4TS U1980 ( .A(n1726), .B(DMP_SFG[22]), .Y(n2372) );
AOI21X4TS U1981 ( .A0(n1091), .A1(n1088), .B0(n1087), .Y(n1086) );
AOI21X4TS U1982 ( .A0(n1447), .A1(n1530), .B0(n1341), .Y(n1445) );
AOI21X2TS U1983 ( .A0(n1098), .A1(n2040), .B0(n1097), .Y(n1101) );
NOR2X8TS U1984 ( .A(n1620), .B(n1621), .Y(n1096) );
OAI21X4TS U1985 ( .A0(n1099), .A1(n2886), .B0(n1622), .Y(n522) );
XNOR2X4TS U1986 ( .A(n1100), .B(n2376), .Y(n1099) );
OAI21X4TS U1987 ( .A0(n1072), .A1(n1061), .B0(n1128), .Y(n1100) );
NOR2X8TS U1988 ( .A(Raw_mant_NRM_SWR[22]), .B(n1650), .Y(n1218) );
NAND3X8TS U1989 ( .A(n987), .B(n1680), .C(n532), .Y(n1117) );
NAND2X8TS U1990 ( .A(n1471), .B(n1473), .Y(n532) );
NAND2X8TS U1991 ( .A(n2827), .B(n2828), .Y(n1473) );
NAND2X8TS U1992 ( .A(n953), .B(n2829), .Y(n1471) );
NOR2X8TS U1993 ( .A(n898), .B(Raw_mant_NRM_SWR[17]), .Y(n1680) );
CLKINVX2TS U1994 ( .A(n1104), .Y(n1103) );
BUFX20TS U1995 ( .A(n1643), .Y(n1108) );
NOR2X8TS U1996 ( .A(n1111), .B(n1110), .Y(n2404) );
AND2X8TS U1997 ( .A(n1400), .B(intDY_EWSW[7]), .Y(n1768) );
NAND2X8TS U1998 ( .A(n2426), .B(n1115), .Y(n1363) );
NOR2X8TS U1999 ( .A(n1117), .B(n1567), .Y(n1116) );
INVX16TS U2000 ( .A(n1119), .Y(n2223) );
NAND4X8TS U2001 ( .A(n1592), .B(n1589), .C(n1590), .D(n1591), .Y(n1119) );
OAI21X4TS U2002 ( .A0(n1191), .A1(n1241), .B0(n1751), .Y(n1120) );
NOR2X8TS U2003 ( .A(n1121), .B(n1192), .Y(n1590) );
OAI21X4TS U2004 ( .A0(n1193), .A1(n1242), .B0(n1757), .Y(n1121) );
NAND2X8TS U2005 ( .A(n1123), .B(n1122), .Y(n1592) );
OAI21X4TS U2006 ( .A0(n2980), .A1(n1966), .B0(n1124), .Y(n2983) );
XOR2X4TS U2007 ( .A(DmP_mant_SFG_SWR[23]), .B(n2920), .Y(n1723) );
NOR2X6TS U2008 ( .A(DMP_SFG[20]), .B(n1722), .Y(n1125) );
XOR2X4TS U2009 ( .A(n1503), .B(DmP_mant_SFG_SWR[22]), .Y(n1722) );
NOR2X8TS U2010 ( .A(n1552), .B(n1172), .Y(n1129) );
BUFX12TS U2011 ( .A(n1114), .Y(n1135) );
NAND3X1TS U2012 ( .A(n1520), .B(n1136), .C(n2409), .Y(n1148) );
NAND2X8TS U2013 ( .A(n1605), .B(n2410), .Y(n1136) );
OAI21X4TS U2014 ( .A0(n1138), .A1(n1429), .B0(n1137), .Y(n535) );
XOR2X4TS U2015 ( .A(n1139), .B(n2264), .Y(n1138) );
OAI21X4TS U2016 ( .A0(n2260), .A1(n2259), .B0(n2258), .Y(n1139) );
AOI21X4TS U2017 ( .A0(n2254), .A1(n1143), .B0(n2048), .Y(n2260) );
OAI21X2TS U2018 ( .A0(n1141), .A1(n2886), .B0(n1140), .Y(n536) );
XOR2X2TS U2019 ( .A(n2260), .B(n1142), .Y(n1141) );
OAI21X4TS U2020 ( .A0(n2249), .A1(n2386), .B0(n2250), .Y(n2254) );
NAND2X8TS U2021 ( .A(n1149), .B(n1515), .Y(n1529) );
NAND2X4TS U2022 ( .A(n1625), .B(n1651), .Y(n1153) );
NAND2X2TS U2023 ( .A(n1868), .B(Raw_mant_NRM_SWR[3]), .Y(n2956) );
NOR2X8TS U2024 ( .A(n2137), .B(n2399), .Y(n2403) );
NAND4X8TS U2025 ( .A(n1160), .B(n1550), .C(n1159), .D(n963), .Y(n2399) );
NOR2X8TS U2026 ( .A(n2136), .B(n1690), .Y(n1160) );
NAND2X8TS U2027 ( .A(n1173), .B(n1496), .Y(n3003) );
AND2X8TS U2028 ( .A(n1945), .B(n1946), .Y(n1173) );
NAND2X8TS U2029 ( .A(n2569), .B(n1328), .Y(n2345) );
NOR2X8TS U2030 ( .A(n1177), .B(n1176), .Y(n478) );
NOR2X8TS U2031 ( .A(n1178), .B(n900), .Y(n1177) );
BUFX20TS U2032 ( .A(n2223), .Y(n1183) );
NAND2X8TS U2033 ( .A(n1823), .B(n2439), .Y(n2497) );
AOI21X4TS U2034 ( .A0(n1738), .A1(n955), .B0(n1737), .Y(n1191) );
AOI21X4TS U2035 ( .A0(n1202), .A1(n1753), .B0(n1196), .Y(n1193) );
OAI22X4TS U2036 ( .A0(n1201), .A1(n1199), .B0(n1198), .B1(n1197), .Y(n1196)
);
NOR2X8TS U2037 ( .A(n1201), .B(n1200), .Y(n1753) );
NOR2X8TS U2038 ( .A(n2576), .B(intDX_EWSW[27]), .Y(n1201) );
OAI22X4TS U2039 ( .A0(n1752), .A1(n1204), .B0(n1203), .B1(n952), .Y(n1202)
);
OAI2BB1X4TS U2040 ( .A0N(n2739), .A1N(n1271), .B0(n1205), .Y(n2335) );
NOR2BX4TS U2041 ( .AN(n1206), .B(n2738), .Y(n1205) );
NOR2BX4TS U2042 ( .AN(n2782), .B(n1207), .Y(n1206) );
INVX12TS U2043 ( .A(n1272), .Y(n1271) );
AOI2BB2X4TS U2044 ( .B0(n1928), .B1(n1415), .A0N(n985), .A1N(n1211), .Y(
n3025) );
NAND2X8TS U2045 ( .A(n1665), .B(n1208), .Y(n1928) );
NOR2X8TS U2046 ( .A(n1210), .B(n1209), .Y(n1208) );
NAND2X6TS U2047 ( .A(n947), .B(n1671), .Y(n1210) );
OAI21X4TS U2048 ( .A0(n3025), .A1(n933), .B0(n1212), .Y(n486) );
OAI21X4TS U2049 ( .A0(n1766), .A1(n1217), .B0(n1216), .Y(n1483) );
AND2X8TS U2050 ( .A(n1312), .B(intDY_EWSW[5]), .Y(n1766) );
AOI21X4TS U2051 ( .A0(n1219), .A1(n2529), .B0(n1702), .Y(n1624) );
NOR2X8TS U2052 ( .A(Raw_mant_NRM_SWR[11]), .B(Raw_mant_NRM_SWR[13]), .Y(
n1959) );
NAND2BX4TS U2053 ( .AN(Raw_mant_NRM_SWR[3]), .B(n1220), .Y(n1219) );
OAI21X4TS U2054 ( .A0(n2531), .A1(Raw_mant_NRM_SWR[1]), .B0(n2694), .Y(n1220) );
AND2X8TS U2055 ( .A(n2303), .B(n2409), .Y(n1221) );
OAI21X4TS U2056 ( .A0(n1600), .A1(n934), .B0(n1223), .Y(n483) );
OA21X4TS U2057 ( .A0(n1832), .A1(n932), .B0(n1224), .Y(n1223) );
AOI2BB2X4TS U2058 ( .B0(n2023), .B1(n1430), .A0N(n1014), .A1N(n1226), .Y(
n1225) );
NAND3BX4TS U2059 ( .AN(n2758), .B(n2836), .C(n2835), .Y(n1228) );
AOI21X4TS U2060 ( .A0(n2332), .A1(n1434), .B0(n1230), .Y(n3055) );
OAI2BB1X4TS U2061 ( .A0N(n1328), .A1N(n2454), .B0(n1356), .Y(n2333) );
NOR2BX4TS U2062 ( .AN(n1870), .B(n1234), .Y(n1233) );
AOI21X4TS U2063 ( .A0(n1507), .A1(n1559), .B0(n1558), .Y(n1239) );
XOR2X4TS U2064 ( .A(n480), .B(n2377), .Y(n2798) );
MXI2X8TS U2065 ( .A(n3034), .B(n940), .S0(n900), .Y(n480) );
AOI22X4TS U2066 ( .A0(n2314), .A1(n2330), .B0(n1414), .B1(n2462), .Y(n1849)
);
NAND2X8TS U2067 ( .A(n1246), .B(n1244), .Y(n2314) );
AOI21X4TS U2068 ( .A0(n1941), .A1(n1937), .B0(n1247), .Y(n1246) );
NOR2BX4TS U2069 ( .AN(n1938), .B(n1358), .Y(n1247) );
NAND2X2TS U2070 ( .A(n1361), .B(intDX_EWSW[21]), .Y(n2090) );
NAND3X2TS U2071 ( .A(n2220), .B(n2221), .C(n2219), .Y(n606) );
NAND3X2TS U2072 ( .A(n2381), .B(n2380), .C(n2379), .Y(n730) );
NAND3X2TS U2073 ( .A(n1780), .B(n1779), .C(n1778), .Y(n727) );
NAND2X2TS U2074 ( .A(n1006), .B(n1546), .Y(n1536) );
NAND3X2TS U2075 ( .A(n979), .B(n1546), .C(n1542), .Y(n1541) );
NAND2X6TS U2076 ( .A(n1449), .B(n2373), .Y(n1448) );
NAND3X4TS U2077 ( .A(n1334), .B(n1626), .C(n1609), .Y(n524) );
NAND3X4TS U2078 ( .A(n2088), .B(n2087), .C(n2086), .Y(n731) );
NAND2X2TS U2079 ( .A(n2222), .B(n889), .Y(n2221) );
NAND4X4TS U2080 ( .A(n1917), .B(n1916), .C(n1915), .D(n1914), .Y(n1921) );
AOI22X4TS U2081 ( .A0(n936), .A1(n2310), .B0(n2330), .B1(n2349), .Y(n1944)
);
BUFX16TS U2082 ( .A(n2103), .Y(n2231) );
INVX2TS U2083 ( .A(n1252), .Y(n1253) );
NAND3X4TS U2084 ( .A(n2215), .B(n2214), .C(n2213), .Y(n570) );
XNOR2X4TS U2085 ( .A(n984), .B(n479), .Y(n2818) );
AND2X4TS U2086 ( .A(n2417), .B(n2418), .Y(n1254) );
NAND2X4TS U2087 ( .A(n884), .B(intDX_EWSW[14]), .Y(n2075) );
NAND2X4TS U2088 ( .A(n884), .B(n1362), .Y(n2218) );
NAND2X4TS U2089 ( .A(n884), .B(intDY_EWSW[14]), .Y(n2199) );
NAND2X2TS U2090 ( .A(n1398), .B(intDX_EWSW[12]), .Y(n1596) );
NAND2X2TS U2091 ( .A(n1398), .B(intDY_EWSW[13]), .Y(n2187) );
NAND2X4TS U2092 ( .A(n1612), .B(n1336), .Y(n1611) );
NAND2X4TS U2093 ( .A(n2743), .B(n2342), .Y(n1667) );
NAND3X6TS U2094 ( .A(n1271), .B(n1262), .C(n2729), .Y(n1795) );
AOI21X4TS U2095 ( .A0(n1271), .A1(n2736), .B0(n2735), .Y(n1663) );
CLKINVX12TS U2096 ( .A(n1274), .Y(n1272) );
OR3X6TS U2097 ( .A(n1272), .B(n1261), .C(n1273), .Y(n1796) );
OAI22X1TS U2098 ( .A0(n1277), .A1(n2863), .B0(n1276), .B1(n2862), .Y(
final_result_ieee[12]) );
OAI22X1TS U2099 ( .A0(n1277), .A1(n2856), .B0(n1276), .B1(n2855), .Y(
final_result_ieee[6]) );
OAI22X1TS U2100 ( .A0(n1275), .A1(n2851), .B0(n1276), .B1(n2850), .Y(
final_result_ieee[20]) );
OAI22X1TS U2101 ( .A0(n1275), .A1(n2821), .B0(n1276), .B1(n2820), .Y(
final_result_ieee[8]) );
OAI22X1TS U2102 ( .A0(n1275), .A1(n2815), .B0(n1276), .B1(n2814), .Y(
final_result_ieee[11]) );
OAI22X1TS U2103 ( .A0(n1275), .A1(n2810), .B0(n1276), .B1(n2809), .Y(
final_result_ieee[5]) );
OAI22X1TS U2104 ( .A0(n1277), .A1(n2779), .B0(n1276), .B1(n2778), .Y(
final_result_ieee[9]) );
OAI22X1TS U2105 ( .A0(n1275), .A1(n2710), .B0(n1276), .B1(n2709), .Y(
final_result_ieee[7]) );
OAI22X1TS U2106 ( .A0(n1277), .A1(n2865), .B0(n1267), .B1(n2864), .Y(
final_result_ieee[15]) );
OAI22X1TS U2107 ( .A0(n1277), .A1(n2707), .B0(n1267), .B1(n2706), .Y(
final_result_ieee[16]) );
OAI22X1TS U2108 ( .A0(n1277), .A1(n2790), .B0(n1267), .B1(n2789), .Y(
final_result_ieee[21]) );
XOR2X4TS U2109 ( .A(n2920), .B(DmP_mant_SFG_SWR[13]), .Y(n1712) );
NAND2X4TS U2110 ( .A(n1712), .B(DMP_SFG[11]), .Y(n2299) );
NOR2X8TS U2111 ( .A(n1712), .B(DMP_SFG[11]), .Y(n2298) );
XOR2X4TS U2112 ( .A(n2156), .B(n2155), .Y(n2157) );
NAND2X4TS U2113 ( .A(n885), .B(intDX_EWSW[11]), .Y(n2101) );
NAND2X4TS U2114 ( .A(n1513), .B(intDX_EWSW[17]), .Y(n2081) );
NAND2X4TS U2115 ( .A(intDY_EWSW[9]), .B(n885), .Y(n2205) );
MXI2X2TS U2116 ( .A(n2361), .B(final_result_ieee[24]), .S0(n2922), .Y(n2362)
);
NAND2X4TS U2117 ( .A(n1512), .B(intDY_EWSW[4]), .Y(n2190) );
NAND2X4TS U2118 ( .A(n1512), .B(intDY_EWSW[5]), .Y(n2178) );
NAND2X4TS U2119 ( .A(n1512), .B(intDX_EWSW[6]), .Y(n2062) );
NAND2X2TS U2120 ( .A(n1418), .B(intDY_EWSW[10]), .Y(n2097) );
NAND3X4TS U2121 ( .A(n2125), .B(n2124), .C(n2123), .Y(n563) );
NAND3X4TS U2122 ( .A(n2105), .B(n2106), .C(n2104), .Y(n751) );
NAND3X6TS U2123 ( .A(n2093), .B(n2094), .C(n2092), .Y(n744) );
NOR2X4TS U2124 ( .A(n1440), .B(n1441), .Y(n1493) );
NAND3X4TS U2125 ( .A(n2218), .B(n2217), .C(n2216), .Y(n604) );
NAND3X4TS U2126 ( .A(n2131), .B(n2130), .C(n2129), .Y(n561) );
NAND3X4TS U2127 ( .A(n2178), .B(n2177), .C(n2176), .Y(n600) );
NAND3X4TS U2128 ( .A(n2184), .B(n2183), .C(n2182), .Y(n578) );
NAND3X4TS U2129 ( .A(n2199), .B(n2198), .C(n2197), .Y(n582) );
NAND2X2TS U2130 ( .A(n1418), .B(n1362), .Y(n2112) );
NAND3BX4TS U2131 ( .AN(n966), .B(n1926), .C(n1925), .Y(n729) );
NAND3X4TS U2132 ( .A(n2096), .B(n2097), .C(n2095), .Y(n743) );
NAND3X4TS U2133 ( .A(n2205), .B(n2204), .C(n2203), .Y(n592) );
NAND3X4TS U2134 ( .A(n2169), .B(n2168), .C(n2167), .Y(n590) );
NAND3X4TS U2135 ( .A(n2081), .B(n2082), .C(n2080), .Y(n736) );
NAND3X4TS U2136 ( .A(n2101), .B(n2102), .C(n2100), .Y(n742) );
NAND2X4TS U2137 ( .A(intDX_EWSW[13]), .B(n1513), .Y(n2066) );
NAND2X4TS U2138 ( .A(intDY_EWSW[12]), .B(n1480), .Y(n2163) );
NOR2X4TS U2139 ( .A(n2583), .B(intDX_EWSW[12]), .Y(n1451) );
INVX2TS U2140 ( .A(n1385), .Y(n1386) );
NAND2X4TS U2141 ( .A(n2589), .B(intDX_EWSW[6]), .Y(n1572) );
NOR2X4TS U2142 ( .A(n2588), .B(intDX_EWSW[10]), .Y(n1599) );
NOR2X4TS U2143 ( .A(n2572), .B(intDX_EWSW[14]), .Y(n1452) );
NAND2X2TS U2144 ( .A(n1660), .B(n1693), .Y(n1580) );
NAND2X4TS U2145 ( .A(n1678), .B(n1677), .Y(n1567) );
CLKINVX6TS U2146 ( .A(n2304), .Y(n1519) );
NAND2X2TS U2147 ( .A(n986), .B(n2455), .Y(n1815) );
NAND2X4TS U2148 ( .A(n1586), .B(n1583), .Y(n1582) );
NAND2X6TS U2149 ( .A(n1330), .B(n1785), .Y(n2328) );
NAND2X2TS U2150 ( .A(n2455), .B(n2350), .Y(n1477) );
NOR2X4TS U2151 ( .A(n2590), .B(intDX_EWSW[29]), .Y(n1756) );
NAND2X2TS U2152 ( .A(n2583), .B(intDX_EWSW[12]), .Y(n1442) );
NOR2X2TS U2153 ( .A(n2594), .B(intDX_EWSW[20]), .Y(n1739) );
INVX8TS U2154 ( .A(n2041), .Y(n1617) );
NAND2X2TS U2155 ( .A(n2024), .B(n2454), .Y(n1478) );
INVX6TS U2156 ( .A(n1413), .Y(n1402) );
INVX4TS U2157 ( .A(n2520), .Y(n2416) );
AOI22X2TS U2158 ( .A0(n2024), .A1(n2270), .B0(n2350), .B1(n1869), .Y(n1465)
);
AND2X4TS U2159 ( .A(n2845), .B(n2844), .Y(n1464) );
AND2X4TS U2160 ( .A(n2843), .B(n2791), .Y(n1463) );
INVX8TS U2161 ( .A(n1648), .Y(n2472) );
OAI21X2TS U2162 ( .A0(n1517), .A1(n2481), .B0(n1516), .Y(n526) );
NAND2X2TS U2163 ( .A(n2461), .B(n1387), .Y(n1566) );
NAND2X2TS U2164 ( .A(n2233), .B(n903), .Y(n2129) );
NAND2X4TS U2165 ( .A(n2597), .B(intDX_EWSW[0]), .Y(n1491) );
NOR3X4TS U2166 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[20]), .C(
n1385), .Y(n1678) );
NAND2X2TS U2167 ( .A(n2579), .B(intDX_EWSW[17]), .Y(n1732) );
OAI21X2TS U2168 ( .A0(n1756), .A1(n1755), .B0(n1754), .Y(n1759) );
NAND2X4TS U2169 ( .A(n2826), .B(n1473), .Y(n1470) );
NOR2X2TS U2170 ( .A(n2527), .B(Raw_mant_NRM_SWR[21]), .Y(n1694) );
NAND3X6TS U2171 ( .A(n2289), .B(n1525), .C(n1340), .Y(n1528) );
INVX4TS U2172 ( .A(n1887), .Y(n1499) );
NOR2X4TS U2173 ( .A(n1888), .B(n1889), .Y(n1500) );
NOR2X4TS U2174 ( .A(n2345), .B(n2456), .Y(n1664) );
NAND2X2TS U2175 ( .A(n1950), .B(n2350), .Y(n1353) );
NOR2X2TS U2176 ( .A(n2419), .B(n1578), .Y(n1577) );
INVX2TS U2177 ( .A(n1515), .Y(n1623) );
NOR2X2TS U2178 ( .A(n2423), .B(n2494), .Y(n1539) );
NAND2X2TS U2179 ( .A(n1927), .B(n1937), .Y(n1356) );
NAND2X4TS U2180 ( .A(n2759), .B(n2342), .Y(n2343) );
CLKINVX3TS U2181 ( .A(n3068), .Y(n1426) );
NAND2X2TS U2182 ( .A(n2033), .B(n2032), .Y(n2450) );
NAND3X4TS U2183 ( .A(n2202), .B(n2201), .C(n2200), .Y(n580) );
NAND2X2TS U2184 ( .A(n2387), .B(n2386), .Y(n2388) );
MXI2X1TS U2185 ( .A(n2532), .B(n2481), .S0(n2503), .Y(n865) );
INVX2TS U2186 ( .A(n1808), .Y(n2459) );
NAND2X4TS U2187 ( .A(n1316), .B(n1565), .Y(n2946) );
AOI21X2TS U2188 ( .A0(n2414), .A1(n1646), .B0(n1562), .Y(n1561) );
MX2X1TS U2189 ( .A(Data_X[8]), .B(intDX_EWSW[8]), .S0(n2518), .Y(n854) );
NAND2X2TS U2190 ( .A(n2886), .B(Raw_mant_NRM_SWR[19]), .Y(n1501) );
MXI2X1TS U2191 ( .A(n2550), .B(n2880), .S0(n1443), .Y(n690) );
AND2X2TS U2192 ( .A(n1646), .B(LZD_output_NRM2_EW[0]), .Y(n1606) );
NAND2X4TS U2193 ( .A(n1000), .B(Raw_mant_NRM_SWR[1]), .Y(n1504) );
INVX2TS U2194 ( .A(n2468), .Y(n2469) );
NAND3X2TS U2195 ( .A(n1167), .B(n988), .C(DmP_mant_SHT1_SW[12]), .Y(n2985)
);
INVX2TS U2196 ( .A(n2305), .Y(n1549) );
MXI2X1TS U2197 ( .A(n2512), .B(final_result_ieee[27]), .S0(n2607), .Y(n3064)
);
NAND2X2TS U2198 ( .A(n2329), .B(n2330), .Y(n1476) );
MXI2X2TS U2199 ( .A(n2357), .B(n2660), .S0(n900), .Y(n488) );
CLKINVX3TS U2200 ( .A(n1426), .Y(n1417) );
AOI2BB2X2TS U2201 ( .B0(n2489), .B1(DmP_mant_SHT1_SW[7]), .A0N(n2497), .A1N(
n2628), .Y(n1947) );
INVX2TS U2202 ( .A(n2486), .Y(n2487) );
NAND2X2TS U2203 ( .A(n1346), .B(Raw_mant_NRM_SWR[13]), .Y(n2939) );
NAND2X2TS U2204 ( .A(n1868), .B(Raw_mant_NRM_SWR[17]), .Y(n2996) );
NAND2X2TS U2205 ( .A(n1868), .B(Raw_mant_NRM_SWR[7]), .Y(n2960) );
INVX3TS U2206 ( .A(rst), .Y(n1419) );
INVX2TS U2207 ( .A(rst), .Y(n1422) );
BUFX3TS U2208 ( .A(n1437), .Y(n2899) );
INVX2TS U2209 ( .A(rst), .Y(n1405) );
NAND2X2TS U2210 ( .A(n1108), .B(Raw_mant_NRM_SWR[2]), .Y(n2958) );
NAND2X2TS U2211 ( .A(n1108), .B(Raw_mant_NRM_SWR[7]), .Y(n2970) );
INVX2TS U2212 ( .A(n1426), .Y(n1410) );
NAND2X1TS U2213 ( .A(n1189), .B(Raw_mant_NRM_SWR[3]), .Y(n2928) );
NAND2X2TS U2214 ( .A(n1868), .B(n991), .Y(n3010) );
MXI2X2TS U2215 ( .A(n2360), .B(n2613), .S0(n2447), .Y(n463) );
CLKINVX3TS U2216 ( .A(rst), .Y(n1408) );
CLKINVX3TS U2217 ( .A(n1426), .Y(n1406) );
NAND2X1TS U2218 ( .A(n2206), .B(DmP_EXP_EWSW[10]), .Y(n2167) );
CLKINVX3TS U2219 ( .A(n1426), .Y(n1421) );
CLKMX2X2TS U2220 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[27]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n627) );
CLKMX2X2TS U2221 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[25]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n637) );
INVX2TS U2222 ( .A(n1426), .Y(n1409) );
MXI2X1TS U2223 ( .A(n2548), .B(n2632), .S0(n1443), .Y(n684) );
MXI2X1TS U2224 ( .A(n2549), .B(n2630), .S0(n1443), .Y(n687) );
CLKBUFX3TS U2225 ( .A(n2918), .Y(n2898) );
MXI2X1TS U2226 ( .A(n2551), .B(n2693), .S0(n1443), .Y(n696) );
MXI2X1TS U2227 ( .A(n2552), .B(n2689), .S0(n1443), .Y(n699) );
CLKBUFX2TS U2228 ( .A(n2895), .Y(n2910) );
NAND2X2TS U2229 ( .A(n2119), .B(DMP_EXP_EWSW[3]), .Y(n2110) );
NAND3X4TS U2230 ( .A(n2072), .B(n2073), .C(n2071), .Y(n737) );
NAND3X4TS U2231 ( .A(n2075), .B(n2076), .C(n2074), .Y(n739) );
NOR2X8TS U2232 ( .A(n2297), .B(n2298), .Y(n2405) );
NAND2X4TS U2233 ( .A(n969), .B(n1937), .Y(n1602) );
NOR2X8TS U2234 ( .A(n2580), .B(intDX_EWSW[15]), .Y(n1777) );
OAI21X4TS U2235 ( .A0(n1777), .A1(n1776), .B0(n1775), .Y(n1558) );
NOR2X4TS U2236 ( .A(n1692), .B(n1701), .Y(n1674) );
NOR2X6TS U2237 ( .A(Raw_mant_NRM_SWR[17]), .B(n1385), .Y(n1686) );
MXI2X1TS U2238 ( .A(n2363), .B(final_result_ieee[26]), .S0(n2922), .Y(n2364)
);
AND4X4TS U2239 ( .A(n2363), .B(n2389), .C(n1908), .D(n1907), .Y(n1909) );
INVX4TS U2240 ( .A(n2363), .Y(n1884) );
BUFX3TS U2241 ( .A(n1435), .Y(n2902) );
INVX2TS U2242 ( .A(n1856), .Y(n1469) );
AND2X4TS U2243 ( .A(n1502), .B(Raw_mant_NRM_SWR[21]), .Y(n1316) );
AND2X8TS U2244 ( .A(n1630), .B(Raw_mant_NRM_SWR[6]), .Y(n1326) );
AND3X6TS U2245 ( .A(n1477), .B(n1784), .C(n1478), .Y(n1330) );
AND2X4TS U2246 ( .A(n987), .B(n2526), .Y(n1332) );
NOR2X6TS U2247 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1957)
);
AND2X4TS U2248 ( .A(n1612), .B(n1610), .Y(n1335) );
OR2X2TS U2249 ( .A(n2345), .B(n2496), .Y(n1339) );
OR2X4TS U2250 ( .A(DmP_mant_SFG_SWR_signed[10]), .B(DMP_SFG[8]), .Y(n1340)
);
BUFX16TS U2251 ( .A(shift_value_SHT2_EWR_4_), .Y(n2348) );
INVX8TS U2252 ( .A(n1819), .Y(n2495) );
AND2X2TS U2253 ( .A(n2494), .B(n898), .Y(n1341) );
AND2X2TS U2254 ( .A(n1454), .B(n2338), .Y(n1342) );
AND2X4TS U2255 ( .A(n1722), .B(DMP_SFG[20]), .Y(n1836) );
AND2X2TS U2256 ( .A(n2400), .B(n987), .Y(n1343) );
NAND2X1TS U2257 ( .A(n2427), .B(n2426), .Y(n1345) );
CLKBUFX2TS U2258 ( .A(n2888), .Y(n2905) );
INVX2TS U2259 ( .A(n1426), .Y(n1424) );
CLKINVX3TS U2260 ( .A(n1426), .Y(n1427) );
INVX3TS U2261 ( .A(rst), .Y(n1420) );
CLKINVX3TS U2262 ( .A(rst), .Y(n3068) );
CLKBUFX2TS U2263 ( .A(n2889), .Y(n2897) );
CLKBUFX3TS U2264 ( .A(n1405), .Y(n1437) );
CLKBUFX3TS U2265 ( .A(n1423), .Y(n1436) );
CLKBUFX3TS U2266 ( .A(n1410), .Y(n1435) );
CLKBUFX3TS U2267 ( .A(n1427), .Y(n2919) );
INVX2TS U2268 ( .A(rst), .Y(n1423) );
INVX2TS U2269 ( .A(n1426), .Y(n1407) );
BUFX6TS U2270 ( .A(n1643), .Y(n1346) );
NAND2X2TS U2271 ( .A(n1346), .B(Raw_mant_NRM_SWR[6]), .Y(n2962) );
OR2X8TS U2272 ( .A(n1720), .B(DMP_SFG[19]), .Y(n2422) );
XOR2X4TS U2273 ( .A(n993), .B(DmP_mant_SFG_SWR[21]), .Y(n1720) );
NOR2X8TS U2274 ( .A(n2731), .B(n1255), .Y(n1349) );
NAND3X8TS U2275 ( .A(n1355), .B(n1806), .C(n1350), .Y(n1972) );
NOR2X8TS U2276 ( .A(n1809), .B(n1351), .Y(n1350) );
NAND2X2TS U2277 ( .A(n2749), .B(n2748), .Y(n1826) );
NAND3X4TS U2278 ( .A(n2062), .B(n2063), .C(n2061), .Y(n747) );
NOR2X2TS U2279 ( .A(n2267), .B(n2266), .Y(n3000) );
OAI21X2TS U2280 ( .A0(n1411), .A1(n2599), .B0(n2265), .Y(n2267) );
NAND2X6TS U2281 ( .A(n2385), .B(DMP_SFG[0]), .Y(n2386) );
NAND3X2TS U2282 ( .A(n2018), .B(n2017), .C(n2016), .Y(n720) );
BUFX20TS U2283 ( .A(n2103), .Y(n1480) );
OAI2BB1X4TS U2284 ( .A0N(n1364), .A1N(n1365), .B0(n1789), .Y(n1790) );
NOR2X4TS U2285 ( .A(n2010), .B(n2009), .Y(n2011) );
NAND2X2TS U2286 ( .A(n1418), .B(intDY_EWSW[16]), .Y(n2073) );
NAND2X2TS U2287 ( .A(n886), .B(intDY_EWSW[11]), .Y(n2102) );
NAND2X2TS U2288 ( .A(n998), .B(intDX_EWSW[3]), .Y(n2217) );
NAND2X2TS U2289 ( .A(n1594), .B(n882), .Y(n2115) );
NAND2X4TS U2290 ( .A(n2328), .B(n2358), .Y(n1788) );
NOR2X6TS U2291 ( .A(n1764), .B(n1766), .Y(n1485) );
OAI22X2TS U2292 ( .A0(n1432), .A1(n2609), .B0(n2457), .B1(n1404), .Y(n2995)
);
NAND2X6TS U2293 ( .A(n1335), .B(n1194), .Y(n1609) );
OAI2BB2X4TS U2294 ( .B0(n1769), .B1(n1455), .A0N(n2574), .A1N(intDX_EWSW[9]),
.Y(n1506) );
OA21X4TS U2295 ( .A0(n1772), .A1(n1771), .B0(n1770), .Y(n1380) );
BUFX20TS U2296 ( .A(n1183), .Y(n1495) );
NAND3X6TS U2297 ( .A(n2128), .B(n2127), .C(n2126), .Y(n564) );
AOI2BB2X4TS U2298 ( .B0(n2336), .B1(n1434), .A0N(n1381), .A1N(n1382), .Y(
n3063) );
INVX2TS U2299 ( .A(n1387), .Y(n1382) );
NAND2X2TS U2300 ( .A(n1398), .B(intDY_EWSW[17]), .Y(n2175) );
NAND2X2TS U2301 ( .A(n1512), .B(intDY_EWSW[22]), .Y(n2181) );
NAND2X2TS U2302 ( .A(n2231), .B(intDY_EWSW[25]), .Y(n2134) );
NAND2X2TS U2303 ( .A(n2231), .B(intDY_EWSW[19]), .Y(n2196) );
NAND2X2TS U2304 ( .A(n2231), .B(intDX_EWSW[0]), .Y(n2118) );
NAND2X2TS U2305 ( .A(n2403), .B(Raw_mant_NRM_SWR[0]), .Y(n2142) );
NAND2X6TS U2306 ( .A(n2403), .B(n1958), .Y(n2143) );
NAND2X2TS U2307 ( .A(n1418), .B(n1497), .Y(n2229) );
NAND2X4TS U2308 ( .A(n978), .B(intDY_EWSW[12]), .Y(n1595) );
INVX2TS U2309 ( .A(n1619), .Y(n1717) );
AOI22X2TS U2310 ( .A0(n936), .A1(n2335), .B0(n2330), .B1(n2333), .Y(n1873)
);
NAND3X4TS U2311 ( .A(n2020), .B(n2773), .C(n2772), .Y(n2021) );
OAI21X2TS U2312 ( .A0(n2272), .A1(n1411), .B0(n2271), .Y(n2979) );
NAND2X2TS U2313 ( .A(n2231), .B(intDX_EWSW[28]), .Y(n2245) );
INVX12TS U2314 ( .A(n1657), .Y(n2882) );
NAND2X2TS U2315 ( .A(n886), .B(n889), .Y(n2106) );
NAND2X2TS U2316 ( .A(n1418), .B(intDY_EWSW[8]), .Y(n2109) );
OAI21X2TS U2317 ( .A0(n1736), .A1(n1735), .B0(n1734), .Y(n1737) );
NAND2X4TS U2318 ( .A(n1468), .B(n1466), .Y(n2325) );
NAND3X4TS U2319 ( .A(n1535), .B(n1541), .C(n1534), .Y(n521) );
AND2X8TS U2320 ( .A(intDY_EWSW[6]), .B(n1397), .Y(n1765) );
NOR2X4TS U2321 ( .A(n2882), .B(Raw_mant_NRM_SWR[14]), .Y(n1675) );
NOR2X4TS U2322 ( .A(n2259), .B(n2261), .Y(n2047) );
XOR2X4TS U2323 ( .A(n1401), .B(n2616), .Y(n1726) );
NAND4X8TS U2324 ( .A(n2786), .B(n2785), .C(n1786), .D(n2784), .Y(n2331) );
NAND2X2TS U2325 ( .A(n1868), .B(n2424), .Y(n3015) );
AOI2BB2X2TS U2326 ( .B0(n2489), .B1(DmP_mant_SHT1_SW[9]), .A0N(n2497), .A1N(
n2601), .Y(n1951) );
NAND2X2TS U2327 ( .A(n2231), .B(intDX_EWSW[31]), .Y(n2017) );
NOR2X8TS U2328 ( .A(n2356), .B(n2348), .Y(n2330) );
NAND2X2TS U2329 ( .A(n2313), .B(n2356), .Y(n1850) );
NAND2X2TS U2330 ( .A(n1398), .B(n1395), .Y(n2166) );
NAND2X2TS U2331 ( .A(n1398), .B(intDY_EWSW[21]), .Y(n2172) );
INVX3TS U2332 ( .A(rst), .Y(n1416) );
MXI2X2TS U2333 ( .A(n2538), .B(n2692), .S0(n1443), .Y(n693) );
NAND2X1TS U2334 ( .A(n2500), .B(shift_value_SHT2_EWR_4_), .Y(n2147) );
NAND2X2TS U2335 ( .A(n2349), .B(n2348), .Y(n2353) );
NAND2X2TS U2336 ( .A(n2314), .B(n2348), .Y(n2027) );
NAND2X4TS U2337 ( .A(n2318), .B(n2348), .Y(n1915) );
NAND2X2TS U2338 ( .A(n2481), .B(Raw_mant_NRM_SWR[18]), .Y(n1626) );
NAND2X2TS U2339 ( .A(n2350), .B(n2454), .Y(n1814) );
NAND2X8TS U2340 ( .A(n2305), .B(n1969), .Y(n1821) );
NOR2X8TS U2341 ( .A(n2348), .B(n2358), .Y(n2334) );
NAND2BX2TS U2342 ( .AN(n2358), .B(n1863), .Y(n1438) );
NAND2X2TS U2343 ( .A(n1862), .B(n2358), .Y(n1439) );
NAND2X2TS U2344 ( .A(n1594), .B(intDX_EWSW[23]), .Y(n2127) );
NAND2X2TS U2345 ( .A(n978), .B(intDX_EWSW[18]), .Y(n2165) );
NAND2X2TS U2346 ( .A(n978), .B(intDX_EWSW[19]), .Y(n2195) );
NAND2X2TS U2347 ( .A(n2232), .B(n883), .Y(n2189) );
NAND2X2TS U2348 ( .A(n978), .B(intDX_EWSW[13]), .Y(n2186) );
XOR2X2TS U2349 ( .A(n1503), .B(DmP_mant_SFG_SWR[25]), .Y(n1727) );
NOR2X6TS U2350 ( .A(n1662), .B(n1661), .Y(n2503) );
NAND2BX2TS U2351 ( .AN(n2615), .B(n1726), .Y(n2373) );
XNOR2X4TS U2352 ( .A(n984), .B(n474), .Y(n2873) );
XNOR2X4TS U2353 ( .A(n483), .B(n984), .Y(n2762) );
OAI22X4TS U2354 ( .A0(n1774), .A1(n1442), .B0(intDY_EWSW[13]), .B1(n1314),
.Y(n1507) );
NOR2X8TS U2355 ( .A(n2592), .B(intDX_EWSW[13]), .Y(n1774) );
MXI2X2TS U2356 ( .A(n2555), .B(n2680), .S0(n1443), .Y(n708) );
NAND2X4TS U2357 ( .A(n1448), .B(n1530), .Y(n1444) );
NOR2X8TS U2358 ( .A(n1777), .B(n1452), .Y(n1559) );
XNOR2X4TS U2359 ( .A(n993), .B(DmP_mant_SFG_SWR[19]), .Y(n1619) );
NOR2X8TS U2360 ( .A(n2574), .B(intDX_EWSW[9]), .Y(n1769) );
XOR2X4TS U2361 ( .A(n477), .B(n2377), .Y(n2819) );
AND3X8TS U2362 ( .A(n1458), .B(n1864), .C(n1457), .Y(n3040) );
NAND2BX4TS U2363 ( .AN(n2356), .B(n1863), .Y(n1457) );
NAND3X8TS U2364 ( .A(n1464), .B(n1463), .C(n1461), .Y(n2455) );
NOR2X8TS U2365 ( .A(n1462), .B(n1327), .Y(n1461) );
AND3X8TS U2366 ( .A(n2727), .B(n2728), .C(n2726), .Y(n1462) );
NAND2X2TS U2367 ( .A(n2454), .B(n986), .Y(n1468) );
INVX12TS U2368 ( .A(n1812), .Y(n2350) );
NAND3X8TS U2369 ( .A(n1313), .B(n1668), .C(n1333), .Y(n2270) );
NAND2X8TS U2370 ( .A(n1673), .B(n1467), .Y(n1927) );
NOR2BX4TS U2371 ( .AN(n2801), .B(n1331), .Y(n1467) );
AOI21X4TS U2372 ( .A0(n2328), .A1(n1415), .B0(n1474), .Y(n3032) );
OAI2BB1X4TS U2373 ( .A0N(n2270), .A1N(n1937), .B0(n1669), .Y(n2329) );
INVX16TS U2374 ( .A(n1479), .Y(n2103) );
NAND2X8TS U2375 ( .A(n1514), .B(Shift_reg_FLAGS_7_6), .Y(n1479) );
OAI21X4TS U2376 ( .A0(n1487), .A1(n1484), .B0(n1481), .Y(n1511) );
AOI21X4TS U2377 ( .A0(n1483), .A1(n1486), .B0(n1482), .Y(n1481) );
OAI21X4TS U2378 ( .A0(n1768), .A1(n1572), .B0(n1767), .Y(n1482) );
NOR2X8TS U2379 ( .A(n1768), .B(n1765), .Y(n1486) );
AOI21X4TS U2380 ( .A0(n1493), .A1(n1489), .B0(n1488), .Y(n1487) );
OAI21X4TS U2381 ( .A0(n1492), .A1(n1491), .B0(n1490), .Y(n1489) );
NOR2X4TS U2382 ( .A(n1392), .B(intDX_EWSW[1]), .Y(n1492) );
NAND2X2TS U2383 ( .A(n2378), .B(DMP_EXP_EWSW[9]), .Y(n2092) );
CLKINVX12TS U2384 ( .A(n2059), .Y(n2060) );
NOR2X8TS U2385 ( .A(n2512), .B(n2505), .Y(n1904) );
NOR2X8TS U2386 ( .A(n1494), .B(n1894), .Y(n1654) );
AND2X8TS U2387 ( .A(n1896), .B(n1895), .Y(n1494) );
NAND2X2TS U2388 ( .A(n2119), .B(DMP_EXP_EWSW[8]), .Y(n2107) );
NAND2X2TS U2389 ( .A(n2119), .B(DMP_EXP_EWSW[7]), .Y(n2113) );
NAND2X2TS U2390 ( .A(n2206), .B(DmP_EXP_EWSW[12]), .Y(n2161) );
NAND2X2TS U2391 ( .A(n2206), .B(DmP_EXP_EWSW[8]), .Y(n2207) );
MXI2X4TS U2392 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2490), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2502) );
BUFX6TS U2393 ( .A(intDX_EWSW[1]), .Y(n1497) );
INVX2TS U2394 ( .A(n1963), .Y(n1498) );
OAI21X4TS U2395 ( .A0(n1880), .A1(n1890), .B0(n1892), .Y(n1883) );
NOR2X8TS U2396 ( .A(n1500), .B(n1499), .Y(n1880) );
NAND3X4TS U2397 ( .A(n1886), .B(n1885), .C(n1884), .Y(n1900) );
NAND3X8TS U2398 ( .A(n1528), .B(n1527), .C(n2052), .Y(n1521) );
AOI2BB2X2TS U2399 ( .B0(n2472), .B1(DmP_mant_SHT1_SW[11]), .A0N(n2497),
.A1N(n2604), .Y(n1824) );
NAND2BX4TS U2400 ( .AN(n1818), .B(n1554), .Y(n2941) );
NOR2X1TS U2401 ( .A(n2345), .B(n2344), .Y(n2346) );
NOR2X2TS U2402 ( .A(n2347), .B(n2346), .Y(n2354) );
NOR2X4TS U2403 ( .A(n1650), .B(Raw_mant_NRM_SWR[14]), .Y(n1677) );
NOR2X6TS U2404 ( .A(n1711), .B(DMP_SFG[10]), .Y(n2297) );
INVX6TS U2405 ( .A(n2270), .Y(n1811) );
AND2X8TS U2406 ( .A(n1711), .B(DMP_SFG[10]), .Y(n1515) );
NAND2BX1TS U2407 ( .AN(n1515), .B(n2295), .Y(n1518) );
NAND2X8TS U2408 ( .A(n1526), .B(n2279), .Y(n2289) );
OR2X8TS U2409 ( .A(n2278), .B(n2394), .Y(n1526) );
NAND2X8TS U2410 ( .A(n1529), .B(n2299), .Y(n1605) );
NOR2X8TS U2411 ( .A(n1061), .B(n1533), .Y(n1546) );
NOR2BX4TS U2412 ( .AN(n1824), .B(n1555), .Y(n1554) );
INVX2TS U2413 ( .A(n1825), .Y(n1555) );
INVX12TS U2414 ( .A(n1653), .Y(n2439) );
OR2X8TS U2415 ( .A(n2537), .B(n2248), .Y(n1653) );
NAND2X8TS U2416 ( .A(n1413), .B(n1820), .Y(n1822) );
OR2X8TS U2417 ( .A(n2884), .B(n1564), .Y(n2977) );
OAI21X4TS U2418 ( .A0(n1579), .A1(n2481), .B0(n1641), .Y(n525) );
AOI2BB1X4TS U2419 ( .A0N(n2595), .A1N(intDX_EWSW[16]), .B0(n1760), .Y(n1581)
);
NAND3X8TS U2420 ( .A(n1584), .B(n2839), .C(n1796), .Y(n2468) );
NOR2BX4TS U2421 ( .AN(n2837), .B(n1585), .Y(n1584) );
NAND3X8TS U2422 ( .A(n1588), .B(n1795), .C(n1587), .Y(n2486) );
NOR2BX4TS U2423 ( .AN(n2792), .B(n951), .Y(n1587) );
BUFX20TS U2424 ( .A(n2223), .Y(n1594) );
NOR2X4TS U2425 ( .A(n2584), .B(intDX_EWSW[8]), .Y(n1598) );
NOR2X8TS U2426 ( .A(n2581), .B(intDX_EWSW[11]), .Y(n1772) );
NAND2X8TS U2427 ( .A(n1841), .B(n1601), .Y(n2989) );
AOI21X4TS U2428 ( .A0(n2342), .A1(n2744), .B0(n957), .Y(n1604) );
OAI2BB1X4TS U2429 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1646), .B0(n2308),
.Y(n512) );
NAND2X2TS U2430 ( .A(n1630), .B(Raw_mant_NRM_SWR[19]), .Y(n1833) );
NAND2X4TS U2431 ( .A(n2990), .B(n2883), .Y(n2993) );
NAND2X6TS U2432 ( .A(n1135), .B(Raw_mant_NRM_SWR[18]), .Y(n1835) );
XOR2X4TS U2433 ( .A(n993), .B(DmP_mant_SFG_SWR[17]), .Y(n1715) );
OR2X8TS U2434 ( .A(n1043), .B(n1606), .Y(n515) );
NAND2X8TS U2435 ( .A(n1687), .B(n1607), .Y(n1695) );
OAI21X4TS U2436 ( .A0(n1627), .A1(n2041), .B0(n1613), .Y(n1612) );
CLKINVX6TS U2437 ( .A(n2417), .Y(n1620) );
OAI21X4TS U2438 ( .A0(n1840), .A1(n1429), .B0(n1839), .Y(n519) );
OAI21X4TS U2439 ( .A0(n1694), .A1(Raw_mant_NRM_SWR[22]), .B0(n1307), .Y(
n1625) );
NAND3X4TS U2440 ( .A(n2400), .B(n987), .C(n2530), .Y(n1696) );
BUFX20TS U2441 ( .A(n2501), .Y(n1630) );
NAND2X4TS U2442 ( .A(n2885), .B(Raw_mant_NRM_SWR[8]), .Y(n2967) );
AOI22X4TS U2443 ( .A0(n2885), .A1(Raw_mant_NRM_SWR[13]), .B0(n988), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1841) );
AOI22X4TS U2444 ( .A0(n2885), .A1(Raw_mant_NRM_SWR[5]), .B0(n988), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1968) );
NAND3BX4TS U2445 ( .AN(n1633), .B(n2027), .C(n2026), .Y(n2336) );
NAND3BX4TS U2446 ( .AN(n2022), .B(n2025), .C(n1339), .Y(n1633) );
NOR2BX4TS U2447 ( .AN(n1964), .B(n1637), .Y(n1636) );
XOR2X4TS U2448 ( .A(n2920), .B(DmP_mant_SFG_SWR[12]), .Y(n1711) );
AOI2BB2X2TS U2449 ( .B0(n2023), .B1(n2461), .A0N(n1821), .A1N(n2639), .Y(
n1825) );
NAND2X2TS U2450 ( .A(n2317), .B(n1434), .Y(n2321) );
BUFX12TS U2451 ( .A(n2651), .Y(n2886) );
MXI2X4TS U2452 ( .A(n3049), .B(n2671), .S0(n2448), .Y(n472) );
NAND2X2TS U2453 ( .A(n2138), .B(n2137), .Y(n2140) );
OR2X4TS U2454 ( .A(n1713), .B(DMP_SFG[13]), .Y(n2304) );
NAND3X8TS U2455 ( .A(n1905), .B(n1904), .C(n1644), .Y(n2059) );
NOR2X8TS U2456 ( .A(n1900), .B(n2369), .Y(n1905) );
NAND3X4TS U2457 ( .A(n1799), .B(n1798), .C(n1797), .Y(n1852) );
NAND4X4TS U2458 ( .A(n1807), .B(n2870), .C(n2871), .D(n2869), .Y(n1808) );
NAND2X2TS U2459 ( .A(n1921), .B(n1434), .Y(n1920) );
OAI21X4TS U2460 ( .A0(n1893), .A1(n1892), .B0(n1891), .Y(n1894) );
NAND2X2TS U2461 ( .A(n1643), .B(n991), .Y(n3016) );
AOI22X2TS U2462 ( .A0(n1800), .A1(n2462), .B0(n2334), .B1(n2314), .Y(n2315)
);
OAI22X2TS U2463 ( .A0(n1432), .A1(n2603), .B0(n2458), .B1(n1404), .Y(n3004)
);
NAND3X6TS U2464 ( .A(n2122), .B(n2121), .C(n2120), .Y(n752) );
NAND3X6TS U2465 ( .A(n2212), .B(n2211), .C(n2210), .Y(n560) );
NAND2X4TS U2466 ( .A(n1015), .B(n2486), .Y(n1799) );
NAND2X2TS U2467 ( .A(n1108), .B(Raw_mant_NRM_SWR[5]), .Y(n2931) );
NAND3X6TS U2468 ( .A(n1848), .B(n1847), .C(n2872), .Y(n2462) );
MXI2X4TS U2469 ( .A(n3055), .B(n2659), .S0(n2448), .Y(n469) );
NAND2X4TS U2470 ( .A(n2332), .B(n1415), .Y(n1874) );
NAND2X4TS U2471 ( .A(n1929), .B(DMP_SFG[1]), .Y(n2250) );
NAND2X2TS U2472 ( .A(n2323), .B(n2306), .Y(n1966) );
MXI2X2TS U2473 ( .A(n2388), .B(n2694), .S0(n1429), .Y(n540) );
MXI2X2TS U2474 ( .A(n3051), .B(n2670), .S0(n2448), .Y(n471) );
NOR2X8TS U2475 ( .A(n1656), .B(DMP_exp_NRM2_EW[3]), .Y(n1893) );
AOI2BB2X4TS U2476 ( .B0(DmP_mant_SHT1_SW[15]), .B1(n2489), .A0N(n1411),
.A1N(n2602), .Y(n2366) );
AND4X8TS U2477 ( .A(n2854), .B(n2853), .C(n1663), .D(n2852), .Y(n2456) );
MXI2X2TS U2478 ( .A(n2325), .B(n2324), .S0(n2358), .Y(n2327) );
AOI22X2TS U2479 ( .A0(n2355), .A1(n2310), .B0(n2334), .B1(n2349), .Y(n2311)
);
CLKMX2X3TS U2480 ( .A(Data_Y[7]), .B(n882), .S0(n2514), .Y(n821) );
NAND2X4TS U2481 ( .A(n2512), .B(n1909), .Y(n1910) );
NOR2X4TS U2482 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM2_EW[5]), .Y(n1897)
);
NAND2X2TS U2483 ( .A(n2582), .B(intDX_EWSW[7]), .Y(n1767) );
BUFX20TS U2484 ( .A(n1800), .Y(n2355) );
NAND2X4TS U2485 ( .A(n978), .B(intDY_EWSW[0]), .Y(n2117) );
NAND2X4TS U2486 ( .A(n1495), .B(intDX_EWSW[6]), .Y(n2226) );
NAND2X6TS U2487 ( .A(n1971), .B(n1970), .Y(n2971) );
NAND2X2TS U2488 ( .A(n2578), .B(intDX_EWSW[21]), .Y(n1742) );
NAND2X2TS U2489 ( .A(n977), .B(intDX_EWSW[11]), .Y(n2192) );
NAND2X2TS U2490 ( .A(n998), .B(intDX_EWSW[9]), .Y(n2204) );
MXI2X4TS U2491 ( .A(n2337), .B(n2678), .S0(n900), .Y(n487) );
NAND2X4TS U2492 ( .A(n1715), .B(DMP_SFG[15]), .Y(n2417) );
NAND3X4TS U2493 ( .A(n1794), .B(n1793), .C(n1792), .Y(n1851) );
AOI22X2TS U2494 ( .A0(n2355), .A1(n2465), .B0(n1414), .B1(n1950), .Y(n1864)
);
NAND2X2TS U2495 ( .A(n1913), .B(n1927), .Y(n1813) );
NAND2X4TS U2496 ( .A(n878), .B(intDX_EWSW[15]), .Y(n2201) );
NAND2X4TS U2497 ( .A(n1398), .B(intDY_EWSW[15]), .Y(n2202) );
CLKMX2X3TS U2498 ( .A(Data_X[4]), .B(n883), .S0(n2518), .Y(n858) );
NOR2X4TS U2499 ( .A(n2585), .B(intDX_EWSW[4]), .Y(n1764) );
NOR2X8TS U2500 ( .A(DMP_exp_NRM2_EW[1]), .B(n1311), .Y(n1889) );
NAND2X4TS U2501 ( .A(n2745), .B(n1259), .Y(n1670) );
OAI21X4TS U2502 ( .A0(n2473), .A1(n2476), .B0(n2477), .Y(n2048) );
XOR2X4TS U2503 ( .A(n2876), .B(DmP_mant_SFG_SWR[7]), .Y(n2045) );
OAI21X4TS U2504 ( .A0(n1760), .A1(n1733), .B0(n1732), .Y(n1738) );
NAND2X2TS U2505 ( .A(n2595), .B(intDX_EWSW[16]), .Y(n1733) );
NAND2X4TS U2506 ( .A(n2024), .B(n1941), .Y(n1942) );
NAND2X2TS U2507 ( .A(n1941), .B(n2350), .Y(n1793) );
INVX16TS U2508 ( .A(n2884), .Y(n2883) );
AOI22X2TS U2509 ( .A0(n2359), .A1(n1415), .B0(n969), .B1(n2355), .Y(n2357)
);
NAND3X8TS U2510 ( .A(n2834), .B(n1667), .C(n2833), .Y(n2465) );
OAI22X2TS U2511 ( .A0(n1432), .A1(n2598), .B0(n2459), .B1(n1404), .Y(n3009)
);
MXI2X4TS U2512 ( .A(n3057), .B(n2668), .S0(n2448), .Y(n468) );
MX2X4TS U2513 ( .A(Data_X[2]), .B(intDX_EWSW[2]), .S0(n2518), .Y(n860) );
NAND4BX4TS U2514 ( .AN(n2813), .B(n1829), .C(n2812), .D(n2811), .Y(n2319) );
NAND2X4TS U2515 ( .A(n2754), .B(n2342), .Y(n1829) );
AOI21X4TS U2516 ( .A0(n1750), .A1(n1749), .B0(n1748), .Y(n1751) );
OAI21X2TS U2517 ( .A0(n1747), .A1(n1746), .B0(n1745), .Y(n1748) );
NAND2X4TS U2518 ( .A(n2885), .B(n1306), .Y(n1865) );
NAND4BX4TS U2519 ( .AN(n2868), .B(n1918), .C(n2867), .D(n2866), .Y(n2339) );
NAND2X4TS U2520 ( .A(n2757), .B(n2342), .Y(n1918) );
NAND2X4TS U2521 ( .A(n1656), .B(DMP_exp_NRM2_EW[3]), .Y(n1891) );
NAND2X2TS U2522 ( .A(n2581), .B(intDX_EWSW[11]), .Y(n1770) );
NAND2X4TS U2523 ( .A(n2740), .B(n1259), .Y(n2020) );
NAND2X2TS U2524 ( .A(n2045), .B(DMP_SFG[5]), .Y(n2262) );
NOR2X4TS U2525 ( .A(n2045), .B(DMP_SFG[5]), .Y(n2261) );
XNOR2X4TS U2526 ( .A(n1899), .B(DMP_exp_NRM2_EW[7]), .Y(n2369) );
OAI21X4TS U2527 ( .A0(n1654), .A1(n2509), .B0(n1898), .Y(n1899) );
NOR2X4TS U2528 ( .A(n2577), .B(intDX_EWSW[23]), .Y(n1747) );
NAND2X4TS U2529 ( .A(n1720), .B(DMP_SFG[19]), .Y(n2421) );
NAND2X2TS U2530 ( .A(n1430), .B(n2468), .Y(n1798) );
NAND2X2TS U2531 ( .A(n1913), .B(n2468), .Y(n1842) );
AOI22X2TS U2532 ( .A0(n2359), .A1(n1434), .B0(n936), .B1(n969), .Y(n2360) );
NOR2X4TS U2533 ( .A(n1826), .B(n2756), .Y(n1827) );
NOR2X4TS U2534 ( .A(n1930), .B(DMP_SFG[2]), .Y(n2474) );
XOR2X4TS U2535 ( .A(n2876), .B(DmP_mant_SFG_SWR[4]), .Y(n1930) );
XOR2X4TS U2536 ( .A(n1880), .B(n1879), .Y(n2389) );
NAND2X4TS U2537 ( .A(n1878), .B(n1892), .Y(n1879) );
NAND2X4TS U2538 ( .A(n1328), .B(n2468), .Y(n1830) );
NAND2X2TS U2539 ( .A(n1328), .B(n1869), .Y(n1669) );
NOR2X4TS U2540 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[11]), .Y(
n1679) );
MXI2X4TS U2541 ( .A(n3045), .B(n2625), .S0(n935), .Y(n474) );
AOI22X2TS U2542 ( .A0(n1972), .A1(n1415), .B0(n2270), .B1(n1800), .Y(n3027)
);
AOI22X2TS U2543 ( .A0(n2336), .A1(n1415), .B0(n1387), .B1(n1800), .Y(n2337)
);
XOR2X4TS U2544 ( .A(n1877), .B(n1888), .Y(n2361) );
NAND2X4TS U2545 ( .A(n1876), .B(n1887), .Y(n1877) );
XOR2X4TS U2546 ( .A(n1654), .B(n1902), .Y(n2512) );
NAND4X8TS U2547 ( .A(n1801), .B(n2842), .C(n2841), .D(n2840), .Y(n2483) );
OAI21X4TS U2548 ( .A0(n2720), .A1(n2719), .B0(n2718), .Y(n1801) );
XNOR2X4TS U2549 ( .A(n1883), .B(n1882), .Y(n2363) );
NOR2X8TS U2550 ( .A(DmP_mant_SFG_SWR_signed[9]), .B(DMP_SFG[7]), .Y(n2278)
);
MXI2X1TS U2551 ( .A(DmP_mant_SHT1_SW[14]), .B(n913), .S0(n2433), .Y(n1645)
);
INVX8TS U2552 ( .A(n1521), .Y(n2408) );
INVX2TS U2553 ( .A(DmP_mant_SHT1_SW[20]), .Y(n2470) );
CLKBUFX3TS U2554 ( .A(n2906), .Y(n2896) );
NAND2X2TS U2555 ( .A(n1108), .B(Raw_mant_NRM_SWR[11]), .Y(n2988) );
BUFX3TS U2556 ( .A(n2705), .Y(n2911) );
BUFX3TS U2557 ( .A(n2700), .Y(n2891) );
NAND2X4TS U2561 ( .A(n2741), .B(n1259), .Y(n1668) );
NAND2X1TS U2562 ( .A(n1430), .B(n2453), .Y(n1671) );
NAND2X4TS U2563 ( .A(n2882), .B(n1686), .Y(n1681) );
OR2X2TS U2564 ( .A(n1650), .B(Raw_mant_NRM_SWR[13]), .Y(n1688) );
INVX12TS U2565 ( .A(n2925), .Y(n2440) );
OR2X8TS U2566 ( .A(n2248), .B(n2440), .Y(n1819) );
OAI21X4TS U2567 ( .A0(n2399), .A1(n1706), .B0(n1705), .Y(n2145) );
NAND2X2TS U2568 ( .A(DmP_mant_SFG_SWR_signed[10]), .B(DMP_SFG[8]), .Y(n2292)
);
XOR2X4TS U2569 ( .A(n993), .B(DmP_mant_SFG_SWR[20]), .Y(n1719) );
XOR2X4TS U2570 ( .A(n993), .B(DmP_mant_SFG_SWR[18]), .Y(n1716) );
NOR2X4TS U2571 ( .A(n1728), .B(n1752), .Y(n1729) );
NOR2X6TS U2572 ( .A(n1730), .B(n1756), .Y(n1731) );
NOR2X4TS U2573 ( .A(n2578), .B(intDX_EWSW[21]), .Y(n1744) );
NOR2X4TS U2574 ( .A(n1739), .B(n1744), .Y(n1741) );
OAI21X2TS U2575 ( .A0(n1744), .A1(n1743), .B0(n1742), .Y(n1750) );
NAND2X1TS U2576 ( .A(n2577), .B(intDX_EWSW[23]), .Y(n1745) );
INVX12TS U2577 ( .A(Shift_reg_FLAGS_7_6), .Y(n2206) );
NAND2X2TS U2578 ( .A(n2231), .B(intDX_EWSW[26]), .Y(n1779) );
NAND2X1TS U2579 ( .A(n2378), .B(n1374), .Y(n1778) );
NAND2X1TS U2580 ( .A(n2747), .B(n2746), .Y(n1781) );
NOR2X4TS U2581 ( .A(n1781), .B(n2755), .Y(n1782) );
NAND2X1TS U2582 ( .A(n1940), .B(n1927), .Y(n1784) );
AOI2BB2X4TS U2583 ( .B0(n2753), .B1(n2752), .A0N(n1258), .A1N(n2751), .Y(
n1783) );
INVX16TS U2584 ( .A(n2358), .Y(n2356) );
AOI22X1TS U2585 ( .A0(n2355), .A1(n2331), .B0(n2334), .B1(n2329), .Y(n1787)
);
AND2X4TS U2586 ( .A(n1788), .B(n1787), .Y(n3053) );
NAND2X8TS U2587 ( .A(n1875), .B(Shift_reg_FLAGS_7[3]), .Y(n2444) );
BUFX12TS U2588 ( .A(n2444), .Y(n2448) );
MXI2X4TS U2589 ( .A(n3053), .B(n2669), .S0(n2448), .Y(n470) );
NAND2X4TS U2590 ( .A(n1015), .B(n2365), .Y(n1794) );
AOI21X4TS U2591 ( .A0(n1256), .A1(n2712), .B0(n2711), .Y(n1791) );
MXI2X4TS U2592 ( .A(n1851), .B(n1852), .S0(n2358), .Y(n1803) );
AOI22X1TS U2593 ( .A0(n2439), .A1(DmP_mant_SHT1_SW[9]), .B0(n1969), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1804) );
NAND2X2TS U2594 ( .A(n2024), .B(n2455), .Y(n1806) );
INVX2TS U2595 ( .A(n2331), .Y(n2458) );
NAND2X4TS U2596 ( .A(n1015), .B(n2465), .Y(n1810) );
OAI22X4TS U2597 ( .A0(n2341), .A1(n1383), .B0(n1812), .B1(n1811), .Y(n1863)
);
NAND3X4TS U2598 ( .A(n1815), .B(n1814), .C(n1813), .Y(n1862) );
AOI22X2TS U2599 ( .A0(n2355), .A1(n1950), .B0(n1414), .B1(n2465), .Y(n1816)
);
NOR2X8TS U2600 ( .A(n2500), .B(n1820), .Y(n2305) );
MXI2X4TS U2601 ( .A(n3061), .B(n2657), .S0(n2448), .Y(n465) );
AOI22X1TS U2602 ( .A0(n2439), .A1(DmP_mant_SHT1_SW[5]), .B0(n1969), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1834) );
NAND2X2TS U2603 ( .A(n1108), .B(n1385), .Y(n2997) );
NAND2X2TS U2604 ( .A(n2350), .B(n2486), .Y(n1844) );
NAND2X1TS U2605 ( .A(n1940), .B(n1387), .Y(n1843) );
NAND2X1TS U2606 ( .A(n2716), .B(n2715), .Y(n1846) );
AND2X8TS U2607 ( .A(n1850), .B(n1849), .Y(n3034) );
MXI2X4TS U2608 ( .A(n1852), .B(n1851), .S0(n2358), .Y(n1854) );
AOI22X1TS U2609 ( .A0(n2439), .A1(DmP_mant_SHT1_SW[1]), .B0(n1969), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1866) );
NAND2X1TS U2610 ( .A(n1430), .B(n2465), .Y(n1872) );
NAND2X1TS U2611 ( .A(n1940), .B(n2270), .Y(n1871) );
NAND2X1TS U2612 ( .A(n2024), .B(n1869), .Y(n1870) );
NOR2X6TS U2613 ( .A(n1658), .B(DMP_exp_NRM2_EW[2]), .Y(n1890) );
INVX2TS U2614 ( .A(n1890), .Y(n1878) );
INVX2TS U2615 ( .A(n2389), .Y(n1885) );
NOR2X4TS U2616 ( .A(n1890), .B(n1893), .Y(n1895) );
NAND2X4TS U2617 ( .A(n1897), .B(n2506), .Y(n1906) );
INVX2TS U2618 ( .A(n1906), .Y(n1898) );
INVX2TS U2619 ( .A(n2509), .Y(n1901) );
NAND2X4TS U2620 ( .A(n1901), .B(n2506), .Y(n1902) );
NOR2X1TS U2621 ( .A(n1906), .B(DMP_exp_NRM2_EW[7]), .Y(n1907) );
OAI2BB1X4TS U2622 ( .A0N(n2059), .A1N(n1911), .B0(n2383), .Y(n1912) );
OAI2BB1X4TS U2623 ( .A0N(final_result_ieee[31]), .A1N(n2607), .B0(n1912),
.Y(n543) );
NAND2X8TS U2624 ( .A(n2383), .B(n2059), .Y(n2881) );
AOI22X1TS U2625 ( .A0(n1800), .A1(n2339), .B0(n2334), .B1(n1922), .Y(n1919)
);
OAI22X4TS U2626 ( .A0(n2881), .A1(n2322), .B0(n974), .B1(n2673), .Y(n494) );
NAND2X2TS U2627 ( .A(n1512), .B(intDX_EWSW[24]), .Y(n1926) );
NAND2X1TS U2628 ( .A(n2378), .B(n1294), .Y(n1925) );
XOR2X4TS U2629 ( .A(n1503), .B(DmP_mant_SFG_SWR[3]), .Y(n1929) );
XOR2X4TS U2630 ( .A(n1503), .B(DmP_mant_SFG_SWR[2]), .Y(n2385) );
AND2X2TS U2631 ( .A(n2875), .B(DMP_SFG[3]), .Y(n1931) );
XOR2X4TS U2632 ( .A(n993), .B(n2568), .Y(n1932) );
NAND2X2TS U2633 ( .A(n1195), .B(intDY_EWSW[15]), .Y(n1936) );
NAND2X2TS U2634 ( .A(n2222), .B(intDX_EWSW[15]), .Y(n1935) );
NAND2X1TS U2635 ( .A(n2640), .B(n1369), .Y(n1934) );
NAND2X4TS U2636 ( .A(n2309), .B(n2356), .Y(n1943) );
AND2X8TS U2637 ( .A(n1943), .B(n1944), .Y(n3036) );
AOI22X1TS U2638 ( .A0(n2439), .A1(DmP_mant_SHT1_SW[6]), .B0(n1969), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1946) );
AOI2BB2X1TS U2639 ( .B0(n2310), .B1(n2461), .A0N(n1821), .A1N(n2642), .Y(
n1948) );
AOI2BB2X1TS U2640 ( .B0(n1950), .B1(n2461), .A0N(n1821), .A1N(n2641), .Y(
n1952) );
NOR3X1TS U2641 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .C(n2565),
.Y(n1958) );
OA21X4TS U2642 ( .A0(n2248), .A1(LZD_output_NRM2_EW[3]), .B0(n2239), .Y(n516) );
NAND2X2TS U2643 ( .A(n988), .B(DmP_mant_SHT1_SW[13]), .Y(n2306) );
NAND2X4TS U2644 ( .A(n1135), .B(Raw_mant_NRM_SWR[1]), .Y(n1971) );
AOI22X1TS U2645 ( .A0(n2439), .A1(DmP_mant_SHT1_SW[22]), .B0(n1969), .B1(
DmP_mant_SHT1_SW[21]), .Y(n1970) );
NAND2X4TS U2646 ( .A(n2971), .B(n2883), .Y(n2975) );
MXI2X2TS U2647 ( .A(n3027), .B(n2656), .S0(n933), .Y(n485) );
CLKXOR2X2TS U2648 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n2030) );
XNOR2X1TS U2649 ( .A(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1975) );
XNOR2X1TS U2650 ( .A(intDY_EWSW[26]), .B(intDX_EWSW[26]), .Y(n1974) );
XNOR2X1TS U2651 ( .A(n1395), .B(intDX_EWSW[18]), .Y(n1973) );
XOR2X1TS U2652 ( .A(intDY_EWSW[30]), .B(intDX_EWSW[30]), .Y(n1979) );
XOR2X1TS U2653 ( .A(intDY_EWSW[7]), .B(intDX_EWSW[7]), .Y(n1978) );
XOR2X1TS U2654 ( .A(intDY_EWSW[25]), .B(intDX_EWSW[25]), .Y(n1977) );
XNOR2X1TS U2655 ( .A(intDY_EWSW[17]), .B(intDX_EWSW[17]), .Y(n1984) );
XNOR2X1TS U2656 ( .A(intDY_EWSW[20]), .B(intDX_EWSW[20]), .Y(n1983) );
XNOR2X1TS U2657 ( .A(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n1982) );
XNOR2X1TS U2658 ( .A(intDY_EWSW[22]), .B(intDX_EWSW[22]), .Y(n1981) );
XNOR2X1TS U2659 ( .A(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n1988) );
XNOR2X1TS U2660 ( .A(intDY_EWSW[23]), .B(intDX_EWSW[23]), .Y(n1987) );
XNOR2X1TS U2661 ( .A(intDY_EWSW[10]), .B(intDX_EWSW[10]), .Y(n1986) );
XNOR2X1TS U2662 ( .A(intDY_EWSW[12]), .B(intDX_EWSW[12]), .Y(n1994) );
XNOR2X1TS U2663 ( .A(intDY_EWSW[14]), .B(intDX_EWSW[14]), .Y(n1992) );
XNOR2X1TS U2664 ( .A(intDY_EWSW[24]), .B(intDX_EWSW[24]), .Y(n1998) );
NOR2X2TS U2665 ( .A(n2000), .B(n1999), .Y(n2012) );
XNOR2X1TS U2666 ( .A(n1362), .B(intDX_EWSW[3]), .Y(n2004) );
XNOR2X1TS U2667 ( .A(intDY_EWSW[6]), .B(intDX_EWSW[6]), .Y(n2003) );
XNOR2X1TS U2668 ( .A(intDY_EWSW[16]), .B(intDX_EWSW[16]), .Y(n2001) );
NAND4X2TS U2669 ( .A(n2004), .B(n2003), .C(n2002), .D(n2001), .Y(n2010) );
XNOR2X1TS U2670 ( .A(intDX_EWSW[0]), .B(intDY_EWSW[0]), .Y(n2008) );
XNOR2X1TS U2671 ( .A(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2007) );
XNOR2X1TS U2672 ( .A(intDY_EWSW[28]), .B(intDX_EWSW[28]), .Y(n2006) );
XNOR2X1TS U2673 ( .A(intDY_EWSW[8]), .B(intDX_EWSW[8]), .Y(n2005) );
NAND4X2TS U2674 ( .A(n2008), .B(n2007), .C(n2006), .D(n2005), .Y(n2009) );
INVX2TS U2675 ( .A(n2030), .Y(n2015) );
NOR2X4TS U2676 ( .A(n2015), .B(n2626), .Y(n2029) );
MXI2X1TS U2677 ( .A(n2029), .B(n1299), .S0(n2640), .Y(n2016) );
INVX2TS U2678 ( .A(n2319), .Y(n2019) );
INVX2TS U2679 ( .A(n2021), .Y(n2496) );
NAND2X1TS U2680 ( .A(n2024), .B(n2023), .Y(n2026) );
NAND2X1TS U2681 ( .A(n2350), .B(n2310), .Y(n2025) );
BUFX12TS U2682 ( .A(n2444), .Y(n2447) );
MXI2X4TS U2683 ( .A(n3063), .B(n2616), .S0(n2447), .Y(n464) );
OAI22X4TS U2684 ( .A0(n2881), .A1(n2028), .B0(n974), .B1(n2672), .Y(n499) );
INVX2TS U2685 ( .A(n2029), .Y(n2033) );
NOR2X1TS U2686 ( .A(intDX_EWSW[31]), .B(n2030), .Y(n2031) );
INVX2TS U2687 ( .A(n2152), .Y(n2035) );
NOR2X2TS U2688 ( .A(n1370), .B(n2649), .Y(n2436) );
NOR2X4TS U2689 ( .A(n1294), .B(n907), .Y(n2273) );
OAI21X4TS U2690 ( .A0(n2436), .A1(n2273), .B0(n2275), .Y(n2284) );
NOR2X1TS U2691 ( .A(n1373), .B(n1252), .Y(n2036) );
OAI22X4TS U2692 ( .A0(n2284), .A1(n2036), .B0(n1372), .B1(n1253), .Y(n2154)
);
MXI2X4TS U2693 ( .A(n2038), .B(n2654), .S0(n975), .Y(n763) );
BUFX12TS U2694 ( .A(n2651), .Y(n2494) );
NAND2X2TS U2695 ( .A(n1418), .B(intDY_EWSW[25]), .Y(n2044) );
NAND2X2TS U2696 ( .A(n2378), .B(n1372), .Y(n2042) );
NOR2X4TS U2697 ( .A(n2278), .B(n2393), .Y(n2288) );
NAND2X1TS U2698 ( .A(n2288), .B(n1340), .Y(n2051) );
AOI21X1TS U2699 ( .A0(n2289), .A1(n1340), .B0(n2049), .Y(n2050) );
OAI21X4TS U2700 ( .A0(n2397), .A1(n2051), .B0(n2050), .Y(n2055) );
NAND2BX1TS U2701 ( .AN(DmP_mant_SFG_SWR_signed[11]), .B(n2880), .Y(n2053) );
NAND2X1TS U2702 ( .A(n2053), .B(n2052), .Y(n2054) );
XNOR2X4TS U2703 ( .A(n2055), .B(n2054), .Y(n2056) );
OAI2BB1X4TS U2704 ( .A0N(Raw_mant_NRM_SWR[11]), .A1N(n2481), .B0(n2057), .Y(
n531) );
NAND2X8TS U2705 ( .A(n2060), .B(n974), .Y(n3067) );
NAND2X1TS U2706 ( .A(n1594), .B(n1395), .Y(n2070) );
NAND2X2TS U2707 ( .A(n1361), .B(intDX_EWSW[18]), .Y(n2069) );
NAND2X1TS U2708 ( .A(n2640), .B(n1367), .Y(n2068) );
NAND3X2TS U2709 ( .A(n2070), .B(n2069), .C(n2068), .Y(n735) );
NAND2X2TS U2710 ( .A(n2222), .B(intDX_EWSW[20]), .Y(n2078) );
NAND2X1TS U2711 ( .A(n2640), .B(n1357), .Y(n2077) );
NAND2X2TS U2712 ( .A(n2231), .B(intDX_EWSW[19]), .Y(n2084) );
NAND2X1TS U2713 ( .A(n2640), .B(n1303), .Y(n2083) );
NAND3X2TS U2714 ( .A(n2085), .B(n2084), .C(n2083), .Y(n734) );
NAND2X1TS U2715 ( .A(n2451), .B(n1300), .Y(n2089) );
NAND2X1TS U2716 ( .A(n2119), .B(n1249), .Y(n2116) );
NAND2X2TS U2717 ( .A(n2233), .B(n906), .Y(n2123) );
NAND2X1TS U2718 ( .A(n2233), .B(n1252), .Y(n2132) );
OAI2BB1X1TS U2719 ( .A0N(n2141), .A1N(n2140), .B0(n2139), .Y(n2144) );
NAND2X2TS U2720 ( .A(n2378), .B(DMP_EXP_EWSW[27]), .Y(n2149) );
OAI21X4TS U2721 ( .A0(n2154), .A1(n2153), .B0(n2152), .Y(n2156) );
XOR2X1TS U2722 ( .A(DMP_EXP_EWSW[27]), .B(DmP_EXP_EWSW[27]), .Y(n2155) );
MXI2X4TS U2723 ( .A(n2157), .B(n2614), .S0(n2650), .Y(n762) );
NAND3X2TS U2724 ( .A(n1283), .B(n1282), .C(n1281), .Y(n568) );
NAND2X1TS U2725 ( .A(n2233), .B(n1295), .Y(n2179) );
NAND2X1TS U2726 ( .A(n2206), .B(n1297), .Y(n2191) );
NAND3X2TS U2727 ( .A(n2192), .B(n2193), .C(n2191), .Y(n588) );
NAND2X1TS U2728 ( .A(n2224), .B(n1250), .Y(n2194) );
NAND2X2TS U2729 ( .A(n2224), .B(n1368), .Y(n2200) );
NAND2X1TS U2730 ( .A(n2206), .B(n910), .Y(n2203) );
NAND2X1TS U2731 ( .A(n2451), .B(n1301), .Y(n2219) );
NAND2X2TS U2732 ( .A(n2451), .B(DmP_EXP_EWSW[1]), .Y(n2228) );
NAND2X1TS U2733 ( .A(n2451), .B(n1302), .Y(n2236) );
NAND2X1TS U2734 ( .A(Shift_amount_SHT1_EWR[3]), .B(busy), .Y(n2240) );
NAND2X1TS U2735 ( .A(n2451), .B(n1251), .Y(n2243) );
CLKBUFX3TS U2736 ( .A(n1417), .Y(n2889) );
CLKBUFX3TS U2737 ( .A(n1417), .Y(n2918) );
BUFX3TS U2738 ( .A(n2918), .Y(n2888) );
CLKBUFX3TS U2739 ( .A(n2918), .Y(n2895) );
BUFX3TS U2740 ( .A(n2696), .Y(n2704) );
CLKBUFX3TS U2741 ( .A(n2895), .Y(n2695) );
CLKBUFX2TS U2742 ( .A(n2888), .Y(n2696) );
BUFX3TS U2743 ( .A(n1417), .Y(n2894) );
BUFX3TS U2744 ( .A(n1417), .Y(n2893) );
BUFX3TS U2745 ( .A(n2700), .Y(n2892) );
BUFX3TS U2746 ( .A(n1417), .Y(n2912) );
BUFX3TS U2747 ( .A(n1427), .Y(n2909) );
CLKBUFX3TS U2748 ( .A(n2888), .Y(n2702) );
BUFX3TS U2749 ( .A(n1420), .Y(n2913) );
CLKBUFX3TS U2750 ( .A(n2896), .Y(n2705) );
BUFX3TS U2751 ( .A(n2898), .Y(n2907) );
CLKBUFX3TS U2752 ( .A(n2895), .Y(n2908) );
BUFX3TS U2753 ( .A(n2700), .Y(n2914) );
BUFX3TS U2754 ( .A(n2696), .Y(n2703) );
CLKBUFX3TS U2755 ( .A(n2919), .Y(n2917) );
BUFX3TS U2756 ( .A(n1417), .Y(n2901) );
BUFX3TS U2757 ( .A(n2700), .Y(n2890) );
BUFX3TS U2758 ( .A(n2896), .Y(n2916) );
BUFX3TS U2759 ( .A(n2905), .Y(n2903) );
INVX2TS U2760 ( .A(n2878), .Y(n2246) );
CLKMX2X2TS U2761 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n1431),
.Y(n544) );
CLKMX2X2TS U2762 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1431),
.Y(n616) );
INVX2TS U2763 ( .A(n2879), .Y(n2247) );
CLKMX2X2TS U2764 ( .A(n2247), .B(DMP_exp_NRM_EW[1]), .S0(n2248), .Y(n641) );
CLKMX2X2TS U2765 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n1431),
.Y(n621) );
CLKMX2X2TS U2766 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n2248),
.Y(n646) );
CLKMX2X2TS U2767 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1431),
.Y(n631) );
CLKMX2X2TS U2768 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n1431),
.Y(n611) );
CLKMX2X2TS U2769 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n2248),
.Y(n553) );
OAI21X1TS U2770 ( .A0(busy), .A1(n1415), .B0(n1646), .Y(n829) );
CLKMX2X2TS U2771 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2248),
.Y(n626) );
OAI21X1TS U2772 ( .A0(n1404), .A1(n985), .B0(n1432), .Y(n2972) );
INVX2TS U2773 ( .A(n2249), .Y(n2251) );
NAND2X1TS U2774 ( .A(n2251), .B(n2250), .Y(n2252) );
INVX2TS U2775 ( .A(n2474), .Y(n2255) );
NAND2X1TS U2776 ( .A(n2255), .B(n2473), .Y(n2256) );
INVX2TS U2777 ( .A(n2261), .Y(n2263) );
NAND2X1TS U2778 ( .A(n2263), .B(n2262), .Y(n2264) );
OAI22X1TS U2779 ( .A0(n1821), .A1(n2606), .B0(n1383), .B1(n1403), .Y(n2266)
);
AOI22X1TS U2780 ( .A0(n2489), .A1(DmP_mant_SHT1_SW[2]), .B0(n2339), .B1(
n2461), .Y(n2268) );
AOI22X1TS U2781 ( .A0(n2489), .A1(DmP_mant_SHT1_SW[20]), .B0(n2270), .B1(
n2500), .Y(n2271) );
INVX2TS U2782 ( .A(n2273), .Y(n2274) );
NAND2X1TS U2783 ( .A(n2275), .B(n2274), .Y(n2276) );
XNOR2X1TS U2784 ( .A(n2276), .B(n2436), .Y(n2277) );
MXI2X1TS U2785 ( .A(n2277), .B(n2655), .S0(n975), .Y(n765) );
INVX2TS U2786 ( .A(n2278), .Y(n2280) );
NAND2X1TS U2787 ( .A(n2280), .B(n2279), .Y(n2281) );
XNOR2X1TS U2788 ( .A(n2282), .B(n2281), .Y(Raw_mant_SGF[9]) );
XNOR2X1TS U2789 ( .A(n1372), .B(n1252), .Y(n2283) );
XNOR2X1TS U2790 ( .A(n2284), .B(n2283), .Y(n2285) );
MXI2X1TS U2791 ( .A(n2285), .B(n2600), .S0(n975), .Y(n764) );
MXI2X1TS U2792 ( .A(beg_OP), .B(n2644), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2287) );
NOR2X1TS U2793 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2286) );
INVX2TS U2794 ( .A(n2288), .Y(n2291) );
INVX2TS U2795 ( .A(n2289), .Y(n2290) );
XNOR2X1TS U2796 ( .A(n2294), .B(n2293), .Y(Raw_mant_SGF[10]) );
INVX2TS U2797 ( .A(n2297), .Y(n2295) );
INVX2TS U2798 ( .A(n2306), .Y(n2307) );
NAND2X2TS U2799 ( .A(n1167), .B(n2307), .Y(n2952) );
AOI22X1TS U2800 ( .A0(n2355), .A1(n2319), .B0(n2334), .B1(n2318), .Y(n2320)
);
INVX2TS U2801 ( .A(n2323), .Y(n2734) );
NAND2X1TS U2802 ( .A(n1189), .B(Raw_mant_NRM_SWR[13]), .Y(n2987) );
NAND2X1TS U2803 ( .A(n1189), .B(n1385), .Y(n2951) );
NAND2X1TS U2804 ( .A(n1189), .B(n1650), .Y(n2964) );
NAND2X1TS U2805 ( .A(n1189), .B(Raw_mant_NRM_SWR[7]), .Y(n2930) );
NAND2X1TS U2806 ( .A(n1189), .B(n991), .Y(n2947) );
INVX2TS U2807 ( .A(n2339), .Y(n2340) );
NAND2X1TS U2808 ( .A(n2024), .B(n2483), .Y(n2352) );
NAND2X1TS U2809 ( .A(n2350), .B(n2462), .Y(n2351) );
NAND4X4TS U2810 ( .A(n2351), .B(n2353), .C(n2352), .D(n2354), .Y(n2359) );
NAND2X1TS U2811 ( .A(n1189), .B(Raw_mant_NRM_SWR[11]), .Y(n2942) );
NAND2X2TS U2812 ( .A(n1108), .B(n533), .Y(n2943) );
NAND2X2TS U2813 ( .A(n1108), .B(n2882), .Y(n3006) );
NAND2X2TS U2814 ( .A(n1108), .B(Raw_mant_NRM_SWR[19]), .Y(n3011) );
NAND2X2TS U2815 ( .A(n3067), .B(n2362), .Y(n760) );
NAND2X2TS U2816 ( .A(n3067), .B(n2364), .Y(n758) );
AOI2BB2X1TS U2817 ( .B0(n2365), .B1(n2461), .A0N(n1821), .A1N(n2599), .Y(
n2367) );
INVX2TS U2818 ( .A(n2877), .Y(n2424) );
NAND2X2TS U2819 ( .A(n2231), .B(intDX_EWSW[23]), .Y(n2380) );
CLKMX2X2TS U2820 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(n974), .Y(n552) );
NAND2X1TS U2821 ( .A(n988), .B(DmP_mant_SHT1_SW[16]), .Y(n2384) );
OR2X2TS U2822 ( .A(n2385), .B(DMP_SFG[0]), .Y(n2387) );
MXI2X1TS U2823 ( .A(n2389), .B(final_result_ieee[25]), .S0(n2607), .Y(n2390)
);
NAND2X2TS U2824 ( .A(n3067), .B(n2390), .Y(n759) );
MXI2X1TS U2825 ( .A(n2391), .B(final_result_ieee[23]), .S0(n2607), .Y(n2392)
);
NAND2X2TS U2826 ( .A(n3067), .B(n2392), .Y(n761) );
INVX2TS U2827 ( .A(n2393), .Y(n2395) );
CLKBUFX2TS U2828 ( .A(n2889), .Y(n2698) );
CLKBUFX3TS U2829 ( .A(n2889), .Y(n2699) );
CLKBUFX3TS U2830 ( .A(n2918), .Y(n2906) );
CLKBUFX3TS U2831 ( .A(n2889), .Y(n2697) );
BUFX3TS U2832 ( .A(n2889), .Y(n2904) );
CLKBUFX3TS U2833 ( .A(n2918), .Y(n2887) );
BUFX3TS U2834 ( .A(n2889), .Y(n2915) );
INVX2TS U2835 ( .A(final_result_ieee[14]), .Y(n3048) );
INVX2TS U2836 ( .A(final_result_ieee[8]), .Y(n3037) );
INVX2TS U2837 ( .A(final_result_ieee[9]), .Y(n3039) );
INVX2TS U2838 ( .A(final_result_ieee[22]), .Y(n3062) );
INVX2TS U2839 ( .A(final_result_ieee[18]), .Y(n3056) );
INVX2TS U2840 ( .A(final_result_ieee[15]), .Y(n3050) );
INVX2TS U2841 ( .A(final_result_ieee[12]), .Y(n3044) );
INVX2TS U2842 ( .A(final_result_ieee[11]), .Y(n3042) );
INVX2TS U2843 ( .A(final_result_ieee[7]), .Y(n3035) );
INVX2TS U2844 ( .A(final_result_ieee[16]), .Y(n3052) );
INVX2TS U2845 ( .A(final_result_ieee[13]), .Y(n3046) );
INVX2TS U2846 ( .A(final_result_ieee[1]), .Y(n3026) );
INVX2TS U2847 ( .A(final_result_ieee[20]), .Y(n3058) );
INVX2TS U2848 ( .A(final_result_ieee[5]), .Y(n3031) );
INVX2TS U2849 ( .A(final_result_ieee[21]), .Y(n3060) );
INVX2TS U2850 ( .A(final_result_ieee[0]), .Y(n3024) );
INVX2TS U2851 ( .A(final_result_ieee[6]), .Y(n3033) );
INVX2TS U2852 ( .A(final_result_ieee[2]), .Y(n3028) );
INVX2TS U2853 ( .A(final_result_ieee[17]), .Y(n3054) );
INVX2TS U2854 ( .A(n2405), .Y(n2407) );
NAND2X1TS U2855 ( .A(n2410), .B(n2409), .Y(n2411) );
NOR2X1TS U2856 ( .A(n2500), .B(n2600), .Y(n2414) );
NAND2X2TS U2857 ( .A(n2422), .B(n2421), .Y(n2423) );
NAND2X2TS U2858 ( .A(n988), .B(DmP_mant_SHT1_SW[20]), .Y(n3021) );
NAND2X2TS U2859 ( .A(n1266), .B(n2802), .Y(final_result_ieee[28]) );
NAND2X2TS U2860 ( .A(n1266), .B(n2832), .Y(final_result_ieee[29]) );
NAND2X2TS U2861 ( .A(n1266), .B(n2780), .Y(final_result_ieee[27]) );
CLKMX2X3TS U2862 ( .A(DMP_SHT1_EWSW[7]), .B(DMP_EXP_EWSW[7]), .S0(n2431),
.Y(n698) );
CLKMX2X3TS U2863 ( .A(DMP_SHT1_EWSW[3]), .B(DMP_EXP_EWSW[3]), .S0(n2431),
.Y(n710) );
CLKMX2X2TS U2864 ( .A(DMP_SHT1_EWSW[9]), .B(DMP_EXP_EWSW[9]), .S0(n2431),
.Y(n692) );
CLKMX2X3TS U2865 ( .A(DMP_SHT1_EWSW[4]), .B(DMP_EXP_EWSW[4]), .S0(n2431),
.Y(n707) );
CLKMX2X3TS U2866 ( .A(DMP_SHT1_EWSW[11]), .B(n909), .S0(n2431), .Y(n686) );
CLKMX2X3TS U2867 ( .A(DMP_SHT1_EWSW[8]), .B(DMP_EXP_EWSW[8]), .S0(n2431),
.Y(n695) );
CLKMX2X3TS U2868 ( .A(DMP_SHT1_EWSW[6]), .B(n919), .S0(n2431), .Y(n701) );
CLKMX2X3TS U2869 ( .A(DMP_SHT1_EWSW[10]), .B(n905), .S0(n2431), .Y(n689) );
CLKMX2X3TS U2870 ( .A(DMP_SHT1_EWSW[5]), .B(DMP_EXP_EWSW[5]), .S0(n2431),
.Y(n704) );
CLKMX2X2TS U2871 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n2433), .Y(
n557) );
CLKMX2X2TS U2872 ( .A(DmP_mant_SHT1_SW[22]), .B(n1295), .S0(n2433), .Y(n565)
);
CLKMX2X2TS U2873 ( .A(DMP_SHT1_EWSW[1]), .B(DMP_EXP_EWSW[1]), .S0(n2433),
.Y(n716) );
CLKMX2X2TS U2874 ( .A(DmP_mant_SHT1_SW[12]), .B(DmP_EXP_EWSW[12]), .S0(n2432), .Y(n585) );
XNOR2X1TS U2875 ( .A(n2876), .B(DmP_mant_SFG_SWR[1]), .Y(n2434) );
MXI2X1TS U2876 ( .A(n2565), .B(n2434), .S0(Shift_reg_FLAGS_7[2]), .Y(n541)
);
CLKMX2X2TS U2877 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[23]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n647) );
CLKMX2X2TS U2878 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(
Shift_reg_FLAGS_7[2]), .Y(n545) );
CLKMX2X2TS U2879 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[26]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n632) );
CLKMX2X2TS U2880 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[24]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n642) );
CLKMX2X2TS U2881 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(
Shift_reg_FLAGS_7[2]), .Y(n554) );
CLKMX2X2TS U2882 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[29]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n617) );
MXI2X1TS U2883 ( .A(n2653), .B(n1373), .S0(n2437), .Y(n640) );
MXI2X1TS U2884 ( .A(n2445), .B(n2653), .S0(busy), .Y(n639) );
NOR2X1TS U2885 ( .A(n2436), .B(n2435), .Y(n2438) );
MXI2X1TS U2886 ( .A(n2537), .B(n2438), .S0(n2437), .Y(n766) );
CLKMX2X2TS U2887 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n2440),
.Y(n644) );
CLKMX2X2TS U2888 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n2440),
.Y(n679) );
CLKMX2X2TS U2889 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n2440),
.Y(n682) );
CLKMX2X2TS U2890 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(n2440),
.Y(n634) );
CLKMX2X2TS U2891 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(n2440),
.Y(n619) );
CLKMX2X2TS U2892 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(n2440),
.Y(n624) );
CLKMX2X2TS U2893 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n2440),
.Y(n649) );
CLKMX2X3TS U2894 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(n924), .Y(n550)
);
CLKMX2X2TS U2895 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(busy), .Y(
n556) );
CLKMX2X2TS U2896 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(busy),
.Y(n614) );
CLKMX2X2TS U2897 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(busy),
.Y(n667) );
CLKMX2X2TS U2898 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(busy),
.Y(n673) );
CLKMX2X2TS U2899 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(busy), .Y(
n547) );
XNOR2X1TS U2900 ( .A(n2876), .B(DmP_mant_SFG_SWR[0]), .Y(n2442) );
MXI2X1TS U2901 ( .A(n2531), .B(n2442), .S0(Shift_reg_FLAGS_7[2]), .Y(n542)
);
MXI2X1TS U2902 ( .A(n2535), .B(n2618), .S0(n900), .Y(n717) );
MXI2X1TS U2903 ( .A(n2533), .B(n2617), .S0(n900), .Y(n711) );
MXI2X1TS U2904 ( .A(n2534), .B(n2619), .S0(n900), .Y(n714) );
BUFX12TS U2905 ( .A(n2444), .Y(n2446) );
MXI2X1TS U2906 ( .A(n2545), .B(n2688), .S0(n2446), .Y(n648) );
MXI2X1TS U2907 ( .A(n2544), .B(n2687), .S0(n2446), .Y(n643) );
MXI2X1TS U2908 ( .A(n2539), .B(n2681), .S0(n2446), .Y(n613) );
MXI2X1TS U2909 ( .A(n2540), .B(n2682), .S0(n2446), .Y(n618) );
MXI2X1TS U2910 ( .A(n2543), .B(n2685), .S0(n2446), .Y(n633) );
MXI2X1TS U2911 ( .A(n2542), .B(n2684), .S0(n2446), .Y(n628) );
MXI2X1TS U2912 ( .A(n2541), .B(n2683), .S0(n2446), .Y(n623) );
MXI2X1TS U2913 ( .A(n2445), .B(n2686), .S0(n2446), .Y(n638) );
MXI2X1TS U2914 ( .A(n2546), .B(n2677), .S0(n2446), .Y(n678) );
MXI2X1TS U2915 ( .A(n2563), .B(n2634), .S0(n2447), .Y(n675) );
MXI2X1TS U2916 ( .A(n2559), .B(n2633), .S0(n2447), .Y(n663) );
MXI2X1TS U2917 ( .A(n2556), .B(n2675), .S0(n2447), .Y(n654) );
MXI2X1TS U2918 ( .A(n2561), .B(n2635), .S0(n2447), .Y(n669) );
MXI2X1TS U2919 ( .A(n2557), .B(n2636), .S0(n2447), .Y(n657) );
MXI2X1TS U2920 ( .A(n2562), .B(n2638), .S0(n2447), .Y(n672) );
MXI2X1TS U2921 ( .A(n2560), .B(n2637), .S0(n2447), .Y(n666) );
MXI2X1TS U2922 ( .A(n2558), .B(n2676), .S0(n2447), .Y(n660) );
MXI2X1TS U2923 ( .A(n2564), .B(n2691), .S0(n2448), .Y(n555) );
MXI2X1TS U2924 ( .A(n2449), .B(n2690), .S0(n2448), .Y(n546) );
OAI2BB1X1TS U2925 ( .A0N(OP_FLAG_EXP), .A1N(n2451), .B0(n2450), .Y(n722) );
CLKMX2X2TS U2926 ( .A(DMP_SHT1_EWSW[13]), .B(DMP_EXP_EWSW[13]), .S0(
Shift_reg_FLAGS_7_5), .Y(n680) );
CLKMX2X2TS U2927 ( .A(DMP_SHT1_EWSW[29]), .B(n1360), .S0(Shift_reg_FLAGS_7_5), .Y(n620) );
CLKMX2X2TS U2928 ( .A(DMP_SHT1_EWSW[28]), .B(n1251), .S0(Shift_reg_FLAGS_7_5), .Y(n625) );
CLKMX2X2TS U2929 ( .A(DMP_SHT1_EWSW[12]), .B(n741), .S0(Shift_reg_FLAGS_7_5),
.Y(n683) );
CLKMX2X3TS U2930 ( .A(DmP_mant_SHT1_SW[6]), .B(DmP_EXP_EWSW[6]), .S0(n2452),
.Y(n597) );
CLKMX2X3TS U2931 ( .A(DmP_mant_SHT1_SW[4]), .B(n921), .S0(n2452), .Y(n601)
);
CLKMX2X3TS U2932 ( .A(DmP_mant_SHT1_SW[8]), .B(DmP_EXP_EWSW[8]), .S0(n2452),
.Y(n593) );
CLKMX2X3TS U2933 ( .A(DmP_mant_SHT1_SW[10]), .B(DmP_EXP_EWSW[10]), .S0(n2452), .Y(n589) );
CLKMX2X3TS U2934 ( .A(DmP_mant_SHT1_SW[3]), .B(n914), .S0(n2452), .Y(n603)
);
AOI2BB2X1TS U2935 ( .B0(n2453), .B1(n2500), .A0N(n1432), .A1N(n2601), .Y(
n2992) );
AOI2BB2X1TS U2936 ( .B0(n2454), .B1(n2461), .A0N(n1432), .A1N(n2629), .Y(
n3019) );
AOI2BB2X1TS U2937 ( .B0(n2455), .B1(n2500), .A0N(n1432), .A1N(n2039), .Y(
n2966) );
OAI22X1TS U2938 ( .A0(n1432), .A1(n2608), .B0(n2456), .B1(n1404), .Y(n3014)
);
INVX2TS U2939 ( .A(n2462), .Y(n2463) );
OAI22X1TS U2940 ( .A0(n2497), .A1(n2603), .B0(n2463), .B1(n1413), .Y(n2464)
);
AOI21X1TS U2941 ( .A0(n2472), .A1(DmP_mant_SHT1_SW[6]), .B0(n2464), .Y(n2949) );
AOI2BB2X1TS U2942 ( .B0(DmP_mant_SHT1_SW[13]), .B1(n2472), .A0N(n1411),
.A1N(n2605), .Y(n2965) );
INVX2TS U2943 ( .A(n2465), .Y(n2466) );
OAI22X1TS U2944 ( .A0(n1821), .A1(n2470), .B0(n2469), .B1(n1403), .Y(n2471)
);
AOI21X1TS U2945 ( .A0(n2472), .A1(DmP_mant_SHT1_SW[18]), .B0(n2471), .Y(
n2955) );
CLKMX2X2TS U2946 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n2924),
.Y(n652) );
CLKMX2X2TS U2947 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n2924),
.Y(n718) );
CLKMX2X2TS U2948 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n2924),
.Y(n658) );
CLKMX2X2TS U2949 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n2924),
.Y(n661) );
CLKMX2X2TS U2950 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n2924),
.Y(n670) );
CLKMX2X2TS U2951 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n2924),
.Y(n676) );
CLKMX2X2TS U2952 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n2924),
.Y(n655) );
CLKMX2X2TS U2953 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n2924),
.Y(n664) );
CLKMX2X2TS U2954 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n2924),
.Y(n715) );
CLKMX2X2TS U2955 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n2924),
.Y(n712) );
INVX2TS U2956 ( .A(n2476), .Y(n2478) );
NAND2X1TS U2957 ( .A(n2478), .B(n2477), .Y(n2479) );
XNOR2X4TS U2958 ( .A(n2480), .B(n2479), .Y(n2482) );
INVX2TS U2959 ( .A(n2483), .Y(n2484) );
OAI22X1TS U2960 ( .A0(n1821), .A1(n2604), .B0(n2484), .B1(n1413), .Y(n2485)
);
AOI21X1TS U2961 ( .A0(n2489), .A1(DmP_mant_SHT1_SW[10]), .B0(n2485), .Y(
n2953) );
OAI22X1TS U2962 ( .A0(n1432), .A1(n2602), .B0(n2487), .B1(n1403), .Y(n2488)
);
INVX2TS U2963 ( .A(n2490), .Y(n2492) );
NAND2X1TS U2964 ( .A(n2492), .B(n2491), .Y(n871) );
MXI2X1TS U2965 ( .A(n1560), .B(n2922), .S0(n2503), .Y(n863) );
MXI2X1TS U2966 ( .A(n2481), .B(n1560), .S0(n2503), .Y(n864) );
MXI2X1TS U2967 ( .A(n2640), .B(n975), .S0(n2503), .Y(n868) );
OAI22X1TS U2968 ( .A0(n2497), .A1(n2610), .B0(n2496), .B1(n1403), .Y(n2498)
);
AOI21X1TS U2969 ( .A0(n2885), .A1(n1650), .B0(n2498), .Y(n2944) );
MXI2X1TS U2970 ( .A(n2925), .B(n2532), .S0(n2503), .Y(n866) );
AOI22X1TS U2971 ( .A0(n2885), .A1(n898), .B0(n2500), .B1(n2499), .Y(n2963)
);
CLKINVX1TS U2972 ( .A(n2502), .Y(n2504) );
MXI2X1TS U2973 ( .A(n2504), .B(n2640), .S0(n2503), .Y(n869) );
MXI2X1TS U2974 ( .A(n2505), .B(final_result_ieee[28]), .S0(n2607), .Y(n3065)
);
INVX2TS U2975 ( .A(n2506), .Y(n2507) );
NOR2X1TS U2976 ( .A(n2507), .B(DMP_exp_NRM2_EW[5]), .Y(n2508) );
XNOR2X2TS U2977 ( .A(n2510), .B(DMP_exp_NRM2_EW[6]), .Y(n2511) );
MXI2X1TS U2978 ( .A(n2511), .B(final_result_ieee[29]), .S0(n2607), .Y(n3066)
);
CLKMX2X2TS U2979 ( .A(Data_Y[30]), .B(intDY_EWSW[30]), .S0(n2519), .Y(n798)
);
CLKMX2X2TS U2980 ( .A(Data_Y[28]), .B(intDY_EWSW[28]), .S0(n2515), .Y(n800)
);
CLKMX2X2TS U2981 ( .A(Data_Y[29]), .B(intDY_EWSW[29]), .S0(n2515), .Y(n799)
);
CLKMX2X2TS U2982 ( .A(Data_Y[13]), .B(intDY_EWSW[13]), .S0(n2513), .Y(n815)
);
CLKMX2X2TS U2983 ( .A(Data_Y[27]), .B(intDY_EWSW[27]), .S0(n2515), .Y(n801)
);
CLKMX2X2TS U2984 ( .A(Data_Y[17]), .B(intDY_EWSW[17]), .S0(n2513), .Y(n811)
);
CLKMX2X2TS U2985 ( .A(Data_Y[19]), .B(intDY_EWSW[19]), .S0(n2513), .Y(n809)
);
CLKMX2X2TS U2986 ( .A(Data_Y[25]), .B(intDY_EWSW[25]), .S0(n2515), .Y(n803)
);
CLKMX2X2TS U2987 ( .A(Data_Y[9]), .B(intDY_EWSW[9]), .S0(n2514), .Y(n819) );
CLKMX2X2TS U2988 ( .A(Data_Y[26]), .B(intDY_EWSW[26]), .S0(n2515), .Y(n802)
);
CLKMX2X2TS U2989 ( .A(Data_Y[20]), .B(intDY_EWSW[20]), .S0(n2513), .Y(n808)
);
CLKMX2X2TS U2990 ( .A(Data_Y[6]), .B(intDY_EWSW[6]), .S0(n2514), .Y(n822) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk1.tcl_ACAIIN16Q8_syn.sdf");
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : xaw2verilog
// / / Filename : relojes.v
// /___/ /\ Timestamp : 07/10/2016 17:24:36
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle A:/gitzxuno/cores/test/test_sram_y_video/ipcore_dir/relojes.xaw -st relojes.v
//Design Name: relojes
//Device: xc3s250e-4tq144
//
// Module relojes
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.92 ns
`timescale 1ns / 1ps
module relojes(CLKIN_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(10.0), .CLKFX_DIVIDE(25),
.CLKFX_MULTIPLY(14), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
endmodule
|
//IS61WV102416BLL-10 Simulation Model
// `define OEb
`timescale 1ns/10ps
module is61wv102416bll (A, IO, CE_, OE_, WE_, LB_, UB_);
parameter SPEED_RANK = 10;
/*
generate
if(SPEED_RANK == 8)begin
localparam dqbits = 16;
localparam memdepth = 1048576; //1M bit
localparam addbits = 20;
localparam Taa = 8;
localparam Toha = 3;
localparam Thzce = 3;
localparam Tsa = 0;
localparam Thzwe = 4;
end
else if(SPEED_RANK == 10)begin
localparam dqbits = 16;
localparam memdepth = 1048576; //1M bit
localparam addbits = 20;
localparam Taa = 10;
localparam Toha = 3;
localparam Thzce = 4;
localparam Tsa = 0;
localparam Thzwe = 5;
end
else begin //20ns
localparam dqbits = 16;
localparam memdepth = 1048576; //1M bit
localparam addbits = 20;
localparam Taa = 20;
localparam Toha = 3;
localparam Thzce = 8;
localparam Tsa = 0;
localparam Thzwe = 9;
end
endgenerate
*/
localparam dqbits = 16;
localparam memdepth = 1048576; //1M bit
localparam addbits = 20;
localparam Taa = 10;
localparam Toha = 3;
localparam Thzce = 4;
localparam Tsa = 0;
localparam Thzwe = 5;
/*
parameter dqbits = 16;
parameter memdepth = 1048576; //1M bit
parameter addbits = 20;
parameter Taa = 10;
parameter Toha = 3;
parameter Thzce = 4;
parameter Tsa = 0;
parameter Thzwe = 5;
*/
input CE_, OE_, WE_, LB_, UB_;
input [(addbits - 1) : 0] A;
inout [(dqbits - 1) : 0] IO;
wire [(dqbits - 1) : 0] dout;
reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
wire r_en = WE_ & (~CE_) & (~OE_);
wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_));
assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;
assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A];
assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
/*
int i;
initial
#0 begin
for(i = 0; i < 640*480; i = i + 1)begin
if(i < (640*480)/2)begin
{bank1[i], bank0[i]} = {5'hFF, 6'h00, 5'h00};
end
else begin
{bank1[i], bank0[i]} = {5'h0, 6'h00, 5'hFF};
end
end
end
*/
always @(A or w_en)
begin
#Tsa
if (w_en)
#Thzwe
begin
bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
end
end
specify
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 8,
tPWE1 = 8,
tPBW = 8;
$setup (A, negedge CE_, tSA);
$setup (A, posedge CE_, tAW);
$setup (IO, posedge CE_, tSD);
$setup (A, negedge WE_, tSA);
$setup (IO, posedge WE_, tSD);
$setup (A, negedge LB_, tSA);
$setup (A, negedge UB_, tSA);
$width (negedge CE_, tSCE);
$width (negedge LB_, tPBW);
$width (negedge UB_, tPBW);
`ifdef OEb
$width (negedge WE_, tPWE1);
`else
$width (negedge WE_, tPWE2);
`endif
endspecify
endmodule
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs.
As of Coq 8.4 [admit] is in the standard library, but we include
it here for backwards compatibility.
*)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool := negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool := andb (andb b1 b2) b3.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| 0 => 1
| S n => mult (S n) (factorial n)
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite <- H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o.
intros H1 H2.
rewrite -> H1.
rewrite <- H2.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m.
intros H.
rewrite -> plus_1_l.
rewrite <- H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n as [|n'].
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros.
rewrite -> H.
rewrite -> H.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros.
rewrite -> H.
rewrite -> H.
destruct b.
reflexivity.
reflexivity.
Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b.
destruct c.
reflexivity.
simpl.
intros H1.
rewrite H1.
reflexivity.
simpl.
intro H2.
rewrite H2.
reflexivity.
Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive bin : Type :=
| Z : bin
| Twice : bin -> bin
| OneTwice : bin -> bin.
Fixpoint incr (b : bin) : bin :=
match b with
| Z => OneTwice Z
| Twice b => OneTwice b
| OneTwice b => Twice (incr b)
end.
Fixpoint bin_to_nat (b : bin) : nat :=
match b with
| Z => 0
| Twice b => 2 * (bin_to_nat b)
| OneTwice b => 1 + 2 * (bin_to_nat b)
end.
Example test_bin_to_nat0: bin_to_nat (Twice Z) = 0.
Proof. reflexivity. Qed.
Example test_bin_to_nat1: bin_to_nat (OneTwice Z) = 1.
Proof. reflexivity. Qed.
Example test_bin_to_nat2: bin_to_nat (Twice (OneTwice Z)) = 2.
Proof. reflexivity. Qed.
Example test_bin_to_nat3: bin_to_nat (OneTwice (OneTwice Z)) = 3.
Proof. reflexivity. Qed.
Example test_incr_1: bin_to_nat (incr (OneTwice (OneTwice Z))) = 4.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(**
Fixpoint decreasing (a : nat) (b : nat) : nat :=
match a with
| 0 => match b with
| 0 => 0
| S b' => decreasing b' a
end
| S a' => decreasing a' b
end.
**)
(** [decreasing] first decreases on 1st argument then 2nd argument **)
(** [] *)
(* $Date: 2013-12-03 07:45:41 -0500 (Tue, 03 Dec 2013) $ *)
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// --
// TLB management unit for the ZAP processor. The TLB units use single cycle --
// clearing memories since TLBs are shallow. --
// --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_tlb #(
parameter LPAGE_TLB_ENTRIES = 8,
parameter SPAGE_TLB_ENTRIES = 8,
parameter SECTION_TLB_ENTRIES = 8,
parameter FPAGE_TLB_ENTRIES = 8
) (
// Clock and reset.
input wire i_clk,
input wire i_reset,
// From cache FSM (processor)
input wire [31:0] i_address,
input wire [31:0] i_address_nxt,
input wire i_rd,
input wire i_wr,
// CPSR, SR, DAC register.
input wire [31:0] i_cpsr,
input wire [1:0] i_sr,
input wire [31:0] i_dac_reg,
input wire [31:0] i_baddr,
// From CP15.
input wire i_mmu_en,
input wire i_inv,
// To cache FSM.
output wire [31:0] o_phy_addr,
output wire [7:0] o_fsr,
output wire [31:0] o_far,
output wire o_fault,
output wire o_cacheable,
output wire o_busy,
// Wishbone memory interface - Needs to go through some OR gates.
output wire o_wb_stb_nxt,
output wire o_wb_cyc_nxt,
output wire [31:0] o_wb_adr_nxt,
output wire o_wb_wen_nxt,
output wire [3:0] o_wb_sel_nxt,
input wire [31:0] i_wb_dat,
output wire [31:0] o_wb_dat_nxt,
input wire i_wb_ack
);
// ----------------------------------------------------------------------------
assign o_wb_dat_nxt = 32'd0;
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
wire [`SECTION_TLB_WDT-1:0] setlb_wdata, setlb_rdata;
wire [`LPAGE_TLB_WDT-1:0] lptlb_wdata, lptlb_rdata;
wire [`SPAGE_TLB_WDT-1:0] sptlb_wdata, sptlb_rdata;
wire [`FPAGE_TLB_WDT-1:0] fptlb_wdata, fptlb_rdata;
wire sptlb_wen, lptlb_wen, setlb_wen;
wire sptlb_ren, lptlb_ren, setlb_ren;
wire fptlb_ren, fptlb_wen;
wire walk;
wire [7:0] fsr;
wire [31:0] far;
wire cacheable;
wire [31:0] phy_addr;
wire [31:0] tlb_address;
// ----------------------------------------------------------------------------
zap_mem_inv_block #(.WIDTH(`SECTION_TLB_WDT), .DEPTH(SECTION_TLB_ENTRIES))
u_section_tlb (
.i_clk (i_clk),
.i_reset (i_reset),
.i_wdata (setlb_wdata),
.i_wen (setlb_wen),
.i_ren (1'd1),
.i_inv (i_inv | !i_mmu_en),
.i_raddr (i_address_nxt[`VA__SECTION_INDEX]),
.i_waddr (tlb_address[`VA__SECTION_INDEX]),
.o_rdata (setlb_rdata),
.o_rdav (setlb_ren)
);
// ----------------------------------------------------------------------------
zap_mem_inv_block #(.WIDTH(`LPAGE_TLB_WDT), .DEPTH(LPAGE_TLB_ENTRIES))
u_lpage_tlb (
.i_clk (i_clk),
.i_reset (i_reset),
.i_wdata (lptlb_wdata),
.i_wen (lptlb_wen),
.i_ren (1'd1),
.i_inv (i_inv | !i_mmu_en),
.i_raddr (i_address_nxt[`VA__LPAGE_INDEX]),
.i_waddr (tlb_address[`VA__LPAGE_INDEX]),
.o_rdata (lptlb_rdata),
.o_rdav (lptlb_ren)
);
// ----------------------------------------------------------------------------
zap_mem_inv_block #(.WIDTH(`SPAGE_TLB_WDT), .DEPTH(SPAGE_TLB_ENTRIES))
u_spage_tlb (
.i_clk (i_clk),
.i_reset (i_reset),
.i_wdata (sptlb_wdata),
.i_wen (sptlb_wen),
.i_ren (1'd1),
.i_inv (i_inv | !i_mmu_en),
.i_raddr (i_address_nxt[`VA__SPAGE_INDEX]),
.i_waddr (tlb_address[`VA__SPAGE_INDEX]),
.o_rdata (sptlb_rdata),
.o_rdav (sptlb_ren)
);
// ----------------------------------------------------------------------------
zap_mem_inv_block #(.WIDTH(`FPAGE_TLB_WDT), .DEPTH(FPAGE_TLB_ENTRIES))
u_fpage_tlb (
.i_clk (i_clk),
.i_reset (i_reset),
.i_wdata (fptlb_wdata),
.i_wen (fptlb_wen),
.i_ren (1'd1),
.i_inv (i_inv | !i_mmu_en),
.i_raddr (i_address_nxt[`VA__FPAGE_INDEX]),
.i_waddr (tlb_address[`VA__FPAGE_INDEX]),
.o_rdata (fptlb_rdata),
.o_rdav (fptlb_ren)
);
// ----------------------------------------------------------------------------
zap_tlb_check #(
.LPAGE_TLB_ENTRIES(LPAGE_TLB_ENTRIES),
.SPAGE_TLB_ENTRIES(SPAGE_TLB_ENTRIES),
.SECTION_TLB_ENTRIES(SECTION_TLB_ENTRIES),
.FPAGE_TLB_ENTRIES(FPAGE_TLB_ENTRIES)
)
u_zap_tlb_check (
.i_mmu_en (i_mmu_en),
.i_va (i_address),
.i_rd (i_rd),
.i_wr (i_wr),
.i_cpsr (i_cpsr),
.i_sr (i_sr),
.i_dac_reg (i_dac_reg),
.i_sptlb_rdata (sptlb_rdata),
.i_sptlb_rdav (sptlb_ren),
.i_lptlb_rdata (lptlb_rdata),
.i_lptlb_rdav (lptlb_ren),
.i_setlb_rdata (setlb_rdata),
.i_setlb_rdav (setlb_ren),
.i_fptlb_rdata (fptlb_rdata),
.i_fptlb_rdav (fptlb_ren),
.o_walk (walk),
.o_fsr (fsr),
.o_far (far),
.o_cacheable (cacheable),
.o_phy_addr (phy_addr)
);
// ----------------------------------------------------------------------------
zap_tlb_fsm #(
.LPAGE_TLB_ENTRIES (LPAGE_TLB_ENTRIES),
.SPAGE_TLB_ENTRIES (SPAGE_TLB_ENTRIES),
.SECTION_TLB_ENTRIES (SECTION_TLB_ENTRIES),
.FPAGE_TLB_ENTRIES (FPAGE_TLB_ENTRIES)
) u_zap_tlb_fsm (
.o_unused_ok (), // UNCONNECTED. For lint.
.i_clk (i_clk),
.i_reset (i_reset),
.i_mmu_en (i_mmu_en),
.i_baddr (i_baddr),
.i_address (i_address),
.i_walk (walk),
.i_fsr (fsr),
.i_far (far),
.i_cacheable (cacheable),
.i_phy_addr (phy_addr),
.o_fsr (o_fsr),
.o_far (o_far),
.o_fault (o_fault),
.o_phy_addr (o_phy_addr),
.o_cacheable (o_cacheable),
.o_busy (o_busy),
.o_setlb_wdata (setlb_wdata),
.o_setlb_wen (setlb_wen),
.o_sptlb_wdata (sptlb_wdata),
.o_sptlb_wen (sptlb_wen),
.o_lptlb_wdata (lptlb_wdata),
.o_lptlb_wen (lptlb_wen),
.o_fptlb_wdata (fptlb_wdata),
.o_fptlb_wen (fptlb_wen),
.o_address (tlb_address),
.o_wb_cyc (),
.o_wb_stb (),
.o_wb_wen (o_wb_wen_nxt),
.o_wb_sel (),
.o_wb_adr (),
.i_wb_dat (i_wb_dat),
.i_wb_ack (i_wb_ack),
.o_wb_sel_nxt (o_wb_sel_nxt),
.o_wb_cyc_nxt (o_wb_cyc_nxt),
.o_wb_stb_nxt (o_wb_stb_nxt),
.o_wb_adr_nxt (o_wb_adr_nxt)
);
// ----------------------------------------------------------------------------
endmodule
`default_nettype wire
|
module not_32(
input [31:0] a, //input value
output [31:0] out //output value
);
//output is the inverse of a
assign out[0] = !a[0];
assign out[1] = !a[1];
assign out[2] = !a[2];
assign out[3] = !a[3];
assign out[4] = !a[4];
assign out[5] = !a[5];
assign out[6] = !a[6];
assign out[7] = !a[7];
assign out[8] = !a[8];
assign out[9] = !a[9];
assign out[10] = !a[10];
assign out[11] = !a[11];
assign out[12] = !a[12];
assign out[13] = !a[13];
assign out[14] = !a[14];
assign out[15] = !a[15];
assign out[16] = !a[16];
assign out[17] = !a[17];
assign out[18] = !a[18];
assign out[19] = !a[19];
assign out[20] = !a[20];
assign out[21] = !a[21];
assign out[22] = !a[22];
assign out[23] = !a[23];
assign out[24] = !a[24];
assign out[25] = !a[25];
assign out[26] = !a[26];
assign out[27] = !a[27];
assign out[28] = !a[28];
assign out[29] = !a[29];
assign out[30] = !a[30];
assign out[31] = !a[31];
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_maccontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_maccontrol.v,v $
// Revision 1.7 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.6 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.5 2002/11/21 00:14:39 mohor
// TxDone and TxAbort changed so they're not propagated to the wishbone
// module when control frame is transmitted.
//
// Revision 1.4 2002/11/19 17:37:32 mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/07/03 12:51:54 mohor
// Initial release of the MAC Control module.
//
//
//
//
`include "timescale.v"
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input MRxClk; // Receive clock (from PHY)
input TxReset; // Transmit reset
input RxReset; // Receive reset
input TPauseRq; // Transmit control frame (from host)
input [7:0] TxDataIn; // Transmit packet data byte (from host)
input TxStartFrmIn; // Transmit packet start frame input (from host)
input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
input TxEndFrmIn; // Transmit packet end frame input (from host)
input TxDoneIn; // Transmit packet done (from TxEthMAC)
input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
input PadIn; // Padding (input from registers)
input CrcEnIn; // Crc append (input from registers)
input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
input RxValid; // Received a valid packet
input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
input ReceivedPacketGood; // Received packet is good
input ReceivedLengthOK; // Length of the received packet is OK
input TxFlow; // Tx flow control (from registers)
input RxFlow; // Rx flow control (from registers)
input DlyCrcEn; // Delayed CRC enabled (from registers)
input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
input [47:0] MAC; // MAC address (from registers)
input RxStatusWriteLatched_sync2;
input r_PassAll;
output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
output TxDoneOut; // Transmit packet done (to host)
output TxAbortOut; // Transmit packet aborted (to host)
output TxUsedDataOut; // Transmit packet used data (to host)
output PadOut; // Padding (output to TxEthMAC)
output CrcEnOut; // Crc append (output to TxEthMAC)
output WillSendControlFrame;
output TxCtrlEndFrm;
output ReceivedPauseFrm;
output ControlFrmAddressOK;
output SetPauseTimer;
reg TxUsedDataOutDetected;
reg TxAbortInLatched;
reg TxDoneInLatched;
reg MuxedDone;
reg MuxedAbort;
wire Pause;
wire TxCtrlStartFrm;
wire [7:0] ControlData;
wire CtrlMux;
wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
wire BlockTxDone;
// Signal TxUsedDataOut was detected (a transfer is already in progress)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxDoneIn | TxAbortIn)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxUsedDataOut)
TxUsedDataOutDetected <= #Tp 1'b1;
end
// Latching variables
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
TxAbortInLatched <= #Tp 1'b0;
TxDoneInLatched <= #Tp 1'b0;
end
else
begin
TxAbortInLatched <= #Tp TxAbortIn;
TxDoneInLatched <= #Tp TxDoneIn;
end
end
// Generating muxed abort signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedAbort <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedAbort <= #Tp 1'b0;
else
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
MuxedAbort <= #Tp 1'b1;
end
// Generating muxed done signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedDone <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedDone <= #Tp 1'b0;
else
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
MuxedDone <= #Tp 1'b1;
end
// TxDoneOut
assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
// TxAbortOut
assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
// TxUsedDataOut
assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
// TxStartFrmOut
assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
// TxEndFrmOut
assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
// TxDataOut[7:0]
assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
// PadOut
assign PadOut = PadIn | SendingCtrlFrm;
// CrcEnOut
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
// Connecting receivecontrol module
eth_receivecontrol receivecontrol1
(
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
);
eth_transmitcontrol transmitcontrol1
(
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
.TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
.MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
.CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:32:04 03/31/2015
// Design Name: zlozony
// Module Name: C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/src/tb_zlozony.v
// Project Name: zlozony
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: zlozony
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_zlozony;
// Inputs
reg clk;
reg ce;
reg [17:0] a;
reg [7:0] b;
reg [11:0] c;
reg [7:0] d;
reg [13:0] e;
reg [18:0] f;
// Outputs
wire [36:0] y;
// Instantiate the Unit Under Test (UUT)
zlozony uut (
.clk(clk),
.ce(ce),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.y(y)
);
integer i;
initial begin
// Initialize Inputs
clk = 0;
ce = 1;
//Sta³e wygenerowane w matlabie skryptem gen_tb_data
a = 18'h39ba9;
b = 8'h3b;
c = 12'hd8a;
d = 8'h24;
e = 14'h3380;
f = 19'h10d1f;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for(i = 0; i < 20; i = i + 1)
begin
clk <= 1; #1;
clk <= 0; #1;
end
if(y != 37'h1ffac0469a) $stop;
$stop;
end
endmodule
|
`include "scmem.vh"
module dcache_pipe_wp(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input logic clk
,input logic reset
//---------------------------
// core interface LD
,input logic coretodc_ld_valid
,output logic coretodc_ld_retry
// ,input I_coretodc_ld_type coretodc_ld
,input DC_ckpid_type coretodc_ld_ckpid //4
,input CORE_reqid_type coretodc_ld_coreid //6
,input CORE_lop_type coretodc_ld_lop //5
,input logic coretodc_ld_pnr //1
,input SC_pcsign_type coretodc_ld_pcsign //13
,input SC_poffset_type coretodc_ld_poffset //12
,input SC_imm_type coretodc_ld_imm //12
,output logic dctocore_ld_valid
,input logic dctocore_ld_retry
// ,output I_dctocore_ld_type dctocore_ld
,output CORE_reqid_type dctocore_ld_coreid
,output SC_fault_type dctocore_ld_fault
//,output SC_line_type dctocore_ld_data
,output logic [63:0] dctocore_ld_data_7
,output logic [63:0] dctocore_ld_data_6
,output logic [63:0] dctocore_ld_data_5
,output logic [63:0] dctocore_ld_data_4
,output logic [63:0] dctocore_ld_data_3
,output logic [63:0] dctocore_ld_data_2
,output logic [63:0] dctocore_ld_data_1
,output logic [63:0] dctocore_ld_data_0
//---------------------------
// core interface STD
,input logic coretodc_std_valid
,output logic coretodc_std_retry
// ,input I_coretodc_std_type coretodc_std
,input DC_ckpid_type coretodc_std_ckpid
,input CORE_reqid_type coretodc_std_coreid
,input CORE_mop_type coretodc_std_mop
,input logic coretodc_std_pnr
,input SC_pcsign_type coretodc_std_pcsign
,input SC_poffset_type coretodc_std_poffset
,input SC_imm_type coretodc_std_imm
//,input SC_line_type coretodc_std_data
,input logic [63:0] coretodc_std_data_7
,input logic [63:0] coretodc_std_data_6
,input logic [63:0] coretodc_std_data_5
,input logic [63:0] coretodc_std_data_4
,input logic [63:0] coretodc_std_data_3
,input logic [63:0] coretodc_std_data_2
,input logic [63:0] coretodc_std_data_1
,input logic [63:0] coretodc_std_data_0
,output logic dctocore_std_ack_valid
,input logic dctocore_std_ack_retry
// ,output I_dctocore_std_ack_type dctocore_std_ack
,output SC_fault_type dctocore_std_ack_fault
,output CORE_reqid_type dctocore_std_ack_coreid
//---------------------------
// core Prefetch interface
,output PF_cache_stats_type cachetopf_stats
//---------------------------
// TLB interface
// TLB interface LD
,input logic l1tlbtol1_fwd0_valid
,output logic l1tlbtol1_fwd0_retry
// ,input I_l1tlbtol1_fwd_type l1tlbtol1_fwd0
,input CORE_reqid_type l1tlbtol1_fwd0_coreid //6
,input logic l1tlbtol1_fwd0_prefetch //1
,input logic l1tlbtol1_fwd0_l2_prefetch //1
,input SC_fault_type l1tlbtol1_fwd0_fault //3
,input TLB_hpaddr_type l1tlbtol1_fwd0_hpaddr //11
,input SC_ppaddr_type l1tlbtol1_fwd0_ppaddr //3
// TLB interface STD
,input logic l1tlbtol1_fwd1_valid
,output logic l1tlbtol1_fwd1_retry
// ,input I_l1tlbtol1_fwd_type l1tlbtol1_fwd1
,input CORE_reqid_type l1tlbtol1_fwd1_coreid
,input logic l1tlbtol1_fwd1_prefetch
,input logic l1tlbtol1_fwd1_l2_prefetch
,input SC_fault_type l1tlbtol1_fwd1_fault
,input TLB_hpaddr_type l1tlbtol1_fwd1_hpaddr
,input SC_ppaddr_type l1tlbtol1_fwd1_ppaddr
// Notify the L1 that the index of the TLB is gone
,input logic l1tlbtol1_cmd_valid
,output logic l1tlbtol1_cmd_retry
// ,input I_l1tlbtol1_cmd_type l1tlbtol1_cmd
,input logic l1tlbtol1_cmd_flush
,input TLB_hpaddr_type l1tlbtol1_cmd_hpaddr
//---------------------------
// L2 interface (same for IC and DC)
,output logic l1tol2tlb_req_valid
,input logic l1tol2tlb_req_retry
// ,output I_l1tol2tlb_req_type l1tol2tlb_req
,output L1_reqid_type l1tol2tlb_req_l1id
,output logic l1tol2tlb_req_prefetch
,output TLB_hpaddr_type l1tol2tlb_req_hpaddr
,output logic l1tol2_req_valid
,input logic l1tol2_req_retry
// ,output I_l1tol2_req_type l1tol2_req
,output L1_reqid_type l1tol2_req_l1id
,output SC_cmd_type l1tol2_req_cmd
,output SC_pcsign_type l1tol2_req_pcsign
,output SC_poffset_type l1tol2_req_poffset
,output SC_ppaddr_type l1tol2_req_ppaddr
,input logic l2tol1_snack_valid
,output logic l2tol1_snack_retry
// ,input I_l2tol1_snack_type l2tol1_snack
,input L1_reqid_type l2tol1_snack_l1id
,input L2_reqid_type l2tol1_snack_l2id
,input SC_snack_type l2tol1_snack_snack
//,input SC_line_type l2tol1_snack_line
,input logic [63:0] l2tol1_snack_line_7
,input logic [63:0] l2tol1_snack_line_6
,input logic [63:0] l2tol1_snack_line_5
,input logic [63:0] l2tol1_snack_line_4
,input logic [63:0] l2tol1_snack_line_3
,input logic [63:0] l2tol1_snack_line_2
,input logic [63:0] l2tol1_snack_line_1
,input logic [63:0] l2tol1_snack_line_0
,input SC_poffset_type l2tol1_snack_poffset
,input TLB_hpaddr_type l2tol1_snack_hpaddr
,output logic l1tol2_snoop_ack_valid
,input logic l1tol2_snoop_ack_retry
// ,output I_l2snoop_ack_type l1tol2_snoop_ack
,output L2_reqid_type l1tol2_snoop_ack_l2id
,output DR_ndirs_type l1tol2_snoop_ack_directory_id
,output logic l1tol2_disp_valid
,input logic l1tol2_disp_retry
// ,output I_l1tol2_disp_type l1tol2_disp
,output L1_reqid_type l1tol2_disp_l1id
,output L2_reqid_type l1tol2_disp_l2id
,output SC_disp_mask_type l1tol2_disp_mask
,output SC_dcmd_type l1tol2_disp_dcmd
//,output SC_line_type l1tol2_disp_line
,output logic [63:0] l1tol2_disp_line_7
,output logic [63:0] l1tol2_disp_line_6
,output logic [63:0] l1tol2_disp_line_5
,output logic [63:0] l1tol2_disp_line_4
,output logic [63:0] l1tol2_disp_line_3
,output logic [63:0] l1tol2_disp_line_2
,output logic [63:0] l1tol2_disp_line_1
,output logic [63:0] l1tol2_disp_line_0
,output SC_ppaddr_type l1tol2_disp_ppaddr
,input logic l2tol1_dack_valid
,output logic l2tol1_dack_retry
// ,input I_l2tol1_dack_type l2tol1_dack
,input L1_reqid_type l2tol1_dack_l1id
/* verilator lint_on UNUSED */
/* verilator lint_on UNDRIVEN */
);
I_coretodc_ld_type coretodc_ld;
assign coretodc_ld.ckpid = coretodc_ld_ckpid;
assign coretodc_ld.coreid = coretodc_ld_coreid;
assign coretodc_ld.lop = coretodc_ld_lop;
assign coretodc_ld.pnr = coretodc_ld_pnr;
assign coretodc_ld.pcsign = coretodc_ld_pcsign;
assign coretodc_ld.poffset = coretodc_ld_poffset;
assign coretodc_ld.imm = coretodc_ld_imm;
I_dctocore_ld_type dctocore_ld;
assign dctocore_ld_coreid = dctocore_ld.coreid;
assign dctocore_ld_fault = dctocore_ld.fault;
assign {dctocore_ld_data_7,
dctocore_ld_data_6,
dctocore_ld_data_5,
dctocore_ld_data_4,
dctocore_ld_data_3,
dctocore_ld_data_2,
dctocore_ld_data_1,
dctocore_ld_data_0} = dctocore_ld.data;
I_coretodc_std_type coretodc_std;
assign coretodc_std.ckpid = coretodc_std_ckpid;
assign coretodc_std.coreid = coretodc_std_coreid;
assign coretodc_std.mop = coretodc_std_mop;
assign coretodc_std.pnr = coretodc_std_pnr;
assign coretodc_std.pcsign = coretodc_std_pcsign;
assign coretodc_std.poffset = coretodc_std_poffset;
assign coretodc_std.imm = coretodc_std_imm;
assign coretodc_std.data = {coretodc_std_data_7,
coretodc_std_data_6,
coretodc_std_data_5,
coretodc_std_data_4,
coretodc_std_data_3,
coretodc_std_data_2,
coretodc_std_data_1,
coretodc_std_data_0};
I_dctocore_std_ack_type dctocore_std_ack;
assign dctocore_std_ack_fault = dctocore_std_ack.fault;
assign dctocore_std_ack_coreid = dctocore_std_ack.coreid;
I_l1tlbtol1_fwd_type l1tlbtol1_fwd0;
assign l1tlbtol1_fwd0.coreid = l1tlbtol1_fwd0_coreid;
assign l1tlbtol1_fwd0.prefetch = l1tlbtol1_fwd0_prefetch;
assign l1tlbtol1_fwd0.l2_prefetch = l1tlbtol1_fwd0_l2_prefetch;
assign l1tlbtol1_fwd0.fault = l1tlbtol1_fwd0_fault;
assign l1tlbtol1_fwd0.hpaddr = l1tlbtol1_fwd0_hpaddr;
assign l1tlbtol1_fwd0.ppaddr = l1tlbtol1_fwd0_ppaddr;
I_l1tlbtol1_fwd_type l1tlbtol1_fwd1;
assign l1tlbtol1_fwd1.coreid = l1tlbtol1_fwd1_coreid;
assign l1tlbtol1_fwd1.prefetch = l1tlbtol1_fwd1_prefetch;
assign l1tlbtol1_fwd1.l2_prefetch = l1tlbtol1_fwd1_l2_prefetch;
assign l1tlbtol1_fwd1.fault = l1tlbtol1_fwd1_fault;
assign l1tlbtol1_fwd1.hpaddr = l1tlbtol1_fwd1_hpaddr;
assign l1tlbtol1_fwd1.ppaddr = l1tlbtol1_fwd1_ppaddr;
I_l1tlbtol1_cmd_type l1tlbtol1_cmd;
assign l1tlbtol1_cmd.flush = l1tlbtol1_cmd_flush;
assign l1tlbtol1_cmd.hpaddr = l1tlbtol1_cmd_hpaddr;
I_l1tol2tlb_req_type l1tol2tlb_req;
assign l1tol2tlb_req_l1id = l1tol2tlb_req.l1id;
assign l1tol2tlb_req_prefetch = l1tol2tlb_req.prefetch;
assign l1tol2tlb_req_hpaddr = l1tol2tlb_req.hpaddr;
I_l1tol2_req_type l1tol2_req;
assign l1tol2_req_l1id = l1tol2_req.l1id;
assign l1tol2_req_cmd = l1tol2_req.cmd;
assign l1tol2_req_pcsign = l1tol2_req.pcsign;
assign l1tol2_req_poffset = l1tol2_req.poffset;
assign l1tol2_req_ppaddr = l1tol2_req.ppaddr;
I_l2tol1_snack_type l2tol1_snack;
assign l2tol1_snack.l1id = l2tol1_snack_l1id;
assign l2tol1_snack.l2id = l2tol1_snack_l2id;
assign l2tol1_snack.snack = l2tol1_snack_snack;
assign l2tol1_snack.line = {l2tol1_snack_line_7,
l2tol1_snack_line_6,
l2tol1_snack_line_5,
l2tol1_snack_line_4,
l2tol1_snack_line_3,
l2tol1_snack_line_2,
l2tol1_snack_line_1,
l2tol1_snack_line_0};
assign l2tol1_snack.poffset = l2tol1_snack_poffset;
assign l2tol1_snack.hpaddr = l2tol1_snack_hpaddr;
I_l2snoop_ack_type l1tol2_snoop_ack;
assign l1tol2_snoop_ack_l2id = l1tol2_snoop_ack.l2id;
assign l1tol2_snoop_ack_directory_id = l1tol2_snoop_ack.directory_id;
I_l1tol2_disp_type l1tol2_disp;
assign l1tol2_disp_l1id = l1tol2_disp.l1id;
assign l1tol2_disp_l2id = l1tol2_disp.l2id;
assign l1tol2_disp_mask = l1tol2_disp.mask;
assign l1tol2_disp_dcmd = l1tol2_disp.dcmd;
assign {l1tol2_disp_line_7,
l1tol2_disp_line_6,
l1tol2_disp_line_5,
l1tol2_disp_line_4,
l1tol2_disp_line_3,
l1tol2_disp_line_2,
l1tol2_disp_line_1,
l1tol2_disp_line_0} = l1tol2_disp.line;
assign l1tol2_disp_ppaddr = l1tol2_disp.ppaddr;
I_l2tol1_dack_type l2tol1_dack;
assign l2tol1_dack.l1id = l2tol1_dack_l1id;
dcache_pipe dcache_pipe_dut(.dctocore_ld (dctocore_ld), .*);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ae
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ae.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_ae.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ae
//
// No `defines in this module
module ent_ae
//
// Generated module inst_ae
//
(
port_ae_2, // Use internally test2, no port generated
port_ae_5, // Bus, single bits go to outside
port_ae_6, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_i_ae, // Input Bus
sig_o_ae // Output Bus
);
// Generated Module Inputs:
input [4:0] port_ae_2;
input [3:0] port_ae_5;
input [3:0] port_ae_6;
input [5:0] sig_07;
input [8:2] sig_08;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output [7:0] sig_o_ae;
// Generated Wires:
wire [4:0] port_ae_2;
wire [3:0] port_ae_5;
wire [3:0] port_ae_6;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [6:0] sig_i_ae;
wire [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ae
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and2 (
X ,
A ,
B ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PS_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DFF_PS_SYMBOL_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$PS (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PS_SYMBOL_V
|
module forward_mem_stage(mem_wb_op,mem_wb_regA,mem_wb_regC,ex_mem_op,ex_mem_regA,F3,mem_wb_CCR_write,ex_mem_CCR_write);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
input [2:0] mem_wb_regA,mem_wb_regC,ex_mem_regA;
input [5:0]mem_wb_op,ex_mem_op;
input mem_wb_CCR_write,ex_mem_CCR_write;
output reg [1:0]F3;
always @(*)
begin
if(ex_mem_op[5:2]==SW)
begin
if((ex_mem_regA == mem_wb_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC||mem_wb_op==ADZ
||mem_wb_op==NDC||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F3 = 2'd2;//b
else if((ex_mem_regA==mem_wb_regA)&&(mem_wb_op[5:2]==LW))
F3 = 2'd3;//c
else
F3 = 2'b0;
end
else
F3 = 2'b0;
end
endmodule
|
/**
*@file BCocd_Encoder.v
*@brief IRIG-B code encoding and transmating module
*@author LUAN Yuezhen
*@date Origin 2016.11.16
*@tab Tab size = 4 spaces
*/
module bcode_encoder(
input clk,
input pps,
input rst_n,
input clk_reload_n,
input utc_cnv_end,
input [5 : 0] sec_bin,
input [5 : 0] min_bin,
input [4 : 0] hour_bin,
input [8 : 0] day_bin,
input [15: 0] year_bin,
input [63: 0] tai_sec,
input [7 : 0] time_zone,
input [63: 0] dst_ing,
input [63: 0] dst_eng,
input [63: 0] leap_occur,
input leap_direct,
input [3 : 0] time_quality,
input [16: 0] sec_of_day,
output bcode_trans
);
localparam CODE_P = 4'd7;
localparam CODE_1 = 4'd4;
localparam CODE_0 = 4'd1;
localparam BCD_WAIT_PPS = 11'b1;
localparam BCD_WAIT_UTC_CNV = 11'b10;
localparam BCD_CNV_SEC_START = 11'b100;
localparam BCD_CNV_SEC = 11'b1000;
localparam BCD_CNV_MIN_START = 11'b10000;
localparam BCD_CNV_MIN = 11'b100000;
localparam BCD_CNV_HOUR_START = 11'b1000000;
localparam BCD_CNV_HOUR = 11'b10000000;
localparam BCD_CNV_DAY_START = 11'b100000000;
localparam BCD_CNV_DAY = 11'b1000000000;
localparam BCD_ECC = 11'b10000000000;
localparam ITR_WAIT_PPS = 11'b1;
localparam ITR_SEND_SEC = 11'b10;
localparam ITR_SEND_MIN = 11'b100;
localparam ITR_SEND_HOUR = 11'b1000;
localparam ITR_SEND_DAY_LOW = 11'b10000;
localparam ITR_SEND_DAY_HIGH = 11'b100000;
localparam ITR_SEND_YEAR = 11'b1000000;
localparam ITR_SEND_CTRL_FLAG = 11'b10000000;
localparam ITR_SEND_ECC = 11'b100000000;
localparam ITR_SEND_SBS_LOW = 11'b1000000000;
localparam ITR_SEND_SBS_HIGH = 11'b10000000000;
wire pps_forward;
wire clk_100hz;
wire clk_1khz;
wire pps_forward_ok;
wire clk_100hz_ok;
wire clk_1khz_ok;
reg [1 : 0] pps_catch;
reg [1 : 0] pps_catch_100hz;
reg [1 : 0] pps_catch_1khz;
wire pps_redge_catch;
wire pps_redge_catch_100hz;
wire pps_redge_catch_1khz;
reg [10 : 0] bcd_cnv_state;
reg [10 : 0] bcd_next_state;
reg [10 : 0] itr_cnv_state;
reg [10 : 0] itr_next_state;
reg cnv_ok;
reg [3 : 0] bit_count;
wire bit_count_less_than_9;
reg [7 : 0] sec_bcd;
reg [7 : 0] min_bcd;
reg [7 : 0] hour_bcd;
reg [11 : 0] day_bcd;
reg [7 : 0] year_bcd;
reg [63 : 0] tai_plus_59;
reg signed [7 : 0] time_offset;
reg dst_flag;
reg leap_precast;
reg dst_precast;
reg time_offset_sign;
reg [3 : 0] time_offset_hour;
reg time_offset_half_hour;
reg ecc_bit;
wire is_not_dst_period;
wire [4 : 0] time_offset_complete;
reg [8 : 0] shifter;
reg [3 : 0] rz_code;
reg [8 : 0] bcd_bin_num;
reg bcd_start;
reg [15 : 0] l_bcd_bin_num;
reg l_bcd_start;
wire bcd_end;
wire [11 : 0] bcd_rslt;
wire l_bcd_end;
wire [19 : 0] l_bcd_rslt;
reg [3 : 0] rz_encode_timer;
reg bcode_gen;
always @ (posedge clk or negedge clk_reload_n)
begin
if (!clk_reload_n) begin
pps_catch <= 2'b11;
end
else begin
pps_catch[0] <= pps_forward;
pps_catch[1] <= pps_catch[0];
end
end
assign pps_redge_catch = (pps_catch == 2'b01) ? 1 : 0;
/********* Start of bcd convert FSM *********/
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
bcd_cnv_state <= BCD_WAIT_PPS;
end
else begin
bcd_cnv_state <= bcd_next_state;
end
end
always @ (*)
begin
case (bcd_cnv_state)
BCD_WAIT_PPS : begin
if (pps_redge_catch) begin
bcd_next_state = BCD_WAIT_UTC_CNV;
end
else begin
bcd_next_state = BCD_WAIT_PPS;
end
end
BCD_WAIT_UTC_CNV : begin
if (utc_cnv_end) begin
bcd_next_state = BCD_CNV_SEC_START;
end
else begin
bcd_next_state = BCD_WAIT_UTC_CNV;
end
end
BCD_CNV_SEC_START : begin
bcd_next_state = BCD_CNV_SEC;
end
BCD_CNV_SEC : begin
if (bcd_end) begin
bcd_next_state = BCD_CNV_MIN_START;
end
else begin
bcd_next_state = BCD_CNV_SEC;
end
end
BCD_CNV_MIN_START : begin
bcd_next_state = BCD_CNV_MIN;
end
BCD_CNV_MIN : begin
if (bcd_end) begin
bcd_next_state = BCD_CNV_HOUR_START;
end
else begin
bcd_next_state = BCD_CNV_MIN;
end
end
BCD_CNV_HOUR_START : begin
bcd_next_state = BCD_CNV_HOUR;
end
BCD_CNV_HOUR : begin
if (bcd_end) begin
bcd_next_state = BCD_CNV_DAY_START;
end
else begin
bcd_next_state = BCD_CNV_HOUR;
end
end
BCD_CNV_DAY_START : begin
bcd_next_state = BCD_CNV_DAY;
end
BCD_CNV_DAY : begin
if (bcd_end) begin
bcd_next_state = BCD_ECC;
end
else begin
bcd_next_state = BCD_CNV_DAY;
end
end
BCD_ECC : begin
bcd_next_state = BCD_WAIT_PPS;
end
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin
cnv_ok <= 0;
end
else begin
case (bcd_cnv_state)
BCD_WAIT_PPS : begin
if (pps_redge_catch) begin
cnv_ok <= 0;
end
else begin
cnv_ok <= cnv_ok;
end
end
BCD_WAIT_UTC_CNV : begin
bcd_bin_num <= sec_bin;
bcd_start <= 0;
l_bcd_bin_num <= year_bin;
l_bcd_start <= 0;
end
BCD_CNV_SEC_START : begin
bcd_start <= 1;
l_bcd_start <= 1;
tai_plus_59 <= tai_sec + 64'd59;
time_offset <= $signed(time_zone) +
((is_not_dst_period) ?
($signed(8'd0)) : ($signed(8'd2)));
dst_flag <= (is_not_dst_period) ? 0 : 1;
end
BCD_CNV_SEC : begin
bcd_start <= 0;
l_bcd_start <= 0;
sec_bcd <= bcd_rslt;
end
BCD_CNV_MIN_START : begin
bcd_bin_num <= min_bin;
bcd_start <= 1;
if ((tai_plus_59 < leap_occur) ||
(tai_sec > leap_occur)) begin
leap_precast <= 0;
end
else begin
leap_precast <= 1;
end
if ((tai_plus_59 < dst_ing) ||
(tai_sec > dst_ing)) begin
dst_precast <= 0;
end
else begin
dst_precast <= 1;
end
if (time_offset < 0) begin
time_offset_sign <= 1;
time_offset_hour <= time_offset_complete[4 : 1];
time_offset_half_hour <= time_offset_complete[0];
end
else begin
time_offset_sign <= 0;
time_offset_hour <= time_offset[4 : 1];
time_offset_half_hour <= time_offset[0];
end
end
BCD_CNV_MIN : begin
bcd_start <= 0;
min_bcd <= bcd_rslt;
year_bcd <= l_bcd_rslt;
end
BCD_CNV_HOUR_START : begin
bcd_bin_num <= hour_bin;
bcd_start <= 1;
end
BCD_CNV_HOUR : begin
bcd_start <= 0;
hour_bcd <= bcd_rslt;
end
BCD_CNV_DAY_START : begin
bcd_bin_num <= day_bin;
bcd_start <= 1;
end
BCD_CNV_DAY : begin
bcd_start <= 0;
day_bcd <= bcd_rslt;
end
BCD_ECC : begin
ecc_bit <=
!(^{sec_bcd,
min_bcd,
hour_bcd,
day_bcd,
year_bcd,
leap_precast,
leap_direct,
dst_precast,
dst_flag,
time_offset_sign,
time_offset_hour,
time_offset_half_hour,
time_quality});
cnv_ok <= 1;
end
endcase
end
end
assign is_not_dst_period = ((tai_sec < dst_ing) || (tai_sec > dst_eng)) ? 1 : 0;
assign time_offset_complete = ~(time_offset[4 : 0]) + 1;
bin2bcd #(
.BIN_BITS(9)
)bin2bcd_short (
.clk(clk),
.rst(rst_n),
.start(bcd_start),
.bin_num_in(bcd_bin_num),
.bcd_out(bcd_rslt),
.end_of_cnv(bcd_end)
);
bin2bcd #(
.BIN_BITS(16)
)bin2bcd_long (
.clk(clk),
.rst(rst_n),
.start(l_bcd_start),
.bin_num_in(l_bcd_bin_num),
.bcd_out(l_bcd_rslt),
.end_of_cnv(l_bcd_end)
);
/********* End of bcd convert FSM *********/
/********* Start of IRIG-B code bit iterator FSM *********/
always @ (posedge clk_100hz or negedge clk_reload_n)
begin
if (!clk_reload_n) begin
pps_catch_100hz <= 2'b11;
end
else begin
pps_catch_100hz[0] <= pps_forward;
pps_catch_100hz[1] <= pps_catch_100hz[0];
end
end
assign pps_redge_catch_100hz = (pps_catch_100hz == 2'b01) ? 1 : 0;
always @ (posedge clk_100hz or negedge rst_n)
begin
if (!rst_n) begin
itr_cnv_state <= ITR_WAIT_PPS;
end
else begin
itr_cnv_state <= itr_next_state;
end
end
always @ (*)
begin
case (itr_cnv_state)
ITR_WAIT_PPS : begin
if (pps_redge_catch_100hz) begin
itr_next_state = ITR_SEND_SEC;
end
else begin
itr_next_state = ITR_WAIT_PPS;
end
end
ITR_SEND_SEC : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_SEC;
end
else begin
itr_next_state = ITR_SEND_MIN;
end
end
ITR_SEND_MIN : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_MIN;
end
else begin
itr_next_state = ITR_SEND_HOUR;
end
end
ITR_SEND_HOUR : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_HOUR;
end
else begin
itr_next_state = ITR_SEND_DAY_LOW;
end
end
ITR_SEND_DAY_LOW : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_DAY_LOW;
end
else begin
itr_next_state = ITR_SEND_DAY_HIGH;
end
end
ITR_SEND_DAY_HIGH : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_DAY_HIGH;
end
else begin
itr_next_state = ITR_SEND_YEAR;
end
end
ITR_SEND_YEAR : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_YEAR;
end
else begin
itr_next_state = ITR_SEND_CTRL_FLAG;
end
end
ITR_SEND_CTRL_FLAG : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_CTRL_FLAG;
end
else begin
itr_next_state = ITR_SEND_ECC;
end
end
ITR_SEND_ECC : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_ECC;
end
else begin
itr_next_state = ITR_SEND_SBS_LOW;
end
end
ITR_SEND_SBS_LOW : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_SBS_LOW;
end
else begin
itr_next_state = ITR_SEND_SBS_HIGH;
end
end
ITR_SEND_SBS_HIGH : begin
if (bit_count_less_than_9) begin
itr_next_state = ITR_SEND_SBS_HIGH;
end
else begin
itr_next_state = ITR_WAIT_PPS;
end
end
endcase
end
always @ (posedge clk_100hz or negedge rst_n)
begin
if (!rst_n) begin
shifter <= 0;
bit_count <= 0;
rz_code <= CODE_P;
end
else begin
case (itr_cnv_state)
ITR_WAIT_PPS : begin
if (pps_redge_catch_100hz) begin
shifter <= {sec_bcd[4 * 1 +: 4],
1'b0,
sec_bcd[4 * 0 +: 4]}
>> 1;
bit_count <= 2;
rz_code <= (sec_bcd[0]) ?
CODE_1 :
CODE_0;
end
else begin
bit_count <= 1;
rz_code <= CODE_P;
end
end
ITR_SEND_SEC : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= {min_bcd[4 * 1 +: 4],
1'b0,
min_bcd[4 * 0 +: 4]};
bit_count <= 0;
rz_code <= CODE_P;
end
end
ITR_SEND_MIN : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= {hour_bcd[4 * 1 +: 4],
1'b0,
hour_bcd[4 * 0 +: 4]};
bit_count <= 0;
rz_code <= CODE_P;
end
end
ITR_SEND_HOUR : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= {day_bcd[4 * 1 +: 4],
1'b0,
day_bcd[4 * 0 +: 4]};
bit_count <= 0;
rz_code <= CODE_P;
end
end
ITR_SEND_DAY_LOW : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= {5'b0,
day_bcd[4 * 2 +: 4]};
bit_count <= 0;
rz_code <= CODE_P;
end
end
ITR_SEND_DAY_HIGH : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= {year_bcd[4 * 1 +: 4],
1'b0,
year_bcd[4 * 0 +: 4]};
bit_count <= 0;
rz_code <= CODE_P;
end
end
ITR_SEND_YEAR : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= {time_offset_hour,
time_offset_sign,
dst_flag,
dst_precast,
leap_direct,
leap_precast};
bit_count <= 0;
rz_code <= CODE_P;
end
end
ITR_SEND_CTRL_FLAG : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= {3'b0,
ecc_bit,
time_quality,
time_offset_half_hour};
bit_count <= 0;
rz_code <= CODE_P;
end
end
ITR_SEND_ECC : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= sec_of_day[0 +: 9];
bit_count <= 0;
rz_code <= CODE_P;
end
end
ITR_SEND_SBS_LOW : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= {1'b0,
sec_of_day[9 +: 8]};
bit_count <= 0;
rz_code <= CODE_P;
end
end
ITR_SEND_SBS_HIGH : begin
if (bit_count_less_than_9) begin
shifter <= shifter >> 1;
bit_count <= bit_count + 1;
rz_code <= (shifter[0]) ?
CODE_1 :
CODE_0;
end
else begin
shifter <= 9'bx;
bit_count <= 0;
rz_code <= CODE_P;
end
end
endcase
end
end
assign bit_count_less_than_9 = (bit_count < 9) ? 1 : 0;
/********* End of IRIG-B code bit iterator FSM *********/
/********* Start of rz code encoder *********/
always @ (posedge clk_1khz or negedge clk_reload_n)
begin
if (!clk_reload_n) begin
pps_catch_1khz <= 2'b11;
end
else begin
pps_catch_1khz[0] <= pps_forward;
pps_catch_1khz[1] <= pps_catch_1khz[0];
end
end
assign pps_redge_catch_1khz = (pps_catch_1khz == 2'b01) ? 1 : 0;
always @ (posedge clk_1khz or negedge rst_n)
begin
if (!rst_n) begin
rz_encode_timer <= 4'd1;
end
else begin
if ((rz_encode_timer < rz_code) ||
(!(rz_encode_timer < 4'd9))) begin
bcode_gen <= 1;
end
else begin
bcode_gen <= 0;
end
if (pps_redge_catch_1khz) begin
rz_encode_timer <= 4'd1;
end
else if (rz_encode_timer < 4'd9) begin
rz_encode_timer <= rz_encode_timer + 1;
end
else begin
rz_encode_timer <= 0;
end
end
end
assign bcode_trans = bcode_gen;
/********* End of rz code encoder *********/
clk_synchronizer #(
.SYSCLK_FREQ_HZ(64'd100_000_000),
.PPS_HIGH_LEVEL_US(64'd1_000),
.GENCLK_FREQ_HZ(1),
.FORWARD_OFFSET_CLK(1)
) pps_forward_generator (
.clk(clk),
.rst_n(clk_reload_n),
.pps_in(pps),
.sync_clk_out(pps_forward),
.clk_sync_ok_out(pps_forward_ok)
);
clk_synchronizer #(
.SYSCLK_FREQ_HZ(64'd100_000_000),
.PPS_HIGH_LEVEL_US(64'd1_000),
.GENCLK_FREQ_HZ(100),
.FORWARD_OFFSET_CLK(0)
) synced_100hz_generator (
.clk(clk),
.rst_n(clk_reload_n),
.pps_in(pps),
.sync_clk_out(clk_100hz),
.clk_sync_ok_out(clk_100hz_ok)
);
clk_synchronizer #(
.SYSCLK_FREQ_HZ(64'd100_000_000),
.PPS_HIGH_LEVEL_US(64'd100),
.GENCLK_FREQ_HZ(1000),
.FORWARD_OFFSET_CLK(0)
) synced_1khz_generator (
.clk(clk),
.rst_n(clk_reload_n),
.pps_in(pps),
.sync_clk_out(clk_1khz),
.clk_sync_ok_out(clk_1khz_ok)
);
endmodule
|
module Computer_Datapath_FunctionUnit(
output reg [WORD_WIDTH-1:0] FU_out,
output [ALU_FLAGS_WIDTH-1:0] FLAG_bus_out,
input [WORD_WIDTH-1:0] ADDR_bus_in, DATA_bus_in,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SA_WIDTH = DR_WIDTH;
parameter SB_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter FS_WIDTH = 4;
parameter ALU_FLAGS_WIDTH = 4;
parameter CNTRL_FLAGS_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SA_WIDTH+SB_WIDTH+FS_WIDTH+CNTRL_FLAGS_WIDTH;
wire [FS_WIDTH-1:0] FS = CNTRL_bus_in[9:6];
wire [WORD_WIDTH-2:0] V_temp = ADDR_bus_in[WORD_WIDTH-2:0]+DATA_bus_in[WORD_WIDTH-2:0];
wire V = V_temp[WORD_WIDTH-2:0];
wire N = FU_out[WORD_WIDTH-1];
wire Z = (!FU_out)?1'b1:1'b0;
reg C;
assign FLAG_bus_out = {V, C, N, Z};
always@(*) begin
case(FS)
4'b0000: {C, FU_out} = ADDR_bus_in; // Move A
4'b0001: {C, FU_out} = ADDR_bus_in+1; // Increment
4'b0010: {C, FU_out} = ADDR_bus_in+DATA_bus_in; // Add
4'b0011: {C, FU_out} = ADDR_bus_in+DATA_bus_in+1; //
4'b0100: {C, FU_out} = ADDR_bus_in+(~DATA_bus_in); //
4'b0101: {C, FU_out} = ADDR_bus_in+(~DATA_bus_in)+1; // Subtraction
4'b0110: {C, FU_out} = ADDR_bus_in-1; // Decrement
4'b0111: {C, FU_out} = ADDR_bus_in; // Move A
4'b1000: {C, FU_out} = ADDR_bus_in&DATA_bus_in; // Bitwize and
4'b1001: {C, FU_out} = ADDR_bus_in|DATA_bus_in; // Bitwize or
4'b1010: {C, FU_out} = ADDR_bus_in^DATA_bus_in; // Bitwize xor
4'b1011: {C, FU_out} = (~ADDR_bus_in); // Bitwize Invert
4'b1100: {C, FU_out} = DATA_bus_in; // Move B
4'b1101: {C, FU_out} = (DATA_bus_in>>1); // Shift Right B
4'b1110: {C, FU_out} = (DATA_bus_in<<1); // Shift Left B
4'b1111: {C, FU_out} = (~DATA_bus_in); // Ivert B
endcase
end
endmodule |
`timescale 1ns / 1ps
/********************************************************************
* TEST BENCH FOR PROTECTION CELLS *
********************************************************************
* Laboratory : Robotics and Embedded System Technology
* Engineer : Hanjara Cahya Adhyatma
* Create Date : 19/04/2017
* Project Name : FINAL PROJECT
* Target Devices: TEST BENCH SIM PROTECTION AND FPGA
* Tool versions : VERILOG 2001 RUN ON ICARUS 10
* Description : ??????????????
* Dependencies : ???
* Revision : ???
* Additional Comments: ???
********************************************************************
* INCLUDE MODULES *
*******************************************************************/
`include "./module/selesai/alu.v"
/********************************************************************
* IO DEFINITIONS *
*******************************************************************/
module alu_tb;
reg RST, CLK, ENA;
reg [7:0]OPT;
reg [7:0]RGA;
reg [7:0]RGB;
wire [7:0]RGZ;
reg [1:0]KEY;
/********************************************************************
* DUMPER MONITOR *
*******************************************************************/
initial
begin
$dumpfile("vcd");
$dumpvars(0, alus);
$monitor($time, " REG A = %b REG Z = %b", RGA, RGZ);
end
/********************************************************************
* CLOCKING *
*******************************************************************/
initial
begin
CLK = 1'b1;
forever #5 CLK = ~CLK;
end
/********************************************************************
* RESET *
*******************************************************************/
initial
begin
RST = 1'b1;
#5 RST = 1'b0;
end
/********************************************************************
* DATAS INJECTION *
*******************************************************************/
initial
begin
RGA = 8'b00000000;
#10 RGA = 8'b00000111;
#10 RGA = 8'b00000101;
#10 RGA = 8'b00000110;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000011;
#10 RGA = 8'b00000100;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000000;
#10 RGA = 8'b00000111;
#10 RGA = 8'b00000100;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000001;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000101;
#10 RGA = 8'b00000011;
#10 RGA = 8'b00000100;
#10 RGA = 8'b00000010;
#10 RGA = 8'b00000111;
#10 RGA = 8'b00000011;
#10 RGA = 8'b00000000;
$finish;
end
/********************************************************************
* OPCODE *
*******************************************************************/
initial
begin
OPT = 8'b00000001;
#5 OPT = 8'b00000011;
end
initial
begin
KEY = 1'b1;
#5 KEY = 1'b1;
end
initial
begin
RGB = 1;
end
/********************************************************************
* MODULE IN TEST *
*******************************************************************/
alu alus(RST, CLK, ENA, RGA, RGB, RGZ, KEY, OPT);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_4_V
`define SKY130_FD_SC_HD__DECAP_4_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__decap_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_4_V
|
module sing(
input [11:0] PTX,
input [11:0] PTY,
input [11:0] P1X,
input [11:0] P1Y,
input [11:0] P2X,
input [11:0] P2Y,
output sin
);
wire signed [11:0] Sub1;
wire signed [11:0] Sub2;
wire signed [11:0] Sub3;
wire signed [11:0] Sub4;
wire signed [22:0] Sub5;
wire signed [22:0] Mult1;
wire signed [22:0] Mult2;
assign Sub1 = PTX - P2X;
assign Sub2 = P1Y - P2Y;
assign Sub3 = P1X - P2X;
assign Sub4 = PTY - P2Y;
assign Mult1 = Sub1 * Sub2;
assign Mult2 = Sub3 * Sub4;
assign Sub5 = Mult1 - Mult2;
assign sin = (Sub5 >= 0) ? 1 : 0;
endmodule
module TesteTriangulo (
input [11:0] Ponto1X,
input [11:0] Ponto1Y,
input [11:0] Ponto2X,
input [11:0] Ponto2Y,
input [11:0] Ponto3X,
input [11:0] Ponto3Y,
input [11:0] PontoTX,
input [11:0] PontoTY,
output dentro
);
wire sinal1;
wire sinal2;
wire sinal3;
assign dentro = (sinal1 == 1 && sinal2 == 1 && sinal3 == 1) ? 1:0;
sinal S1(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, PontoTX, PontoTY, sinal1);
sinal S2(Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, sinal2);
sinal S3(Ponto3X, Ponto3Y, Ponto1X, Ponto1Y, PontoTX, PontoTY, sinal3);
endmodule
module Teste;
reg [11:0] Ponto1X;
reg [11:0] Ponto1Y;
reg [11:0] Ponto2X;
reg [11:0] Ponto2Y;
reg [11:0] Ponto3X;
reg [11:0] Ponto3Y;
reg [11:0] PontoTX;
reg [11:0] PontoTY;
wire Dentro;
TesteTriangulo A(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, Dentro);
initial
begin
$dumpvars(0,A);
#1
Ponto1X <= 10;
Ponto1Y <= 10;
Ponto2X <= 30;
Ponto2Y <= 10;
Ponto3X <= 20;
Ponto3Y <= 30;
PontoTX <= 15;
PontoTY <= 15;
#1
PontoTX <= 15;
PontoTY <= 15;
#1
PontoTX <= 9;
PontoTY <= 15;
#1
PontoTX <= 10;
PontoTY <= 11;
#1
PontoTX <= 30;
PontoTY <= 11;
#40
$finish;
end
endmodule
|
//-----------------------------------------------------------------------------
// File : instruction_decoder.v
// Creation date : 16.05.2017
// Creation time : 09:02:07
// Description :
// Created by : TermosPullo
// Tool : Kactus2 3.4.106 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:cpu.logic:instruction_decoder:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.logic/instruction_decoder/1.0/instruction_decoder.1.0.xml
//-----------------------------------------------------------------------------
module instruction_decoder #(
parameter REGISTER_ID_WIDTH = 4, // Bits reserved for identification a single register.
parameter LITERAL_WIDTH = 16, // How long literals the instructions may have.
parameter OP_CODE_WIDTH = 4, // Bits reserved for operation identifiers.
parameter INSTRUCTION_WIDTH = OP_CODE_WIDTH+2*REGISTER_ID_WIDTH+LITERAL_WIDTH, // Total width of an instruction
parameter DATA_WIDTH = 16, // Width for data in registers and instructions.
parameter ALU_OP_WIDTH = 3, // Bits reserved for identification of alu operation
parameter INSTRUCTION_ADDRESS_WIDTH = 8 // Width of an instruction address.
) (
// Interface: cpu_clk_sink
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i, // The mandatory reset, as this is synchronous logic.
// Interface: cpu_system
input [DATA_WIDTH-1:0] alu_status_i,
input [DATA_WIDTH-1:0] load_value_i,
input mem_rdy_i,
output reg alu_active_o,
output reg [ALU_OP_WIDTH-1:0] alu_op_o,
output reg [REGISTER_ID_WIDTH-1:0] choose_reg1_o,
output reg [REGISTER_ID_WIDTH-1:0] choose_reg2_o,
output reg mem_active_o,
output reg register_active_o,
output reg [DATA_WIDTH-1:0] register_value_o,
output reg we_o,
// Interface: instructions
input [INSTRUCTION_WIDTH-1:0] instruction_feed,
output [INSTRUCTION_ADDRESS_WIDTH-1:0] iaddr_o
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// The available instructions.
parameter [OP_CODE_WIDTH-1:0]
NOP = 4'b0000,
SET = 4'b0001,
LOAD = 4'b0010,
STORE = 4'b0011,
BRA = 4'b0100,
BNE = 4'b0101,
PLUS = 4'b1000,
MINUS = 4'b1001,
MUL = 4'b1010,
DIV = 4'b1011,
CMP = 4'b1100,
END = 4'b1111;
// The address of the currently decoded instruction.
reg [INSTRUCTION_ADDRESS_WIDTH-1:0] instruction_pointer;
// Sliced operands of instruction decoded in combinational logic.
integer next_reg1;
integer next_reg2;
reg [OP_CODE_WIDTH-1:0] operation;
reg [DATA_WIDTH:0] literal;
// Intermediate values that are result from combinational logic.
reg [INSTRUCTION_ADDRESS_WIDTH-1:0] next_instruction;
reg next_mem_active;
reg next_we;
reg next_alu_active;
reg [DATA_WIDTH:0] next_register_value;
reg next_register_active;
// This output comes directly from combinational logic.
assign iaddr_o = next_instruction;
// Combinational logic used for decoding, as well as for those outputs that needs to take effect within current cycle.
always @* begin
if (mem_active_o)begin
// If waiting for memory operation, the CPU is stalled.
if (mem_rdy_i) begin
// If ready, no longer waiting and the next instruction is fetched.
next_mem_active <= 0;
next_instruction <= instruction_pointer + 1;
end
else begin
// Else the stalling continues.
next_mem_active <= 1;
next_instruction <= instruction_pointer;
end
// These remain zero.
next_register_value <= 0;
next_register_active <= 0;
next_we <= we_o;
next_alu_active <= 0;
end
else begin
// No stalling: process the next instruction.
// Slice the instruction to parts:
// Operation is the primary directive for what happens next.
operation = instruction_feed[INSTRUCTION_WIDTH-1:INSTRUCTION_WIDTH-4];
// Instructions may have two registers as operands.
next_reg1 = instruction_feed[INSTRUCTION_WIDTH-5:INSTRUCTION_WIDTH-8];
next_reg2 = instruction_feed[INSTRUCTION_WIDTH-9:INSTRUCTION_WIDTH-12];
// Each instruction may come with a literal value.
literal <= instruction_feed[LITERAL_WIDTH-1:0];
// Activate ALU if arithmetic operation.
if (operation == PLUS ||
operation == MINUS ||
operation == MUL ||
operation == DIV)
begin
next_alu_active <= 1;
end
else begin
next_alu_active <= 0;
end
// Memory and instruction operations do some mutually exclusive stuff.
if (operation == BRA ||
(operation == BNE && !alu_status_i[alu.ZERO]))
begin
// Branch if branching, obviously excludes data memory operations.
next_mem_active <= 0;
// Moreover, the address of the next instruction comes from operation.
next_instruction = literal;
end
else if (operation == LOAD || operation == STORE)
begin
// Activate memory controller if memory operation.
next_mem_active <= 1;
// Stalling the CPU: The instruction pointer stays the same.
next_instruction = instruction_pointer;
end
else begin
// Else the instruction pointer increases as normal.
next_mem_active <= 0;
next_instruction = instruction_pointer + 1;
end
// Activate write enable if storing to memory.
if (operation == STORE) begin
next_we <= 1;
end
else begin
next_we <= 0;
end
if (operation == SET) begin
// Activate register bank, pass the literal to it.
next_register_active <= 1;
next_register_value <= literal;
end
else begin
next_register_active <= 0;
end
end
end
// Since the processor operates on clock cycles, most outputs take effect on the next clock cycle.
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
alu_active_o <= 0;
alu_op_o <= 0;
choose_reg1_o <= 0;
choose_reg2_o <= 0;
mem_active_o <= 0;
we_o <= 0;
instruction_pointer <= 0;
register_value_o <= 0;
register_active_o <= 0;
end
else begin
// Pass the results of decoding as the operations and outputs of the next cycle.
// Register bank:
choose_reg1_o <= next_reg1;
choose_reg2_o <= next_reg2;
register_value_o <= next_register_value;
register_active_o <= next_register_active;
alu_active_o <= next_alu_active;
// Memory:
instruction_pointer <= next_instruction;
mem_active_o <= next_mem_active;
we_o <= next_we;
// Pass ALU operation: It should be part of the instruction, if any.
alu_op_o <= operation[ALU_OP_WIDTH-1:0];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A211OI_BEHAVIORAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_SYMBOL_V
`define SKY130_FD_SC_LS__DLYMETAL6S2S_SYMBOL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlymetal6s2s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S2S_SYMBOL_V
|
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|P%d|%d%d%d|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("(%d)", u.core.state);
$write("| %d", u.core.decompressor.dmf_cnt);
///////////////// can be parameterized
$write("| %d %d %d %d| %d %d %d %d|",
u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt,
u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt);
$write("| %d %d", u.core.ob_a.compressor.tmp.cnt, u.core.ob_b.compressor.tmp.cnt);
$write("| %d %d|", u.core.ob_a.OB_cnt, u.core.ob_b.OB_cnt);
$write("(%d)", u.core.ob_a.buf_t_cnt);
if (u.core.decompressor.dmf_cnt > (1<<`IB_SIZE)) begin $write("\noverflow at dc"); $finish(); end
if (u.core.im00_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im00_a"); $finish(); end
if (u.core.im01_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im01_a"); $finish(); end
if (u.core.im02_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im02_a"); $finish(); end
if (u.core.im03_a.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im03_a"); $finish(); end
if (u.core.im00_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im00_b"); $finish(); end
if (u.core.im01_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im01_b"); $finish(); end
if (u.core.im02_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im02_b"); $finish(); end
if (u.core.im03_b.imf.cnt > (1<<`IB_SIZE)) begin $write("\noverflow at im03_b"); $finish(); end
if (u.core.ob_a.compressor.tmp.cnt > 2) begin $write("\noverflow at ob_a.cmp"); $finish(); end
if (u.core.ob_b.compressor.tmp.cnt > 2) begin $write("\noverflow at ob_b.cmp"); $finish(); end
if (u.core.ob_a.OB_cnt > (1<<`OB_SIZE)) begin $write("\noverflow at ob_a"); $finish(); end
if (u.core.ob_b.OB_cnt > (1<<`OB_SIZE)) begin $write("\noverflow at ob_b"); $finish(); end
$write(" ");
if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" ");
if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M %08x %08x ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
// wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
// (selector == 1) ? {r07,r06,r05,r04} :
// (selector == 2) ? {r11,r10,r09,r08} :
// (selector == 3) ? {r15,r14,r13,r12} : 0;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,(r01 % 32'd65536),(r00 % 32'd65536)} :
(selector == 1) ? {r07,(r06 % 32'd65536),r05,(r04 % 32'd65536)} :
(selector == 2) ? {r11,(r10 % 32'd65536),r09,(r08 % 32'd65536)} :
(selector == 3) ? {(r15 % 32'd65536),(r14 % 32'd65536),r13,(r12 % 32'd65536)} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:02:30 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_33 ( CLK, EN, ENCLK, TE
);
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch3v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire enab_d_ff4_Zn, enab_d_ff_RB1, enab_RB3, enab_d_ff5_data_out,
d_ff1_operation_out, d_ff1_shift_region_flag_out_0_, d_ff3_sign_out,
enab_d_ff4_Yn, enab_d_ff4_Xn, fmtted_Result_31_, ITER_CONT_net3611507,
ITER_CONT_N5, ITER_CONT_N4, ITER_CONT_N3, d_ff5_data_out_net3611471,
reg_Z0_net3611471, reg_val_muxZ_2stage_net3611471,
reg_shift_y_net3611471, d_ff4_Xn_net3611471, d_ff4_Yn_net3611471,
d_ff4_Zn_net3611471, n154, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n531, n532, n533, n534, n535, n536,
n537, intadd_423_CI, intadd_423_n3, intadd_423_n2, intadd_423_n1,
intadd_424_CI, intadd_424_n3, intadd_424_n2, intadd_424_n1, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616,
n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638,
n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660,
n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671,
n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682,
n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693,
n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704,
n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726,
n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748,
n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] first_mux_X;
wire [31:0] d_ff_Yn;
wire [31:0] first_mux_Y;
wire [31:0] d_ff_Zn;
wire [31:0] first_mux_Z;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [7:0] sh_exp_x;
wire [7:0] sh_exp_y;
wire [25:4] data_out_LUT;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [30:0] mux_sal;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_33 ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(ITER_CONT_net3611507), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3611471),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff_RB1), .ENCLK(reg_Z0_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
reg_val_muxZ_2stage_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_RB3), .ENCLK(reg_shift_y_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3611471), .TE(1'b0) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n780), .QN(n606) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3611471), .RN(n782), .Q(d_ff1_shift_region_flag_out_0_),
.QN(n612) );
DFFRXLTS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3611471), .RN(n783), .QN(n608) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n524), .CK(reg_shift_y_net3611471), .RN(n783),
.Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n534), .CK(reg_shift_y_net3611471), .RN(n788),
.Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n528), .CK(reg_shift_y_net3611471), .RN(n788),
.Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n536), .CK(reg_shift_y_net3611471), .RN(n788),
.Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[4]), .CK(reg_shift_y_net3611471),
.RN(n787), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n525), .CK(reg_shift_y_net3611471), .RN(n780),
.Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n527), .CK(reg_shift_y_net3611471), .RN(n785),
.Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n531), .CK(reg_shift_y_net3611471), .RN(n784),
.Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n756), .CK(reg_shift_y_net3611471), .RN(n780),
.Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n533), .CK(reg_shift_y_net3611471), .RN(n788),
.Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n526), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n532), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n523), .CK(reg_shift_y_net3611471), .RN(n783), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n535), .CK(reg_shift_y_net3611471), .RN(n785), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n537), .CK(reg_shift_y_net3611471), .RN(n784), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n522), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n521), .CK(reg_shift_y_net3611471), .RN(n783), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n520), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3611471), .RN(n786), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n529), .CK(reg_shift_y_net3611471), .RN(n789), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3611471), .RN(n769),
.Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3611471), .RN(n786),
.Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3611471), .RN(n778),
.Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3611471), .RN(n779),
.Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3611471), .RN(n781),
.Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3611471), .RN(n789),
.Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3611471), .RN(n154),
.Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3611471), .RN(n786),
.Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3611471), .RN(n778),
.Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3611471), .RN(n779),
.Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3611471), .RN(
n782), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3611471), .RN(
n787), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3611471), .RN(
n788), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3611471), .RN(
n785), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3611471), .RN(
n784), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3611471), .RN(
n780), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3611471), .RN(
n783), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3611471), .RN(
n788), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3611471), .RN(
n787), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3611471), .RN(
n783), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3611471), .RN(
n785), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3611471), .RN(
n784), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3611471), .RN(
n783), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3611471), .RN(
n785), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3611471), .RN(
n784), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3611471), .RN(
n780), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3611471), .RN(
n782), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3611471), .RN(
n783), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3611471), .RN(
n787), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3611471), .RN(
n782), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3611471), .RN(
n785), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3611471), .RN(
n784), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3611471), .RN(n787), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3611471), .RN(n785), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3611471), .RN(n784), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3611471), .RN(n787), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3611471), .RN(n785), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3611471), .RN(n784), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3611471), .RN(n787), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n783), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3611471),
.RN(n785), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3611471), .RN(n784), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n780), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3611471),
.RN(n782), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3611471), .RN(n783), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n787), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3611471),
.RN(n782), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3611471), .RN(n785), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n781), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3611471),
.RN(n789), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3611471), .RN(n154), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n786), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3611471),
.RN(n778), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3611471), .RN(n779), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n781), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3611471),
.RN(n789), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3611471), .RN(n154), .Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n786), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3611471),
.RN(n778), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3611471), .RN(n779), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n784), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3611471),
.RN(n780), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3611471), .RN(n788), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n787), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3611471),
.RN(n787), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3611471), .RN(n788), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n785), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3611471),
.RN(n784), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3611471), .RN(n780), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n783), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3611471), .RN(n787), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n781), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3611471), .RN(n789), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3611471), .RN(n786), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n778), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3611471), .RN(n779), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3611471), .RN(n781), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n789), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3611471), .RN(n786), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3611471), .RN(n778), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n779), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3611471), .RN(n781), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3611471), .RN(n789), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n786), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3611471), .RN(n778), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3611471), .RN(n779), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n781), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3611471), .RN(n789), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3611471), .RN(n786), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n778), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3611471), .RN(n779), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3611471), .RN(n781), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n789), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3611471), .RN(n786), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3611471), .RN(n778), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n788), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3611471), .RN(n784), .Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3611471), .RN(n769), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3611471), .RN(n775), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3611471), .RN(n767), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3611471), .RN(n768), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n769), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3611471), .RN(n775), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3611471), .RN(n784), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n770), .Q(d_ff2_X[23]), .QN(n614)
);
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3611471), .RN(n776), .Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3611471), .RN(n774), .Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3611471), .RN(n776), .Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3611471), .RN(n774), .Q(d_ff_Xn[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3611471), .RN(n776), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_X[28]), .QN(n762)
);
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3611471), .RN(n771), .Q(d_ff_Xn[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3611471), .RN(n773), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n772), .Q(d_ff2_X[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3611471), .RN(n777), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3611471), .RN(n777), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3611471), .RN(n777), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n770), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3611471),
.RN(n773), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(mux_sal[0]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3611471), .RN(n776), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n772), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3611471),
.RN(n773), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(mux_sal[1]), .CK(
d_ff5_data_out_net3611471), .RN(n765), .Q(data_output[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3611471), .RN(n769), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n775), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3611471),
.RN(n776), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(mux_sal[2]), .CK(
d_ff5_data_out_net3611471), .RN(n785), .Q(data_output[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3611471), .RN(n780), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n769), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3611471),
.RN(n775), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(mux_sal[3]), .CK(
d_ff5_data_out_net3611471), .RN(n773), .Q(data_output[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3611471), .RN(n784), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3611471),
.RN(n770), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(mux_sal[4]), .CK(
d_ff5_data_out_net3611471), .RN(n776), .Q(data_output[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3611471), .RN(n772), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3611471),
.RN(n771), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(mux_sal[5]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3611471), .RN(n771), .Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n771), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3611471),
.RN(n774), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(mux_sal[6]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3611471), .RN(n773), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n770), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3611471),
.RN(n776), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(mux_sal[7]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3611471), .RN(n771), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3611471),
.RN(n771), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(mux_sal[8]), .CK(
d_ff5_data_out_net3611471), .RN(n773), .Q(data_output[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3611471), .RN(n772), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n774), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3611471),
.RN(n777), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(mux_sal[9]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3611471), .RN(n774), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n774), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3611471), .RN(n772), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(mux_sal[10]), .CK(
d_ff5_data_out_net3611471), .RN(n771), .Q(data_output[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3611471), .RN(n777), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3611471), .RN(n774), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(mux_sal[11]), .CK(
d_ff5_data_out_net3611471), .RN(n770), .Q(data_output[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3611471), .RN(n776), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n772), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3611471), .RN(n770), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(mux_sal[12]), .CK(
d_ff5_data_out_net3611471), .RN(n772), .Q(data_output[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3611471), .RN(n773), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3611471), .RN(n776), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(mux_sal[13]), .CK(
d_ff5_data_out_net3611471), .RN(n773), .Q(data_output[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3611471), .RN(n770), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n771), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3611471), .RN(n771), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(mux_sal[14]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3611471), .RN(n772), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n774), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3611471), .RN(n773), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(mux_sal[15]), .CK(
d_ff5_data_out_net3611471), .RN(n776), .Q(data_output[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3611471), .RN(n770), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n772), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(mux_sal[16]), .CK(
d_ff5_data_out_net3611471), .RN(n768), .Q(data_output[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3611471), .RN(n767), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3611471), .RN(n769), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(mux_sal[17]), .CK(
d_ff5_data_out_net3611471), .RN(n775), .Q(data_output[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3611471), .RN(n767), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n784), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3611471), .RN(n785), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(mux_sal[18]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3611471), .RN(n769), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n775), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3611471), .RN(n773), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(mux_sal[19]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3611471), .RN(n774), .Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3611471), .RN(n774), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(mux_sal[20]), .CK(
d_ff5_data_out_net3611471), .RN(n770), .Q(data_output[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3611471), .RN(n773), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n771), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3611471), .RN(n772), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(mux_sal[21]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3611471), .RN(n770), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3611471), .RN(n769), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(mux_sal[22]), .CK(
d_ff5_data_out_net3611471), .RN(n776), .Q(data_output[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3611471), .RN(n769), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n775), .Q(d_ff2_Y[23]), .QN(n613)
);
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(mux_sal[23]), .CK(
d_ff5_data_out_net3611471), .RN(n765), .Q(data_output[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3611471), .RN(n765), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(mux_sal[24]), .CK(
d_ff5_data_out_net3611471), .RN(n780), .Q(data_output[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3611471), .RN(n785), .Q(d_ff_Yn[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(mux_sal[25]), .CK(
d_ff5_data_out_net3611471), .RN(n769), .Q(data_output[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3611471), .RN(n775), .Q(d_ff_Yn[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(mux_sal[26]), .CK(
d_ff5_data_out_net3611471), .RN(n769), .Q(data_output[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3611471), .RN(n775), .Q(d_ff_Yn[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(mux_sal[27]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3611471), .RN(n768), .Q(d_ff_Yn[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n764), .Q(d_ff2_Y[28]), .QN(n763)
);
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(mux_sal[28]), .CK(
d_ff5_data_out_net3611471), .RN(n769), .Q(data_output[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3611471), .RN(n775), .Q(d_ff_Yn[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(mux_sal[29]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3611471), .RN(n765), .Q(d_ff_Yn[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(mux_sal[30]), .CK(
d_ff5_data_out_net3611471), .RN(n768), .Q(data_output[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3611471), .RN(n768), .Q(d_ff_Yn[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(fmtted_Result_31_), .CK(
d_ff5_data_out_net3611471), .RN(n768), .Q(data_output[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3611471), .RN(n768), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3611471), .RN(n768), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Z[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3611471), .RN(n768), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Z[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3611471), .RN(n768), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Z[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3611471), .RN(n790), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n764), .Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3611471), .RN(n790), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n764), .Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Z[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3611471), .RN(n154), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3611471), .RN(n154), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3611471), .RN(n154), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3611471), .RN(n154), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3611471), .RN(n790), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n764), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[31]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[31]), .CK(reg_shift_y_net3611471),
.RN(n790), .Q(d_ff3_sign_out) );
DFFSX2TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n790), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(reg_shift_y_net3611471), .RN(n764), .Q(d_ff3_LUT_out[27]) );
DFFRX1TS VAR_CONT_temp_reg_1_ ( .D(n519), .CK(clk), .RN(n781), .Q(
cont_var_out[1]), .QN(n760) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n518), .CK(clk), .RN(n786), .Q(
cont_var_out[0]), .QN(n759) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n758), .CK(ITER_CONT_net3611507), .RN(
n778), .Q(cont_iter_out[0]), .QN(n758) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(ITER_CONT_N5), .CK(ITER_CONT_net3611507),
.RN(n781), .Q(cont_iter_out[3]), .QN(n757) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(ITER_CONT_N4), .CK(ITER_CONT_net3611507),
.RN(n779), .Q(cont_iter_out[2]), .QN(n756) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n779), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n785), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n778), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_X[29]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3611471),
.RN(n784), .Q(d_ff1_operation_out) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_Y[29]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n154), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX4TS ITER_CONT_temp_reg_1_ ( .D(ITER_CONT_N3), .CK(ITER_CONT_net3611507),
.RN(n789), .Q(cont_iter_out[1]), .QN(n761) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n774), .Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n785), .Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n775), .Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n769), .Q(d_ff2_Y[24]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n788), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n154), .Q(
inst_CORDIC_FSM_v3_state_reg[6]) );
ADDFX1TS intadd_423_U4 ( .A(n761), .B(d_ff2_X[24]), .CI(intadd_423_CI), .CO(
intadd_423_n3), .S(sh_exp_x[1]) );
ADDFX1TS intadd_424_U4 ( .A(d_ff2_Y[24]), .B(n761), .CI(intadd_424_CI), .CO(
intadd_424_n3), .S(sh_exp_y[1]) );
ADDFX1TS intadd_424_U3 ( .A(d_ff2_Y[25]), .B(n756), .CI(intadd_424_n3), .CO(
intadd_424_n2), .S(sh_exp_y[2]) );
ADDFX1TS intadd_423_U3 ( .A(d_ff2_X[25]), .B(n756), .CI(intadd_423_n3), .CO(
intadd_423_n2), .S(sh_exp_x[2]) );
ADDFX1TS intadd_423_U2 ( .A(d_ff2_X[26]), .B(n757), .CI(intadd_423_n2), .CO(
intadd_423_n1), .S(sh_exp_x[3]) );
ADDFX1TS intadd_424_U2 ( .A(d_ff2_Y[26]), .B(n757), .CI(intadd_424_n2), .CO(
intadd_424_n1), .S(sh_exp_y[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Y[30]) );
AOI222X1TS U407 ( .A0(n739), .A1(d_ff2_X[30]), .B0(n691), .B1(d_ff2_Y[30]),
.C0(n741), .C1(d_ff2_Z[30]), .Y(n680) );
NAND3BX1TS U408 ( .AN(inst_CORDIC_FSM_v3_state_reg[6]), .B(n628), .C(
inst_CORDIC_FSM_v3_state_reg[4]), .Y(n721) );
CLKINVX6TS U409 ( .A(n708), .Y(n605) );
OR2X4TS U410 ( .A(cont_iter_out[2]), .B(n698), .Y(n615) );
OR2X2TS U411 ( .A(n760), .B(cont_var_out[0]), .Y(n659) );
CLKINVX6TS U412 ( .A(rst), .Y(n154) );
NAND2BXLTS U413 ( .AN(n611), .B(n635), .Y(n623) );
NAND3XLTS U414 ( .A(n721), .B(n694), .C(n697), .Y(n748) );
AOI222X1TS U415 ( .A0(n734), .A1(d_ff3_sh_y_out[0]), .B0(n691), .B1(
d_ff3_sh_x_out[0]), .C0(n741), .C1(d_ff3_LUT_out[0]), .Y(n682) );
AOI222X1TS U416 ( .A0(n739), .A1(d_ff3_sh_y_out[1]), .B0(n691), .B1(
d_ff3_sh_x_out[1]), .C0(n736), .C1(d_ff3_LUT_out[1]), .Y(n675) );
AOI222X1TS U417 ( .A0(n725), .A1(d_ff3_sh_y_out[2]), .B0(n691), .B1(
d_ff3_sh_x_out[2]), .C0(n741), .C1(d_ff3_LUT_out[2]), .Y(n676) );
AOI222X1TS U418 ( .A0(n734), .A1(d_ff3_sh_y_out[4]), .B0(n691), .B1(
d_ff3_sh_x_out[4]), .C0(n736), .C1(d_ff3_LUT_out[4]), .Y(n670) );
AOI222X1TS U419 ( .A0(n739), .A1(d_ff2_X[0]), .B0(n691), .B1(d_ff2_Y[0]),
.C0(n736), .C1(d_ff2_Z[0]), .Y(n684) );
AOI222X1TS U420 ( .A0(n734), .A1(d_ff2_X[11]), .B0(n687), .B1(d_ff2_Y[11]),
.C0(n741), .C1(d_ff2_Z[11]), .Y(n645) );
AOI222X1TS U421 ( .A0(n734), .A1(d_ff2_X[14]), .B0(n687), .B1(d_ff2_Y[14]),
.C0(n736), .C1(d_ff2_Z[14]), .Y(n643) );
AOI222X1TS U422 ( .A0(n739), .A1(d_ff2_X[16]), .B0(n687), .B1(d_ff2_Y[16]),
.C0(n690), .C1(d_ff2_Z[16]), .Y(n644) );
AOI222X1TS U423 ( .A0(n739), .A1(d_ff2_X[18]), .B0(n687), .B1(d_ff2_Y[18]),
.C0(n741), .C1(d_ff2_Z[18]), .Y(n646) );
AOI222X1TS U424 ( .A0(n734), .A1(d_ff2_X[20]), .B0(n687), .B1(d_ff2_Y[20]),
.C0(n736), .C1(d_ff2_Z[20]), .Y(n652) );
AOI222X1TS U425 ( .A0(n725), .A1(d_ff2_X[22]), .B0(n687), .B1(d_ff2_Y[22]),
.C0(n690), .C1(d_ff2_Z[22]), .Y(n651) );
AOI222X1TS U426 ( .A0(n739), .A1(d_ff2_X[24]), .B0(n691), .B1(d_ff2_Y[24]),
.C0(n741), .C1(d_ff2_Z[24]), .Y(n672) );
AOI222X1TS U427 ( .A0(n734), .A1(d_ff2_X[25]), .B0(n691), .B1(d_ff2_Y[25]),
.C0(n690), .C1(d_ff2_Z[25]), .Y(n689) );
AOI222X1TS U428 ( .A0(n725), .A1(d_ff2_X[26]), .B0(n691), .B1(d_ff2_Y[26]),
.C0(n690), .C1(d_ff2_Z[26]), .Y(n693) );
AOI222X1TS U429 ( .A0(n739), .A1(d_ff2_X[27]), .B0(n691), .B1(d_ff2_Y[27]),
.C0(n736), .C1(d_ff2_Z[27]), .Y(n685) );
AOI222X1TS U430 ( .A0(n734), .A1(d_ff2_X[29]), .B0(n691), .B1(d_ff2_Y[29]),
.C0(n690), .C1(d_ff2_Z[29]), .Y(n673) );
OR4X2TS U431 ( .A(n611), .B(inst_CORDIC_FSM_v3_state_reg[1]), .C(
inst_CORDIC_FSM_v3_state_reg[0]), .D(inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n607) );
INVX2TS U432 ( .A(n607), .Y(n609) );
NAND3X2TS U433 ( .A(n757), .B(n758), .C(n761), .Y(n698) );
NOR2X2TS U434 ( .A(n697), .B(n659), .Y(enab_d_ff4_Zn) );
BUFX4TS U435 ( .A(n766), .Y(n768) );
BUFX6TS U436 ( .A(n154), .Y(n769) );
BUFX4TS U437 ( .A(n771), .Y(n788) );
BUFX4TS U438 ( .A(n789), .Y(n785) );
BUFX4TS U439 ( .A(n781), .Y(n784) );
BUFX4TS U440 ( .A(n779), .Y(n780) );
BUFX4TS U441 ( .A(n769), .Y(n776) );
BUFX4TS U442 ( .A(n769), .Y(n777) );
BUFX4TS U443 ( .A(n769), .Y(n774) );
BUFX4TS U444 ( .A(n770), .Y(n773) );
NOR2X4TS U445 ( .A(n756), .B(n757), .Y(n742) );
BUFX6TS U446 ( .A(n642), .Y(n741) );
BUFX6TS U447 ( .A(n642), .Y(n690) );
BUFX4TS U448 ( .A(n642), .Y(n736) );
INVX2TS U449 ( .A(n608), .Y(n610) );
INVX2TS U450 ( .A(n606), .Y(n611) );
CLKINVX3TS U451 ( .A(n615), .Y(n710) );
CLKINVX6TS U452 ( .A(n708), .Y(n707) );
INVX2TS U453 ( .A(n708), .Y(n706) );
INVX4TS U454 ( .A(n696), .Y(n692) );
CLKINVX6TS U455 ( .A(n696), .Y(n734) );
CLKINVX3TS U456 ( .A(n696), .Y(n725) );
CLKINVX6TS U457 ( .A(n696), .Y(n739) );
CLKINVX6TS U458 ( .A(n659), .Y(n738) );
CLKINVX6TS U459 ( .A(n659), .Y(n733) );
AOI222X1TS U460 ( .A0(n734), .A1(d_ff2_X[28]), .B0(n691), .B1(d_ff2_Y[28]),
.C0(n690), .C1(d_ff2_Z[28]), .Y(n686) );
INVX3TS U461 ( .A(n659), .Y(n691) );
NOR3BX2TS U462 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n621), .Y(ready_cordic) );
NOR3BX2TS U463 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .C(n621), .Y(
inst_CORDIC_FSM_v3_state_next[3]) );
NOR2X4TS U464 ( .A(n758), .B(n761), .Y(n724) );
BUFX4TS U465 ( .A(n764), .Y(n765) );
BUFX4TS U466 ( .A(n790), .Y(n767) );
BUFX3TS U467 ( .A(n154), .Y(n790) );
OAI32X4TS U468 ( .A0(n612), .A1(d_ff1_operation_out), .A2(n610), .B0(
d_ff1_shift_region_flag_out_0_), .B1(n701), .Y(n702) );
AOI21X2TS U469 ( .A0(cont_iter_out[2]), .A1(n757), .B0(n616), .Y(n637) );
NAND4BXLTS U470 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(n611), .C(n636),
.D(n635), .Y(n638) );
INVX4TS U471 ( .A(n714), .Y(n713) );
CLKINVX3TS U472 ( .A(n700), .Y(n714) );
INVX3TS U473 ( .A(n659), .Y(n687) );
NOR2XLTS U474 ( .A(n697), .B(n696), .Y(enab_d_ff4_Yn) );
OR2X1TS U475 ( .A(d_ff_Xn[28]), .B(n710), .Y(first_mux_X[28]) );
OR2X1TS U476 ( .A(d_ff_Xn[20]), .B(n706), .Y(first_mux_X[20]) );
OR2X1TS U477 ( .A(d_ff_Xn[14]), .B(n605), .Y(first_mux_X[14]) );
OR2X1TS U478 ( .A(d_ff_Xn[1]), .B(n707), .Y(first_mux_X[1]) );
OAI21XLTS U479 ( .A0(n755), .A1(n762), .B0(n754), .Y(sh_exp_x[5]) );
OAI21XLTS U480 ( .A0(cont_iter_out[0]), .A1(n537), .B0(n747), .Y(n521) );
OAI21XLTS U481 ( .A0(cont_iter_out[1]), .A1(n744), .B0(n637), .Y(n534) );
NOR2X1TS U482 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .Y(n622) );
NAND2X1TS U483 ( .A(n609), .B(n622), .Y(n621) );
INVX2TS U484 ( .A(ready_add_subt), .Y(n697) );
NAND2X1TS U485 ( .A(n724), .B(n756), .Y(n630) );
OAI31X1TS U486 ( .A0(cont_iter_out[3]), .A1(cont_iter_out[1]), .A2(n756),
.B0(n630), .Y(n528) );
INVX2TS U487 ( .A(n742), .Y(n537) );
OAI31X4TS U488 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .A2(n758),
.B0(n537), .Y(n744) );
NAND2X1TS U489 ( .A(n756), .B(cont_iter_out[3]), .Y(n631) );
OAI21XLTS U490 ( .A0(n761), .A1(n744), .B0(n631), .Y(n532) );
INVX2TS U491 ( .A(n631), .Y(n616) );
NAND2X1TS U492 ( .A(n537), .B(cont_iter_out[0]), .Y(n747) );
INVX2TS U493 ( .A(n747), .Y(n746) );
NOR2X1TS U494 ( .A(n616), .B(n746), .Y(n743) );
OAI211X1TS U495 ( .A0(cont_iter_out[3]), .A1(n758), .B0(n756), .C0(n761),
.Y(n745) );
OAI21XLTS U496 ( .A0(n743), .A1(n761), .B0(n745), .Y(n526) );
BUFX3TS U497 ( .A(n154), .Y(n775) );
BUFX3TS U498 ( .A(n769), .Y(n772) );
BUFX3TS U499 ( .A(n769), .Y(n771) );
BUFX3TS U500 ( .A(n790), .Y(n778) );
BUFX3TS U501 ( .A(n764), .Y(n779) );
BUFX3TS U502 ( .A(n770), .Y(n781) );
BUFX3TS U503 ( .A(n772), .Y(n782) );
BUFX3TS U504 ( .A(n771), .Y(n789) );
BUFX3TS U505 ( .A(n154), .Y(n764) );
BUFX3TS U506 ( .A(n154), .Y(n766) );
BUFX3TS U507 ( .A(n772), .Y(n786) );
BUFX3TS U508 ( .A(n769), .Y(n770) );
BUFX3TS U509 ( .A(n766), .Y(n783) );
BUFX3TS U510 ( .A(n769), .Y(n787) );
BUFX3TS U511 ( .A(n615), .Y(n709) );
INVX4TS U512 ( .A(n709), .Y(n718) );
BUFX3TS U513 ( .A(n615), .Y(n708) );
AO22XLTS U514 ( .A0(n718), .A1(d_ff1_Z[0]), .B0(n708), .B1(d_ff_Zn[0]), .Y(
first_mux_Z[0]) );
AO22XLTS U515 ( .A0(n718), .A1(d_ff1_Z[29]), .B0(n708), .B1(d_ff_Zn[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U516 ( .A0(n718), .A1(d_ff1_Z[30]), .B0(n708), .B1(d_ff_Zn[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U517 ( .A0(n718), .A1(d_ff1_Z[31]), .B0(n708), .B1(d_ff_Zn[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U518 ( .A0(n718), .A1(d_ff1_Z[28]), .B0(n615), .B1(d_ff_Zn[28]),
.Y(first_mux_Z[28]) );
NAND2X1TS U519 ( .A(n637), .B(n747), .Y(n523) );
OR2X2TS U520 ( .A(n759), .B(cont_var_out[1]), .Y(n696) );
AOI22X1TS U521 ( .A0(n739), .A1(d_ff3_sh_y_out[20]), .B0(n733), .B1(
d_ff3_sh_x_out[20]), .Y(n617) );
NAND2X1TS U522 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n720) );
INVX2TS U523 ( .A(n720), .Y(n642) );
NAND2X1TS U524 ( .A(n741), .B(d_ff3_LUT_out[15]), .Y(n619) );
NAND2X1TS U525 ( .A(n617), .B(n619), .Y(add_subt_dataB[20]) );
AOI22X1TS U526 ( .A0(n734), .A1(d_ff3_sh_y_out[15]), .B0(n733), .B1(
d_ff3_sh_x_out[15]), .Y(n618) );
NAND2X1TS U527 ( .A(n618), .B(n619), .Y(add_subt_dataB[15]) );
AOI22X1TS U528 ( .A0(n739), .A1(d_ff3_sh_y_out[17]), .B0(n733), .B1(
d_ff3_sh_x_out[17]), .Y(n620) );
NAND2X1TS U529 ( .A(n620), .B(n619), .Y(add_subt_dataB[17]) );
NOR3BX1TS U530 ( .AN(n622), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n635) );
NOR2X1TS U531 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n636) );
NAND3BXLTS U532 ( .AN(n623), .B(inst_CORDIC_FSM_v3_state_reg[1]), .C(n636),
.Y(n633) );
NOR2X1TS U533 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(n623), .Y(n629) );
NAND3BX1TS U534 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n629), .Y(n719) );
NAND2X1TS U535 ( .A(n633), .B(n719), .Y(enab_d_ff_RB1) );
AOI22X1TS U536 ( .A0(n725), .A1(d_ff3_sh_y_out[28]), .B0(n733), .B1(
d_ff3_sh_x_out[28]), .Y(n624) );
NAND2X1TS U537 ( .A(n690), .B(d_ff3_LUT_out[27]), .Y(n626) );
NAND2X1TS U538 ( .A(n624), .B(n626), .Y(add_subt_dataB[28]) );
AOI22X1TS U539 ( .A0(n734), .A1(d_ff3_sh_y_out[29]), .B0(n733), .B1(
d_ff3_sh_x_out[29]), .Y(n625) );
NAND2X1TS U540 ( .A(n625), .B(n626), .Y(add_subt_dataB[29]) );
AOI22X1TS U541 ( .A0(n739), .A1(d_ff3_sh_y_out[27]), .B0(n733), .B1(
d_ff3_sh_x_out[27]), .Y(n627) );
NAND2X1TS U542 ( .A(n627), .B(n626), .Y(add_subt_dataB[27]) );
NOR3BX1TS U543 ( .AN(n609), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n628) );
NAND3BX1TS U544 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .C(n628), .Y(n694) );
INVX2TS U545 ( .A(n694), .Y(enab_cont_iter) );
NAND3BX1TS U546 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n629), .Y(n722) );
NAND2X1TS U547 ( .A(n721), .B(n722), .Y(beg_add_subt) );
NAND2X1TS U548 ( .A(n613), .B(cont_iter_out[0]), .Y(intadd_424_CI) );
OAI21XLTS U549 ( .A0(cont_iter_out[0]), .A1(n613), .B0(intadd_424_CI), .Y(
sh_exp_y[0]) );
NAND2X1TS U550 ( .A(n614), .B(cont_iter_out[0]), .Y(intadd_423_CI) );
OAI21XLTS U551 ( .A0(cont_iter_out[0]), .A1(n614), .B0(intadd_423_CI), .Y(
sh_exp_x[0]) );
NOR2X1TS U552 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .Y(n632) );
NOR2XLTS U553 ( .A(n724), .B(n632), .Y(ITER_CONT_N3) );
OAI21XLTS U554 ( .A0(n742), .A1(cont_iter_out[1]), .B0(n637), .Y(n536) );
OAI211XLTS U555 ( .A0(n632), .A1(n631), .B0(n630), .C0(n698), .Y(n527) );
NOR2X1TS U556 ( .A(d_ff2_Y[27]), .B(intadd_424_n1), .Y(n752) );
OR3X1TS U557 ( .A(d_ff2_Y[28]), .B(d_ff2_Y[27]), .C(intadd_424_n1), .Y(n751)
);
OAI21XLTS U558 ( .A0(n752), .A1(n763), .B0(n751), .Y(sh_exp_y[5]) );
NOR2X1TS U559 ( .A(d_ff2_X[27]), .B(intadd_423_n1), .Y(n755) );
OR3X1TS U560 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(intadd_423_n1), .Y(n754)
);
NAND2X1TS U561 ( .A(cont_iter_out[2]), .B(n724), .Y(n723) );
CLKAND2X2TS U562 ( .A(n723), .B(n757), .Y(n529) );
NOR2X1TS U563 ( .A(n757), .B(n723), .Y(n634) );
NOR2XLTS U564 ( .A(n634), .B(n529), .Y(ITER_CONT_N5) );
OR2X1TS U565 ( .A(d_ff_Xn[24]), .B(n710), .Y(first_mux_X[24]) );
OR2X1TS U566 ( .A(d_ff_Xn[27]), .B(n710), .Y(first_mux_X[27]) );
OR2X1TS U567 ( .A(d_ff_Xn[25]), .B(n710), .Y(first_mux_X[25]) );
OR2X1TS U568 ( .A(d_ff_Xn[29]), .B(n710), .Y(first_mux_X[29]) );
OR2X1TS U569 ( .A(d_ff_Xn[26]), .B(n710), .Y(first_mux_X[26]) );
OR2X1TS U570 ( .A(d_ff_Xn[7]), .B(n710), .Y(first_mux_X[7]) );
OR2X1TS U571 ( .A(d_ff_Xn[13]), .B(n710), .Y(first_mux_X[13]) );
OAI21XLTS U572 ( .A0(n634), .A1(n694), .B0(n633), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
OR2X1TS U573 ( .A(d_ff_Xn[2]), .B(n707), .Y(first_mux_X[2]) );
OR2X1TS U574 ( .A(d_ff_Xn[5]), .B(n706), .Y(first_mux_X[5]) );
OR2X1TS U575 ( .A(d_ff_Xn[17]), .B(n605), .Y(first_mux_X[17]) );
OR2X1TS U576 ( .A(d_ff_Xn[3]), .B(n707), .Y(first_mux_X[3]) );
OR2X1TS U577 ( .A(d_ff_Xn[10]), .B(n707), .Y(first_mux_X[10]) );
OR2X1TS U578 ( .A(d_ff_Xn[6]), .B(n706), .Y(first_mux_X[6]) );
OR2X1TS U579 ( .A(d_ff_Xn[16]), .B(n605), .Y(first_mux_X[16]) );
OR2X1TS U580 ( .A(d_ff_Xn[12]), .B(n707), .Y(first_mux_X[12]) );
OR2X1TS U581 ( .A(d_ff_Xn[19]), .B(n707), .Y(first_mux_X[19]) );
OAI21XLTS U582 ( .A0(n741), .A1(n721), .B0(n638), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
OAI21X1TS U583 ( .A0(n742), .A1(n761), .B0(n637), .Y(n535) );
OR2X1TS U584 ( .A(n535), .B(n746), .Y(n522) );
INVX2TS U585 ( .A(ready_cordic), .Y(n705) );
NAND3XLTS U586 ( .A(enab_cont_iter), .B(n742), .C(n724), .Y(n704) );
OAI21XLTS U587 ( .A0(ack_cordic), .A1(n705), .B0(n704), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
INVX2TS U588 ( .A(n638), .Y(enab_RB3) );
NOR4X1TS U589 ( .A(enab_cont_iter), .B(enab_RB3), .C(enab_d_ff_RB1), .D(
beg_add_subt), .Y(n640) );
INVX2TS U590 ( .A(inst_CORDIC_FSM_v3_state_next[3]), .Y(n639) );
AOI32X1TS U591 ( .A0(n640), .A1(n705), .A2(n639), .B0(ready_cordic), .B1(
ack_cordic), .Y(n641) );
OAI21XLTS U592 ( .A0(beg_fsm_cordic), .A1(n719), .B0(n641), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
INVX2TS U593 ( .A(n643), .Y(add_subt_dataA[14]) );
INVX2TS U594 ( .A(n644), .Y(add_subt_dataA[16]) );
INVX2TS U595 ( .A(n645), .Y(add_subt_dataA[11]) );
INVX2TS U596 ( .A(n646), .Y(add_subt_dataA[18]) );
AOI222X1TS U597 ( .A0(n734), .A1(d_ff2_X[4]), .B0(n738), .B1(d_ff2_Y[4]),
.C0(n741), .C1(d_ff2_Z[4]), .Y(n647) );
INVX2TS U598 ( .A(n647), .Y(add_subt_dataA[4]) );
AOI222X1TS U599 ( .A0(n739), .A1(d_ff2_X[2]), .B0(n738), .B1(d_ff2_Y[2]),
.C0(n736), .C1(d_ff2_Z[2]), .Y(n648) );
INVX2TS U600 ( .A(n648), .Y(add_subt_dataA[2]) );
AOI222X1TS U601 ( .A0(n734), .A1(d_ff2_X[9]), .B0(n738), .B1(d_ff2_Y[9]),
.C0(n690), .C1(d_ff2_Z[9]), .Y(n649) );
INVX2TS U602 ( .A(n649), .Y(add_subt_dataA[9]) );
AOI222X1TS U603 ( .A0(n739), .A1(d_ff2_X[10]), .B0(n738), .B1(d_ff2_Y[10]),
.C0(n690), .C1(d_ff2_Z[10]), .Y(n650) );
INVX2TS U604 ( .A(n650), .Y(add_subt_dataA[10]) );
INVX2TS U605 ( .A(n651), .Y(add_subt_dataA[22]) );
INVX2TS U606 ( .A(n652), .Y(add_subt_dataA[20]) );
AOI222X1TS U607 ( .A0(n734), .A1(d_ff2_X[1]), .B0(n738), .B1(d_ff2_Y[1]),
.C0(n741), .C1(d_ff2_Z[1]), .Y(n653) );
INVX2TS U608 ( .A(n653), .Y(add_subt_dataA[1]) );
AOI222X1TS U609 ( .A0(n725), .A1(d_ff2_X[7]), .B0(n738), .B1(d_ff2_Y[7]),
.C0(n736), .C1(d_ff2_Z[7]), .Y(n654) );
INVX2TS U610 ( .A(n654), .Y(add_subt_dataA[7]) );
AOI222X1TS U611 ( .A0(n739), .A1(d_ff2_X[6]), .B0(n738), .B1(d_ff2_Y[6]),
.C0(n736), .C1(d_ff2_Z[6]), .Y(n655) );
INVX2TS U612 ( .A(n655), .Y(add_subt_dataA[6]) );
AOI222X1TS U613 ( .A0(n734), .A1(d_ff2_X[3]), .B0(n738), .B1(d_ff2_Y[3]),
.C0(n736), .C1(d_ff2_Z[3]), .Y(n656) );
INVX2TS U614 ( .A(n656), .Y(add_subt_dataA[3]) );
AOI222X1TS U615 ( .A0(n725), .A1(d_ff2_X[8]), .B0(n738), .B1(d_ff2_Y[8]),
.C0(n690), .C1(d_ff2_Z[8]), .Y(n657) );
INVX2TS U616 ( .A(n657), .Y(add_subt_dataA[8]) );
AOI222X1TS U617 ( .A0(n739), .A1(d_ff2_X[5]), .B0(n738), .B1(d_ff2_Y[5]),
.C0(n690), .C1(d_ff2_Z[5]), .Y(n658) );
INVX2TS U618 ( .A(n658), .Y(add_subt_dataA[5]) );
AOI222X1TS U619 ( .A0(n692), .A1(d_ff3_sh_y_out[24]), .B0(n738), .B1(
d_ff3_sh_x_out[24]), .C0(n690), .C1(d_ff3_LUT_out[24]), .Y(n660) );
INVX2TS U620 ( .A(n660), .Y(add_subt_dataB[24]) );
AOI222X1TS U621 ( .A0(n692), .A1(d_ff3_sh_y_out[21]), .B0(n738), .B1(
d_ff3_sh_x_out[21]), .C0(n741), .C1(d_ff3_LUT_out[21]), .Y(n661) );
INVX2TS U622 ( .A(n661), .Y(add_subt_dataB[21]) );
AOI222X1TS U623 ( .A0(n692), .A1(d_ff3_sh_y_out[9]), .B0(n738), .B1(
d_ff3_sh_x_out[9]), .C0(n736), .C1(d_ff3_LUT_out[9]), .Y(n662) );
INVX2TS U624 ( .A(n662), .Y(add_subt_dataB[9]) );
AOI222X1TS U625 ( .A0(n692), .A1(d_ff3_sh_y_out[26]), .B0(n738), .B1(
d_ff3_sh_x_out[26]), .C0(n741), .C1(d_ff3_LUT_out[26]), .Y(n663) );
INVX2TS U626 ( .A(n663), .Y(add_subt_dataB[26]) );
AOI222X1TS U627 ( .A0(n692), .A1(d_ff3_sh_y_out[6]), .B0(n738), .B1(
d_ff3_sh_x_out[6]), .C0(n690), .C1(d_ff3_LUT_out[6]), .Y(n664) );
INVX2TS U628 ( .A(n664), .Y(add_subt_dataB[6]) );
AOI222X1TS U629 ( .A0(n692), .A1(d_ff3_sh_y_out[23]), .B0(n738), .B1(
d_ff3_sh_x_out[23]), .C0(n741), .C1(d_ff3_LUT_out[23]), .Y(n665) );
INVX2TS U630 ( .A(n665), .Y(add_subt_dataB[23]) );
AOI222X1TS U631 ( .A0(n692), .A1(d_ff3_sh_y_out[10]), .B0(n738), .B1(
d_ff3_sh_x_out[10]), .C0(n736), .C1(d_ff3_LUT_out[10]), .Y(n666) );
INVX2TS U632 ( .A(n666), .Y(add_subt_dataB[10]) );
AOI222X1TS U633 ( .A0(n692), .A1(d_ff3_sh_y_out[12]), .B0(n738), .B1(
d_ff3_sh_x_out[12]), .C0(n690), .C1(d_ff3_LUT_out[12]), .Y(n667) );
INVX2TS U634 ( .A(n667), .Y(add_subt_dataB[12]) );
AOI222X1TS U635 ( .A0(n692), .A1(d_ff3_sh_y_out[25]), .B0(n738), .B1(
d_ff3_sh_x_out[25]), .C0(n741), .C1(d_ff3_LUT_out[25]), .Y(n668) );
INVX2TS U636 ( .A(n668), .Y(add_subt_dataB[25]) );
AOI222X1TS U637 ( .A0(n692), .A1(d_ff3_sh_y_out[8]), .B0(n738), .B1(
d_ff3_sh_x_out[8]), .C0(n736), .C1(d_ff3_LUT_out[8]), .Y(n669) );
INVX2TS U638 ( .A(n669), .Y(add_subt_dataB[8]) );
INVX2TS U639 ( .A(n670), .Y(add_subt_dataB[4]) );
AOI222X1TS U640 ( .A0(n692), .A1(d_ff2_X[19]), .B0(n687), .B1(d_ff2_Y[19]),
.C0(n736), .C1(d_ff2_Z[19]), .Y(n671) );
INVX2TS U641 ( .A(n671), .Y(add_subt_dataA[19]) );
INVX2TS U642 ( .A(n672), .Y(add_subt_dataA[24]) );
INVX2TS U643 ( .A(n673), .Y(add_subt_dataA[29]) );
AOI222X1TS U644 ( .A0(n692), .A1(d_ff2_X[23]), .B0(n687), .B1(d_ff2_Y[23]),
.C0(n741), .C1(d_ff2_Z[23]), .Y(n674) );
INVX2TS U645 ( .A(n674), .Y(add_subt_dataA[23]) );
INVX2TS U646 ( .A(n675), .Y(add_subt_dataB[1]) );
INVX2TS U647 ( .A(n676), .Y(add_subt_dataB[2]) );
AOI222X1TS U648 ( .A0(n692), .A1(d_ff2_X[13]), .B0(n687), .B1(d_ff2_Y[13]),
.C0(n741), .C1(d_ff2_Z[13]), .Y(n677) );
INVX2TS U649 ( .A(n677), .Y(add_subt_dataA[13]) );
AOI222X1TS U650 ( .A0(n692), .A1(d_ff2_X[12]), .B0(n687), .B1(d_ff2_Y[12]),
.C0(n690), .C1(d_ff2_Z[12]), .Y(n678) );
INVX2TS U651 ( .A(n678), .Y(add_subt_dataA[12]) );
AOI222X1TS U652 ( .A0(n739), .A1(d_ff2_X[31]), .B0(n691), .B1(d_ff2_Y[31]),
.C0(n736), .C1(d_ff2_Z[31]), .Y(n679) );
INVX2TS U653 ( .A(n679), .Y(add_subt_dataA[31]) );
INVX2TS U654 ( .A(n680), .Y(add_subt_dataA[30]) );
AOI222X1TS U655 ( .A0(n692), .A1(d_ff2_X[15]), .B0(n687), .B1(d_ff2_Y[15]),
.C0(n736), .C1(d_ff2_Z[15]), .Y(n681) );
INVX2TS U656 ( .A(n681), .Y(add_subt_dataA[15]) );
INVX2TS U657 ( .A(n682), .Y(add_subt_dataB[0]) );
AOI222X1TS U658 ( .A0(n692), .A1(d_ff2_X[17]), .B0(n687), .B1(d_ff2_Y[17]),
.C0(n741), .C1(d_ff2_Z[17]), .Y(n683) );
INVX2TS U659 ( .A(n683), .Y(add_subt_dataA[17]) );
INVX2TS U660 ( .A(n684), .Y(add_subt_dataA[0]) );
INVX2TS U661 ( .A(n685), .Y(add_subt_dataA[27]) );
INVX2TS U662 ( .A(n686), .Y(add_subt_dataA[28]) );
AOI222X1TS U663 ( .A0(n725), .A1(d_ff2_X[21]), .B0(n687), .B1(d_ff2_Y[21]),
.C0(n690), .C1(d_ff2_Z[21]), .Y(n688) );
INVX2TS U664 ( .A(n688), .Y(add_subt_dataA[21]) );
INVX2TS U665 ( .A(n689), .Y(add_subt_dataA[25]) );
INVX2TS U666 ( .A(n693), .Y(add_subt_dataA[26]) );
INVX2TS U667 ( .A(n748), .Y(n749) );
NAND2X1TS U668 ( .A(n749), .B(cont_var_out[1]), .Y(n695) );
OAI211XLTS U669 ( .A0(n749), .A1(n696), .B0(n659), .C0(n695), .Y(n519) );
OAI21XLTS U670 ( .A0(n742), .A1(n761), .B0(n744), .Y(n531) );
NOR3XLTS U671 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n697), .Y(
enab_d_ff4_Xn) );
AOI32X1TS U673 ( .A0(cont_iter_out[3]), .A1(n698), .A2(n761), .B0(
cont_iter_out[2]), .B1(n698), .Y(data_out_LUT[4]) );
OAI22X1TS U674 ( .A0(cont_iter_out[3]), .A1(n723), .B0(cont_iter_out[2]),
.B1(n724), .Y(data_out_LUT[25]) );
NAND2X1TS U675 ( .A(d_ff1_operation_out), .B(n610), .Y(n701) );
OAI21XLTS U676 ( .A0(d_ff1_operation_out), .A1(n610), .B0(n701), .Y(n699) );
XOR2X1TS U677 ( .A(n612), .B(n699), .Y(n700) );
BUFX3TS U678 ( .A(n714), .Y(n712) );
AOI22X1TS U679 ( .A0(n715), .A1(d_ff_Yn[31]), .B0(d_ff_Xn[31]), .B1(n712),
.Y(n703) );
XNOR2X1TS U680 ( .A(n703), .B(n702), .Y(fmtted_Result_31_) );
NAND2X1TS U681 ( .A(n705), .B(n704), .Y(enab_d_ff5_data_out) );
NOR2BX1TS U682 ( .AN(d_ff_Yn[0]), .B(n605), .Y(first_mux_Y[0]) );
NOR2BX1TS U683 ( .AN(d_ff_Yn[1]), .B(n706), .Y(first_mux_Y[1]) );
NOR2BX1TS U684 ( .AN(d_ff_Yn[2]), .B(n707), .Y(first_mux_Y[2]) );
NOR2BX1TS U685 ( .AN(d_ff_Yn[3]), .B(n707), .Y(first_mux_Y[3]) );
NOR2BX1TS U686 ( .AN(d_ff_Yn[4]), .B(n605), .Y(first_mux_Y[4]) );
NOR2BX1TS U687 ( .AN(d_ff_Yn[5]), .B(n706), .Y(first_mux_Y[5]) );
NOR2BX1TS U688 ( .AN(d_ff_Yn[6]), .B(n707), .Y(first_mux_Y[6]) );
NOR2BX1TS U689 ( .AN(d_ff_Yn[7]), .B(n707), .Y(first_mux_Y[7]) );
NOR2BX1TS U690 ( .AN(d_ff_Yn[8]), .B(n706), .Y(first_mux_Y[8]) );
NOR2BX1TS U691 ( .AN(d_ff_Yn[9]), .B(n605), .Y(first_mux_Y[9]) );
NOR2BX1TS U692 ( .AN(d_ff_Yn[10]), .B(n707), .Y(first_mux_Y[10]) );
NOR2BX1TS U693 ( .AN(d_ff_Yn[11]), .B(n707), .Y(first_mux_Y[11]) );
NOR2BX1TS U694 ( .AN(d_ff_Yn[12]), .B(n707), .Y(first_mux_Y[12]) );
NOR2BX1TS U695 ( .AN(d_ff_Yn[13]), .B(n605), .Y(first_mux_Y[13]) );
NOR2BX1TS U696 ( .AN(d_ff_Yn[14]), .B(n706), .Y(first_mux_Y[14]) );
NOR2BX1TS U697 ( .AN(d_ff_Yn[15]), .B(n707), .Y(first_mux_Y[15]) );
NOR2BX1TS U698 ( .AN(d_ff_Yn[16]), .B(n707), .Y(first_mux_Y[16]) );
NOR2BX1TS U699 ( .AN(d_ff_Yn[17]), .B(n605), .Y(first_mux_Y[17]) );
NOR2BX1TS U700 ( .AN(d_ff_Yn[18]), .B(n706), .Y(first_mux_Y[18]) );
NOR2BX1TS U701 ( .AN(d_ff_Yn[19]), .B(n707), .Y(first_mux_Y[19]) );
NOR2BX1TS U702 ( .AN(d_ff_Yn[20]), .B(n707), .Y(first_mux_Y[20]) );
NOR2BX1TS U703 ( .AN(d_ff_Yn[21]), .B(n706), .Y(first_mux_Y[21]) );
NOR2BX1TS U704 ( .AN(d_ff_Yn[22]), .B(n605), .Y(first_mux_Y[22]) );
NOR2BX1TS U705 ( .AN(d_ff_Yn[23]), .B(n707), .Y(first_mux_Y[23]) );
NOR2BX1TS U706 ( .AN(d_ff_Yn[24]), .B(n605), .Y(first_mux_Y[24]) );
NOR2BX1TS U707 ( .AN(d_ff_Yn[25]), .B(n605), .Y(first_mux_Y[25]) );
NOR2BX1TS U708 ( .AN(d_ff_Yn[26]), .B(n605), .Y(first_mux_Y[26]) );
NOR2BX1TS U709 ( .AN(d_ff_Yn[27]), .B(n605), .Y(first_mux_Y[27]) );
NOR2BX1TS U710 ( .AN(d_ff_Yn[28]), .B(n605), .Y(first_mux_Y[28]) );
NOR2BX1TS U711 ( .AN(d_ff_Yn[29]), .B(n605), .Y(first_mux_Y[29]) );
NOR2BX1TS U712 ( .AN(d_ff_Yn[30]), .B(n605), .Y(first_mux_Y[30]) );
NOR2BX1TS U713 ( .AN(d_ff_Yn[31]), .B(n605), .Y(first_mux_Y[31]) );
INVX4TS U714 ( .A(n709), .Y(n711) );
AO22XLTS U715 ( .A0(n718), .A1(d_ff1_Z[1]), .B0(n615), .B1(d_ff_Zn[1]), .Y(
first_mux_Z[1]) );
AO22XLTS U716 ( .A0(n605), .A1(d_ff1_Z[2]), .B0(n708), .B1(d_ff_Zn[2]), .Y(
first_mux_Z[2]) );
AO22XLTS U717 ( .A0(n718), .A1(d_ff1_Z[3]), .B0(n708), .B1(d_ff_Zn[3]), .Y(
first_mux_Z[3]) );
AO22XLTS U718 ( .A0(n718), .A1(d_ff1_Z[4]), .B0(n708), .B1(d_ff_Zn[4]), .Y(
first_mux_Z[4]) );
AO22XLTS U719 ( .A0(n718), .A1(d_ff1_Z[5]), .B0(n708), .B1(d_ff_Zn[5]), .Y(
first_mux_Z[5]) );
AO22XLTS U720 ( .A0(n718), .A1(d_ff1_Z[6]), .B0(n709), .B1(d_ff_Zn[6]), .Y(
first_mux_Z[6]) );
AO22XLTS U721 ( .A0(n718), .A1(d_ff1_Z[7]), .B0(n709), .B1(d_ff_Zn[7]), .Y(
first_mux_Z[7]) );
AO22XLTS U722 ( .A0(n711), .A1(d_ff1_Z[8]), .B0(n709), .B1(d_ff_Zn[8]), .Y(
first_mux_Z[8]) );
AO22XLTS U723 ( .A0(n711), .A1(d_ff1_Z[9]), .B0(n709), .B1(d_ff_Zn[9]), .Y(
first_mux_Z[9]) );
AO22XLTS U724 ( .A0(n711), .A1(d_ff1_Z[10]), .B0(n709), .B1(d_ff_Zn[10]),
.Y(first_mux_Z[10]) );
AO22XLTS U725 ( .A0(n711), .A1(d_ff1_Z[11]), .B0(n709), .B1(d_ff_Zn[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U726 ( .A0(n711), .A1(d_ff1_Z[12]), .B0(n709), .B1(d_ff_Zn[12]),
.Y(first_mux_Z[12]) );
AO22XLTS U727 ( .A0(n711), .A1(d_ff1_Z[13]), .B0(n709), .B1(d_ff_Zn[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U728 ( .A0(n711), .A1(d_ff1_Z[14]), .B0(n709), .B1(d_ff_Zn[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U729 ( .A0(n718), .A1(d_ff1_Z[15]), .B0(n709), .B1(d_ff_Zn[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U730 ( .A0(n718), .A1(d_ff1_Z[16]), .B0(n709), .B1(d_ff_Zn[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U731 ( .A0(n718), .A1(d_ff1_Z[17]), .B0(n615), .B1(d_ff_Zn[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U732 ( .A0(n710), .A1(d_ff1_Z[18]), .B0(n615), .B1(d_ff_Zn[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U733 ( .A0(n718), .A1(d_ff1_Z[19]), .B0(n615), .B1(d_ff_Zn[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U734 ( .A0(n718), .A1(d_ff1_Z[20]), .B0(n615), .B1(d_ff_Zn[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U735 ( .A0(n710), .A1(d_ff1_Z[21]), .B0(n615), .B1(d_ff_Zn[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U736 ( .A0(n718), .A1(d_ff1_Z[22]), .B0(n615), .B1(d_ff_Zn[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U737 ( .A0(n710), .A1(d_ff1_Z[23]), .B0(n615), .B1(d_ff_Zn[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U738 ( .A0(n718), .A1(d_ff1_Z[24]), .B0(n615), .B1(d_ff_Zn[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U739 ( .A0(n710), .A1(d_ff1_Z[25]), .B0(n615), .B1(d_ff_Zn[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U740 ( .A0(n711), .A1(d_ff1_Z[26]), .B0(n615), .B1(d_ff_Zn[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U741 ( .A0(n711), .A1(d_ff1_Z[27]), .B0(n615), .B1(d_ff_Zn[27]),
.Y(first_mux_Z[27]) );
BUFX3TS U742 ( .A(n712), .Y(n716) );
AO22XLTS U743 ( .A0(n713), .A1(d_ff_Yn[0]), .B0(n716), .B1(d_ff_Xn[0]), .Y(
mux_sal[0]) );
AO22XLTS U744 ( .A0(n713), .A1(d_ff_Yn[1]), .B0(n712), .B1(d_ff_Xn[1]), .Y(
mux_sal[1]) );
AO22XLTS U745 ( .A0(n713), .A1(d_ff_Yn[2]), .B0(n712), .B1(d_ff_Xn[2]), .Y(
mux_sal[2]) );
AO22XLTS U746 ( .A0(n713), .A1(d_ff_Yn[3]), .B0(n712), .B1(d_ff_Xn[3]), .Y(
mux_sal[3]) );
AO22XLTS U747 ( .A0(n713), .A1(d_ff_Yn[4]), .B0(n712), .B1(d_ff_Xn[4]), .Y(
mux_sal[4]) );
AO22XLTS U748 ( .A0(n713), .A1(d_ff_Yn[5]), .B0(n712), .B1(d_ff_Xn[5]), .Y(
mux_sal[5]) );
AO22XLTS U749 ( .A0(n713), .A1(d_ff_Yn[6]), .B0(n712), .B1(d_ff_Xn[6]), .Y(
mux_sal[6]) );
AO22XLTS U750 ( .A0(n713), .A1(d_ff_Yn[7]), .B0(n712), .B1(d_ff_Xn[7]), .Y(
mux_sal[7]) );
AO22XLTS U751 ( .A0(n713), .A1(d_ff_Yn[8]), .B0(n712), .B1(d_ff_Xn[8]), .Y(
mux_sal[8]) );
AO22XLTS U752 ( .A0(n713), .A1(d_ff_Yn[9]), .B0(n712), .B1(d_ff_Xn[9]), .Y(
mux_sal[9]) );
AO22XLTS U753 ( .A0(n713), .A1(d_ff_Yn[10]), .B0(n712), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U754 ( .A0(n713), .A1(d_ff_Yn[11]), .B0(n714), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U755 ( .A0(n713), .A1(d_ff_Yn[12]), .B0(n714), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
INVX2TS U756 ( .A(n714), .Y(n715) );
AO22XLTS U757 ( .A0(n713), .A1(d_ff_Yn[13]), .B0(n714), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U758 ( .A0(n713), .A1(d_ff_Yn[14]), .B0(n714), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U759 ( .A0(n713), .A1(d_ff_Yn[15]), .B0(n714), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U760 ( .A0(n713), .A1(d_ff_Yn[16]), .B0(n714), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U761 ( .A0(n713), .A1(d_ff_Yn[17]), .B0(n714), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U762 ( .A0(n715), .A1(d_ff_Yn[18]), .B0(n712), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U763 ( .A0(n715), .A1(d_ff_Yn[19]), .B0(n716), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U764 ( .A0(n715), .A1(d_ff_Yn[20]), .B0(n716), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U765 ( .A0(n715), .A1(d_ff_Yn[21]), .B0(n716), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U766 ( .A0(n715), .A1(d_ff_Yn[22]), .B0(n716), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U767 ( .A0(n715), .A1(d_ff_Yn[23]), .B0(n716), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U768 ( .A0(n715), .A1(d_ff_Yn[24]), .B0(n716), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U769 ( .A0(n715), .A1(d_ff_Yn[25]), .B0(n716), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U770 ( .A0(n715), .A1(d_ff_Yn[26]), .B0(n716), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
INVX2TS U771 ( .A(n712), .Y(n717) );
AO22XLTS U772 ( .A0(n717), .A1(d_ff_Yn[27]), .B0(n716), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U773 ( .A0(n717), .A1(d_ff_Yn[28]), .B0(n716), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U774 ( .A0(n717), .A1(d_ff_Yn[29]), .B0(n716), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U775 ( .A0(n717), .A1(d_ff_Yn[30]), .B0(n716), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
NOR2BX1TS U776 ( .AN(d_ff_Xn[0]), .B(n711), .Y(first_mux_X[0]) );
NOR2BX1TS U777 ( .AN(d_ff_Xn[4]), .B(n711), .Y(first_mux_X[4]) );
NOR2BX1TS U778 ( .AN(d_ff_Xn[8]), .B(n711), .Y(first_mux_X[8]) );
NOR2BX1TS U779 ( .AN(d_ff_Xn[9]), .B(n711), .Y(first_mux_X[9]) );
NOR2BX1TS U780 ( .AN(d_ff_Xn[11]), .B(n711), .Y(first_mux_X[11]) );
NOR2BX1TS U781 ( .AN(d_ff_Xn[15]), .B(n711), .Y(first_mux_X[15]) );
NOR2BX1TS U782 ( .AN(d_ff_Xn[18]), .B(n711), .Y(first_mux_X[18]) );
NOR2BX1TS U783 ( .AN(d_ff_Xn[21]), .B(n707), .Y(first_mux_X[21]) );
NOR2BX1TS U784 ( .AN(d_ff_Xn[22]), .B(n605), .Y(first_mux_X[22]) );
NOR2BX1TS U785 ( .AN(d_ff_Xn[23]), .B(n706), .Y(first_mux_X[23]) );
NOR2BX1TS U786 ( .AN(d_ff_Xn[30]), .B(n707), .Y(first_mux_X[30]) );
NOR2BX1TS U787 ( .AN(d_ff_Xn[31]), .B(n711), .Y(first_mux_X[31]) );
NOR2BX1TS U788 ( .AN(beg_fsm_cordic), .B(n719), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U789 ( .A0(enab_d_ff4_Zn), .A1(n722), .B0(n721), .B1(n720), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U790 ( .AN(enab_d_ff4_Zn), .B(n722), .Y(
inst_CORDIC_FSM_v3_state_next[6]) );
OA21XLTS U791 ( .A0(cont_iter_out[2]), .A1(n724), .B0(n723), .Y(ITER_CONT_N4) );
XOR2XLTS U792 ( .A(d_ff3_sign_out), .B(cont_var_out[0]), .Y(op_add_subt) );
AO22XLTS U793 ( .A0(n725), .A1(d_ff3_sh_y_out[31]), .B0(n733), .B1(
d_ff3_sh_x_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U794 ( .A0(n734), .A1(d_ff3_sh_y_out[30]), .B0(n733), .B1(
d_ff3_sh_x_out[30]), .Y(add_subt_dataB[30]) );
AOI22X1TS U795 ( .A0(n739), .A1(d_ff3_sh_y_out[22]), .B0(n733), .B1(
d_ff3_sh_x_out[22]), .Y(n726) );
OAI2BB1X1TS U796 ( .A0N(n736), .A1N(d_ff3_LUT_out[19]), .B0(n726), .Y(
add_subt_dataB[22]) );
AOI22X1TS U797 ( .A0(n734), .A1(d_ff3_sh_y_out[19]), .B0(n733), .B1(
d_ff3_sh_x_out[19]), .Y(n727) );
OAI2BB1X1TS U798 ( .A0N(n690), .A1N(d_ff3_LUT_out[19]), .B0(n727), .Y(
add_subt_dataB[19]) );
AOI22X1TS U799 ( .A0(n725), .A1(d_ff3_sh_y_out[18]), .B0(n733), .B1(
d_ff3_sh_x_out[18]), .Y(n728) );
OAI2BB1X1TS U800 ( .A0N(n690), .A1N(d_ff3_LUT_out[13]), .B0(n728), .Y(
add_subt_dataB[18]) );
AOI22X1TS U801 ( .A0(n739), .A1(d_ff3_sh_y_out[16]), .B0(n733), .B1(
d_ff3_sh_x_out[16]), .Y(n729) );
OAI2BB1X1TS U802 ( .A0N(n741), .A1N(d_ff3_LUT_out[3]), .B0(n729), .Y(
add_subt_dataB[16]) );
AOI22X1TS U803 ( .A0(n734), .A1(d_ff3_sh_y_out[14]), .B0(n733), .B1(
d_ff3_sh_x_out[14]), .Y(n730) );
OAI2BB1X1TS U804 ( .A0N(n741), .A1N(d_ff3_LUT_out[5]), .B0(n730), .Y(
add_subt_dataB[14]) );
AOI22X1TS U805 ( .A0(n725), .A1(d_ff3_sh_y_out[13]), .B0(n733), .B1(
d_ff3_sh_x_out[13]), .Y(n731) );
OAI2BB1X1TS U806 ( .A0N(n736), .A1N(d_ff3_LUT_out[13]), .B0(n731), .Y(
add_subt_dataB[13]) );
AOI22X1TS U807 ( .A0(n739), .A1(d_ff3_sh_y_out[11]), .B0(n733), .B1(
d_ff3_sh_x_out[11]), .Y(n732) );
OAI2BB1X1TS U808 ( .A0N(n741), .A1N(d_ff3_LUT_out[7]), .B0(n732), .Y(
add_subt_dataB[11]) );
AOI22X1TS U809 ( .A0(n734), .A1(d_ff3_sh_y_out[7]), .B0(n733), .B1(
d_ff3_sh_x_out[7]), .Y(n735) );
OAI2BB1X1TS U810 ( .A0N(n690), .A1N(d_ff3_LUT_out[7]), .B0(n735), .Y(
add_subt_dataB[7]) );
AOI22X1TS U811 ( .A0(n739), .A1(d_ff3_sh_y_out[5]), .B0(n733), .B1(
d_ff3_sh_x_out[5]), .Y(n737) );
OAI2BB1X1TS U812 ( .A0N(n690), .A1N(d_ff3_LUT_out[5]), .B0(n737), .Y(
add_subt_dataB[5]) );
AOI22X1TS U813 ( .A0(n734), .A1(d_ff3_sh_y_out[3]), .B0(n733), .B1(
d_ff3_sh_x_out[3]), .Y(n740) );
OAI2BB1X1TS U814 ( .A0N(n736), .A1N(d_ff3_LUT_out[3]), .B0(n740), .Y(
add_subt_dataB[3]) );
AOI22X1TS U815 ( .A0(cont_iter_out[1]), .A1(n744), .B0(n742), .B1(n761), .Y(
n533) );
AOI22X1TS U816 ( .A0(cont_iter_out[1]), .A1(n744), .B0(n743), .B1(n761), .Y(
n525) );
OAI2BB1X1TS U817 ( .A0N(cont_iter_out[1]), .A1N(n523), .B0(n745), .Y(n524)
);
AOI22X1TS U818 ( .A0(cont_iter_out[1]), .A1(n747), .B0(n746), .B1(n761), .Y(
n520) );
AOI22X1TS U819 ( .A0(n749), .A1(n759), .B0(cont_var_out[0]), .B1(n748), .Y(
n518) );
NOR2XLTS U821 ( .A(d_ff2_Y[29]), .B(n751), .Y(n750) );
XOR2XLTS U822 ( .A(d_ff2_Y[30]), .B(n750), .Y(sh_exp_y[7]) );
XNOR2X1TS U823 ( .A(d_ff2_Y[29]), .B(n751), .Y(sh_exp_y[6]) );
AO21XLTS U824 ( .A0(intadd_424_n1), .A1(d_ff2_Y[27]), .B0(n752), .Y(
sh_exp_y[4]) );
NOR2XLTS U825 ( .A(d_ff2_X[29]), .B(n754), .Y(n753) );
XOR2XLTS U826 ( .A(d_ff2_X[30]), .B(n753), .Y(sh_exp_x[7]) );
XNOR2X1TS U827 ( .A(d_ff2_X[29]), .B(n754), .Y(sh_exp_x[6]) );
AO21XLTS U828 ( .A0(intadd_423_n1), .A1(d_ff2_X[27]), .B0(n755), .Y(
sh_exp_x[4]) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fei4_rx
#(
parameter BASEADDR = 32'h0000,
parameter HIGHADDR = 32'h0000,
parameter DSIZE = 10,
parameter DATA_IDENTIFIER = 0,
parameter ABUSWIDTH = 16,
parameter USE_FIFO_CLK = 0
)
(
input wire RX_CLK,
input wire RX_CLK2X,
input wire DATA_CLK,
input wire RX_DATA,
output wire RX_READY,
output wire RX_8B10B_DECODER_ERR,
output wire RX_FIFO_OVERFLOW_ERR,
input wire FIFO_CLK,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
output wire RX_FIFO_FULL,
output wire RX_ENABLED,
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
wire FIFO_CLK_INT;
generate
if (USE_FIFO_CLK == 0)
assign FIFO_CLK_INT = BUS_CLK;
else
assign FIFO_CLK_INT = FIFO_CLK;
endgenerate
fei4_rx_core
#(
.DSIZE(DSIZE),
.DATA_IDENTIFIER(DATA_IDENTIFIER),
.ABUSWIDTH(ABUSWIDTH)
) i_fei4_rx_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.RX_CLK(RX_CLK),
.RX_CLK2X(RX_CLK2X),
.DATA_CLK(DATA_CLK),
.RX_DATA(RX_DATA),
.RX_READY(RX_READY),
.RX_8B10B_DECODER_ERR(RX_8B10B_DECODER_ERR),
.RX_FIFO_OVERFLOW_ERR(RX_FIFO_OVERFLOW_ERR),
.FIFO_CLK(FIFO_CLK_INT),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.RX_FIFO_FULL(RX_FIFO_FULL),
.RX_ENABLED(RX_ENABLED)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A32OI_BEHAVIORAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 nand0_out ;
wire B1 nand1_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_BEHAVIORAL_PP_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_7_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_7_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_7_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_7_e
//
// No `defines in this module
module inst_7_e
//
// Generated Module inst_7
//
(
);
// Module parameters:
parameter FOO = 34;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_7_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_qspi_media(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [7:0] io_ctrl_dla_cssck,
input [7:0] io_ctrl_dla_sckcs,
input [7:0] io_ctrl_dla_intercs,
input [7:0] io_ctrl_dla_interxfr,
input io_ctrl_cs_id,
input io_ctrl_cs_dflt_0,
output io_link_tx_ready,
input io_link_tx_valid,
input [7:0] io_link_tx_bits,
output io_link_rx_valid,
output [7:0] io_link_rx_bits,
input [7:0] io_link_cnt,
input [1:0] io_link_fmt_proto,
input io_link_fmt_endian,
input io_link_fmt_iodir,
input io_link_cs_set,
input io_link_cs_clear,
input io_link_cs_hold,
output io_link_active
);
wire phy_clock;
wire phy_reset;
wire phy_io_port_sck;
wire phy_io_port_dq_0_i;
wire phy_io_port_dq_0_o;
wire phy_io_port_dq_0_oe;
wire phy_io_port_dq_1_i;
wire phy_io_port_dq_1_o;
wire phy_io_port_dq_1_oe;
wire phy_io_port_dq_2_i;
wire phy_io_port_dq_2_o;
wire phy_io_port_dq_2_oe;
wire phy_io_port_dq_3_i;
wire phy_io_port_dq_3_o;
wire phy_io_port_dq_3_oe;
wire phy_io_port_cs_0;
wire [11:0] phy_io_ctrl_sck_div;
wire phy_io_ctrl_sck_pol;
wire phy_io_ctrl_sck_pha;
wire [1:0] phy_io_ctrl_fmt_proto;
wire phy_io_ctrl_fmt_endian;
wire phy_io_ctrl_fmt_iodir;
wire phy_io_op_ready;
wire phy_io_op_valid;
wire phy_io_op_bits_fn;
wire phy_io_op_bits_stb;
wire [7:0] phy_io_op_bits_cnt;
wire [7:0] phy_io_op_bits_data;
wire phy_io_rx_valid;
wire [7:0] phy_io_rx_bits;
reg cs_id;
reg [31:0] GEN_5;
reg cs_dflt_0;
reg [31:0] GEN_52;
reg cs_set;
reg [31:0] GEN_53;
wire [1:0] GEN_48;
wire [1:0] T_162;
wire [1:0] GEN_49;
wire [1:0] T_163;
wire T_164;
wire cs_active_0;
wire cs_update;
reg clear;
reg [31:0] GEN_54;
reg cs_assert;
reg [31:0] GEN_55;
wire T_175;
wire T_176;
wire cs_deassert;
wire T_177;
wire T_178;
wire continuous;
reg [1:0] state;
reg [31:0] GEN_56;
wire T_182;
wire [1:0] GEN_0;
wire [7:0] GEN_1;
wire [1:0] GEN_2;
wire T_184;
wire T_186;
wire [1:0] GEN_3;
wire GEN_4;
wire GEN_6;
wire GEN_7;
wire [1:0] GEN_8;
wire [7:0] GEN_9;
wire [1:0] GEN_10;
wire GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire T_188;
wire T_189;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire [7:0] GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire T_194;
wire T_195;
wire [7:0] GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire [7:0] GEN_26;
wire [1:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire T_198;
wire T_200;
wire T_201;
wire [1:0] GEN_36;
wire GEN_37;
wire [7:0] GEN_38;
wire [1:0] GEN_39;
wire T_202;
wire [1:0] GEN_50;
wire [1:0] T_206;
wire [1:0] GEN_51;
wire [1:0] T_207;
wire T_208;
wire T_213_0;
wire GEN_40;
wire [1:0] GEN_41;
wire [7:0] GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire [1:0] GEN_47;
sirv_qspi_physical phy (
.clock(phy_clock),
.reset(phy_reset),
.io_port_sck(phy_io_port_sck),
.io_port_dq_0_i(phy_io_port_dq_0_i),
.io_port_dq_0_o(phy_io_port_dq_0_o),
.io_port_dq_0_oe(phy_io_port_dq_0_oe),
.io_port_dq_1_i(phy_io_port_dq_1_i),
.io_port_dq_1_o(phy_io_port_dq_1_o),
.io_port_dq_1_oe(phy_io_port_dq_1_oe),
.io_port_dq_2_i(phy_io_port_dq_2_i),
.io_port_dq_2_o(phy_io_port_dq_2_o),
.io_port_dq_2_oe(phy_io_port_dq_2_oe),
.io_port_dq_3_i(phy_io_port_dq_3_i),
.io_port_dq_3_o(phy_io_port_dq_3_o),
.io_port_dq_3_oe(phy_io_port_dq_3_oe),
.io_port_cs_0(phy_io_port_cs_0),
.io_ctrl_sck_div(phy_io_ctrl_sck_div),
.io_ctrl_sck_pol(phy_io_ctrl_sck_pol),
.io_ctrl_sck_pha(phy_io_ctrl_sck_pha),
.io_ctrl_fmt_proto(phy_io_ctrl_fmt_proto),
.io_ctrl_fmt_endian(phy_io_ctrl_fmt_endian),
.io_ctrl_fmt_iodir(phy_io_ctrl_fmt_iodir),
.io_op_ready(phy_io_op_ready),
.io_op_valid(phy_io_op_valid),
.io_op_bits_fn(phy_io_op_bits_fn),
.io_op_bits_stb(phy_io_op_bits_stb),
.io_op_bits_cnt(phy_io_op_bits_cnt),
.io_op_bits_data(phy_io_op_bits_data),
.io_rx_valid(phy_io_rx_valid),
.io_rx_bits(phy_io_rx_bits)
);
assign io_port_sck = phy_io_port_sck;
assign io_port_dq_0_o = phy_io_port_dq_0_o;
assign io_port_dq_0_oe = phy_io_port_dq_0_oe;
assign io_port_dq_1_o = phy_io_port_dq_1_o;
assign io_port_dq_1_oe = phy_io_port_dq_1_oe;
assign io_port_dq_2_o = phy_io_port_dq_2_o;
assign io_port_dq_2_oe = phy_io_port_dq_2_oe;
assign io_port_dq_3_o = phy_io_port_dq_3_o;
assign io_port_dq_3_oe = phy_io_port_dq_3_oe;
assign io_port_cs_0 = cs_dflt_0;
assign io_link_tx_ready = GEN_31;
assign io_link_rx_valid = phy_io_rx_valid;
assign io_link_rx_bits = phy_io_rx_bits;
assign io_link_active = cs_assert;
assign phy_clock = clock;
assign phy_reset = reset;
assign phy_io_port_dq_0_i = io_port_dq_0_i;
assign phy_io_port_dq_1_i = io_port_dq_1_i;
assign phy_io_port_dq_2_i = io_port_dq_2_i;
assign phy_io_port_dq_3_i = io_port_dq_3_i;
assign phy_io_ctrl_sck_div = io_ctrl_sck_div;
assign phy_io_ctrl_sck_pol = io_ctrl_sck_pol;
assign phy_io_ctrl_sck_pha = io_ctrl_sck_pha;
assign phy_io_ctrl_fmt_proto = io_link_fmt_proto;
assign phy_io_ctrl_fmt_endian = io_link_fmt_endian;
assign phy_io_ctrl_fmt_iodir = io_link_fmt_iodir;
assign phy_io_op_valid = GEN_37;
assign phy_io_op_bits_fn = GEN_28;
assign phy_io_op_bits_stb = GEN_43;
assign phy_io_op_bits_cnt = GEN_42;
assign phy_io_op_bits_data = io_link_tx_bits;
assign GEN_48 = {{1'd0}, io_link_cs_set};
assign T_162 = GEN_48 << io_ctrl_cs_id;
assign GEN_49 = {{1'd0}, io_ctrl_cs_dflt_0};
assign T_163 = GEN_49 ^ T_162;
assign T_164 = T_163[0];
assign cs_active_0 = T_164;
assign cs_update = cs_active_0 != cs_dflt_0;
assign T_175 = io_link_cs_hold == 1'h0;
assign T_176 = cs_update & T_175;
assign cs_deassert = clear | T_176;
assign T_177 = io_link_cs_clear & cs_assert;
assign T_178 = clear | T_177;
assign continuous = io_ctrl_dla_interxfr == 8'h0;
assign T_182 = 2'h0 == state;
assign GEN_0 = phy_io_op_ready ? 2'h2 : state;
assign GEN_1 = cs_deassert ? io_ctrl_dla_sckcs : io_link_cnt;
assign GEN_2 = cs_deassert ? GEN_0 : state;
assign T_184 = cs_deassert == 1'h0;
assign T_186 = phy_io_op_ready & phy_io_op_valid;
assign GEN_3 = T_186 ? 2'h1 : GEN_2;
assign GEN_4 = T_184 ? 1'h0 : 1'h1;
assign GEN_6 = T_184 ? io_link_tx_valid : 1'h1;
assign GEN_7 = T_184 ? phy_io_op_ready : 1'h0;
assign GEN_8 = T_184 ? GEN_3 : GEN_2;
assign GEN_9 = cs_assert ? GEN_1 : io_link_cnt;
assign GEN_10 = cs_assert ? GEN_8 : state;
assign GEN_11 = cs_assert ? GEN_4 : 1'h1;
assign GEN_12 = cs_assert ? T_184 : 1'h0;
assign GEN_13 = cs_assert ? GEN_6 : 1'h1;
assign GEN_14 = cs_assert ? GEN_7 : 1'h0;
assign T_188 = cs_assert == 1'h0;
assign T_189 = T_188 & io_link_tx_valid;
assign GEN_15 = phy_io_op_ready ? 1'h1 : cs_assert;
assign GEN_16 = phy_io_op_ready ? io_link_cs_set : cs_set;
assign GEN_17 = phy_io_op_ready ? cs_active_0 : cs_dflt_0;
assign GEN_18 = T_189 ? io_ctrl_dla_cssck : GEN_9;
assign GEN_19 = T_189 ? GEN_15 : cs_assert;
assign GEN_20 = T_189 ? GEN_16 : cs_set;
assign GEN_21 = T_189 ? GEN_17 : cs_dflt_0;
assign T_194 = io_link_tx_valid == 1'h0;
assign T_195 = T_188 & T_194;
assign GEN_22 = T_195 ? 8'h0 : GEN_18;
assign GEN_23 = T_195 ? 1'h1 : GEN_12;
assign GEN_24 = T_195 ? io_ctrl_cs_id : cs_id;
assign GEN_25 = T_195 ? io_ctrl_cs_dflt_0 : GEN_21;
assign GEN_26 = T_182 ? GEN_22 : io_link_cnt;
assign GEN_27 = T_182 ? GEN_10 : state;
assign GEN_28 = T_182 ? GEN_11 : 1'h1;
assign GEN_29 = T_182 ? GEN_23 : 1'h0;
assign GEN_30 = T_182 ? GEN_13 : 1'h1;
assign GEN_31 = T_182 ? GEN_14 : 1'h0;
assign GEN_32 = T_182 ? GEN_19 : cs_assert;
assign GEN_33 = T_182 ? GEN_20 : cs_set;
assign GEN_34 = T_182 ? GEN_25 : cs_dflt_0;
assign GEN_35 = T_182 ? GEN_24 : cs_id;
assign T_198 = 2'h1 == state;
assign T_200 = continuous == 1'h0;
assign T_201 = phy_io_op_ready | continuous;
assign GEN_36 = T_201 ? 2'h0 : GEN_27;
assign GEN_37 = T_198 ? T_200 : GEN_30;
assign GEN_38 = T_198 ? io_ctrl_dla_interxfr : GEN_26;
assign GEN_39 = T_198 ? GEN_36 : GEN_27;
assign T_202 = 2'h2 == state;
assign GEN_50 = {{1'd0}, cs_set};
assign T_206 = GEN_50 << cs_id;
assign GEN_51 = {{1'd0}, cs_dflt_0};
assign T_207 = GEN_51 ^ T_206;
assign T_208 = T_207[0];
assign T_213_0 = T_208;
assign GEN_40 = phy_io_op_ready ? T_213_0 : GEN_34;
assign GEN_41 = phy_io_op_ready ? 2'h0 : GEN_39;
assign GEN_42 = T_202 ? io_ctrl_dla_intercs : GEN_38;
assign GEN_43 = T_202 ? 1'h1 : GEN_29;
assign GEN_44 = T_202 ? 1'h0 : GEN_32;
assign GEN_45 = T_202 ? 1'h0 : T_178;
assign GEN_46 = T_202 ? GEN_40 : GEN_34;
assign GEN_47 = T_202 ? GEN_41 : GEN_39;
always @(posedge clock or posedge reset)
if(reset) begin
cs_id <= 2'b0;
cs_dflt_0 <= 1'b1;
cs_set <= 1'b0;
end
else begin//{
if (T_182) begin
if (T_195) begin
cs_id <= io_ctrl_cs_id;
end
end
if (T_202) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= T_213_0;
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_set <= io_link_cs_set;
end
end
end
end//}
always @(posedge clock or posedge reset)
if (reset) begin
clear <= 1'h0;
end else begin
if (T_202) begin
clear <= 1'h0;
end else begin
clear <= T_178;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cs_assert <= 1'h0;
end else begin
if (T_202) begin
cs_assert <= 1'h0;
end else begin
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_assert <= 1'h1;
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 2'h0;
end else begin
if (T_202) begin
if (phy_io_op_ready) begin
state <= 2'h0;
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_16_V
`define SKY130_FD_SC_HDLL__NAND2_16_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_16 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_16 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_SYMBOL_V
`define SKY130_FD_SC_LP__O311AI_SYMBOL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o311ai (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_SYMBOL_V
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "consts.vh"
module data_memory (
input [31:0] inst,
input [31:0] data,
input [31:0] addr,
output [31:0] memory_addr,
output reg [31:0] write_data,
output reg [3:0] write_mask,
input [31:0] load_data,
output reg [31:0] output_data
);
wire [2:0] funct3 = inst[9:7];
wire [6:0] opcode = inst[6:0];
assign memory_addr = {addr[31:2], 2'b0};
reg [31:0] write_data_masked;
always @ (*) begin
case (funct3)
`F3_SB: write_data_masked = data & 32'hFF;
`F3_SH: write_data_masked = data & 32'hFFFF;
`F3_SW: write_data_masked = data & 32'hFFFFFFFF;
default: write_data_masked = 32'h0;
endcase
end
always @ (*) begin
case (addr[1:0])
2'b00: write_data = write_data_masked;
2'b01: write_data = write_data_masked << 8;
2'b10: write_data = write_data_masked << 16;
2'b11: write_data = write_data_masked << 24;
default: write_data = 32'b0;
endcase
end
always @ (*) begin
case (funct3)
`F3_SB: write_mask = 4'b1 << addr[1:0];
`F3_SH: write_mask = 4'b11 << addr[1:0];
`F3_SW: write_mask = 4'b1111;
default: write_mask = 0;
endcase
end
reg [31:0] load_data_shifted;
always @ (*) begin
case (funct3)
`F3_LB, `F3_LBU: case (addr[1:0])
2'b00: load_data_shifted = {24'b0, load_data[7:0]};
2'b01: load_data_shifted = {24'b0, load_data[15:8]};
2'b10: load_data_shifted = {24'b0, load_data[23:16]};
2'b11: load_data_shifted = {24'b0, load_data[31:24]};
default: load_data_shifted = 32'b0;
endcase
`F3_LH, `F3_LHU: case (addr[1:0])
2'b00: load_data_shifted = {16'b0, load_data[15:0]};
2'b10: load_data_shifted = {16'b0, load_data[31:16]};
default: load_data_shifted = 32'b0;
endcase
`F3_LW: load_data_shifted = load_data;
default: load_data_shifted = 32'b0;
endcase
end
wire [31:0] lds = load_data_shifted;
always @ (*) begin
case (funct3)
`F3_LB: output_data = lds[7] ? {24'hFFFFFF, lds[7:0]} : {24'h0, lds[7:0]};
`F3_LH: output_data = lds[15] ? {16'hFFFF, lds[15:0]} : {16'h0, lds[15:0]};
`F3_LW, `F3_LHU, `F3_LBU: output_data = lds;
default: output_data = 32'b0;
endcase
end
endmodule
|
`timescale 1ns / 1ps
// Name: WcaStrobe.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaDspStrobe(
clock,
reset, //Resets the counter.
strobe_in, //
enable,
rate, //Strobe rate.
strobe_out, //strobe signal.
count //Optional Strobe Counter output.
);
parameter INITIAL_VAL = 24'd0;
parameter INCREMENT_VAL = 24'h1;
input wire clock, reset, enable, strobe_in;
input wire [23: 0] rate;
output wire strobe_out;
output reg [23:0] count;
assign strobe_out = count == rate;
always @(posedge clock)
if(reset | ~enable | strobe_out)
count <= #1 INITIAL_VAL;
else if( strobe_in)
count <= #1 count + INCREMENT_VAL;
//Implment internal counter.
/*
DspCounter24 dspctcor( .clk(clock), .up( 1'b0), .load( strobe | reset), .l( rate), .q( count) );
*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDLCLKP_PP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.07.2016 12:04:13
// Design Name:
// Module Name: pc_ctrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pc_ctrl #(
parameter DATA_W_IN_BYTES = 4,
parameter ADDR_W_IN_BITS = (8 + 2),
parameter DCADDR_LOW_BIT_W = 8,
parameter DCADDR_STROBE_MEM_SEG = 2
) (
//--------------------------------------------------------------------------
// register IO section
//--------------------------------------------------------------------------
// Block pm0
input wire [31:0] pm0_accum_low_period,
input wire [15:0] pm0_pulse_per_second,
input wire pm0_ready_to_read ,
// Block pm1
input wire [31:0] pm1_accum_low_period,
input wire [15:0] pm1_pulse_per_second,
input wire pm1_ready_to_read ,
// Block pm0
output wire [31:0] pm0_clk_freq ,
output wire [31:0] pm0_clk_subsample ,
output wire pm0_enable ,
output wire pm0_use_one_pps_in ,
// Block pm1
output wire [31:0] pm1_clk_freq ,
output wire pm1_clk_subsample ,
output wire pm1_enable ,
output wire pm1_use_one_pps_in ,
//--------------------------------------------------------------------------
// Control strobe section
//--------------------------------------------------------------------------
input wire [(ADDR_W_IN_BITS)-1 : 0] S_AXI_AWADDR, // Write channel Protection type. This signal indicates the privilege and security level of the transaction, and whether // the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT, // Write address valid. This signal indicates that the master signaling // valid write address and control information.
input wire S_AXI_AWVALID, // Write address ready. This signal indicates that the slave is ready // to accept an address and associated control signals.
output wire S_AXI_AWREADY, // Write data (issued by master, acceped by Slave)
input wire [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_WDATA, // Write strobes. This signal indicates which byte lanes hold // valid data. There is one write strobe bit for each eight // bits of the write data bus.
input wire [DATA_W_IN_BYTES-1 : 0] S_AXI_WSTRB, // Write valid. This signal indicates that valid write // data and strobes are available.
input wire S_AXI_WVALID, // Write ready. This signal indicates that the slave // can accept the write data.
output wire S_AXI_WREADY, // Write response. This signal indicates the status // of the write transaction.
output wire [1 : 0] S_AXI_BRESP, // Write response valid. This signal indicates that the channel // is signaling a valid write response.
output wire S_AXI_BVALID, // Response ready. This signal indicates that the master // can accept a write response.
input wire S_AXI_BREADY, // Read address (issued by master, acceped by Slave)
input wire [(ADDR_W_IN_BITS)-1 : 0] S_AXI_ARADDR, // Protection type. This signal indicates the privilege // and security level of the transaction, and whether the // transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT, // Read address valid. This signal indicates that the channel // is signaling valid read address and control information.
input wire S_AXI_ARVALID, // Read address ready. This signal indicates that the slave is // ready to accept an address and associated control signals.
output wire S_AXI_ARREADY, // Read data (issued by slave)
output wire [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_RDATA, // Read response. This signal indicates the status of the // read transfer.
output wire [1 : 0] S_AXI_RRESP, // Read valid. This signal indicates that the channel is signaling the required read data.
output wire S_AXI_RVALID, // Read ready. This signal indicates that the master can accept the read data and response information.
input wire S_AXI_RREADY, //
input wire ACLK, // Clock source
input wire ARESETn // Reset source
);
//------------------------------------------------------------------------------
// read/write control strobes
//------------------------------------------------------------------------------
wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_rd_start; // read start strobe
wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_rd_done; // read done strobe
wire [DCADDR_LOW_BIT_W - 1:0] bank_rd_addr; // read address bus
reg [(DATA_W_IN_BYTES*8) - 1:0] bank_rd_data; // read data bus
wire [(ADDR_W_IN_BITS)-1:DCADDR_LOW_BIT_W] decode_rd_addr;// used external to the block to select the correct returning data
wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_wr_start; // write start strobe
wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_wr_done; // write done strobe
wire [DCADDR_LOW_BIT_W - 1:0] bank_wr_addr; // write address bus
wire [(DATA_W_IN_BYTES*8) - 1:0] bank_wr_data; // write data bus
wire [(DATA_W_IN_BYTES*8) - 1:0] bank_rd_data_bus[DCADDR_STROBE_MEM_SEG-1:0]; // read data bus
//------------------------------------------------------------------------------
// Register interface control logic. This can be swapped for the appropiate
// protocol.
//------------------------------------------------------------------------------
pc_ctrl_axi4_reg_if #(
.DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
.ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
.DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W ),
.DCADDR_STROBE_MEM_SEG (DCADDR_STROBE_MEM_SEG )
) pc_ctrl_axi4_reg_if_0_i (
.S_AXI_AWADDR (S_AXI_AWADDR ),
.S_AXI_AWPROT (S_AXI_AWPROT ), // Write channel Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
.S_AXI_AWVALID (S_AXI_AWVALID ), // Write address valid. This signal indicates that the master signaling valid write address and control information.
.S_AXI_AWREADY (S_AXI_AWREADY ), // Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.
.S_AXI_WDATA (S_AXI_WDATA ), // Write data (issued by master, acceped by Slave)
.S_AXI_WSTRB (S_AXI_WSTRB ), // Write strobes. This signal indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus.
.S_AXI_WVALID (S_AXI_WVALID ), // Write valid. This signal indicates that valid write data and strobes are available.
.S_AXI_WREADY (S_AXI_WREADY ), // Write ready. This signal indicates that the slave can accept the write data.
.S_AXI_BRESP (S_AXI_BRESP ), // Write response. This signal indicates the status of the write transaction.
.S_AXI_BVALID (S_AXI_BVALID ), // Write response valid. This signal indicates that the channel is signaling a valid write response.
.S_AXI_BREADY (S_AXI_BREADY ), // Response ready. This signal indicates that the master can accept a write response.
.S_AXI_ARADDR (S_AXI_ARADDR ), // Read address (issued by master, acceped by Slave)
.S_AXI_ARPROT (S_AXI_ARPROT ), // Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
.S_AXI_ARVALID (S_AXI_ARVALID ), // Read address valid. This signal indicates that the channel is signaling valid read address and control information.
.S_AXI_ARREADY (S_AXI_ARREADY ), // Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals.
.S_AXI_RDATA (S_AXI_RDATA ), // Read data (issued by slave)
.S_AXI_RRESP (S_AXI_RRESP ), // Read response. This signal indicates the status of the read transfer.
.S_AXI_RVALID (S_AXI_RVALID ), // Read valid. This signal indicates that the channel is signaling the required read data.
.S_AXI_RREADY (S_AXI_RREADY ), // Read ready. This signal indicates that the master can accept the read data and response information.
.reg_bank_rd_start (bank_rd_start ), // read start strobe
.reg_bank_rd_done (bank_rd_done ), // read done strobe
.reg_bank_rd_addr (bank_rd_addr ), // read address bus
.reg_bank_rd_data (bank_rd_data ), // read data bus
.decode_rd_addr (decode_rd_addr), // Upper address bits used to select the correct read data back into
.reg_bank_wr_start (bank_wr_start ), // write start strobe
.reg_bank_wr_done (bank_wr_done ), // write done strobe
.reg_bank_wr_addr (bank_wr_addr ), // write address bus
.reg_bank_wr_data (bank_wr_data ), // write data bus
.ACLK (ACLK ), // Clock source
.ARESETn (ARESETn ) // Reset source
);
//------------------------------------------------------------------------------
// Mux the read data lines back into the interface logic.
// DCADDR_STROBE_MEM_SEG defines the number of strobes required.
//------------------------------------------------------------------------------
always @(*) begin
case(decode_rd_addr)
0:bank_rd_data = bank_rd_data_bus[0]; // DECODE FOR instance pm0 of type reg_sync_v
1:bank_rd_data = bank_rd_data_bus[1]; // DECODE FOR instance pm1 of type reg_sync_v
default:bank_rd_data = bank_rd_data_bus[0];
endcase
end
//------------------------------------------------------------------------------
// Data basic register type : pm0
//------------------------------------------------------------------------------
pc_ctrl_pm0 #(
.DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
.ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
.DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W )
) pc_ctrl_pm0_0_i (
// Block pm0 Inputs
.accum_low_period(pm0_accum_low_period),
.pulse_per_second(pm0_pulse_per_second),
.ready_to_read (pm0_ready_to_read ),
// Block pm0 Outputs
.clk_freq (pm0_clk_freq ),
.clk_subsample (pm0_clk_subsample ),
.enable (pm0_enable ),
.use_one_pps_in (pm0_use_one_pps_in ),
.reg_bank_rd_start (bank_rd_start[0] ), // read start strobe
.reg_bank_rd_done (bank_rd_done[0] ), // read done strobe
.reg_bank_rd_addr (bank_rd_addr ), // read address bus
.reg_bank_rd_data (bank_rd_data_bus[0] ), // read data bus
.reg_bank_wr_start (bank_wr_start[0] ), // write start strobe
.reg_bank_wr_done (bank_wr_done[0] ), // write done strobe
.reg_bank_wr_addr (bank_wr_addr ), // write address bus
.reg_bank_wr_data (bank_wr_data ), // write data bus
.ACLK (ACLK ), // Clock source
.ARESETn (ARESETn ) // Reset source
);
//------------------------------------------------------------------------------
// Data basic register type : pm1
//------------------------------------------------------------------------------
pc_ctrl_pm1 #(
.DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
.ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
.DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W )
) pc_ctrl_pm1_1_i (
// Block pm1 Inputs
.accum_low_period(pm1_accum_low_period),
.pulse_per_second(pm1_pulse_per_second),
.ready_to_read (pm1_ready_to_read ),
// Block pm1 Outputs
.clk_freq (pm1_clk_freq ),
.clk_subsample (pm1_clk_subsample ),
.enable (pm1_enable ),
.use_one_pps_in (pm1_use_one_pps_in ),
.reg_bank_rd_start (bank_rd_start[1] ), // read start strobe
.reg_bank_rd_done (bank_rd_done[1] ), // read done strobe
.reg_bank_rd_addr (bank_rd_addr ), // read address bus
.reg_bank_rd_data (bank_rd_data_bus[1] ), // read data bus
.reg_bank_wr_start (bank_wr_start[1] ), // write start strobe
.reg_bank_wr_done (bank_wr_done[1] ), // write done strobe
.reg_bank_wr_addr (bank_wr_addr ), // write address bus
.reg_bank_wr_data (bank_wr_data ), // write data bus
.ACLK (ACLK ), // Clock source
.ARESETn (ARESETn ) // Reset source
);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NOR2B_BEHAVIORAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:48:36 05/12/2015
// Design Name:
// Module Name: organisation
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module organisation(
input clock,
input [2:0] reg_read_adr1,
input [2:0] reg_read_adr2,
input [2:0] reg_write_adr,
input reg_write,
input flush_e,
input [1:0] forward1,
input [1:0] forward2,
input [7:0] ALU_con,
input ALU_source2,
input [15:0] offset,
input mem_write,
input mem_to_reg,
input [15:0] processor_input,
input processor_uart_rx,
output N,
output Z,
output C,
output V,
output [15:0] processor_output,
output processor_uart_tx,
output internal_IRQ
);
reg [15:0] ram_data_in_m;
reg [15:0] ALU_data_out_w;
reg [15:0] ALU_data_out_m;
reg [15:0] ALU_data_in1;
reg [15:0] ALU_data_in2;
reg [15:0] ram_data_in_e;
reg [15:0] result_w;
wire [15:0] reg_file_data_out1_e;
wire [15:0] reg_file_data_out2_e;
wire [15:0] RAM_data_out_w;
wire [15:0] ALU_out;
IO_memory IO_memory (
.clock(clock),
.IO_write(mem_write),
.IO_address(ALU_data_out_m[11:0]),
.IO_data_in(ram_data_in_m),
.IO_data_out(RAM_data_out_w),
.processor_input(processor_input),
.processor_output(processor_output),
.processor_uart_rx(processor_uart_rx),
.processor_uart_tx(processor_uart_tx),
.internal_IRQ(internal_IRQ)
);
register_file reg_file (
.clock(clock),
.flush(flush_e),
.read_adr_1(reg_read_adr1),
.read_adr_2(reg_read_adr2),
.write_data(result_w),
.write_adr(reg_write_adr),
.write_en(reg_write),
.data_out_1(reg_file_data_out1_e),
.data_out_2(reg_file_data_out2_e)
);
ALU_16 ALU (
.clock(clock),
.ALU_data_in1(ALU_data_in1),
.ALU_data_in2(ALU_data_in2),
.ALU_control(ALU_con),
.ALU_data_out(ALU_out),
.N(N),
.Z(Z),
.C(C),
.V(V)
);
always @(*) begin
case (forward1)
2'h0: begin
ALU_data_in1 <= reg_file_data_out1_e;
end
2'h1: begin
ALU_data_in1 <= ALU_data_out_m;
end
2'h2: begin
ALU_data_in1 <= result_w;
end
endcase
case (forward2)
2'h0: begin
ram_data_in_e <= reg_file_data_out2_e;
end
2'h1: begin
ram_data_in_e <= ALU_data_out_m;
end
2'h2: begin
ram_data_in_e <= result_w;
end
endcase
case (ALU_source2)
0: begin
ALU_data_in2 = ram_data_in_e;
end
1: begin
ALU_data_in2 = offset;
end
endcase
case (mem_to_reg)
0: begin
result_w <= ALU_data_out_w;
end
1: begin
result_w <= RAM_data_out_w;
end
endcase
end
always @(posedge clock) begin
ram_data_in_m <= ram_data_in_e;
ALU_data_out_m <= ALU_out;
ALU_data_out_w <= ALU_data_out_m;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by John Stevenson.
typedef logic [63:0] uid_t;
typedef logic [31:0] value_t;
interface the_intf #(parameter M = 5);
logic valid;
uid_t uid;
value_t [M-1:0] values;
modport i(
output valid,
output uid,
output values
);
modport t(
input valid,
input uid,
input values
);
endinterface
module Contemplator #(
parameter IMPL = 0,
parameter M = 5,
parameter N = 1 )
(
input logic clk,
the_intf.i out [N-1:0]
);
the_intf #(.M(M)) inp[N-1:0] ();
DeepThought #(
.N ( N ))
ultimateAnswerer(
.src ( inp ),
.dst ( out ));
endmodule
module DeepThought #(
parameter N = 1 )
(
the_intf.t src[N-1:0],
the_intf.i dst[N-1:0]
);
endmodule
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam M = 5;
localparam N = 1;
the_intf #(.M(M)) out0 [N-1:0] ();
the_intf #(.M(M)) out1 [N-1:0] ();
Contemplator #(
.IMPL ( 0 ),
.M ( M ),
.N ( N ))
contemplatorOfTheZerothKind(
.clk ( clk ),
.out ( out0 ));
Contemplator #(
.IMPL ( 1 ),
.M ( M ),
.N ( N ))
contemplatorOfTheFirstKind(
.clk ( clk ),
.out ( out1 ));
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//======================================================================
//
// tb_fpga_entropy.v
// -----------------
// Testbench for the FPGA Entropy generator core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/10ps
module tb_fpga_entropy();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter VERBOSE = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_init;
reg tb_update;
reg tb_seed;
wire [31 : 0] tb_rnd;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
fpga_entropy_core dut(
// Clock and reset.
.clk(),
.reset_n(),
.init(tb_init),
.update(tb_update),
.seed(tb_seed),
.rnd(tb_rnd)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor
//
// System monitor. Can display status about the dut and TB
// every cycle.
//----------------------------------------------------------------
always
begin : sys_monitor
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
$display("");
end
if (VERBOSE)
begin
$display("cycle: 0x%016x", cycle_ctr);
end
cycle_ctr = cycle_ctr + 1;
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dut when needed.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("init = 0x%01x, update = 0x%01x, seed = 0x%01x",
tb_init, tb_update, tb_seed);
$display("rnd= 0x%08x", tb_rnd);
$display("");
$display("Internal values:");
$display("shift_reg = 0x%08x, rnd_reg = 0x%08x, bit_ctr_reg = 0x%02x",
dut.shift_reg, dut.rnd_reg, dut.bit_ctr_reg);
$display("l5d = 0x%01x, l7d = 0x%01x, l13d = 0x%01x, l41d = 0x01x, l43d = 0x%01x",
dut.l5d, dut.l7d, dut.l13d, dut.l41d, dut.l43d);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_init = 1;
tb_seed = 1;
tb_update = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// fpga_entropy_test
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : fpga_entropy_test
$display(" -- Testbench for fpga entropy core started --");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
tb_update = 1;
#(64 * CLK_PERIOD);
tb_init = 0;
#(1000 * CLK_PERIOD);
$display("*** Simulation done. ***");
$finish;
end // fpga_entropy_test
endmodule // tb_fpga_entropy
//======================================================================
// EOF tb_fpga_entropy.v
//======================================================================
|
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
*--------------------------------------------------------------------------------
*/
//`timescale 1ps/1ps
module LAG_test_random ();
parameter CLOCK_PERIOD = 10_000;
localparam global_links_num = find_max_global_link_num(links);
flit_t flit_in[network_x-1:0][network_y-1:0];
flit_t flit_out[network_x-1:0][network_y-1:0][global_links_num-1:0];
logic [router_num_pls_on_entry-1:0] input_full_flag [network_x-1:0][network_y-1:0];
logic [global_links_num-1:0] cntrl_in [network_x-1:0][network_y-1:0];
integer rec_count [network_x-1:0][network_y-1:0];
integer flits_sent [network_x-1:0][network_y-1:0];
sim_stats_t stats [network_x-1:0][network_y-1:0];
real av_lat[network_x-1:0][network_y-1:0];
integer link_util [network_x-1:0][network_y-1:0][router_radix-1:0][global_links_num-1:0];
real link_util_ [network_x-1:0][network_y-1:0][router_radix-1:0][global_links_num-1:0];
genvar x,y;
integer i,j,k,l;
integer sys_time, total_packets, total_hops, min_latency, max_latency, total_latency;
integer min_hops, max_hops;
integer total_rec_count;
integer total_send_count;
integer lat_freq[100:0];
logic clk, rst_n;
integer s;
// clock generator
initial begin
clk=0;
end
always #(CLOCK_PERIOD/2) clk = ~clk;
always@(posedge clk) begin
if (!rst_n) begin
sys_time=0;
end else begin
sys_time++;
end
end
// ########################
// Network
// ########################
LAG_mesh_network #(.XS(network_x),
.YS(network_y),
.NP(router_radix),
.global_links_num(global_links_num),
.links(links)
) network
(flit_in, flit_out,
input_full_flag,
cntrl_in, link_util,
clk, rst_n
);
// ########################
// Traffic Sources
// ########################
generate
for (x=0; x<network_x; x++) begin:xl
for (y=0; y<network_y; y++) begin:yl
LAG_random_traffic_source #(.np(router_num_pls_on_entry),
.destinations(destinations[x][y]),
.xdim(network_x), .ydim(network_y), .xpos(x), .ypos(y),
.packet_length(sim_packet_length)
)
traf_src (.flit_out(flit_in[x][y]),
.flits_sent_o(flits_sent[x][y]),
.network_ready(~input_full_flag[x][y]),
.clk, .rst_n
);
end
end
endgenerate
// ########################
// Traffic Sinks
// ########################
generate
for (x=0; x<network_x; x++) begin:xl2
for (y=0; y<network_y; y++) begin:yl2
LAG_traffic_sink #(.xdim(network_x), .ydim(network_y), .xpos(x), .ypos(y), .global_links_num(global_links_num),
.local_links_num(links[x][y][`TILE][OUT]), .warmup_packets(sim_warmup_packets), .measurement_packets(sim_measurement_packets)
)
traf_sink (.flit_in(flit_out[x][y]),
.cntrl_out(cntrl_in[x][y]),
.rec_count(rec_count[x][y]),
.stats(stats[x][y]),
.clk, .rst_n);
end
end
endgenerate
//
// All measurement packets must be received before we end the simulation
// (this includes a drain phase)
//
always@(posedge clk) begin
total_rec_count = 0;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
if(rec_count[i][j] != -1)
total_rec_count = total_rec_count+rec_count[i][j];
end
end
if ( rst_n /* if not reset */ && ((total_rec_count - sim_warmup_packets)%(sim_measurement_packets/20)) == 0 )
$display ("%1d: %1.2f%% complete", sys_time, $itor(total_rec_count*100)/$itor(sim_measurement_packets) );
end
initial begin
$display ("******************************************");
$display ("* NoC with LAG - Predefined Traffic Test *");
$display ("******************************************");
total_hops=0;
total_latency=0;
total_send_count=0;
link_util_[i][j][k][l] = '0;
//
// reset
//
rst_n=0;
// reset
#(CLOCK_PERIOD*20);
rst_n=1;
$display ("-- Reset Complete");
$display ("-- Entering warmup phase (%1d packets per node)", sim_warmup_packets);
`ifdef DUMPTRACE
$dumpfile ("/tmp/trace.vcd");
$dumpvars;
`endif
// #################################################################
// wait for all traffic sinks to rec. all measurement packets
// #################################################################
wait (total_rec_count > sim_measurement_packets);
$display ("** Simulation End **\n");
//calculating utilization of links
for (i=0; i<network_x; i++)
for (j=0; j<network_y; j++)
for (k=0; k<router_radix; k++)
for (l=0; l<global_links_num; l++)
link_util_[i][j][k][l] = $itor(link_util[i][j][k][l]) / $itor(sys_time);
//calculating the blocking rate of each input link of each router
total_packets = sim_measurement_packets;
min_latency=stats[0][0].min_latency;
max_latency=stats[0][0].max_latency;
min_hops=stats[0][0].min_hops;
max_hops=stats[0][0].max_hops;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
av_lat[i][j] = $itor(stats[i][j].total_latency)/$itor(rec_count[i][j]);
total_latency = total_latency + stats[i][j].total_latency;
total_hops=total_hops+stats[i][j].total_hops;
min_latency = min(min_latency, stats[i][j].min_latency);
max_latency = max(max_latency, stats[i][j].max_latency);
min_hops = min(min_hops, stats[i][j].min_hops);
max_hops = max(max_hops, stats[i][j].max_hops);
end
end
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
total_send_count += flits_sent[i][j] / sim_packet_length;
end
end
for (k=0; k<=100; k++) lat_freq[k]=0;
for (i=0; i<network_x; i++) begin
for (j=0; j<network_y; j++) begin
for (k=0; k<=100; k++) begin
lat_freq[k]=lat_freq[k]+stats[i][j].lat_freq[k];
end
end
end
$display ("***********************************************************************************");
$display ("-- Channel Latency = %1d", 0);
$display ("***********************************************************************************");
$display ("-- Packet Length = %1d", sim_packet_length);
$display ("-- Average Latency = %1.2f (cycles)", $itor(total_latency)/$itor(total_packets));
$display ("-- Min. Latency = %1d, Max. Latency = %1d", min_latency, max_latency);
$display ("-- Average no. of hops taken by packet = %1.2f hops (min=%1d, max=%1d)",
$itor(total_hops)/$itor(total_packets), min_hops, max_hops);
$display ("***********************************************************************************");
$display ("\n");
$display ("Average Latencies for packets rec'd at nodes [x,y] and (no. of packets received)");
for (j=0; j<network_y;j++) begin
for (i=0; i<network_x; i++)
if (rec_count[i][j] != -1)
$write ("%1.2f (%1d)\t", av_lat[i][j], rec_count[i][j]);
else
$write ("0.00 (0)\t");
$display ("");
end
$display ("");
$display ("Flits/cycle sent at each node:");
for (j=0; j<network_y; j++) begin
for (i=0; i<network_x; i++) begin
$write ("%1.2f\t", $itor(flits_sent[i][j])/$itor(sys_time));
end
$display ("");
end
$display ("");
$display ("Flits/cycle received at each node: (should approx. injection rate)");
for (j=0; j<network_y; j++) begin
for (i=0; i<network_x; i++) begin
$write ("%1.2f\t", $itor(stats[i][j].flit_count)/$itor(stats[i][j].measure_end-stats[i][j].measure_start));
end
$display ("");
end
$display ("");
$display ("Latencies for packet flows (in clock cycles)");
$display("----------------------------------------------------------");
for (j=0; j<network_y; j++) // destination y
for (i=0; i<network_x; i++) // destination x
for (l=0; l<network_y; l++) // source y
for (k=0; k<network_x; k++) // source x
if(stats[i][j].flows_latencies[k][l][0]) begin
$display ("(%1d, %1d) -> (%1d, %1d): min = %1d; av = %1d; max = %1d;",
k, l, i, j, stats[i][j].flows_latencies[k][l][3],
stats[i][j].flows_latencies[k][l][1] / stats[i][j].flows_latencies[k][l][2],
stats[i][j].flows_latencies[k][l][4]);
$display("----------------------------------------------------------");
end
$display ("\n");
$display ("Distribution of packet latencies: ");
$display ("Latency : Frequency (as percentage of total)");
$display ("-------------------");
for (k=0; k<100; k++) begin
$display ("%1d %1.2f", k, $itor(lat_freq[k]*100)/$itor(total_packets));
end
$display ("100+ %1.2f", $itor(lat_freq[k]*100)/$itor(total_packets));
$finish;
end
endmodule // LAG_test_random
|
module hps_tabby(
input coe_M1_RSTN, coe_M1_CLK,
input [21:0] coe_M1_ADDR,
inout [31:0] coe_M1_DATA,
input [3:0] coe_M1_CSN,
input [3:0] coe_M1_BEN,
input coe_M1_RDN, coe_M1_WRN,
output coe_M1_WAITN,
output [9:0] coe_M1_EINT,
output rso_MRST_reset,
output cso_MCLK_clk,
output cso_H1CLK_clk,
output cso_H2CLK_clk,
output [31:0] avm_M1_writedata,
input [31:0] avm_M1_readdata,
output [29:0] avm_M1_address,
output [3:0] avm_M1_byteenable,
output avm_M1_write,
output avm_M1_read,
output avm_M1_begintransfer,
input avm_M1_readdatavalid,
input avm_M1_waitrequest,
input [9:0] inr_EVENTS_irq
);
// rSMC_SETUP(0) = (0 << 24) + (2 << 16) + (0 << 8) + (0 << 0);
// rSMC_PULSE(0) = (0 << 24) + (6 << 16) + (0 << 8) + (2 << 0);
// rSMC_CYCLE(0) = (0 << 23) + (8 << 16) + (0 << 7) + (6 << 0);
// rSMC_MODE(0) = (0 << 28) + (0 << 24) + (1 << 20) + (8 << 16) + (2 << 12) + (0 << 8) + (2 << 4) + (1 << 1) + (1 << 0);
assign rso_MRST_reset = ~(pll_locked & coe_M1_RSTN);
assign cso_MCLK_clk = pll_clocks[0]; //133.33 MHz
assign cso_H1CLK_clk = coe_M1_CLK; //66.66 MHz
assign cso_H2CLK_clk = pll_clocks[1]; //200.00 MHz
assign coe_M1_DATA = ((!coe_M1_RDN) && (coe_M1_CSN != 4'b1111) && (!rso_MRST_reset)) ? h_rdata : 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
assign coe_M1_WAITN = (~h_wait) | (rso_MRST_reset);
assign coe_M1_EINT = inr_EVENTS_irq;
assign avm_M1_writedata = q_wdata;
assign q_rdata = avm_M1_readdata;
assign avm_M1_address = q_addr;
assign avm_M1_byteenable = q_be;
assign avm_M1_write = q_wr;
assign avm_M1_read = q_rd;
assign avm_M1_begintransfer = q_btrans;
assign q_rdvalid = avm_M1_readdatavalid;
assign q_wait = avm_M1_waitrequest;
assign q_clock = cso_MCLK_clk;
assign q_reset = rso_MRST_reset;
wire q_clock;
wire q_reset;
reg [3:0] state = 0;
reg [31:0] h_rdata = 0;
reg h_wait = 0;
reg [31:0] q_wdata = 0;
wire [31:0] q_rdata;
reg [29:0] q_addr = 0;
reg [3:0] q_be = 0;
reg q_wr = 0;
reg q_rd = 0;
reg q_btrans = 0;
wire q_rdvalid, q_wait;
reg [3:0] tmp_cs;
reg [21:0] tmp_addr;
reg [19:0] timeout = 0;
always@(posedge q_clock or posedge q_reset)
begin
if(q_reset) begin
q_addr <= 0;
q_be <= 0;
end
else begin
q_be <= ~coe_M1_BEN;
case(coe_M1_CSN)
4'b1110: begin q_addr <= {8'b00010000, coe_M1_ADDR}; end
4'b1101: begin q_addr <= {8'b00100000, coe_M1_ADDR}; end
4'b1011: begin q_addr <= {8'b00110000, coe_M1_ADDR}; end
4'b0111: begin q_addr <= {8'b01000000, coe_M1_ADDR}; end
default: begin q_addr <= 0; end
endcase
end
end
parameter idle = 4'd0;
parameter read_prepare = idle + 1'd1;
parameter read_data = read_prepare + 1'd1;
parameter read_finish = read_data + 1'd1;
parameter write_prepare = read_finish + 1'd1;
parameter write_data = write_prepare + 1'd1;
parameter write_write = write_data + 1'd1;
parameter write_finish = write_write + 1'd1;
always@(posedge q_clock or posedge q_reset)
begin
if(q_reset) begin
h_rdata <= 0;
q_wdata <= 0;
q_wr <= 0;
q_rd <= 0;
q_btrans <= 0;
h_wait <= 0;
timeout <= 0;
state <= idle;
end
else begin
case(state)
idle: begin
timeout <= 0;
if((coe_M1_CSN != 4'b1111)&&(!coe_M1_RDN)&&(!q_wait)) begin
q_btrans <= 0;
q_wr <= 0;
q_rd <= 0;
h_wait <= 1;
state <= read_prepare;
end
else if((coe_M1_CSN != 4'b1111)&&(!coe_M1_WRN)&&(!q_wait)) begin
q_btrans <= 0;
q_wr <= 0;
q_rd <= 0;
h_wait <= 1;
state <= write_prepare;
end
else begin
h_rdata <= 0;
q_wdata <= 0;
q_wr <= 0;
q_rd <= 0;
q_btrans <= 0;
h_wait <= 0;
state <= idle;
end
end
// Read process.
read_prepare: begin
tmp_addr <= coe_M1_ADDR;
tmp_cs <= coe_M1_CSN;
if((!q_wait)||(timeout == 20'hFFFFF)) begin
q_btrans <= 1;
q_rd <= 1;
timeout <= 0;
state <= read_data;
end
else begin
timeout <= timeout + 1;
state <= read_prepare;
end
end
read_data: begin
q_btrans <= 0;
q_rd <= 0;
if((q_rdvalid)||(timeout == 20'hFFFFF)) begin
h_rdata <= q_rdata;
h_wait <= q_wait;
timeout <= 0;
state <= read_finish;
end
else begin
timeout <= timeout + 1;
state <= read_data;
end
end
read_finish: begin
h_wait <= q_wait;
if((tmp_addr != coe_M1_ADDR)||(tmp_cs != coe_M1_CSN)||(coe_M1_RDN)||(timeout == 20'hFFFFF))
state <= idle;
else begin
timeout <= timeout + 1;
state <= read_finish;
end
end
// Write process.
write_prepare: begin
q_wdata <= coe_M1_DATA;
if(coe_M1_WRN && (!q_wait)) begin
h_wait <= 1;
state <= write_data;
end
else begin
h_wait <= q_wait;
state <= write_prepare;
end
end
write_data: begin
if((!q_wait)||(timeout == 20'hFFFFF)) begin
q_btrans <= 1;
q_wr <= 1;
timeout <= 0;
state <= write_write;
end
else begin
timeout <= timeout + 1;
state <= write_data;
end
end
write_write: begin
q_btrans <= 0;
q_wr <= 0;
if((!q_wait)||(timeout == 20'hFFFFF)) begin
timeout <= 0;
state <= write_finish;
end
else begin
timeout <= timeout + 1;
state <= write_write;
end
end
write_finish: begin
if((!q_wait)||(timeout == 20'hFFFFF)) begin
timeout <= 0;
h_wait <= 0;
state <= idle;
end
else begin
timeout <= timeout + 1;
state <= write_finish;
end
end
default: begin
h_rdata <= 0;
h_wait <= 0;
q_wdata <= 0;
q_wr <= 0;
q_rd <= 0;
q_btrans <= 0;
timeout <= 0;
state <= idle;
end
endcase
end
end
wire [4:0] pll_clocks;
wire pll_locked;
altpll m1_bus_pll_inst1(
.inclk (coe_M1_CLK),
.clk (pll_clocks),
.locked (pll_locked),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
m1_bus_pll_inst1.bandwidth_type = "AUTO",
m1_bus_pll_inst1.clk0_divide_by = 1,
m1_bus_pll_inst1.clk0_duty_cycle = 50,
m1_bus_pll_inst1.clk0_multiply_by = 2,
m1_bus_pll_inst1.clk0_phase_shift = "0",
m1_bus_pll_inst1.clk1_divide_by = 1,
m1_bus_pll_inst1.clk1_duty_cycle = 50,
m1_bus_pll_inst1.clk1_multiply_by = 3,
m1_bus_pll_inst1.clk1_phase_shift = "0",
m1_bus_pll_inst1.compensate_clock = "CLK0",
m1_bus_pll_inst1.inclk0_input_frequency = 15000,
m1_bus_pll_inst1.intended_device_family = "Cyclone IV E",
m1_bus_pll_inst1.lpm_hint = "CBX_MODULE_PREFIX=apll",
m1_bus_pll_inst1.lpm_type = "altpll",
m1_bus_pll_inst1.operation_mode = "NORMAL",
m1_bus_pll_inst1.pll_type = "AUTO",
m1_bus_pll_inst1.port_activeclock = "PORT_UNUSED",
m1_bus_pll_inst1.port_areset = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkbad0 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkbad1 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkloss = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkswitch = "PORT_UNUSED",
m1_bus_pll_inst1.port_configupdate = "PORT_UNUSED",
m1_bus_pll_inst1.port_fbin = "PORT_UNUSED",
m1_bus_pll_inst1.port_inclk0 = "PORT_USED",
m1_bus_pll_inst1.port_inclk1 = "PORT_UNUSED",
m1_bus_pll_inst1.port_locked = "PORT_USED",
m1_bus_pll_inst1.port_pfdena = "PORT_UNUSED",
m1_bus_pll_inst1.port_phasecounterselect = "PORT_UNUSED",
m1_bus_pll_inst1.port_phasedone = "PORT_UNUSED",
m1_bus_pll_inst1.port_phasestep = "PORT_UNUSED",
m1_bus_pll_inst1.port_phaseupdown = "PORT_UNUSED",
m1_bus_pll_inst1.port_pllena = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanaclr = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanclk = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanclkena = "PORT_UNUSED",
m1_bus_pll_inst1.port_scandata = "PORT_UNUSED",
m1_bus_pll_inst1.port_scandataout = "PORT_UNUSED",
m1_bus_pll_inst1.port_scandone = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanread = "PORT_UNUSED",
m1_bus_pll_inst1.port_scanwrite = "PORT_UNUSED",
m1_bus_pll_inst1.port_clk0 = "PORT_USED",
m1_bus_pll_inst1.port_clk1 = "PORT_USED",
m1_bus_pll_inst1.port_clk2 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clk3 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clk4 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clk5 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena0 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena1 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena2 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena3 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena4 = "PORT_UNUSED",
m1_bus_pll_inst1.port_clkena5 = "PORT_UNUSED",
m1_bus_pll_inst1.port_extclk0 = "PORT_UNUSED",
m1_bus_pll_inst1.port_extclk1 = "PORT_UNUSED",
m1_bus_pll_inst1.port_extclk2 = "PORT_UNUSED",
m1_bus_pll_inst1.port_extclk3 = "PORT_UNUSED",
m1_bus_pll_inst1.self_reset_on_loss_lock = "ON",
m1_bus_pll_inst1.width_clock = 5;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A21BO_PP_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_PP_BLACKBOX_V
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_multi_mac.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_multi_mac.v,v $
//
// $Revision: #1 $
// $Date: 2011/08/15 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet - 10/100/1000 MAC
//
// Description :
//
// Top Level Triple Speed Ethernet(10/100/1000) MAC with FIFOs, MII/GMII
// interfaces, mdio module and register space (statistic, control and
// management)
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_multi_mac
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter ENABLE_CLK_SHARING = 0, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 1, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// SHARED CLK SIGNALS
input wire rx_clk, // Receive Clock
input wire tx_clk, // Transmit Clock
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clock
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_0, // Carrier Sense
input wire m_rx_col_0, // Collition
input wire rx_clk_0, // Receive Clock
input wire tx_clk_0, // Transmit Clock
input wire [7:0] gm_rx_d_0, // GMII Receive Data
input wire gm_rx_dv_0, // GMII Receive Frame Enable
input wire gm_rx_err_0, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_0, // GMII Transmit Data
output wire gm_tx_en_0, // GMII Transmit Frame Enable
output wire gm_tx_err_0, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_0, // MII Receive Data
input wire m_rx_en_0, // MII Receive Frame Enable
input wire m_rx_err_0, // MII Receive Drame Error
output wire [3:0] m_tx_d_0, // MII Transmit Data
output wire m_tx_en_0, // MII Transmit Frame Enable
output wire m_tx_err_0, // MII Transmit Frame Error
output wire tx_control_0,
output wire [3:0] rgmii_out_0,
input wire [3:0] rgmii_in_0,
input wire rx_control_0,
output wire eth_mode_0, // Ethernet Mode
output wire ena_10_0, // Enable 10Mbps Mode
input wire set_1000_0, // Gigabit Mode Enable
input wire set_10_0, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// CHANNEL 1
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_1, // Carrier Sense
input wire m_rx_col_1, // Collition
input wire rx_clk_1, // Receive Clock
input wire tx_clk_1, // Transmit Clock
input wire [7:0] gm_rx_d_1, // GMII Receive Data
input wire gm_rx_dv_1, // GMII Receive Frame Enable
input wire gm_rx_err_1, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_1, // GMII Transmit Data
output wire gm_tx_en_1, // GMII Transmit Frame Enable
output wire gm_tx_err_1, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_1, // MII Receive Data
input wire m_rx_en_1, // MII Receive Frame Enable
input wire m_rx_err_1, // MII Receive Drame Error
output wire [3:0] m_tx_d_1, // MII Transmit Data
output wire m_tx_en_1, // MII Transmit Frame Enable
output wire m_tx_err_1, // MII Transmit Frame Error
output wire tx_control_1,
output wire [3:0] rgmii_out_1,
input wire [3:0] rgmii_in_1,
input wire rx_control_1,
output wire eth_mode_1, // Ethernet Mode
output wire ena_10_1, // Enable 10Mbps Mode
input wire set_1000_1, // Gigabit Mode Enable
input wire set_10_1, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// CHANNEL 2
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_2, // Carrier Sense
input wire m_rx_col_2, // Collition
input wire rx_clk_2, // Receive Clock
input wire tx_clk_2, // Transmit Clock
input wire [7:0] gm_rx_d_2, // GMII Receive Data
input wire gm_rx_dv_2, // GMII Receive Frame Enable
input wire gm_rx_err_2, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_2, // GMII Transmit Data
output wire gm_tx_en_2, // GMII Transmit Frame Enable
output wire gm_tx_err_2, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_2, // MII Receive Data
input wire m_rx_en_2, // MII Receive Frame Enable
input wire m_rx_err_2, // MII Receive Drame Error
output wire [3:0] m_tx_d_2, // MII Transmit Data
output wire m_tx_en_2, // MII Transmit Frame Enable
output wire m_tx_err_2, // MII Transmit Frame Error
output wire tx_control_2,
output wire [3:0] rgmii_out_2,
input wire [3:0] rgmii_in_2,
input wire rx_control_2,
output wire eth_mode_2, // Ethernet Mode
output wire ena_10_2, // Enable 10Mbps Mode
input wire set_1000_2, // Gigabit Mode Enable
input wire set_10_2, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// CHANNEL 3
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_3, // Carrier Sense
input wire m_rx_col_3, // Collition
input wire rx_clk_3, // Receive Clock
input wire tx_clk_3, // Transmit Clock
input wire [7:0] gm_rx_d_3, // GMII Receive Data
input wire gm_rx_dv_3, // GMII Receive Frame Enable
input wire gm_rx_err_3, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_3, // GMII Transmit Data
output wire gm_tx_en_3, // GMII Transmit Frame Enable
output wire gm_tx_err_3, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_3, // MII Receive Data
input wire m_rx_en_3, // MII Receive Frame Enable
input wire m_rx_err_3, // MII Receive Drame Error
output wire [3:0] m_tx_d_3, // MII Transmit Data
output wire m_tx_en_3, // MII Transmit Frame Enable
output wire m_tx_err_3, // MII Transmit Frame Error
output wire tx_control_3,
output wire [3:0] rgmii_out_3,
input wire [3:0] rgmii_in_3,
input wire rx_control_3,
output wire eth_mode_3, // Ethernet Mode
output wire ena_10_3, // Enable 10Mbps Mode
input wire set_1000_3, // Gigabit Mode Enable
input wire set_10_3, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// CHANNEL 4
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_4, // Carrier Sense
input wire m_rx_col_4, // Collition
input wire rx_clk_4, // Receive Clock
input wire tx_clk_4, // Transmit Clock
input wire [7:0] gm_rx_d_4, // GMII Receive Data
input wire gm_rx_dv_4, // GMII Receive Frame Enable
input wire gm_rx_err_4, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_4, // GMII Transmit Data
output wire gm_tx_en_4, // GMII Transmit Frame Enable
output wire gm_tx_err_4, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_4, // MII Receive Data
input wire m_rx_en_4, // MII Receive Frame Enable
input wire m_rx_err_4, // MII Receive Drame Error
output wire [3:0] m_tx_d_4, // MII Transmit Data
output wire m_tx_en_4, // MII Transmit Frame Enable
output wire m_tx_err_4, // MII Transmit Frame Error
output wire tx_control_4,
output wire [3:0] rgmii_out_4,
input wire [3:0] rgmii_in_4,
input wire rx_control_4,
output wire eth_mode_4, // Ethernet Mode
output wire ena_10_4, // Enable 10Mbps Mode
input wire set_1000_4, // Gigabit Mode Enable
input wire set_10_4, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// CHANNEL 5
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_5, // Carrier Sense
input wire m_rx_col_5, // Collition
input wire rx_clk_5, // Receive Clock
input wire tx_clk_5, // Transmit Clock
input wire [7:0] gm_rx_d_5, // GMII Receive Data
input wire gm_rx_dv_5, // GMII Receive Frame Enable
input wire gm_rx_err_5, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_5, // GMII Transmit Data
output wire gm_tx_en_5, // GMII Transmit Frame Enable
output wire gm_tx_err_5, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_5, // MII Receive Data
input wire m_rx_en_5, // MII Receive Frame Enable
input wire m_rx_err_5, // MII Receive Drame Error
output wire [3:0] m_tx_d_5, // MII Transmit Data
output wire m_tx_en_5, // MII Transmit Frame Enable
output wire m_tx_err_5, // MII Transmit Frame Error
output wire tx_control_5,
output wire [3:0] rgmii_out_5,
input wire [3:0] rgmii_in_5,
input wire rx_control_5,
output wire eth_mode_5, // Ethernet Mode
output wire ena_10_5, // Enable 10Mbps Mode
input wire set_1000_5, // Gigabit Mode Enable
input wire set_10_5, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// CHANNEL 6
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_6, // Carrier Sense
input wire m_rx_col_6, // Collition
input wire rx_clk_6, // Receive Clock
input wire tx_clk_6, // Transmit Clock
input wire [7:0] gm_rx_d_6, // GMII Receive Data
input wire gm_rx_dv_6, // GMII Receive Frame Enable
input wire gm_rx_err_6, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_6, // GMII Transmit Data
output wire gm_tx_en_6, // GMII Transmit Frame Enable
output wire gm_tx_err_6, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_6, // MII Receive Data
input wire m_rx_en_6, // MII Receive Frame Enable
input wire m_rx_err_6, // MII Receive Drame Error
output wire [3:0] m_tx_d_6, // MII Transmit Data
output wire m_tx_en_6, // MII Transmit Frame Enable
output wire m_tx_err_6, // MII Transmit Frame Error
output wire tx_control_6,
output wire [3:0] rgmii_out_6,
input wire [3:0] rgmii_in_6,
input wire rx_control_6,
output wire eth_mode_6, // Ethernet Mode
output wire ena_10_6, // Enable 10Mbps Mode
input wire set_1000_6, // Gigabit Mode Enable
input wire set_10_6, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// CHANNEL 7
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_7, // Carrier Sense
input wire m_rx_col_7, // Collition
input wire rx_clk_7, // Receive Clock
input wire tx_clk_7, // Transmit Clock
input wire [7:0] gm_rx_d_7, // GMII Receive Data
input wire gm_rx_dv_7, // GMII Receive Frame Enable
input wire gm_rx_err_7, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_7, // GMII Transmit Data
output wire gm_tx_en_7, // GMII Transmit Frame Enable
output wire gm_tx_err_7, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_7, // MII Receive Data
input wire m_rx_en_7, // MII Receive Frame Enable
input wire m_rx_err_7, // MII Receive Drame Error
output wire [3:0] m_tx_d_7, // MII Transmit Data
output wire m_tx_en_7, // MII Transmit Frame Enable
output wire m_tx_err_7, // MII Transmit Frame Error
output wire tx_control_7,
output wire [3:0] rgmii_out_7,
input wire [3:0] rgmii_in_7,
input wire rx_control_7,
output wire eth_mode_7, // Ethernet Mode
output wire ena_10_7, // Enable 10Mbps Mode
input wire set_1000_7, // Gigabit Mode Enable
input wire set_10_7, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// CHANNEL 8
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_8, // Carrier Sense
input wire m_rx_col_8, // Collition
input wire rx_clk_8, // Receive Clock
input wire tx_clk_8, // Transmit Clock
input wire [7:0] gm_rx_d_8, // GMII Receive Data
input wire gm_rx_dv_8, // GMII Receive Frame Enable
input wire gm_rx_err_8, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_8, // GMII Transmit Data
output wire gm_tx_en_8, // GMII Transmit Frame Enable
output wire gm_tx_err_8, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_8, // MII Receive Data
input wire m_rx_en_8, // MII Receive Frame Enable
input wire m_rx_err_8, // MII Receive Drame Error
output wire [3:0] m_tx_d_8, // MII Transmit Data
output wire m_tx_en_8, // MII Transmit Frame Enable
output wire m_tx_err_8, // MII Transmit Frame Error
output wire tx_control_8,
output wire [3:0] rgmii_out_8,
input wire [3:0] rgmii_in_8,
input wire rx_control_8,
output wire eth_mode_8, // Ethernet Mode
output wire ena_10_8, // Enable 10Mbps Mode
input wire set_1000_8, // Gigabit Mode Enable
input wire set_10_8, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// CHANNEL 9
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_9, // Carrier Sense
input wire m_rx_col_9, // Collition
input wire rx_clk_9, // Receive Clock
input wire tx_clk_9, // Transmit Clock
input wire [7:0] gm_rx_d_9, // GMII Receive Data
input wire gm_rx_dv_9, // GMII Receive Frame Enable
input wire gm_rx_err_9, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_9, // GMII Transmit Data
output wire gm_tx_en_9, // GMII Transmit Frame Enable
output wire gm_tx_err_9, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_9, // MII Receive Data
input wire m_rx_en_9, // MII Receive Frame Enable
input wire m_rx_err_9, // MII Receive Drame Error
output wire [3:0] m_tx_d_9, // MII Transmit Data
output wire m_tx_en_9, // MII Transmit Frame Enable
output wire m_tx_err_9, // MII Transmit Frame Error
output wire tx_control_9,
output wire [3:0] rgmii_out_9,
input wire [3:0] rgmii_in_9,
input wire rx_control_9,
output wire eth_mode_9, // Ethernet Mode
output wire ena_10_9, // Enable 10Mbps Mode
input wire set_1000_9, // Gigabit Mode Enable
input wire set_10_9, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// CHANNEL 10
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_10, // Carrier Sense
input wire m_rx_col_10, // Collition
input wire rx_clk_10, // Receive Clock
input wire tx_clk_10, // Transmit Clock
input wire [7:0] gm_rx_d_10, // GMII Receive Data
input wire gm_rx_dv_10, // GMII Receive Frame Enable
input wire gm_rx_err_10, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_10, // GMII Transmit Data
output wire gm_tx_en_10, // GMII Transmit Frame Enable
output wire gm_tx_err_10, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_10, // MII Receive Data
input wire m_rx_en_10, // MII Receive Frame Enable
input wire m_rx_err_10, // MII Receive Drame Error
output wire [3:0] m_tx_d_10, // MII Transmit Data
output wire m_tx_en_10, // MII Transmit Frame Enable
output wire m_tx_err_10, // MII Transmit Frame Error
output wire tx_control_10,
output wire [3:0] rgmii_out_10,
input wire [3:0] rgmii_in_10,
input wire rx_control_10,
output wire eth_mode_10, // Ethernet Mode
output wire ena_10_10, // Enable 10Mbps Mode
input wire set_1000_10, // Gigabit Mode Enable
input wire set_10_10, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// CHANNEL 11
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_11, // Carrier Sense
input wire m_rx_col_11, // Collition
input wire rx_clk_11, // Receive Clock
input wire tx_clk_11, // Transmit Clock
input wire [7:0] gm_rx_d_11, // GMII Receive Data
input wire gm_rx_dv_11, // GMII Receive Frame Enable
input wire gm_rx_err_11, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_11, // GMII Transmit Data
output wire gm_tx_en_11, // GMII Transmit Frame Enable
output wire gm_tx_err_11, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_11, // MII Receive Data
input wire m_rx_en_11, // MII Receive Frame Enable
input wire m_rx_err_11, // MII Receive Drame Error
output wire [3:0] m_tx_d_11, // MII Transmit Data
output wire m_tx_en_11, // MII Transmit Frame Enable
output wire m_tx_err_11, // MII Transmit Frame Error
output wire tx_control_11,
output wire [3:0] rgmii_out_11,
input wire [3:0] rgmii_in_11,
input wire rx_control_11,
output wire eth_mode_11, // Ethernet Mode
output wire ena_10_11, // Enable 10Mbps Mode
input wire set_1000_11, // Gigabit Mode Enable
input wire set_10_11, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// CHANNEL 12
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_12, // Carrier Sense
input wire m_rx_col_12, // Collition
input wire rx_clk_12, // Receive Clock
input wire tx_clk_12, // Transmit Clock
input wire [7:0] gm_rx_d_12, // GMII Receive Data
input wire gm_rx_dv_12, // GMII Receive Frame Enable
input wire gm_rx_err_12, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_12, // GMII Transmit Data
output wire gm_tx_en_12, // GMII Transmit Frame Enable
output wire gm_tx_err_12, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_12, // MII Receive Data
input wire m_rx_en_12, // MII Receive Frame Enable
input wire m_rx_err_12, // MII Receive Drame Error
output wire [3:0] m_tx_d_12, // MII Transmit Data
output wire m_tx_en_12, // MII Transmit Frame Enable
output wire m_tx_err_12, // MII Transmit Frame Error
output wire tx_control_12,
output wire [3:0] rgmii_out_12,
input wire [3:0] rgmii_in_12,
input wire rx_control_12,
output wire eth_mode_12, // Ethernet Mode
output wire ena_10_12, // Enable 10Mbps Mode
input wire set_1000_12, // Gigabit Mode Enable
input wire set_10_12, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// CHANNEL 13
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_13, // Carrier Sense
input wire m_rx_col_13, // Collition
input wire rx_clk_13, // Receive Clock
input wire tx_clk_13, // Transmit Clock
input wire [7:0] gm_rx_d_13, // GMII Receive Data
input wire gm_rx_dv_13, // GMII Receive Frame Enable
input wire gm_rx_err_13, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_13, // GMII Transmit Data
output wire gm_tx_en_13, // GMII Transmit Frame Enable
output wire gm_tx_err_13, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_13, // MII Receive Data
input wire m_rx_en_13, // MII Receive Frame Enable
input wire m_rx_err_13, // MII Receive Drame Error
output wire [3:0] m_tx_d_13, // MII Transmit Data
output wire m_tx_en_13, // MII Transmit Frame Enable
output wire m_tx_err_13, // MII Transmit Frame Error
output wire tx_control_13,
output wire [3:0] rgmii_out_13,
input wire [3:0] rgmii_in_13,
input wire rx_control_13,
output wire eth_mode_13, // Ethernet Mode
output wire ena_10_13, // Enable 10Mbps Mode
input wire set_1000_13, // Gigabit Mode Enable
input wire set_10_13, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// CHANNEL 14
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_14, // Carrier Sense
input wire m_rx_col_14, // Collition
input wire rx_clk_14, // Receive Clock
input wire tx_clk_14, // Transmit Clock
input wire [7:0] gm_rx_d_14, // GMII Receive Data
input wire gm_rx_dv_14, // GMII Receive Frame Enable
input wire gm_rx_err_14, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_14, // GMII Transmit Data
output wire gm_tx_en_14, // GMII Transmit Frame Enable
output wire gm_tx_err_14, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_14, // MII Receive Data
input wire m_rx_en_14, // MII Receive Frame Enable
input wire m_rx_err_14, // MII Receive Drame Error
output wire [3:0] m_tx_d_14, // MII Transmit Data
output wire m_tx_en_14, // MII Transmit Frame Enable
output wire m_tx_err_14, // MII Transmit Frame Error
output wire tx_control_14,
output wire [3:0] rgmii_out_14,
input wire [3:0] rgmii_in_14,
input wire rx_control_14,
output wire eth_mode_14, // Ethernet Mode
output wire ena_10_14, // Enable 10Mbps Mode
input wire set_1000_14, // Gigabit Mode Enable
input wire set_10_14, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// CHANNEL 15
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_15, // Carrier Sense
input wire m_rx_col_15, // Collition
input wire rx_clk_15, // Receive Clock
input wire tx_clk_15, // Transmit Clock
input wire [7:0] gm_rx_d_15, // GMII Receive Data
input wire gm_rx_dv_15, // GMII Receive Frame Enable
input wire gm_rx_err_15, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_15, // GMII Transmit Data
output wire gm_tx_en_15, // GMII Transmit Frame Enable
output wire gm_tx_err_15, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_15, // MII Receive Data
input wire m_rx_en_15, // MII Receive Frame Enable
input wire m_rx_err_15, // MII Receive Drame Error
output wire [3:0] m_tx_d_15, // MII Transmit Data
output wire m_tx_en_15, // MII Transmit Frame Enable
output wire m_tx_err_15, // MII Transmit Frame Error
output wire tx_control_15,
output wire [3:0] rgmii_out_15,
input wire [3:0] rgmii_in_15,
input wire rx_control_15,
output wire eth_mode_15, // Ethernet Mode
output wire ena_10_15, // Enable 10Mbps Mode
input wire set_1000_15, // Gigabit Mode Enable
input wire set_10_15, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// CHANNEL 16
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_16, // Carrier Sense
input wire m_rx_col_16, // Collition
input wire rx_clk_16, // Receive Clock
input wire tx_clk_16, // Transmit Clock
input wire [7:0] gm_rx_d_16, // GMII Receive Data
input wire gm_rx_dv_16, // GMII Receive Frame Enable
input wire gm_rx_err_16, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_16, // GMII Transmit Data
output wire gm_tx_en_16, // GMII Transmit Frame Enable
output wire gm_tx_err_16, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_16, // MII Receive Data
input wire m_rx_en_16, // MII Receive Frame Enable
input wire m_rx_err_16, // MII Receive Drame Error
output wire [3:0] m_tx_d_16, // MII Transmit Data
output wire m_tx_en_16, // MII Transmit Frame Enable
output wire m_tx_err_16, // MII Transmit Frame Error
output wire tx_control_16,
output wire [3:0] rgmii_out_16,
input wire [3:0] rgmii_in_16,
input wire rx_control_16,
output wire eth_mode_16, // Ethernet Mode
output wire ena_10_16, // Enable 10Mbps Mode
input wire set_1000_16, // Gigabit Mode Enable
input wire set_10_16, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// CHANNEL 17
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_17, // Carrier Sense
input wire m_rx_col_17, // Collition
input wire rx_clk_17, // Receive Clock
input wire tx_clk_17, // Transmit Clock
input wire [7:0] gm_rx_d_17, // GMII Receive Data
input wire gm_rx_dv_17, // GMII Receive Frame Enable
input wire gm_rx_err_17, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_17, // GMII Transmit Data
output wire gm_tx_en_17, // GMII Transmit Frame Enable
output wire gm_tx_err_17, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_17, // MII Receive Data
input wire m_rx_en_17, // MII Receive Frame Enable
input wire m_rx_err_17, // MII Receive Drame Error
output wire [3:0] m_tx_d_17, // MII Transmit Data
output wire m_tx_en_17, // MII Transmit Frame Enable
output wire m_tx_err_17, // MII Transmit Frame Error
output wire tx_control_17,
output wire [3:0] rgmii_out_17,
input wire [3:0] rgmii_in_17,
input wire rx_control_17,
output wire eth_mode_17, // Ethernet Mode
output wire ena_10_17, // Enable 10Mbps Mode
input wire set_1000_17, // Gigabit Mode Enable
input wire set_10_17, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// CHANNEL 18
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_18, // Carrier Sense
input wire m_rx_col_18, // Collition
input wire rx_clk_18, // Receive Clock
input wire tx_clk_18, // Transmit Clock
input wire [7:0] gm_rx_d_18, // GMII Receive Data
input wire gm_rx_dv_18, // GMII Receive Frame Enable
input wire gm_rx_err_18, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_18, // GMII Transmit Data
output wire gm_tx_en_18, // GMII Transmit Frame Enable
output wire gm_tx_err_18, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_18, // MII Receive Data
input wire m_rx_en_18, // MII Receive Frame Enable
input wire m_rx_err_18, // MII Receive Drame Error
output wire [3:0] m_tx_d_18, // MII Transmit Data
output wire m_tx_en_18, // MII Transmit Frame Enable
output wire m_tx_err_18, // MII Transmit Frame Error
output wire tx_control_18,
output wire [3:0] rgmii_out_18,
input wire [3:0] rgmii_in_18,
input wire rx_control_18,
output wire eth_mode_18, // Ethernet Mode
output wire ena_10_18, // Enable 10Mbps Mode
input wire set_1000_18, // Gigabit Mode Enable
input wire set_10_18, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// CHANNEL 19
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_19, // Carrier Sense
input wire m_rx_col_19, // Collition
input wire rx_clk_19, // Receive Clock
input wire tx_clk_19, // Transmit Clock
input wire [7:0] gm_rx_d_19, // GMII Receive Data
input wire gm_rx_dv_19, // GMII Receive Frame Enable
input wire gm_rx_err_19, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_19, // GMII Transmit Data
output wire gm_tx_en_19, // GMII Transmit Frame Enable
output wire gm_tx_err_19, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_19, // MII Receive Data
input wire m_rx_en_19, // MII Receive Frame Enable
input wire m_rx_err_19, // MII Receive Drame Error
output wire [3:0] m_tx_d_19, // MII Transmit Data
output wire m_tx_en_19, // MII Transmit Frame Enable
output wire m_tx_err_19, // MII Transmit Frame Error
output wire tx_control_19,
output wire [3:0] rgmii_out_19,
input wire [3:0] rgmii_in_19,
input wire rx_control_19,
output wire eth_mode_19, // Ethernet Mode
output wire ena_10_19, // Enable 10Mbps Mode
input wire set_1000_19, // Gigabit Mode Enable
input wire set_10_19, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// CHANNEL 20
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_20, // Carrier Sense
input wire m_rx_col_20, // Collition
input wire rx_clk_20, // Receive Clock
input wire tx_clk_20, // Transmit Clock
input wire [7:0] gm_rx_d_20, // GMII Receive Data
input wire gm_rx_dv_20, // GMII Receive Frame Enable
input wire gm_rx_err_20, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_20, // GMII Transmit Data
output wire gm_tx_en_20, // GMII Transmit Frame Enable
output wire gm_tx_err_20, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_20, // MII Receive Data
input wire m_rx_en_20, // MII Receive Frame Enable
input wire m_rx_err_20, // MII Receive Drame Error
output wire [3:0] m_tx_d_20, // MII Transmit Data
output wire m_tx_en_20, // MII Transmit Frame Enable
output wire m_tx_err_20, // MII Transmit Frame Error
output wire tx_control_20,
output wire [3:0] rgmii_out_20,
input wire [3:0] rgmii_in_20,
input wire rx_control_20,
output wire eth_mode_20, // Ethernet Mode
output wire ena_10_20, // Enable 10Mbps Mode
input wire set_1000_20, // Gigabit Mode Enable
input wire set_10_20, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// CHANNEL 21
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_21, // Carrier Sense
input wire m_rx_col_21, // Collition
input wire rx_clk_21, // Receive Clock
input wire tx_clk_21, // Transmit Clock
input wire [7:0] gm_rx_d_21, // GMII Receive Data
input wire gm_rx_dv_21, // GMII Receive Frame Enable
input wire gm_rx_err_21, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_21, // GMII Transmit Data
output wire gm_tx_en_21, // GMII Transmit Frame Enable
output wire gm_tx_err_21, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_21, // MII Receive Data
input wire m_rx_en_21, // MII Receive Frame Enable
input wire m_rx_err_21, // MII Receive Drame Error
output wire [3:0] m_tx_d_21, // MII Transmit Data
output wire m_tx_en_21, // MII Transmit Frame Enable
output wire m_tx_err_21, // MII Transmit Frame Error
output wire tx_control_21,
output wire [3:0] rgmii_out_21,
input wire [3:0] rgmii_in_21,
input wire rx_control_21,
output wire eth_mode_21, // Ethernet Mode
output wire ena_10_21, // Enable 10Mbps Mode
input wire set_1000_21, // Gigabit Mode Enable
input wire set_10_21, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// CHANNEL 22
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_22, // Carrier Sense
input wire m_rx_col_22, // Collition
input wire rx_clk_22, // Receive Clock
input wire tx_clk_22, // Transmit Clock
input wire [7:0] gm_rx_d_22, // GMII Receive Data
input wire gm_rx_dv_22, // GMII Receive Frame Enable
input wire gm_rx_err_22, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_22, // GMII Transmit Data
output wire gm_tx_en_22, // GMII Transmit Frame Enable
output wire gm_tx_err_22, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_22, // MII Receive Data
input wire m_rx_en_22, // MII Receive Frame Enable
input wire m_rx_err_22, // MII Receive Drame Error
output wire [3:0] m_tx_d_22, // MII Transmit Data
output wire m_tx_en_22, // MII Transmit Frame Enable
output wire m_tx_err_22, // MII Transmit Frame Error
output wire tx_control_22,
output wire [3:0] rgmii_out_22,
input wire [3:0] rgmii_in_22,
input wire rx_control_22,
output wire eth_mode_22, // Ethernet Mode
output wire ena_10_22, // Enable 10Mbps Mode
input wire set_1000_22, // Gigabit Mode Enable
input wire set_10_22, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// CHANNEL 23
// GMII / MII / RGMII SIGNALS
input wire m_rx_crs_23, // Carrier Sense
input wire m_rx_col_23, // Collition
input wire rx_clk_23, // Receive Clock
input wire tx_clk_23, // Transmit Clock
input wire [7:0] gm_rx_d_23, // GMII Receive Data
input wire gm_rx_dv_23, // GMII Receive Frame Enable
input wire gm_rx_err_23, // GMII Receive Frame Error
output wire [7:0] gm_tx_d_23, // GMII Transmit Data
output wire gm_tx_en_23, // GMII Transmit Frame Enable
output wire gm_tx_err_23, // GMII Transmit Frame Error
input wire [3:0] m_rx_d_23, // MII Receive Data
input wire m_rx_en_23, // MII Receive Frame Enable
input wire m_rx_err_23, // MII Receive Drame Error
output wire [3:0] m_tx_d_23, // MII Transmit Data
output wire m_tx_en_23, // MII Transmit Frame Enable
output wire m_tx_err_23, // MII Transmit Frame Error
output wire tx_control_23,
output wire [3:0] rgmii_out_23,
input wire [3:0] rgmii_in_23,
input wire rx_control_23,
output wire eth_mode_23, // Ethernet Mode
output wire ena_10_23, // Enable 10Mbps Mode
input wire set_1000_23, // Gigabit Mode Enable
input wire set_10_23, // 10Mbps Mode Enable
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23); // Wake Up Request
altera_tse_top_multi_mac U_TOP_MULTI_MAC(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.rx_clk(rx_clk), //INPUT : MAC RX CLK
.tx_clk(tx_clk), //INPUT : MAC TX CLK
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.rx_clk_0(rx_clk_0), //INPUT : MAC RX CLK
.tx_clk_0(tx_clk_0), //INPUT : MAC TX CLK
.gm_rx_d_0(gm_rx_d_0), //INPUT : GMII RX DATA
.gm_rx_dv_0(gm_rx_dv_0), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_0(gm_rx_err_0), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_0(gm_tx_d_0), //OUTPUT : GMII TX DATA
.gm_tx_en_0(gm_tx_en_0), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_0(gm_tx_err_0), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_0(m_rx_crs_0), //INPUT : MII RX CARRIER SENSE
.m_rx_col_0(m_rx_col_0), //INPUT : MII RX COLLISION
.m_rx_d_0(m_rx_d_0), //INPUT : MII RX DATA
.m_rx_en_0(m_rx_en_0), //INPUT : MII RX VALID INDICATION
.m_rx_err_0(m_rx_err_0), //INPUT : MII RX ERROR INDICATION
.m_tx_d_0(m_tx_d_0), //OUTPUT : MII TX DATA
.m_tx_en_0(m_tx_en_0), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_0(m_tx_err_0), //OUTPUT : MII TX ERROR INDICATION
.rx_control_0(rx_control_0), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_0(rgmii_in_0), //INPUT : RGMII RX DATA INDICATION
.tx_control_0(tx_control_0), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_0(rgmii_out_0), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_0(eth_mode_0), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_0(ena_10_0), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_0(set_10_0), //INPUT : SPEED 10 MBPS
.set_1000_0(set_1000_0), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.rx_clk_1(rx_clk_1), //INPUT : MAC RX CLK
.tx_clk_1(tx_clk_1), //INPUT : MAC TX CLK
.gm_rx_d_1(gm_rx_d_1), //INPUT : GMII RX DATA
.gm_rx_dv_1(gm_rx_dv_1), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_1(gm_rx_err_1), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_1(gm_tx_d_1), //OUTPUT : GMII TX DATA
.gm_tx_en_1(gm_tx_en_1), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_1(gm_tx_err_1), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_1(m_rx_crs_1), //INPUT : MII RX CARRIER SENSE
.m_rx_col_1(m_rx_col_1), //INPUT : MII RX COLLISION
.m_rx_d_1(m_rx_d_1), //INPUT : MII RX DATA
.m_rx_en_1(m_rx_en_1), //INPUT : MII RX VALID INDICATION
.m_rx_err_1(m_rx_err_1), //INPUT : MII RX ERROR INDICATION
.m_tx_d_1(m_tx_d_1), //OUTPUT : MII TX DATA
.m_tx_en_1(m_tx_en_1), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_1(m_tx_err_1), //OUTPUT : MII TX ERROR INDICATION
.rx_control_1(rx_control_1), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_1(rgmii_in_1), //INPUT : RGMII RX DATA INDICATION
.tx_control_1(tx_control_1), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_1(rgmii_out_1), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_1(eth_mode_1), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_1(ena_10_1), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_1(set_10_1), //INPUT : SPEED 10 MBPS
.set_1000_1(set_1000_1), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.rx_clk_2(rx_clk_2), //INPUT : MAC RX CLK
.tx_clk_2(tx_clk_2), //INPUT : MAC TX CLK
.gm_rx_d_2(gm_rx_d_2), //INPUT : GMII RX DATA
.gm_rx_dv_2(gm_rx_dv_2), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_2(gm_rx_err_2), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_2(gm_tx_d_2), //OUTPUT : GMII TX DATA
.gm_tx_en_2(gm_tx_en_2), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_2(gm_tx_err_2), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_2(m_rx_crs_2), //INPUT : MII RX CARRIER SENSE
.m_rx_col_2(m_rx_col_2), //INPUT : MII RX COLLISION
.m_rx_d_2(m_rx_d_2), //INPUT : MII RX DATA
.m_rx_en_2(m_rx_en_2), //INPUT : MII RX VALID INDICATION
.m_rx_err_2(m_rx_err_2), //INPUT : MII RX ERROR INDICATION
.m_tx_d_2(m_tx_d_2), //OUTPUT : MII TX DATA
.m_tx_en_2(m_tx_en_2), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_2(m_tx_err_2), //OUTPUT : MII TX ERROR INDICATION
.rx_control_2(rx_control_2), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_2(rgmii_in_2), //INPUT : RGMII RX DATA INDICATION
.tx_control_2(tx_control_2), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_2(rgmii_out_2), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_2(eth_mode_2), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_2(ena_10_2), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_2(set_10_2), //INPUT : SPEED 10 MBPS
.set_1000_2(set_1000_2), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.rx_clk_3(rx_clk_3), //INPUT : MAC RX CLK
.tx_clk_3(tx_clk_3), //INPUT : MAC TX CLK
.gm_rx_d_3(gm_rx_d_3), //INPUT : GMII RX DATA
.gm_rx_dv_3(gm_rx_dv_3), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_3(gm_rx_err_3), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_3(gm_tx_d_3), //OUTPUT : GMII TX DATA
.gm_tx_en_3(gm_tx_en_3), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_3(gm_tx_err_3), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_3(m_rx_crs_3), //INPUT : MII RX CARRIER SENSE
.m_rx_col_3(m_rx_col_3), //INPUT : MII RX COLLISION
.m_rx_d_3(m_rx_d_3), //INPUT : MII RX DATA
.m_rx_en_3(m_rx_en_3), //INPUT : MII RX VALID INDICATION
.m_rx_err_3(m_rx_err_3), //INPUT : MII RX ERROR INDICATION
.m_tx_d_3(m_tx_d_3), //OUTPUT : MII TX DATA
.m_tx_en_3(m_tx_en_3), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_3(m_tx_err_3), //OUTPUT : MII TX ERROR INDICATION
.rx_control_3(rx_control_3), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_3(rgmii_in_3), //INPUT : RGMII RX DATA INDICATION
.tx_control_3(tx_control_3), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_3(rgmii_out_3), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_3(eth_mode_3), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_3(ena_10_3), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_3(set_10_3), //INPUT : SPEED 10 MBPS
.set_1000_3(set_1000_3), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.rx_clk_4(rx_clk_4), //INPUT : MAC RX CLK
.tx_clk_4(tx_clk_4), //INPUT : MAC TX CLK
.gm_rx_d_4(gm_rx_d_4), //INPUT : GMII RX DATA
.gm_rx_dv_4(gm_rx_dv_4), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_4(gm_rx_err_4), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_4(gm_tx_d_4), //OUTPUT : GMII TX DATA
.gm_tx_en_4(gm_tx_en_4), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_4(gm_tx_err_4), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_4(m_rx_crs_4), //INPUT : MII RX CARRIER SENSE
.m_rx_col_4(m_rx_col_4), //INPUT : MII RX COLLISION
.m_rx_d_4(m_rx_d_4), //INPUT : MII RX DATA
.m_rx_en_4(m_rx_en_4), //INPUT : MII RX VALID INDICATION
.m_rx_err_4(m_rx_err_4), //INPUT : MII RX ERROR INDICATION
.m_tx_d_4(m_tx_d_4), //OUTPUT : MII TX DATA
.m_tx_en_4(m_tx_en_4), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_4(m_tx_err_4), //OUTPUT : MII TX ERROR INDICATION
.rx_control_4(rx_control_4), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_4(rgmii_in_4), //INPUT : RGMII RX DATA INDICATION
.tx_control_4(tx_control_4), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_4(rgmii_out_4), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_4(eth_mode_4), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_4(ena_10_4), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_4(set_10_4), //INPUT : SPEED 10 MBPS
.set_1000_4(set_1000_4), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.rx_clk_5(rx_clk_5), //INPUT : MAC RX CLK
.tx_clk_5(tx_clk_5), //INPUT : MAC TX CLK
.gm_rx_d_5(gm_rx_d_5), //INPUT : GMII RX DATA
.gm_rx_dv_5(gm_rx_dv_5), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_5(gm_rx_err_5), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_5(gm_tx_d_5), //OUTPUT : GMII TX DATA
.gm_tx_en_5(gm_tx_en_5), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_5(gm_tx_err_5), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_5(m_rx_crs_5), //INPUT : MII RX CARRIER SENSE
.m_rx_col_5(m_rx_col_5), //INPUT : MII RX COLLISION
.m_rx_d_5(m_rx_d_5), //INPUT : MII RX DATA
.m_rx_en_5(m_rx_en_5), //INPUT : MII RX VALID INDICATION
.m_rx_err_5(m_rx_err_5), //INPUT : MII RX ERROR INDICATION
.m_tx_d_5(m_tx_d_5), //OUTPUT : MII TX DATA
.m_tx_en_5(m_tx_en_5), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_5(m_tx_err_5), //OUTPUT : MII TX ERROR INDICATION
.rx_control_5(rx_control_5), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_5(rgmii_in_5), //INPUT : RGMII RX DATA INDICATION
.tx_control_5(tx_control_5), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_5(rgmii_out_5), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_5(eth_mode_5), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_5(ena_10_5), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_5(set_10_5), //INPUT : SPEED 10 MBPS
.set_1000_5(set_1000_5), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.rx_clk_6(rx_clk_6), //INPUT : MAC RX CLK
.tx_clk_6(tx_clk_6), //INPUT : MAC TX CLK
.gm_rx_d_6(gm_rx_d_6), //INPUT : GMII RX DATA
.gm_rx_dv_6(gm_rx_dv_6), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_6(gm_rx_err_6), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_6(gm_tx_d_6), //OUTPUT : GMII TX DATA
.gm_tx_en_6(gm_tx_en_6), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_6(gm_tx_err_6), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_6(m_rx_crs_6), //INPUT : MII RX CARRIER SENSE
.m_rx_col_6(m_rx_col_6), //INPUT : MII RX COLLISION
.m_rx_d_6(m_rx_d_6), //INPUT : MII RX DATA
.m_rx_en_6(m_rx_en_6), //INPUT : MII RX VALID INDICATION
.m_rx_err_6(m_rx_err_6), //INPUT : MII RX ERROR INDICATION
.m_tx_d_6(m_tx_d_6), //OUTPUT : MII TX DATA
.m_tx_en_6(m_tx_en_6), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_6(m_tx_err_6), //OUTPUT : MII TX ERROR INDICATION
.rx_control_6(rx_control_6), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_6(rgmii_in_6), //INPUT : RGMII RX DATA INDICATION
.tx_control_6(tx_control_6), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_6(rgmii_out_6), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_6(eth_mode_6), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_6(ena_10_6), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_6(set_10_6), //INPUT : SPEED 10 MBPS
.set_1000_6(set_1000_6), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.rx_clk_7(rx_clk_7), //INPUT : MAC RX CLK
.tx_clk_7(tx_clk_7), //INPUT : MAC TX CLK
.gm_rx_d_7(gm_rx_d_7), //INPUT : GMII RX DATA
.gm_rx_dv_7(gm_rx_dv_7), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_7(gm_rx_err_7), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_7(gm_tx_d_7), //OUTPUT : GMII TX DATA
.gm_tx_en_7(gm_tx_en_7), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_7(gm_tx_err_7), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_7(m_rx_crs_7), //INPUT : MII RX CARRIER SENSE
.m_rx_col_7(m_rx_col_7), //INPUT : MII RX COLLISION
.m_rx_d_7(m_rx_d_7), //INPUT : MII RX DATA
.m_rx_en_7(m_rx_en_7), //INPUT : MII RX VALID INDICATION
.m_rx_err_7(m_rx_err_7), //INPUT : MII RX ERROR INDICATION
.m_tx_d_7(m_tx_d_7), //OUTPUT : MII TX DATA
.m_tx_en_7(m_tx_en_7), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_7(m_tx_err_7), //OUTPUT : MII TX ERROR INDICATION
.rx_control_7(rx_control_7), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_7(rgmii_in_7), //INPUT : RGMII RX DATA INDICATION
.tx_control_7(tx_control_7), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_7(rgmii_out_7), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_7(eth_mode_7), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_7(ena_10_7), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_7(set_10_7), //INPUT : SPEED 10 MBPS
.set_1000_7(set_1000_7), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.rx_clk_8(rx_clk_8), //INPUT : MAC RX CLK
.tx_clk_8(tx_clk_8), //INPUT : MAC TX CLK
.gm_rx_d_8(gm_rx_d_8), //INPUT : GMII RX DATA
.gm_rx_dv_8(gm_rx_dv_8), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_8(gm_rx_err_8), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_8(gm_tx_d_8), //OUTPUT : GMII TX DATA
.gm_tx_en_8(gm_tx_en_8), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_8(gm_tx_err_8), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_8(m_rx_crs_8), //INPUT : MII RX CARRIER SENSE
.m_rx_col_8(m_rx_col_8), //INPUT : MII RX COLLISION
.m_rx_d_8(m_rx_d_8), //INPUT : MII RX DATA
.m_rx_en_8(m_rx_en_8), //INPUT : MII RX VALID INDICATION
.m_rx_err_8(m_rx_err_8), //INPUT : MII RX ERROR INDICATION
.m_tx_d_8(m_tx_d_8), //OUTPUT : MII TX DATA
.m_tx_en_8(m_tx_en_8), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_8(m_tx_err_8), //OUTPUT : MII TX ERROR INDICATION
.rx_control_8(rx_control_8), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_8(rgmii_in_8), //INPUT : RGMII RX DATA INDICATION
.tx_control_8(tx_control_8), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_8(rgmii_out_8), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_8(eth_mode_8), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_8(ena_10_8), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_8(set_10_8), //INPUT : SPEED 10 MBPS
.set_1000_8(set_1000_8), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.rx_clk_9(rx_clk_9), //INPUT : MAC RX CLK
.tx_clk_9(tx_clk_9), //INPUT : MAC TX CLK
.gm_rx_d_9(gm_rx_d_9), //INPUT : GMII RX DATA
.gm_rx_dv_9(gm_rx_dv_9), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_9(gm_rx_err_9), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_9(gm_tx_d_9), //OUTPUT : GMII TX DATA
.gm_tx_en_9(gm_tx_en_9), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_9(gm_tx_err_9), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_9(m_rx_crs_9), //INPUT : MII RX CARRIER SENSE
.m_rx_col_9(m_rx_col_9), //INPUT : MII RX COLLISION
.m_rx_d_9(m_rx_d_9), //INPUT : MII RX DATA
.m_rx_en_9(m_rx_en_9), //INPUT : MII RX VALID INDICATION
.m_rx_err_9(m_rx_err_9), //INPUT : MII RX ERROR INDICATION
.m_tx_d_9(m_tx_d_9), //OUTPUT : MII TX DATA
.m_tx_en_9(m_tx_en_9), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_9(m_tx_err_9), //OUTPUT : MII TX ERROR INDICATION
.rx_control_9(rx_control_9), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_9(rgmii_in_9), //INPUT : RGMII RX DATA INDICATION
.tx_control_9(tx_control_9), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_9(rgmii_out_9), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_9(eth_mode_9), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_9(ena_10_9), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_9(set_10_9), //INPUT : SPEED 10 MBPS
.set_1000_9(set_1000_9), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.rx_clk_10(rx_clk_10), //INPUT : MAC RX CLK
.tx_clk_10(tx_clk_10), //INPUT : MAC TX CLK
.gm_rx_d_10(gm_rx_d_10), //INPUT : GMII RX DATA
.gm_rx_dv_10(gm_rx_dv_10), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_10(gm_rx_err_10), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_10(gm_tx_d_10), //OUTPUT : GMII TX DATA
.gm_tx_en_10(gm_tx_en_10), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_10(gm_tx_err_10), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_10(m_rx_crs_10), //INPUT : MII RX CARRIER SENSE
.m_rx_col_10(m_rx_col_10), //INPUT : MII RX COLLISION
.m_rx_d_10(m_rx_d_10), //INPUT : MII RX DATA
.m_rx_en_10(m_rx_en_10), //INPUT : MII RX VALID INDICATION
.m_rx_err_10(m_rx_err_10), //INPUT : MII RX ERROR INDICATION
.m_tx_d_10(m_tx_d_10), //OUTPUT : MII TX DATA
.m_tx_en_10(m_tx_en_10), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_10(m_tx_err_10), //OUTPUT : MII TX ERROR INDICATION
.rx_control_10(rx_control_10), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_10(rgmii_in_10), //INPUT : RGMII RX DATA INDICATION
.tx_control_10(tx_control_10), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_10(rgmii_out_10), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_10(eth_mode_10), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_10(ena_10_10), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_10(set_10_10), //INPUT : SPEED 10 MBPS
.set_1000_10(set_1000_10), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.rx_clk_11(rx_clk_11), //INPUT : MAC RX CLK
.tx_clk_11(tx_clk_11), //INPUT : MAC TX CLK
.gm_rx_d_11(gm_rx_d_11), //INPUT : GMII RX DATA
.gm_rx_dv_11(gm_rx_dv_11), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_11(gm_rx_err_11), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_11(gm_tx_d_11), //OUTPUT : GMII TX DATA
.gm_tx_en_11(gm_tx_en_11), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_11(gm_tx_err_11), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_11(m_rx_crs_11), //INPUT : MII RX CARRIER SENSE
.m_rx_col_11(m_rx_col_11), //INPUT : MII RX COLLISION
.m_rx_d_11(m_rx_d_11), //INPUT : MII RX DATA
.m_rx_en_11(m_rx_en_11), //INPUT : MII RX VALID INDICATION
.m_rx_err_11(m_rx_err_11), //INPUT : MII RX ERROR INDICATION
.m_tx_d_11(m_tx_d_11), //OUTPUT : MII TX DATA
.m_tx_en_11(m_tx_en_11), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_11(m_tx_err_11), //OUTPUT : MII TX ERROR INDICATION
.rx_control_11(rx_control_11), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_11(rgmii_in_11), //INPUT : RGMII RX DATA INDICATION
.tx_control_11(tx_control_11), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_11(rgmii_out_11), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_11(eth_mode_11), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_11(ena_10_11), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_11(set_10_11), //INPUT : SPEED 10 MBPS
.set_1000_11(set_1000_11), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.rx_clk_12(rx_clk_12), //INPUT : MAC RX CLK
.tx_clk_12(tx_clk_12), //INPUT : MAC TX CLK
.gm_rx_d_12(gm_rx_d_12), //INPUT : GMII RX DATA
.gm_rx_dv_12(gm_rx_dv_12), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_12(gm_rx_err_12), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_12(gm_tx_d_12), //OUTPUT : GMII TX DATA
.gm_tx_en_12(gm_tx_en_12), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_12(gm_tx_err_12), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_12(m_rx_crs_12), //INPUT : MII RX CARRIER SENSE
.m_rx_col_12(m_rx_col_12), //INPUT : MII RX COLLISION
.m_rx_d_12(m_rx_d_12), //INPUT : MII RX DATA
.m_rx_en_12(m_rx_en_12), //INPUT : MII RX VALID INDICATION
.m_rx_err_12(m_rx_err_12), //INPUT : MII RX ERROR INDICATION
.m_tx_d_12(m_tx_d_12), //OUTPUT : MII TX DATA
.m_tx_en_12(m_tx_en_12), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_12(m_tx_err_12), //OUTPUT : MII TX ERROR INDICATION
.rx_control_12(rx_control_12), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_12(rgmii_in_12), //INPUT : RGMII RX DATA INDICATION
.tx_control_12(tx_control_12), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_12(rgmii_out_12), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_12(eth_mode_12), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_12(ena_10_12), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_12(set_10_12), //INPUT : SPEED 10 MBPS
.set_1000_12(set_1000_12), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.rx_clk_13(rx_clk_13), //INPUT : MAC RX CLK
.tx_clk_13(tx_clk_13), //INPUT : MAC TX CLK
.gm_rx_d_13(gm_rx_d_13), //INPUT : GMII RX DATA
.gm_rx_dv_13(gm_rx_dv_13), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_13(gm_rx_err_13), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_13(gm_tx_d_13), //OUTPUT : GMII TX DATA
.gm_tx_en_13(gm_tx_en_13), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_13(gm_tx_err_13), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_13(m_rx_crs_13), //INPUT : MII RX CARRIER SENSE
.m_rx_col_13(m_rx_col_13), //INPUT : MII RX COLLISION
.m_rx_d_13(m_rx_d_13), //INPUT : MII RX DATA
.m_rx_en_13(m_rx_en_13), //INPUT : MII RX VALID INDICATION
.m_rx_err_13(m_rx_err_13), //INPUT : MII RX ERROR INDICATION
.m_tx_d_13(m_tx_d_13), //OUTPUT : MII TX DATA
.m_tx_en_13(m_tx_en_13), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_13(m_tx_err_13), //OUTPUT : MII TX ERROR INDICATION
.rx_control_13(rx_control_13), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_13(rgmii_in_13), //INPUT : RGMII RX DATA INDICATION
.tx_control_13(tx_control_13), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_13(rgmii_out_13), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_13(eth_mode_13), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_13(ena_10_13), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_13(set_10_13), //INPUT : SPEED 10 MBPS
.set_1000_13(set_1000_13), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.rx_clk_14(rx_clk_14), //INPUT : MAC RX CLK
.tx_clk_14(tx_clk_14), //INPUT : MAC TX CLK
.gm_rx_d_14(gm_rx_d_14), //INPUT : GMII RX DATA
.gm_rx_dv_14(gm_rx_dv_14), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_14(gm_rx_err_14), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_14(gm_tx_d_14), //OUTPUT : GMII TX DATA
.gm_tx_en_14(gm_tx_en_14), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_14(gm_tx_err_14), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_14(m_rx_crs_14), //INPUT : MII RX CARRIER SENSE
.m_rx_col_14(m_rx_col_14), //INPUT : MII RX COLLISION
.m_rx_d_14(m_rx_d_14), //INPUT : MII RX DATA
.m_rx_en_14(m_rx_en_14), //INPUT : MII RX VALID INDICATION
.m_rx_err_14(m_rx_err_14), //INPUT : MII RX ERROR INDICATION
.m_tx_d_14(m_tx_d_14), //OUTPUT : MII TX DATA
.m_tx_en_14(m_tx_en_14), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_14(m_tx_err_14), //OUTPUT : MII TX ERROR INDICATION
.rx_control_14(rx_control_14), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_14(rgmii_in_14), //INPUT : RGMII RX DATA INDICATION
.tx_control_14(tx_control_14), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_14(rgmii_out_14), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_14(eth_mode_14), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_14(ena_10_14), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_14(set_10_14), //INPUT : SPEED 10 MBPS
.set_1000_14(set_1000_14), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.rx_clk_15(rx_clk_15), //INPUT : MAC RX CLK
.tx_clk_15(tx_clk_15), //INPUT : MAC TX CLK
.gm_rx_d_15(gm_rx_d_15), //INPUT : GMII RX DATA
.gm_rx_dv_15(gm_rx_dv_15), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_15(gm_rx_err_15), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_15(gm_tx_d_15), //OUTPUT : GMII TX DATA
.gm_tx_en_15(gm_tx_en_15), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_15(gm_tx_err_15), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_15(m_rx_crs_15), //INPUT : MII RX CARRIER SENSE
.m_rx_col_15(m_rx_col_15), //INPUT : MII RX COLLISION
.m_rx_d_15(m_rx_d_15), //INPUT : MII RX DATA
.m_rx_en_15(m_rx_en_15), //INPUT : MII RX VALID INDICATION
.m_rx_err_15(m_rx_err_15), //INPUT : MII RX ERROR INDICATION
.m_tx_d_15(m_tx_d_15), //OUTPUT : MII TX DATA
.m_tx_en_15(m_tx_en_15), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_15(m_tx_err_15), //OUTPUT : MII TX ERROR INDICATION
.rx_control_15(rx_control_15), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_15(rgmii_in_15), //INPUT : RGMII RX DATA INDICATION
.tx_control_15(tx_control_15), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_15(rgmii_out_15), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_15(eth_mode_15), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_15(ena_10_15), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_15(set_10_15), //INPUT : SPEED 10 MBPS
.set_1000_15(set_1000_15), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.rx_clk_16(rx_clk_16), //INPUT : MAC RX CLK
.tx_clk_16(tx_clk_16), //INPUT : MAC TX CLK
.gm_rx_d_16(gm_rx_d_16), //INPUT : GMII RX DATA
.gm_rx_dv_16(gm_rx_dv_16), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_16(gm_rx_err_16), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_16(gm_tx_d_16), //OUTPUT : GMII TX DATA
.gm_tx_en_16(gm_tx_en_16), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_16(gm_tx_err_16), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_16(m_rx_crs_16), //INPUT : MII RX CARRIER SENSE
.m_rx_col_16(m_rx_col_16), //INPUT : MII RX COLLISION
.m_rx_d_16(m_rx_d_16), //INPUT : MII RX DATA
.m_rx_en_16(m_rx_en_16), //INPUT : MII RX VALID INDICATION
.m_rx_err_16(m_rx_err_16), //INPUT : MII RX ERROR INDICATION
.m_tx_d_16(m_tx_d_16), //OUTPUT : MII TX DATA
.m_tx_en_16(m_tx_en_16), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_16(m_tx_err_16), //OUTPUT : MII TX ERROR INDICATION
.rx_control_16(rx_control_16), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_16(rgmii_in_16), //INPUT : RGMII RX DATA INDICATION
.tx_control_16(tx_control_16), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_16(rgmii_out_16), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_16(eth_mode_16), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_16(ena_10_16), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_16(set_10_16), //INPUT : SPEED 10 MBPS
.set_1000_16(set_1000_16), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.rx_clk_17(rx_clk_17), //INPUT : MAC RX CLK
.tx_clk_17(tx_clk_17), //INPUT : MAC TX CLK
.gm_rx_d_17(gm_rx_d_17), //INPUT : GMII RX DATA
.gm_rx_dv_17(gm_rx_dv_17), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_17(gm_rx_err_17), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_17(gm_tx_d_17), //OUTPUT : GMII TX DATA
.gm_tx_en_17(gm_tx_en_17), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_17(gm_tx_err_17), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_17(m_rx_crs_17), //INPUT : MII RX CARRIER SENSE
.m_rx_col_17(m_rx_col_17), //INPUT : MII RX COLLISION
.m_rx_d_17(m_rx_d_17), //INPUT : MII RX DATA
.m_rx_en_17(m_rx_en_17), //INPUT : MII RX VALID INDICATION
.m_rx_err_17(m_rx_err_17), //INPUT : MII RX ERROR INDICATION
.m_tx_d_17(m_tx_d_17), //OUTPUT : MII TX DATA
.m_tx_en_17(m_tx_en_17), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_17(m_tx_err_17), //OUTPUT : MII TX ERROR INDICATION
.rx_control_17(rx_control_17), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_17(rgmii_in_17), //INPUT : RGMII RX DATA INDICATION
.tx_control_17(tx_control_17), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_17(rgmii_out_17), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_17(eth_mode_17), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_17(ena_10_17), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_17(set_10_17), //INPUT : SPEED 10 MBPS
.set_1000_17(set_1000_17), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.rx_clk_18(rx_clk_18), //INPUT : MAC RX CLK
.tx_clk_18(tx_clk_18), //INPUT : MAC TX CLK
.gm_rx_d_18(gm_rx_d_18), //INPUT : GMII RX DATA
.gm_rx_dv_18(gm_rx_dv_18), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_18(gm_rx_err_18), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_18(gm_tx_d_18), //OUTPUT : GMII TX DATA
.gm_tx_en_18(gm_tx_en_18), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_18(gm_tx_err_18), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_18(m_rx_crs_18), //INPUT : MII RX CARRIER SENSE
.m_rx_col_18(m_rx_col_18), //INPUT : MII RX COLLISION
.m_rx_d_18(m_rx_d_18), //INPUT : MII RX DATA
.m_rx_en_18(m_rx_en_18), //INPUT : MII RX VALID INDICATION
.m_rx_err_18(m_rx_err_18), //INPUT : MII RX ERROR INDICATION
.m_tx_d_18(m_tx_d_18), //OUTPUT : MII TX DATA
.m_tx_en_18(m_tx_en_18), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_18(m_tx_err_18), //OUTPUT : MII TX ERROR INDICATION
.rx_control_18(rx_control_18), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_18(rgmii_in_18), //INPUT : RGMII RX DATA INDICATION
.tx_control_18(tx_control_18), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_18(rgmii_out_18), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_18(eth_mode_18), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_18(ena_10_18), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_18(set_10_18), //INPUT : SPEED 10 MBPS
.set_1000_18(set_1000_18), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.rx_clk_19(rx_clk_19), //INPUT : MAC RX CLK
.tx_clk_19(tx_clk_19), //INPUT : MAC TX CLK
.gm_rx_d_19(gm_rx_d_19), //INPUT : GMII RX DATA
.gm_rx_dv_19(gm_rx_dv_19), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_19(gm_rx_err_19), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_19(gm_tx_d_19), //OUTPUT : GMII TX DATA
.gm_tx_en_19(gm_tx_en_19), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_19(gm_tx_err_19), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_19(m_rx_crs_19), //INPUT : MII RX CARRIER SENSE
.m_rx_col_19(m_rx_col_19), //INPUT : MII RX COLLISION
.m_rx_d_19(m_rx_d_19), //INPUT : MII RX DATA
.m_rx_en_19(m_rx_en_19), //INPUT : MII RX VALID INDICATION
.m_rx_err_19(m_rx_err_19), //INPUT : MII RX ERROR INDICATION
.m_tx_d_19(m_tx_d_19), //OUTPUT : MII TX DATA
.m_tx_en_19(m_tx_en_19), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_19(m_tx_err_19), //OUTPUT : MII TX ERROR INDICATION
.rx_control_19(rx_control_19), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_19(rgmii_in_19), //INPUT : RGMII RX DATA INDICATION
.tx_control_19(tx_control_19), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_19(rgmii_out_19), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_19(eth_mode_19), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_19(ena_10_19), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_19(set_10_19), //INPUT : SPEED 10 MBPS
.set_1000_19(set_1000_19), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.rx_clk_20(rx_clk_20), //INPUT : MAC RX CLK
.tx_clk_20(tx_clk_20), //INPUT : MAC TX CLK
.gm_rx_d_20(gm_rx_d_20), //INPUT : GMII RX DATA
.gm_rx_dv_20(gm_rx_dv_20), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_20(gm_rx_err_20), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_20(gm_tx_d_20), //OUTPUT : GMII TX DATA
.gm_tx_en_20(gm_tx_en_20), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_20(gm_tx_err_20), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_20(m_rx_crs_20), //INPUT : MII RX CARRIER SENSE
.m_rx_col_20(m_rx_col_20), //INPUT : MII RX COLLISION
.m_rx_d_20(m_rx_d_20), //INPUT : MII RX DATA
.m_rx_en_20(m_rx_en_20), //INPUT : MII RX VALID INDICATION
.m_rx_err_20(m_rx_err_20), //INPUT : MII RX ERROR INDICATION
.m_tx_d_20(m_tx_d_20), //OUTPUT : MII TX DATA
.m_tx_en_20(m_tx_en_20), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_20(m_tx_err_20), //OUTPUT : MII TX ERROR INDICATION
.rx_control_20(rx_control_20), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_20(rgmii_in_20), //INPUT : RGMII RX DATA INDICATION
.tx_control_20(tx_control_20), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_20(rgmii_out_20), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_20(eth_mode_20), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_20(ena_10_20), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_20(set_10_20), //INPUT : SPEED 10 MBPS
.set_1000_20(set_1000_20), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.rx_clk_21(rx_clk_21), //INPUT : MAC RX CLK
.tx_clk_21(tx_clk_21), //INPUT : MAC TX CLK
.gm_rx_d_21(gm_rx_d_21), //INPUT : GMII RX DATA
.gm_rx_dv_21(gm_rx_dv_21), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_21(gm_rx_err_21), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_21(gm_tx_d_21), //OUTPUT : GMII TX DATA
.gm_tx_en_21(gm_tx_en_21), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_21(gm_tx_err_21), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_21(m_rx_crs_21), //INPUT : MII RX CARRIER SENSE
.m_rx_col_21(m_rx_col_21), //INPUT : MII RX COLLISION
.m_rx_d_21(m_rx_d_21), //INPUT : MII RX DATA
.m_rx_en_21(m_rx_en_21), //INPUT : MII RX VALID INDICATION
.m_rx_err_21(m_rx_err_21), //INPUT : MII RX ERROR INDICATION
.m_tx_d_21(m_tx_d_21), //OUTPUT : MII TX DATA
.m_tx_en_21(m_tx_en_21), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_21(m_tx_err_21), //OUTPUT : MII TX ERROR INDICATION
.rx_control_21(rx_control_21), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_21(rgmii_in_21), //INPUT : RGMII RX DATA INDICATION
.tx_control_21(tx_control_21), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_21(rgmii_out_21), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_21(eth_mode_21), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_21(ena_10_21), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_21(set_10_21), //INPUT : SPEED 10 MBPS
.set_1000_21(set_1000_21), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.rx_clk_22(rx_clk_22), //INPUT : MAC RX CLK
.tx_clk_22(tx_clk_22), //INPUT : MAC TX CLK
.gm_rx_d_22(gm_rx_d_22), //INPUT : GMII RX DATA
.gm_rx_dv_22(gm_rx_dv_22), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_22(gm_rx_err_22), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_22(gm_tx_d_22), //OUTPUT : GMII TX DATA
.gm_tx_en_22(gm_tx_en_22), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_22(gm_tx_err_22), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_22(m_rx_crs_22), //INPUT : MII RX CARRIER SENSE
.m_rx_col_22(m_rx_col_22), //INPUT : MII RX COLLISION
.m_rx_d_22(m_rx_d_22), //INPUT : MII RX DATA
.m_rx_en_22(m_rx_en_22), //INPUT : MII RX VALID INDICATION
.m_rx_err_22(m_rx_err_22), //INPUT : MII RX ERROR INDICATION
.m_tx_d_22(m_tx_d_22), //OUTPUT : MII TX DATA
.m_tx_en_22(m_tx_en_22), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_22(m_tx_err_22), //OUTPUT : MII TX ERROR INDICATION
.rx_control_22(rx_control_22), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_22(rgmii_in_22), //INPUT : RGMII RX DATA INDICATION
.tx_control_22(tx_control_22), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_22(rgmii_out_22), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_22(eth_mode_22), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_22(ena_10_22), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_22(set_10_22), //INPUT : SPEED 10 MBPS
.set_1000_22(set_1000_22), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.rx_clk_23(rx_clk_23), //INPUT : MAC RX CLK
.tx_clk_23(tx_clk_23), //INPUT : MAC TX CLK
.gm_rx_d_23(gm_rx_d_23), //INPUT : GMII RX DATA
.gm_rx_dv_23(gm_rx_dv_23), //INPUT : GMII RX VALID INDICATION
.gm_rx_err_23(gm_rx_err_23), //INPUT : GMII RX ERROR INDICATION
.gm_tx_d_23(gm_tx_d_23), //OUTPUT : GMII TX DATA
.gm_tx_en_23(gm_tx_en_23), //OUTPUT : GMII TX VALID INDICATION
.gm_tx_err_23(gm_tx_err_23), //OUTPUT : GMII TX ERROR INDICATION
.m_rx_crs_23(m_rx_crs_23), //INPUT : MII RX CARRIER SENSE
.m_rx_col_23(m_rx_col_23), //INPUT : MII RX COLLISION
.m_rx_d_23(m_rx_d_23), //INPUT : MII RX DATA
.m_rx_en_23(m_rx_en_23), //INPUT : MII RX VALID INDICATION
.m_rx_err_23(m_rx_err_23), //INPUT : MII RX ERROR INDICATION
.m_tx_d_23(m_tx_d_23), //OUTPUT : MII TX DATA
.m_tx_en_23(m_tx_en_23), //OUTPUT : MII TX VALID INDICATION
.m_tx_err_23(m_tx_err_23), //OUTPUT : MII TX ERROR INDICATION
.rx_control_23(rx_control_23), //INPUT : RGMII RX CONTROL INDICATION
.rgmii_in_23(rgmii_in_23), //INPUT : RGMII RX DATA INDICATION
.tx_control_23(tx_control_23), //OUTPUT : RGMII TX CONTROL INDICATION
.rgmii_out_23(rgmii_out_23), //OUTPUT : RGMII TX DATA INDICATION
.eth_mode_23(eth_mode_23), //OUTPUT : ETHERNET SPEED 1000MBPS INDICATION
.ena_10_23(ena_10_23), //OUTPUT : SPEED 10 MBPS INDICATION
.set_10_23(set_10_23), //INPUT : SPEED 10 MBPS
.set_1000_23(set_1000_23), //INPUT : SPEED 1000 MBPS
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_TOP_MULTI_MAC.USE_SYNC_RESET = USE_SYNC_RESET,
U_TOP_MULTI_MAC.RESET_LEVEL = RESET_LEVEL,
U_TOP_MULTI_MAC.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_TOP_MULTI_MAC.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_TOP_MULTI_MAC.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_TOP_MULTI_MAC.ENA_HASH = ENA_HASH,
U_TOP_MULTI_MAC.STAT_CNT_ENA = STAT_CNT_ENA,
U_TOP_MULTI_MAC.CORE_VERSION = CORE_VERSION,
U_TOP_MULTI_MAC.CUST_VERSION = CUST_VERSION,
U_TOP_MULTI_MAC.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_TOP_MULTI_MAC.ENABLE_MDIO = ENABLE_MDIO,
U_TOP_MULTI_MAC.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_TOP_MULTI_MAC.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_TOP_MULTI_MAC.CRC32DWIDTH = CRC32DWIDTH,
U_TOP_MULTI_MAC.CRC32GENDELAY = CRC32GENDELAY,
U_TOP_MULTI_MAC.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_TOP_MULTI_MAC.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_TOP_MULTI_MAC.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_TOP_MULTI_MAC.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_TOP_MULTI_MAC.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_TOP_MULTI_MAC.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_TOP_MULTI_MAC.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_TOP_MULTI_MAC.ADDR_WIDTH = ADDR_WIDTH,
U_TOP_MULTI_MAC.MAX_CHANNELS = MAX_CHANNELS,
U_TOP_MULTI_MAC.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_TOP_MULTI_MAC.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_TOP_MULTI_MAC.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_TOP_MULTI_MAC.ENABLE_REG_SHARING = ENABLE_REG_SHARING,
U_TOP_MULTI_MAC.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
U_TOP_MULTI_MAC.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING;
endmodule // module altera_tse_multi_mac
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_TB_V
`define SKY130_FD_SC_HD__AND4BB_TB_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_hd__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVPWRVGND_1_V
`define SKY130_FD_SC_HDLL__TAPVPWRVGND_1_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog wrapper for tapvpwrvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tapvpwrvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__tapvpwrvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVPWRVGND_1_V
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={650.000000} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525.000000} readRate={0.5} writeRate={0.5} /><IO interface={Timer} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={108.333336} usageRate={0.5} /><IO interface={SPI} ioStandard={} bidis={0} ioBank={} clockFreq={166.666672} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=525.000000, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.034, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.03, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.082, PCW_UIPARAM_DDR_BOARD_DELAY0=0.176, PCW_UIPARAM_DDR_BOARD_DELAY1=0.159, PCW_UIPARAM_DDR_BOARD_DELAY2=0.162, PCW_UIPARAM_DDR_BOARD_DELAY3=0.187, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=27.85, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=22.87, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=22.9, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=29.9, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=27, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=22.8, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=24, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=30.45, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=20.6, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=165, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50.000000, PCW_APU_PERIPHERAL_FREQMHZ=650.000000, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=175.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=12.288000, PCW_FPGA3_PERIPHERAL_FREQMHZ=100.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K128M16 JT-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=1, PCW_SPI0_SPI0_IO=EMIO, PCW_SPI0_GRP_SS0_ENABLE=1, PCW_SPI0_GRP_SS0_IO=EMIO, PCW_SPI0_GRP_SS1_ENABLE=1, PCW_SPI0_GRP_SS1_IO=EMIO, PCW_SPI0_GRP_SS2_ENABLE=1, PCW_SPI0_GRP_SS2_IO=EMIO, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=MIO 42 .. 43, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=0, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=DDR PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=ARM PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=1, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "block_design_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
secret_sub secret_inst (.*);
secret_other secret_inst2 (.*);
endmodule
module secret_sub
(
input clk);
// verilator no_inline_module
integer secret_cyc;
real secret_cyc_r;
integer secret_o;
real secret_r;
export "DPI-C" task dpix_a_task;
task dpix_a_task(input int i, output int o); o = i + 1; endtask
import "DPI-C" context task dpii_a_task(input int i, output int o);
export "DPI-C" function dpix_a_func;
function int dpix_a_func(input int i); return i + 2; endfunction
import "DPI-C" context function int dpii_a_func(input int i);
// Test loop
always @ (posedge clk) begin
secret_cyc_r = $itor(secret_cyc)/10.0 - 5.0;
secret_cyc <= dpii_a_func(secret_cyc);
secret_r += 1.0 + $cos(secret_cyc_r);
dpix_a_task(secret_cyc, secret_o);
if (secret_cyc==90) begin
$write("*-* All Finished *-*\n");
end
end
endmodule
module secret_other
(
input clk);
integer secret_cyc;
always @ (posedge clk) begin
secret_cyc <= secret_cyc + 1;
if (secret_cyc==99) begin
$finish;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06:43:33 11/30/2014
// Design Name:
// Module Name: FSMNeuronalNetwork
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSMNeuronalNetwork(CLK, reset,Start,Read,Address,ResetInterfaz,ResetStart,ResetCoeffALUandInput,
EnableCoeffALUandInput,SELCoeff,EnableSumALU,EnableMultALU,EnableAcumulador,ResetAcumulador,EnableFuncActivacion,
EnableRegisterOutput,ResetRegisterOutput,Listo);
input CLK;
input reset;
input Start;
input Read;
input [8:0] Address;
output reg ResetInterfaz =0;
output reg ResetStart=0;
output reg ResetCoeffALUandInput=0;
output reg EnableCoeffALUandInput=0;
output reg [4:0] SELCoeff=0;
output reg EnableSumALU=0;
output reg EnableMultALU=0;
output reg EnableAcumulador=0;
output reg ResetAcumulador=0;
output reg EnableFuncActivacion=0;
output reg EnableRegisterOutput=0;
output reg ResetRegisterOutput=0;
output reg Listo=0;
//** Registros de la Maquina de Estados***********************************************************************************
reg[5:0] State = 0;
reg [5:0] NextState = 0;
parameter S1=5'd1, S2=5'd2, S3=5'd3, S4=5'd4, S5=5'd5, S6=5'd6, S7=5'd7, S8=5'd8, S9=5'd9, S10=5'd10,
S11=5'd11, S12=5'd12, S13=5'd13, S14=5'd14, S15=5'd15, S16=5'd16, S17=5'd17, S18=5'd18, S19=5'd19, S20=5'd20,
S21=5'd21, S22=5'd22, S23=5'd23, S24=5'd24, S25=5'd25, S26=5'd26, S27=5'd27, S28=5'd28, S29=5'd29, S30=5'd30,
S31=5'd31, RESETEADOR=5'd00;
//******************************** FIN DE DECLARACIÓN DE REGISTROS Y PAMAMETROS MAQUIINA DE ESTADOS***********************************
// *********************Registro de estado *********************************************************
always @(posedge CLK) begin //or posedge reset) begin
begin
if(reset)
State<=RESETEADOR;
else
State<=NextState;
end
end
// Lógica combinacional de estado siguiente ************************************
always @*
begin
case(State)
RESETEADOR: begin //***********ESTADO DE RESET DEL SISTEMA
if (reset) NextState <= RESETEADOR;
else NextState <= S1;
end
S1: begin //***********ESTADO DE ESPERA INICIO
if (Start) NextState <= S2;
else NextState <= S1;
end
S2: begin // ****************ESTADO DE HABILITA EnableCoeffALUandInput
NextState <= S3;
end
S3: begin // ***********SELCoeff = 00 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S4;
end
S4: begin // ***********SELCoeff = 01 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S5;
end
S5: begin // ***********SELCoeff = 02 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S6;
end
S6: begin // ***********SELCoeff = 03 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S7;
end
S7: begin // ***********SELCoeff = 04 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S8;
end
S8: begin // ***********SELCoeff = 05 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S9;
end
S9: begin // ***********SELCoeff = 06 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S10;
end
S10: begin // ***********SELCoeff = 07 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S11;
end
S11: begin /// ***********SELCoeff = 08 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S12;
end
S12: begin // ***********SELCoeff = 09 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S13;
end
S13: begin // ***********SELCoeff = 10 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S14;
end
S14: begin // ***********SELCoeff = 11 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S15;
end
S15: begin // ***********SELCoeff = 12 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S16;
end
S16: begin // ***********SELCoeff = 13 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S17;
end
S17: begin // ***********SELCoeff = 14 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S18;
end
S18: begin // ***********SELCoeff = 15 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S19;
end
S19: begin // ***********SELCoeff = 16 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S20;
end
S20: begin // ***********SELCoeff = 17 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S21;
end
S21: begin // ***********SELCoeff = 18 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
NextState <= S22;
end
S22: begin // ***********SELCoeff = 19 y EnableSumALU = 1, EnableMultALU = 0, EnableAcum = 1
NextState <= S23;
end
S23: begin // ***********SELCoeff = 20 y EnableSumALU = 1, EnableMultALU = 0, EnableAcum = 1
NextState <= S24;
end
S24: begin // ***********SELCoeff = xx y EnableSumALU = 0, EnableMultALU = 0, EnableAcum = 0
NextState <= S25;
end
S25: begin // ***********EnableFuncActivation = 1 EnableAcum = 0
NextState <= S26;
end
S26: begin // ***********EnableFuncActivation = 1 EnableAcum = 0 EnableRegisterOutput = 1
NextState <= S27;
end
S27: begin // ***********EnableFuncActivation = 0 EnableAcum = 0 EnableRegisterOutput = 0, Listo = 1
if(Address==9'h050 && Read == 1'b1) NextState <= S28; // Direccion de memoria donde se hace la ultima lectura
else NextState <= S27;
end
S28: begin // ***********EnableFuncActivation = 0 EnableAcum = 0 EnableRegisterOutput = 0, Listo = 1
if(Address==9'h050 && Read == 1'b1) NextState <= S28; // Direccion de memoria donde se hace la ultima lectura
else NextState <= S29;
end
S29: begin // Estado de resetea todos los registros excepto el reset
NextState <= S1;
end
default: begin // Salidas por defecto iguales a la del ResetInterfaz
NextState <= RESETEADOR;
end
endcase
end
//********************************************LOGICA DE SALIDA COMBINACIONAL*********************************************
always @*
begin
case(State)
RESETEADOR: begin //***********ESTADO DE RESET DEL SISTEMA
ResetInterfaz <=1;
ResetStart<=1;
ResetCoeffALUandInput<=1;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=1;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=1;
Listo<=0;
end
S1: begin //***********ESTADO DE ESPERA INICIO
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S2: begin // ****************ESTADO DE HABILITA EnableCoeffALUandInput
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=1;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S3: begin // ***********SELCoeff = 00 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S4: begin // ***********SELCoeff = 01 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=1;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S5: begin // ***********SELCoeff = 02 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=2;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S6: begin // ***********SELCoeff = 03 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=3;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S7: begin // ***********SELCoeff = 04 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=4;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S8: begin // ***********SELCoeff = 05 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=5;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S9: begin // ***********SELCoeff = 06 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=6;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S10: begin // ***********SELCoeff = 07 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=7;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S11: begin /// ***********SELCoeff = 08 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=8;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S12: begin // ***********SELCoeff = 09 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=9;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S13: begin // ***********SELCoeff = 10 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=10;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S14: begin // ***********SELCoeff = 11 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=11;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S15: begin // ***********SELCoeff = 12 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=12;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S16: begin // ***********SELCoeff = 13 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=13;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S17: begin // ***********SELCoeff = 14 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=14;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S18: begin // ***********SELCoeff = 15 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=15;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S19: begin // ***********SELCoeff = 16 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=16;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S20: begin // ***********SELCoeff = 17 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=17;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S21: begin // ***********SELCoeff = 18 y EnableSumALU = 1, EnableMultALU = 1, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=18;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S22: begin // ***********SELCoeff = 19 y EnableSumALU = 1, EnableMultALU = 0, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=19;
EnableSumALU<=1;
EnableMultALU<=1;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S23: begin // ***********SELCoeff = 20 y EnableSumALU = 1, EnableMultALU = 0, EnableAcum = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=20;
EnableSumALU<=1;
EnableMultALU<=0;
EnableAcumulador<=1;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S24: begin // ***********SELCoeff = xx y EnableSumALU = 0, EnableMultALU = 0, EnableAcum = 0
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S25: begin // ***********EnableFuncActivation = 1 EnableAcum = 0
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
EnableFuncActivacion<=1;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=0;
end
S26: begin // ***********EnableFuncActivation = 1 EnableAcum = 0 EnableRegisterOutput = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
EnableFuncActivacion<=1;
EnableRegisterOutput<=1;
ResetRegisterOutput<=0;
Listo<=0;
end
S27: begin // ***********EnableFuncActivation = 0 EnableAcum = 0 EnableRegisterOutput = 0, Listo = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=1;
end
S28: begin // ***********EnableFuncActivation = 0 EnableAcum = 0 EnableRegisterOutput = 0, Listo = 1
ResetInterfaz <=0;
ResetStart<=0;
ResetCoeffALUandInput<=0;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=0;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=0;
Listo<=1;
end
S29: begin // Estado de resetea todos los registros excepto el reset
ResetInterfaz <=0;
ResetStart<=1;
ResetCoeffALUandInput<=1;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=1;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=1;
Listo<=0;
end
default: begin // Salidas por defecto iguales a la del reset
ResetInterfaz <=1;
ResetStart<=1;
ResetCoeffALUandInput<=1;
EnableCoeffALUandInput<=0;
SELCoeff<=0;
EnableSumALU<=0;
EnableMultALU<=0;
EnableAcumulador<=0;
ResetAcumulador<=1;
EnableFuncActivacion<=0;
EnableRegisterOutput<=0;
ResetRegisterOutput<=1;
Listo<=0;
end
endcase
end
endmodule
|
`timescale 1 ps / 1 ps
module system_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
system system_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFRBP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_SYMBOL_V
|
`timescale 1 ns / 1 ps
/*******************************************************************************
* DescriPixtion: Compute pixel value based on context
* Latency: 800*1.5
******************************************************************************/
module lbp #(
parameter CTX_SIZE = 3,
parameter WIDTH = 12,
parameter LINE_LENGTH = 800
)(
input iClk,
input [7:0] iR,
input [7:0] iG,
input [7:0] iB,
input iHSync,
input iVSync,
input iLineValid,
input iFrameValid,
output [7:0] oY,
output oHSync,
output oVSync,
output oLineValid,
output oFrameValid
);
/*******************************************************************************
* Wiring
******************************************************************************/
wire [7:0] wGray;
wire wHSync;
wire wVSync;
wire wLineValid;
wire wFrameValid;
/*******************************************************************************
* Context wiring
******************************************************************************/
wire [11:0] wChain [CTX_SIZE-1:0][CTX_SIZE:0];
/*******************************************************************************
* Assignments
******************************************************************************/
assign wChain[0][0] = { wGray, wHSync, wVSync, wLineValid, wFrameValid};
assign oHSync = wChain[1][1][3];
assign oVSync = wChain[1][1][2];
assign oLineValid = wChain[1][1][1];
assign oFrameValid = wChain[1][1][0];
assign oY = { wChain[0][0][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[0][1][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[0][2][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[1][2][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[2][2][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[2][1][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[2][0][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[1][0][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1 };
/*******************************************************************************
* Delays generator
******************************************************************************/
genvar i;
genvar j;
generate
for(i = 0; i < CTX_SIZE; i = i + 1)
begin : ctx_delay_inst
for(j = 0; j < (CTX_SIZE - 1); j = j + 1)
begin : ctx_latches_inst
wlatch #(
.WIDTH(WIDTH)
) lth (
.ce(1),
.rst(0),
.clk(iClk),
.in( wChain[i][j]),
.out(wChain[i][j+1])
);
end
delayLine#(
.WIDTH(WIDTH),
.DELAY(LINE_LENGTH - CTX_SIZE + 1)
) ctxDelay (
.ce(1),
.rst(0),
.clk(iClk),
.in( wChain[i][CTX_SIZE-1]),
.out(wChain[i][CTX_SIZE])
);
if(i < (CTX_SIZE - 1)) assign wChain[i][CTX_SIZE] = wChain[i+1][0];
end
endgenerate
/*******************************************************************************
* Convert to grayscale
******************************************************************************/
rgb2gray u1 (
.iClk(iClk),
.iR(iR),
.iG(iG),
.iB(iB),
.iHSync(iHSync),
.iVSync(iVSync),
.iLineValid(iLineValid),
.iFrameValid(iFrameValid),
.oY(wGray),
.oHSync(wHSync),
.oVSync(wVSync),
.oLineValid(wLineValid),
.oFrameValid(wFrameValid)
);
endmodule
|
// readStreamTest.v
// Testbench for integration of EBABReadStream and EBABWriteMaster
`timescale 1ns/1ns
module butter_test();
reg rst, CLOCK_50;
reg [31:0] counter;
reg audio_input_ready;
// DDS update signal for testing
reg [31:0] dds_accum;
// DDS LUT
reg [31:0] sine_out;
wire [31:0] my_out;
// make reset
initial begin
counter = 32'b0;
CLOCK_50 = 1'b0;
audio_input_ready = 1'b0;
dds_accum = 32'd0;
sine_out = 32'h7fff_ffff;
rst = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
CLOCK_50 = !CLOCK_50;
end
always begin
#1000000
sine_out = ~sine_out;
end
always begin
#20813
audio_input_ready = 1;
#20
audio_input_ready = 0;
end
// update phase accumulator
// sync to audio data rate (48kHz) using audio_input_ready signal
/*always @(posedge CLOCK_50) begin //CLOCK_50
// Fout = (sample_rate)/(2^32)*(constant)
// then Fout=48000/(2^32)*(44739242) = 500 Hz
if (audio_input_ready) dds_accum <= dds_accum + 32'd44739242;
end*/
// DDS sine wave ROM
//sync_rom sineTable(CLOCK_50, dds_accum[31:24], sine_out);
//Filter: cutoff=0.145833
IIR6_32bit_fixed filter(
.audio_out (my_out),
.audio_in (sine_out),
.scale (3'd3),
.b1 (32'h226C),
.b2 (32'hCE8B),
.b3 (32'h2045B),
.b4 (32'h2B07A),
.b5 (32'h2045B),
.b6 (32'hCE8B),
.b7 (32'h226C),
.a2 (32'h21DC9D38),
.a3 (32'hC2BABD8C),
.a4 (32'h3C58991F),
.a5 (32'hDDFDB62D),
.a6 (32'hA5FA11C),
.a7 (32'hFEAA19B2),
.clk(CLOCK_50),
.data_val(audio_input_ready),
.rst(rst),
.audio_out_val(audio_out_val)
); //end filter
endmodule
//////////////////////////////////////////////////
//////////// Sin Wave ROM Table //////////////
//////////////////////////////////////////////////
// produces a 2's comp, 16-bit, approximation
// of a sine wave, given an input phase (address)
module sync_rom (clock, address, sine);
input clock;
input [7:0] address;
output [15:0] sine;
reg signed [15:0] sine;
always@(posedge clock)
begin
case(address)
8'h00: sine = 16'h0000;
8'h01: sine = 16'h0192;
8'h02: sine = 16'h0323;
8'h03: sine = 16'h04b5;
8'h04: sine = 16'h0645;
8'h05: sine = 16'h07d5;
8'h06: sine = 16'h0963;
8'h07: sine = 16'h0af0;
8'h08: sine = 16'h0c7c;
8'h09: sine = 16'h0e05;
8'h0a: sine = 16'h0f8c;
8'h0b: sine = 16'h1111;
8'h0c: sine = 16'h1293;
8'h0d: sine = 16'h1413;
8'h0e: sine = 16'h158f;
8'h0f: sine = 16'h1708;
8'h10: sine = 16'h187d;
8'h11: sine = 16'h19ef;
8'h12: sine = 16'h1b5c;
8'h13: sine = 16'h1cc5;
8'h14: sine = 16'h1e2a;
8'h15: sine = 16'h1f8b;
8'h16: sine = 16'h20e6;
8'h17: sine = 16'h223c;
8'h18: sine = 16'h238d;
8'h19: sine = 16'h24d9;
8'h1a: sine = 16'h261f;
8'h1b: sine = 16'h275f;
8'h1c: sine = 16'h2899;
8'h1d: sine = 16'h29cc;
8'h1e: sine = 16'h2afa;
8'h1f: sine = 16'h2c20;
8'h20: sine = 16'h2d40;
8'h21: sine = 16'h2e59;
8'h22: sine = 16'h2f6b;
8'h23: sine = 16'h3075;
8'h24: sine = 16'h3178;
8'h25: sine = 16'h3273;
8'h26: sine = 16'h3366;
8'h27: sine = 16'h3452;
8'h28: sine = 16'h3535;
8'h29: sine = 16'h3611;
8'h2a: sine = 16'h36e4;
8'h2b: sine = 16'h37ae;
8'h2c: sine = 16'h3870;
8'h2d: sine = 16'h3929;
8'h2e: sine = 16'h39da;
8'h2f: sine = 16'h3a81;
8'h30: sine = 16'h3b1f;
8'h31: sine = 16'h3bb5;
8'h32: sine = 16'h3c41;
8'h33: sine = 16'h3cc4;
8'h34: sine = 16'h3d3d;
8'h35: sine = 16'h3dad;
8'h36: sine = 16'h3e14;
8'h37: sine = 16'h3e70;
8'h38: sine = 16'h3ec4;
8'h39: sine = 16'h3f0d;
8'h3a: sine = 16'h3f4d;
8'h3b: sine = 16'h3f83;
8'h3c: sine = 16'h3fb0;
8'h3d: sine = 16'h3fd2;
8'h3e: sine = 16'h3feb;
8'h3f: sine = 16'h3ffa;
8'h40: sine = 16'h3fff;
8'h41: sine = 16'h3ffa;
8'h42: sine = 16'h3feb;
8'h43: sine = 16'h3fd2;
8'h44: sine = 16'h3fb0;
8'h45: sine = 16'h3f83;
8'h46: sine = 16'h3f4d;
8'h47: sine = 16'h3f0d;
8'h48: sine = 16'h3ec4;
8'h49: sine = 16'h3e70;
8'h4a: sine = 16'h3e14;
8'h4b: sine = 16'h3dad;
8'h4c: sine = 16'h3d3d;
8'h4d: sine = 16'h3cc4;
8'h4e: sine = 16'h3c41;
8'h4f: sine = 16'h3bb5;
8'h50: sine = 16'h3b1f;
8'h51: sine = 16'h3a81;
8'h52: sine = 16'h39da;
8'h53: sine = 16'h3929;
8'h54: sine = 16'h3870;
8'h55: sine = 16'h37ae;
8'h56: sine = 16'h36e4;
8'h57: sine = 16'h3611;
8'h58: sine = 16'h3535;
8'h59: sine = 16'h3452;
8'h5a: sine = 16'h3366;
8'h5b: sine = 16'h3273;
8'h5c: sine = 16'h3178;
8'h5d: sine = 16'h3075;
8'h5e: sine = 16'h2f6b;
8'h5f: sine = 16'h2e59;
8'h60: sine = 16'h2d40;
8'h61: sine = 16'h2c20;
8'h62: sine = 16'h2afa;
8'h63: sine = 16'h29cc;
8'h64: sine = 16'h2899;
8'h65: sine = 16'h275f;
8'h66: sine = 16'h261f;
8'h67: sine = 16'h24d9;
8'h68: sine = 16'h238d;
8'h69: sine = 16'h223c;
8'h6a: sine = 16'h20e6;
8'h6b: sine = 16'h1f8b;
8'h6c: sine = 16'h1e2a;
8'h6d: sine = 16'h1cc5;
8'h6e: sine = 16'h1b5c;
8'h6f: sine = 16'h19ef;
8'h70: sine = 16'h187d;
8'h71: sine = 16'h1708;
8'h72: sine = 16'h158f;
8'h73: sine = 16'h1413;
8'h74: sine = 16'h1293;
8'h75: sine = 16'h1111;
8'h76: sine = 16'h0f8c;
8'h77: sine = 16'h0e05;
8'h78: sine = 16'h0c7c;
8'h79: sine = 16'h0af0;
8'h7a: sine = 16'h0963;
8'h7b: sine = 16'h07d5;
8'h7c: sine = 16'h0645;
8'h7d: sine = 16'h04b5;
8'h7e: sine = 16'h0323;
8'h7f: sine = 16'h0192;
8'h80: sine = 16'h0000;
8'h81: sine = 16'hfe6e;
8'h82: sine = 16'hfcdd;
8'h83: sine = 16'hfb4b;
8'h84: sine = 16'hf9bb;
8'h85: sine = 16'hf82b;
8'h86: sine = 16'hf69d;
8'h87: sine = 16'hf510;
8'h88: sine = 16'hf384;
8'h89: sine = 16'hf1fb;
8'h8a: sine = 16'hf074;
8'h8b: sine = 16'heeef;
8'h8c: sine = 16'hed6d;
8'h8d: sine = 16'hebed;
8'h8e: sine = 16'hea71;
8'h8f: sine = 16'he8f8;
8'h90: sine = 16'he783;
8'h91: sine = 16'he611;
8'h92: sine = 16'he4a4;
8'h93: sine = 16'he33b;
8'h94: sine = 16'he1d6;
8'h95: sine = 16'he075;
8'h96: sine = 16'hdf1a;
8'h97: sine = 16'hddc4;
8'h98: sine = 16'hdc73;
8'h99: sine = 16'hdb27;
8'h9a: sine = 16'hd9e1;
8'h9b: sine = 16'hd8a1;
8'h9c: sine = 16'hd767;
8'h9d: sine = 16'hd634;
8'h9e: sine = 16'hd506;
8'h9f: sine = 16'hd3e0;
8'ha0: sine = 16'hd2c0;
8'ha1: sine = 16'hd1a7;
8'ha2: sine = 16'hd095;
8'ha3: sine = 16'hcf8b;
8'ha4: sine = 16'hce88;
8'ha5: sine = 16'hcd8d;
8'ha6: sine = 16'hcc9a;
8'ha7: sine = 16'hcbae;
8'ha8: sine = 16'hcacb;
8'ha9: sine = 16'hc9ef;
8'haa: sine = 16'hc91c;
8'hab: sine = 16'hc852;
8'hac: sine = 16'hc790;
8'had: sine = 16'hc6d7;
8'hae: sine = 16'hc626;
8'haf: sine = 16'hc57f;
8'hb0: sine = 16'hc4e1;
8'hb1: sine = 16'hc44b;
8'hb2: sine = 16'hc3bf;
8'hb3: sine = 16'hc33c;
8'hb4: sine = 16'hc2c3;
8'hb5: sine = 16'hc253;
8'hb6: sine = 16'hc1ec;
8'hb7: sine = 16'hc190;
8'hb8: sine = 16'hc13c;
8'hb9: sine = 16'hc0f3;
8'hba: sine = 16'hc0b3;
8'hbb: sine = 16'hc07d;
8'hbc: sine = 16'hc050;
8'hbd: sine = 16'hc02e;
8'hbe: sine = 16'hc015;
8'hbf: sine = 16'hc006;
8'hc0: sine = 16'hc001;
8'hc1: sine = 16'hc006;
8'hc2: sine = 16'hc015;
8'hc3: sine = 16'hc02e;
8'hc4: sine = 16'hc050;
8'hc5: sine = 16'hc07d;
8'hc6: sine = 16'hc0b3;
8'hc7: sine = 16'hc0f3;
8'hc8: sine = 16'hc13c;
8'hc9: sine = 16'hc190;
8'hca: sine = 16'hc1ec;
8'hcb: sine = 16'hc253;
8'hcc: sine = 16'hc2c3;
8'hcd: sine = 16'hc33c;
8'hce: sine = 16'hc3bf;
8'hcf: sine = 16'hc44b;
8'hd0: sine = 16'hc4e1;
8'hd1: sine = 16'hc57f;
8'hd2: sine = 16'hc626;
8'hd3: sine = 16'hc6d7;
8'hd4: sine = 16'hc790;
8'hd5: sine = 16'hc852;
8'hd6: sine = 16'hc91c;
8'hd7: sine = 16'hc9ef;
8'hd8: sine = 16'hcacb;
8'hd9: sine = 16'hcbae;
8'hda: sine = 16'hcc9a;
8'hdb: sine = 16'hcd8d;
8'hdc: sine = 16'hce88;
8'hdd: sine = 16'hcf8b;
8'hde: sine = 16'hd095;
8'hdf: sine = 16'hd1a7;
8'he0: sine = 16'hd2c0;
8'he1: sine = 16'hd3e0;
8'he2: sine = 16'hd506;
8'he3: sine = 16'hd634;
8'he4: sine = 16'hd767;
8'he5: sine = 16'hd8a1;
8'he6: sine = 16'hd9e1;
8'he7: sine = 16'hdb27;
8'he8: sine = 16'hdc73;
8'he9: sine = 16'hddc4;
8'hea: sine = 16'hdf1a;
8'heb: sine = 16'he075;
8'hec: sine = 16'he1d6;
8'hed: sine = 16'he33b;
8'hee: sine = 16'he4a4;
8'hef: sine = 16'he611;
8'hf0: sine = 16'he783;
8'hf1: sine = 16'he8f8;
8'hf2: sine = 16'hea71;
8'hf3: sine = 16'hebed;
8'hf4: sine = 16'hed6d;
8'hf5: sine = 16'heeef;
8'hf6: sine = 16'hf074;
8'hf7: sine = 16'hf1fb;
8'hf8: sine = 16'hf384;
8'hf9: sine = 16'hf510;
8'hfa: sine = 16'hf69d;
8'hfb: sine = 16'hf82b;
8'hfc: sine = 16'hf9bb;
8'hfd: sine = 16'hfb4b;
8'hfe: sine = 16'hfcdd;
8'hff: sine = 16'hfe6e;
endcase
end
endmodule
//////////////////////////////////////////////////
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
//Date : Tue Jan 27 10:02:38 2015
//Host : Dtysky running 64-bit major release (build 9200)
//Command : generate_target MIPS_CPU_wrapper.bd
//Design : MIPS_CPU_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module MIPS_CPU_wrapper
(alu_pinout,
clk,
data_pinout,
inst_pinout,
pc_pinout,
restet);
output [31:0]alu_pinout;
input clk;
output [31:0]data_pinout;
output [31:0]inst_pinout;
output [31:0]pc_pinout;
input restet;
wire [31:0]alu_pinout;
wire clk;
wire [31:0]data_pinout;
wire [31:0]inst_pinout;
wire [31:0]pc_pinout;
wire restet;
MIPS_CPU MIPS_CPU_i
(.alu_pinout(alu_pinout),
.clk(clk),
.data_pinout(data_pinout),
.inst_pinout(inst_pinout),
.pc_pinout(pc_pinout),
.restet(restet));
endmodule
|
module nes_hci (
input clk,
input rst,
//Host Interface
input i_reset_sm,
input [7:0] i_opcode,
input i_opcode_strobe,
output reg [15:0] o_opcode_status,
output reg o_opcode_ack,
input [15:0] i_address,
input [31:0] i_count,
//Input data path
input i_data_strobe,
output reg o_hci_ready,
input [7:0] i_data,
//Output data path
output reg o_data_strobe,
input i_host_ready,
output reg [7:0] o_data,
//NES Interface
//CPU Interface
input i_cpu_break,
output reg o_cpu_r_nw, //CPU Read/!Write Pin
output reg [15:0] o_cpu_address,
input [7:0] i_cpu_din,
output reg [7:0] o_cpu_dout,
//CPU Debug Registers
output o_dbg_active,
output reg o_cpu_dbg_reg_wr,
output reg [3:0] o_cpu_dbg_reg_sel,
input [7:0] i_cpu_dbg_reg_din,
output reg [7:0] o_cpu_dbg_reg_dout,
//Picture Processing Unit (PPU)
output reg o_ppu_vram_wr,
output reg [15:0] o_ppu_vram_address,
input [7:0] i_ppu_vram_din,
output reg [7:0] o_ppu_vram_dout,
//Cartridge Config Data
output reg [39:0] o_cart_cfg,
output reg o_cart_cfg_update
);
//localparams
// Debug packet opcodes.
localparam [7:0] OP_NOP = 8'h00; //Tested
localparam [7:0] OP_DBG_BRK = 8'h01; //Tested
localparam [7:0] OP_DBG_RUN = 8'h02; //Tested
localparam [7:0] OP_QUERY_DBG_BRK = 8'h03; //Tested
localparam [7:0] OP_CPU_MEM_RD = 8'h04; //Tested
localparam [7:0] OP_CPU_MEM_WR = 8'h05; //Tested
localparam [7:0] OP_CPU_REG_RD = 8'h06; //Tested
localparam [7:0] OP_CPU_REG_WR = 8'h07; //Tested
localparam [7:0] OP_PPU_MEM_RD = 8'h08; //Tested
localparam [7:0] OP_PPU_MEM_WR = 8'h09; //Tested
localparam [7:0] OP_PPU_DISABLE = 8'h0A; //Tested
localparam [7:0] OP_CART_SET_CFG = 8'h0B; //Tested
// Symbolic state representations.
localparam [4:0] S_DISABLED = 5'h00;
localparam [4:0] S_DECODE = 5'h01;
localparam [4:0] S_CPU_MEM_RD = 5'h02;
localparam [4:0] S_CPU_MEM_WR = 5'h03;
localparam [4:0] S_CPU_REG_RD = 5'h04;
localparam [4:0] S_CPU_REG_WR = 5'h05;
localparam [4:0] S_PPU_MEM_RD = 5'h06;
localparam [4:0] S_PPU_MEM_WR = 5'h07;
localparam [4:0] S_PPU_DISABLE_STG_0 = 5'h08;
localparam [4:0] S_PPU_DISABLE_STG_1 = 5'h09;
localparam [4:0] S_PPU_DISABLE_STG_2 = 5'h0A;
localparam [4:0] S_PPU_DISABLE_STG_3 = 5'h0B;
localparam [4:0] S_PPU_DISABLE_STG_4 = 5'h0C;
localparam [4:0] S_PPU_DISABLE_STG_5 = 5'h0D;
localparam [4:0] S_CART_SET_CFG = 5'h0E;
// Opcode Status
localparam OS_OK = 32'h00000001;
localparam OS_ERROR = 32'h00000002;
localparam OS_UNKNOWN_OPCODE = 32'h00000004;
localparam OS_COUNT_IS_ZERO = 32'h00000008;
//registers/wires
reg [4:0] state;
reg [15:0] r_execute_count;
reg r_host_one_shot;
reg [15:0] r_address;
//submodules
//asynchronous logic
assign o_dbg_active = (state != S_DISABLED);
//synchronous logic
always @ (posedge clk) begin
if (rst || i_reset_sm) begin
state <= S_DECODE;
o_opcode_ack <= 0;
o_opcode_status <= 0;
r_execute_count <= 0;
o_hci_ready <= 0;
o_data_strobe <= 0;
o_data <= 0;
//CPU
o_cpu_address <= 0;
o_cpu_dout <= 0;
o_cpu_r_nw <= 1;
//Debug Interface
o_cpu_dbg_reg_wr <= 0;
o_cpu_dbg_reg_sel <= 0;
o_cpu_dbg_reg_dout<= 0;
//Picture Processing Unit (PPU)
o_ppu_vram_wr <= 0;
o_ppu_vram_dout <= 0;
o_ppu_vram_address<= 0;
//Cartridge
o_cart_cfg <= 0;
o_cart_cfg_update <= 0;
r_host_one_shot <= 0;
r_address <= 0;
end
else begin
//De-assert strobes
o_opcode_ack <= 0;
o_opcode_status <= 0;
o_hci_ready <= 0;
o_cart_cfg_update <= 0;
o_cpu_r_nw <= 1;
o_ppu_vram_wr <= 0;
o_data_strobe <= 0;
o_cpu_dbg_reg_wr <= 0;
case (state)
S_DISABLED: begin
o_hci_ready <= 1;
if (i_cpu_break) begin
//Received CPU initiated break. Begin active Debugging
state <= S_DECODE;
end
else if (i_opcode_strobe) begin
case (i_opcode)
//User Initiated break
OP_DBG_BRK: begin
state <= S_DECODE;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
OP_QUERY_DBG_BRK: begin
o_opcode_status <= OS_ERROR;
o_opcode_ack <= 1;
end
OP_NOP: begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
endcase
end
end
S_DECODE: begin
o_hci_ready <= 1;
r_execute_count <= 0;
r_address <= i_address;
o_cpu_address <= 0;
o_ppu_vram_address <= 0;
o_cpu_dbg_reg_sel <= 4'h0;
o_cpu_dbg_reg_sel <= i_address[3:0];
r_host_one_shot <= 1;
if (i_opcode_strobe) begin
case (i_opcode)
OP_CPU_MEM_RD: begin
o_cpu_address <= i_address;
state <= S_CPU_MEM_RD;
end
OP_CPU_MEM_WR: state <= S_CPU_MEM_WR;
OP_CPU_REG_RD: state <= S_CPU_REG_RD;
OP_CPU_REG_WR: state <= S_CPU_REG_WR;
OP_PPU_MEM_RD: begin
o_ppu_vram_address <= i_address;
state <= S_PPU_MEM_RD;
end
OP_PPU_MEM_WR: state <= S_PPU_MEM_WR;
OP_CART_SET_CFG: state <= S_CART_SET_CFG;
OP_DBG_BRK: state <= S_DECODE;
OP_PPU_DISABLE: state <= S_PPU_DISABLE_STG_0;
OP_DBG_RUN: begin
//Go into normal execution of code
state <= S_DISABLED;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
OP_QUERY_DBG_BRK: begin
//Yes we are in a debug break
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
OP_NOP: begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
end
default:
begin
// Invalid opcode. Ignore, but set error code.
o_opcode_status <= OS_UNKNOWN_OPCODE | OS_ERROR;
o_opcode_ack <= 1;
//Stay in decode
end
endcase
end
end
//CPU Mem Read
//User must populate the count and the address
//When data is available read the data [data] * count bytes
S_CPU_MEM_RD: begin
if (r_execute_count >= i_count) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
if (i_host_ready && r_host_one_shot) begin
o_data <= i_cpu_din;
o_data_strobe <= 1;
r_host_one_shot <= 0;
end
if (o_data_strobe) begin
r_execute_count <= r_execute_count + 32'h00000001;
o_cpu_address <= o_cpu_address + 16'h0001;
end
if (!i_host_ready) begin
r_host_one_shot <= 1;
end
end
//CPU Mem Write
//User must populate count and address before sending opcode
S_CPU_MEM_WR: begin
if (r_execute_count >= i_count) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
else if (i_data_strobe) begin
o_cpu_dout <= i_data;
o_cpu_r_nw <= 0;
o_cpu_address <= r_address;
end
else begin
o_hci_ready <= 1;
end
//When the strobe is high increment the counter and address
if (!o_cpu_r_nw) begin
r_execute_count <= r_execute_count + 32'h00000001;
r_address <= r_address + 16'h0001;
end
end
//CPU Read Register
S_CPU_REG_RD: begin
if (i_host_ready) begin
o_data <= i_cpu_dbg_reg_din;
o_data_strobe <= 1;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
end
//CPU Write Register
//Set up the CPU Address for the debug register
S_CPU_REG_WR: begin
o_hci_ready <= 1;
if (i_data_strobe) begin
o_cpu_dbg_reg_wr <= 1;
o_cpu_dbg_reg_dout <= i_data;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
end
//Picture Processing Unit Memory Read
S_PPU_MEM_RD: begin
if (r_execute_count >= i_count) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
else if (i_host_ready && r_host_one_shot) begin
o_data <= i_ppu_vram_din;
o_data_strobe <= 1;
r_host_one_shot <= 0;
end
if (o_data_strobe) begin
r_execute_count <= r_execute_count + 32'h00000001;
o_ppu_vram_address <= o_ppu_vram_address + 16'h0001;
end
if (!i_host_ready) begin
r_host_one_shot <= 1;
end
end
//Picture Processing Unit Memory Write
S_PPU_MEM_WR: begin
if (r_execute_count >= i_count) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
else if (i_data_strobe) begin
o_ppu_vram_dout <= i_data;
o_ppu_vram_wr <= 1;
o_ppu_vram_address <= r_address;
end
else begin
o_hci_ready <= 1;
end
//When the write stobe goes high increment the address
if (o_ppu_vram_wr) begin
r_execute_count <= r_execute_count + 32'h00000001;
r_address <= r_address + 16'h0001;
end
end
S_PPU_DISABLE_STG_0: begin
o_cpu_address <= 16'h2000;
state <= S_PPU_DISABLE_STG_1;
end
S_PPU_DISABLE_STG_1: begin
// Write 0x2000 to 0.
o_cpu_r_nw <= 1;
o_cpu_dout <= 8'h00;
// Set addr to 0x0000 for one cycle (due to PPU quirk only recognizing register
// interface reads/writes when address bits [15-13] change from 3'b001 from another
// value.
o_cpu_address <= 16'h0000;
state <= S_PPU_DISABLE_STG_2;
end
S_PPU_DISABLE_STG_2: begin
o_cpu_address <= 16'h2001;
state <= S_PPU_DISABLE_STG_3;
end
S_PPU_DISABLE_STG_3: begin
// Write 0x2001 to 0.
o_cpu_r_nw <= 1;
o_cpu_dout <= 8'h00;
// Set addr to 0x0000 for one cycle (due to PPU quirk only recognizing register
// interface reads/writes when address bits [15-13] change from 3'b001 from another
// value.
o_cpu_address <= 16'h0000;
state <= S_PPU_DISABLE_STG_4;
end
S_PPU_DISABLE_STG_4: begin
o_cpu_address <= 16'h2002;
state <= S_PPU_DISABLE_STG_5;
end
S_PPU_DISABLE_STG_5: begin
// Read 0x2002 to reset PPU byte pointer.
o_cpu_address <= 16'h0000;
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
end
S_CART_SET_CFG: begin
if (r_execute_count >= 4) begin
o_opcode_status <= OS_OK;
o_opcode_ack <= 1;
state <= S_DECODE;
o_cart_cfg_update <= 1;
end
else if (i_data_strobe && o_hci_ready) begin
o_hci_ready <= 0;
r_execute_count <= r_execute_count + 32'h00000001;
o_cart_cfg <= {o_cart_cfg[31:0], i_data};
end
else begin
o_hci_ready <= 1;
end
//When the write stobe goes high increment the address
end
default: begin
state <= S_DECODE;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: switch fabric -- crossbar --
-- Description: Estructura de interconexion entre puertos de entrada y
salida. El modulo implementa un crossbar por medio de un
conjunto de multiplexores.
Las señales de control provienen del camino de control,
en especifico de los modulos 'planificador de salida'.
-- Dependencies: -- system.vh
-- Parameters: -- CHANNEL_WIDTH: Ancho de palabra de los canales
de comunicacion entre routers.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 07 de Junio 2015
*/
`include "system.vh"
module switch_fabric
(
input wire clk,
input wire reset,
// -- input -------------------------------------------------- >>>>>
input wire [`CHANNEL_WIDTH-1:0] inport_pe_din,
input wire [`CHANNEL_WIDTH-1:0] inport_xpos_din,
input wire [`CHANNEL_WIDTH-1:0] inport_ypos_din,
input wire [`CHANNEL_WIDTH-1:0] inport_xneg_din,
input wire [`CHANNEL_WIDTH-1:0] inport_yneg_din,
input wire [3:0] conf_pe_din,
input wire [3:0] conf_xpos_din,
input wire [3:0] conf_ypos_din,
input wire [3:0] conf_xneg_din,
input wire [3:0] conf_yneg_din,
// -- output ------------------------------------------------- >>>>>
output reg [`CHANNEL_WIDTH-1:0] outport_pe_dout,
output reg [`CHANNEL_WIDTH-1:0] outport_xpos_dout,
output reg [`CHANNEL_WIDTH-1:0] outport_ypos_dout,
output reg [`CHANNEL_WIDTH-1:0] outport_xneg_dout,
output reg [`CHANNEL_WIDTH-1:0] outport_yneg_dout
);
/*
-- Descripcion: Nucleo de crossbar. Cada puerto de salida esta
resguardado por un multiplexor. Cada multiplexor recibe
las salidas de las colas de almacenamiento de los
puertos de entrada de direcciones opuestas a el.
Ej. El multiplexor resguardando el puerto de salida 'y-'
esta conectado a las colas de almacenamiento {pe, x+,
y+, x-}.
Cada multiplexor tiene a su salida un registro. Este
registro disminuye el retardo de propagacion de
informacion al router vecino. Sin embargo, el registro
agreaga 1 ciclo de latencia en la propagacion de datos.
Para eliminar este registro solo se debe de sustituir:
always @(posedge clk)
outport_pe_dout = output_pe;
con:
assign outport_pe_dout = output_pe;
y cambiar el tipo de señal del puerto de salida en la
declaracion del modulo de 'reg' a 'wire'.
*/
// -- Parametros locales ----------------------------------------- >>>>>
localparam RQS0 = 4'b0001;
localparam RQS1 = 4'b0010;
localparam RQS2 = 4'b0100;
localparam RQS3 = 4'b1000;
// -- MUX :: Salida PE ------------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_pe;
always @(*)
begin
output_pe = {`CHANNEL_WIDTH{1'b0}};
case (conf_pe_din)
RQS0: output_pe = inport_xpos_din;
RQS1: output_pe = inport_ypos_din;
RQS2: output_pe = inport_xneg_din;
RQS3: output_pe = inport_yneg_din;
endcase // conf_pe_din
end
// -- Registro de Puerto de Salida PE ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_pe_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_pe_dout = output_pe;
// -- MUX :: Salida X+ --------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_xpos;
always @(*)
begin
output_xpos = {`CHANNEL_WIDTH{1'b0}};
case (conf_xpos_din)
RQS0: output_xpos = inport_pe_din;
RQS1: output_xpos = inport_ypos_din;
RQS2: output_xpos = inport_xneg_din;
RQS3: output_xpos = inport_yneg_din;
endcase // conf_xpos_din
end
// -- Registro de Puerto de Salida X+ ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_xpos_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_xpos_dout = output_xpos;
// -- MUX :: Salida Y+ --------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_ypos;
always @(*)
begin
output_ypos = {`CHANNEL_WIDTH{1'b0}};
case (conf_ypos_din)
RQS0: output_ypos = inport_pe_din;
RQS1: output_ypos = inport_xpos_din;
RQS2: output_ypos = inport_xneg_din;
RQS3: output_ypos = inport_yneg_din;
endcase // conf_ypos_din
end
// -- Registro de Puerto de Salida Y+ ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_ypos_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_ypos_dout = output_ypos;
// -- MUX :: Salida X- --------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_xneg;
always @(*)
begin
output_xneg = {`CHANNEL_WIDTH{1'b0}};
case (conf_xneg_din)
RQS0: output_xneg = inport_pe_din;
RQS1: output_xneg = inport_xpos_din;
RQS2: output_xneg = inport_ypos_din;
RQS3: output_xneg = inport_yneg_din;
endcase // conf_xneg_din
end
// -- Registro de Puerto de Salida X- ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_xneg_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_xneg_dout = output_xneg;
// -- MUX :: Salida Y- --------------------------------------- >>>>>
reg [`CHANNEL_WIDTH-1:0] output_yneg;
always @(*)
begin
output_yneg = {`CHANNEL_WIDTH{1'b0}};
case (conf_yneg_din)
RQS0: output_yneg = inport_pe_din;
RQS1: output_yneg = inport_xpos_din;
RQS2: output_yneg = inport_ypos_din;
RQS3: output_yneg = inport_xneg_din;
endcase // conf_yneg_din
end
// -- Registro de Puerto de Salida Y- ------------------------ >>>>>
always @(posedge clk)
if (reset)
outport_yneg_dout = {`CHANNEL_WIDTH{1'b0}};
else
outport_yneg_dout = output_yneg;
endmodule
/*-- Plantilla de Instancia -------------------------------------- >>>>>
switch_fabric xbar
(
.clk (clk),
// -- input -------------------------------------------------- >>>>>
.inport_pe_din (inport_pe_din),
.inport_xpos_din (inport_xpos_din),
.inport_ypos_din (inport_ypos_din),
.inport_xneg_din (inport_xneg_din),
.inport_yneg_din (inport_yneg_din),
.conf_pe_din (conf_pe_din),
.conf_xpos_din (conf_xpos_din),
.conf_ypos_din (conf_ypos_din),
.conf_xneg_din (conf_xneg_din),
.conf_yneg_din (conf_yneg_din),
// -- output ------------------------------------------------- >>>>>
.outport_pe_dout (outport_pe_dout),
.outport_xpos_dout (outport_xpos_dout),
.outport_ypos_dout (outport_ypos_dout),
.outport_xneg_dout (outport_xneg_dout),
.outport_yneg_dout (outport_yneg_dout)
);
*/ |
module map_table_tb();
reg clk;
reg rst;
//dispatch
reg [4:0] l_rs;
reg [4:0] l_rt;
reg [4:0] l_rd;
reg [5:0] p_rd_new;
reg RegDest;
reg isDispatch;
//recovery
reg [4:0] recover_rd;
reg [5:0] p_rd_flush;
reg recover;
reg RegDest_ROB;
reg hazard_stall;
reg [5:0] p_rd_compl;
reg complete;
reg RegDest_compl;
wire [5:0] p_rs;
wire [5:0] p_rt;
wire p_rs_v;
wire p_rt_v;
wire [5:0] PR_old_rd;
map_table i_map_table(
.clk(clk),
.rst(rst),
.l_rs(l_rs),
.l_rt(l_rt),
.l_rd(l_rd),
.recover_rd(recover_rd),
.p_rd_new(p_rd_new),
.p_rd_flush(p_rd_flush),
.recover(recover),
.hazard_stall(hazard_stall),
.RegDest(RegDest),
.p_rd_compl(p_rd_compl),
.complete(complete),
.RegDest_ROB(RegDest_ROB),
.RegDest_compl(RegDest_compl),
.p_rs(p_rs),
.p_rt(p_rt),
.p_rs_v(p_rs_v),
.p_rt_v(p_rt_v),
.PR_old_rd(PR_old_rd));
initial begin
clk = 0;
rst = 0;
hazard_stall = 0;
set_dispatch(0, 5'h00, 5'h00, 5'h00, 6'h00, 0);
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h00, 0, 0);
#2 rst = 1;
////////////////////dispatch tests/////////////////////////
@(posedge clk);
set_dispatch(1, 5'h01, 5'h02, 5'h03, 6'h20, 1); //ADD $r3, $r1, $r2 [3] = 20
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h00, 0, 1);
@(posedge clk);
set_dispatch(1, 5'h04, 5'h05, 5'h06, 6'h21, 1); //SUB $r6, $r4, $r5 [6] = 21
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h00, 0, 1);
@(posedge clk);
set_dispatch(1, 5'h07, 5'h08, 5'h00, 6'h22, 0); //B $r7 $r8 there's no rd
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h00, 0, 1);
/////////////////////////complete test//////////////////////////
@(posedge clk);
set_dispatch(1, 5'h03, 5'h02, 5'h07, 6'h22, 1); //ADD $r7, $r3, $r2 ,$r3 should have new map, [7] = 22
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h20, 1, 1);
@(posedge clk);
set_dispatch(1, 5'h01, 5'h02, 5'h07, 6'h23, 1); //SUB $r7, $r1, $r2 WAW with ADD [7] = 23
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h21, 1, 1);
@(posedge clk);
set_dispatch(1, 5'h01, 5'h02, 5'h09, 6'h24, 1); //ADD $r9, $r1, $r2 [9] = 24
set_recovery(5'h00, 6'h00, 0, 0);
set_complete(6'h22, 0, 0); //should not set valid[22]
@(posedge clk);
set_dispatch(1, 5'h09, 5'h0a, 5'h0b, 6'h25, 1); //ADD $r11, $r9, $r10
set_recovery(5'h06, 6'h06, 1, 1); //[6] = 06
set_complete(6'h22, 1, 1);
@(posedge clk);
set_dispatch(1, 5'h00, 5'h00, 5'h00, 6'h23, 0); //NOP
set_recovery(5'h07, 6'h22, 1, 0);
set_complete(6'h22, 1, 0); //during recovery, the CDB will also be stalled, value pair will be kept in EX/CMP
@(posedge clk);
set_dispatch(1, 5'h00, 5'h00, 5'h00, 6'h23, 0); //NOP
set_recovery(5'h09, 6'h24, 0, 0); //will be not written
set_complete(6'h23, 1, 1); //
repeat (3) @(posedge clk);
$stop;
end
always
#5 clk = ~clk;
task set_dispatch(input isDis, input [4:0] Lrs, input [4:0] Lrt, input [4:0] Lrd, input [5:0] PR_new, input regdst);
begin
isDispatch = isDis; l_rs = Lrs; l_rt = Lrt; l_rd = Lrd; p_rd_new = PR_new; RegDest = regdst;
end
endtask
task set_recovery(input [4:0] rec_rd, input [5:0] PR_flush, input rec, input regdst_rob);
begin
recover_rd = rec_rd; p_rd_flush = PR_flush; recover = rec; RegDest_ROB = regdst_rob;
end
endtask
task set_complete(input [5:0] rd_compl, input compl, input regdst_compl);
begin
p_rd_compl = rd_compl; complete = compl; RegDest_compl = regdst_compl;
end
endtask
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_srl_fifo_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
count);
// dump file
$dumpfile("test_axis_srl_fifo_64.lxt");
$dumpvars(0, test_axis_srl_fifo_64);
end
axis_srl_fifo_64 #(
.DEPTH(4),
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Status
.count(count)
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file blk_mem_gen_v7_3.v when simulating
// the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module blk_mem_gen_v7_3(
clka,
ena,
addra,
douta
);
input clka;
input ena;
input [7 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("blk_mem_gen_v7_3.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__EBUFN_BEHAVIORAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_BEHAVIORAL_V |
module s386 (
v4,
v3,
v5,
v1,
v0,
blif_clk_net,
v2,
v6,
blif_reset_net,
v13_D_11,
v13_D_6,
v13_D_10,
v13_D_12,
v13_D_7,
v13_D_8,
v13_D_9);
// Start PIs
input v4;
input v3;
input v5;
input v1;
input v0;
input blif_clk_net;
input v2;
input v6;
input blif_reset_net;
// Start POs
output v13_D_11;
output v13_D_6;
output v13_D_10;
output v13_D_12;
output v13_D_7;
output v13_D_8;
output v13_D_9;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_159;
wire v13_D_7;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire net_117;
wire net_12;
wire net_151;
wire net_74;
wire v13_D_12;
wire net_53;
wire net_93;
wire net_168;
wire net_135;
wire net_130;
wire net_147;
wire net_127;
wire net_14;
wire net_113;
wire net_26;
wire net_76;
wire blif_clk_net;
wire net_101;
wire net_32;
wire net_111;
wire net_90;
wire net_40;
wire net_100;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire net_141;
wire net_160;
wire v1;
wire net_83;
wire net_115;
wire v2;
wire net_4;
wire net_95;
wire net_17;
wire net_78;
wire net_27;
wire net_164;
wire net_56;
wire net_87;
wire v13_D_11;
wire net_0;
wire net_155;
wire net_35;
wire v6;
wire net_16;
wire net_22;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire v3;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire net_120;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_162;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire net_136;
wire net_134;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire net_34;
wire net_108;
wire v13_D_6;
wire net_150;
wire net_63;
wire net_152;
wire net_116;
wire net_30;
wire net_91;
wire net_24;
wire net_55;
wire net_99;
wire net_106;
wire net_46;
wire net_140;
wire net_118;
wire net_148;
wire net_104;
wire net_146;
wire v13_D_8;
wire net_72;
wire net_122;
wire net_25;
wire v0;
wire net_7;
wire net_70;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire v5;
wire net_138;
wire net_13;
wire net_94;
wire net_11;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire net_29;
wire net_68;
wire net_149;
wire net_142;
wire v13_D_10;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_158;
wire v4;
wire net_15;
wire net_41;
wire net_57;
wire net_71;
wire net_153;
wire net_156;
wire net_3;
wire net_84;
wire net_154;
wire net_1;
wire net_92;
wire net_112;
wire net_103;
wire net_139;
wire net_43;
wire net_10;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_79;
wire net_143;
wire net_97;
wire net_88;
wire net_145;
wire net_60;
wire net_81;
wire net_163;
wire net_58;
wire v13_D_9;
wire net_67;
wire net_82;
wire net_64;
wire net_37;
wire net_110;
wire net_121;
wire net_73;
wire net_33;
wire net_48;
wire net_8;
wire net_75;
wire net_86;
wire net_133;
wire net_125;
// Start cells
DFFR_X2 inst_145 ( .QN(net_146), .RN(net_97), .D(net_90), .CK(net_165) );
INV_X4 inst_103 ( .ZN(net_43), .A(v1) );
INV_X4 inst_125 ( .ZN(net_24), .A(net_19) );
INV_X2 inst_138 ( .A(net_133), .ZN(net_132) );
CLKBUF_X2 inst_159 ( .A(net_151), .Z(net_152) );
NOR2_X2 inst_15 ( .A2(net_139), .ZN(net_13), .A1(net_12) );
INV_X4 inst_134 ( .ZN(net_94), .A(net_87) );
NAND4_X2 inst_24 ( .A3(net_74), .ZN(net_64), .A2(net_63), .A4(net_62), .A1(net_2) );
INV_X4 inst_114 ( .A(net_143), .ZN(net_14) );
NOR4_X2 inst_6 ( .A3(net_75), .A4(net_73), .A2(net_40), .A1(net_17), .ZN(v13_D_9) );
INV_X4 inst_131 ( .A(net_46), .ZN(net_32) );
NAND2_X2 inst_76 ( .A2(net_142), .ZN(net_122), .A1(net_51) );
CLKBUF_X2 inst_160 ( .A(net_152), .Z(net_153) );
AND4_X2 inst_150 ( .A3(net_146), .A4(net_129), .ZN(net_44), .A2(net_43), .A1(v4) );
NAND3_X2 inst_33 ( .ZN(net_102), .A2(net_74), .A1(net_68), .A3(net_65) );
CLKBUF_X2 inst_172 ( .A(net_164), .Z(net_165) );
NAND2_X2 inst_83 ( .A1(net_111), .ZN(net_78), .A2(net_31) );
NAND2_X4 inst_47 ( .ZN(net_85), .A2(net_31), .A1(net_24) );
NOR2_X2 inst_19 ( .ZN(net_49), .A1(net_23), .A2(net_14) );
INV_X4 inst_123 ( .ZN(net_25), .A(net_18) );
INV_X4 inst_121 ( .ZN(net_15), .A(net_14) );
OR2_X2 inst_2 ( .A2(net_147), .A1(net_143), .ZN(net_9) );
NOR3_X2 inst_8 ( .ZN(net_119), .A3(net_116), .A2(net_114), .A1(net_49) );
INV_X4 inst_118 ( .ZN(net_77), .A(net_75) );
NAND2_X2 inst_86 ( .ZN(net_110), .A2(net_72), .A1(net_52) );
AND2_X4 inst_153 ( .A2(net_148), .A1(net_147), .ZN(net_6) );
NOR2_X2 inst_20 ( .A1(net_132), .ZN(net_59), .A2(net_41) );
NAND3_X4 inst_27 ( .ZN(net_90), .A2(net_88), .A1(net_82), .A3(net_66) );
NAND3_X2 inst_38 ( .ZN(net_130), .A1(net_67), .A3(net_37), .A2(net_33) );
INV_X4 inst_100 ( .A(net_134), .ZN(net_133) );
NAND2_X4 inst_52 ( .A1(net_112), .ZN(net_106), .A2(net_68) );
NAND2_X2 inst_90 ( .A2(net_121), .A1(net_120), .ZN(net_112) );
INV_X2 inst_140 ( .ZN(net_0), .A(v2) );
NAND3_X2 inst_40 ( .ZN(net_81), .A3(net_48), .A2(net_39), .A1(net_30) );
CLKBUF_X2 inst_162 ( .A(net_154), .Z(net_155) );
CLKBUF_X2 inst_167 ( .A(blif_clk_net), .Z(net_160) );
NAND2_X2 inst_93 ( .A2(net_100), .A1(net_80), .ZN(v13_D_11) );
NAND2_X2 inst_81 ( .ZN(net_72), .A1(net_71), .A2(net_57) );
INV_X4 inst_95 ( .A(net_144), .ZN(net_138) );
OR2_X4 inst_1 ( .ZN(net_28), .A1(net_27), .A2(net_26) );
NAND2_X2 inst_72 ( .ZN(net_55), .A1(net_54), .A2(net_53) );
INV_X2 inst_139 ( .A(net_117), .ZN(net_116) );
AND2_X2 inst_155 ( .ZN(net_124), .A2(net_31), .A1(v1) );
NAND2_X2 inst_59 ( .ZN(net_141), .A1(net_19), .A2(net_7) );
INV_X4 inst_135 ( .ZN(net_95), .A(net_93) );
NAND3_X2 inst_44 ( .A1(net_103), .ZN(net_96), .A3(net_92), .A2(net_91) );
NAND2_X2 inst_55 ( .ZN(net_140), .A1(net_131), .A2(v2) );
CLKBUF_X2 inst_174 ( .A(net_166), .Z(net_167) );
INV_X4 inst_115 ( .A(net_146), .ZN(net_16) );
NAND3_X2 inst_37 ( .A2(net_147), .A1(net_105), .ZN(net_67), .A3(v4) );
DFFR_X2 inst_148 ( .QN(net_147), .RN(net_97), .D(net_95), .CK(net_156) );
CLKBUF_X2 inst_164 ( .A(net_154), .Z(net_157) );
NOR4_X2 inst_5 ( .A2(net_77), .A1(net_76), .A3(net_63), .ZN(v13_D_12), .A4(v0) );
CLKBUF_X2 inst_157 ( .A(net_149), .Z(net_150) );
NAND2_X2 inst_84 ( .A1(net_122), .ZN(net_109), .A2(net_71) );
NAND2_X4 inst_51 ( .A1(net_126), .ZN(net_120), .A2(net_31) );
INV_X2 inst_142 ( .ZN(net_40), .A(net_39) );
NAND2_X2 inst_80 ( .ZN(net_88), .A1(net_74), .A2(net_56) );
CLKBUF_X2 inst_173 ( .A(net_155), .Z(net_166) );
INV_X4 inst_105 ( .A(net_148), .ZN(net_34) );
NAND2_X2 inst_68 ( .ZN(net_121), .A2(net_65), .A1(v1) );
NAND2_X2 inst_78 ( .A1(net_134), .ZN(net_70), .A2(net_42) );
NAND3_X2 inst_42 ( .A1(net_110), .A3(net_92), .A2(net_91), .ZN(net_87) );
CLKBUF_X2 inst_175 ( .A(net_167), .Z(net_168) );
NAND2_X2 inst_53 ( .A2(net_145), .ZN(net_3), .A1(v1) );
INV_X4 inst_133 ( .A(net_85), .ZN(net_56) );
NAND4_X2 inst_26 ( .A4(net_102), .A1(net_101), .ZN(net_89), .A3(net_88), .A2(net_64) );
AND4_X2 inst_151 ( .A1(net_75), .A4(net_62), .A3(net_47), .ZN(v13_D_10), .A2(v1) );
INV_X4 inst_112 ( .ZN(net_75), .A(net_5) );
NAND2_X2 inst_64 ( .A2(net_143), .A1(net_140), .ZN(net_105) );
INV_X4 inst_107 ( .ZN(net_12), .A(v3) );
NAND2_X2 inst_67 ( .ZN(net_45), .A2(net_25), .A1(net_16) );
INV_X4 inst_127 ( .ZN(net_65), .A(net_36) );
NAND2_X2 inst_70 ( .A2(net_129), .ZN(net_48), .A1(net_28) );
INV_X4 inst_129 ( .ZN(net_38), .A(net_24) );
NAND2_X2 inst_92 ( .ZN(net_100), .A2(net_99), .A1(net_77) );
NAND3_X2 inst_29 ( .A2(net_136), .ZN(net_21), .A3(net_6), .A1(net_1) );
NOR2_X2 inst_17 ( .A1(net_147), .ZN(net_54), .A2(net_31) );
NOR2_X4 inst_11 ( .A1(net_131), .ZN(net_129), .A2(v3) );
DFFR_X2 inst_146 ( .QN(net_145), .RN(net_97), .D(net_89), .CK(net_161) );
NOR2_X2 inst_14 ( .A2(net_143), .ZN(net_125), .A1(net_63) );
INV_X4 inst_122 ( .ZN(net_68), .A(net_16) );
NAND3_X2 inst_31 ( .ZN(net_37), .A1(net_13), .A3(net_10), .A2(net_9) );
NAND4_X2 inst_25 ( .A2(net_115), .ZN(net_107), .A1(net_65), .A4(net_31), .A3(v0) );
INV_X4 inst_126 ( .A(net_147), .ZN(net_22) );
CLKBUF_X2 inst_158 ( .A(net_150), .Z(net_151) );
INV_X2 inst_141 ( .A(net_71), .ZN(net_17) );
NAND2_X2 inst_62 ( .A2(net_125), .A1(net_114), .ZN(net_33) );
INV_X4 inst_110 ( .ZN(net_5), .A(net_2) );
NAND2_X2 inst_74 ( .ZN(net_57), .A1(net_35), .A2(net_21) );
NAND2_X2 inst_57 ( .ZN(net_11), .A2(net_3), .A1(v0) );
NAND3_X2 inst_35 ( .A3(net_65), .ZN(net_60), .A2(net_54), .A1(v5) );
INV_X4 inst_99 ( .A(net_135), .ZN(net_134) );
NAND2_X4 inst_48 ( .A1(net_118), .ZN(net_113), .A2(net_85) );
NAND2_X2 inst_69 ( .ZN(net_47), .A1(net_46), .A2(net_4) );
NAND2_X4 inst_46 ( .A2(net_143), .A1(net_139), .ZN(net_36) );
NAND2_X2 inst_82 ( .ZN(net_126), .A2(net_70), .A1(net_43) );
INV_X4 inst_136 ( .ZN(net_98), .A(net_96) );
NAND3_X2 inst_30 ( .A1(net_147), .A2(net_129), .ZN(net_117), .A3(net_26) );
INV_X4 inst_102 ( .ZN(net_63), .A(v5) );
INV_X4 inst_108 ( .A(net_145), .ZN(net_2) );
CLKBUF_X2 inst_165 ( .A(net_157), .Z(net_158) );
NAND3_X2 inst_32 ( .A1(net_147), .ZN(net_142), .A2(net_135), .A3(net_34) );
NOR2_X2 inst_22 ( .A2(net_116), .ZN(net_79), .A1(net_59) );
DFFR_X2 inst_144 ( .QN(net_143), .RN(net_97), .D(net_86), .CK(net_169) );
NAND3_X2 inst_34 ( .A1(net_133), .ZN(net_50), .A3(net_18), .A2(v2) );
NOR2_X4 inst_12 ( .A2(net_146), .ZN(net_115), .A1(net_22) );
NAND2_X2 inst_56 ( .A2(net_143), .ZN(net_10), .A1(v2) );
NAND2_X2 inst_71 ( .ZN(net_76), .A2(net_62), .A1(net_46) );
NOR2_X2 inst_21 ( .ZN(net_73), .A1(net_69), .A2(net_44) );
INV_X4 inst_104 ( .ZN(net_74), .A(v0) );
NAND2_X2 inst_60 ( .A1(net_31), .ZN(net_29), .A2(net_5) );
CLKBUF_X2 inst_169 ( .A(net_155), .Z(net_162) );
CLKBUF_X2 inst_168 ( .A(net_160), .Z(net_161) );
INV_X4 inst_97 ( .A(net_138), .ZN(net_137) );
CLKBUF_X2 inst_161 ( .A(net_153), .Z(net_154) );
INV_X4 inst_124 ( .A(net_68), .ZN(net_46) );
NOR2_X2 inst_18 ( .ZN(net_62), .A2(net_36), .A1(net_8) );
NOR2_X2 inst_16 ( .ZN(net_53), .A1(net_36), .A2(v5) );
NAND2_X2 inst_88 ( .A1(net_130), .ZN(net_108), .A2(net_31) );
OR2_X2 inst_3 ( .ZN(net_52), .A2(net_51), .A1(net_15) );
CLKBUF_X2 inst_156 ( .A(blif_clk_net), .Z(net_149) );
NOR3_X2 inst_9 ( .A1(net_119), .ZN(net_86), .A3(net_85), .A2(net_84) );
INV_X4 inst_113 ( .ZN(net_8), .A(net_6) );
CLKBUF_X2 inst_170 ( .A(net_162), .Z(net_163) );
NAND2_X4 inst_50 ( .A2(net_124), .A1(net_123), .ZN(net_82) );
INV_X2 inst_137 ( .A(net_137), .ZN(net_136) );
NAND3_X2 inst_41 ( .ZN(net_104), .A1(net_78), .A3(net_55), .A2(net_50) );
INV_X4 inst_130 ( .ZN(net_39), .A(net_25) );
NAND2_X2 inst_91 ( .A2(net_107), .A1(net_106), .ZN(net_99) );
INV_X4 inst_132 ( .ZN(net_92), .A(net_38) );
INV_X1 inst_143 ( .ZN(net_97), .A(blif_reset_net) );
CLKBUF_X2 inst_176 ( .A(net_168), .Z(net_169) );
AND3_X1 inst_152 ( .A1(net_92), .A2(net_91), .A3(net_83), .ZN(v13_D_6) );
NAND2_X2 inst_58 ( .A2(net_146), .A1(net_145), .ZN(net_19) );
NAND3_X2 inst_36 ( .ZN(net_66), .A2(net_65), .A1(net_45), .A3(net_11) );
DFFR_X2 inst_147 ( .QN(net_148), .RN(net_97), .D(net_94), .CK(net_151) );
NAND2_X2 inst_87 ( .ZN(net_83), .A2(net_81), .A1(net_60) );
NAND2_X2 inst_61 ( .A1(net_71), .ZN(net_30), .A2(net_0) );
NAND2_X4 inst_45 ( .ZN(net_7), .A1(net_6), .A2(v0) );
INV_X4 inst_96 ( .ZN(net_139), .A(net_138) );
INV_X4 inst_101 ( .A(net_138), .ZN(net_131) );
OR2_X4 inst_0 ( .A1(net_147), .A2(net_143), .ZN(net_41) );
NOR3_X2 inst_10 ( .A1(net_85), .A2(net_84), .A3(net_79), .ZN(v13_D_7) );
NOR4_X2 inst_4 ( .A1(net_76), .A2(net_75), .A3(net_74), .ZN(v13_D_8), .A4(v6) );
NAND2_X2 inst_65 ( .A2(net_114), .ZN(net_35), .A1(net_34) );
NAND2_X2 inst_89 ( .A2(net_109), .A1(net_108), .ZN(net_103) );
NAND3_X2 inst_28 ( .A3(net_147), .A1(net_26), .ZN(net_20), .A2(net_12) );
INV_X4 inst_111 ( .A(net_34), .ZN(net_31) );
NAND2_X2 inst_66 ( .ZN(net_42), .A1(net_41), .A2(net_20) );
INV_X4 inst_117 ( .ZN(net_27), .A(net_14) );
INV_X4 inst_98 ( .A(net_136), .ZN(net_135) );
NAND2_X2 inst_63 ( .A2(net_128), .A1(net_127), .ZN(net_51) );
NOR3_X2 inst_7 ( .A1(net_132), .A2(net_74), .ZN(net_69), .A3(net_68) );
NAND2_X4 inst_49 ( .A1(net_113), .ZN(net_101), .A2(v1) );
INV_X4 inst_120 ( .ZN(net_91), .A(net_84) );
AND2_X2 inst_154 ( .ZN(net_1), .A2(v2), .A1(v3) );
NOR2_X2 inst_13 ( .A1(net_147), .A2(net_138), .ZN(net_114) );
INV_X4 inst_119 ( .ZN(net_71), .A(net_14) );
NAND2_X2 inst_75 ( .ZN(net_58), .A1(net_36), .A2(net_29) );
CLKBUF_X2 inst_166 ( .A(net_158), .Z(net_159) );
INV_X4 inst_116 ( .ZN(net_18), .A(net_8) );
CLKBUF_X2 inst_163 ( .A(net_155), .Z(net_156) );
NAND2_X2 inst_85 ( .ZN(net_123), .A2(net_61), .A1(net_38) );
NAND2_X2 inst_54 ( .ZN(net_84), .A2(net_43), .A1(v0) );
NAND2_X2 inst_79 ( .A1(net_117), .ZN(net_111), .A2(net_27) );
INV_X4 inst_109 ( .ZN(net_128), .A(net_34) );
INV_X4 inst_106 ( .ZN(net_26), .A(v4) );
DFFR_X2 inst_149 ( .QN(net_144), .D(net_98), .RN(net_97), .CK(net_159) );
NAND3_X2 inst_43 ( .A1(net_104), .ZN(net_93), .A3(net_92), .A2(net_91) );
NAND3_X2 inst_39 ( .ZN(net_80), .A2(net_74), .A3(net_58), .A1(net_32) );
INV_X4 inst_128 ( .ZN(net_23), .A(net_22) );
NAND2_X2 inst_73 ( .A1(net_141), .ZN(net_118), .A2(net_65) );
NOR2_X1 inst_23 ( .A2(net_147), .A1(net_137), .ZN(net_127) );
CLKBUF_X2 inst_171 ( .A(net_163), .Z(net_164) );
NAND2_X2 inst_77 ( .A1(net_115), .ZN(net_61), .A2(net_53) );
NAND2_X1 inst_94 ( .ZN(net_4), .A2(v0), .A1(v5) );
endmodule
|
//******************************************************************************
// *
// Copyright (C) 2010 Regents of the University of California. *
// *
// The information contained herein is the exclusive property of the VCL *
// group but may be used and/or modified for non-comercial purposes if the *
// author is acknowledged. For all other uses, permission must be attained *
// by the VLSI Computation Lab. *
// *
// This work has been developed by members of the VLSI Computation Lab *
// (VCL) in the Department of Electrical and Computer Engineering at *
// the University of California at Davis. Contact: [email protected] *
//******************************************************************************
//
// SRAM.v
//
// 16-bit by 128, Static Random Access Memory
//
// $Id: SRAM.v,v 1.0 9/10/2010 02:15:36 astill Exp $
// Written: Aaron Stillmaker
//
// This is a simple memory module created for use with the FIFO.
// This was used instead of a standard cell for simplicity of changing
// the size and simplicity of opperation.
//
// Define FIFO Address width minus 1 and Data word width minus 1
`define ADDR_WIDTH_M1 6
`define DATA_WIDTH_M1 15
`timescale 10ps/1ps
`celldefine
module SRAM (
wr_en, // write enable
clk_wr, // clock coming from write side of FIFO -- write signals
wr_ptr, // write pointer
data_in, // data to be written into the SRAM
rd_en, // read enable
clk_rd, // clock coming from read side of FIFO -- read signals
rd_ptr, // read pointer
data_out // data to be read from the SRAM
);
// I/O %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
input [`DATA_WIDTH_M1:0] data_in;
input clk_wr,
clk_rd,
wr_en,
rd_en;
input [`ADDR_WIDTH_M1:0] wr_ptr,
rd_ptr;
output [`DATA_WIDTH_M1:0] data_out;
// Internal Registers %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
reg [`DATA_WIDTH_M1:0] mem_array [0:128]; // Internal Memory
reg [`DATA_WIDTH_M1:0] data_out; // data output
wire [`DATA_WIDTH_M1:0] data_in; // data in
// Main %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
always @(posedge clk_wr) begin
if (wr_en) mem_array[wr_ptr] <= #1 data_in;
end
always @(posedge clk_rd) begin
if (rd_en) data_out <= #1 mem_array[rd_ptr];
end
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
module fifo
#(
parameter DATA_WIDTH = 8,
parameter FIFO_DEPTH = 12
)
(
input wire reset,
output reg [FIFO_DEPTH:0] count,
output reg full,
// IN PORT
input wire [DATA_WIDTH-1:0] data_in,
input wire data_in_clock,
input wire data_in_enable,
input wire data_in_start,
input wire data_in_end,
output reg [FIFO_DEPTH-1:0] data_in_address,
input wire data_in_reset,
input wire [FIFO_DEPTH-1:0] data_in_reset_address,
// OUT PORT
output reg [DATA_WIDTH-1:0] data_out,
input wire data_out_clock,
input wire data_out_enable,
output reg data_out_start,
output reg data_out_end,
output reg [FIFO_DEPTH-1:0] data_out_address,
input wire data_out_reset,
input wire [FIFO_DEPTH-1:0] data_out_reset_address
);
reg [DATA_WIDTH + 1:0] mem[(2**FIFO_DEPTH) - 1:0]; // 2 bits added to data to facilitate start and stop bits.
always @(posedge data_in_clock)
begin
if ( count && (data_in_address == data_out_address - 1 ))
begin
full <= 1;
end
else
begin
full <= 0;
end
end
always @(posedge data_in_clock)
begin
if( data_in_enable )
begin
if ( data_out_address != data_in_address || (data_out_address == data_in_address && !count))
mem[ data_in_address ]<= { data_in, data_in_start, data_in_end };
end
end
always @(posedge data_in_clock or posedge reset)
begin
if( reset )
begin
data_in_address <= 0;
count <= 0;
end
else if (data_in_reset)
begin
count = count - (data_in_address - data_in_reset_address);
data_in_address = data_in_reset_address;
end
else
begin
if( data_in_enable )
begin
count <= count + 1;
data_in_address <= data_in_address + 1;
end
end
end
always @(posedge data_out_clock or posedge reset)
begin
if (reset)
begin
data_out <= 0;
data_out_address <= 0;
end
else if (data_out_reset)
begin
data_out_address <= data_out_reset_address;
end
else if (data_out_enable)
begin
{ data_out, data_out_start, data_out_end } <= mem[data_out_address];
data_out_address <= data_out_address + 1;
count <= count - 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_16_V
`define SKY130_FD_SC_HVL__INV_16_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_16_V
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream GMII frame transmitter (AXI in, GMII out)
*/
module axis_gmii_tx #
(
parameter DATA_WIDTH = 8,
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* GMII output
*/
output wire [DATA_WIDTH-1:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Control
*/
input wire clk_enable,
input wire mii_select,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
/*
* Status
*/
output wire start_packet,
output wire error_underflow
);
// bus width assertions
initial begin
if (DATA_WIDTH != 8) begin
$error("Error: Interface width must be 8");
$finish;
end
end
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PREAMBLE = 3'd1,
STATE_PAYLOAD = 3'd2,
STATE_LAST = 3'd3,
STATE_PAD = 3'd4,
STATE_FCS = 3'd5,
STATE_WAIT_END = 3'd6,
STATE_IFG = 3'd7;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg [7:0] s_tdata_reg = 8'd0, s_tdata_next;
reg mii_odd_reg = 1'b0, mii_odd_next;
reg [3:0] mii_msn_reg = 4'b0, mii_msn_next;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
reg [7:0] gmii_txd_reg = 8'd0, gmii_txd_next;
reg gmii_tx_en_reg = 1'b0, gmii_tx_en_next;
reg gmii_tx_er_reg = 1'b0, gmii_tx_er_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next;
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next;
reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
reg start_packet_reg = 1'b0, start_packet_next;
reg error_underflow_reg = 1'b0, error_underflow_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next;
assign s_axis_tready = s_axis_tready_reg;
assign gmii_txd = gmii_txd_reg;
assign gmii_tx_en = gmii_tx_en_reg;
assign gmii_tx_er = gmii_tx_er_reg;
assign m_axis_ptp_ts = PTP_TS_ENABLE ? m_axis_ptp_ts_reg : 0;
assign m_axis_ptp_ts_tag = PTP_TAG_ENABLE ? m_axis_ptp_ts_tag_reg : 0;
assign m_axis_ptp_ts_valid = PTP_TS_ENABLE || PTP_TAG_ENABLE ? m_axis_ptp_ts_valid_reg : 1'b0;
assign start_packet = start_packet_reg;
assign error_underflow = error_underflow_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(s_tdata_reg),
.state_in(crc_state),
.data_out(),
.state_out(crc_next)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
mii_odd_next = mii_odd_reg;
mii_msn_next = mii_msn_reg;
frame_ptr_next = frame_ptr_reg;
s_axis_tready_next = 1'b0;
s_tdata_next = s_tdata_reg;
m_axis_ptp_ts_next = m_axis_ptp_ts_reg;
m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg;
m_axis_ptp_ts_valid_next = 1'b0;
gmii_txd_next = {DATA_WIDTH{1'b0}};
gmii_tx_en_next = 1'b0;
gmii_tx_er_next = 1'b0;
start_packet_next = 1'b0;
error_underflow_next = 1'b0;
if (!clk_enable) begin
// clock disabled - hold state and outputs
gmii_txd_next = gmii_txd_reg;
gmii_tx_en_next = gmii_tx_en_reg;
gmii_tx_er_next = gmii_tx_er_reg;
state_next = state_reg;
end else if (mii_select && mii_odd_reg) begin
// MII odd cycle - hold state, output MSN
mii_odd_next = 1'b0;
gmii_txd_next = {4'd0, mii_msn_reg};
gmii_tx_en_next = gmii_tx_en_reg;
gmii_tx_er_next = gmii_tx_er_reg;
state_next = state_reg;
end else begin
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
mii_odd_next = 1'b0;
if (s_axis_tvalid) begin
mii_odd_next = 1'b1;
frame_ptr_next = 16'd1;
gmii_txd_next = ETH_PRE;
gmii_tx_en_next = 1'b1;
state_next = STATE_PREAMBLE;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PREAMBLE: begin
// send preamble
reset_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
gmii_txd_next = ETH_PRE;
gmii_tx_en_next = 1'b1;
if (frame_ptr_reg == 16'd6) begin
s_axis_tready_next = 1'b1;
s_tdata_next = s_axis_tdata;
state_next = STATE_PREAMBLE;
end else if (frame_ptr_reg == 16'd7) begin
// end of preamble; start payload
frame_ptr_next = 16'd0;
if (s_axis_tready_reg) begin
s_axis_tready_next = 1'b1;
s_tdata_next = s_axis_tdata;
end
gmii_txd_next = ETH_SFD;
m_axis_ptp_ts_next = ptp_ts;
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_next = 1'b1;
start_packet_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_PREAMBLE;
end
end
STATE_PAYLOAD: begin
// send payload
update_crc = 1'b1;
s_axis_tready_next = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
gmii_txd_next = s_tdata_reg;
gmii_tx_en_next = 1'b1;
s_tdata_next = s_axis_tdata;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
s_axis_tready_next = !s_axis_tready_reg;
if (s_axis_tuser[0]) begin
gmii_tx_er_next = 1'b1;
frame_ptr_next = 1'b0;
state_next = STATE_IFG;
end else begin
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
// tvalid deassert, fail frame
gmii_tx_er_next = 1'b1;
frame_ptr_next = 16'd0;
error_underflow_next = 1'b1;
state_next = STATE_WAIT_END;
end
end
STATE_LAST: begin
// last payload word
update_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
gmii_txd_next = s_tdata_reg;
gmii_tx_en_next = 1'b1;
if (ENABLE_PADDING && frame_ptr_reg < MIN_FRAME_LENGTH-5) begin
s_tdata_next = 8'd0;
state_next = STATE_PAD;
end else begin
frame_ptr_next = 16'd0;
state_next = STATE_FCS;
end
end
STATE_PAD: begin
// send padding
update_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
gmii_txd_next = 8'd0;
gmii_tx_en_next = 1'b1;
s_tdata_next = 8'd0;
if (frame_ptr_reg < MIN_FRAME_LENGTH-5) begin
state_next = STATE_PAD;
end else begin
frame_ptr_next = 16'd0;
state_next = STATE_FCS;
end
end
STATE_FCS: begin
// send FCS
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
case (frame_ptr_reg)
2'd0: gmii_txd_next = ~crc_state[7:0];
2'd1: gmii_txd_next = ~crc_state[15:8];
2'd2: gmii_txd_next = ~crc_state[23:16];
2'd3: gmii_txd_next = ~crc_state[31:24];
endcase
gmii_tx_en_next = 1'b1;
if (frame_ptr_reg < 3) begin
state_next = STATE_FCS;
end else begin
frame_ptr_next = 16'd0;
state_next = STATE_IFG;
end
end
STATE_WAIT_END: begin
// wait for end of frame
reset_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
s_axis_tready_next = 1'b1;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
s_axis_tready_next = 1'b0;
if (frame_ptr_reg < ifg_delay-1) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_WAIT_END;
end
end else begin
state_next = STATE_WAIT_END;
end
end
STATE_IFG: begin
// send IFG
reset_crc = 1'b1;
mii_odd_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd1;
if (frame_ptr_reg < ifg_delay-1) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
end
end
endcase
if (mii_select) begin
mii_msn_next = gmii_txd_next[7:4];
gmii_txd_next[7:4] = 4'd0;
end
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
s_axis_tready_reg <= 1'b0;
m_axis_ptp_ts_valid_reg <= 1'b0;
gmii_tx_en_reg <= 1'b0;
gmii_tx_er_reg <= 1'b0;
start_packet_reg <= 1'b0;
error_underflow_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
s_axis_tready_reg <= s_axis_tready_next;
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next;
gmii_tx_en_reg <= gmii_tx_en_next;
gmii_tx_er_reg <= gmii_tx_er_next;
start_packet_reg <= start_packet_next;
error_underflow_reg <= error_underflow_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next;
end
end
m_axis_ptp_ts_reg <= m_axis_ptp_ts_next;
m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next;
mii_odd_reg <= mii_odd_next;
mii_msn_reg <= mii_msn_next;
s_tdata_reg <= s_tdata_next;
gmii_txd_reg <= gmii_txd_next;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22A_SYMBOL_V
`define SKY130_FD_SC_HS__O22A_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o22a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22A_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:08:25 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952,
DP_OP_15J11_123_2691_n8, DP_OP_15J11_123_2691_n7,
DP_OP_15J11_123_2691_n6, DP_OP_15J11_123_2691_n5,
DP_OP_15J11_123_2691_n4, intadd_5_B_9_, intadd_5_B_8_, intadd_5_B_7_,
intadd_5_B_6_, intadd_5_B_5_, intadd_5_B_4_, intadd_5_B_3_,
intadd_5_B_2_, intadd_5_B_1_, intadd_5_B_0_, intadd_5_CI,
intadd_5_SUM_9_, intadd_5_SUM_8_, intadd_5_SUM_7_, intadd_5_SUM_6_,
intadd_5_SUM_5_, intadd_5_SUM_4_, intadd_5_SUM_3_, intadd_5_SUM_2_,
intadd_5_SUM_1_, intadd_5_SUM_0_, intadd_5_n10, intadd_5_n9,
intadd_5_n8, intadd_5_n7, intadd_5_n6, intadd_5_n5, intadd_5_n4,
intadd_5_n3, intadd_5_n2, intadd_5_n1, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1379, n1380, n1381, n1382, n1383,
n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393,
n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403,
n1404, n1405, n1406, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1541, n1542, n1543, n1544, n1545, n1546,
n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556,
n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566,
n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576,
n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606,
n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616,
n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626,
n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636,
n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646,
n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656,
n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676,
n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686,
n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696,
n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706,
n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716,
n1717, n1718, n1719, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1750, n1751, n1752;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:1] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:1] Raw_mant_NRM_SWR;
wire [23:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n947), .CK(clk), .RN(n1721), .QN(
n970) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n941), .CK(clk), .RN(n1730),
.QN(n963) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n933), .CK(clk), .RN(n1723),
.QN(n964) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n911), .CK(clk), .RN(n1722), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n910), .CK(clk), .RN(n1721), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1727),
.Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n873), .CK(clk), .RN(n1728), .QN(
n958) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n869), .CK(clk), .RN(n1725), .QN(
n967) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n855), .CK(clk), .RN(n1745), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n854), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n846), .CK(clk), .RN(n1729),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n845), .CK(clk), .RN(n1728),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n844), .CK(clk), .RN(n1725),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n843), .CK(clk), .RN(n1729),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n1743), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n841), .CK(clk), .RN(n1747), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n840), .CK(clk), .RN(n1747), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n839), .CK(clk), .RN(n1747), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n838), .CK(clk), .RN(n1747), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n837), .CK(clk), .RN(n1747), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n836), .CK(clk), .RN(n1747), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n835), .CK(clk), .RN(n1747), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n834), .CK(clk), .RN(n1744), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n833), .CK(clk), .RN(n1726), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n832), .CK(clk), .RN(n1726), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n831), .CK(clk), .RN(n1728), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n830), .CK(clk), .RN(n1725), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n829), .CK(clk), .RN(n1745), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n828), .CK(clk), .RN(n1732), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n827), .CK(clk), .RN(n1726), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n826), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n825), .CK(clk), .RN(n1730), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n824), .CK(clk), .RN(n1723), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n823), .CK(clk), .RN(n1724), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n822), .CK(clk), .RN(n1722), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n821), .CK(clk), .RN(n1721), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n820), .CK(clk), .RN(n1727), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n819), .CK(clk), .RN(n1730), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n818), .CK(clk), .RN(n1723), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n817), .CK(clk), .RN(n1734), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n816), .CK(clk), .RN(n1721), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n815), .CK(clk), .RN(n1724), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n814), .CK(clk), .RN(n1727), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n813), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n812), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n807), .CK(clk), .RN(n1731), .QN(n971)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n806), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n805), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n804), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n803), .CK(clk), .RN(n1731), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n802), .CK(clk), .RN(n1731), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n801), .CK(clk), .RN(n1722), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n800), .CK(clk), .RN(n1722), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n799), .CK(clk), .RN(n1723), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n797), .CK(clk), .RN(n956), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n796), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n794), .CK(clk), .RN(n956), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n793), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n791), .CK(clk), .RN(n956), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n790), .CK(clk), .RN(n1005), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n788), .CK(clk), .RN(n956), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n787), .CK(clk), .RN(n1732), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n785), .CK(clk), .RN(n1732), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n784), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n782), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n781), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n779), .CK(clk), .RN(n1736), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1005), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n776), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n775), .CK(clk), .RN(n1733), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n773), .CK(clk), .RN(n1005), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n772), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n770), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n769), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n767), .CK(clk), .RN(n1005), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n766), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n764), .CK(clk), .RN(n1722), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n763), .CK(clk), .RN(n1734), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n761), .CK(clk), .RN(n1722), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n760), .CK(clk), .RN(n1734), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n759), .CK(clk), .RN(n1722), .Q(
DMP_SFG[13]), .QN(n1668) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n758), .CK(clk), .RN(n1734), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n757), .CK(clk), .RN(n1722), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n756), .CK(clk), .RN(n1734), .Q(
DMP_SFG[14]), .QN(n1671) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n755), .CK(clk), .RN(n1734), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n754), .CK(clk), .RN(n1722), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n753), .CK(clk), .RN(n1746), .Q(
DMP_SFG[15]), .QN(n1690) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n752), .CK(clk), .RN(n1735), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n751), .CK(clk), .RN(n1746), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n750), .CK(clk), .RN(n1735), .Q(
DMP_SFG[16]), .QN(n1689) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n749), .CK(clk), .RN(n1746), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n748), .CK(clk), .RN(n1735), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n747), .CK(clk), .RN(n1746), .Q(
DMP_SFG[17]), .QN(n1703) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n746), .CK(clk), .RN(n1735), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n745), .CK(clk), .RN(n1746), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n744), .CK(clk), .RN(n1735), .Q(
DMP_SFG[18]), .QN(n1702) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n743), .CK(clk), .RN(n1746), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n742), .CK(clk), .RN(n1735), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n741), .CK(clk), .RN(n1005), .Q(
DMP_SFG[19]), .QN(n1709) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n740), .CK(clk), .RN(n1736), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n739), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n738), .CK(clk), .RN(n1733), .Q(
DMP_SFG[20]), .QN(n1708) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n737), .CK(clk), .RN(n1732), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n736), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n735), .CK(clk), .RN(n956), .Q(
DMP_SFG[21]), .QN(n1718) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n734), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n733), .CK(clk), .RN(n1733), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n732), .CK(clk), .RN(n1736), .Q(
DMP_SFG[22]), .QN(n1717) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n731), .CK(clk), .RN(n1005), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1732), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n729), .CK(clk), .RN(n956), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n728), .CK(clk), .RN(n1743), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n726), .CK(clk), .RN(n1733), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n725), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n724), .CK(clk), .RN(n1005), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n723), .CK(clk), .RN(n1736), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n721), .CK(clk), .RN(n1736), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n720), .CK(clk), .RN(n1732), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n1743), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n718), .CK(clk), .RN(n1736), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n716), .CK(clk), .RN(n1732), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n715), .CK(clk), .RN(n956), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n714), .CK(clk), .RN(n1738), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n713), .CK(clk), .RN(n1738), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n711), .CK(clk), .RN(n1738), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n710), .CK(clk), .RN(n1738), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n1738), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n708), .CK(clk), .RN(n1738), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n706), .CK(clk), .RN(n1738), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n705), .CK(clk), .RN(n1738), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n704), .CK(clk), .RN(n1738), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1738), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n701), .CK(clk), .RN(n1738), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n700), .CK(clk), .RN(n1738), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n699), .CK(clk), .RN(n1739), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n698), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n696), .CK(clk), .RN(n1739), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n695), .CK(clk), .RN(n1739), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n694), .CK(clk), .RN(n1739), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n693), .CK(clk), .RN(n1739), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n691), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n690), .CK(clk), .RN(n1739), .QN(
n972) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n687), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n685), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n683), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n682), .CK(clk), .RN(n1740), .QN(
n975) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n681), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n680), .CK(clk), .RN(n1740), .QN(
n973) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n679), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n677), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n675), .CK(clk), .RN(n1740), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n673), .CK(clk), .RN(n1739), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n672), .CK(clk), .RN(n1743), .QN(
n959) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n671), .CK(clk), .RN(n1731), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n669), .CK(clk), .RN(n1736), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n668), .CK(clk), .RN(n1740),
.QN(n974) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n667), .CK(clk), .RN(n1733), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n665), .CK(clk), .RN(n1736), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n664), .CK(clk), .RN(n1729),
.QN(n960) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n663), .CK(clk), .RN(n1727), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n661), .CK(clk), .RN(n1745), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n660), .CK(clk), .RN(n1738),
.QN(n968) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n659), .CK(clk), .RN(n1745), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n657), .CK(clk), .RN(n1744), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n655), .CK(clk), .RN(n1729), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n653), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n652), .CK(clk), .RN(n1739),
.QN(n969) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n651), .CK(clk), .RN(n1731), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n649), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n647), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n645), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n640), .CK(clk), .RN(n1741), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n639), .CK(clk), .RN(n1747), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n638), .CK(clk), .RN(n1741), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n637), .CK(clk), .RN(n1741), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n636), .CK(clk), .RN(n1742), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n635), .CK(clk), .RN(n1742), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n634), .CK(clk), .RN(n1742), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n633), .CK(clk), .RN(n1742), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n632), .CK(clk), .RN(n1742), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n631), .CK(clk), .RN(n1742), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n629), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n628), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n626), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n625), .CK(clk), .RN(n1742), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n624), .CK(clk), .RN(n1747), .Q(
final_result_ieee[31]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n612), .CK(clk), .RN(n1733), .Q(
DmP_mant_SFG_SWR[14]), .QN(n996) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n610), .CK(clk), .RN(n1736), .Q(
LZD_output_NRM2_EW[4]), .QN(n1672) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n609), .CK(clk), .RN(n1729), .Q(
DmP_mant_SFG_SWR[1]), .QN(n997) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n607), .CK(clk), .RN(n1732), .Q(
LZD_output_NRM2_EW[2]), .QN(n1669) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n604), .CK(clk), .RN(n1736), .Q(
LZD_output_NRM2_EW[1]), .QN(n1663) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[0]), .QN(n999) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n1721), .QN(
n965) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n598), .CK(clk), .RN(n1733), .Q(
LZD_output_NRM2_EW[3]), .QN(n1673) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n595), .CK(clk), .RN(n1730), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1743), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n592), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1001) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n590), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1000) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n588), .CK(clk), .RN(n1745), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n586), .CK(clk), .RN(n1743), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n583), .CK(clk), .RN(n1735), .Q(
final_result_ieee[10]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n580), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n578), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n577), .CK(clk), .RN(n1744), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n576), .CK(clk), .RN(n1744), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n574), .CK(clk), .RN(n1744), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n573), .CK(clk), .RN(n1744), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n572), .CK(clk), .RN(n1744), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n571), .CK(clk), .RN(n1744), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n570), .CK(clk), .RN(n1745), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n569), .CK(clk), .RN(n1729), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n568), .CK(clk), .RN(n1745), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n567), .CK(clk), .RN(n1729), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n566), .CK(clk), .RN(n1745), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n565), .CK(clk), .RN(n1729), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n564), .CK(clk), .RN(n1745), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n563), .CK(clk), .RN(n1729), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n1745), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n561), .CK(clk), .RN(n1729), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n560), .CK(clk), .RN(n1745), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n559), .CK(clk), .RN(n1729), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n558), .CK(clk), .RN(n1746), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n557), .CK(clk), .RN(n1735), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n556), .CK(clk), .RN(n1746), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n555), .CK(clk), .RN(n1735), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n554), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n553), .CK(clk), .RN(n1735), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n552), .CK(clk), .RN(n1735), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n551), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n550), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n549), .CK(clk), .RN(n1735), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n548), .CK(clk), .RN(n1735), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n545), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[24]), .QN(n993) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n544), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[25]), .QN(n994) );
CMPR32X2TS intadd_5_U11 ( .A(n1668), .B(intadd_5_B_0_), .C(intadd_5_CI),
.CO(intadd_5_n10), .S(intadd_5_SUM_0_) );
CMPR32X2TS intadd_5_U10 ( .A(n1671), .B(intadd_5_B_1_), .C(intadd_5_n10),
.CO(intadd_5_n9), .S(intadd_5_SUM_1_) );
CMPR32X2TS intadd_5_U9 ( .A(n1690), .B(intadd_5_B_2_), .C(intadd_5_n9), .CO(
intadd_5_n8), .S(intadd_5_SUM_2_) );
CMPR32X2TS intadd_5_U8 ( .A(n1689), .B(intadd_5_B_3_), .C(intadd_5_n8), .CO(
intadd_5_n7), .S(intadd_5_SUM_3_) );
CMPR32X2TS intadd_5_U7 ( .A(n1703), .B(intadd_5_B_4_), .C(intadd_5_n7), .CO(
intadd_5_n6), .S(intadd_5_SUM_4_) );
CMPR32X2TS intadd_5_U6 ( .A(n1702), .B(intadd_5_B_5_), .C(intadd_5_n6), .CO(
intadd_5_n5), .S(intadd_5_SUM_5_) );
CMPR32X2TS intadd_5_U5 ( .A(n1709), .B(intadd_5_B_6_), .C(intadd_5_n5), .CO(
intadd_5_n4), .S(intadd_5_SUM_6_) );
CMPR32X2TS intadd_5_U4 ( .A(n1708), .B(intadd_5_B_7_), .C(intadd_5_n4), .CO(
intadd_5_n3), .S(intadd_5_SUM_7_) );
CMPR32X2TS intadd_5_U3 ( .A(n1718), .B(intadd_5_B_8_), .C(intadd_5_n3), .CO(
intadd_5_n2), .S(intadd_5_SUM_8_) );
CMPR32X2TS intadd_5_U2 ( .A(n1717), .B(intadd_5_B_9_), .C(intadd_5_n2), .CO(
intadd_5_n1), .S(intadd_5_SUM_9_) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n872), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[19]), .QN(n1715) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n643), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[25]), .QN(n1714) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n808), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[26]), .QN(n1713) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n919), .CK(clk), .RN(n1734),
.Q(intDX_EWSW[24]), .QN(n1712) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n864), .CK(clk), .RN(n1728), .Q(
Data_array_SWR[12]), .QN(n1711) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n642), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[26]), .QN(n1710) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n692), .CK(clk), .RN(n1747), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1707) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n809), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[25]), .QN(n1706) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n863), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[11]), .QN(n1705) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n862), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[10]), .QN(n1704) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n871), .CK(clk), .RN(n1729), .Q(
Data_array_SWR[18]), .QN(n1701) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n599), .CK(clk), .RN(n1005), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1700) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n891), .CK(clk), .RN(n1726),
.Q(intDY_EWSW[18]), .QN(n1699) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n915), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[28]), .QN(n1698) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n870), .CK(clk), .RN(n1730), .Q(
Data_array_SWR[17]), .QN(n1697) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n901), .CK(clk), .RN(n1726), .Q(
intDY_EWSW[8]), .QN(n1696) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n908), .CK(clk), .RN(n1721), .Q(
intDY_EWSW[1]), .QN(n1695) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n892), .CK(clk), .RN(n1744),
.Q(intDY_EWSW[17]), .QN(n1694) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n909), .CK(clk), .RN(n1722), .Q(
intDY_EWSW[0]), .QN(n1693) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n884), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[25]), .QN(n1692) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n883), .CK(clk), .RN(n1725),
.Q(intDY_EWSW[26]), .QN(n1691) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1732), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1688) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n697), .CK(clk), .RN(n1746), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1687) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n886), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[23]), .QN(n1686) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n914), .CK(clk), .RN(n1721),
.Q(intDX_EWSW[29]), .QN(n1685) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n902), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[7]), .QN(n1684) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n882), .CK(clk), .RN(n1723),
.Q(intDY_EWSW[27]), .QN(n1683) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n895), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[14]), .QN(n1681) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n897), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[12]), .QN(n1680) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n905), .CK(clk), .RN(n1745), .Q(
intDY_EWSW[4]), .QN(n1679) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n907), .CK(clk), .RN(n1730), .Q(
intDY_EWSW[2]), .QN(n1678) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n896), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[13]), .QN(n1676) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n900), .CK(clk), .RN(n1738), .Q(
intDY_EWSW[9]), .QN(n1675) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n903), .CK(clk), .RN(n1726), .Q(
intDY_EWSW[6]), .QN(n1674) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n951), .CK(clk), .RN(
n1724), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1670) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n879), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[30]), .QN(n1667) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n927), .CK(clk), .RN(n1723),
.Q(intDX_EWSW[16]), .QN(n1665) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n587), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1664) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n727), .CK(clk), .RN(n1006), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1662) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n937), .CK(clk), .RN(n1730), .Q(
intDX_EWSW[6]), .QN(n1660) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n594), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1659) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n938), .CK(clk), .RN(n1724), .Q(
intDX_EWSW[5]), .QN(n1658) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n600), .CK(clk), .RN(n1740), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1657) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n585), .CK(clk), .RN(n1723), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1656) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n848), .CK(clk), .RN(n1721), .Q(
shift_value_SHT2_EWR[4]), .QN(n1655) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n589), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1654) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n579), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1653) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n949), .CK(clk), .RN(n1730), .Q(
n1632), .QN(n1716) );
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(n948), .CK(clk), .RN(n1721), .QN(
n1719) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n917), .CK(clk), .RN(n1724),
.Q(intDX_EWSW[26]), .QN(n1652) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n918), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[25]), .QN(n1651) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n867), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[15]), .QN(n1650) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n866), .CK(clk), .RN(n1745), .Q(
Data_array_SWR[14]), .QN(n1649) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n810), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[24]), .QN(n1648) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[24]), .QN(n1647) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n875), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[21]), .QN(n1646) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n890), .CK(clk), .RN(n1726),
.Q(intDY_EWSW[19]), .QN(n1645) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n913), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[30]), .QN(n1644) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n887), .CK(clk), .RN(n1726),
.Q(intDY_EWSW[22]), .QN(n1643) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n893), .CK(clk), .RN(n1725),
.Q(intDY_EWSW[16]), .QN(n1642) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n904), .CK(clk), .RN(n1725), .Q(
intDY_EWSW[5]), .QN(n1641) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1723), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1640) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n880), .CK(clk), .RN(n1734),
.Q(intDY_EWSW[29]), .QN(n1638) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n936), .CK(clk), .RN(n1723), .Q(
intDX_EWSW[7]), .QN(n1637) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n939), .CK(clk), .RN(n1734), .Q(
intDX_EWSW[4]), .QN(n1636) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n596), .CK(clk), .RN(n1733), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1635) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1634) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n611), .CK(clk), .RN(n1736), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1633) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n622), .CK(clk), .RN(n1735), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1631) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n874), .CK(clk), .RN(n1727), .Q(
Data_array_SWR[20]), .QN(n1630) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n885), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[24]), .QN(n1629) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n621), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1628) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n617), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1627) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n630), .CK(clk), .RN(n1745), .Q(n1002), .QN(n1639) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n613), .CK(clk), .RN(n1743), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1626) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n616), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1625) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n920), .CK(clk), .RN(n1724),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n930), .CK(clk), .RN(n1721),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n940), .CK(clk), .RN(n1727), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n928), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n922), .CK(clk), .RN(n1721),
.Q(intDX_EWSW[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n876), .CK(clk), .RN(n1722), .Q(
Data_array_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n1006), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n926), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n877), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n932), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n934), .CK(clk), .RN(n1730), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n935), .CK(clk), .RN(n1723), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n916), .CK(clk), .RN(n1722),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n865), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n943), .CK(clk), .RN(n1727), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n925), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n581), .CK(clk), .RN(n1744), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n605), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n623), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1741), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n591), .CK(clk), .RN(n1733), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n952), .CK(clk), .RN(
n1724), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n860), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n868), .CK(clk), .RN(n1726), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n620), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n856), .CK(clk), .RN(n1729), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1728), .Q(
Data_array_SWR[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n956), .Q(
Raw_mant_NRM_SWR[23]), .QN(n961) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n858), .CK(clk), .RN(n1725), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n859), .CK(clk), .RN(n1746), .Q(
Data_array_SWR[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n792), .CK(clk), .RN(n1005), .Q(
DMP_SFG[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n762), .CK(clk), .RN(n1734), .Q(
DMP_SFG[12]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n912), .CK(clk), .RN(n1723),
.Q(intDX_EWSW[31]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n850), .CK(clk), .RN(n1730), .Q(
shift_value_SHT2_EWR[3]), .QN(n1666) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n774), .CK(clk), .RN(n1006), .Q(
DMP_SFG[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n795), .CK(clk), .RN(n956), .Q(
DMP_SFG[1]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n614), .CK(clk), .RN(n1005), .Q(
Raw_mant_NRM_SWR[24]), .QN(n995) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n646), .CK(clk), .RN(n1741), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n658), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n656), .CK(clk), .RN(n1723), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n676), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n684), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n654), .CK(clk), .RN(n1724), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n666), .CK(clk), .RN(n1723), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n670), .CK(clk), .RN(n1724), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n674), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n899), .CK(clk), .RN(n1726),
.Q(intDY_EWSW[10]), .QN(n957) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n650), .CK(clk), .RN(n1730), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n662), .CK(clk), .RN(n1730), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n648), .CK(clk), .RN(n1741), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n1740), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n686), .CK(clk), .RN(n1739), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n688), .CK(clk), .RN(n1739), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n777), .CK(clk), .RN(n1006), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n765), .CK(clk), .RN(n1722), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n786), .CK(clk), .RN(n1730), .Q(
DMP_SFG[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n789), .CK(clk), .RN(n1724), .Q(
DMP_SFG[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n582), .CK(clk), .RN(n1744), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n584), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n597), .CK(clk), .RN(n1005), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n601), .CK(clk), .RN(n956), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n768), .CK(clk), .RN(n1732), .Q(
DMP_SFG[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n780), .CK(clk), .RN(n1743), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n798), .CK(clk), .RN(n956), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n771), .CK(clk), .RN(n1722), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n546), .CK(clk), .RN(n1747), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n547), .CK(clk), .RN(n1746), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n847), .CK(clk), .RN(n1738),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n783), .CK(clk), .RN(n1736), .Q(
DMP_SFG[5]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n894), .CK(clk), .RN(n1745),
.Q(intDY_EWSW[15]), .QN(n1752) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n889), .CK(clk), .RN(n1728),
.Q(intDY_EWSW[20]), .QN(n1682) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n888), .CK(clk), .RN(n1739),
.Q(intDY_EWSW[21]), .QN(n1677) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n811), .CK(clk), .RN(n1731), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n712), .CK(clk), .RN(n1733), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n717), .CK(clk), .RN(n1006), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1006), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n878), .CK(clk), .RN(n1724),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n931), .CK(clk), .RN(n1724),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n923), .CK(clk), .RN(n1723),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n929), .CK(clk), .RN(n1724),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n921), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n942), .CK(clk), .RN(n1727), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n906), .CK(clk), .RN(n1725), .Q(
intDY_EWSW[3]), .QN(n1750) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n881), .CK(clk), .RN(n1723),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n898), .CK(clk), .RN(n1746),
.Q(intDY_EWSW[11]), .QN(n1751) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n924), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n861), .CK(clk), .RN(n1747), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n851), .CK(clk), .RN(n1723), .Q(
shift_value_SHT2_EWR[2]), .QN(n1661) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n852), .CK(clk), .RN(n1724), .Q(
Data_array_SWR[0]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1732), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n853), .CK(clk), .RN(n1724), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n1741), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n606), .CK(clk), .RN(n1733), .Q(
DmP_mant_SFG_SWR[8]), .QN(n998) );
ADDFX1TS DP_OP_15J11_123_2691_U8 ( .A(n1663), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J11_123_2691_n8), .CO(DP_OP_15J11_123_2691_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J11_123_2691_U7 ( .A(n1669), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J11_123_2691_n7), .CO(DP_OP_15J11_123_2691_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J11_123_2691_U6 ( .A(n1673), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J11_123_2691_n6), .CO(DP_OP_15J11_123_2691_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J11_123_2691_U5 ( .A(n1672), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J11_123_2691_n5), .CO(DP_OP_15J11_123_2691_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7[1]), .QN(n954) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n950), .CK(clk), .RN(n1734), .Q(
Shift_reg_FLAGS_7_6), .QN(n1003) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n944), .CK(clk), .RN(n1727), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n946), .CK(clk), .RN(n1727), .Q(
n953), .QN(n1748) );
CLKINVX6TS U964 ( .A(rst), .Y(n1005) );
AOI211X1TS U965 ( .A0(n1456), .A1(Data_array_SWR[3]), .B0(n1455), .C0(n1454),
.Y(n1590) );
AOI211X1TS U966 ( .A0(n1456), .A1(Data_array_SWR[2]), .B0(n1451), .C0(n1450),
.Y(n1593) );
CMPR32X2TS U967 ( .A(DMP_SFG[1]), .B(n1020), .C(n1461), .CO(n1474), .S(n1007) );
AOI222X4TS U968 ( .A0(n989), .A1(n1471), .B0(n990), .B1(n1470), .C0(
Data_array_SWR[23]), .C1(n1445), .Y(n1436) );
INVX6TS U969 ( .A(n1354), .Y(n955) );
CLKINVX6TS U970 ( .A(n1373), .Y(n1221) );
AOI31XLTS U971 ( .A0(n1205), .A1(Raw_mant_NRM_SWR[8]), .A2(n1664), .B0(n1330), .Y(n1206) );
AND2X4TS U972 ( .A(Shift_reg_FLAGS_7_6), .B(n1085), .Y(n1095) );
CLKINVX3TS U973 ( .A(n1344), .Y(n1347) );
CLKINVX3TS U974 ( .A(n1349), .Y(n1348) );
BUFX6TS U975 ( .A(n1403), .Y(n1617) );
INVX6TS U976 ( .A(n1379), .Y(n1210) );
CLKINVX3TS U977 ( .A(n1544), .Y(n1420) );
NOR2X6TS U978 ( .A(shift_value_SHT2_EWR[4]), .B(n1453), .Y(n1421) );
INVX6TS U979 ( .A(Shift_reg_FLAGS_7_6), .Y(n1086) );
CLKINVX3TS U980 ( .A(n1543), .Y(n1429) );
BUFX6TS U981 ( .A(n1639), .Y(n1505) );
BUFX6TS U982 ( .A(n1005), .Y(n956) );
NAND2BXLTS U983 ( .AN(n992), .B(intDY_EWSW[2]), .Y(n1034) );
NAND2BXLTS U984 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1068) );
NAND2BXLTS U985 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1022) );
NAND2BXLTS U986 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1047) );
OAI2BB2XLTS U987 ( .B0(intDY_EWSW[14]), .B1(n1053), .A0N(intDX_EWSW[15]),
.A1N(n1752), .Y(n1054) );
NAND2BXLTS U988 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1043) );
NAND2BXLTS U989 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1062) );
AO22XLTS U990 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1506), .B0(n1505), .B1(n1001),
.Y(n966) );
AOI222X4TS U991 ( .A0(n989), .A1(n1420), .B0(n990), .B1(n1421), .C0(
Data_array_SWR[23]), .C1(n1429), .Y(n1519) );
NAND2BXLTS U992 ( .AN(n1333), .B(n1014), .Y(n1017) );
AOI222X1TS U993 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1362), .C1(DmP_mant_SHT1_SW[8]), .Y(n1260)
);
AOI222X1TS U994 ( .A0(DMP_SFG[12]), .A1(n976), .B0(DMP_SFG[12]), .B1(n1311),
.C0(n976), .C1(n1311), .Y(intadd_5_B_0_) );
AOI211X1TS U995 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n954), .B0(n1362), .C0(
n1351), .Y(n1356) );
AOI222X1TS U996 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n955), .B0(n1363), .B1(n982), .C0(n1362), .C1(DmP_mant_SHT1_SW[14]), .Y(n1253) );
AOI31X1TS U997 ( .A0(n977), .A1(DMP_SFG[2]), .A2(n1463), .B0(n1473), .Y(
n1483) );
AOI222X1TS U998 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n955), .B0(n1363), .B1(n984), .C0(n1362), .C1(DmP_mant_SHT1_SW[10]), .Y(n1269) );
AOI222X1TS U999 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n955), .B0(n1363), .B1(n983), .C0(n1362), .C1(DmP_mant_SHT1_SW[12]), .Y(n1266) );
AOI222X1TS U1000 ( .A0(n1570), .A1(n1621), .B0(Data_array_SWR[9]), .B1(n1588), .C0(n1569), .C1(n1586), .Y(n1602) );
AOI222X1TS U1001 ( .A0(n1570), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[9]), .C0(n1569), .C1(n1503), .Y(n1568) );
INVX4TS U1002 ( .A(n1618), .Y(n1613) );
BUFX4TS U1003 ( .A(n1719), .Y(n1404) );
AOI222X1TS U1004 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1362), .C1(DmP_mant_SHT1_SW[3]), .Y(n1280)
);
AOI222X1TS U1005 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1362), .C1(n979), .Y(n1276) );
AOI222X1TS U1006 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n955), .B0(n1363), .B1(n981), .C0(n1362), .C1(DmP_mant_SHT1_SW[16]), .Y(n1250) );
AOI222X1TS U1007 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n955), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1362), .C0(n1363), .C1(n980), .Y(n1261) );
AO22XLTS U1008 ( .A0(n1521), .A1(DMP_SHT2_EWSW[5]), .B0(n1618), .B1(
DMP_SFG[5]), .Y(n783) );
AO22XLTS U1009 ( .A0(n1616), .A1(DMP_SHT2_EWSW[9]), .B0(n1617), .B1(
DMP_SFG[9]), .Y(n771) );
AO22XLTS U1010 ( .A0(n1521), .A1(DMP_SHT2_EWSW[0]), .B0(n1618), .B1(
DMP_SFG[0]), .Y(n798) );
AO22XLTS U1011 ( .A0(n1616), .A1(DMP_SHT2_EWSW[6]), .B0(n1618), .B1(
DMP_SFG[6]), .Y(n780) );
AO22XLTS U1012 ( .A0(n1521), .A1(DMP_SHT2_EWSW[10]), .B0(n1520), .B1(
DMP_SFG[10]), .Y(n768) );
AO22XLTS U1013 ( .A0(n1521), .A1(n1584), .B0(n1520), .B1(DmP_mant_SFG_SWR[2]), .Y(n601) );
AO22XLTS U1014 ( .A0(n1521), .A1(n1583), .B0(n1520), .B1(DmP_mant_SFG_SWR[3]), .Y(n597) );
AO22XLTS U1015 ( .A0(n1521), .A1(n1516), .B0(n1520), .B1(
DmP_mant_SFG_SWR[12]), .Y(n584) );
AO22XLTS U1016 ( .A0(n1521), .A1(n1567), .B0(n1520), .B1(
DmP_mant_SFG_SWR[13]), .Y(n582) );
AO22XLTS U1017 ( .A0(n1616), .A1(DMP_SHT2_EWSW[3]), .B0(n1618), .B1(
DMP_SFG[3]), .Y(n789) );
AO22XLTS U1018 ( .A0(n1616), .A1(DMP_SHT2_EWSW[4]), .B0(n1618), .B1(
DMP_SFG[4]), .Y(n786) );
AO22XLTS U1019 ( .A0(n1616), .A1(DMP_SHT2_EWSW[11]), .B0(n1403), .B1(
DMP_SFG[11]), .Y(n765) );
AO22XLTS U1020 ( .A0(n1411), .A1(DmP_EXP_EWSW[1]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[1]), .Y(n688) );
AO22XLTS U1021 ( .A0(n1411), .A1(DmP_EXP_EWSW[2]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[2]), .Y(n686) );
AO22XLTS U1022 ( .A0(n1411), .A1(DmP_EXP_EWSW[6]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[6]), .Y(n678) );
AO22XLTS U1023 ( .A0(n1411), .A1(DmP_EXP_EWSW[21]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[21]), .Y(n648) );
AO22XLTS U1024 ( .A0(n1416), .A1(DmP_EXP_EWSW[20]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[20]), .Y(n650) );
AO22XLTS U1025 ( .A0(n1411), .A1(DmP_EXP_EWSW[8]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[8]), .Y(n674) );
AO22XLTS U1026 ( .A0(n1411), .A1(DmP_EXP_EWSW[10]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[10]), .Y(n670) );
AO22XLTS U1027 ( .A0(n1411), .A1(DmP_EXP_EWSW[12]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[12]), .Y(n666) );
AO22XLTS U1028 ( .A0(n1411), .A1(DmP_EXP_EWSW[18]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[18]), .Y(n654) );
AO22XLTS U1029 ( .A0(n1411), .A1(DmP_EXP_EWSW[3]), .B0(n1716), .B1(
DmP_mant_SHT1_SW[3]), .Y(n684) );
AO22XLTS U1030 ( .A0(n1411), .A1(DmP_EXP_EWSW[7]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[7]), .Y(n676) );
AO22XLTS U1031 ( .A0(n1416), .A1(DmP_EXP_EWSW[17]), .B0(n1413), .B1(
DmP_mant_SHT1_SW[17]), .Y(n656) );
AO22XLTS U1032 ( .A0(n1616), .A1(DMP_SHT2_EWSW[1]), .B0(n1618), .B1(
DMP_SFG[1]), .Y(n795) );
AO22XLTS U1033 ( .A0(n1521), .A1(DMP_SHT2_EWSW[8]), .B0(n1617), .B1(
DMP_SFG[8]), .Y(n774) );
AO22XLTS U1034 ( .A0(n1340), .A1(n1564), .B0(n1341), .B1(n978), .Y(n946) );
AO22XLTS U1035 ( .A0(n1345), .A1(Data_X[31]), .B0(n1343), .B1(intDX_EWSW[31]), .Y(n912) );
AO22XLTS U1036 ( .A0(n1521), .A1(DMP_SHT2_EWSW[12]), .B0(n1618), .B1(
DMP_SFG[12]), .Y(n762) );
AO22XLTS U1037 ( .A0(n1616), .A1(DMP_SHT2_EWSW[2]), .B0(n1618), .B1(
DMP_SFG[2]), .Y(n792) );
NAND2BXLTS U1038 ( .AN(n1525), .B(n1524), .Y(n1526) );
AO22XLTS U1039 ( .A0(n1416), .A1(DmP_EXP_EWSW[15]), .B0(n1405), .B1(n981),
.Y(n660) );
AO22XLTS U1040 ( .A0(n1416), .A1(DmP_EXP_EWSW[13]), .B0(n1415), .B1(n982),
.Y(n664) );
AO22XLTS U1041 ( .A0(n1411), .A1(DmP_EXP_EWSW[11]), .B0(n1716), .B1(n983),
.Y(n668) );
AO22XLTS U1042 ( .A0(n1411), .A1(DmP_EXP_EWSW[9]), .B0(n1413), .B1(n984),
.Y(n672) );
AO22XLTS U1043 ( .A0(n1411), .A1(DmP_EXP_EWSW[5]), .B0(n1413), .B1(n985),
.Y(n680) );
AO22XLTS U1044 ( .A0(n1411), .A1(DmP_EXP_EWSW[4]), .B0(n1415), .B1(n979),
.Y(n682) );
AO22XLTS U1045 ( .A0(n1411), .A1(DmP_EXP_EWSW[0]), .B0(n1413), .B1(n986),
.Y(n690) );
AO22XLTS U1046 ( .A0(n1341), .A1(busy), .B0(n1340), .B1(n978), .Y(n947) );
OA22X1TS U1047 ( .A0(n1505), .A1(DmP_mant_SFG_SWR[14]), .B0(n1002), .B1(n996), .Y(n962) );
BUFX3TS U1048 ( .A(n1005), .Y(n1732) );
NOR2BX2TS U1049 ( .AN(n1325), .B(n1324), .Y(n1200) );
NAND4XLTS U1050 ( .A(n1626), .B(n995), .C(n961), .D(n1625), .Y(n1324) );
AOI222X1TS U1051 ( .A0(n1589), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[8]), .C0(n1587), .C1(n1503), .Y(n1585) );
CLKINVX3TS U1052 ( .A(n1591), .Y(n1622) );
AOI222X1TS U1053 ( .A0(n1589), .A1(n1621), .B0(Data_array_SWR[8]), .B1(n1588), .C0(n1587), .C1(n1586), .Y(n1604) );
CLKINVX3TS U1054 ( .A(n1548), .Y(n1588) );
BUFX4TS U1055 ( .A(n1743), .Y(n1738) );
BUFX4TS U1056 ( .A(n1745), .Y(n1747) );
BUFX4TS U1057 ( .A(n1744), .Y(n1735) );
BUFX4TS U1058 ( .A(n1741), .Y(n1746) );
BUFX4TS U1059 ( .A(n1736), .Y(n1745) );
BUFX4TS U1060 ( .A(n1736), .Y(n1729) );
BUFX4TS U1061 ( .A(n956), .Y(n1740) );
BUFX4TS U1062 ( .A(n1005), .Y(n1731) );
BUFX4TS U1063 ( .A(n956), .Y(n1739) );
NOR2X4TS U1064 ( .A(shift_value_SHT2_EWR[4]), .B(n1621), .Y(n1586) );
BUFX4TS U1065 ( .A(n1005), .Y(n1744) );
BUFX4TS U1066 ( .A(n1005), .Y(n1741) );
NOR2X4TS U1067 ( .A(shift_value_SHT2_EWR[4]), .B(n1592), .Y(n1503) );
BUFX6TS U1068 ( .A(n1403), .Y(n1618) );
CLKINVX6TS U1069 ( .A(n1405), .Y(n1414) );
BUFX6TS U1070 ( .A(n1716), .Y(n1413) );
BUFX4TS U1071 ( .A(n1728), .Y(n1724) );
BUFX4TS U1072 ( .A(n1005), .Y(n1733) );
BUFX4TS U1073 ( .A(n1005), .Y(n1736) );
BUFX4TS U1074 ( .A(n1005), .Y(n1743) );
NOR2X2TS U1075 ( .A(shift_value_SHT2_EWR[2]), .B(n1666), .Y(n1445) );
OAI22X2TS U1076 ( .A0(n1630), .A1(n1453), .B0(n1697), .B1(n1452), .Y(n1572)
);
OAI22X2TS U1077 ( .A0(n1646), .A1(n1453), .B0(n1701), .B1(n1452), .Y(n1581)
);
BUFX6TS U1078 ( .A(n1004), .Y(n1345) );
BUFX4TS U1079 ( .A(n1004), .Y(n1349) );
BUFX4TS U1080 ( .A(n1004), .Y(n1344) );
BUFX4TS U1081 ( .A(n1725), .Y(n1723) );
BUFX4TS U1082 ( .A(n1729), .Y(n1730) );
BUFX4TS U1083 ( .A(n1739), .Y(n1722) );
BUFX4TS U1084 ( .A(n1726), .Y(n1727) );
INVX2TS U1085 ( .A(n962), .Y(n976) );
INVX2TS U1086 ( .A(n966), .Y(n977) );
OR2X1TS U1087 ( .A(n954), .B(n1226), .Y(n1354) );
OAI211X2TS U1088 ( .A0(n1659), .A1(n1208), .B0(n1207), .C0(n1206), .Y(n1226)
);
NOR2X4TS U1089 ( .A(n1452), .B(shift_value_SHT2_EWR[4]), .Y(n1456) );
INVX2TS U1090 ( .A(n970), .Y(n978) );
INVX2TS U1091 ( .A(n975), .Y(n979) );
INVX2TS U1092 ( .A(n969), .Y(n980) );
INVX2TS U1093 ( .A(n968), .Y(n981) );
INVX2TS U1094 ( .A(n960), .Y(n982) );
INVX2TS U1095 ( .A(n974), .Y(n983) );
INVX2TS U1096 ( .A(n959), .Y(n984) );
INVX2TS U1097 ( .A(n973), .Y(n985) );
INVX2TS U1098 ( .A(n972), .Y(n986) );
INVX2TS U1099 ( .A(n971), .Y(n987) );
CLKINVX3TS U1100 ( .A(n1287), .Y(n1265) );
CLKINVX6TS U1101 ( .A(n1621), .Y(n1592) );
BUFX6TS U1102 ( .A(left_right_SHT2), .Y(n1621) );
INVX3TS U1103 ( .A(n1293), .Y(n1371) );
BUFX6TS U1104 ( .A(n1223), .Y(n1369) );
BUFX6TS U1105 ( .A(n1237), .Y(n1362) );
BUFX6TS U1106 ( .A(n1209), .Y(n1363) );
CLKINVX6TS U1107 ( .A(n1345), .Y(n1343) );
CLKINVX3TS U1108 ( .A(n1618), .Y(n1624) );
INVX2TS U1109 ( .A(n965), .Y(n988) );
INVX2TS U1110 ( .A(n958), .Y(n989) );
INVX2TS U1111 ( .A(n967), .Y(n990) );
AOI32X1TS U1112 ( .A0(n1699), .A1(n1068), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1645), .Y(n1069) );
AOI221X1TS U1113 ( .A0(n1699), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1645), .C0(n1148), .Y(n1153) );
AOI221X1TS U1114 ( .A0(n957), .A1(n991), .B0(intDX_EWSW[11]), .B1(n1751),
.C0(n1156), .Y(n1161) );
AOI221X1TS U1115 ( .A0(n1683), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1698), .C0(n1141), .Y(n1145) );
INVX2TS U1116 ( .A(n964), .Y(n991) );
AOI221X1TS U1117 ( .A0(n1678), .A1(n992), .B0(intDX_EWSW[3]), .B1(n1750),
.C0(n1164), .Y(n1169) );
INVX2TS U1118 ( .A(n963), .Y(n992) );
AOI221X1TS U1119 ( .A0(n1695), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1694), .C0(n1147), .Y(n1154) );
AOI221X1TS U1120 ( .A0(n1643), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1686), .C0(n1150), .Y(n1151) );
AOI221X1TS U1121 ( .A0(n1681), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1752), .C0(n1158), .Y(n1159) );
OAI211X2TS U1122 ( .A0(intDX_EWSW[20]), .A1(n1682), .B0(n1076), .C0(n1062),
.Y(n1071) );
AOI221X1TS U1123 ( .A0(n1682), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1677), .C0(n1149), .Y(n1152) );
OAI211X2TS U1124 ( .A0(intDX_EWSW[12]), .A1(n1680), .B0(n1057), .C0(n1043),
.Y(n1059) );
AOI221X1TS U1125 ( .A0(n1680), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1676), .C0(n1157), .Y(n1160) );
AOI211X1TS U1126 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1202), .B0(n1218), .C0(
n1193), .Y(n1195) );
OAI31XLTS U1127 ( .A0(n1402), .A1(n1178), .A2(n1408), .B0(n1177), .Y(n801)
);
NOR2X2TS U1128 ( .A(n1243), .B(n954), .Y(n1332) );
NOR4BBX2TS U1129 ( .AN(n1220), .BN(n1219), .C(n1218), .D(n1217), .Y(n1243)
);
NOR2X2TS U1130 ( .A(n1382), .B(DMP_EXP_EWSW[23]), .Y(n1387) );
BUFX4TS U1131 ( .A(n1743), .Y(n1726) );
XNOR2X2TS U1132 ( .A(DMP_exp_NRM2_EW[6]), .B(n1015), .Y(n1333) );
XNOR2X2TS U1133 ( .A(DMP_exp_NRM2_EW[0]), .B(n1312), .Y(n1298) );
XNOR2X2TS U1134 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J11_123_2691_n4), .Y(
n1300) );
CLKINVX6TS U1135 ( .A(n1505), .Y(n1506) );
NOR2X2TS U1136 ( .A(n1460), .B(DMP_SFG[3]), .Y(n1472) );
NOR2X2TS U1137 ( .A(n1437), .B(DMP_SFG[4]), .Y(n1484) );
NOR2X2TS U1138 ( .A(n1310), .B(DMP_SFG[11]), .Y(n1525) );
NOR2X2TS U1139 ( .A(n1495), .B(DMP_SFG[7]), .Y(n1554) );
AOI222X1TS U1140 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1237), .C1(DmP_mant_SHT1_SW[7]), .Y(n1294)
);
AOI222X1TS U1141 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1362), .C1(DmP_mant_SHT1_SW[18]), .Y(n1264) );
AOI222X4TS U1142 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1362), .C1(DmP_mant_SHT1_SW[17]), .Y(n1288) );
AOI222X1TS U1143 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1362), .C1(DmP_mant_SHT1_SW[22]), .Y(n1270) );
AOI211X1TS U1144 ( .A0(n1216), .A1(n1215), .B0(Raw_mant_NRM_SWR[24]), .C0(
Raw_mant_NRM_SWR[25]), .Y(n1217) );
OAI211XLTS U1145 ( .A0(n977), .A1(DMP_SFG[2]), .B0(n1461), .C0(DMP_SFG[1]),
.Y(n1464) );
NOR2X4TS U1146 ( .A(n1515), .B(n1514), .Y(n1595) );
OAI2BB1X2TS U1147 ( .A0N(n1306), .A1N(n1305), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1514) );
NAND3X2TS U1148 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1655), .Y(n1543) );
NAND2X4TS U1149 ( .A(n954), .B(n1404), .Y(n1379) );
BUFX4TS U1150 ( .A(n1748), .Y(n1562) );
XOR2XLTS U1151 ( .A(DMP_SFG[12]), .B(n976), .Y(n1427) );
AOI222X1TS U1152 ( .A0(n1573), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[7]), .C0(n1572), .C1(n1503), .Y(n1571) );
AOI222X1TS U1153 ( .A0(n1573), .A1(n1621), .B0(Data_array_SWR[7]), .B1(n1588), .C0(n1572), .C1(n1586), .Y(n1606) );
AOI222X1TS U1154 ( .A0(n1582), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[6]), .C0(n1581), .C1(n1503), .Y(n1580) );
AOI222X1TS U1155 ( .A0(n1582), .A1(n1621), .B0(Data_array_SWR[6]), .B1(n1588), .C0(n1581), .C1(n1586), .Y(n1608) );
INVX4TS U1156 ( .A(n1095), .Y(n1406) );
AOI222X1TS U1157 ( .A0(n1576), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[5]), .C0(n1575), .C1(n1503), .Y(n1574) );
AOI222X1TS U1158 ( .A0(n1576), .A1(n1621), .B0(Data_array_SWR[5]), .B1(n1588), .C0(n1575), .C1(n1586), .Y(n1610) );
AOI222X1TS U1159 ( .A0(n1579), .A1(n1592), .B0(n1622), .B1(Data_array_SWR[4]), .C0(n1578), .C1(n1503), .Y(n1577) );
AOI222X1TS U1160 ( .A0(n1579), .A1(n1621), .B0(Data_array_SWR[4]), .B1(n1588), .C0(n1578), .C1(n1586), .Y(n1612) );
INVX3TS U1161 ( .A(n1409), .Y(n1597) );
CLKINVX6TS U1162 ( .A(n1404), .Y(n1417) );
AOI222X4TS U1163 ( .A0(Data_array_SWR[19]), .A1(n1420), .B0(
Data_array_SWR[22]), .B1(n1429), .C0(Data_array_SWR[16]), .C1(n1421),
.Y(n1518) );
AOI222X4TS U1164 ( .A0(Data_array_SWR[19]), .A1(n1471), .B0(
Data_array_SWR[22]), .B1(n1445), .C0(Data_array_SWR[16]), .C1(n1470),
.Y(n1502) );
NOR2X2TS U1165 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1670), .Y(n1338) );
NOR3X2TS U1166 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1208),
.Y(n1202) );
AOI32X1TS U1167 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1214), .A2(n1213), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1214), .Y(n1215) );
NOR2X2TS U1168 ( .A(Raw_mant_NRM_SWR[13]), .B(n1187), .Y(n1212) );
OAI21X2TS U1169 ( .A0(intDX_EWSW[18]), .A1(n1699), .B0(n1068), .Y(n1148) );
NOR3X1TS U1170 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1325) );
AOI221X1TS U1171 ( .A0(n1696), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1674), .C0(n1166), .Y(n1167) );
AND2X2TS U1172 ( .A(beg_OP), .B(n1342), .Y(n1004) );
NOR2XLTS U1173 ( .A(n1751), .B(intDX_EWSW[11]), .Y(n1045) );
OAI21XLTS U1174 ( .A0(intDX_EWSW[15]), .A1(n1752), .B0(intDX_EWSW[14]), .Y(
n1053) );
NOR2XLTS U1175 ( .A(n1066), .B(intDY_EWSW[16]), .Y(n1067) );
OAI21XLTS U1176 ( .A0(intDX_EWSW[21]), .A1(n1677), .B0(intDX_EWSW[20]), .Y(
n1065) );
NOR2XLTS U1177 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1213) );
OAI21XLTS U1178 ( .A0(n1554), .A1(n1509), .B0(n1552), .Y(n1510) );
NOR2XLTS U1179 ( .A(n1473), .B(n1472), .Y(n1476) );
OAI21XLTS U1180 ( .A0(n1178), .A1(n1086), .B0(n1175), .Y(n1176) );
AOI31XLTS U1181 ( .A0(n1417), .A1(Shift_amount_SHT1_EWR[4]), .A2(n954), .B0(
n1314), .Y(n1196) );
OAI21XLTS U1182 ( .A0(n1379), .A1(n1655), .B0(n1196), .Y(n848) );
OAI211XLTS U1183 ( .A0(n1269), .A1(n1369), .B0(n1268), .C0(n1267), .Y(n863)
);
OAI21XLTS U1184 ( .A0(n1683), .A1(n1408), .B0(n1088), .Y(n807) );
OAI21XLTS U1185 ( .A0(n957), .A1(n1182), .B0(n1134), .Y(n824) );
OAI211XLTS U1186 ( .A0(n1276), .A1(n1221), .B0(n1228), .C0(n1227), .Y(n855)
);
CLKBUFX2TS U1187 ( .A(n1005), .Y(n1006) );
BUFX3TS U1188 ( .A(n1731), .Y(n1734) );
BUFX3TS U1189 ( .A(n1736), .Y(n1742) );
BUFX3TS U1190 ( .A(n956), .Y(n1728) );
BUFX3TS U1191 ( .A(n1743), .Y(n1725) );
BUFX3TS U1192 ( .A(n1726), .Y(n1721) );
AO22XLTS U1193 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n954),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n634) );
AO22XLTS U1194 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n954),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n625) );
INVX4TS U1195 ( .A(n1748), .Y(n1477) );
AOI2BB2X1TS U1196 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n1002), .A0N(n1002), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n1018) );
CLKAND2X2TS U1197 ( .A(n1018), .B(DMP_SFG[0]), .Y(n1020) );
AOI2BB2X1TS U1198 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n1002), .A0N(n1002), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1461) );
AO22XLTS U1199 ( .A0(n1562), .A1(Raw_mant_NRM_SWR[3]), .B0(n1477), .B1(n1007), .Y(n599) );
AO22XLTS U1200 ( .A0(n1748), .A1(Raw_mant_NRM_SWR[4]), .B0(n1477), .B1(n1008), .Y(n596) );
INVX2TS U1201 ( .A(DP_OP_15J11_123_2691_n4), .Y(n1009) );
NAND2X1TS U1202 ( .A(n1688), .B(n1009), .Y(n1015) );
INVX1TS U1203 ( .A(LZD_output_NRM2_EW[0]), .Y(n1312) );
NOR2XLTS U1204 ( .A(n1298), .B(exp_rslt_NRM2_EW1[1]), .Y(n1012) );
INVX2TS U1205 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1011) );
INVX2TS U1206 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1010) );
NAND4BXLTS U1207 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1012), .C(n1011), .D(n1010), .Y(n1013) );
NOR2XLTS U1208 ( .A(n1013), .B(n1300), .Y(n1014) );
INVX2TS U1209 ( .A(n1015), .Y(n1016) );
NAND2X1TS U1210 ( .A(n1687), .B(n1016), .Y(n1303) );
XNOR2X1TS U1211 ( .A(DMP_exp_NRM2_EW[7]), .B(n1303), .Y(n1297) );
OR2X1TS U1212 ( .A(n1017), .B(n1297), .Y(n1308) );
CLKBUFX2TS U1213 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1409) );
NAND2X2TS U1214 ( .A(n1308), .B(n1409), .Y(n1334) );
OA22X1TS U1215 ( .A0(n1334), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n839) );
OA22X1TS U1216 ( .A0(n1334), .A1(n1298), .B0(final_result_ieee[23]), .B1(
Shift_reg_FLAGS_7[0]), .Y(n842) );
OA22X1TS U1217 ( .A0(n1334), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n840) );
OA22X1TS U1218 ( .A0(n1334), .A1(n1300), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n837) );
OA22X1TS U1219 ( .A0(n1334), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n841) );
OA22X1TS U1220 ( .A0(n1334), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n838) );
INVX4TS U1221 ( .A(n1404), .Y(busy) );
OAI21XLTS U1222 ( .A0(n1417), .A1(n1592), .B0(n954), .Y(n910) );
NOR2XLTS U1223 ( .A(n1018), .B(DMP_SFG[0]), .Y(n1019) );
INVX4TS U1224 ( .A(n1748), .Y(n1564) );
OAI32X1TS U1225 ( .A0(n1748), .A1(n1020), .A2(n1019), .B0(n1564), .B1(n1657),
.Y(n600) );
NOR2X1TS U1226 ( .A(n1692), .B(intDX_EWSW[25]), .Y(n1079) );
NOR2XLTS U1227 ( .A(n1079), .B(intDY_EWSW[24]), .Y(n1021) );
AOI22X1TS U1228 ( .A0(intDX_EWSW[25]), .A1(n1692), .B0(intDX_EWSW[24]), .B1(
n1021), .Y(n1025) );
OAI21X1TS U1229 ( .A0(intDX_EWSW[26]), .A1(n1691), .B0(n1022), .Y(n1080) );
NAND3XLTS U1230 ( .A(n1691), .B(n1022), .C(intDX_EWSW[26]), .Y(n1024) );
NAND2BXLTS U1231 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1023) );
OAI211XLTS U1232 ( .A0(n1025), .A1(n1080), .B0(n1024), .C0(n1023), .Y(n1030)
);
NOR2X1TS U1233 ( .A(n1667), .B(intDX_EWSW[30]), .Y(n1028) );
NOR2X1TS U1234 ( .A(n1638), .B(intDX_EWSW[29]), .Y(n1026) );
AOI211X1TS U1235 ( .A0(intDY_EWSW[28]), .A1(n1698), .B0(n1028), .C0(n1026),
.Y(n1078) );
NOR3X1TS U1236 ( .A(n1698), .B(n1026), .C(intDY_EWSW[28]), .Y(n1027) );
AOI221X1TS U1237 ( .A0(intDX_EWSW[30]), .A1(n1667), .B0(intDX_EWSW[29]),
.B1(n1638), .C0(n1027), .Y(n1029) );
AOI2BB2X1TS U1238 ( .B0(n1030), .B1(n1078), .A0N(n1029), .A1N(n1028), .Y(
n1084) );
NOR2X1TS U1239 ( .A(n1694), .B(intDX_EWSW[17]), .Y(n1066) );
OAI22X1TS U1240 ( .A0(n957), .A1(n991), .B0(n1751), .B1(intDX_EWSW[11]), .Y(
n1156) );
INVX2TS U1241 ( .A(n1156), .Y(n1050) );
OAI211XLTS U1242 ( .A0(intDX_EWSW[8]), .A1(n1696), .B0(n1047), .C0(n1050),
.Y(n1061) );
OAI2BB1X1TS U1243 ( .A0N(n1658), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1031) );
OAI22X1TS U1244 ( .A0(intDY_EWSW[4]), .A1(n1031), .B0(n1658), .B1(
intDY_EWSW[5]), .Y(n1042) );
OAI2BB1X1TS U1245 ( .A0N(n1637), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1032) );
OAI22X1TS U1246 ( .A0(intDY_EWSW[6]), .A1(n1032), .B0(n1637), .B1(
intDY_EWSW[7]), .Y(n1041) );
OAI21XLTS U1247 ( .A0(intDX_EWSW[1]), .A1(n1695), .B0(intDX_EWSW[0]), .Y(
n1033) );
OAI2BB2XLTS U1248 ( .B0(intDY_EWSW[0]), .B1(n1033), .A0N(intDX_EWSW[1]),
.A1N(n1695), .Y(n1035) );
OAI211XLTS U1249 ( .A0(n1750), .A1(intDX_EWSW[3]), .B0(n1035), .C0(n1034),
.Y(n1038) );
OAI21XLTS U1250 ( .A0(intDX_EWSW[3]), .A1(n1750), .B0(n992), .Y(n1036) );
AOI2BB2XLTS U1251 ( .B0(intDX_EWSW[3]), .B1(n1750), .A0N(intDY_EWSW[2]),
.A1N(n1036), .Y(n1037) );
AOI222X1TS U1252 ( .A0(intDY_EWSW[4]), .A1(n1636), .B0(n1038), .B1(n1037),
.C0(intDY_EWSW[5]), .C1(n1658), .Y(n1040) );
AOI22X1TS U1253 ( .A0(intDY_EWSW[7]), .A1(n1637), .B0(intDY_EWSW[6]), .B1(
n1660), .Y(n1039) );
OAI32X1TS U1254 ( .A0(n1042), .A1(n1041), .A2(n1040), .B0(n1039), .B1(n1041),
.Y(n1060) );
OA22X1TS U1255 ( .A0(n1681), .A1(intDX_EWSW[14]), .B0(n1752), .B1(
intDX_EWSW[15]), .Y(n1057) );
OAI21XLTS U1256 ( .A0(intDX_EWSW[13]), .A1(n1676), .B0(intDX_EWSW[12]), .Y(
n1044) );
OAI2BB2XLTS U1257 ( .B0(intDY_EWSW[12]), .B1(n1044), .A0N(intDX_EWSW[13]),
.A1N(n1676), .Y(n1056) );
NOR2XLTS U1258 ( .A(n1045), .B(intDY_EWSW[10]), .Y(n1046) );
AOI22X1TS U1259 ( .A0(intDX_EWSW[11]), .A1(n1751), .B0(n991), .B1(n1046),
.Y(n1052) );
NAND2BXLTS U1260 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1049) );
NAND3XLTS U1261 ( .A(n1696), .B(n1047), .C(intDX_EWSW[8]), .Y(n1048) );
AOI21X1TS U1262 ( .A0(n1049), .A1(n1048), .B0(n1059), .Y(n1051) );
OAI2BB2XLTS U1263 ( .B0(n1052), .B1(n1059), .A0N(n1051), .A1N(n1050), .Y(
n1055) );
AOI211X1TS U1264 ( .A0(n1057), .A1(n1056), .B0(n1055), .C0(n1054), .Y(n1058)
);
OAI31X1TS U1265 ( .A0(n1061), .A1(n1060), .A2(n1059), .B0(n1058), .Y(n1064)
);
OA22X1TS U1266 ( .A0(n1643), .A1(intDX_EWSW[22]), .B0(n1686), .B1(
intDX_EWSW[23]), .Y(n1076) );
AOI211XLTS U1267 ( .A0(intDY_EWSW[16]), .A1(n1665), .B0(n1071), .C0(n1148),
.Y(n1063) );
NAND3BXLTS U1268 ( .AN(n1066), .B(n1064), .C(n1063), .Y(n1083) );
OAI2BB2XLTS U1269 ( .B0(intDY_EWSW[20]), .B1(n1065), .A0N(intDX_EWSW[21]),
.A1N(n1677), .Y(n1075) );
AOI22X1TS U1270 ( .A0(intDX_EWSW[17]), .A1(n1694), .B0(intDX_EWSW[16]), .B1(
n1067), .Y(n1070) );
OAI32X1TS U1271 ( .A0(n1148), .A1(n1071), .A2(n1070), .B0(n1069), .B1(n1071),
.Y(n1074) );
OAI21XLTS U1272 ( .A0(intDX_EWSW[23]), .A1(n1686), .B0(intDX_EWSW[22]), .Y(
n1072) );
OAI2BB2XLTS U1273 ( .B0(intDY_EWSW[22]), .B1(n1072), .A0N(intDX_EWSW[23]),
.A1N(n1686), .Y(n1073) );
AOI211X1TS U1274 ( .A0(n1076), .A1(n1075), .B0(n1074), .C0(n1073), .Y(n1082)
);
NAND2BXLTS U1275 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1077) );
NAND4BBX1TS U1276 ( .AN(n1080), .BN(n1079), .C(n1078), .D(n1077), .Y(n1081)
);
AOI32X1TS U1277 ( .A0(n1084), .A1(n1083), .A2(n1082), .B0(n1081), .B1(n1084),
.Y(n1085) );
NOR2X1TS U1278 ( .A(n1085), .B(n1003), .Y(n1096) );
INVX4TS U1279 ( .A(n1096), .Y(n1408) );
BUFX4TS U1280 ( .A(n1086), .Y(n1183) );
AOI22X1TS U1281 ( .A0(intDX_EWSW[22]), .A1(n1095), .B0(DMP_EXP_EWSW[22]),
.B1(n1183), .Y(n1087) );
OAI21XLTS U1282 ( .A0(n1643), .A1(n1408), .B0(n1087), .Y(n812) );
BUFX4TS U1283 ( .A(n1086), .Y(n1339) );
AOI22X1TS U1284 ( .A0(n987), .A1(n1339), .B0(intDX_EWSW[27]), .B1(n1095),
.Y(n1088) );
AOI22X1TS U1285 ( .A0(intDX_EWSW[20]), .A1(n1095), .B0(DMP_EXP_EWSW[20]),
.B1(n1183), .Y(n1089) );
OAI21XLTS U1286 ( .A0(n1682), .A1(n1408), .B0(n1089), .Y(n814) );
INVX4TS U1287 ( .A(n1135), .Y(n1182) );
AOI22X1TS U1288 ( .A0(DMP_EXP_EWSW[23]), .A1(n1339), .B0(intDX_EWSW[23]),
.B1(n1095), .Y(n1090) );
OAI21XLTS U1289 ( .A0(n1686), .A1(n1182), .B0(n1090), .Y(n811) );
AOI22X1TS U1290 ( .A0(intDX_EWSW[4]), .A1(n1095), .B0(DMP_EXP_EWSW[4]), .B1(
n1086), .Y(n1091) );
OAI21XLTS U1291 ( .A0(n1679), .A1(n1408), .B0(n1091), .Y(n830) );
AOI22X1TS U1292 ( .A0(intDX_EWSW[7]), .A1(n1095), .B0(DMP_EXP_EWSW[7]), .B1(
n1086), .Y(n1092) );
OAI21XLTS U1293 ( .A0(n1684), .A1(n1182), .B0(n1092), .Y(n827) );
AOI22X1TS U1294 ( .A0(intDX_EWSW[5]), .A1(n1095), .B0(DMP_EXP_EWSW[5]), .B1(
n1086), .Y(n1093) );
OAI21XLTS U1295 ( .A0(n1641), .A1(n1182), .B0(n1093), .Y(n829) );
AOI22X1TS U1296 ( .A0(intDX_EWSW[6]), .A1(n1095), .B0(DMP_EXP_EWSW[6]), .B1(
n1086), .Y(n1094) );
OAI21XLTS U1297 ( .A0(n1674), .A1(n1182), .B0(n1094), .Y(n828) );
BUFX3TS U1298 ( .A(n1096), .Y(n1135) );
BUFX4TS U1299 ( .A(n1135), .Y(n1123) );
AOI22X1TS U1300 ( .A0(intDX_EWSW[18]), .A1(n1123), .B0(DmP_EXP_EWSW[18]),
.B1(n1339), .Y(n1097) );
OAI21XLTS U1301 ( .A0(n1699), .A1(n1406), .B0(n1097), .Y(n655) );
AOI22X1TS U1302 ( .A0(intDY_EWSW[28]), .A1(n1123), .B0(DMP_EXP_EWSW[28]),
.B1(n1183), .Y(n1098) );
OAI21XLTS U1303 ( .A0(n1698), .A1(n1175), .B0(n1098), .Y(n806) );
AOI22X1TS U1304 ( .A0(intDX_EWSW[22]), .A1(n1123), .B0(DmP_EXP_EWSW[22]),
.B1(n1339), .Y(n1099) );
OAI21XLTS U1305 ( .A0(n1643), .A1(n1406), .B0(n1099), .Y(n647) );
AOI22X1TS U1306 ( .A0(intDX_EWSW[19]), .A1(n1123), .B0(DmP_EXP_EWSW[19]),
.B1(n1339), .Y(n1100) );
OAI21XLTS U1307 ( .A0(n1645), .A1(n1406), .B0(n1100), .Y(n653) );
AOI22X1TS U1308 ( .A0(intDX_EWSW[17]), .A1(n1123), .B0(DmP_EXP_EWSW[17]),
.B1(n1339), .Y(n1101) );
OAI21XLTS U1309 ( .A0(n1694), .A1(n1175), .B0(n1101), .Y(n657) );
AOI22X1TS U1310 ( .A0(intDX_EWSW[20]), .A1(n1123), .B0(DmP_EXP_EWSW[20]),
.B1(n1339), .Y(n1102) );
OAI21XLTS U1311 ( .A0(n1682), .A1(n1175), .B0(n1102), .Y(n651) );
INVX4TS U1312 ( .A(n1095), .Y(n1175) );
AOI22X1TS U1313 ( .A0(intDX_EWSW[3]), .A1(n1135), .B0(DmP_EXP_EWSW[3]), .B1(
n1183), .Y(n1103) );
OAI21XLTS U1314 ( .A0(n1750), .A1(n1406), .B0(n1103), .Y(n685) );
AOI22X1TS U1315 ( .A0(intDY_EWSW[29]), .A1(n1135), .B0(DMP_EXP_EWSW[29]),
.B1(n1183), .Y(n1104) );
OAI21XLTS U1316 ( .A0(n1685), .A1(n1175), .B0(n1104), .Y(n805) );
AOI22X1TS U1317 ( .A0(intDX_EWSW[12]), .A1(n1123), .B0(DmP_EXP_EWSW[12]),
.B1(n1086), .Y(n1105) );
OAI21XLTS U1318 ( .A0(n1680), .A1(n1175), .B0(n1105), .Y(n667) );
AOI22X1TS U1319 ( .A0(n992), .A1(n1135), .B0(DmP_EXP_EWSW[2]), .B1(n1339),
.Y(n1106) );
OAI21XLTS U1320 ( .A0(n1678), .A1(n1406), .B0(n1106), .Y(n687) );
AOI22X1TS U1321 ( .A0(DmP_EXP_EWSW[27]), .A1(n1339), .B0(intDX_EWSW[27]),
.B1(n1135), .Y(n1107) );
OAI21XLTS U1322 ( .A0(n1683), .A1(n1175), .B0(n1107), .Y(n641) );
AOI22X1TS U1323 ( .A0(intDX_EWSW[9]), .A1(n1123), .B0(DmP_EXP_EWSW[9]), .B1(
n1183), .Y(n1108) );
OAI21XLTS U1324 ( .A0(n1675), .A1(n1406), .B0(n1108), .Y(n673) );
AOI22X1TS U1325 ( .A0(intDX_EWSW[8]), .A1(n1123), .B0(DmP_EXP_EWSW[8]), .B1(
n1086), .Y(n1109) );
OAI21XLTS U1326 ( .A0(n1696), .A1(n1175), .B0(n1109), .Y(n675) );
AOI22X1TS U1327 ( .A0(intDY_EWSW[30]), .A1(n1135), .B0(DMP_EXP_EWSW[30]),
.B1(n1183), .Y(n1110) );
OAI21XLTS U1328 ( .A0(n1644), .A1(n1406), .B0(n1110), .Y(n804) );
AOI22X1TS U1329 ( .A0(intDX_EWSW[16]), .A1(n1123), .B0(DmP_EXP_EWSW[16]),
.B1(n1339), .Y(n1111) );
OAI21XLTS U1330 ( .A0(n1642), .A1(n1175), .B0(n1111), .Y(n659) );
AOI22X1TS U1331 ( .A0(intDX_EWSW[15]), .A1(n1123), .B0(DmP_EXP_EWSW[15]),
.B1(n1339), .Y(n1112) );
OAI21XLTS U1332 ( .A0(n1752), .A1(n1406), .B0(n1112), .Y(n661) );
AOI22X1TS U1333 ( .A0(intDX_EWSW[14]), .A1(n1123), .B0(DmP_EXP_EWSW[14]),
.B1(n1183), .Y(n1113) );
OAI21XLTS U1334 ( .A0(n1681), .A1(n1406), .B0(n1113), .Y(n663) );
AOI22X1TS U1335 ( .A0(intDX_EWSW[13]), .A1(n1123), .B0(DmP_EXP_EWSW[13]),
.B1(n1339), .Y(n1114) );
OAI21XLTS U1336 ( .A0(n1676), .A1(n1175), .B0(n1114), .Y(n665) );
AOI22X1TS U1337 ( .A0(intDX_EWSW[4]), .A1(n1135), .B0(DmP_EXP_EWSW[4]), .B1(
n1086), .Y(n1115) );
OAI21XLTS U1338 ( .A0(n1679), .A1(n1406), .B0(n1115), .Y(n683) );
AOI22X1TS U1339 ( .A0(intDX_EWSW[1]), .A1(n1135), .B0(DmP_EXP_EWSW[1]), .B1(
n1339), .Y(n1116) );
OAI21XLTS U1340 ( .A0(n1695), .A1(n1175), .B0(n1116), .Y(n689) );
AOI22X1TS U1341 ( .A0(intDX_EWSW[0]), .A1(n1135), .B0(DmP_EXP_EWSW[0]), .B1(
n1183), .Y(n1117) );
OAI21XLTS U1342 ( .A0(n1693), .A1(n1406), .B0(n1117), .Y(n691) );
AOI22X1TS U1343 ( .A0(intDX_EWSW[5]), .A1(n1123), .B0(DmP_EXP_EWSW[5]), .B1(
n1183), .Y(n1118) );
OAI21XLTS U1344 ( .A0(n1641), .A1(n1175), .B0(n1118), .Y(n681) );
AOI22X1TS U1345 ( .A0(intDX_EWSW[7]), .A1(n1135), .B0(DmP_EXP_EWSW[7]), .B1(
n1183), .Y(n1119) );
OAI21XLTS U1346 ( .A0(n1684), .A1(n1406), .B0(n1119), .Y(n677) );
AOI22X1TS U1347 ( .A0(intDX_EWSW[6]), .A1(n1123), .B0(DmP_EXP_EWSW[6]), .B1(
n1339), .Y(n1120) );
OAI21XLTS U1348 ( .A0(n1674), .A1(n1175), .B0(n1120), .Y(n679) );
AOI22X1TS U1349 ( .A0(n991), .A1(n1123), .B0(DmP_EXP_EWSW[10]), .B1(n1183),
.Y(n1121) );
OAI21XLTS U1350 ( .A0(n957), .A1(n1175), .B0(n1121), .Y(n671) );
AOI22X1TS U1351 ( .A0(intDX_EWSW[11]), .A1(n1123), .B0(DmP_EXP_EWSW[11]),
.B1(n1339), .Y(n1122) );
OAI21XLTS U1352 ( .A0(n1751), .A1(n1406), .B0(n1122), .Y(n669) );
AOI22X1TS U1353 ( .A0(intDX_EWSW[21]), .A1(n1123), .B0(DmP_EXP_EWSW[21]),
.B1(n1339), .Y(n1124) );
OAI21XLTS U1354 ( .A0(n1677), .A1(n1406), .B0(n1124), .Y(n649) );
AOI22X1TS U1355 ( .A0(intDX_EWSW[0]), .A1(n1095), .B0(DMP_EXP_EWSW[0]), .B1(
n1086), .Y(n1125) );
OAI21XLTS U1356 ( .A0(n1693), .A1(n1408), .B0(n1125), .Y(n834) );
AOI22X1TS U1357 ( .A0(intDX_EWSW[9]), .A1(n1095), .B0(DMP_EXP_EWSW[9]), .B1(
n1086), .Y(n1126) );
OAI21XLTS U1358 ( .A0(n1675), .A1(n1182), .B0(n1126), .Y(n825) );
AOI22X1TS U1359 ( .A0(n992), .A1(n1095), .B0(DMP_EXP_EWSW[2]), .B1(n1086),
.Y(n1127) );
OAI21XLTS U1360 ( .A0(n1678), .A1(n1182), .B0(n1127), .Y(n832) );
AOI22X1TS U1361 ( .A0(intDX_EWSW[1]), .A1(n1095), .B0(DMP_EXP_EWSW[1]), .B1(
n1183), .Y(n1128) );
OAI21XLTS U1362 ( .A0(n1695), .A1(n1182), .B0(n1128), .Y(n833) );
AOI22X1TS U1363 ( .A0(intDX_EWSW[8]), .A1(n1095), .B0(DMP_EXP_EWSW[8]), .B1(
n1086), .Y(n1129) );
OAI21XLTS U1364 ( .A0(n1696), .A1(n1182), .B0(n1129), .Y(n826) );
AOI22X1TS U1365 ( .A0(intDX_EWSW[3]), .A1(n1095), .B0(DMP_EXP_EWSW[3]), .B1(
n1086), .Y(n1130) );
OAI21XLTS U1366 ( .A0(n1750), .A1(n1408), .B0(n1130), .Y(n831) );
BUFX3TS U1367 ( .A(n1095), .Y(n1184) );
AOI22X1TS U1368 ( .A0(intDX_EWSW[16]), .A1(n1184), .B0(DMP_EXP_EWSW[16]),
.B1(n1183), .Y(n1131) );
OAI21XLTS U1369 ( .A0(n1642), .A1(n1182), .B0(n1131), .Y(n818) );
AOI22X1TS U1370 ( .A0(intDX_EWSW[19]), .A1(n1184), .B0(DMP_EXP_EWSW[19]),
.B1(n1183), .Y(n1132) );
OAI21XLTS U1371 ( .A0(n1645), .A1(n1408), .B0(n1132), .Y(n815) );
AOI22X1TS U1372 ( .A0(intDX_EWSW[18]), .A1(n1184), .B0(DMP_EXP_EWSW[18]),
.B1(n1183), .Y(n1133) );
OAI21XLTS U1373 ( .A0(n1699), .A1(n1182), .B0(n1133), .Y(n816) );
AOI22X1TS U1374 ( .A0(n991), .A1(n1184), .B0(DMP_EXP_EWSW[10]), .B1(n1086),
.Y(n1134) );
AOI222X1TS U1375 ( .A0(n1135), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1086), .C0(intDY_EWSW[23]), .C1(n1184), .Y(n1136) );
INVX2TS U1376 ( .A(n1136), .Y(n645) );
AOI22X1TS U1377 ( .A0(intDX_EWSW[14]), .A1(n1184), .B0(DMP_EXP_EWSW[14]),
.B1(n1086), .Y(n1137) );
OAI21XLTS U1378 ( .A0(n1681), .A1(n1182), .B0(n1137), .Y(n820) );
AOI22X1TS U1379 ( .A0(intDX_EWSW[17]), .A1(n1184), .B0(DMP_EXP_EWSW[17]),
.B1(n1183), .Y(n1138) );
OAI21XLTS U1380 ( .A0(n1694), .A1(n1182), .B0(n1138), .Y(n817) );
AOI22X1TS U1381 ( .A0(intDX_EWSW[12]), .A1(n1184), .B0(DMP_EXP_EWSW[12]),
.B1(n1086), .Y(n1139) );
OAI21XLTS U1382 ( .A0(n1680), .A1(n1182), .B0(n1139), .Y(n822) );
OAI22X1TS U1383 ( .A0(n1692), .A1(intDX_EWSW[25]), .B0(n1691), .B1(
intDX_EWSW[26]), .Y(n1140) );
AOI221X1TS U1384 ( .A0(n1692), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1691), .C0(n1140), .Y(n1146) );
OAI22X1TS U1385 ( .A0(n1683), .A1(intDX_EWSW[27]), .B0(n1698), .B1(
intDY_EWSW[28]), .Y(n1141) );
OAI22X1TS U1386 ( .A0(n1685), .A1(intDY_EWSW[29]), .B0(n1644), .B1(
intDY_EWSW[30]), .Y(n1142) );
AOI221X1TS U1387 ( .A0(n1685), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1644), .C0(n1142), .Y(n1144) );
AOI2BB2XLTS U1388 ( .B0(intDX_EWSW[7]), .B1(n1684), .A0N(n1684), .A1N(
intDX_EWSW[7]), .Y(n1143) );
NAND4XLTS U1389 ( .A(n1146), .B(n1145), .C(n1144), .D(n1143), .Y(n1174) );
OAI22X1TS U1390 ( .A0(n1695), .A1(intDX_EWSW[1]), .B0(n1694), .B1(
intDX_EWSW[17]), .Y(n1147) );
OAI22X1TS U1391 ( .A0(n1682), .A1(intDX_EWSW[20]), .B0(n1677), .B1(
intDX_EWSW[21]), .Y(n1149) );
OAI22X1TS U1392 ( .A0(n1643), .A1(intDX_EWSW[22]), .B0(n1686), .B1(
intDX_EWSW[23]), .Y(n1150) );
NAND4XLTS U1393 ( .A(n1154), .B(n1153), .C(n1152), .D(n1151), .Y(n1173) );
OAI22X1TS U1394 ( .A0(n1629), .A1(intDX_EWSW[24]), .B0(n1675), .B1(
intDX_EWSW[9]), .Y(n1155) );
AOI221X1TS U1395 ( .A0(n1629), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1675), .C0(n1155), .Y(n1162) );
OAI22X1TS U1396 ( .A0(n1680), .A1(intDX_EWSW[12]), .B0(n1676), .B1(
intDX_EWSW[13]), .Y(n1157) );
OAI22X1TS U1397 ( .A0(n1681), .A1(intDX_EWSW[14]), .B0(n1752), .B1(
intDX_EWSW[15]), .Y(n1158) );
NAND4XLTS U1398 ( .A(n1162), .B(n1161), .C(n1160), .D(n1159), .Y(n1172) );
OAI22X1TS U1399 ( .A0(n1642), .A1(intDX_EWSW[16]), .B0(n1693), .B1(
intDX_EWSW[0]), .Y(n1163) );
AOI221X1TS U1400 ( .A0(n1642), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1693), .C0(n1163), .Y(n1170) );
OAI22X1TS U1401 ( .A0(n1678), .A1(n992), .B0(n1750), .B1(intDX_EWSW[3]), .Y(
n1164) );
OAI22X1TS U1402 ( .A0(n1679), .A1(intDX_EWSW[4]), .B0(n1641), .B1(
intDX_EWSW[5]), .Y(n1165) );
AOI221X1TS U1403 ( .A0(n1679), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1641), .C0(n1165), .Y(n1168) );
OAI22X1TS U1404 ( .A0(n1696), .A1(intDX_EWSW[8]), .B0(n1674), .B1(
intDX_EWSW[6]), .Y(n1166) );
NAND4XLTS U1405 ( .A(n1170), .B(n1169), .C(n1168), .D(n1167), .Y(n1171) );
NOR4X1TS U1406 ( .A(n1174), .B(n1173), .C(n1172), .D(n1171), .Y(n1402) );
CLKXOR2X2TS U1407 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1400) );
INVX2TS U1408 ( .A(n1400), .Y(n1178) );
AOI22X1TS U1409 ( .A0(intDX_EWSW[31]), .A1(n1176), .B0(SIGN_FLAG_EXP), .B1(
n1339), .Y(n1177) );
AOI22X1TS U1410 ( .A0(intDX_EWSW[11]), .A1(n1184), .B0(DMP_EXP_EWSW[11]),
.B1(n1183), .Y(n1179) );
OAI21XLTS U1411 ( .A0(n1751), .A1(n1182), .B0(n1179), .Y(n823) );
AOI22X1TS U1412 ( .A0(intDX_EWSW[13]), .A1(n1184), .B0(DMP_EXP_EWSW[13]),
.B1(n1086), .Y(n1180) );
OAI21XLTS U1413 ( .A0(n1676), .A1(n1182), .B0(n1180), .Y(n821) );
AOI22X1TS U1414 ( .A0(intDX_EWSW[15]), .A1(n1184), .B0(DMP_EXP_EWSW[15]),
.B1(n1086), .Y(n1181) );
OAI21XLTS U1415 ( .A0(n1752), .A1(n1182), .B0(n1181), .Y(n819) );
AOI22X1TS U1416 ( .A0(intDX_EWSW[21]), .A1(n1184), .B0(DMP_EXP_EWSW[21]),
.B1(n1183), .Y(n1185) );
OAI21XLTS U1417 ( .A0(n1677), .A1(n1408), .B0(n1185), .Y(n813) );
AOI2BB2XLTS U1418 ( .B0(beg_OP), .B1(n1640), .A0N(n1640), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1186) );
NAND3XLTS U1419 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1640), .C(
n1670), .Y(n1335) );
OAI21XLTS U1420 ( .A0(n1338), .A1(n1186), .B0(n1335), .Y(n951) );
NOR2BX1TS U1421 ( .AN(n1200), .B(Raw_mant_NRM_SWR[18]), .Y(n1316) );
NOR3X1TS U1422 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1317) );
CLKAND2X2TS U1423 ( .A(n1316), .B(n1317), .Y(n1315) );
NAND2X1TS U1424 ( .A(n1315), .B(n1633), .Y(n1187) );
NAND2X1TS U1425 ( .A(n1212), .B(n1634), .Y(n1199) );
NOR2X1TS U1426 ( .A(Raw_mant_NRM_SWR[10]), .B(n1199), .Y(n1205) );
NAND2X1TS U1427 ( .A(n1205), .B(n1653), .Y(n1191) );
NOR3X1TS U1428 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .C(n1191),
.Y(n1188) );
NAND2X1TS U1429 ( .A(n1188), .B(n1654), .Y(n1208) );
NOR2XLTS U1430 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1190)
);
NAND2X1TS U1431 ( .A(n1202), .B(n1635), .Y(n1326) );
OAI21XLTS U1432 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1188), .Y(n1189) );
OAI21X1TS U1433 ( .A0(n1190), .A1(n1326), .B0(n1189), .Y(n1218) );
NOR2XLTS U1434 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n1192)
);
NAND2BXLTS U1435 ( .AN(n1208), .B(Raw_mant_NRM_SWR[5]), .Y(n1327) );
OAI21XLTS U1436 ( .A0(n1192), .A1(n1191), .B0(n1327), .Y(n1193) );
NOR3X1TS U1437 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .C(n1326),
.Y(n1194) );
NAND2X1TS U1438 ( .A(n1194), .B(n988), .Y(n1204) );
NAND2X1TS U1439 ( .A(Raw_mant_NRM_SWR[1]), .B(n1194), .Y(n1319) );
AOI31X1TS U1440 ( .A0(n1195), .A1(n1204), .A2(n1319), .B0(n954), .Y(n1314)
);
NAND2X1TS U1441 ( .A(Raw_mant_NRM_SWR[14]), .B(n1315), .Y(n1220) );
AOI32X1TS U1442 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n961), .A2(n1627), .B0(
Raw_mant_NRM_SWR[22]), .B1(n961), .Y(n1197) );
AOI32X1TS U1443 ( .A0(n995), .A1(n1220), .A2(n1197), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1220), .Y(n1198) );
AOI31XLTS U1444 ( .A0(n1200), .A1(Raw_mant_NRM_SWR[16]), .A2(n1628), .B0(
n1198), .Y(n1207) );
OAI21XLTS U1445 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1657), .B0(n1635), .Y(n1201) );
NOR3X1TS U1446 ( .A(Raw_mant_NRM_SWR[12]), .B(n1656), .C(n1199), .Y(n1322)
);
AO21XLTS U1447 ( .A0(n1200), .A1(Raw_mant_NRM_SWR[18]), .B0(n1322), .Y(n1211) );
AOI21X1TS U1448 ( .A0(n1202), .A1(n1201), .B0(n1211), .Y(n1203) );
NAND2X1TS U1449 ( .A(Raw_mant_NRM_SWR[12]), .B(n1212), .Y(n1320) );
OAI211X1TS U1450 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1204), .B0(n1203), .C0(
n1320), .Y(n1330) );
NOR2XLTS U1451 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n1209) );
NOR2BX1TS U1452 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1237) );
AOI31XLTS U1453 ( .A0(n1653), .A1(Raw_mant_NRM_SWR[11]), .A2(n1212), .B0(
n1211), .Y(n1219) );
NOR2XLTS U1454 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1216) );
NOR2X1TS U1455 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1214) );
AOI21X1TS U1456 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n954), .B0(n1332), .Y(
n1222) );
NOR2X2TS U1457 ( .A(n1210), .B(n1222), .Y(n1373) );
NAND2X1TS U1458 ( .A(n1222), .B(n1379), .Y(n1223) );
INVX2TS U1459 ( .A(n1369), .Y(n1240) );
NAND2X2TS U1460 ( .A(n1226), .B(Shift_reg_FLAGS_7[1]), .Y(n1365) );
INVX2TS U1461 ( .A(n1365), .Y(n1352) );
AOI22X1TS U1462 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1352), .B0(n1362), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1225) );
AOI22X1TS U1463 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n955), .B0(n1363), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1224) );
NAND2X1TS U1464 ( .A(n1225), .B(n1224), .Y(n1254) );
AOI22X1TS U1465 ( .A0(n1210), .A1(Data_array_SWR[3]), .B0(n1240), .B1(n1254),
.Y(n1228) );
NAND2X1TS U1466 ( .A(n1332), .B(n1226), .Y(n1287) );
NAND2X1TS U1467 ( .A(Raw_mant_NRM_SWR[19]), .B(n1265), .Y(n1227) );
AOI22X1TS U1468 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1352), .B0(n1362), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1230) );
AOI22X1TS U1469 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n955), .B0(n1363), .B1(n986), .Y(n1229) );
NAND2X1TS U1470 ( .A(n1230), .B(n1229), .Y(n1372) );
AOI22X1TS U1471 ( .A0(n1210), .A1(Data_array_SWR[2]), .B0(n1240), .B1(n1372),
.Y(n1232) );
NAND2X1TS U1472 ( .A(Raw_mant_NRM_SWR[20]), .B(n1265), .Y(n1231) );
OAI211XLTS U1473 ( .A0(n1280), .A1(n1221), .B0(n1232), .C0(n1231), .Y(n854)
);
AOI22X1TS U1474 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1352), .B0(n1362), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1234) );
AOI22X1TS U1475 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n955), .B0(n1363), .B1(n985), .Y(n1233) );
NAND2X1TS U1476 ( .A(n1234), .B(n1233), .Y(n1273) );
AOI22X1TS U1477 ( .A0(n1210), .A1(Data_array_SWR[7]), .B0(n1240), .B1(n1273),
.Y(n1236) );
NAND2X1TS U1478 ( .A(Raw_mant_NRM_SWR[15]), .B(n1265), .Y(n1235) );
OAI211XLTS U1479 ( .A0(n1260), .A1(n1221), .B0(n1236), .C0(n1235), .Y(n859)
);
AOI22X1TS U1480 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1352), .B0(n1362), .B1(
n985), .Y(n1239) );
AOI22X1TS U1481 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n955), .B0(n1363), .B1(n979), .Y(n1238) );
NAND2X1TS U1482 ( .A(n1239), .B(n1238), .Y(n1277) );
AOI22X1TS U1483 ( .A0(n1210), .A1(Data_array_SWR[6]), .B0(n1240), .B1(n1277),
.Y(n1242) );
NAND2X1TS U1484 ( .A(Raw_mant_NRM_SWR[16]), .B(n1265), .Y(n1241) );
OAI211XLTS U1485 ( .A0(n1294), .A1(n1221), .B0(n1242), .C0(n1241), .Y(n858)
);
AOI22X1TS U1486 ( .A0(n1210), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1265), .Y(n1245) );
NAND2X1TS U1487 ( .A(n1243), .B(n1352), .Y(n1293) );
AOI2BB2XLTS U1488 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1371), .A0N(n1253),
.A1N(n1221), .Y(n1244) );
OAI211XLTS U1489 ( .A0(n1266), .A1(n1369), .B0(n1245), .C0(n1244), .Y(n865)
);
AOI22X1TS U1490 ( .A0(n1210), .A1(n989), .B0(Raw_mant_NRM_SWR[1]), .B1(n1265), .Y(n1247) );
AOI2BB2XLTS U1491 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1371), .A0N(n1270), .A1N(
n1221), .Y(n1246) );
OAI211XLTS U1492 ( .A0(n1261), .A1(n1369), .B0(n1247), .C0(n1246), .Y(n873)
);
AOI22X1TS U1493 ( .A0(n1210), .A1(n990), .B0(Raw_mant_NRM_SWR[5]), .B1(n1265), .Y(n1249) );
AOI2BB2XLTS U1494 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1371), .A0N(n1264), .A1N(
n1221), .Y(n1248) );
OAI211XLTS U1495 ( .A0(n1250), .A1(n1369), .B0(n1249), .C0(n1248), .Y(n869)
);
AOI22X1TS U1496 ( .A0(n1210), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1265), .Y(n1252) );
AOI2BB2XLTS U1497 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1371), .A0N(n1250), .A1N(
n1221), .Y(n1251) );
OAI211XLTS U1498 ( .A0(n1253), .A1(n1369), .B0(n1252), .C0(n1251), .Y(n867)
);
AOI22X1TS U1499 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n955), .B0(n1362), .B1(n986), .Y(n1257) );
AOI22X1TS U1500 ( .A0(n1210), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1371), .Y(n1256) );
NAND2X1TS U1501 ( .A(n1373), .B(n1254), .Y(n1255) );
OAI211XLTS U1502 ( .A0(n1257), .A1(n1369), .B0(n1256), .C0(n1255), .Y(n853)
);
AOI22X1TS U1503 ( .A0(n1210), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1265), .Y(n1259) );
AOI2BB2XLTS U1504 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1371), .A0N(n1269),
.A1N(n1221), .Y(n1258) );
OAI211XLTS U1505 ( .A0(n1260), .A1(n1369), .B0(n1259), .C0(n1258), .Y(n861)
);
AOI22X1TS U1506 ( .A0(n1210), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1265), .Y(n1263) );
AOI2BB2XLTS U1507 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1371), .A0N(n1261), .A1N(
n1221), .Y(n1262) );
OAI211XLTS U1508 ( .A0(n1264), .A1(n1369), .B0(n1263), .C0(n1262), .Y(n871)
);
AOI22X1TS U1509 ( .A0(n1210), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1265), .Y(n1268) );
AOI2BB2XLTS U1510 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1371), .A0N(n1266),
.A1N(n1221), .Y(n1267) );
AOI21X1TS U1511 ( .A0(n955), .A1(n988), .B0(n1363), .Y(n1350) );
OAI22X1TS U1512 ( .A0(n1270), .A1(n1369), .B0(n1379), .B1(n1646), .Y(n1271)
);
AOI21X1TS U1513 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1371), .B0(n1271), .Y(n1272) );
OAI21XLTS U1514 ( .A0(n1350), .A1(n1221), .B0(n1272), .Y(n875) );
AOI22X1TS U1515 ( .A0(n1210), .A1(Data_array_SWR[5]), .B0(n1373), .B1(n1273),
.Y(n1275) );
NAND2X1TS U1516 ( .A(Raw_mant_NRM_SWR[19]), .B(n1371), .Y(n1274) );
OAI211XLTS U1517 ( .A0(n1276), .A1(n1369), .B0(n1275), .C0(n1274), .Y(n857)
);
AOI22X1TS U1518 ( .A0(n1210), .A1(Data_array_SWR[4]), .B0(n1373), .B1(n1277),
.Y(n1279) );
NAND2X1TS U1519 ( .A(Raw_mant_NRM_SWR[20]), .B(n1371), .Y(n1278) );
OAI211XLTS U1520 ( .A0(n1280), .A1(n1369), .B0(n1279), .C0(n1278), .Y(n856)
);
AOI22X1TS U1521 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[18]), .B0(n1362), .B1(
n980), .Y(n1281) );
OAI21XLTS U1522 ( .A0(n1635), .A1(n1365), .B0(n1281), .Y(n1282) );
AOI21X1TS U1523 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n955), .B0(n1282), .Y(n1357)
);
OAI22X1TS U1524 ( .A0(n1288), .A1(n1369), .B0(n1659), .B1(n1293), .Y(n1283)
);
AOI21X1TS U1525 ( .A0(n1210), .A1(Data_array_SWR[17]), .B0(n1283), .Y(n1284)
);
OAI21XLTS U1526 ( .A0(n1357), .A1(n1221), .B0(n1284), .Y(n870) );
AOI22X1TS U1527 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1352), .B0(n1362), .B1(n981), .Y(n1285) );
OAI21XLTS U1528 ( .A0(n1664), .A1(n1354), .B0(n1285), .Y(n1286) );
AOI21X1TS U1529 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[14]), .B0(n1286), .Y(
n1361) );
OAI22X1TS U1530 ( .A0(n1288), .A1(n1221), .B0(n1659), .B1(n1287), .Y(n1289)
);
AOI21X1TS U1531 ( .A0(n1210), .A1(Data_array_SWR[16]), .B0(n1289), .Y(n1290)
);
OAI21XLTS U1532 ( .A0(n1361), .A1(n1369), .B0(n1290), .Y(n868) );
AOI22X1TS U1533 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[8]), .B0(n1362), .B1(n984), .Y(n1291) );
OAI21XLTS U1534 ( .A0(n1633), .A1(n1365), .B0(n1291), .Y(n1292) );
AOI21X1TS U1535 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n955), .B0(n1292), .Y(n1368) );
OAI22X1TS U1536 ( .A0(n1294), .A1(n1369), .B0(n1631), .B1(n1293), .Y(n1295)
);
AOI21X1TS U1537 ( .A0(n1210), .A1(Data_array_SWR[8]), .B0(n1295), .Y(n1296)
);
OAI21XLTS U1538 ( .A0(n1368), .A1(n1221), .B0(n1296), .Y(n860) );
INVX2TS U1539 ( .A(n1297), .Y(n1307) );
AND4X1TS U1540 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1298), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1299) );
NAND3XLTS U1541 ( .A(n1300), .B(exp_rslt_NRM2_EW1[4]), .C(n1299), .Y(n1301)
);
NAND2BXLTS U1542 ( .AN(n1301), .B(n1333), .Y(n1302) );
NOR2XLTS U1543 ( .A(n1307), .B(n1302), .Y(n1306) );
INVX2TS U1544 ( .A(n1303), .Y(n1304) );
CLKAND2X2TS U1545 ( .A(n1707), .B(n1304), .Y(n1305) );
OAI2BB2XLTS U1546 ( .B0(n1514), .B1(n1307), .A0N(final_result_ieee[30]),
.A1N(n1597), .Y(n835) );
INVX2TS U1547 ( .A(n1308), .Y(n1515) );
NOR2XLTS U1548 ( .A(n1515), .B(SIGN_FLAG_SHT1SHT2), .Y(n1309) );
OAI2BB2XLTS U1549 ( .B0(n1309), .B1(n1514), .A0N(n1597), .A1N(
final_result_ieee[31]), .Y(n624) );
AOI2BB2X1TS U1550 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1002), .A0N(n1002),
.A1N(DmP_mant_SFG_SWR[13]), .Y(n1310) );
AOI2BB2X1TS U1551 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1505), .A0N(n1505),
.A1N(DmP_mant_SFG_SWR[12]), .Y(n1424) );
NAND2BX1TS U1552 ( .AN(n1424), .B(DMP_SFG[10]), .Y(n1537) );
NAND2X1TS U1553 ( .A(n1310), .B(DMP_SFG[11]), .Y(n1524) );
OAI21X1TS U1554 ( .A0(n1525), .A1(n1537), .B0(n1524), .Y(n1311) );
INVX2TS U1555 ( .A(n1312), .Y(n1313) );
NAND2X1TS U1556 ( .A(n1662), .B(n1313), .Y(DP_OP_15J11_123_2691_n8) );
MX2X1TS U1557 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n692) );
MX2X1TS U1558 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n697) );
MX2X1TS U1559 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n702) );
MX2X1TS U1560 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n707) );
MX2X1TS U1561 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n712) );
MX2X1TS U1562 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n717) );
MX2X1TS U1563 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n722) );
MX2X1TS U1564 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n727) );
AO21XLTS U1565 ( .A0(LZD_output_NRM2_EW[4]), .A1(n954), .B0(n1314), .Y(n610)
);
OAI211X1TS U1566 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1315), .C0(n1633), .Y(n1323) );
OAI2BB1X1TS U1567 ( .A0N(n1317), .A1N(n1633), .B0(n1316), .Y(n1318) );
NAND4XLTS U1568 ( .A(n1320), .B(n1323), .C(n1319), .D(n1318), .Y(n1321) );
OAI21X1TS U1569 ( .A0(n1322), .A1(n1321), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1380) );
OAI2BB1X1TS U1570 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n954), .B0(n1380), .Y(
n598) );
OAI21XLTS U1571 ( .A0(n1325), .A1(n1324), .B0(n1323), .Y(n1331) );
OAI22X1TS U1572 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1327), .B0(n1326), .B1(
n1700), .Y(n1329) );
OAI31X1TS U1573 ( .A0(n1331), .A1(n1330), .A2(n1329), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1376) );
OAI2BB1X1TS U1574 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n954), .B0(n1376), .Y(
n607) );
AO21XLTS U1575 ( .A0(LZD_output_NRM2_EW[1]), .A1(n954), .B0(n1332), .Y(n604)
);
OAI2BB1X1TS U1576 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n954), .B0(n1365), .Y(
n593) );
OA22X1TS U1577 ( .A0(n1334), .A1(n1333), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n836) );
OA21XLTS U1578 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1514),
.Y(n639) );
INVX2TS U1579 ( .A(n1338), .Y(n1336) );
AOI22X1TS U1580 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1336), .B1(n1640), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1581 ( .A(n1336), .B(n1335), .Y(n952) );
NOR2XLTS U1582 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1337) );
AOI32X4TS U1583 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1337), .B1(n1670), .Y(n1341)
);
INVX2TS U1584 ( .A(n1341), .Y(n1340) );
AOI22X1TS U1585 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1338), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1640), .Y(n1342) );
AO22XLTS U1586 ( .A0(n1340), .A1(Shift_reg_FLAGS_7_6), .B0(n1341), .B1(n1342), .Y(n950) );
AOI22X1TS U1587 ( .A0(n1341), .A1(n1339), .B0(n1415), .B1(n1340), .Y(n949)
);
AOI22X1TS U1588 ( .A0(n1341), .A1(n1413), .B0(n1404), .B1(n1340), .Y(n948)
);
AOI22X1TS U1589 ( .A0(n1341), .A1(n1748), .B0(n954), .B1(n1340), .Y(n945) );
AOI22X1TS U1590 ( .A0(n1341), .A1(n954), .B0(n1597), .B1(n1340), .Y(n944) );
AO22XLTS U1591 ( .A0(n1345), .A1(Data_X[0]), .B0(n1347), .B1(intDX_EWSW[0]),
.Y(n943) );
AO22XLTS U1592 ( .A0(n1344), .A1(Data_X[1]), .B0(n1343), .B1(intDX_EWSW[1]),
.Y(n942) );
AO22XLTS U1593 ( .A0(n1344), .A1(Data_X[2]), .B0(n1343), .B1(n992), .Y(n941)
);
AO22XLTS U1594 ( .A0(n1349), .A1(Data_X[3]), .B0(n1343), .B1(intDX_EWSW[3]),
.Y(n940) );
AO22XLTS U1595 ( .A0(n1349), .A1(Data_X[4]), .B0(n1347), .B1(intDX_EWSW[4]),
.Y(n939) );
AO22XLTS U1596 ( .A0(n1344), .A1(Data_X[5]), .B0(n1343), .B1(intDX_EWSW[5]),
.Y(n938) );
AO22XLTS U1597 ( .A0(n1345), .A1(Data_X[6]), .B0(n1343), .B1(intDX_EWSW[6]),
.Y(n937) );
AO22XLTS U1598 ( .A0(n1345), .A1(Data_X[7]), .B0(n1343), .B1(intDX_EWSW[7]),
.Y(n936) );
AO22XLTS U1599 ( .A0(n1349), .A1(Data_X[8]), .B0(n1347), .B1(intDX_EWSW[8]),
.Y(n935) );
AO22XLTS U1600 ( .A0(n1344), .A1(Data_X[9]), .B0(n1343), .B1(intDX_EWSW[9]),
.Y(n934) );
AO22XLTS U1601 ( .A0(n1345), .A1(Data_X[10]), .B0(n1347), .B1(n991), .Y(n933) );
AO22XLTS U1602 ( .A0(n1344), .A1(Data_X[11]), .B0(n1347), .B1(intDX_EWSW[11]), .Y(n932) );
AO22XLTS U1603 ( .A0(n1345), .A1(Data_X[12]), .B0(n1348), .B1(intDX_EWSW[12]), .Y(n931) );
AO22XLTS U1604 ( .A0(n1344), .A1(Data_X[13]), .B0(n1348), .B1(intDX_EWSW[13]), .Y(n930) );
AO22XLTS U1605 ( .A0(n1344), .A1(Data_X[14]), .B0(n1348), .B1(intDX_EWSW[14]), .Y(n929) );
AO22XLTS U1606 ( .A0(n1349), .A1(Data_X[15]), .B0(n1348), .B1(intDX_EWSW[15]), .Y(n928) );
AO22XLTS U1607 ( .A0(n1344), .A1(Data_X[16]), .B0(n1348), .B1(intDX_EWSW[16]), .Y(n927) );
AO22XLTS U1608 ( .A0(n1345), .A1(Data_X[17]), .B0(n1348), .B1(intDX_EWSW[17]), .Y(n926) );
AO22XLTS U1609 ( .A0(n1345), .A1(Data_X[18]), .B0(n1348), .B1(intDX_EWSW[18]), .Y(n925) );
AO22XLTS U1610 ( .A0(n1345), .A1(Data_X[19]), .B0(n1348), .B1(intDX_EWSW[19]), .Y(n924) );
AO22XLTS U1611 ( .A0(n1345), .A1(Data_X[20]), .B0(n1348), .B1(intDX_EWSW[20]), .Y(n923) );
AO22XLTS U1612 ( .A0(n1349), .A1(Data_X[21]), .B0(n1348), .B1(intDX_EWSW[21]), .Y(n922) );
AO22XLTS U1613 ( .A0(n1349), .A1(Data_X[22]), .B0(n1348), .B1(intDX_EWSW[22]), .Y(n921) );
AO22XLTS U1614 ( .A0(n1345), .A1(Data_X[23]), .B0(n1348), .B1(intDX_EWSW[23]), .Y(n920) );
AO22XLTS U1615 ( .A0(n1343), .A1(intDX_EWSW[24]), .B0(n1004), .B1(Data_X[24]), .Y(n919) );
AO22XLTS U1616 ( .A0(n1343), .A1(intDX_EWSW[25]), .B0(n1345), .B1(Data_X[25]), .Y(n918) );
AO22XLTS U1617 ( .A0(n1347), .A1(intDX_EWSW[26]), .B0(n1349), .B1(Data_X[26]), .Y(n917) );
AO22XLTS U1618 ( .A0(n1349), .A1(Data_X[27]), .B0(n1343), .B1(intDX_EWSW[27]), .Y(n916) );
AO22XLTS U1619 ( .A0(n1343), .A1(intDX_EWSW[28]), .B0(n1349), .B1(Data_X[28]), .Y(n915) );
AO22XLTS U1620 ( .A0(n1343), .A1(intDX_EWSW[29]), .B0(n1349), .B1(Data_X[29]), .Y(n914) );
AO22XLTS U1621 ( .A0(n1347), .A1(intDX_EWSW[30]), .B0(n1344), .B1(Data_X[30]), .Y(n913) );
AO22XLTS U1622 ( .A0(n1349), .A1(add_subt), .B0(n1347), .B1(intAS), .Y(n911)
);
AO22XLTS U1623 ( .A0(n1343), .A1(intDY_EWSW[0]), .B0(n1345), .B1(Data_Y[0]),
.Y(n909) );
AO22XLTS U1624 ( .A0(n1343), .A1(intDY_EWSW[1]), .B0(n1344), .B1(Data_Y[1]),
.Y(n908) );
AO22XLTS U1625 ( .A0(n1343), .A1(intDY_EWSW[2]), .B0(n1345), .B1(Data_Y[2]),
.Y(n907) );
AO22XLTS U1626 ( .A0(n1347), .A1(intDY_EWSW[3]), .B0(n1345), .B1(Data_Y[3]),
.Y(n906) );
INVX4TS U1627 ( .A(n1004), .Y(n1346) );
AO22XLTS U1628 ( .A0(n1346), .A1(intDY_EWSW[4]), .B0(n1349), .B1(Data_Y[4]),
.Y(n905) );
AO22XLTS U1629 ( .A0(n1346), .A1(intDY_EWSW[5]), .B0(n1344), .B1(Data_Y[5]),
.Y(n904) );
AO22XLTS U1630 ( .A0(n1347), .A1(intDY_EWSW[6]), .B0(n1345), .B1(Data_Y[6]),
.Y(n903) );
AO22XLTS U1631 ( .A0(n1343), .A1(intDY_EWSW[7]), .B0(n1004), .B1(Data_Y[7]),
.Y(n902) );
AO22XLTS U1632 ( .A0(n1346), .A1(intDY_EWSW[8]), .B0(n1344), .B1(Data_Y[8]),
.Y(n901) );
AO22XLTS U1633 ( .A0(n1343), .A1(intDY_EWSW[9]), .B0(n1344), .B1(Data_Y[9]),
.Y(n900) );
AO22XLTS U1634 ( .A0(n1347), .A1(intDY_EWSW[10]), .B0(n1004), .B1(Data_Y[10]), .Y(n899) );
AO22XLTS U1635 ( .A0(n1343), .A1(intDY_EWSW[11]), .B0(n1344), .B1(Data_Y[11]), .Y(n898) );
AO22XLTS U1636 ( .A0(n1346), .A1(intDY_EWSW[12]), .B0(n1345), .B1(Data_Y[12]), .Y(n897) );
AO22XLTS U1637 ( .A0(n1346), .A1(intDY_EWSW[13]), .B0(n1344), .B1(Data_Y[13]), .Y(n896) );
AO22XLTS U1638 ( .A0(n1346), .A1(intDY_EWSW[14]), .B0(n1349), .B1(Data_Y[14]), .Y(n895) );
AO22XLTS U1639 ( .A0(n1343), .A1(intDY_EWSW[15]), .B0(n1345), .B1(Data_Y[15]), .Y(n894) );
AO22XLTS U1640 ( .A0(n1346), .A1(intDY_EWSW[16]), .B0(n1004), .B1(Data_Y[16]), .Y(n893) );
AO22XLTS U1641 ( .A0(n1346), .A1(intDY_EWSW[17]), .B0(n1345), .B1(Data_Y[17]), .Y(n892) );
AO22XLTS U1642 ( .A0(n1346), .A1(intDY_EWSW[18]), .B0(n1349), .B1(Data_Y[18]), .Y(n891) );
AO22XLTS U1643 ( .A0(n1346), .A1(intDY_EWSW[19]), .B0(n1004), .B1(Data_Y[19]), .Y(n890) );
AO22XLTS U1644 ( .A0(n1346), .A1(intDY_EWSW[20]), .B0(n1345), .B1(Data_Y[20]), .Y(n889) );
AO22XLTS U1645 ( .A0(n1346), .A1(intDY_EWSW[21]), .B0(n1349), .B1(Data_Y[21]), .Y(n888) );
AO22XLTS U1646 ( .A0(n1346), .A1(intDY_EWSW[22]), .B0(n1344), .B1(Data_Y[22]), .Y(n887) );
AO22XLTS U1647 ( .A0(n1346), .A1(intDY_EWSW[23]), .B0(n1345), .B1(Data_Y[23]), .Y(n886) );
AO22XLTS U1648 ( .A0(n1346), .A1(intDY_EWSW[24]), .B0(n1349), .B1(Data_Y[24]), .Y(n885) );
AO22XLTS U1649 ( .A0(n1346), .A1(intDY_EWSW[25]), .B0(n1349), .B1(Data_Y[25]), .Y(n884) );
AO22XLTS U1650 ( .A0(n1346), .A1(intDY_EWSW[26]), .B0(n1344), .B1(Data_Y[26]), .Y(n883) );
AO22XLTS U1651 ( .A0(n1346), .A1(intDY_EWSW[27]), .B0(n1345), .B1(Data_Y[27]), .Y(n882) );
AO22XLTS U1652 ( .A0(n1345), .A1(Data_Y[28]), .B0(n1343), .B1(intDY_EWSW[28]), .Y(n881) );
AO22XLTS U1653 ( .A0(n1345), .A1(Data_Y[29]), .B0(n1343), .B1(intDY_EWSW[29]), .Y(n880) );
AO22XLTS U1654 ( .A0(n1344), .A1(Data_Y[30]), .B0(n1343), .B1(intDY_EWSW[30]), .Y(n879) );
AO22XLTS U1655 ( .A0(n1349), .A1(Data_Y[31]), .B0(n1347), .B1(intDY_EWSW[31]), .Y(n878) );
OAI2BB2XLTS U1656 ( .B0(n1350), .B1(n1369), .A0N(n1210), .A1N(
Data_array_SWR[23]), .Y(n877) );
AO22XLTS U1657 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n955), .B0(n988), .B1(n1352),
.Y(n1351) );
OAI2BB2XLTS U1658 ( .B0(n1356), .B1(n1369), .A0N(n1210), .A1N(
Data_array_SWR[22]), .Y(n876) );
AOI22X1TS U1659 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1352), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1362), .Y(n1353) );
OAI21XLTS U1660 ( .A0(n1700), .A1(n1354), .B0(n1353), .Y(n1355) );
AOI21X1TS U1661 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n1363), .B0(n1355), .Y(
n1358) );
OAI222X1TS U1662 ( .A0(n1379), .A1(n1630), .B0(n1221), .B1(n1356), .C0(n1369), .C1(n1358), .Y(n874) );
OAI222X1TS U1663 ( .A0(n1715), .A1(n1379), .B0(n1221), .B1(n1358), .C0(n1369), .C1(n1357), .Y(n872) );
AOI22X1TS U1664 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[12]), .B0(n1362), .B1(
n982), .Y(n1359) );
OAI21XLTS U1665 ( .A0(n1656), .A1(n1365), .B0(n1359), .Y(n1360) );
AOI21X1TS U1666 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n955), .B0(n1360), .Y(n1367) );
OAI222X1TS U1667 ( .A0(n1649), .A1(n1379), .B0(n1221), .B1(n1361), .C0(n1369), .C1(n1367), .Y(n866) );
AOI22X1TS U1668 ( .A0(n1363), .A1(DmP_mant_SHT1_SW[10]), .B0(n1362), .B1(
n983), .Y(n1364) );
OAI21XLTS U1669 ( .A0(n1653), .A1(n1365), .B0(n1364), .Y(n1366) );
AOI21X1TS U1670 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n955), .B0(n1366), .Y(n1370) );
OAI222X1TS U1671 ( .A0(n1711), .A1(n1379), .B0(n1221), .B1(n1367), .C0(n1369), .C1(n1370), .Y(n864) );
OAI222X1TS U1672 ( .A0(n1704), .A1(n1379), .B0(n1221), .B1(n1370), .C0(n1369), .C1(n1368), .Y(n862) );
AOI22X1TS U1673 ( .A0(n1210), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1371), .Y(n1375) );
AOI22X1TS U1674 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n955), .B0(n1373), .B1(
n1372), .Y(n1374) );
NAND2X1TS U1675 ( .A(n1375), .B(n1374), .Y(n852) );
AOI32X1TS U1676 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1379), .A2(n954), .B0(
shift_value_SHT2_EWR[2]), .B1(n1210), .Y(n1377) );
NAND2X1TS U1677 ( .A(n1377), .B(n1376), .Y(n851) );
AOI32X1TS U1678 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1379), .A2(n954), .B0(
shift_value_SHT2_EWR[3]), .B1(n1210), .Y(n1381) );
NAND2X1TS U1679 ( .A(n1381), .B(n1380), .Y(n850) );
INVX4TS U1680 ( .A(n1405), .Y(n1411) );
CLKINVX1TS U1681 ( .A(DmP_EXP_EWSW[23]), .Y(n1382) );
AOI21X1TS U1682 ( .A0(DMP_EXP_EWSW[23]), .A1(n1382), .B0(n1387), .Y(n1383)
);
AOI2BB2XLTS U1683 ( .B0(n1411), .B1(n1383), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1632), .Y(n847) );
NOR2X1TS U1684 ( .A(n1647), .B(DMP_EXP_EWSW[24]), .Y(n1386) );
AOI21X1TS U1685 ( .A0(DMP_EXP_EWSW[24]), .A1(n1647), .B0(n1386), .Y(n1384)
);
XNOR2X1TS U1686 ( .A(n1387), .B(n1384), .Y(n1385) );
AO22XLTS U1687 ( .A0(n1632), .A1(n1385), .B0(n1413), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n846) );
OAI22X1TS U1688 ( .A0(n1387), .A1(n1386), .B0(DmP_EXP_EWSW[24]), .B1(n1648),
.Y(n1390) );
NAND2X1TS U1689 ( .A(DmP_EXP_EWSW[25]), .B(n1706), .Y(n1391) );
OAI21XLTS U1690 ( .A0(DmP_EXP_EWSW[25]), .A1(n1706), .B0(n1391), .Y(n1388)
);
XNOR2X1TS U1691 ( .A(n1390), .B(n1388), .Y(n1389) );
AO22XLTS U1692 ( .A0(n1632), .A1(n1389), .B0(n1415), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n845) );
AOI22X1TS U1693 ( .A0(DMP_EXP_EWSW[25]), .A1(n1714), .B0(n1391), .B1(n1390),
.Y(n1394) );
NOR2X1TS U1694 ( .A(n1710), .B(DMP_EXP_EWSW[26]), .Y(n1395) );
AOI21X1TS U1695 ( .A0(DMP_EXP_EWSW[26]), .A1(n1710), .B0(n1395), .Y(n1392)
);
XNOR2X1TS U1696 ( .A(n1394), .B(n1392), .Y(n1393) );
AO22XLTS U1697 ( .A0(n1632), .A1(n1393), .B0(n1405), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n844) );
OAI22X1TS U1698 ( .A0(n1395), .A1(n1394), .B0(DmP_EXP_EWSW[26]), .B1(n1713),
.Y(n1397) );
XNOR2X1TS U1699 ( .A(DmP_EXP_EWSW[27]), .B(n987), .Y(n1396) );
XOR2XLTS U1700 ( .A(n1397), .B(n1396), .Y(n1398) );
AO22XLTS U1701 ( .A0(n1632), .A1(n1398), .B0(n1415), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n843) );
OAI222X1TS U1702 ( .A0(n1175), .A1(n1712), .B0(n1648), .B1(
Shift_reg_FLAGS_7_6), .C0(n1629), .C1(n1408), .Y(n810) );
OAI222X1TS U1703 ( .A0(n1406), .A1(n1651), .B0(n1706), .B1(
Shift_reg_FLAGS_7_6), .C0(n1692), .C1(n1408), .Y(n809) );
OAI222X1TS U1704 ( .A0(n1175), .A1(n1652), .B0(n1713), .B1(
Shift_reg_FLAGS_7_6), .C0(n1691), .C1(n1408), .Y(n808) );
OAI21XLTS U1705 ( .A0(n1400), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1399) );
AOI21X1TS U1706 ( .A0(n1400), .A1(intDX_EWSW[31]), .B0(n1399), .Y(n1401) );
AO21XLTS U1707 ( .A0(OP_FLAG_EXP), .A1(n1086), .B0(n1401), .Y(n803) );
AO22XLTS U1708 ( .A0(n1402), .A1(n1401), .B0(ZERO_FLAG_EXP), .B1(n1086), .Y(
n802) );
AO22XLTS U1709 ( .A0(n1632), .A1(DMP_EXP_EWSW[0]), .B0(n1415), .B1(
DMP_SHT1_EWSW[0]), .Y(n800) );
AO22XLTS U1710 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1404), .B1(
DMP_SHT2_EWSW[0]), .Y(n799) );
NAND2X1TS U1711 ( .A(n978), .B(n1597), .Y(n1403) );
INVX4TS U1712 ( .A(n1617), .Y(n1521) );
AO22XLTS U1713 ( .A0(n1632), .A1(DMP_EXP_EWSW[1]), .B0(n1413), .B1(
DMP_SHT1_EWSW[1]), .Y(n797) );
AO22XLTS U1714 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1404), .B1(
DMP_SHT2_EWSW[1]), .Y(n796) );
INVX4TS U1715 ( .A(n1617), .Y(n1616) );
AO22XLTS U1716 ( .A0(n1632), .A1(DMP_EXP_EWSW[2]), .B0(n1405), .B1(
DMP_SHT1_EWSW[2]), .Y(n794) );
AO22XLTS U1717 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1404), .B1(
DMP_SHT2_EWSW[2]), .Y(n793) );
AO22XLTS U1718 ( .A0(n1414), .A1(DMP_EXP_EWSW[3]), .B0(n1413), .B1(
DMP_SHT1_EWSW[3]), .Y(n791) );
AO22XLTS U1719 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1404), .B1(
DMP_SHT2_EWSW[3]), .Y(n790) );
AO22XLTS U1720 ( .A0(n1414), .A1(DMP_EXP_EWSW[4]), .B0(n1415), .B1(
DMP_SHT1_EWSW[4]), .Y(n788) );
AO22XLTS U1721 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1404), .B1(
DMP_SHT2_EWSW[4]), .Y(n787) );
AO22XLTS U1722 ( .A0(n1414), .A1(DMP_EXP_EWSW[5]), .B0(n1413), .B1(
DMP_SHT1_EWSW[5]), .Y(n785) );
AO22XLTS U1723 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1404), .B1(
DMP_SHT2_EWSW[5]), .Y(n784) );
AO22XLTS U1724 ( .A0(n1414), .A1(DMP_EXP_EWSW[6]), .B0(n1405), .B1(
DMP_SHT1_EWSW[6]), .Y(n782) );
AO22XLTS U1725 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1404), .B1(
DMP_SHT2_EWSW[6]), .Y(n781) );
AO22XLTS U1726 ( .A0(n1414), .A1(DMP_EXP_EWSW[7]), .B0(n1415), .B1(
DMP_SHT1_EWSW[7]), .Y(n779) );
AO22XLTS U1727 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1404), .B1(
DMP_SHT2_EWSW[7]), .Y(n778) );
AO22XLTS U1728 ( .A0(n1624), .A1(DMP_SHT2_EWSW[7]), .B0(n1618), .B1(
DMP_SFG[7]), .Y(n777) );
AO22XLTS U1729 ( .A0(n1414), .A1(DMP_EXP_EWSW[8]), .B0(n1413), .B1(
DMP_SHT1_EWSW[8]), .Y(n776) );
AO22XLTS U1730 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1404), .B1(
DMP_SHT2_EWSW[8]), .Y(n775) );
AO22XLTS U1731 ( .A0(n1414), .A1(DMP_EXP_EWSW[9]), .B0(n1413), .B1(
DMP_SHT1_EWSW[9]), .Y(n773) );
AO22XLTS U1732 ( .A0(n1417), .A1(DMP_SHT1_EWSW[9]), .B0(n1404), .B1(
DMP_SHT2_EWSW[9]), .Y(n772) );
AO22XLTS U1733 ( .A0(n1414), .A1(DMP_EXP_EWSW[10]), .B0(n1415), .B1(
DMP_SHT1_EWSW[10]), .Y(n770) );
BUFX4TS U1734 ( .A(n1404), .Y(n1412) );
AO22XLTS U1735 ( .A0(n1417), .A1(DMP_SHT1_EWSW[10]), .B0(n1412), .B1(
DMP_SHT2_EWSW[10]), .Y(n769) );
BUFX4TS U1736 ( .A(n1716), .Y(n1415) );
AO22XLTS U1737 ( .A0(n1414), .A1(DMP_EXP_EWSW[11]), .B0(n1716), .B1(
DMP_SHT1_EWSW[11]), .Y(n767) );
AO22XLTS U1738 ( .A0(n1417), .A1(DMP_SHT1_EWSW[11]), .B0(n1412), .B1(
DMP_SHT2_EWSW[11]), .Y(n766) );
AO22XLTS U1739 ( .A0(n1414), .A1(DMP_EXP_EWSW[12]), .B0(n1413), .B1(
DMP_SHT1_EWSW[12]), .Y(n764) );
AO22XLTS U1740 ( .A0(n1417), .A1(DMP_SHT1_EWSW[12]), .B0(n1412), .B1(
DMP_SHT2_EWSW[12]), .Y(n763) );
AO22XLTS U1741 ( .A0(n1414), .A1(DMP_EXP_EWSW[13]), .B0(n1415), .B1(
DMP_SHT1_EWSW[13]), .Y(n761) );
AO22XLTS U1742 ( .A0(n1417), .A1(DMP_SHT1_EWSW[13]), .B0(n1412), .B1(
DMP_SHT2_EWSW[13]), .Y(n760) );
AO22XLTS U1743 ( .A0(n1617), .A1(DMP_SFG[13]), .B0(n1616), .B1(
DMP_SHT2_EWSW[13]), .Y(n759) );
AO22XLTS U1744 ( .A0(n1414), .A1(DMP_EXP_EWSW[14]), .B0(n1413), .B1(
DMP_SHT1_EWSW[14]), .Y(n758) );
AO22XLTS U1745 ( .A0(n1417), .A1(DMP_SHT1_EWSW[14]), .B0(n1412), .B1(
DMP_SHT2_EWSW[14]), .Y(n757) );
AO22XLTS U1746 ( .A0(n1617), .A1(DMP_SFG[14]), .B0(n1616), .B1(
DMP_SHT2_EWSW[14]), .Y(n756) );
AO22XLTS U1747 ( .A0(n1414), .A1(DMP_EXP_EWSW[15]), .B0(n1716), .B1(
DMP_SHT1_EWSW[15]), .Y(n755) );
AO22XLTS U1748 ( .A0(n1417), .A1(DMP_SHT1_EWSW[15]), .B0(n1412), .B1(
DMP_SHT2_EWSW[15]), .Y(n754) );
AO22XLTS U1749 ( .A0(n1617), .A1(DMP_SFG[15]), .B0(n1616), .B1(
DMP_SHT2_EWSW[15]), .Y(n753) );
AO22XLTS U1750 ( .A0(n1414), .A1(DMP_EXP_EWSW[16]), .B0(n1413), .B1(
DMP_SHT1_EWSW[16]), .Y(n752) );
AO22XLTS U1751 ( .A0(n1417), .A1(DMP_SHT1_EWSW[16]), .B0(n1412), .B1(
DMP_SHT2_EWSW[16]), .Y(n751) );
AO22XLTS U1752 ( .A0(n1617), .A1(DMP_SFG[16]), .B0(n1521), .B1(
DMP_SHT2_EWSW[16]), .Y(n750) );
INVX4TS U1753 ( .A(n1405), .Y(n1416) );
AO22XLTS U1754 ( .A0(n1416), .A1(DMP_EXP_EWSW[17]), .B0(n1415), .B1(
DMP_SHT1_EWSW[17]), .Y(n749) );
AO22XLTS U1755 ( .A0(n1417), .A1(DMP_SHT1_EWSW[17]), .B0(n1412), .B1(
DMP_SHT2_EWSW[17]), .Y(n748) );
AO22XLTS U1756 ( .A0(n1617), .A1(DMP_SFG[17]), .B0(n1616), .B1(
DMP_SHT2_EWSW[17]), .Y(n747) );
AO22XLTS U1757 ( .A0(n1416), .A1(DMP_EXP_EWSW[18]), .B0(n1413), .B1(
DMP_SHT1_EWSW[18]), .Y(n746) );
AO22XLTS U1758 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1412), .B1(
DMP_SHT2_EWSW[18]), .Y(n745) );
AO22XLTS U1759 ( .A0(n1617), .A1(DMP_SFG[18]), .B0(n1521), .B1(
DMP_SHT2_EWSW[18]), .Y(n744) );
BUFX4TS U1760 ( .A(n1716), .Y(n1405) );
AO22XLTS U1761 ( .A0(n1416), .A1(DMP_EXP_EWSW[19]), .B0(n1415), .B1(
DMP_SHT1_EWSW[19]), .Y(n743) );
AO22XLTS U1762 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1412), .B1(
DMP_SHT2_EWSW[19]), .Y(n742) );
AO22XLTS U1763 ( .A0(n1617), .A1(DMP_SFG[19]), .B0(n1521), .B1(
DMP_SHT2_EWSW[19]), .Y(n741) );
AO22XLTS U1764 ( .A0(n1416), .A1(DMP_EXP_EWSW[20]), .B0(n1405), .B1(
DMP_SHT1_EWSW[20]), .Y(n740) );
AO22XLTS U1765 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1412), .B1(
DMP_SHT2_EWSW[20]), .Y(n739) );
AO22XLTS U1766 ( .A0(n1617), .A1(DMP_SFG[20]), .B0(n1616), .B1(
DMP_SHT2_EWSW[20]), .Y(n738) );
AO22XLTS U1767 ( .A0(n1416), .A1(DMP_EXP_EWSW[21]), .B0(n1415), .B1(
DMP_SHT1_EWSW[21]), .Y(n737) );
AO22XLTS U1768 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1412), .B1(
DMP_SHT2_EWSW[21]), .Y(n736) );
AO22XLTS U1769 ( .A0(n1617), .A1(DMP_SFG[21]), .B0(n1616), .B1(
DMP_SHT2_EWSW[21]), .Y(n735) );
AO22XLTS U1770 ( .A0(n1416), .A1(DMP_EXP_EWSW[22]), .B0(n1415), .B1(
DMP_SHT1_EWSW[22]), .Y(n734) );
AO22XLTS U1771 ( .A0(n1417), .A1(DMP_SHT1_EWSW[22]), .B0(n1719), .B1(
DMP_SHT2_EWSW[22]), .Y(n733) );
AO22XLTS U1772 ( .A0(n1617), .A1(DMP_SFG[22]), .B0(n1521), .B1(
DMP_SHT2_EWSW[22]), .Y(n732) );
AO22XLTS U1773 ( .A0(n1416), .A1(DMP_EXP_EWSW[23]), .B0(n1413), .B1(
DMP_SHT1_EWSW[23]), .Y(n731) );
AO22XLTS U1774 ( .A0(n1417), .A1(DMP_SHT1_EWSW[23]), .B0(n1404), .B1(
DMP_SHT2_EWSW[23]), .Y(n730) );
BUFX3TS U1775 ( .A(n1617), .Y(n1520) );
AO22XLTS U1776 ( .A0(n1624), .A1(DMP_SHT2_EWSW[23]), .B0(n1520), .B1(
DMP_SFG[23]), .Y(n729) );
AO22XLTS U1777 ( .A0(n1477), .A1(DMP_SFG[23]), .B0(n1562), .B1(
DMP_exp_NRM_EW[0]), .Y(n728) );
AO22XLTS U1778 ( .A0(n1416), .A1(DMP_EXP_EWSW[24]), .B0(n1405), .B1(
DMP_SHT1_EWSW[24]), .Y(n726) );
AO22XLTS U1779 ( .A0(n1417), .A1(DMP_SHT1_EWSW[24]), .B0(n1412), .B1(
DMP_SHT2_EWSW[24]), .Y(n725) );
AO22XLTS U1780 ( .A0(n1521), .A1(DMP_SHT2_EWSW[24]), .B0(n1617), .B1(
DMP_SFG[24]), .Y(n724) );
AO22XLTS U1781 ( .A0(n1477), .A1(DMP_SFG[24]), .B0(n1562), .B1(
DMP_exp_NRM_EW[1]), .Y(n723) );
AO22XLTS U1782 ( .A0(n1416), .A1(DMP_EXP_EWSW[25]), .B0(n1413), .B1(
DMP_SHT1_EWSW[25]), .Y(n721) );
AO22XLTS U1783 ( .A0(n1417), .A1(DMP_SHT1_EWSW[25]), .B0(n1412), .B1(
DMP_SHT2_EWSW[25]), .Y(n720) );
AO22XLTS U1784 ( .A0(n1624), .A1(DMP_SHT2_EWSW[25]), .B0(n1617), .B1(
DMP_SFG[25]), .Y(n719) );
AO22XLTS U1785 ( .A0(n1477), .A1(DMP_SFG[25]), .B0(n1562), .B1(
DMP_exp_NRM_EW[2]), .Y(n718) );
AO22XLTS U1786 ( .A0(n1416), .A1(DMP_EXP_EWSW[26]), .B0(n1415), .B1(
DMP_SHT1_EWSW[26]), .Y(n716) );
AO22XLTS U1787 ( .A0(n1417), .A1(DMP_SHT1_EWSW[26]), .B0(n1412), .B1(
DMP_SHT2_EWSW[26]), .Y(n715) );
AO22XLTS U1788 ( .A0(n1521), .A1(DMP_SHT2_EWSW[26]), .B0(n1520), .B1(
DMP_SFG[26]), .Y(n714) );
AO22XLTS U1789 ( .A0(n1477), .A1(DMP_SFG[26]), .B0(n1562), .B1(
DMP_exp_NRM_EW[3]), .Y(n713) );
AO22XLTS U1790 ( .A0(n1416), .A1(n987), .B0(n1413), .B1(DMP_SHT1_EWSW[27]),
.Y(n711) );
AO22XLTS U1791 ( .A0(n1417), .A1(DMP_SHT1_EWSW[27]), .B0(n1412), .B1(
DMP_SHT2_EWSW[27]), .Y(n710) );
AO22XLTS U1792 ( .A0(n1624), .A1(DMP_SHT2_EWSW[27]), .B0(n1520), .B1(
DMP_SFG[27]), .Y(n709) );
AO22XLTS U1793 ( .A0(n1477), .A1(DMP_SFG[27]), .B0(n1562), .B1(
DMP_exp_NRM_EW[4]), .Y(n708) );
AO22XLTS U1794 ( .A0(n1416), .A1(DMP_EXP_EWSW[28]), .B0(n1716), .B1(
DMP_SHT1_EWSW[28]), .Y(n706) );
AO22XLTS U1795 ( .A0(n1417), .A1(DMP_SHT1_EWSW[28]), .B0(n1412), .B1(
DMP_SHT2_EWSW[28]), .Y(n705) );
AO22XLTS U1796 ( .A0(n1521), .A1(DMP_SHT2_EWSW[28]), .B0(n1617), .B1(
DMP_SFG[28]), .Y(n704) );
AO22XLTS U1797 ( .A0(n1477), .A1(DMP_SFG[28]), .B0(n1562), .B1(
DMP_exp_NRM_EW[5]), .Y(n703) );
AO22XLTS U1798 ( .A0(n1416), .A1(DMP_EXP_EWSW[29]), .B0(n1415), .B1(
DMP_SHT1_EWSW[29]), .Y(n701) );
AO22XLTS U1799 ( .A0(n1417), .A1(DMP_SHT1_EWSW[29]), .B0(n1412), .B1(
DMP_SHT2_EWSW[29]), .Y(n700) );
AO22XLTS U1800 ( .A0(n1521), .A1(DMP_SHT2_EWSW[29]), .B0(n1520), .B1(
DMP_SFG[29]), .Y(n699) );
AO22XLTS U1801 ( .A0(n1477), .A1(DMP_SFG[29]), .B0(n1748), .B1(
DMP_exp_NRM_EW[6]), .Y(n698) );
AO22XLTS U1802 ( .A0(n1411), .A1(DMP_EXP_EWSW[30]), .B0(n1413), .B1(
DMP_SHT1_EWSW[30]), .Y(n696) );
AO22XLTS U1803 ( .A0(n1417), .A1(DMP_SHT1_EWSW[30]), .B0(n1412), .B1(
DMP_SHT2_EWSW[30]), .Y(n695) );
AO22XLTS U1804 ( .A0(n1624), .A1(DMP_SHT2_EWSW[30]), .B0(n1520), .B1(
DMP_SFG[30]), .Y(n694) );
AO22XLTS U1805 ( .A0(n953), .A1(DMP_SFG[30]), .B0(n1748), .B1(
DMP_exp_NRM_EW[7]), .Y(n693) );
AO22XLTS U1806 ( .A0(n1414), .A1(DmP_EXP_EWSW[14]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[14]), .Y(n662) );
AO22XLTS U1807 ( .A0(n1414), .A1(DmP_EXP_EWSW[16]), .B0(n1405), .B1(
DmP_mant_SHT1_SW[16]), .Y(n658) );
AO22XLTS U1808 ( .A0(n1414), .A1(DmP_EXP_EWSW[19]), .B0(n1716), .B1(n980),
.Y(n652) );
AO22XLTS U1809 ( .A0(n1414), .A1(DmP_EXP_EWSW[22]), .B0(n1415), .B1(
DmP_mant_SHT1_SW[22]), .Y(n646) );
OAI222X1TS U1810 ( .A0(n1408), .A1(n1712), .B0(n1647), .B1(
Shift_reg_FLAGS_7_6), .C0(n1629), .C1(n1406), .Y(n644) );
OAI222X1TS U1811 ( .A0(n1408), .A1(n1651), .B0(n1714), .B1(
Shift_reg_FLAGS_7_6), .C0(n1692), .C1(n1175), .Y(n643) );
OAI222X1TS U1812 ( .A0(n1408), .A1(n1652), .B0(n1710), .B1(
Shift_reg_FLAGS_7_6), .C0(n1691), .C1(n1406), .Y(n642) );
INVX4TS U1813 ( .A(n1409), .Y(n1594) );
NAND2X1TS U1814 ( .A(n1515), .B(Shift_reg_FLAGS_7[0]), .Y(n1410) );
OAI2BB1X1TS U1815 ( .A0N(underflow_flag), .A1N(n1594), .B0(n1410), .Y(n640)
);
AO22XLTS U1816 ( .A0(n1411), .A1(ZERO_FLAG_EXP), .B0(n1405), .B1(
ZERO_FLAG_SHT1), .Y(n638) );
AO22XLTS U1817 ( .A0(n1417), .A1(ZERO_FLAG_SHT1), .B0(n1412), .B1(
ZERO_FLAG_SHT2), .Y(n637) );
AO22XLTS U1818 ( .A0(n1624), .A1(ZERO_FLAG_SHT2), .B0(n1520), .B1(
ZERO_FLAG_SFG), .Y(n636) );
AO22XLTS U1819 ( .A0(n1477), .A1(ZERO_FLAG_SFG), .B0(n1748), .B1(
ZERO_FLAG_NRM), .Y(n635) );
AO22XLTS U1820 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1594), .B1(zero_flag), .Y(n633) );
AO22XLTS U1821 ( .A0(n1414), .A1(OP_FLAG_EXP), .B0(n1413), .B1(OP_FLAG_SHT1),
.Y(n632) );
AO22XLTS U1822 ( .A0(n1417), .A1(OP_FLAG_SHT1), .B0(n1719), .B1(OP_FLAG_SHT2), .Y(n631) );
AO22XLTS U1823 ( .A0(n1617), .A1(n1506), .B0(n1616), .B1(OP_FLAG_SHT2), .Y(
n630) );
AO22XLTS U1824 ( .A0(n1416), .A1(SIGN_FLAG_EXP), .B0(n1413), .B1(
SIGN_FLAG_SHT1), .Y(n629) );
AO22XLTS U1825 ( .A0(n1417), .A1(SIGN_FLAG_SHT1), .B0(n1719), .B1(
SIGN_FLAG_SHT2), .Y(n628) );
AO22XLTS U1826 ( .A0(n1521), .A1(SIGN_FLAG_SHT2), .B0(n1520), .B1(
SIGN_FLAG_SFG), .Y(n627) );
AO22XLTS U1827 ( .A0(n953), .A1(SIGN_FLAG_SFG), .B0(n1562), .B1(
SIGN_FLAG_NRM), .Y(n626) );
INVX1TS U1828 ( .A(DmP_mant_SFG_SWR[15]), .Y(n1599) );
AOI22X1TS U1829 ( .A0(n1506), .A1(n1599), .B0(DmP_mant_SFG_SWR[15]), .B1(
n1639), .Y(intadd_5_CI) );
AOI2BB2XLTS U1830 ( .B0(n953), .B1(intadd_5_SUM_0_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1477), .Y(n623) );
INVX1TS U1831 ( .A(DmP_mant_SFG_SWR[16]), .Y(n1601) );
AOI22X1TS U1832 ( .A0(n1506), .A1(n1601), .B0(DmP_mant_SFG_SWR[16]), .B1(
n1639), .Y(intadd_5_B_1_) );
AOI22X1TS U1833 ( .A0(n1564), .A1(intadd_5_SUM_1_), .B0(n1631), .B1(n1562),
.Y(n622) );
INVX1TS U1834 ( .A(DmP_mant_SFG_SWR[17]), .Y(n1603) );
AOI22X1TS U1835 ( .A0(n1506), .A1(n1603), .B0(DmP_mant_SFG_SWR[17]), .B1(
n1505), .Y(intadd_5_B_2_) );
AOI22X1TS U1836 ( .A0(n1564), .A1(intadd_5_SUM_2_), .B0(n1628), .B1(n1562),
.Y(n621) );
INVX1TS U1837 ( .A(DmP_mant_SFG_SWR[18]), .Y(n1605) );
AOI22X1TS U1838 ( .A0(n1506), .A1(n1605), .B0(DmP_mant_SFG_SWR[18]), .B1(
n1505), .Y(intadd_5_B_3_) );
AOI2BB2XLTS U1839 ( .B0(n953), .B1(intadd_5_SUM_3_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1477), .Y(n620) );
INVX1TS U1840 ( .A(DmP_mant_SFG_SWR[19]), .Y(n1607) );
AOI22X1TS U1841 ( .A0(n1506), .A1(n1607), .B0(DmP_mant_SFG_SWR[19]), .B1(
n1505), .Y(intadd_5_B_4_) );
AOI2BB2XLTS U1842 ( .B0(n953), .B1(intadd_5_SUM_4_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1477), .Y(n619) );
INVX1TS U1843 ( .A(DmP_mant_SFG_SWR[20]), .Y(n1609) );
AOI22X1TS U1844 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1505), .B0(n1506), .B1(
n1609), .Y(intadd_5_B_5_) );
AOI2BB2XLTS U1845 ( .B0(n953), .B1(intadd_5_SUM_5_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1477), .Y(n618) );
INVX1TS U1846 ( .A(DmP_mant_SFG_SWR[21]), .Y(n1611) );
AOI22X1TS U1847 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1505), .B0(n1506), .B1(
n1611), .Y(intadd_5_B_6_) );
AOI22X1TS U1848 ( .A0(n953), .A1(intadd_5_SUM_6_), .B0(n1627), .B1(n1562),
.Y(n617) );
AOI2BB2XLTS U1849 ( .B0(DmP_mant_SFG_SWR[22]), .B1(n1505), .A0N(n1505),
.A1N(DmP_mant_SFG_SWR[22]), .Y(intadd_5_B_7_) );
AOI22X1TS U1850 ( .A0(n953), .A1(intadd_5_SUM_7_), .B0(n1625), .B1(n1562),
.Y(n616) );
AOI2BB2XLTS U1851 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n1505), .A0N(n1505),
.A1N(DmP_mant_SFG_SWR[23]), .Y(intadd_5_B_8_) );
AOI22X1TS U1852 ( .A0(n1564), .A1(intadd_5_SUM_8_), .B0(n961), .B1(n1562),
.Y(n615) );
AOI22X1TS U1853 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1505), .B0(n1002), .B1(
n993), .Y(intadd_5_B_9_) );
AOI22X1TS U1854 ( .A0(n1564), .A1(intadd_5_SUM_9_), .B0(n995), .B1(n1562),
.Y(n614) );
AOI22X1TS U1855 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1506), .B0(n1505), .B1(
n994), .Y(n1418) );
XNOR2X1TS U1856 ( .A(intadd_5_n1), .B(n1418), .Y(n1419) );
AOI22X1TS U1857 ( .A0(n1564), .A1(n1419), .B0(n1626), .B1(n1562), .Y(n613)
);
NAND2X2TS U1858 ( .A(n1655), .B(n1445), .Y(n1544) );
NOR2X2TS U1859 ( .A(shift_value_SHT2_EWR[3]), .B(n1661), .Y(n1471) );
INVX2TS U1860 ( .A(n1471), .Y(n1453) );
AOI22X1TS U1861 ( .A0(Data_array_SWR[18]), .A1(n1420), .B0(
Data_array_SWR[15]), .B1(n1421), .Y(n1422) );
OAI21X1TS U1862 ( .A0(n1646), .A1(n1543), .B0(n1422), .Y(n1531) );
INVX2TS U1863 ( .A(n1421), .Y(n1542) );
OAI22X1TS U1864 ( .A0(n1630), .A1(n1544), .B0(n1697), .B1(n1542), .Y(n1532)
);
NOR2X2TS U1865 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1470) );
INVX2TS U1866 ( .A(n1470), .Y(n1452) );
NAND2X2TS U1867 ( .A(n1592), .B(n1456), .Y(n1591) );
NAND2X2TS U1868 ( .A(n1621), .B(n1456), .Y(n1548) );
OAI22X1TS U1869 ( .A0(n1649), .A1(n1591), .B0(n1705), .B1(n1548), .Y(n1423)
);
AOI221X1TS U1870 ( .A0(n1621), .A1(n1531), .B0(n1592), .B1(n1532), .C0(n1423), .Y(n1566) );
AOI22X1TS U1871 ( .A0(n1613), .A1(n1566), .B0(n1617), .B1(n996), .Y(n612) );
INVX1TS U1872 ( .A(DmP_mant_SFG_SWR[11]), .Y(n1533) );
AOI22X1TS U1873 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[11]), .B0(n1533), .B1(
n1639), .Y(n1522) );
CLKAND2X2TS U1874 ( .A(DMP_SFG[9]), .B(n1522), .Y(n1559) );
NAND2BX1TS U1875 ( .AN(DMP_SFG[10]), .B(n1424), .Y(n1536) );
OAI2BB1X1TS U1876 ( .A0N(n1559), .A1N(n1536), .B0(n1537), .Y(n1523) );
INVX2TS U1877 ( .A(n1523), .Y(n1425) );
OAI21XLTS U1878 ( .A0(n1425), .A1(n1525), .B0(n1524), .Y(n1426) );
XNOR2X1TS U1879 ( .A(n1427), .B(n1426), .Y(n1428) );
AOI22X1TS U1880 ( .A0(n1564), .A1(n1428), .B0(n1633), .B1(n1562), .Y(n611)
);
AOI22X1TS U1881 ( .A0(Data_array_SWR[13]), .A1(n1429), .B0(Data_array_SWR[9]), .B1(n1420), .Y(n1431) );
AOI22X1TS U1882 ( .A0(Data_array_SWR[5]), .A1(n1421), .B0(Data_array_SWR[1]),
.B1(n1456), .Y(n1430) );
OAI211X1TS U1883 ( .A0(n1436), .A1(n1655), .B0(n1431), .C0(n1430), .Y(n1596)
);
AOI22X1TS U1884 ( .A0(Data_array_SWR[22]), .A1(n1588), .B0(n1592), .B1(n1596), .Y(n1432) );
AOI22X1TS U1885 ( .A0(n1613), .A1(n1432), .B0(n1520), .B1(n997), .Y(n609) );
AOI22X1TS U1886 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1505), .B0(n1002), .B1(n997), .Y(n1433) );
AOI2BB2XLTS U1887 ( .B0(n953), .B1(n1433), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n953), .Y(n608) );
AOI22X1TS U1888 ( .A0(Data_array_SWR[12]), .A1(n1421), .B0(
Data_array_SWR[16]), .B1(n1420), .Y(n1435) );
NOR2X2TS U1889 ( .A(n1655), .B(n1452), .Y(n1499) );
AOI22X1TS U1890 ( .A0(Data_array_SWR[19]), .A1(n1429), .B0(
Data_array_SWR[22]), .B1(n1499), .Y(n1434) );
NAND2X1TS U1891 ( .A(n1435), .B(n1434), .Y(n1589) );
INVX2TS U1892 ( .A(n1436), .Y(n1587) );
AOI22X1TS U1893 ( .A0(n1613), .A1(n1585), .B0(n998), .B1(n1520), .Y(n606) );
INVX1TS U1894 ( .A(DmP_mant_SFG_SWR[7]), .Y(n1490) );
AOI22X1TS U1895 ( .A0(n1506), .A1(n1490), .B0(DmP_mant_SFG_SWR[7]), .B1(
n1505), .Y(n1438) );
NAND2BX1TS U1896 ( .AN(DMP_SFG[5]), .B(n1438), .Y(n1493) );
INVX1TS U1897 ( .A(DmP_mant_SFG_SWR[6]), .Y(n1459) );
AOI22X1TS U1898 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[6]), .B0(n1459), .B1(
n1639), .Y(n1437) );
AOI22X1TS U1899 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1506), .B0(n1639), .B1(
n1000), .Y(n1460) );
NAND2X1TS U1900 ( .A(n1460), .B(DMP_SFG[3]), .Y(n1462) );
NAND2X1TS U1901 ( .A(n1437), .B(DMP_SFG[4]), .Y(n1482) );
OAI21XLTS U1902 ( .A0(n1484), .A1(n1462), .B0(n1482), .Y(n1440) );
INVX2TS U1903 ( .A(n1438), .Y(n1439) );
CLKAND2X2TS U1904 ( .A(DMP_SFG[5]), .B(n1439), .Y(n1491) );
AOI21X1TS U1905 ( .A0(n1493), .A1(n1440), .B0(n1491), .Y(n1443) );
OAI22X1TS U1906 ( .A0(n1505), .A1(n998), .B0(DmP_mant_SFG_SWR[8]), .B1(n1506), .Y(n1441) );
NAND2BX1TS U1907 ( .AN(n1441), .B(DMP_SFG[6]), .Y(n1553) );
NAND2BX1TS U1908 ( .AN(DMP_SFG[6]), .B(n1441), .Y(n1492) );
NAND2X1TS U1909 ( .A(n1553), .B(n1492), .Y(n1442) );
XNOR2X1TS U1910 ( .A(n1443), .B(n1442), .Y(n1444) );
AOI2BB2XLTS U1911 ( .B0(n953), .B1(n1444), .A0N(Raw_mant_NRM_SWR[8]), .A1N(
n1564), .Y(n605) );
AOI22X1TS U1912 ( .A0(Data_array_SWR[12]), .A1(n1429), .B0(Data_array_SWR[8]), .B1(n1420), .Y(n1447) );
AOI22X1TS U1913 ( .A0(Data_array_SWR[4]), .A1(n1421), .B0(Data_array_SWR[0]),
.B1(n1456), .Y(n1446) );
OAI211X1TS U1914 ( .A0(n1502), .A1(n1655), .B0(n1447), .C0(n1446), .Y(n1620)
);
AOI22X1TS U1915 ( .A0(Data_array_SWR[23]), .A1(n1588), .B0(n1592), .B1(n1620), .Y(n1448) );
AOI22X1TS U1916 ( .A0(n1624), .A1(n1448), .B0(n1618), .B1(n999), .Y(n603) );
AOI22X1TS U1917 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1505), .B0(n1506), .B1(n999), .Y(n1449) );
AOI2BB2XLTS U1918 ( .B0(n953), .B1(n1449), .A0N(n988), .A1N(n1477), .Y(n602)
);
OAI22X1TS U1919 ( .A0(n1649), .A1(n1543), .B0(n1704), .B1(n1544), .Y(n1451)
);
AO22XLTS U1920 ( .A0(n1572), .A1(shift_value_SHT2_EWR[4]), .B0(
Data_array_SWR[6]), .B1(n1421), .Y(n1450) );
OAI22X1TS U1921 ( .A0(n1621), .A1(n1593), .B0(n1646), .B1(n1548), .Y(n1584)
);
OAI22X1TS U1922 ( .A0(n1650), .A1(n1543), .B0(n1705), .B1(n1544), .Y(n1455)
);
AO22XLTS U1923 ( .A0(n1581), .A1(shift_value_SHT2_EWR[4]), .B0(
Data_array_SWR[7]), .B1(n1421), .Y(n1454) );
OAI22X1TS U1924 ( .A0(n1621), .A1(n1590), .B0(n1630), .B1(n1548), .Y(n1583)
);
AOI22X1TS U1925 ( .A0(Data_array_SWR[14]), .A1(n1420), .B0(
Data_array_SWR[10]), .B1(n1421), .Y(n1458) );
AOI22X1TS U1926 ( .A0(Data_array_SWR[20]), .A1(n1499), .B0(
Data_array_SWR[17]), .B1(n1429), .Y(n1457) );
NAND2X1TS U1927 ( .A(n1458), .B(n1457), .Y(n1582) );
AOI22X1TS U1928 ( .A0(n1613), .A1(n1580), .B0(n1459), .B1(n1617), .Y(n595)
);
INVX2TS U1929 ( .A(n1482), .Y(n1494) );
NOR2XLTS U1930 ( .A(n1494), .B(n1484), .Y(n1466) );
INVX2TS U1931 ( .A(n1472), .Y(n1463) );
INVX2TS U1932 ( .A(n1462), .Y(n1473) );
OAI21XLTS U1933 ( .A0(n1472), .A1(n1464), .B0(n1483), .Y(n1465) );
XNOR2X1TS U1934 ( .A(n1466), .B(n1465), .Y(n1467) );
AOI22X1TS U1935 ( .A0(n1564), .A1(n1467), .B0(n1659), .B1(n1748), .Y(n594)
);
AOI22X1TS U1936 ( .A0(Data_array_SWR[19]), .A1(n1470), .B0(
Data_array_SWR[22]), .B1(n1471), .Y(n1481) );
AOI22X1TS U1937 ( .A0(Data_array_SWR[12]), .A1(n1420), .B0(Data_array_SWR[8]), .B1(n1421), .Y(n1469) );
NAND2X1TS U1938 ( .A(Data_array_SWR[16]), .B(n1429), .Y(n1468) );
OAI211X1TS U1939 ( .A0(n1481), .A1(n1655), .B0(n1469), .C0(n1468), .Y(n1579)
);
AO22X1TS U1940 ( .A0(Data_array_SWR[23]), .A1(n1471), .B0(n989), .B1(n1470),
.Y(n1578) );
AOI22X1TS U1941 ( .A0(n1613), .A1(n1577), .B0(n1617), .B1(n1001), .Y(n592)
);
CMPR32X2TS U1942 ( .A(DMP_SFG[2]), .B(n977), .C(n1474), .CO(n1475), .S(n1008) );
XNOR2X1TS U1943 ( .A(n1476), .B(n1475), .Y(n1478) );
AOI2BB2XLTS U1944 ( .B0(n953), .B1(n1478), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n1477), .Y(n591) );
AOI22X1TS U1945 ( .A0(Data_array_SWR[13]), .A1(n1420), .B0(Data_array_SWR[9]), .B1(n1421), .Y(n1480) );
AOI22X1TS U1946 ( .A0(n990), .A1(n1429), .B0(shift_value_SHT2_EWR[4]), .B1(
n1578), .Y(n1479) );
NAND2X1TS U1947 ( .A(n1480), .B(n1479), .Y(n1576) );
INVX2TS U1948 ( .A(n1481), .Y(n1575) );
AOI22X1TS U1949 ( .A0(n1624), .A1(n1574), .B0(n1618), .B1(n1000), .Y(n590)
);
NOR2BX1TS U1950 ( .AN(n1493), .B(n1491), .Y(n1486) );
OAI21XLTS U1951 ( .A0(n1484), .A1(n1483), .B0(n1482), .Y(n1485) );
XNOR2X1TS U1952 ( .A(n1486), .B(n1485), .Y(n1487) );
AOI22X1TS U1953 ( .A0(n1564), .A1(n1487), .B0(n1654), .B1(n1748), .Y(n589)
);
AOI22X1TS U1954 ( .A0(Data_array_SWR[15]), .A1(n1420), .B0(
Data_array_SWR[11]), .B1(n1421), .Y(n1489) );
AOI22X1TS U1955 ( .A0(Data_array_SWR[21]), .A1(n1499), .B0(
Data_array_SWR[18]), .B1(n1429), .Y(n1488) );
NAND2X1TS U1956 ( .A(n1489), .B(n1488), .Y(n1573) );
AOI22X1TS U1957 ( .A0(n1613), .A1(n1571), .B0(n1490), .B1(n1618), .Y(n588)
);
OAI2BB1X1TS U1958 ( .A0N(n1491), .A1N(n1492), .B0(n1553), .Y(n1508) );
AOI31XLTS U1959 ( .A0(n1494), .A1(n1493), .A2(n1492), .B0(n1508), .Y(n1497)
);
INVX1TS U1960 ( .A(DmP_mant_SFG_SWR[9]), .Y(n1504) );
AOI22X1TS U1961 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[9]), .B0(n1504), .B1(
n1505), .Y(n1495) );
NAND2X1TS U1962 ( .A(n1495), .B(DMP_SFG[7]), .Y(n1552) );
NOR2BX1TS U1963 ( .AN(n1552), .B(n1554), .Y(n1496) );
XOR2X1TS U1964 ( .A(n1497), .B(n1496), .Y(n1498) );
AOI22X1TS U1965 ( .A0(n1564), .A1(n1498), .B0(n1664), .B1(n1748), .Y(n587)
);
AOI22X1TS U1966 ( .A0(n990), .A1(n1420), .B0(Data_array_SWR[13]), .B1(n1421),
.Y(n1501) );
AOI22X1TS U1967 ( .A0(n989), .A1(n1429), .B0(Data_array_SWR[23]), .B1(n1499),
.Y(n1500) );
NAND2X1TS U1968 ( .A(n1501), .B(n1500), .Y(n1570) );
INVX2TS U1969 ( .A(n1502), .Y(n1569) );
AOI22X1TS U1970 ( .A0(n1624), .A1(n1568), .B0(n1504), .B1(n1618), .Y(n586)
);
INVX1TS U1971 ( .A(DmP_mant_SFG_SWR[10]), .Y(n1546) );
AOI22X1TS U1972 ( .A0(n1506), .A1(DmP_mant_SFG_SWR[10]), .B0(n1546), .B1(
n1505), .Y(n1507) );
NAND2X1TS U1973 ( .A(n1507), .B(DMP_SFG[8]), .Y(n1534) );
INVX2TS U1974 ( .A(n1534), .Y(n1557) );
NOR2X2TS U1975 ( .A(n1507), .B(DMP_SFG[8]), .Y(n1555) );
NOR2XLTS U1976 ( .A(n1557), .B(n1555), .Y(n1511) );
INVX2TS U1977 ( .A(n1508), .Y(n1509) );
XNOR2X1TS U1978 ( .A(n1511), .B(n1510), .Y(n1512) );
AOI22X1TS U1979 ( .A0(n1564), .A1(n1512), .B0(n1656), .B1(n1748), .Y(n585)
);
AOI22X1TS U1980 ( .A0(Data_array_SWR[12]), .A1(n1622), .B0(
Data_array_SWR[13]), .B1(n1588), .Y(n1513) );
OAI221X1TS U1981 ( .A0(n1621), .A1(n1518), .B0(n1592), .B1(n1519), .C0(n1513), .Y(n1516) );
AO22XLTS U1982 ( .A0(n1595), .A1(n1516), .B0(final_result_ieee[10]), .B1(
n1594), .Y(n583) );
AOI22X1TS U1983 ( .A0(Data_array_SWR[12]), .A1(n1588), .B0(
Data_array_SWR[13]), .B1(n1622), .Y(n1517) );
OAI221X1TS U1984 ( .A0(n1621), .A1(n1519), .B0(n1592), .B1(n1518), .C0(n1517), .Y(n1567) );
OR2X1TS U1985 ( .A(DMP_SFG[9]), .B(n1522), .Y(n1558) );
AOI31XLTS U1986 ( .A0(n1557), .A1(n1536), .A2(n1558), .B0(n1523), .Y(n1527)
);
XNOR2X1TS U1987 ( .A(n1527), .B(n1526), .Y(n1528) );
AOI2BB2XLTS U1988 ( .B0(n953), .B1(n1528), .A0N(Raw_mant_NRM_SWR[13]), .A1N(
n953), .Y(n581) );
OAI22X1TS U1989 ( .A0(n1649), .A1(n1548), .B0(n1705), .B1(n1591), .Y(n1530)
);
AOI221X1TS U1990 ( .A0(n1621), .A1(n1532), .B0(n1592), .B1(n1531), .C0(n1530), .Y(n1565) );
AOI22X1TS U1991 ( .A0(n1624), .A1(n1565), .B0(n1533), .B1(n1618), .Y(n580)
);
OAI21XLTS U1992 ( .A0(n1555), .A1(n1552), .B0(n1534), .Y(n1535) );
AOI21X1TS U1993 ( .A0(n1558), .A1(n1535), .B0(n1559), .Y(n1539) );
NAND2X1TS U1994 ( .A(n1537), .B(n1536), .Y(n1538) );
XNOR2X1TS U1995 ( .A(n1539), .B(n1538), .Y(n1541) );
AOI22X1TS U1996 ( .A0(n1564), .A1(n1541), .B0(n1653), .B1(n1748), .Y(n579)
);
OAI22X1TS U1997 ( .A0(n1646), .A1(n1544), .B0(n1701), .B1(n1542), .Y(n1550)
);
OAI222X1TS U1998 ( .A0(n1544), .A1(n1697), .B0(n1543), .B1(n1630), .C0(n1542), .C1(n1649), .Y(n1551) );
OAI22X1TS U1999 ( .A0(n1704), .A1(n1591), .B0(n1650), .B1(n1548), .Y(n1545)
);
AOI221X1TS U2000 ( .A0(n1621), .A1(n1550), .B0(n1592), .B1(n1551), .C0(n1545), .Y(n1547) );
AOI22X1TS U2001 ( .A0(n1624), .A1(n1547), .B0(n1546), .B1(n1618), .Y(n578)
);
INVX4TS U2002 ( .A(n1595), .Y(n1598) );
OAI2BB2XLTS U2003 ( .B0(n1547), .B1(n1598), .A0N(final_result_ieee[8]),
.A1N(n1594), .Y(n577) );
OAI22X1TS U2004 ( .A0(n1704), .A1(n1548), .B0(n1650), .B1(n1591), .Y(n1549)
);
AOI221X1TS U2005 ( .A0(n1621), .A1(n1551), .B0(n1592), .B1(n1550), .C0(n1549), .Y(n1600) );
OAI2BB2XLTS U2006 ( .B0(n1600), .B1(n1598), .A0N(final_result_ieee[13]),
.A1N(n1594), .Y(n576) );
OAI32X1TS U2007 ( .A0(n1555), .A1(n1554), .A2(n1553), .B0(n1552), .B1(n1555),
.Y(n1556) );
NOR2XLTS U2008 ( .A(n1557), .B(n1556), .Y(n1561) );
NAND2BXLTS U2009 ( .AN(n1559), .B(n1558), .Y(n1560) );
XNOR2X1TS U2010 ( .A(n1561), .B(n1560), .Y(n1563) );
AOI22X1TS U2011 ( .A0(n1564), .A1(n1563), .B0(n1634), .B1(n1562), .Y(n575)
);
OAI2BB2XLTS U2012 ( .B0(n1565), .B1(n1598), .A0N(final_result_ieee[9]),
.A1N(n1594), .Y(n574) );
OAI2BB2XLTS U2013 ( .B0(n1566), .B1(n1598), .A0N(final_result_ieee[12]),
.A1N(n1594), .Y(n573) );
AO22XLTS U2014 ( .A0(n1595), .A1(n1567), .B0(final_result_ieee[11]), .B1(
n1594), .Y(n572) );
OAI2BB2XLTS U2015 ( .B0(n1568), .B1(n1598), .A0N(final_result_ieee[7]),
.A1N(n1594), .Y(n571) );
OAI2BB2XLTS U2016 ( .B0(n1602), .B1(n1598), .A0N(final_result_ieee[14]),
.A1N(n1594), .Y(n570) );
OAI2BB2XLTS U2017 ( .B0(n1571), .B1(n1598), .A0N(final_result_ieee[5]),
.A1N(n1597), .Y(n569) );
OAI2BB2XLTS U2018 ( .B0(n1606), .B1(n1598), .A0N(final_result_ieee[16]),
.A1N(n1597), .Y(n568) );
OAI2BB2XLTS U2019 ( .B0(n1574), .B1(n1598), .A0N(final_result_ieee[3]),
.A1N(n1597), .Y(n567) );
OAI2BB2XLTS U2020 ( .B0(n1610), .B1(n1598), .A0N(final_result_ieee[18]),
.A1N(n1597), .Y(n566) );
OAI2BB2XLTS U2021 ( .B0(n1577), .B1(n1598), .A0N(final_result_ieee[2]),
.A1N(n1597), .Y(n565) );
OAI2BB2XLTS U2022 ( .B0(n1612), .B1(n1598), .A0N(final_result_ieee[19]),
.A1N(n1597), .Y(n564) );
OAI2BB2XLTS U2023 ( .B0(n1580), .B1(n1598), .A0N(final_result_ieee[4]),
.A1N(n1597), .Y(n563) );
OAI2BB2XLTS U2024 ( .B0(n1608), .B1(n1598), .A0N(final_result_ieee[17]),
.A1N(n1597), .Y(n562) );
AO22XLTS U2025 ( .A0(n1595), .A1(n1583), .B0(final_result_ieee[1]), .B1(
n1594), .Y(n561) );
AO22XLTS U2026 ( .A0(n1595), .A1(n1584), .B0(final_result_ieee[0]), .B1(
n1594), .Y(n560) );
OAI2BB2XLTS U2027 ( .B0(n1585), .B1(n1598), .A0N(final_result_ieee[6]),
.A1N(n1597), .Y(n559) );
OAI2BB2XLTS U2028 ( .B0(n1604), .B1(n1598), .A0N(final_result_ieee[15]),
.A1N(n1594), .Y(n558) );
OAI22X1TS U2029 ( .A0(n1590), .A1(n1592), .B0(n1630), .B1(n1591), .Y(n1614)
);
AO22XLTS U2030 ( .A0(n1595), .A1(n1614), .B0(final_result_ieee[20]), .B1(
n1594), .Y(n557) );
OAI22X1TS U2031 ( .A0(n1593), .A1(n1592), .B0(n1646), .B1(n1591), .Y(n1615)
);
AO22XLTS U2032 ( .A0(n1595), .A1(n1615), .B0(final_result_ieee[21]), .B1(
n1594), .Y(n556) );
AOI22X1TS U2033 ( .A0(Data_array_SWR[22]), .A1(n1622), .B0(n1621), .B1(n1596), .Y(n1619) );
OAI2BB2XLTS U2034 ( .B0(n1619), .B1(n1598), .A0N(final_result_ieee[22]),
.A1N(n1597), .Y(n555) );
AOI22X1TS U2035 ( .A0(n1613), .A1(n1600), .B0(n1599), .B1(n1618), .Y(n554)
);
AOI22X1TS U2036 ( .A0(n1613), .A1(n1602), .B0(n1601), .B1(n1618), .Y(n553)
);
AOI22X1TS U2037 ( .A0(n1613), .A1(n1604), .B0(n1603), .B1(n1618), .Y(n552)
);
AOI22X1TS U2038 ( .A0(n1613), .A1(n1606), .B0(n1605), .B1(n1618), .Y(n551)
);
AOI22X1TS U2039 ( .A0(n1613), .A1(n1608), .B0(n1607), .B1(n1618), .Y(n550)
);
AOI22X1TS U2040 ( .A0(n1613), .A1(n1610), .B0(n1609), .B1(n1618), .Y(n549)
);
AOI22X1TS U2041 ( .A0(n1613), .A1(n1612), .B0(n1611), .B1(n1618), .Y(n548)
);
AO22XLTS U2042 ( .A0(n1617), .A1(DmP_mant_SFG_SWR[22]), .B0(n1616), .B1(
n1614), .Y(n547) );
AO22XLTS U2043 ( .A0(n1617), .A1(DmP_mant_SFG_SWR[23]), .B0(n1616), .B1(
n1615), .Y(n546) );
AOI22X1TS U2044 ( .A0(n1613), .A1(n1619), .B0(n1618), .B1(n993), .Y(n545) );
AOI22X1TS U2045 ( .A0(Data_array_SWR[23]), .A1(n1622), .B0(n1621), .B1(n1620), .Y(n1623) );
AOI22X1TS U2046 ( .A0(n1613), .A1(n1623), .B0(n1617), .B1(n994), .Y(n544) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk40.tcl_ACAIN16Q4_syn.sdf");
endmodule
|
// nios_system_nios2_qsys_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2016.05.03.15:20:15
`timescale 1 ps / 1 ps
module nios_system_nios2_qsys_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [18:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [18:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_system_nios2_qsys_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFSBP_PP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_PP_BLACKBOX_V
|
module Control_tb ();
reg irq, PC31;
reg [5:0] OpCode, Funct;
wire [2:0] PCSrc;
wire [1:0] RegDst, MemtoReg;
wire [5:0] ALUFun;
wire RegWrite, ALUSrc1, ALUSrc2, Branch,
MemWrite, MemRead, ExtOp, LuOp, Sign, Jump;
Control con(
.irq(irq), .PC31(PC31),
.OpCode(OpCode), .Funct(Funct), .PCSrc(PCSrc),
.RegDst(RegDst), .MemtoReg(MemtoReg), .RegWrite(RegWrite),
.ALUSrc1(ALUSrc1), .ALUSrc2(ALUSrc2), .Branch(Branch),
.MemWrite(MemWrite), .MemRead(MemRead), .ExtOp(ExtOp),
.LuOp(LuOp), .Sign(Sign), .ALUFun(ALUFun), .Jump(Jump)
);
initial begin
irq = 1;
PC31 = 0;
OpCode = 6'h23;
Funct = 6'h3f;
#5 irq = 0;
OpCode = 6'h3f;
Funct = 6'h3f;
#5 OpCode = 6'h23;
#5 OpCode = 6'h2b;
#5 OpCode = 6'hf;
#5 OpCode = 6'h0;
Funct = 6'h20;
#5 Funct = 6'h21;
#5 Funct = 6'h22;
#5 Funct = 6'h23;
#5 OpCode = 6'h8;
#5 OpCode = 6'h9;
#5 OpCode = 6'h0;
Funct = 6'h24;
#5 Funct = 6'h25;
#5 Funct = 6'h26;
#5 Funct = 6'h27;
#5 OpCode = 6'hc;
#5 OpCode = 6'hd;
#5 OpCode = 6'h0;
Funct = 6'h0;
#5 Funct = 6'h2;
#5 Funct = 6'h3;
#5 Funct = 6'h2a;
#5 Funct = 6'h2b;
#5 OpCode = 6'ha;
#5 OpCode = 6'hb;
#5 OpCode = 6'h4;
#5 OpCode = 6'h5;
#5 OpCode = 6'h6;
#5 OpCode = 6'h7;
#5 OpCode = 6'h1;
#5 OpCode = 6'h2;
#5 OpCode = 6'h3;
#5 OpCode = 6'h0;
Funct = 6'h8;
#5 Funct = 6'h9;
end
endmodule |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2 #(
parameter csr_addr = 4'h0,
parameter fml_depth = 26,
parameter texel_cache_depth = 14 /* 16kB cache */
) (
/* Global clock and reset signals */
input sys_clk,
input sys_rst,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
output irq,
/* WB master - Vertex read. */
output [31:0] wbm_adr_o,
output [2:0] wbm_cti_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
input [31:0] wbm_dat_i,
/* FML master - Texture pixel read. fml_we=0 is assumed. */
output [fml_depth-1:0] fmlr_adr,
output fmlr_stb,
input fmlr_ack,
input [63:0] fmlr_di,
/* FML master - Destination pixel read. fml_we=0 is assumed. */
output [fml_depth-1:0] fmldr_adr,
output fmldr_stb,
input fmldr_ack,
input [63:0] fmldr_di,
/* FML master - Destination pixel write. fml_we=1 is assumed. */
output [fml_depth-1:0] fmlw_adr,
output fmlw_stb,
input fmlw_ack,
output [7:0] fmlw_sel,
output [63:0] fmlw_do
);
`define TMU_HAS_ALPHA
/*
* Fixed Point (FP) coordinate format:
* 1 sign bit
* 11 integer bits
* 6 fractional bits
* Properties:
* - 18-bit coordinate
* - Range: -2048 to +2047.984375
*/
wire start;
reg busy;
wire [6:0] vertex_hlast; /* < 04 last horizontal vertex index */
wire [6:0] vertex_vlast; /* < 08 last vertical vertex index */
wire [5:0] brightness; /* < 0C output brightness 0-63 */
wire chroma_key_en; /* < 00 enable/disable chroma key filtering */
wire [15:0] chroma_key; /* < 10 chroma key (RGB565 color) */
wire [28:0] vertex_adr; /* < 14 vertex mesh address (64-bit words) */
wire [fml_depth-1-1:0] tex_fbuf; /* < 18 texture address (16-bit words) */
wire [10:0] tex_hres; /* < 1C texture horizontal resolution (positive int) */
wire [10:0] tex_vres; /* < 20 texture vertical resolution (positive int) */
wire [17:0] tex_hmask; /* < 24 binary mask to the X texture coordinates (matches fp width) */
wire [17:0] tex_vmask; /* < 28 binary mask to the Y texture coordinates (matches fp width) */
wire [fml_depth-1-1:0] dst_fbuf; /* < 2C destination framebuffer address (16-bit words) */
wire [10:0] dst_hres; /* < 30 destination horizontal resolution (positive int) */
wire [10:0] dst_vres; /* < 34 destination vertical resolution (positive int) */
wire signed [11:0] dst_hoffset; /* < 38 X offset added to each pixel (signed int) */
wire signed [11:0] dst_voffset; /* < 3C Y offset added to each pixel (signed int) */
wire [10:0] dst_squarew; /* < 40 width of each destination rectangle (positive int)*/
wire [10:0] dst_squareh; /* < 44 height of each destination rectangle (positive int)*/
wire alpha_en;
wire [5:0] alpha; /* < 48 opacity of the output 0-63 */
wire [21:0] c_req_a; /* < 50 texel cache requests on channel A */
wire [21:0] c_hit_a; /* < 54 texel cache hits on channel A */
wire [21:0] c_req_b; /* < 58 texel cache requests on channel B */
wire [21:0] c_hit_b; /* < 5C texel cache hits on channel B */
wire [21:0] c_req_c; /* < 60 texel cache requests on channel C */
wire [21:0] c_hit_c; /* < 64 texel cache hits on channel C */
wire [21:0] c_req_d; /* < 68 texel cache requests on channel D */
wire [21:0] c_hit_d; /* < 6C texel cache hits on channel D */
tmu2_ctlif #(
.csr_addr(csr_addr),
.fml_depth(fml_depth)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.irq(irq),
.start(start),
.busy(busy),
.vertex_hlast(vertex_hlast),
.vertex_vlast(vertex_vlast),
.brightness(brightness),
.chroma_key_en(chroma_key_en),
.chroma_key(chroma_key),
.vertex_adr(vertex_adr),
.tex_fbuf(tex_fbuf),
.tex_hres(tex_hres),
.tex_vres(tex_vres),
.tex_hmask(tex_hmask),
.tex_vmask(tex_vmask),
.dst_fbuf(dst_fbuf),
.dst_hres(dst_hres),
.dst_vres(dst_vres),
.dst_hoffset(dst_hoffset),
.dst_voffset(dst_voffset),
.dst_squarew(dst_squarew),
.dst_squareh(dst_squareh),
.alpha_en(alpha_en),
.alpha(alpha),
.c_req_a(c_req_a),
.c_hit_a(c_hit_a),
.c_req_b(c_req_b),
.c_hit_b(c_hit_b),
.c_req_c(c_req_c),
.c_hit_c(c_hit_c),
.c_req_d(c_req_d),
.c_hit_d(c_hit_d)
);
/* Stage 1 - Fetch vertices */
wire fetchvertex_busy;
wire fetchvertex_pipe_stb;
wire fetchvertex_pipe_ack;
wire signed [17:0] ax;
wire signed [17:0] ay;
wire signed [17:0] bx;
wire signed [17:0] by;
wire signed [17:0] cx;
wire signed [17:0] cy;
wire signed [17:0] dx;
wire signed [17:0] dy;
wire signed [11:0] drx;
wire signed [11:0] dry;
tmu2_fetchvertex fetchvertex(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.start(start),
.busy(fetchvertex_busy),
.wbm_adr_o(wbm_adr_o),
.wbm_cti_o(wbm_cti_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_ack_i(wbm_ack_i),
.wbm_dat_i(wbm_dat_i),
.vertex_hlast(vertex_hlast),
.vertex_vlast(vertex_vlast),
.vertex_adr(vertex_adr),
.dst_hoffset(dst_hoffset),
.dst_voffset(dst_voffset),
.dst_squarew(dst_squarew),
.dst_squareh(dst_squareh),
.pipe_stb_o(fetchvertex_pipe_stb),
.pipe_ack_i(fetchvertex_pipe_ack),
.ax(ax),
.ay(ay),
.bx(bx),
.by(by),
.cx(cx),
.cy(cy),
.dx(dx),
.dy(dy),
.drx(drx),
.dry(dry)
);
/* Stage 2 - Vertical interpolation division operands */
wire vdivops_busy;
wire vdivops_pipe_stb;
wire vdivops_pipe_ack;
wire signed [17:0] ax_f;
wire signed [17:0] ay_f;
wire signed [17:0] bx_f;
wire signed [17:0] by_f;
wire diff_cx_positive;
wire [16:0] diff_cx;
wire diff_cy_positive;
wire [16:0] diff_cy;
wire diff_dx_positive;
wire [16:0] diff_dx;
wire diff_dy_positive;
wire [16:0] diff_dy;
wire signed [11:0] drx_f;
wire signed [11:0] dry_f;
tmu2_vdivops vdivops(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(vdivops_busy),
.pipe_stb_i(fetchvertex_pipe_stb),
.pipe_ack_o(fetchvertex_pipe_ack),
.ax(ax),
.ay(ay),
.bx(bx),
.by(by),
.cx(cx),
.cy(cy),
.dx(dx),
.dy(dy),
.drx(drx),
.dry(dry),
.pipe_stb_o(vdivops_pipe_stb),
.pipe_ack_i(vdivops_pipe_ack),
.ax_f(ax_f),
.ay_f(ay_f),
.bx_f(bx_f),
.by_f(by_f),
.diff_cx_positive(diff_cx_positive),
.diff_cx(diff_cx),
.diff_cy_positive(diff_cy_positive),
.diff_cy(diff_cy),
.diff_dx_positive(diff_dx_positive),
.diff_dx(diff_dx),
.diff_dy_positive(diff_dy_positive),
.diff_dy(diff_dy),
.drx_f(drx_f),
.dry_f(dry_f)
);
/* Stage 3 - Vertical division */
wire vdiv_busy;
wire vdiv_pipe_stb;
wire vdiv_pipe_ack;
wire signed [17:0] ax_f2;
wire signed [17:0] ay_f2;
wire signed [17:0] bx_f2;
wire signed [17:0] by_f2;
wire diff_cx_positive_f;
wire [16:0] diff_cx_q;
wire [16:0] diff_cx_r;
wire diff_cy_positive_f;
wire [16:0] diff_cy_q;
wire [16:0] diff_cy_r;
wire diff_dx_positive_f;
wire [16:0] diff_dx_q;
wire [16:0] diff_dx_r;
wire diff_dy_positive_f;
wire [16:0] diff_dy_q;
wire [16:0] diff_dy_r;
wire signed [11:0] drx_f2;
wire signed [11:0] dry_f2;
tmu2_vdiv vdiv(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(vdiv_busy),
.pipe_stb_i(vdivops_pipe_stb),
.pipe_ack_o(vdivops_pipe_ack),
.ax(ax_f),
.ay(ay_f),
.bx(bx_f),
.by(by_f),
.diff_cx_positive(diff_cx_positive),
.diff_cx(diff_cx),
.diff_cy_positive(diff_cy_positive),
.diff_cy(diff_cy),
.diff_dx_positive(diff_dx_positive),
.diff_dx(diff_dx),
.diff_dy_positive(diff_dy_positive),
.diff_dy(diff_dy),
.drx(drx_f),
.dry(dry_f),
.dst_squareh(dst_squareh),
.pipe_stb_o(vdiv_pipe_stb),
.pipe_ack_i(vdiv_pipe_ack),
.ax_f(ax_f2),
.ay_f(ay_f2),
.bx_f(bx_f2),
.by_f(by_f2),
.diff_cx_positive_f(diff_cx_positive_f),
.diff_cx_q(diff_cx_q),
.diff_cx_r(diff_cx_r),
.diff_cy_positive_f(diff_cy_positive_f),
.diff_cy_q(diff_cy_q),
.diff_cy_r(diff_cy_r),
.diff_dx_positive_f(diff_dx_positive_f),
.diff_dx_q(diff_dx_q),
.diff_dx_r(diff_dx_r),
.diff_dy_positive_f(diff_dy_positive_f),
.diff_dy_q(diff_dy_q),
.diff_dy_r(diff_dy_r),
.drx_f(drx_f2),
.dry_f(dry_f2)
);
/* Stage 4 - Vertical interpolation */
wire vinterp_busy;
wire vinterp_pipe_stb;
wire vinterp_pipe_ack;
wire signed [11:0] vx;
wire signed [11:0] vy;
wire signed [17:0] tsx;
wire signed [17:0] tsy;
wire signed [17:0] tex;
wire signed [17:0] tey;
tmu2_vinterp vinterp(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(vinterp_busy),
.pipe_stb_i(vdiv_pipe_stb),
.pipe_ack_o(vdiv_pipe_ack),
.ax(ax_f2),
.ay(ay_f2),
.bx(bx_f2),
.by(by_f2),
.diff_cx_positive(diff_cx_positive_f),
.diff_cx_q(diff_cx_q),
.diff_cx_r(diff_cx_r),
.diff_cy_positive(diff_cy_positive_f),
.diff_cy_q(diff_cy_q),
.diff_cy_r(diff_cy_r),
.diff_dx_positive(diff_dx_positive_f),
.diff_dx_q(diff_dx_q),
.diff_dx_r(diff_dx_r),
.diff_dy_positive(diff_dy_positive_f),
.diff_dy_q(diff_dy_q),
.diff_dy_r(diff_dy_r),
.drx(drx_f2),
.dry(dry_f2),
.dst_squareh(dst_squareh),
.pipe_stb_o(vinterp_pipe_stb),
.pipe_ack_i(vinterp_pipe_ack),
.x(vx),
.y(vy),
.tsx(tsx),
.tsy(tsy),
.tex(tex),
.tey(tey)
);
/* Stage 5 - Horizontal interpolation division operands */
wire hdivops_busy;
wire hdivops_pipe_stb;
wire hdivops_pipe_ack;
wire signed [11:0] vx_f;
wire signed [11:0] vy_f;
wire signed [17:0] tsx_f;
wire signed [17:0] tsy_f;
wire diff_x_positive;
wire [16:0] diff_x;
wire diff_y_positive;
wire [16:0] diff_y;
tmu2_hdivops hdivops(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(hdivops_busy),
.pipe_stb_i(vinterp_pipe_stb),
.pipe_ack_o(vinterp_pipe_ack),
.x(vx),
.y(vy),
.tsx(tsx),
.tsy(tsy),
.tex(tex),
.tey(tey),
.pipe_stb_o(hdivops_pipe_stb),
.pipe_ack_i(hdivops_pipe_ack),
.x_f(vx_f),
.y_f(vy_f),
.tsx_f(tsx_f),
.tsy_f(tsy_f),
.diff_x_positive(diff_x_positive),
.diff_x(diff_x),
.diff_y_positive(diff_y_positive),
.diff_y(diff_y)
);
/* Stage 6 - Horizontal division */
wire hdiv_busy;
wire hdiv_pipe_stb;
wire hdiv_pipe_ack;
wire signed [11:0] vx_f2;
wire signed [11:0] vy_f2;
wire signed [17:0] tsx_f2;
wire signed [17:0] tsy_f2;
wire diff_x_positive_f;
wire [16:0] diff_x_q;
wire [16:0] diff_x_r;
wire diff_y_positive_f;
wire [16:0] diff_y_q;
wire [16:0] diff_y_r;
tmu2_hdiv hdiv(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(hdiv_busy),
.pipe_stb_i(hdivops_pipe_stb),
.pipe_ack_o(hdivops_pipe_ack),
.x(vx_f),
.y(vy_f),
.tsx(tsx_f),
.tsy(tsy_f),
.diff_x_positive(diff_x_positive),
.diff_x(diff_x),
.diff_y_positive(diff_y_positive),
.diff_y(diff_y),
.dst_squarew(dst_squarew),
.pipe_stb_o(hdiv_pipe_stb),
.pipe_ack_i(hdiv_pipe_ack),
.x_f(vx_f2),
.y_f(vy_f2),
.tsx_f(tsx_f2),
.tsy_f(tsy_f2),
.diff_x_positive_f(diff_x_positive_f),
.diff_x_q(diff_x_q),
.diff_x_r(diff_x_r),
.diff_y_positive_f(diff_y_positive_f),
.diff_y_q(diff_y_q),
.diff_y_r(diff_y_r)
);
/* Stage 7 - Horizontal interpolation */
wire hinterp_busy;
wire hinterp_pipe_stb;
wire hinterp_pipe_ack;
wire signed [11:0] dstx;
wire signed [11:0] dsty;
wire signed [17:0] tx;
wire signed [17:0] ty;
tmu2_hinterp hinterp(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(hinterp_busy),
.pipe_stb_i(hdiv_pipe_stb),
.pipe_ack_o(hdiv_pipe_ack),
.x(vx_f2),
.y(vy_f2),
.tsx(tsx_f2),
.tsy(tsy_f2),
.diff_x_positive(diff_x_positive_f),
.diff_x_q(diff_x_q),
.diff_x_r(diff_x_r),
.diff_y_positive(diff_y_positive_f),
.diff_y_q(diff_y_q),
.diff_y_r(diff_y_r),
.dst_squarew(dst_squarew),
.pipe_stb_o(hinterp_pipe_stb),
.pipe_ack_i(hinterp_pipe_ack),
.dx(dstx),
.dy(dsty),
.tx(tx),
.ty(ty)
);
/* Stage 8 - Mask texture coordinates */
wire mask_busy;
wire mask_pipe_stb;
wire mask_pipe_ack;
wire signed [11:0] dstx_f;
wire signed [11:0] dsty_f;
wire signed [17:0] tx_m;
wire signed [17:0] ty_m;
tmu2_mask mask(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(mask_busy),
.pipe_stb_i(hinterp_pipe_stb),
.pipe_ack_o(hinterp_pipe_ack),
.dx(dstx),
.dy(dsty),
.tx(tx),
.ty(ty),
.tex_hmask(tex_hmask),
.tex_vmask(tex_vmask),
.pipe_stb_o(mask_pipe_stb),
.pipe_ack_i(mask_pipe_ack),
.dx_f(dstx_f),
.dy_f(dsty_f),
.tx_m(tx_m),
.ty_m(ty_m)
);
/* Stage 9 - Clamp texture coordinates and filter out off-screen points */
wire clamp_busy;
wire clamp_pipe_stb;
wire clamp_pipe_ack;
wire [10:0] dstx_c;
wire [10:0] dsty_c;
wire [16:0] tx_c;
wire [16:0] ty_c;
tmu2_clamp clamp(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(clamp_busy),
.pipe_stb_i(mask_pipe_stb),
.pipe_ack_o(mask_pipe_ack),
.dx(dstx_f),
.dy(dsty_f),
.tx(tx_m),
.ty(ty_m),
.tex_hres(tex_hres),
.tex_vres(tex_vres),
.dst_hres(dst_hres),
.dst_vres(dst_vres),
.pipe_stb_o(clamp_pipe_stb),
.pipe_ack_i(clamp_pipe_ack),
.dx_c(dstx_c),
.dy_c(dsty_c),
.tx_c(tx_c),
.ty_c(ty_c)
);
/* Stage 10 - Address generator */
wire adrgen_busy;
wire adrgen_pipe_stb;
wire adrgen_pipe_ack;
wire [fml_depth-1-1:0] dadr;
wire [fml_depth-1-1:0] tadra;
wire [fml_depth-1-1:0] tadrb;
wire [fml_depth-1-1:0] tadrc;
wire [fml_depth-1-1:0] tadrd;
wire [5:0] x_frac;
wire [5:0] y_frac;
tmu2_adrgen #(
.fml_depth(fml_depth)
) adrgen (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(adrgen_busy),
.pipe_stb_i(clamp_pipe_stb),
.pipe_ack_o(clamp_pipe_ack),
.dx_c(dstx_c),
.dy_c(dsty_c),
.tx_c(tx_c),
.ty_c(ty_c),
.dst_fbuf(dst_fbuf),
.dst_hres(dst_hres),
.tex_fbuf(tex_fbuf),
.tex_hres(tex_hres),
.pipe_stb_o(adrgen_pipe_stb),
.pipe_ack_i(adrgen_pipe_ack),
.dadr(dadr),
.tadra(tadra),
.tadrb(tadrb),
.tadrc(tadrc),
.tadrd(tadrd),
.x_frac(x_frac),
.y_frac(y_frac)
);
/* Stage 11 - Texel cache */
wire texcache_busy;
wire texcache_pipe_stb;
wire texcache_pipe_ack;
wire [fml_depth-1-1:0] dadr_f;
wire [15:0] tcolora;
wire [15:0] tcolorb;
wire [15:0] tcolorc;
wire [15:0] tcolord;
wire [5:0] x_frac_f;
wire [5:0] y_frac_f;
tmu2_texcache #(
.cache_depth(texel_cache_depth),
.fml_depth(fml_depth)
) texcache (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.fml_adr(fmlr_adr),
.fml_stb(fmlr_stb),
.fml_ack(fmlr_ack),
.fml_di(fmlr_di),
.flush(start),
.busy(texcache_busy),
.pipe_stb_i(adrgen_pipe_stb),
.pipe_ack_o(adrgen_pipe_ack),
.dadr(dadr),
.tadra(tadra),
.tadrb(tadrb),
.tadrc(tadrc),
.tadrd(tadrd),
.x_frac(x_frac),
.y_frac(y_frac),
.pipe_stb_o(texcache_pipe_stb),
.pipe_ack_i(texcache_pipe_ack),
.dadr_f(dadr_f),
.tcolora(tcolora),
.tcolorb(tcolorb),
.tcolorc(tcolorc),
.tcolord(tcolord),
.x_frac_f(x_frac_f),
.y_frac_f(y_frac_f),
.c_req_a(c_req_a),
.c_hit_a(c_hit_a),
.c_req_b(c_req_b),
.c_hit_b(c_hit_b),
.c_req_c(c_req_c),
.c_hit_c(c_hit_c),
.c_req_d(c_req_d),
.c_hit_d(c_hit_d)
);
/* Stage 11 - Blend neighbouring pixels for bilinear filtering */
wire blend_busy;
wire blend_pipe_stb;
wire blend_pipe_ack;
wire [fml_depth-1-1:0] dadr_f2;
wire [15:0] color;
tmu2_blend #(
.fml_depth(fml_depth)
) blend (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(blend_busy),
.pipe_stb_i(texcache_pipe_stb),
.pipe_ack_o(texcache_pipe_ack),
.dadr(dadr_f),
.colora(tcolora),
.colorb(tcolorb),
.colorc(tcolorc),
.colord(tcolord),
.x_frac(x_frac_f),
.y_frac(y_frac_f),
.pipe_stb_o(blend_pipe_stb),
.pipe_ack_i(blend_pipe_ack),
.dadr_f(dadr_f2),
.color(color)
);
/* Stage 11 - Apply decay effect and chroma key filtering. */
wire decay_busy;
wire decay_pipe_stb;
wire decay_pipe_ack;
wire [15:0] color_d;
wire [fml_depth-1-1:0] dadr_f3;
tmu2_decay #(
.fml_depth(fml_depth)
) decay (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(decay_busy),
.brightness(brightness),
.chroma_key_en(chroma_key_en),
.chroma_key(chroma_key),
.pipe_stb_i(blend_pipe_stb),
.pipe_ack_o(blend_pipe_ack),
.color(color),
.dadr(dadr_f2),
.pipe_stb_o(decay_pipe_stb),
.pipe_ack_i(decay_pipe_ack),
.color_d(color_d),
.dadr_f(dadr_f3)
);
`ifdef TMU_HAS_ALPHA
/* Stage 12 - Fetch destination pixel for alpha blending */
wire fdest_busy;
wire fdest_pipe_stb;
wire fdest_pipe_ack;
wire [15:0] color_d_f;
wire [fml_depth-1-1:0] dadr_f4;
wire [15:0] dcolor;
tmu2_fdest #(
.fml_depth(fml_depth)
) fdest (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.fml_adr(fmldr_adr),
.fml_stb(fmldr_stb),
.fml_ack(fmldr_ack),
.fml_di(fmldr_di),
.flush(start),
.busy(fdest_busy),
.fetch_en(alpha_en),
.pipe_stb_i(decay_pipe_stb),
.pipe_ack_o(decay_pipe_ack),
.color(color_d),
.dadr(dadr_f3),
.pipe_stb_o(fdest_pipe_stb),
.pipe_ack_i(fdest_pipe_ack),
.color_f(color_d_f),
.dadr_f(dadr_f4),
.dcolor(dcolor)
);
/* Stage 13 - Alpha blending */
wire alpha_busy;
wire alpha_pipe_stb;
wire alpha_pipe_ack;
wire [fml_depth-1-1:0] dadr_f5;
wire [15:0] acolor;
tmu2_alpha #(
.fml_depth(fml_depth)
) u_alpha (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(alpha_busy),
.alpha(alpha),
.pipe_stb_i(fdest_pipe_stb),
.pipe_ack_o(fdest_pipe_ack),
.color(color_d_f),
.dadr(dadr_f4),
.dcolor(dcolor),
.pipe_stb_o(alpha_pipe_stb),
.pipe_ack_i(alpha_pipe_ack),
.dadr_f(dadr_f5),
.acolor(acolor)
);
`else
assign fmldr_adr = {fml_depth{1'bx}};
assign fmldr_stb = 1'b0;
`endif
/* Stage 14 - Burst assembler */
reg burst_flush;
wire burst_busy;
wire burst_pipe_stb;
wire burst_pipe_ack;
wire [fml_depth-5-1:0] burst_addr;
wire [15:0] burst_sel;
wire [255:0] burst_do;
tmu2_burst #(
.fml_depth(fml_depth)
) burst (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.flush(burst_flush),
.busy(burst_busy),
`ifdef TMU_HAS_ALPHA
.pipe_stb_i(alpha_pipe_stb),
.pipe_ack_o(alpha_pipe_ack),
.color(acolor),
.dadr(dadr_f5),
`else
.pipe_stb_i(decay_pipe_stb),
.pipe_ack_o(decay_pipe_ack),
.color(color_d),
.dadr(dadr_f3),
`endif
.pipe_stb_o(burst_pipe_stb),
.pipe_ack_i(burst_pipe_ack),
.burst_addr(burst_addr),
.burst_sel(burst_sel),
.burst_do(burst_do)
);
/* Stage 15 - Pixel output */
wire pixout_busy;
tmu2_pixout #(
.fml_depth(fml_depth)
) pixout (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.busy(pixout_busy),
.pipe_stb_i(burst_pipe_stb),
.pipe_ack_o(burst_pipe_ack),
.burst_addr(burst_addr),
.burst_sel(burst_sel),
.burst_do(burst_do),
.fml_adr(fmlw_adr),
.fml_stb(fmlw_stb),
.fml_ack(fmlw_ack),
.fml_sel(fmlw_sel),
.fml_do(fmlw_do)
);
/* FSM to flush the burst assembler at the end */
wire pipeline_busy = fetchvertex_busy
|vdivops_busy|vdiv_busy|vinterp_busy
|hdivops_busy|hdiv_busy|hinterp_busy
|mask_busy|clamp_busy
|texcache_busy
|blend_busy|decay_busy
`ifdef TMU_HAS_ALPHA
|fdest_busy|alpha_busy
`endif
|burst_busy|pixout_busy;
parameter IDLE = 2'd0;
parameter WAIT_PROCESS = 2'd1;
parameter FLUSH = 2'd2;
parameter WAIT_FLUSH = 2'd3;
reg [1:0] state;
reg [1:0] next_state;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
next_state = state;
busy = 1'b1;
burst_flush = 1'b0;
case(state)
IDLE: begin
busy = 1'b0;
if(start)
next_state = WAIT_PROCESS;
end
WAIT_PROCESS: begin
if(~pipeline_busy)
next_state = FLUSH;
end
FLUSH: begin
burst_flush = 1'b1;
next_state = WAIT_FLUSH;
end
WAIT_FLUSH: begin
if(~pipeline_busy)
next_state = IDLE;
end
endcase
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Gigabit Transceiver for UltraScale+ devices
// /___/ /\ Filename : GTHE4_CHANNEL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTHE4_CHANNEL #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0,
parameter [0:0] ACJTAG_MODE = 1'b0,
parameter [0:0] ACJTAG_RESET = 1'b0,
parameter [15:0] ADAPT_CFG0 = 16'h9200,
parameter [15:0] ADAPT_CFG1 = 16'h801C,
parameter [15:0] ADAPT_CFG2 = 16'h0000,
parameter ALIGN_COMMA_DOUBLE = "FALSE",
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111,
parameter integer ALIGN_COMMA_WORD = 1,
parameter ALIGN_MCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011,
parameter ALIGN_PCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100,
parameter [0:0] A_RXOSCALRESET = 1'b0,
parameter [0:0] A_RXPROGDIVRESET = 1'b0,
parameter [0:0] A_RXTERMINATION = 1'b1,
parameter [4:0] A_TXDIFFCTRL = 5'b01100,
parameter [0:0] A_TXPROGDIVRESET = 1'b0,
parameter [0:0] CAPBYPASS_FORCE = 1'b0,
parameter CBCC_DATA_SOURCE_SEL = "DECODED",
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0,
parameter [0:0] CFOK_PWRSVE_EN = 1'b1,
parameter CHAN_BOND_KEEP_ALIGN = "FALSE",
parameter integer CHAN_BOND_MAX_SKEW = 7,
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100,
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111,
parameter CHAN_BOND_SEQ_2_USE = "FALSE",
parameter integer CHAN_BOND_SEQ_LEN = 2,
parameter [15:0] CH_HSPMUX = 16'h2424,
parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000,
parameter [15:0] CKCAL_RSVD0 = 16'h4000,
parameter [15:0] CKCAL_RSVD1 = 16'h0000,
parameter CLK_CORRECT_USE = "TRUE",
parameter CLK_COR_KEEP_IDLE = "FALSE",
parameter integer CLK_COR_MAX_LAT = 20,
parameter integer CLK_COR_MIN_LAT = 18,
parameter CLK_COR_PRECEDENCE = "TRUE",
parameter integer CLK_COR_REPEAT_WAIT = 0,
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100,
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111,
parameter CLK_COR_SEQ_2_USE = "FALSE",
parameter integer CLK_COR_SEQ_LEN = 2,
parameter [15:0] CPLL_CFG0 = 16'h01FA,
parameter [15:0] CPLL_CFG1 = 16'h24A9,
parameter [15:0] CPLL_CFG2 = 16'h6807,
parameter [15:0] CPLL_CFG3 = 16'h0000,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 4,
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000,
parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0,
parameter [1:0] DDI_CTRL = 2'b00,
parameter integer DDI_REALIGN_WAIT = 15,
parameter DEC_MCOMMA_DETECT = "TRUE",
parameter DEC_PCOMMA_DETECT = "TRUE",
parameter DEC_VALID_COMMA_ONLY = "TRUE",
parameter [0:0] DELAY_ELEC = 1'b0,
parameter [9:0] DMONITOR_CFG0 = 10'h000,
parameter [7:0] DMONITOR_CFG1 = 8'h00,
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0,
parameter [5:0] ES_CONTROL = 6'b000000,
parameter ES_ERRDET_EN = "FALSE",
parameter ES_EYE_SCAN_EN = "FALSE",
parameter [11:0] ES_HORZ_OFFSET = 12'h800,
parameter [4:0] ES_PRESCALE = 5'b00000,
parameter [15:0] ES_QUALIFIER0 = 16'h0000,
parameter [15:0] ES_QUALIFIER1 = 16'h0000,
parameter [15:0] ES_QUALIFIER2 = 16'h0000,
parameter [15:0] ES_QUALIFIER3 = 16'h0000,
parameter [15:0] ES_QUALIFIER4 = 16'h0000,
parameter [15:0] ES_QUALIFIER5 = 16'h0000,
parameter [15:0] ES_QUALIFIER6 = 16'h0000,
parameter [15:0] ES_QUALIFIER7 = 16'h0000,
parameter [15:0] ES_QUALIFIER8 = 16'h0000,
parameter [15:0] ES_QUALIFIER9 = 16'h0000,
parameter [15:0] ES_QUAL_MASK0 = 16'h0000,
parameter [15:0] ES_QUAL_MASK1 = 16'h0000,
parameter [15:0] ES_QUAL_MASK2 = 16'h0000,
parameter [15:0] ES_QUAL_MASK3 = 16'h0000,
parameter [15:0] ES_QUAL_MASK4 = 16'h0000,
parameter [15:0] ES_QUAL_MASK5 = 16'h0000,
parameter [15:0] ES_QUAL_MASK6 = 16'h0000,
parameter [15:0] ES_QUAL_MASK7 = 16'h0000,
parameter [15:0] ES_QUAL_MASK8 = 16'h0000,
parameter [15:0] ES_QUAL_MASK9 = 16'h0000,
parameter [15:0] ES_SDATA_MASK0 = 16'h0000,
parameter [15:0] ES_SDATA_MASK1 = 16'h0000,
parameter [15:0] ES_SDATA_MASK2 = 16'h0000,
parameter [15:0] ES_SDATA_MASK3 = 16'h0000,
parameter [15:0] ES_SDATA_MASK4 = 16'h0000,
parameter [15:0] ES_SDATA_MASK5 = 16'h0000,
parameter [15:0] ES_SDATA_MASK6 = 16'h0000,
parameter [15:0] ES_SDATA_MASK7 = 16'h0000,
parameter [15:0] ES_SDATA_MASK8 = 16'h0000,
parameter [15:0] ES_SDATA_MASK9 = 16'h0000,
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0,
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111,
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111,
parameter FTS_LANE_DESKEW_EN = "FALSE",
parameter [4:0] GEARBOX_MODE = 5'b00000,
parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0,
parameter [0:0] LOCAL_MASTER = 1'b0,
parameter [2:0] LPBK_BIAS_CTRL = 3'b000,
parameter [0:0] LPBK_EN_RCAL_B = 1'b0,
parameter [3:0] LPBK_EXT_RCAL = 4'b0000,
parameter [2:0] LPBK_IND_CTRL0 = 3'b000,
parameter [2:0] LPBK_IND_CTRL1 = 3'b000,
parameter [2:0] LPBK_IND_CTRL2 = 3'b000,
parameter [3:0] LPBK_RG_CTRL = 4'b0000,
parameter [1:0] OOBDIVCTL = 2'b00,
parameter [0:0] OOB_PWRUP = 1'b0,
parameter PCI3_AUTO_REALIGN = "FRST_SMPL",
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1,
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00,
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0,
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000,
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000,
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000,
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0,
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0,
parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000,
parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000,
parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000,
parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100,
parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000,
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000,
parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0,
parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0,
parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0,
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000,
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000,
parameter PCS_PCIE_EN = "FALSE",
parameter [15:0] PCS_RSVD0 = 16'b0000000000000000,
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C,
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19,
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64,
parameter integer PREIQ_FREQ_BST = 0,
parameter [2:0] PROCESS_PAR = 3'b010,
parameter [0:0] RATE_SW_USE_DRP = 1'b0,
parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0,
parameter [0:0] RCLK_SIPO_INV_EN = 1'b0,
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0,
parameter [2:0] RTX_BUF_CML_CTRL = 3'b010,
parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00,
parameter [4:0] RXBUFRESET_TIME = 5'b00001,
parameter RXBUF_ADDR_MODE = "FULL",
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000,
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000,
parameter RXBUF_EN = "TRUE",
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE",
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE",
parameter RXBUF_RESET_ON_EIDLE = "FALSE",
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE",
parameter integer RXBUF_THRESH_OVFLW = 0,
parameter RXBUF_THRESH_OVRD = "FALSE",
parameter integer RXBUF_THRESH_UNDFLW = 4,
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001,
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001,
parameter [15:0] RXCDR_CFG0 = 16'h0003,
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003,
parameter [15:0] RXCDR_CFG1 = 16'h0000,
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG2 = 16'h0164,
parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164,
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034,
parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034,
parameter [15:0] RXCDR_CFG3 = 16'h0024,
parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024,
parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024,
parameter [15:0] RXCDR_CFG4 = 16'h5CF6,
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6,
parameter [15:0] RXCDR_CFG5 = 16'hB46B,
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B,
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0,
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0,
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040,
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000,
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000,
parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000,
parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000,
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0,
parameter [15:0] RXCFOK_CFG0 = 16'h0000,
parameter [15:0] RXCFOK_CFG1 = 16'h0002,
parameter [15:0] RXCFOK_CFG2 = 16'h002D,
parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000,
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111,
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000,
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022,
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100,
parameter [15:0] RXDFE_CFG0 = 16'h4000,
parameter [15:0] RXDFE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H3_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H3_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H4_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003,
parameter [15:0] RXDFE_H5_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H5_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H6_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H6_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H7_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H7_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H8_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H8_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H9_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H9_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HA_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HA_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HB_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HB_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG1 = 16'h0002,
parameter [15:0] RXDFE_KH_CFG0 = 16'h0000,
parameter [15:0] RXDFE_KH_CFG1 = 16'h0000,
parameter [15:0] RXDFE_KH_CFG2 = 16'h0000,
parameter [15:0] RXDFE_KH_CFG3 = 16'h0000,
parameter [15:0] RXDFE_OS_CFG0 = 16'h0000,
parameter [15:0] RXDFE_OS_CFG1 = 16'h0002,
parameter [0:0] RXDFE_PWR_SAVING = 1'b0,
parameter [15:0] RXDFE_UT_CFG0 = 16'h0000,
parameter [15:0] RXDFE_UT_CFG1 = 16'h0002,
parameter [15:0] RXDFE_UT_CFG2 = 16'h0000,
parameter [15:0] RXDFE_VP_CFG0 = 16'h0000,
parameter [15:0] RXDFE_VP_CFG1 = 16'h0022,
parameter [15:0] RXDLY_CFG = 16'h0010,
parameter [15:0] RXDLY_LCFG = 16'h0030,
parameter RXELECIDLE_CFG = "SIGCFG_4",
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter RXGEARBOX_EN = "FALSE",
parameter [4:0] RXISCANRESET_TIME = 5'b00001,
parameter [15:0] RXLPM_CFG = 16'h0000,
parameter [15:0] RXLPM_GC_CFG = 16'h1000,
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000,
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002,
parameter [15:0] RXLPM_OS_CFG0 = 16'h0000,
parameter [15:0] RXLPM_OS_CFG1 = 16'h0000,
parameter [8:0] RXOOB_CFG = 9'b000110000,
parameter RXOOB_CLK_CFG = "PMA",
parameter [4:0] RXOSCALRESET_TIME = 5'b00011,
parameter integer RXOUT_DIV = 4,
parameter [4:0] RXPCSRESET_TIME = 5'b00001,
parameter [15:0] RXPHBEACON_CFG = 16'h0000,
parameter [15:0] RXPHDLY_CFG = 16'h2020,
parameter [15:0] RXPHSAMP_CFG = 16'h2100,
parameter [15:0] RXPHSLIP_CFG = 16'h9933,
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000,
parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0,
parameter [15:0] RXPI_CFG0 = 16'h0002,
parameter [15:0] RXPI_CFG1 = 16'b0000000000000000,
parameter [0:0] RXPI_LPM = 1'b0,
parameter [1:0] RXPI_SEL_LC = 2'b00,
parameter [1:0] RXPI_STARTCODE = 2'b00,
parameter [0:0] RXPI_VREFSEL = 1'b0,
parameter RXPMACLK_SEL = "DATA",
parameter [4:0] RXPMARESET_TIME = 5'b00001,
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0,
parameter integer RXPRBS_LINKACQ_CNT = 15,
parameter [0:0] RXREFCLKDIV2_SEL = 1'b0,
parameter integer RXSLIDE_AUTO_WAIT = 7,
parameter RXSLIDE_MODE = "OFF",
parameter [0:0] RXSYNC_MULTILANE = 1'b0,
parameter [0:0] RXSYNC_OVRD = 1'b0,
parameter [0:0] RXSYNC_SKIP_DA = 1'b0,
parameter [0:0] RX_AFE_CM_EN = 1'b0,
parameter [15:0] RX_BIAS_CFG0 = 16'h12B0,
parameter [5:0] RX_BUFFER_CFG = 6'b000000,
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0,
parameter integer RX_CLK25_DIV = 8,
parameter [0:0] RX_CLKMUX_EN = 1'b1,
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000,
parameter [3:0] RX_CM_BUF_CFG = 4'b1010,
parameter [0:0] RX_CM_BUF_PD = 1'b0,
parameter integer RX_CM_SEL = 3,
parameter integer RX_CM_TRIM = 12,
parameter [7:0] RX_CTLE3_LPF = 8'b00000000,
parameter integer RX_DATA_WIDTH = 20,
parameter [5:0] RX_DDI_SEL = 6'b000000,
parameter RX_DEFER_RESET_BUF_EN = "TRUE",
parameter [2:0] RX_DEGEN_CTRL = 3'b011,
parameter integer RX_DFELPM_CFG0 = 0,
parameter [0:0] RX_DFELPM_CFG1 = 1'b1,
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1,
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00,
parameter integer RX_DFE_AGC_CFG1 = 4,
parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1,
parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4,
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01,
parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4,
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0,
parameter RX_DISPERR_SEQ_MATCH = "TRUE",
parameter [0:0] RX_DIV2_MODE_B = 1'b0,
parameter [4:0] RX_DIVRESET_TIME = 5'b00001,
parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0,
parameter [0:0] RX_EN_HI_LR = 1'b1,
parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000,
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000,
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0,
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00,
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0,
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0,
parameter integer RX_INT_DATAWIDTH = 1,
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0,
parameter [15:0] RX_PMA_RSV0 = 16'h0000,
parameter real RX_PROGDIV_CFG = 0.0,
parameter [15:0] RX_PROGDIV_RATE = 16'h0001,
parameter [3:0] RX_RESLOAD_CTRL = 4'b0000,
parameter [0:0] RX_RESLOAD_OVRD = 1'b0,
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101,
parameter integer RX_SIG_VALID_DLY = 11,
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0,
parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001,
parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000,
parameter [3:0] RX_SUM_VCMTUNE = 4'b1010,
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0,
parameter [2:0] RX_SUM_VREF_TUNE = 3'b100,
parameter [1:0] RX_TUNE_AFE_OS = 2'b00,
parameter [2:0] RX_VREG_CTRL = 3'b101,
parameter [0:0] RX_VREG_PDB = 1'b1,
parameter [1:0] RX_WIDEMODE_CDR = 2'b01,
parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01,
parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01,
parameter RX_XCLK_SEL = "RXDES",
parameter [0:0] RX_XMODE_SEL = 1'b0,
parameter [0:0] SAMPLE_CLK_PHASE = 1'b0,
parameter [0:0] SAS_12G_MODE = 1'b0,
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111,
parameter [2:0] SATA_BURST_VAL = 3'b100,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [2:0] SATA_EIDLE_VAL = 3'b100,
parameter SHOW_REALIGN_COMMA = "TRUE",
parameter SIM_DEVICE = "ULTRASCALE_PLUS",
parameter SIM_MODE = "FAST",
parameter SIM_RECEIVER_DETECT_PASS = "TRUE",
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z",
parameter [0:0] SRSTMODE = 1'b0,
parameter [1:0] TAPDLY_SET_TX = 2'h0,
parameter [3:0] TEMPERATURE_PAR = 4'b0010,
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000,
parameter [2:0] TERM_RCAL_OVRD = 3'b000,
parameter [7:0] TRANS_TIME_RATE = 8'h0E,
parameter [7:0] TST_RSV0 = 8'h00,
parameter [7:0] TST_RSV1 = 8'h00,
parameter TXBUF_EN = "TRUE",
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE",
parameter [15:0] TXDLY_CFG = 16'h0010,
parameter [15:0] TXDLY_LCFG = 16'h0030,
parameter [3:0] TXDRVBIAS_N = 4'b1010,
parameter TXFIFO_ADDR_CFG = "LOW",
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter TXGEARBOX_EN = "FALSE",
parameter integer TXOUT_DIV = 4,
parameter [4:0] TXPCSRESET_TIME = 5'b00001,
parameter [15:0] TXPHDLY_CFG0 = 16'h6020,
parameter [15:0] TXPHDLY_CFG1 = 16'h0002,
parameter [15:0] TXPH_CFG = 16'h0123,
parameter [15:0] TXPH_CFG2 = 16'h0000,
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000,
parameter [15:0] TXPI_CFG = 16'h0000,
parameter [1:0] TXPI_CFG0 = 2'b00,
parameter [1:0] TXPI_CFG1 = 2'b00,
parameter [1:0] TXPI_CFG2 = 2'b00,
parameter [0:0] TXPI_CFG3 = 1'b0,
parameter [0:0] TXPI_CFG4 = 1'b1,
parameter [2:0] TXPI_CFG5 = 3'b000,
parameter [0:0] TXPI_GRAY_SEL = 1'b0,
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0,
parameter [0:0] TXPI_LPM = 1'b0,
parameter [0:0] TXPI_PPM = 1'b0,
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2",
parameter [7:0] TXPI_PPM_CFG = 8'b00000000,
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000,
parameter [0:0] TXPI_VREFSEL = 1'b0,
parameter [4:0] TXPMARESET_TIME = 5'b00001,
parameter [0:0] TXREFCLKDIV2_SEL = 1'b0,
parameter [0:0] TXSYNC_MULTILANE = 1'b0,
parameter [0:0] TXSYNC_OVRD = 1'b0,
parameter [0:0] TXSYNC_SKIP_DA = 1'b0,
parameter integer TX_CLK25_DIV = 8,
parameter [0:0] TX_CLKMUX_EN = 1'b1,
parameter integer TX_DATA_WIDTH = 20,
parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000,
parameter [5:0] TX_DEEMPH0 = 6'b000000,
parameter [5:0] TX_DEEMPH1 = 6'b000000,
parameter [5:0] TX_DEEMPH2 = 6'b000000,
parameter [5:0] TX_DEEMPH3 = 6'b000000,
parameter [4:0] TX_DIVRESET_TIME = 5'b00001,
parameter TX_DRIVE_MODE = "DIRECT",
parameter integer TX_DRVMUX_CTRL = 2,
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110,
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100,
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0,
parameter [0:0] TX_FIFO_BYP_EN = 1'b0,
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0,
parameter integer TX_INT_DATAWIDTH = 1,
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE",
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0,
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110,
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001,
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101,
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010,
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110,
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100,
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010,
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000,
parameter [15:0] TX_PHICAL_CFG0 = 16'h0000,
parameter [15:0] TX_PHICAL_CFG1 = 16'h003F,
parameter [15:0] TX_PHICAL_CFG2 = 16'h0000,
parameter integer TX_PI_BIASSET = 0,
parameter [1:0] TX_PI_IBIAS_MID = 2'b00,
parameter [0:0] TX_PMADATA_OPT = 1'b0,
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0,
parameter [15:0] TX_PMA_RSV0 = 16'h0008,
parameter integer TX_PREDRV_CTRL = 2,
parameter TX_PROGCLK_SEL = "POSTPI",
parameter real TX_PROGDIV_CFG = 0.0,
parameter [15:0] TX_PROGDIV_RATE = 16'h0001,
parameter [0:0] TX_QPI_STATUS_EN = 1'b0,
parameter [13:0] TX_RXDETECT_CFG = 14'h0032,
parameter integer TX_RXDETECT_REF = 3,
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101,
parameter [0:0] TX_SARC_LPBK_ENB = 1'b0,
parameter [1:0] TX_SW_MEAS = 2'b00,
parameter [2:0] TX_VREG_CTRL = 3'b000,
parameter [0:0] TX_VREG_PDB = 1'b0,
parameter [1:0] TX_VREG_VREFSEL = 2'b00,
parameter TX_XCLK_SEL = "TXOUT",
parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0,
parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111,
parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011,
parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0,
parameter [0:0] USB_EXT_CNTL = 1'b1,
parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011,
parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011,
parameter [8:0] USB_LFPSPING_BURST = 9'b000000101,
parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001,
parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100,
parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101,
parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011,
parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011,
parameter [3:0] USB_LFPS_TPERIOD = 4'b0011,
parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1,
parameter [0:0] USB_MODE = 1'b0,
parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0,
parameter integer USB_PING_SATA_MAX_INIT = 21,
parameter integer USB_PING_SATA_MIN_INIT = 12,
parameter integer USB_POLL_SATA_MAX_BURST = 8,
parameter integer USB_POLL_SATA_MIN_BURST = 4,
parameter [0:0] USB_RAW_ELEC = 1'b0,
parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1,
parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1,
parameter integer USB_U1_SATA_MAX_WAKE = 7,
parameter integer USB_U1_SATA_MIN_WAKE = 4,
parameter integer USB_U2_SAS_MAX_COM = 64,
parameter integer USB_U2_SAS_MIN_COM = 36,
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0,
parameter [0:0] Y_ALL_MODE = 1'b0
)(
output BUFGTCE,
output [2:0] BUFGTCEMASK,
output [8:0] BUFGTDIV,
output BUFGTRESET,
output [2:0] BUFGTRSTMASK,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output [15:0] DMONITOROUT,
output DMONITOROUTCLK,
output [15:0] DRPDO,
output DRPRDY,
output EYESCANDATAERROR,
output GTHTXN,
output GTHTXP,
output GTPOWERGOOD,
output GTREFCLKMONITOR,
output PCIERATEGEN3,
output PCIERATEIDLE,
output [1:0] PCIERATEQPLLPD,
output [1:0] PCIERATEQPLLRESET,
output PCIESYNCTXSYNCDONE,
output PCIEUSERGEN3RDY,
output PCIEUSERPHYSTATUSRST,
output PCIEUSERRATESTART,
output [15:0] PCSRSVDOUT,
output PHYSTATUS,
output [15:0] PINRSRVDAS,
output POWERPRESENT,
output RESETEXCEPTION,
output [2:0] RXBUFSTATUS,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCDRPHDONE,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output [4:0] RXCHBONDO,
output RXCKCALDONE,
output [1:0] RXCLKCORCNT,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output [15:0] RXCTRL0,
output [15:0] RXCTRL1,
output [7:0] RXCTRL2,
output [7:0] RXCTRL3,
output [127:0] RXDATA,
output [7:0] RXDATAEXTENDRSVD,
output [1:0] RXDATAVALID,
output RXDLYSRESETDONE,
output RXELECIDLE,
output [5:0] RXHEADER,
output [1:0] RXHEADERVALID,
output RXLFPSTRESETDET,
output RXLFPSU2LPEXITDET,
output RXLFPSU3WAKEDET,
output [7:0] RXMONITOROUT,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPHALIGNERR,
output RXPMARESETDONE,
output RXPRBSERR,
output RXPRBSLOCKED,
output RXPRGDIVRESETDONE,
output RXQPISENN,
output RXQPISENP,
output RXRATEDONE,
output RXRECCLKOUT,
output RXRESETDONE,
output RXSLIDERDY,
output RXSLIPDONE,
output RXSLIPOUTCLKRDY,
output RXSLIPPMARDY,
output [1:0] RXSTARTOFSEQ,
output [2:0] RXSTATUS,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output [1:0] TXBUFSTATUS,
output TXCOMFINISH,
output TXDCCDONE,
output TXDLYSRESETDONE,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXPRGDIVRESETDONE,
output TXQPISENN,
output TXQPISENP,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
input CDRSTEPDIR,
input CDRSTEPSQ,
input CDRSTEPSX,
input CFGRESET,
input CLKRSVD0,
input CLKRSVD1,
input CPLLFREQLOCK,
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input [2:0] CPLLREFCLKSEL,
input CPLLRESET,
input DMONFIFORESET,
input DMONITORCLK,
input [9:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPRST,
input DRPWE,
input EYESCANRESET,
input EYESCANTRIGGER,
input FREQOS,
input GTGREFCLK,
input GTHRXN,
input GTHRXP,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input [15:0] GTRSVD,
input GTRXRESET,
input GTRXRESETSEL,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input GTTXRESET,
input GTTXRESETSEL,
input INCPCTRL,
input [2:0] LOOPBACK,
input PCIEEQRXEQADAPTDONE,
input PCIERSTIDLE,
input PCIERSTTXSYNCSTART,
input PCIEUSERRATEDONE,
input [15:0] PCSRSVDIN,
input QPLL0CLK,
input QPLL0FREQLOCK,
input QPLL0REFCLK,
input QPLL1CLK,
input QPLL1FREQLOCK,
input QPLL1REFCLK,
input RESETOVRD,
input RX8B10BEN,
input RXAFECFOKEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCHBONDEN,
input [4:0] RXCHBONDI,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCKCALRESET,
input [6:0] RXCKCALSTART,
input RXCOMMADETEN,
input [1:0] RXDFEAGCCTRL,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input [3:0] RXDFECFOKFCNUM,
input RXDFECFOKFEN,
input RXDFECFOKFPULSE,
input RXDFECFOKHOLD,
input RXDFECFOKOVREN,
input RXDFEKHHOLD,
input RXDFEKHOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFELPMRESET,
input RXDFETAP10HOLD,
input RXDFETAP10OVRDEN,
input RXDFETAP11HOLD,
input RXDFETAP11OVRDEN,
input RXDFETAP12HOLD,
input RXDFETAP12OVRDEN,
input RXDFETAP13HOLD,
input RXDFETAP13OVRDEN,
input RXDFETAP14HOLD,
input RXDFETAP14OVRDEN,
input RXDFETAP15HOLD,
input RXDFETAP15OVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFETAP6HOLD,
input RXDFETAP6OVRDEN,
input RXDFETAP7HOLD,
input RXDFETAP7OVRDEN,
input RXDFETAP8HOLD,
input RXDFETAP8OVRDEN,
input RXDFETAP9HOLD,
input RXDFETAP9OVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input [1:0] RXELECIDLEMODE,
input RXEQTRAINING,
input RXGEARBOXSLIP,
input RXLATCLK,
input RXLPMEN,
input RXLPMGCHOLD,
input RXLPMGCOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMOSHOLD,
input RXLPMOSOVRDEN,
input RXMCOMMAALIGNEN,
input [1:0] RXMONITORSEL,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input RXOSOVRDEN,
input [2:0] RXOUTCLKSEL,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input [1:0] RXPD,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input RXPHOVRDEN,
input [1:0] RXPLLCLKSEL,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input [3:0] RXPRBSSEL,
input RXPROGDIVRESET,
input RXQPIEN,
input [2:0] RXRATE,
input RXRATEMODE,
input RXSLIDE,
input RXSLIPOUTCLK,
input RXSLIPPMA,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input [1:0] RXSYSCLKSEL,
input RXTERMINATION,
input RXUSERRDY,
input RXUSRCLK,
input RXUSRCLK2,
input SIGVALIDCLK,
input [19:0] TSTIN,
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input [15:0] TXCTRL0,
input [15:0] TXCTRL1,
input [7:0] TXCTRL2,
input [127:0] TXDATA,
input [7:0] TXDATAEXTENDRSVD,
input TXDCCFORCESTART,
input TXDCCRESET,
input [1:0] TXDEEMPH,
input TXDETECTRX,
input [4:0] TXDIFFCTRL,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input [5:0] TXHEADER,
input TXINHIBIT,
input TXLATCLK,
input TXLFPSTRESET,
input TXLFPSU2LPEXIT,
input TXLFPSU3WAKE,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input TXMUXDCDEXHOLD,
input TXMUXDCDORWREN,
input TXONESZEROS,
input [2:0] TXOUTCLKSEL,
input TXPCSRESET,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input [4:0] TXPIPPMSTEPSIZE,
input TXPISOPD,
input [1:0] TXPLLCLKSEL,
input TXPMARESET,
input TXPOLARITY,
input [4:0] TXPOSTCURSOR,
input TXPRBSFORCEERR,
input [3:0] TXPRBSSEL,
input [4:0] TXPRECURSOR,
input TXPROGDIVRESET,
input TXQPIBIASEN,
input TXQPIWEAKPUP,
input [2:0] TXRATE,
input TXRATEMODE,
input [6:0] TXSEQUENCE,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input [1:0] TXSYSCLKSEL,
input TXUSERRDY,
input TXUSRCLK,
input TXUSRCLK2
);
// define constants
localparam MODULE_NAME = "GTHE4_CHANNEL";
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "GTHE4_CHANNEL_dr.v"
`else
reg [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE;
reg [0:0] ACJTAG_MODE_REG = ACJTAG_MODE;
reg [0:0] ACJTAG_RESET_REG = ACJTAG_RESET;
reg [15:0] ADAPT_CFG0_REG = ADAPT_CFG0;
reg [15:0] ADAPT_CFG1_REG = ADAPT_CFG1;
reg [15:0] ADAPT_CFG2_REG = ADAPT_CFG2;
reg [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE;
reg [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE;
reg [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD;
reg [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET;
reg [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE;
reg [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET;
reg [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE;
reg [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET;
reg [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET;
reg [0:0] A_RXTERMINATION_REG = A_RXTERMINATION;
reg [4:0] A_TXDIFFCTRL_REG = A_TXDIFFCTRL;
reg [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET;
reg [0:0] CAPBYPASS_FORCE_REG = CAPBYPASS_FORCE;
reg [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL;
reg [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN;
reg [0:0] CFOK_PWRSVE_EN_REG = CFOK_PWRSVE_EN;
reg [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN;
reg [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW;
reg [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1;
reg [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2;
reg [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3;
reg [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4;
reg [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE;
reg [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1;
reg [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2;
reg [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3;
reg [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4;
reg [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE;
reg [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE;
reg [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN;
reg [15:0] CH_HSPMUX_REG = CH_HSPMUX;
reg [15:0] CKCAL1_CFG_0_REG = CKCAL1_CFG_0;
reg [15:0] CKCAL1_CFG_1_REG = CKCAL1_CFG_1;
reg [15:0] CKCAL1_CFG_2_REG = CKCAL1_CFG_2;
reg [15:0] CKCAL1_CFG_3_REG = CKCAL1_CFG_3;
reg [15:0] CKCAL2_CFG_0_REG = CKCAL2_CFG_0;
reg [15:0] CKCAL2_CFG_1_REG = CKCAL2_CFG_1;
reg [15:0] CKCAL2_CFG_2_REG = CKCAL2_CFG_2;
reg [15:0] CKCAL2_CFG_3_REG = CKCAL2_CFG_3;
reg [15:0] CKCAL2_CFG_4_REG = CKCAL2_CFG_4;
reg [15:0] CKCAL_RSVD0_REG = CKCAL_RSVD0;
reg [15:0] CKCAL_RSVD1_REG = CKCAL_RSVD1;
reg [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE;
reg [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE;
reg [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT;
reg [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT;
reg [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE;
reg [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT;
reg [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1;
reg [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2;
reg [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3;
reg [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4;
reg [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE;
reg [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1;
reg [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2;
reg [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3;
reg [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4;
reg [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE;
reg [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE;
reg [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN;
reg [15:0] CPLL_CFG0_REG = CPLL_CFG0;
reg [15:0] CPLL_CFG1_REG = CPLL_CFG1;
reg [15:0] CPLL_CFG2_REG = CPLL_CFG2;
reg [15:0] CPLL_CFG3_REG = CPLL_CFG3;
reg [4:0] CPLL_FBDIV_REG = CPLL_FBDIV;
reg [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45;
reg [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0;
reg [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG;
reg [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV;
reg [2:0] CTLE3_OCAP_EXT_CTRL_REG = CTLE3_OCAP_EXT_CTRL;
reg [0:0] CTLE3_OCAP_EXT_EN_REG = CTLE3_OCAP_EXT_EN;
reg [1:0] DDI_CTRL_REG = DDI_CTRL;
reg [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT;
reg [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT;
reg [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT;
reg [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY;
reg [0:0] DELAY_ELEC_REG = DELAY_ELEC;
reg [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0;
reg [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1;
reg [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL;
reg [5:0] ES_CONTROL_REG = ES_CONTROL;
reg [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN;
reg [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN;
reg [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET;
reg [4:0] ES_PRESCALE_REG = ES_PRESCALE;
reg [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0;
reg [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1;
reg [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2;
reg [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3;
reg [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4;
reg [15:0] ES_QUALIFIER5_REG = ES_QUALIFIER5;
reg [15:0] ES_QUALIFIER6_REG = ES_QUALIFIER6;
reg [15:0] ES_QUALIFIER7_REG = ES_QUALIFIER7;
reg [15:0] ES_QUALIFIER8_REG = ES_QUALIFIER8;
reg [15:0] ES_QUALIFIER9_REG = ES_QUALIFIER9;
reg [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0;
reg [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1;
reg [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2;
reg [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3;
reg [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4;
reg [15:0] ES_QUAL_MASK5_REG = ES_QUAL_MASK5;
reg [15:0] ES_QUAL_MASK6_REG = ES_QUAL_MASK6;
reg [15:0] ES_QUAL_MASK7_REG = ES_QUAL_MASK7;
reg [15:0] ES_QUAL_MASK8_REG = ES_QUAL_MASK8;
reg [15:0] ES_QUAL_MASK9_REG = ES_QUAL_MASK9;
reg [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0;
reg [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1;
reg [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2;
reg [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3;
reg [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4;
reg [15:0] ES_SDATA_MASK5_REG = ES_SDATA_MASK5;
reg [15:0] ES_SDATA_MASK6_REG = ES_SDATA_MASK6;
reg [15:0] ES_SDATA_MASK7_REG = ES_SDATA_MASK7;
reg [15:0] ES_SDATA_MASK8_REG = ES_SDATA_MASK8;
reg [15:0] ES_SDATA_MASK9_REG = ES_SDATA_MASK9;
reg [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN;
reg [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE;
reg [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG;
reg [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN;
reg [4:0] GEARBOX_MODE_REG = GEARBOX_MODE;
reg [0:0] ISCAN_CK_PH_SEL2_REG = ISCAN_CK_PH_SEL2;
reg [0:0] LOCAL_MASTER_REG = LOCAL_MASTER;
reg [2:0] LPBK_BIAS_CTRL_REG = LPBK_BIAS_CTRL;
reg [0:0] LPBK_EN_RCAL_B_REG = LPBK_EN_RCAL_B;
reg [3:0] LPBK_EXT_RCAL_REG = LPBK_EXT_RCAL;
reg [2:0] LPBK_IND_CTRL0_REG = LPBK_IND_CTRL0;
reg [2:0] LPBK_IND_CTRL1_REG = LPBK_IND_CTRL1;
reg [2:0] LPBK_IND_CTRL2_REG = LPBK_IND_CTRL2;
reg [3:0] LPBK_RG_CTRL_REG = LPBK_RG_CTRL;
reg [1:0] OOBDIVCTL_REG = OOBDIVCTL;
reg [0:0] OOB_PWRUP_REG = OOB_PWRUP;
reg [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN;
reg [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE;
reg [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS;
reg [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE;
reg [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT;
reg [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE;
reg [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT;
reg [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE;
reg [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE;
reg [4:0] PCIE3_CLK_COR_EMPTY_THRSH_REG = PCIE3_CLK_COR_EMPTY_THRSH;
reg [5:0] PCIE3_CLK_COR_FULL_THRSH_REG = PCIE3_CLK_COR_FULL_THRSH;
reg [4:0] PCIE3_CLK_COR_MAX_LAT_REG = PCIE3_CLK_COR_MAX_LAT;
reg [4:0] PCIE3_CLK_COR_MIN_LAT_REG = PCIE3_CLK_COR_MIN_LAT;
reg [5:0] PCIE3_CLK_COR_THRSH_TIMER_REG = PCIE3_CLK_COR_THRSH_TIMER;
reg [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL;
reg [1:0] PCIE_PLL_SEL_MODE_GEN12_REG = PCIE_PLL_SEL_MODE_GEN12;
reg [1:0] PCIE_PLL_SEL_MODE_GEN3_REG = PCIE_PLL_SEL_MODE_GEN3;
reg [1:0] PCIE_PLL_SEL_MODE_GEN4_REG = PCIE_PLL_SEL_MODE_GEN4;
reg [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3;
reg [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG;
reg [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3;
reg [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG;
reg [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN;
reg [15:0] PCS_RSVD0_REG = PCS_RSVD0;
reg [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2;
reg [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2;
reg [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2;
reg [1:0] PREIQ_FREQ_BST_REG = PREIQ_FREQ_BST;
reg [2:0] PROCESS_PAR_REG = PROCESS_PAR;
reg [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP;
reg [0:0] RCLK_SIPO_DLY_ENB_REG = RCLK_SIPO_DLY_ENB;
reg [0:0] RCLK_SIPO_INV_EN_REG = RCLK_SIPO_INV_EN;
reg [0:0] RESET_POWERSAVE_DISABLE_REG = RESET_POWERSAVE_DISABLE;
reg [2:0] RTX_BUF_CML_CTRL_REG = RTX_BUF_CML_CTRL;
reg [1:0] RTX_BUF_TERM_CTRL_REG = RTX_BUF_TERM_CTRL;
reg [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME;
reg [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE;
reg [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT;
reg [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT;
reg [40:1] RXBUF_EN_REG = RXBUF_EN;
reg [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE;
reg [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN;
reg [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE;
reg [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE;
reg [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW;
reg [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD;
reg [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW;
reg [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME;
reg [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME;
reg [15:0] RXCDR_CFG0_REG = RXCDR_CFG0;
reg [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3;
reg [15:0] RXCDR_CFG1_REG = RXCDR_CFG1;
reg [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3;
reg [15:0] RXCDR_CFG2_REG = RXCDR_CFG2;
reg [9:0] RXCDR_CFG2_GEN2_REG = RXCDR_CFG2_GEN2;
reg [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3;
reg [15:0] RXCDR_CFG2_GEN4_REG = RXCDR_CFG2_GEN4;
reg [15:0] RXCDR_CFG3_REG = RXCDR_CFG3;
reg [5:0] RXCDR_CFG3_GEN2_REG = RXCDR_CFG3_GEN2;
reg [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3;
reg [15:0] RXCDR_CFG3_GEN4_REG = RXCDR_CFG3_GEN4;
reg [15:0] RXCDR_CFG4_REG = RXCDR_CFG4;
reg [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3;
reg [15:0] RXCDR_CFG5_REG = RXCDR_CFG5;
reg [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3;
reg [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE;
reg [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE;
reg [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0;
reg [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1;
reg [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2;
reg [15:0] RXCDR_LOCK_CFG3_REG = RXCDR_LOCK_CFG3;
reg [15:0] RXCDR_LOCK_CFG4_REG = RXCDR_LOCK_CFG4;
reg [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE;
reg [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0;
reg [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1;
reg [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2;
reg [15:0] RXCKCAL1_IQ_LOOP_RST_CFG_REG = RXCKCAL1_IQ_LOOP_RST_CFG;
reg [15:0] RXCKCAL1_I_LOOP_RST_CFG_REG = RXCKCAL1_I_LOOP_RST_CFG;
reg [15:0] RXCKCAL1_Q_LOOP_RST_CFG_REG = RXCKCAL1_Q_LOOP_RST_CFG;
reg [15:0] RXCKCAL2_DX_LOOP_RST_CFG_REG = RXCKCAL2_DX_LOOP_RST_CFG;
reg [15:0] RXCKCAL2_D_LOOP_RST_CFG_REG = RXCKCAL2_D_LOOP_RST_CFG;
reg [15:0] RXCKCAL2_S_LOOP_RST_CFG_REG = RXCKCAL2_S_LOOP_RST_CFG;
reg [15:0] RXCKCAL2_X_LOOP_RST_CFG_REG = RXCKCAL2_X_LOOP_RST_CFG;
reg [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME;
reg [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0;
reg [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1;
reg [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2;
reg [15:0] RXDFE_CFG0_REG = RXDFE_CFG0;
reg [15:0] RXDFE_CFG1_REG = RXDFE_CFG1;
reg [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0;
reg [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1;
reg [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2;
reg [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0;
reg [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1;
reg [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0;
reg [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1;
reg [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0;
reg [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1;
reg [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0;
reg [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1;
reg [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0;
reg [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1;
reg [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0;
reg [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1;
reg [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0;
reg [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1;
reg [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0;
reg [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1;
reg [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0;
reg [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1;
reg [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0;
reg [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1;
reg [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0;
reg [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1;
reg [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0;
reg [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1;
reg [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0;
reg [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1;
reg [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0;
reg [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1;
reg [15:0] RXDFE_KH_CFG0_REG = RXDFE_KH_CFG0;
reg [15:0] RXDFE_KH_CFG1_REG = RXDFE_KH_CFG1;
reg [15:0] RXDFE_KH_CFG2_REG = RXDFE_KH_CFG2;
reg [15:0] RXDFE_KH_CFG3_REG = RXDFE_KH_CFG3;
reg [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0;
reg [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1;
reg [0:0] RXDFE_PWR_SAVING_REG = RXDFE_PWR_SAVING;
reg [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0;
reg [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1;
reg [15:0] RXDFE_UT_CFG2_REG = RXDFE_UT_CFG2;
reg [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0;
reg [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1;
reg [15:0] RXDLY_CFG_REG = RXDLY_CFG;
reg [15:0] RXDLY_LCFG_REG = RXDLY_LCFG;
reg [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG;
reg [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR;
reg [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN;
reg [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME;
reg [15:0] RXLPM_CFG_REG = RXLPM_CFG;
reg [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG;
reg [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0;
reg [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1;
reg [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0;
reg [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1;
reg [8:0] RXOOB_CFG_REG = RXOOB_CFG;
reg [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG;
reg [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME;
reg [4:0] RXOUT_DIV_REG = RXOUT_DIV;
reg [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME;
reg [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG;
reg [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG;
reg [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG;
reg [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG;
reg [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL;
reg [0:0] RXPI_AUTO_BW_SEL_BYPASS_REG = RXPI_AUTO_BW_SEL_BYPASS;
reg [15:0] RXPI_CFG0_REG = RXPI_CFG0;
reg [15:0] RXPI_CFG1_REG = RXPI_CFG1;
reg [0:0] RXPI_LPM_REG = RXPI_LPM;
reg [1:0] RXPI_SEL_LC_REG = RXPI_SEL_LC;
reg [1:0] RXPI_STARTCODE_REG = RXPI_STARTCODE;
reg [0:0] RXPI_VREFSEL_REG = RXPI_VREFSEL;
reg [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL;
reg [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME;
reg [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK;
reg [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT;
reg [0:0] RXREFCLKDIV2_SEL_REG = RXREFCLKDIV2_SEL;
reg [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT;
reg [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE;
reg [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE;
reg [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD;
reg [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA;
reg [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN;
reg [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0;
reg [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG;
reg [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB;
reg [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV;
reg [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN;
reg [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD;
reg [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG;
reg [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD;
reg [1:0] RX_CM_SEL_REG = RX_CM_SEL;
reg [3:0] RX_CM_TRIM_REG = RX_CM_TRIM;
reg [7:0] RX_CTLE3_LPF_REG = RX_CTLE3_LPF;
reg [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
reg [5:0] RX_DDI_SEL_REG = RX_DDI_SEL;
reg [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN;
reg [2:0] RX_DEGEN_CTRL_REG = RX_DEGEN_CTRL;
reg [3:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0;
reg [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1;
reg [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN;
reg [1:0] RX_DFE_AGC_CFG0_REG = RX_DFE_AGC_CFG0;
reg [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1;
reg [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0;
reg [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1;
reg [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0;
reg [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1;
reg [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE;
reg [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH;
reg [0:0] RX_DIV2_MODE_B_REG = RX_DIV2_MODE_B;
reg [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME;
reg [0:0] RX_EN_CTLE_RCAL_B_REG = RX_EN_CTLE_RCAL_B;
reg [0:0] RX_EN_HI_LR_REG = RX_EN_HI_LR;
reg [8:0] RX_EXT_RL_CTRL_REG = RX_EXT_RL_CTRL;
reg [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE;
reg [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR;
reg [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE;
reg [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN;
reg [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP;
reg [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH;
reg [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE;
reg [15:0] RX_PMA_RSV0_REG = RX_PMA_RSV0;
real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG;
reg [15:0] RX_PROGDIV_RATE_REG = RX_PROGDIV_RATE;
reg [3:0] RX_RESLOAD_CTRL_REG = RX_RESLOAD_CTRL;
reg [0:0] RX_RESLOAD_OVRD_REG = RX_RESLOAD_OVRD;
reg [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD;
reg [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY;
reg [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN;
reg [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE;
reg [3:0] RX_SUM_RESLOAD_CTRL_REG = RX_SUM_RESLOAD_CTRL;
reg [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE;
reg [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR;
reg [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE;
reg [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS;
reg [2:0] RX_VREG_CTRL_REG = RX_VREG_CTRL;
reg [0:0] RX_VREG_PDB_REG = RX_VREG_PDB;
reg [1:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR;
reg [1:0] RX_WIDEMODE_CDR_GEN3_REG = RX_WIDEMODE_CDR_GEN3;
reg [1:0] RX_WIDEMODE_CDR_GEN4_REG = RX_WIDEMODE_CDR_GEN4;
reg [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL;
reg [0:0] RX_XMODE_SEL_REG = RX_XMODE_SEL;
reg [0:0] SAMPLE_CLK_PHASE_REG = SAMPLE_CLK_PHASE;
reg [0:0] SAS_12G_MODE_REG = SAS_12G_MODE;
reg [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN;
reg [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL;
reg [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG;
reg [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL;
reg [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA;
reg [160:1] SIM_DEVICE_REG = SIM_DEVICE;
reg [48:1] SIM_MODE_REG = SIM_MODE;
reg [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS;
reg [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
reg [32:1] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL;
reg [0:0] SRSTMODE_REG = SRSTMODE;
reg [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX;
reg [3:0] TEMPERATURE_PAR_REG = TEMPERATURE_PAR;
reg [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG;
reg [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD;
reg [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE;
reg [7:0] TST_RSV0_REG = TST_RSV0;
reg [7:0] TST_RSV1_REG = TST_RSV1;
reg [40:1] TXBUF_EN_REG = TXBUF_EN;
reg [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE;
reg [15:0] TXDLY_CFG_REG = TXDLY_CFG;
reg [15:0] TXDLY_LCFG_REG = TXDLY_LCFG;
reg [3:0] TXDRVBIAS_N_REG = TXDRVBIAS_N;
reg [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG;
reg [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR;
reg [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN;
reg [4:0] TXOUT_DIV_REG = TXOUT_DIV;
reg [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME;
reg [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0;
reg [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1;
reg [15:0] TXPH_CFG_REG = TXPH_CFG;
reg [15:0] TXPH_CFG2_REG = TXPH_CFG2;
reg [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL;
reg [15:0] TXPI_CFG_REG = TXPI_CFG;
reg [1:0] TXPI_CFG0_REG = TXPI_CFG0;
reg [1:0] TXPI_CFG1_REG = TXPI_CFG1;
reg [1:0] TXPI_CFG2_REG = TXPI_CFG2;
reg [0:0] TXPI_CFG3_REG = TXPI_CFG3;
reg [0:0] TXPI_CFG4_REG = TXPI_CFG4;
reg [2:0] TXPI_CFG5_REG = TXPI_CFG5;
reg [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL;
reg [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL;
reg [0:0] TXPI_LPM_REG = TXPI_LPM;
reg [0:0] TXPI_PPM_REG = TXPI_PPM;
reg [72:1] TXPI_PPMCLK_SEL_REG = TXPI_PPMCLK_SEL;
reg [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG;
reg [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM;
reg [0:0] TXPI_VREFSEL_REG = TXPI_VREFSEL;
reg [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME;
reg [0:0] TXREFCLKDIV2_SEL_REG = TXREFCLKDIV2_SEL;
reg [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE;
reg [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD;
reg [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA;
reg [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV;
reg [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN;
reg [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
reg [15:0] TX_DCC_LOOP_RST_CFG_REG = TX_DCC_LOOP_RST_CFG;
reg [5:0] TX_DEEMPH0_REG = TX_DEEMPH0;
reg [5:0] TX_DEEMPH1_REG = TX_DEEMPH1;
reg [5:0] TX_DEEMPH2_REG = TX_DEEMPH2;
reg [5:0] TX_DEEMPH3_REG = TX_DEEMPH3;
reg [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME;
reg [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE;
reg [1:0] TX_DRVMUX_CTRL_REG = TX_DRVMUX_CTRL;
reg [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY;
reg [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY;
reg [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP;
reg [0:0] TX_FIFO_BYP_EN_REG = TX_FIFO_BYP_EN;
reg [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO;
reg [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH;
reg [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ;
reg [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL;
reg [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0;
reg [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1;
reg [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2;
reg [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3;
reg [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4;
reg [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0;
reg [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1;
reg [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2;
reg [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3;
reg [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4;
reg [15:0] TX_PHICAL_CFG0_REG = TX_PHICAL_CFG0;
reg [15:0] TX_PHICAL_CFG1_REG = TX_PHICAL_CFG1;
reg [15:0] TX_PHICAL_CFG2_REG = TX_PHICAL_CFG2;
reg [1:0] TX_PI_BIASSET_REG = TX_PI_BIASSET;
reg [1:0] TX_PI_IBIAS_MID_REG = TX_PI_IBIAS_MID;
reg [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT;
reg [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE;
reg [15:0] TX_PMA_RSV0_REG = TX_PMA_RSV0;
reg [1:0] TX_PREDRV_CTRL_REG = TX_PREDRV_CTRL;
reg [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL;
real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG;
reg [15:0] TX_PROGDIV_RATE_REG = TX_PROGDIV_RATE;
reg [0:0] TX_QPI_STATUS_EN_REG = TX_QPI_STATUS_EN;
reg [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG;
reg [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF;
reg [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD;
reg [0:0] TX_SARC_LPBK_ENB_REG = TX_SARC_LPBK_ENB;
reg [1:0] TX_SW_MEAS_REG = TX_SW_MEAS;
reg [2:0] TX_VREG_CTRL_REG = TX_VREG_CTRL;
reg [0:0] TX_VREG_PDB_REG = TX_VREG_PDB;
reg [1:0] TX_VREG_VREFSEL_REG = TX_VREG_VREFSEL;
reg [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL;
reg [0:0] USB_BOTH_BURST_IDLE_REG = USB_BOTH_BURST_IDLE;
reg [6:0] USB_BURSTMAX_U3WAKE_REG = USB_BURSTMAX_U3WAKE;
reg [6:0] USB_BURSTMIN_U3WAKE_REG = USB_BURSTMIN_U3WAKE;
reg [0:0] USB_CLK_COR_EQ_EN_REG = USB_CLK_COR_EQ_EN;
reg [0:0] USB_EXT_CNTL_REG = USB_EXT_CNTL;
reg [9:0] USB_IDLEMAX_POLLING_REG = USB_IDLEMAX_POLLING;
reg [9:0] USB_IDLEMIN_POLLING_REG = USB_IDLEMIN_POLLING;
reg [8:0] USB_LFPSPING_BURST_REG = USB_LFPSPING_BURST;
reg [8:0] USB_LFPSPOLLING_BURST_REG = USB_LFPSPOLLING_BURST;
reg [8:0] USB_LFPSPOLLING_IDLE_MS_REG = USB_LFPSPOLLING_IDLE_MS;
reg [8:0] USB_LFPSU1EXIT_BURST_REG = USB_LFPSU1EXIT_BURST;
reg [8:0] USB_LFPSU2LPEXIT_BURST_MS_REG = USB_LFPSU2LPEXIT_BURST_MS;
reg [8:0] USB_LFPSU3WAKE_BURST_MS_REG = USB_LFPSU3WAKE_BURST_MS;
reg [3:0] USB_LFPS_TPERIOD_REG = USB_LFPS_TPERIOD;
reg [0:0] USB_LFPS_TPERIOD_ACCURATE_REG = USB_LFPS_TPERIOD_ACCURATE;
reg [0:0] USB_MODE_REG = USB_MODE;
reg [0:0] USB_PCIE_ERR_REP_DIS_REG = USB_PCIE_ERR_REP_DIS;
reg [5:0] USB_PING_SATA_MAX_INIT_REG = USB_PING_SATA_MAX_INIT;
reg [5:0] USB_PING_SATA_MIN_INIT_REG = USB_PING_SATA_MIN_INIT;
reg [5:0] USB_POLL_SATA_MAX_BURST_REG = USB_POLL_SATA_MAX_BURST;
reg [5:0] USB_POLL_SATA_MIN_BURST_REG = USB_POLL_SATA_MIN_BURST;
reg [0:0] USB_RAW_ELEC_REG = USB_RAW_ELEC;
reg [0:0] USB_RXIDLE_P0_CTRL_REG = USB_RXIDLE_P0_CTRL;
reg [0:0] USB_TXIDLE_TUNE_ENABLE_REG = USB_TXIDLE_TUNE_ENABLE;
reg [5:0] USB_U1_SATA_MAX_WAKE_REG = USB_U1_SATA_MAX_WAKE;
reg [5:0] USB_U1_SATA_MIN_WAKE_REG = USB_U1_SATA_MIN_WAKE;
reg [6:0] USB_U2_SAS_MAX_COM_REG = USB_U2_SAS_MAX_COM;
reg [5:0] USB_U2_SAS_MIN_COM_REG = USB_U2_SAS_MIN_COM;
reg [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL;
reg [0:0] Y_ALL_MODE_REG = Y_ALL_MODE;
`endif
reg [0:0] AEN_CDRSTEPSEL_REG = 1'b0;
reg [0:0] AEN_CPLL_REG = 1'b0;
reg [0:0] AEN_LOOPBACK_REG = 1'b0;
reg [0:0] AEN_MASTER_REG = 1'b0;
reg [0:0] AEN_PD_AND_EIDLE_REG = 1'b0;
reg [0:0] AEN_POLARITY_REG = 1'b0;
reg [0:0] AEN_PRBS_REG = 1'b0;
reg [0:0] AEN_QPI_REG = 1'b0;
reg [0:0] AEN_RESET_REG = 1'b0;
reg [0:0] AEN_RXCDR_REG = 1'b0;
reg [0:0] AEN_RXDFE_REG = 1'b0;
reg [0:0] AEN_RXDFELPM_REG = 1'b0;
reg [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0;
reg [0:0] AEN_RXPHDLY_REG = 1'b0;
reg [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0;
reg [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0;
reg [0:0] AEN_TXMUXDCD_REG = 1'b0;
reg [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0;
reg [0:0] AEN_TXPHDLY_REG = 1'b0;
reg [0:0] AEN_TXPI_PPM_REG = 1'b0;
reg [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0;
reg [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0;
reg [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0;
reg [15:0] AMONITOR_CFG_REG = 16'h0000;
reg [0:0] A_CPLLLOCKEN_REG = 1'b0;
reg [0:0] A_CPLLPD_REG = 1'b0;
reg [0:0] A_CPLLRESET_REG = 1'b0;
reg [0:0] A_EYESCANRESET_REG = 1'b0;
reg [0:0] A_GTRESETSEL_REG = 1'b0;
reg [0:0] A_GTRXRESET_REG = 1'b0;
reg [0:0] A_GTTXRESET_REG = 1'b0;
reg [80:1] A_LOOPBACK_REG = "NOLOOPBACK";
reg [0:0] A_RXAFECFOKEN_REG = 1'b1;
reg [0:0] A_RXBUFRESET_REG = 1'b0;
reg [0:0] A_RXCDRFREQRESET_REG = 1'b0;
reg [0:0] A_RXCDRHOLD_REG = 1'b0;
reg [0:0] A_RXCDROVRDEN_REG = 1'b0;
reg [0:0] A_RXCDRRESET_REG = 1'b0;
reg [0:0] A_RXCKCALRESET_REG = 1'b0;
reg [1:0] A_RXDFEAGCCTRL_REG = 2'b01;
reg [0:0] A_RXDFEAGCHOLD_REG = 1'b0;
reg [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0;
reg [3:0] A_RXDFECFOKFCNUM_REG = 4'b0000;
reg [0:0] A_RXDFECFOKFEN_REG = 1'b0;
reg [0:0] A_RXDFECFOKFPULSE_REG = 1'b0;
reg [0:0] A_RXDFECFOKHOLD_REG = 1'b0;
reg [0:0] A_RXDFECFOKOVREN_REG = 1'b0;
reg [0:0] A_RXDFEKHHOLD_REG = 0;
reg [0:0] A_RXDFEKHOVRDEN_REG = 1'b0;
reg [0:0] A_RXDFELFHOLD_REG = 1'b0;
reg [0:0] A_RXDFELFOVRDEN_REG = 1'b0;
reg [0:0] A_RXDFELPMRESET_REG = 1'b0;
reg [0:0] A_RXDFETAP10HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP11HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP12HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP12OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP13HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP13OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP14HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP14OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP15HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP15OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP2HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP3HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP4HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP5HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP6HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP7HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP8HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP9HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFEUTHOLD_REG = 1'b0;
reg [0:0] A_RXDFEUTOVRDEN_REG = 1'b0;
reg [0:0] A_RXDFEVPHOLD_REG = 1'b0;
reg [0:0] A_RXDFEVPOVRDEN_REG = 1'b0;
reg [0:0] A_RXDFEXYDEN_REG = 1'b0;
reg [0:0] A_RXDLYBYPASS_REG = 1'b0;
reg [0:0] A_RXDLYEN_REG = 1'b0;
reg [0:0] A_RXDLYOVRDEN_REG = 1'b0;
reg [0:0] A_RXDLYSRESET_REG = 1'b0;
reg [0:0] A_RXLPMEN_REG = 1'b0;
reg [0:0] A_RXLPMGCHOLD_REG = 1'b0;
reg [0:0] A_RXLPMGCOVRDEN_REG = 1'b0;
reg [0:0] A_RXLPMHFHOLD_REG = 1'b0;
reg [0:0] A_RXLPMHFOVRDEN_REG = 1'b0;
reg [0:0] A_RXLPMLFHOLD_REG = 1'b0;
reg [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0;
reg [0:0] A_RXLPMOSHOLD_REG = 1'b0;
reg [0:0] A_RXLPMOSOVRDEN_REG = 1'b0;
reg [1:0] A_RXMONITORSEL_REG = 2'b00;
reg [0:0] A_RXOOBRESET_REG = 1'b0;
reg [0:0] A_RXOSHOLD_REG = 1'b0;
reg [0:0] A_RXOSOVRDEN_REG = 1'b0;
reg [128:1] A_RXOUTCLKSEL_REG = "DISABLED";
reg [0:0] A_RXPCSRESET_REG = 1'b0;
reg [24:1] A_RXPD_REG = "P0";
reg [0:0] A_RXPHALIGN_REG = 1'b0;
reg [0:0] A_RXPHALIGNEN_REG = 1'b0;
reg [0:0] A_RXPHDLYPD_REG = 1'b0;
reg [0:0] A_RXPHDLYRESET_REG = 1'b0;
reg [0:0] A_RXPHOVRDEN_REG = 1'b0;
reg [64:1] A_RXPLLCLKSEL_REG = "QPLLCLK1";
reg [0:0] A_RXPMARESET_REG = 1'b0;
reg [0:0] A_RXPOLARITY_REG = 1'b0;
reg [0:0] A_RXPRBSCNTRESET_REG = 1'b0;
reg [48:1] A_RXPRBSSEL_REG = "PRBS7";
reg [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK";
reg [2:0] A_TXBUFDIFFCTRL_REG = 3'b100;
reg [0:0] A_TXDCCRESET_REG = 1'b0;
reg [1:0] A_TXDEEMPH_REG = 2'b00;
reg [0:0] A_TXDLYBYPASS_REG = 1'b0;
reg [0:0] A_TXDLYEN_REG = 1'b0;
reg [0:0] A_TXDLYOVRDEN_REG = 1'b0;
reg [0:0] A_TXDLYSRESET_REG = 1'b0;
reg [0:0] A_TXELECIDLE_REG = 1'b0;
reg [0:0] A_TXINHIBIT_REG = 1'b0;
reg [6:0] A_TXMAINCURSOR_REG = 7'b0000000;
reg [2:0] A_TXMARGIN_REG = 3'b000;
reg [0:0] A_TXMUXDCDEXHOLD_REG = 1'b0;
reg [0:0] A_TXMUXDCDORWREN_REG = 1'b0;
reg [128:1] A_TXOUTCLKSEL_REG = "DISABLED";
reg [0:0] A_TXPCSRESET_REG = 1'b0;
reg [24:1] A_TXPD_REG = "P0";
reg [0:0] A_TXPHALIGN_REG = 1'b0;
reg [0:0] A_TXPHALIGNEN_REG = 1'b0;
reg [0:0] A_TXPHDLYPD_REG = 1'b0;
reg [0:0] A_TXPHDLYRESET_REG = 1'b0;
reg [0:0] A_TXPHINIT_REG = 1'b0;
reg [0:0] A_TXPHOVRDEN_REG = 1'b0;
reg [0:0] A_TXPIPPMOVRDEN_REG = 1'b0;
reg [0:0] A_TXPIPPMPD_REG = 1'b0;
reg [0:0] A_TXPIPPMSEL_REG = 1'b0;
reg [64:1] A_TXPLLCLKSEL_REG = "QPLLCLK1";
reg [0:0] A_TXPMARESET_REG = 1'b0;
reg [0:0] A_TXPOLARITY_REG = 1'b0;
reg [4:0] A_TXPOSTCURSOR_REG = 5'b00000;
reg [0:0] A_TXPRBSFORCEERR_REG = 1'b0;
reg [96:1] A_TXPRBSSEL_REG = "PRBS7";
reg [4:0] A_TXPRECURSOR_REG = 5'b00000;
reg [0:0] A_TXQPIBIASEN_REG = 1'b0;
reg [0:0] A_TXRESETSEL_REG = 1'b0;
reg [0:0] A_TXSWING_REG = 1'b0;
reg [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK";
reg [1:0] BSR_ENABLE_REG = 2'b00;
reg [0:0] COEREG_CLKCTRL_REG = 1'b0;
reg [15:0] CSSD_CLK_MASK0_REG = 16'b0000000000000000;
reg [15:0] CSSD_CLK_MASK1_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG0_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG1_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG10_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG2_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG3_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG4_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG5_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG6_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG7_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG8_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG9_REG = 16'b0000000000000000;
reg [40:1] GEN_RXUSRCLK_REG = "TRUE";
reg [40:1] GEN_TXUSRCLK_REG = "TRUE";
reg [0:0] GT_INSTANTIATED_REG = 1'b1;
reg [15:0] INT_MASK_CFG0_REG = 16'b0000000000000000;
reg [15:0] INT_MASK_CFG1_REG = 16'b0000000000000000;
reg [5:0] RX_DFECFOKFCDAC_REG = 6'b000000;
reg [0:0] TXOUTCLKPCS_SEL_REG = 1'b0;
reg [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100;
reg [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101;
reg [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011;
reg [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010;
reg [9:0] TX_USERPATTERN_DATA4_REG = 10'b0101111100;
reg [9:0] TX_USERPATTERN_DATA5_REG = 10'b0101010101;
reg [9:0] TX_USERPATTERN_DATA6_REG = 10'b1010000011;
reg [9:0] TX_USERPATTERN_DATA7_REG = 10'b1010101010;
`ifdef XIL_XECLIB
wire [63:0] RX_PROGDIV_CFG_BIN;
wire [63:0] TX_PROGDIV_CFG_BIN;
`else
reg [63:0] RX_PROGDIV_CFG_BIN;
reg [63:0] TX_PROGDIV_CFG_BIN;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire BUFGTCE_out;
wire BUFGTRESET_out;
wire CPLLFBCLKLOST_out;
wire CPLLLOCK_out;
wire CPLLREFCLKLOST_out;
wire CSSDSTOPCLKDONE_out;
wire DMONITOROUTCLK_out;
wire DRPRDY_out;
wire EYESCANDATAERROR_out;
wire GTHTXN_out;
wire GTHTXP_out;
wire GTPOWERGOOD_out;
wire GTREFCLKMONITOR_out;
wire PCIERATEGEN3_out;
wire PCIERATEIDLE_out;
wire PCIESYNCTXSYNCDONE_out;
wire PCIEUSERGEN3RDY_out;
wire PCIEUSERPHYSTATUSRST_out;
wire PCIEUSERRATESTART_out;
wire PHYSTATUS_out;
wire POWERPRESENT_out;
wire RESETEXCEPTION_out;
wire RXBYTEISALIGNED_out;
wire RXBYTEREALIGN_out;
wire RXCDRLOCK_out;
wire RXCDRPHDONE_out;
wire RXCHANBONDSEQ_out;
wire RXCHANISALIGNED_out;
wire RXCHANREALIGN_out;
wire RXCKCALDONE_out;
wire RXCOMINITDET_out;
wire RXCOMMADET_out;
wire RXCOMSASDET_out;
wire RXCOMWAKEDET_out;
wire RXDLYSRESETDONE_out;
wire RXELECIDLE_out;
wire RXLFPSTRESETDET_out;
wire RXLFPSU2LPEXITDET_out;
wire RXLFPSU3WAKEDET_out;
wire RXOSINTDONE_out;
wire RXOSINTSTARTED_out;
wire RXOSINTSTROBEDONE_out;
wire RXOSINTSTROBESTARTED_out;
wire RXOUTCLKFABRIC_out;
wire RXOUTCLKPCS_out;
wire RXOUTCLK_out;
wire RXPHALIGNDONE_out;
wire RXPHALIGNERR_out;
wire RXPMARESETDONE_out;
wire RXPRBSERR_out;
wire RXPRBSLOCKED_out;
wire RXPRGDIVRESETDONE_out;
wire RXQPISENN_out;
wire RXQPISENP_out;
wire RXRATEDONE_out;
wire RXRECCLKOUT_out;
wire RXRESETDONE_out;
wire RXSLIDERDY_out;
wire RXSLIPDONE_out;
wire RXSLIPOUTCLKRDY_out;
wire RXSLIPPMARDY_out;
wire RXSYNCDONE_out;
wire RXSYNCOUT_out;
wire RXVALID_out;
wire TXCOMFINISH_out;
wire TXDCCDONE_out;
wire TXDLYSRESETDONE_out;
wire TXOUTCLKFABRIC_out;
wire TXOUTCLKPCS_out;
wire TXOUTCLK_out;
wire TXPHALIGNDONE_out;
wire TXPHINITDONE_out;
wire TXPMARESETDONE_out;
wire TXPRGDIVRESETDONE_out;
wire TXQPISENN_out;
wire TXQPISENP_out;
wire TXRATEDONE_out;
wire TXRESETDONE_out;
wire TXSYNCDONE_out;
wire TXSYNCOUT_out;
wire [127:0] RXDATA_out;
wire [15:0] DMONITOROUT_out;
wire [15:0] DRPDO_out;
wire [15:0] PCSRSVDOUT_out;
wire [15:0] PINRSRVDAS_out;
wire [15:0] RXCTRL0_out;
wire [15:0] RXCTRL1_out;
wire [17:0] PMASCANOUT_out;
wire [18:0] SCANOUT_out;
wire [1:0] PCIERATEQPLLPD_out;
wire [1:0] PCIERATEQPLLRESET_out;
wire [1:0] RXCLKCORCNT_out;
wire [1:0] RXDATAVALID_out;
wire [1:0] RXHEADERVALID_out;
wire [1:0] RXSTARTOFSEQ_out;
wire [1:0] TXBUFSTATUS_out;
wire [2:0] BUFGTCEMASK_out;
wire [2:0] BUFGTRSTMASK_out;
wire [2:0] RXBUFSTATUS_out;
wire [2:0] RXSTATUS_out;
wire [4:0] RXCHBONDO_out;
wire [5:0] RXHEADER_out;
wire [7:0] RXCTRL2_out;
wire [7:0] RXCTRL3_out;
wire [7:0] RXDATAEXTENDRSVD_out;
wire [7:0] RXMONITOROUT_out;
wire [8:0] BUFGTDIV_out;
wire BSR_SERIAL_in;
wire CDRSTEPDIR_in;
wire CDRSTEPSQ_in;
wire CDRSTEPSX_in;
wire CFGRESET_in;
wire CLKRSVD0_in;
wire CLKRSVD1_in;
wire CPLLFREQLOCK_in;
wire CPLLLOCKDETCLK_in;
wire CPLLLOCKEN_in;
wire CPLLPD_in;
wire CPLLRESET_in;
wire CSSDRSTB_in;
wire CSSDSTOPCLK_in;
wire DMONFIFORESET_in;
wire DMONITORCLK_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPRST_in;
wire DRPWE_in;
wire EYESCANRESET_in;
wire EYESCANTRIGGER_in;
wire FREQOS_in;
wire GTGREFCLK_in;
wire GTHRXN_in;
wire GTHRXP_in;
wire GTNORTHREFCLK0_in;
wire GTNORTHREFCLK1_in;
wire GTREFCLK0_in;
wire GTREFCLK1_in;
wire GTRXRESETSEL_in;
wire GTRXRESET_in;
wire GTSOUTHREFCLK0_in;
wire GTSOUTHREFCLK1_in;
wire GTTXRESETSEL_in;
wire GTTXRESET_in;
wire INCPCTRL_in;
wire PCIEEQRXEQADAPTDONE_in;
wire PCIERSTIDLE_in;
wire PCIERSTTXSYNCSTART_in;
wire PCIEUSERRATEDONE_in;
wire PMASCANCLK0_in;
wire PMASCANCLK1_in;
wire PMASCANCLK2_in;
wire PMASCANCLK3_in;
wire PMASCANCLK4_in;
wire PMASCANCLK5_in;
wire PMASCANCLK6_in;
wire PMASCANCLK7_in;
wire PMASCANCLK8_in;
wire PMASCANENB_in;
wire PMASCANMODEB_in;
wire PMASCANRSTEN_in;
wire QPLL0CLK_in;
wire QPLL0FREQLOCK_in;
wire QPLL0REFCLK_in;
wire QPLL1CLK_in;
wire QPLL1FREQLOCK_in;
wire QPLL1REFCLK_in;
wire RESETOVRD_in;
wire RX8B10BEN_in;
wire RXAFECFOKEN_in;
wire RXBUFRESET_in;
wire RXCDRFREQRESET_in;
wire RXCDRHOLD_in;
wire RXCDROVRDEN_in;
wire RXCDRRESET_in;
wire RXCHBONDEN_in;
wire RXCHBONDMASTER_in;
wire RXCHBONDSLAVE_in;
wire RXCKCALRESET_in;
wire RXCOMMADETEN_in;
wire RXDFEAGCHOLD_in;
wire RXDFEAGCOVRDEN_in;
wire RXDFECFOKFEN_in;
wire RXDFECFOKFPULSE_in;
wire RXDFECFOKHOLD_in;
wire RXDFECFOKOVREN_in;
wire RXDFEKHHOLD_in;
wire RXDFEKHOVRDEN_in;
wire RXDFELFHOLD_in;
wire RXDFELFOVRDEN_in;
wire RXDFELPMRESET_in;
wire RXDFETAP10HOLD_in;
wire RXDFETAP10OVRDEN_in;
wire RXDFETAP11HOLD_in;
wire RXDFETAP11OVRDEN_in;
wire RXDFETAP12HOLD_in;
wire RXDFETAP12OVRDEN_in;
wire RXDFETAP13HOLD_in;
wire RXDFETAP13OVRDEN_in;
wire RXDFETAP14HOLD_in;
wire RXDFETAP14OVRDEN_in;
wire RXDFETAP15HOLD_in;
wire RXDFETAP15OVRDEN_in;
wire RXDFETAP2HOLD_in;
wire RXDFETAP2OVRDEN_in;
wire RXDFETAP3HOLD_in;
wire RXDFETAP3OVRDEN_in;
wire RXDFETAP4HOLD_in;
wire RXDFETAP4OVRDEN_in;
wire RXDFETAP5HOLD_in;
wire RXDFETAP5OVRDEN_in;
wire RXDFETAP6HOLD_in;
wire RXDFETAP6OVRDEN_in;
wire RXDFETAP7HOLD_in;
wire RXDFETAP7OVRDEN_in;
wire RXDFETAP8HOLD_in;
wire RXDFETAP8OVRDEN_in;
wire RXDFETAP9HOLD_in;
wire RXDFETAP9OVRDEN_in;
wire RXDFEUTHOLD_in;
wire RXDFEUTOVRDEN_in;
wire RXDFEVPHOLD_in;
wire RXDFEVPOVRDEN_in;
wire RXDFEXYDEN_in;
wire RXDLYBYPASS_in;
wire RXDLYEN_in;
wire RXDLYOVRDEN_in;
wire RXDLYSRESET_in;
wire RXEQTRAINING_in;
wire RXGEARBOXSLIP_in;
wire RXLATCLK_in;
wire RXLPMEN_in;
wire RXLPMGCHOLD_in;
wire RXLPMGCOVRDEN_in;
wire RXLPMHFHOLD_in;
wire RXLPMHFOVRDEN_in;
wire RXLPMLFHOLD_in;
wire RXLPMLFKLOVRDEN_in;
wire RXLPMOSHOLD_in;
wire RXLPMOSOVRDEN_in;
wire RXMCOMMAALIGNEN_in;
wire RXOOBRESET_in;
wire RXOSCALRESET_in;
wire RXOSHOLD_in;
wire RXOSOVRDEN_in;
wire RXPCOMMAALIGNEN_in;
wire RXPCSRESET_in;
wire RXPHALIGNEN_in;
wire RXPHALIGN_in;
wire RXPHDLYPD_in;
wire RXPHDLYRESET_in;
wire RXPHOVRDEN_in;
wire RXPMARESET_in;
wire RXPOLARITY_in;
wire RXPRBSCNTRESET_in;
wire RXPROGDIVRESET_in;
wire RXQPIEN_in;
wire RXRATEMODE_in;
wire RXSLIDE_in;
wire RXSLIPOUTCLK_in;
wire RXSLIPPMA_in;
wire RXSYNCALLIN_in;
wire RXSYNCIN_in;
wire RXSYNCMODE_in;
wire RXTERMINATION_in;
wire RXUSERRDY_in;
wire RXUSRCLK2_in;
wire RXUSRCLK_in;
wire SARCCLK_in;
wire SCANCLK_in;
wire SCANENB_in;
wire SCANMODEB_in;
wire SCANRSTB_in;
wire SCANRSTEN_in;
wire SIGVALIDCLK_in;
wire TSTCLK0_in;
wire TSTCLK1_in;
wire TSTPDOVRDB_in;
wire TX8B10BEN_in;
wire TXCOMINIT_in;
wire TXCOMSAS_in;
wire TXCOMWAKE_in;
wire TXDCCFORCESTART_in;
wire TXDCCRESET_in;
wire TXDETECTRX_in;
wire TXDLYBYPASS_in;
wire TXDLYEN_in;
wire TXDLYHOLD_in;
wire TXDLYOVRDEN_in;
wire TXDLYSRESET_in;
wire TXDLYUPDOWN_in;
wire TXELECIDLE_in;
wire TXINHIBIT_in;
wire TXLATCLK_in;
wire TXLFPSTRESET_in;
wire TXLFPSU2LPEXIT_in;
wire TXLFPSU3WAKE_in;
wire TXMUXDCDEXHOLD_in;
wire TXMUXDCDORWREN_in;
wire TXONESZEROS_in;
wire TXPCSRESET_in;
wire TXPDELECIDLEMODE_in;
wire TXPHALIGNEN_in;
wire TXPHALIGN_in;
wire TXPHDLYPD_in;
wire TXPHDLYRESET_in;
wire TXPHDLYTSTCLK_in;
wire TXPHINIT_in;
wire TXPHOVRDEN_in;
wire TXPIPPMEN_in;
wire TXPIPPMOVRDEN_in;
wire TXPIPPMPD_in;
wire TXPIPPMSEL_in;
wire TXPISOPD_in;
wire TXPMARESET_in;
wire TXPOLARITY_in;
wire TXPRBSFORCEERR_in;
wire TXPROGDIVRESET_in;
wire TXQPIBIASEN_in;
wire TXQPIWEAKPUP_in;
wire TXRATEMODE_in;
wire TXSWING_in;
wire TXSYNCALLIN_in;
wire TXSYNCIN_in;
wire TXSYNCMODE_in;
wire TXUSERRDY_in;
wire TXUSRCLK2_in;
wire TXUSRCLK_in;
wire [127:0] TXDATA_in;
wire [15:0] DRPDI_in;
wire [15:0] GTRSVD_in;
wire [15:0] PCSRSVDIN_in;
wire [15:0] TXCTRL0_in;
wire [15:0] TXCTRL1_in;
wire [17:0] PMASCANIN_in;
wire [18:0] SCANIN_in;
wire [19:0] TSTIN_in;
wire [1:0] RXDFEAGCCTRL_in;
wire [1:0] RXELECIDLEMODE_in;
wire [1:0] RXMONITORSEL_in;
wire [1:0] RXPD_in;
wire [1:0] RXPLLCLKSEL_in;
wire [1:0] RXSYSCLKSEL_in;
wire [1:0] TXDEEMPH_in;
wire [1:0] TXPD_in;
wire [1:0] TXPLLCLKSEL_in;
wire [1:0] TXSYSCLKSEL_in;
wire [2:0] CPLLREFCLKSEL_in;
wire [2:0] LOOPBACK_in;
wire [2:0] RXCHBONDLEVEL_in;
wire [2:0] RXOUTCLKSEL_in;
wire [2:0] RXRATE_in;
wire [2:0] TXMARGIN_in;
wire [2:0] TXOUTCLKSEL_in;
wire [2:0] TXRATE_in;
wire [3:0] RXDFECFOKFCNUM_in;
wire [3:0] RXPRBSSEL_in;
wire [3:0] TXPRBSSEL_in;
wire [4:0] RXCHBONDI_in;
wire [4:0] TSTPD_in;
wire [4:0] TXDIFFCTRL_in;
wire [4:0] TXPIPPMSTEPSIZE_in;
wire [4:0] TXPOSTCURSOR_in;
wire [4:0] TXPRECURSOR_in;
wire [5:0] TXHEADER_in;
wire [6:0] RXCKCALSTART_in;
wire [6:0] TXMAINCURSOR_in;
wire [6:0] TXSEQUENCE_in;
wire [7:0] TX8B10BBYPASS_in;
wire [7:0] TXCTRL2_in;
wire [7:0] TXDATAEXTENDRSVD_in;
wire [9:0] DRPADDR_in;
wire gt_intclk;
reg gt_clk_int;
`ifdef XIL_TIMING
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire RX8B10BEN_delay;
wire RXCHBONDEN_delay;
wire RXCHBONDMASTER_delay;
wire RXCHBONDSLAVE_delay;
wire RXCOMMADETEN_delay;
wire RXGEARBOXSLIP_delay;
wire RXMCOMMAALIGNEN_delay;
wire RXPCOMMAALIGNEN_delay;
wire RXPOLARITY_delay;
wire RXPRBSCNTRESET_delay;
wire RXSLIDE_delay;
wire RXSLIPOUTCLK_delay;
wire RXUSRCLK2_delay;
wire RXUSRCLK_delay;
wire TX8B10BEN_delay;
wire TXCOMINIT_delay;
wire TXCOMSAS_delay;
wire TXCOMWAKE_delay;
wire TXDETECTRX_delay;
wire TXELECIDLE_delay;
wire TXINHIBIT_delay;
wire TXPOLARITY_delay;
wire TXPRBSFORCEERR_delay;
wire TXUSRCLK2_delay;
wire [127:0] TXDATA_delay;
wire [15:0] DRPDI_delay;
wire [15:0] TXCTRL0_delay;
wire [15:0] TXCTRL1_delay;
wire [2:0] RXCHBONDLEVEL_delay;
wire [3:0] RXPRBSSEL_delay;
wire [3:0] TXPRBSSEL_delay;
wire [4:0] RXCHBONDI_delay;
wire [5:0] TXHEADER_delay;
wire [6:0] TXSEQUENCE_delay;
wire [7:0] TX8B10BBYPASS_delay;
wire [7:0] TXCTRL2_delay;
wire [9:0] DRPADDR_delay;
`endif
assign BUFGTCE = BUFGTCE_out;
assign BUFGTCEMASK = BUFGTCEMASK_out;
assign BUFGTDIV = BUFGTDIV_out;
assign BUFGTRESET = BUFGTRESET_out;
assign BUFGTRSTMASK = BUFGTRSTMASK_out;
assign CPLLFBCLKLOST = CPLLFBCLKLOST_out;
assign CPLLLOCK = CPLLLOCK_out;
assign CPLLREFCLKLOST = CPLLREFCLKLOST_out;
assign DMONITOROUT = DMONITOROUT_out;
assign DMONITOROUTCLK = DMONITOROUTCLK_out;
assign DRPDO = DRPDO_out;
assign DRPRDY = DRPRDY_out;
assign EYESCANDATAERROR = EYESCANDATAERROR_out;
assign GTHTXN = GTHTXN_out;
assign GTHTXP = GTHTXP_out;
assign GTPOWERGOOD = GTPOWERGOOD_out;
assign GTREFCLKMONITOR = GTREFCLKMONITOR_out;
assign PCIERATEGEN3 = PCIERATEGEN3_out;
assign PCIERATEIDLE = PCIERATEIDLE_out;
assign PCIERATEQPLLPD = PCIERATEQPLLPD_out;
assign PCIERATEQPLLRESET = PCIERATEQPLLRESET_out;
assign PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_out;
assign PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_out;
assign PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_out;
assign PCIEUSERRATESTART = PCIEUSERRATESTART_out;
assign PCSRSVDOUT = PCSRSVDOUT_out;
assign PHYSTATUS = PHYSTATUS_out;
assign PINRSRVDAS = PINRSRVDAS_out;
assign POWERPRESENT = POWERPRESENT_out;
assign RESETEXCEPTION = RESETEXCEPTION_out;
assign RXBUFSTATUS = RXBUFSTATUS_out;
assign RXBYTEISALIGNED = RXBYTEISALIGNED_out;
assign RXBYTEREALIGN = RXBYTEREALIGN_out;
assign RXCDRLOCK = RXCDRLOCK_out;
assign RXCDRPHDONE = RXCDRPHDONE_out;
assign RXCHANBONDSEQ = RXCHANBONDSEQ_out;
assign RXCHANISALIGNED = RXCHANISALIGNED_out;
assign RXCHANREALIGN = RXCHANREALIGN_out;
assign RXCHBONDO = RXCHBONDO_out;
assign RXCKCALDONE = RXCKCALDONE_out;
assign RXCLKCORCNT = RXCLKCORCNT_out;
assign RXCOMINITDET = RXCOMINITDET_out;
assign RXCOMMADET = RXCOMMADET_out;
assign RXCOMSASDET = RXCOMSASDET_out;
assign RXCOMWAKEDET = RXCOMWAKEDET_out;
assign RXCTRL0 = RXCTRL0_out;
assign RXCTRL1 = RXCTRL1_out;
assign RXCTRL2 = RXCTRL2_out;
assign RXCTRL3 = RXCTRL3_out;
assign RXDATA = RXDATA_out;
assign RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_out;
assign RXDATAVALID = RXDATAVALID_out;
assign RXDLYSRESETDONE = RXDLYSRESETDONE_out;
assign RXELECIDLE = RXELECIDLE_out;
assign RXHEADER = RXHEADER_out;
assign RXHEADERVALID = RXHEADERVALID_out;
assign RXLFPSTRESETDET = RXLFPSTRESETDET_out;
assign RXLFPSU2LPEXITDET = RXLFPSU2LPEXITDET_out;
assign RXLFPSU3WAKEDET = RXLFPSU3WAKEDET_out;
assign RXMONITOROUT = RXMONITOROUT_out;
assign RXOSINTDONE = RXOSINTDONE_out;
assign RXOSINTSTARTED = RXOSINTSTARTED_out;
assign RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_out;
assign RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_out;
assign RXOUTCLK = RXOUTCLK_out;
assign RXOUTCLKFABRIC = RXOUTCLKFABRIC_out;
//EL
//assign RXOUTCLKPCS = RXOUTCLKPCS_out;
assign RXOUTCLKPCS = (RXPD_in == 2'b11) ? gt_intclk : RXOUTCLKPCS_out;
assign RXPHALIGNDONE = RXPHALIGNDONE_out;
assign RXPHALIGNERR = RXPHALIGNERR_out;
assign RXPMARESETDONE = RXPMARESETDONE_out;
assign RXPRBSERR = RXPRBSERR_out;
assign RXPRBSLOCKED = RXPRBSLOCKED_out;
assign RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_out;
assign RXQPISENN = RXQPISENN_out;
assign RXQPISENP = RXQPISENP_out;
assign RXRATEDONE = RXRATEDONE_out;
assign RXRECCLKOUT = RXRECCLKOUT_out;
assign RXRESETDONE = RXRESETDONE_out;
assign RXSLIDERDY = RXSLIDERDY_out;
assign RXSLIPDONE = RXSLIPDONE_out;
assign RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_out;
assign RXSLIPPMARDY = RXSLIPPMARDY_out;
assign RXSTARTOFSEQ = RXSTARTOFSEQ_out;
assign RXSTATUS = RXSTATUS_out;
assign RXSYNCDONE = RXSYNCDONE_out;
assign RXSYNCOUT = RXSYNCOUT_out;
assign RXVALID = RXVALID_out;
assign TXBUFSTATUS = TXBUFSTATUS_out;
assign TXCOMFINISH = TXCOMFINISH_out;
assign TXDCCDONE = TXDCCDONE_out;
assign TXDLYSRESETDONE = TXDLYSRESETDONE_out;
//EL
//assign TXOUTCLK = TXOUTCLK_out;
assign TXOUTCLK = (TXPISOPD_in && TXOUTCLKSEL_in == 3'b101) ? gt_intclk : TXOUTCLK_out;
assign TXOUTCLKFABRIC = TXOUTCLKFABRIC_out;
//EL
// assign TXOUTCLKPCS = TXPISOPD_in ? gt_intclk : TXOUTCLKPCS_out;
assign TXOUTCLKPCS = TXOUTCLKPCS_out;
assign TXPHALIGNDONE = TXPHALIGNDONE_out;
assign TXPHINITDONE = TXPHINITDONE_out;
assign TXPMARESETDONE = TXPMARESETDONE_out;
assign TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_out;
assign TXQPISENN = TXQPISENN_out;
assign TXQPISENP = TXQPISENP_out;
assign TXRATEDONE = TXRATEDONE_out;
assign TXRESETDONE = TXRESETDONE_out;
assign TXSYNCDONE = TXSYNCDONE_out;
assign TXSYNCOUT = TXSYNCOUT_out;
`ifdef XIL_TIMING
assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0
assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0
assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0
assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0
assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0
assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0
assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0
assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0
assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0
assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0
assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0
assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0
assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0
assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0
assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0
assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0
assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0
assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0
assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0
assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0
assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0
assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0
assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0
assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0
assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0
assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0
assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0
assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0
assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0
assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN_delay; // rv 0
assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN_delay; // rv 0
assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI_delay[0]; // rv 0
assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI_delay[1]; // rv 0
assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI_delay[2]; // rv 0
assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI_delay[3]; // rv 0
assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI_delay[4]; // rv 0
assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL_delay[0]; // rv 0
assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL_delay[1]; // rv 0
assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL_delay[2]; // rv 0
assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER_delay; // rv 0
assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE_delay; // rv 0
assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN_delay; // rv 0
assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP_delay; // rv 0
assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN_delay; // rv 0
assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN_delay; // rv 0
assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY_delay; // rv 0
assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET_delay; // rv 0
assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL_delay[0]; // rv 0
assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL_delay[1]; // rv 0
assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL_delay[2]; // rv 0
assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL_delay[3]; // rv 0
assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE_delay; // rv 0
assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK_delay; // rv 0
assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2_delay; // rv 0
assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK_delay; // rv 0
assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS_delay[0]; // rv 0
assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS_delay[1]; // rv 0
assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS_delay[2]; // rv 0
assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS_delay[3]; // rv 0
assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS_delay[4]; // rv 0
assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS_delay[5]; // rv 0
assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS_delay[6]; // rv 0
assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS_delay[7]; // rv 0
assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN_delay; // rv 0
assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT_delay; // rv 0
assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS_delay; // rv 0
assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE_delay; // rv 0
assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0_delay[0]; // rv 0
assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0_delay[10]; // rv 0
assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0_delay[11]; // rv 0
assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0_delay[12]; // rv 0
assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0_delay[13]; // rv 0
assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0_delay[14]; // rv 0
assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0_delay[15]; // rv 0
assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0_delay[1]; // rv 0
assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0_delay[2]; // rv 0
assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0_delay[3]; // rv 0
assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0_delay[4]; // rv 0
assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0_delay[5]; // rv 0
assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0_delay[6]; // rv 0
assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0_delay[7]; // rv 0
assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0_delay[8]; // rv 0
assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0_delay[9]; // rv 0
assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1_delay[0]; // rv 0
assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1_delay[10]; // rv 0
assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1_delay[11]; // rv 0
assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1_delay[12]; // rv 0
assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1_delay[13]; // rv 0
assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1_delay[14]; // rv 0
assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1_delay[15]; // rv 0
assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1_delay[1]; // rv 0
assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1_delay[2]; // rv 0
assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1_delay[3]; // rv 0
assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1_delay[4]; // rv 0
assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1_delay[5]; // rv 0
assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1_delay[6]; // rv 0
assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1_delay[7]; // rv 0
assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1_delay[8]; // rv 0
assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1_delay[9]; // rv 0
assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2_delay[0]; // rv 0
assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2_delay[1]; // rv 0
assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2_delay[2]; // rv 0
assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2_delay[3]; // rv 0
assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2_delay[4]; // rv 0
assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2_delay[5]; // rv 0
assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2_delay[6]; // rv 0
assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2_delay[7]; // rv 0
assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA_delay[0]; // rv 0
assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA_delay[100]; // rv 0
assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA_delay[101]; // rv 0
assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA_delay[102]; // rv 0
assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA_delay[103]; // rv 0
assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA_delay[104]; // rv 0
assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA_delay[105]; // rv 0
assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA_delay[106]; // rv 0
assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA_delay[107]; // rv 0
assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA_delay[108]; // rv 0
assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA_delay[109]; // rv 0
assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA_delay[10]; // rv 0
assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA_delay[110]; // rv 0
assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA_delay[111]; // rv 0
assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA_delay[112]; // rv 0
assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA_delay[113]; // rv 0
assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA_delay[114]; // rv 0
assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA_delay[115]; // rv 0
assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA_delay[116]; // rv 0
assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA_delay[117]; // rv 0
assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA_delay[118]; // rv 0
assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA_delay[119]; // rv 0
assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA_delay[11]; // rv 0
assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA_delay[120]; // rv 0
assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA_delay[121]; // rv 0
assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA_delay[122]; // rv 0
assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA_delay[123]; // rv 0
assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA_delay[124]; // rv 0
assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA_delay[125]; // rv 0
assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA_delay[126]; // rv 0
assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA_delay[127]; // rv 0
assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA_delay[12]; // rv 0
assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA_delay[13]; // rv 0
assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA_delay[14]; // rv 0
assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA_delay[15]; // rv 0
assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA_delay[16]; // rv 0
assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA_delay[17]; // rv 0
assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA_delay[18]; // rv 0
assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA_delay[19]; // rv 0
assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA_delay[1]; // rv 0
assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA_delay[20]; // rv 0
assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA_delay[21]; // rv 0
assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA_delay[22]; // rv 0
assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA_delay[23]; // rv 0
assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA_delay[24]; // rv 0
assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA_delay[25]; // rv 0
assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA_delay[26]; // rv 0
assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA_delay[27]; // rv 0
assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA_delay[28]; // rv 0
assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA_delay[29]; // rv 0
assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA_delay[2]; // rv 0
assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA_delay[30]; // rv 0
assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA_delay[31]; // rv 0
assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA_delay[32]; // rv 0
assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA_delay[33]; // rv 0
assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA_delay[34]; // rv 0
assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA_delay[35]; // rv 0
assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA_delay[36]; // rv 0
assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA_delay[37]; // rv 0
assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA_delay[38]; // rv 0
assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA_delay[39]; // rv 0
assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA_delay[3]; // rv 0
assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA_delay[40]; // rv 0
assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA_delay[41]; // rv 0
assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA_delay[42]; // rv 0
assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA_delay[43]; // rv 0
assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA_delay[44]; // rv 0
assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA_delay[45]; // rv 0
assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA_delay[46]; // rv 0
assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA_delay[47]; // rv 0
assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA_delay[48]; // rv 0
assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA_delay[49]; // rv 0
assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA_delay[4]; // rv 0
assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA_delay[50]; // rv 0
assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA_delay[51]; // rv 0
assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA_delay[52]; // rv 0
assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA_delay[53]; // rv 0
assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA_delay[54]; // rv 0
assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA_delay[55]; // rv 0
assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA_delay[56]; // rv 0
assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA_delay[57]; // rv 0
assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA_delay[58]; // rv 0
assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA_delay[59]; // rv 0
assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA_delay[5]; // rv 0
assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA_delay[60]; // rv 0
assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA_delay[61]; // rv 0
assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA_delay[62]; // rv 0
assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA_delay[63]; // rv 0
assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA_delay[64]; // rv 0
assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA_delay[65]; // rv 0
assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA_delay[66]; // rv 0
assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA_delay[67]; // rv 0
assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA_delay[68]; // rv 0
assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA_delay[69]; // rv 0
assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA_delay[6]; // rv 0
assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA_delay[70]; // rv 0
assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA_delay[71]; // rv 0
assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA_delay[72]; // rv 0
assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA_delay[73]; // rv 0
assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA_delay[74]; // rv 0
assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA_delay[75]; // rv 0
assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA_delay[76]; // rv 0
assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA_delay[77]; // rv 0
assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA_delay[78]; // rv 0
assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA_delay[79]; // rv 0
assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA_delay[7]; // rv 0
assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA_delay[80]; // rv 0
assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA_delay[81]; // rv 0
assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA_delay[82]; // rv 0
assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA_delay[83]; // rv 0
assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA_delay[84]; // rv 0
assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA_delay[85]; // rv 0
assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA_delay[86]; // rv 0
assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA_delay[87]; // rv 0
assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA_delay[88]; // rv 0
assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA_delay[89]; // rv 0
assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA_delay[8]; // rv 0
assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA_delay[90]; // rv 0
assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA_delay[91]; // rv 0
assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA_delay[92]; // rv 0
assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA_delay[93]; // rv 0
assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA_delay[94]; // rv 0
assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA_delay[95]; // rv 0
assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA_delay[96]; // rv 0
assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA_delay[97]; // rv 0
assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA_delay[98]; // rv 0
assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA_delay[99]; // rv 0
assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA_delay[9]; // rv 0
assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX_delay; // rv 0
assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE_delay; // rv 0
assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER_delay[0]; // rv 0
assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER_delay[1]; // rv 0
assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER_delay[2]; // rv 0
assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER_delay[3]; // rv 0
assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER_delay[4]; // rv 0
assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER_delay[5]; // rv 0
assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT_delay; // rv 0
assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY_delay; // rv 0
assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR_delay; // rv 0
assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL_delay[0]; // rv 0
assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL_delay[1]; // rv 0
assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL_delay[2]; // rv 0
assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL_delay[3]; // rv 0
assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE_delay[0]; // rv 0
assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE_delay[1]; // rv 0
assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE_delay[2]; // rv 0
assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE_delay[3]; // rv 0
assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE_delay[4]; // rv 0
assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE_delay[5]; // rv 0
assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE_delay[6]; // rv 0
assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2_delay; // rv 0
`else
assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR[0]; // rv 0
assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR[1]; // rv 0
assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR[2]; // rv 0
assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR[3]; // rv 0
assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR[4]; // rv 0
assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR[5]; // rv 0
assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR[6]; // rv 0
assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR[7]; // rv 0
assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR[8]; // rv 0
assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR[9]; // rv 0
assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK; // rv 0
assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI[0]; // rv 0
assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI[10]; // rv 0
assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI[11]; // rv 0
assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI[12]; // rv 0
assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI[13]; // rv 0
assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI[14]; // rv 0
assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI[15]; // rv 0
assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI[1]; // rv 0
assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI[2]; // rv 0
assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI[3]; // rv 0
assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI[4]; // rv 0
assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI[5]; // rv 0
assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI[6]; // rv 0
assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI[7]; // rv 0
assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI[8]; // rv 0
assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI[9]; // rv 0
assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN; // rv 0
assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE; // rv 0
assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN; // rv 0
assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN; // rv 0
assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI[0]; // rv 0
assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI[1]; // rv 0
assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI[2]; // rv 0
assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI[3]; // rv 0
assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI[4]; // rv 0
assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL[0]; // rv 0
assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL[1]; // rv 0
assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL[2]; // rv 0
assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER; // rv 0
assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE; // rv 0
assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN; // rv 0
assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP; // rv 0
assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN; // rv 0
assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN; // rv 0
assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY; // rv 0
assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET; // rv 0
assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL[0]; // rv 0
assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL[1]; // rv 0
assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL[2]; // rv 0
assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL[3]; // rv 0
assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE; // rv 0
assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK; // rv 0
assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2; // rv 0
assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK; // rv 0
assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS[0]; // rv 0
assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS[1]; // rv 0
assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS[2]; // rv 0
assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS[3]; // rv 0
assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS[4]; // rv 0
assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS[5]; // rv 0
assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS[6]; // rv 0
assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS[7]; // rv 0
assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN; // rv 0
assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT; // rv 0
assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS; // rv 0
assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE; // rv 0
assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0[0]; // rv 0
assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0[10]; // rv 0
assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0[11]; // rv 0
assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0[12]; // rv 0
assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0[13]; // rv 0
assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0[14]; // rv 0
assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0[15]; // rv 0
assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0[1]; // rv 0
assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0[2]; // rv 0
assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0[3]; // rv 0
assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0[4]; // rv 0
assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0[5]; // rv 0
assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0[6]; // rv 0
assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0[7]; // rv 0
assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0[8]; // rv 0
assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0[9]; // rv 0
assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1[0]; // rv 0
assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1[10]; // rv 0
assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1[11]; // rv 0
assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1[12]; // rv 0
assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1[13]; // rv 0
assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1[14]; // rv 0
assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1[15]; // rv 0
assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1[1]; // rv 0
assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1[2]; // rv 0
assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1[3]; // rv 0
assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1[4]; // rv 0
assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1[5]; // rv 0
assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1[6]; // rv 0
assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1[7]; // rv 0
assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1[8]; // rv 0
assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1[9]; // rv 0
assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2[0]; // rv 0
assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2[1]; // rv 0
assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2[2]; // rv 0
assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2[3]; // rv 0
assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2[4]; // rv 0
assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2[5]; // rv 0
assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2[6]; // rv 0
assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2[7]; // rv 0
assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA[0]; // rv 0
assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA[100]; // rv 0
assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA[101]; // rv 0
assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA[102]; // rv 0
assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA[103]; // rv 0
assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA[104]; // rv 0
assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA[105]; // rv 0
assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA[106]; // rv 0
assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA[107]; // rv 0
assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA[108]; // rv 0
assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA[109]; // rv 0
assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA[10]; // rv 0
assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA[110]; // rv 0
assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA[111]; // rv 0
assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA[112]; // rv 0
assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA[113]; // rv 0
assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA[114]; // rv 0
assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA[115]; // rv 0
assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA[116]; // rv 0
assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA[117]; // rv 0
assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA[118]; // rv 0
assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA[119]; // rv 0
assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA[11]; // rv 0
assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA[120]; // rv 0
assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA[121]; // rv 0
assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA[122]; // rv 0
assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA[123]; // rv 0
assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA[124]; // rv 0
assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA[125]; // rv 0
assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA[126]; // rv 0
assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA[127]; // rv 0
assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA[12]; // rv 0
assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA[13]; // rv 0
assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA[14]; // rv 0
assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA[15]; // rv 0
assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA[16]; // rv 0
assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA[17]; // rv 0
assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA[18]; // rv 0
assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA[19]; // rv 0
assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA[1]; // rv 0
assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA[20]; // rv 0
assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA[21]; // rv 0
assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA[22]; // rv 0
assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA[23]; // rv 0
assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA[24]; // rv 0
assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA[25]; // rv 0
assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA[26]; // rv 0
assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA[27]; // rv 0
assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA[28]; // rv 0
assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA[29]; // rv 0
assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA[2]; // rv 0
assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA[30]; // rv 0
assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA[31]; // rv 0
assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA[32]; // rv 0
assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA[33]; // rv 0
assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA[34]; // rv 0
assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA[35]; // rv 0
assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA[36]; // rv 0
assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA[37]; // rv 0
assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA[38]; // rv 0
assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA[39]; // rv 0
assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA[3]; // rv 0
assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA[40]; // rv 0
assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA[41]; // rv 0
assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA[42]; // rv 0
assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA[43]; // rv 0
assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA[44]; // rv 0
assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA[45]; // rv 0
assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA[46]; // rv 0
assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA[47]; // rv 0
assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA[48]; // rv 0
assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA[49]; // rv 0
assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA[4]; // rv 0
assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA[50]; // rv 0
assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA[51]; // rv 0
assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA[52]; // rv 0
assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA[53]; // rv 0
assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA[54]; // rv 0
assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA[55]; // rv 0
assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA[56]; // rv 0
assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA[57]; // rv 0
assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA[58]; // rv 0
assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA[59]; // rv 0
assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA[5]; // rv 0
assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA[60]; // rv 0
assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA[61]; // rv 0
assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA[62]; // rv 0
assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA[63]; // rv 0
assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA[64]; // rv 0
assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA[65]; // rv 0
assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA[66]; // rv 0
assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA[67]; // rv 0
assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA[68]; // rv 0
assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA[69]; // rv 0
assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA[6]; // rv 0
assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA[70]; // rv 0
assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA[71]; // rv 0
assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA[72]; // rv 0
assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA[73]; // rv 0
assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA[74]; // rv 0
assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA[75]; // rv 0
assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA[76]; // rv 0
assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA[77]; // rv 0
assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA[78]; // rv 0
assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA[79]; // rv 0
assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA[7]; // rv 0
assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA[80]; // rv 0
assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA[81]; // rv 0
assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA[82]; // rv 0
assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA[83]; // rv 0
assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA[84]; // rv 0
assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA[85]; // rv 0
assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA[86]; // rv 0
assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA[87]; // rv 0
assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA[88]; // rv 0
assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA[89]; // rv 0
assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA[8]; // rv 0
assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA[90]; // rv 0
assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA[91]; // rv 0
assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA[92]; // rv 0
assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA[93]; // rv 0
assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA[94]; // rv 0
assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA[95]; // rv 0
assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA[96]; // rv 0
assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA[97]; // rv 0
assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA[98]; // rv 0
assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA[99]; // rv 0
assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA[9]; // rv 0
assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX; // rv 0
assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE; // rv 0
assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER[0]; // rv 0
assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER[1]; // rv 0
assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER[2]; // rv 0
assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER[3]; // rv 0
assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER[4]; // rv 0
assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER[5]; // rv 0
assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT; // rv 0
assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY; // rv 0
assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR; // rv 0
assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL[0]; // rv 0
assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL[1]; // rv 0
assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL[2]; // rv 0
assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL[3]; // rv 0
assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE[0]; // rv 0
assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE[1]; // rv 0
assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE[2]; // rv 0
assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE[3]; // rv 0
assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE[4]; // rv 0
assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE[5]; // rv 0
assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE[6]; // rv 0
assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2; // rv 0
`endif
assign CDRSTEPDIR_in = (CDRSTEPDIR !== 1'bz) && CDRSTEPDIR; // rv 0
assign CDRSTEPSQ_in = (CDRSTEPSQ !== 1'bz) && CDRSTEPSQ; // rv 0
assign CDRSTEPSX_in = (CDRSTEPSX !== 1'bz) && CDRSTEPSX; // rv 0
assign CFGRESET_in = (CFGRESET !== 1'bz) && CFGRESET; // rv 0
assign CLKRSVD0_in = (CLKRSVD0 !== 1'bz) && CLKRSVD0; // rv 0
assign CLKRSVD1_in = (CLKRSVD1 !== 1'bz) && CLKRSVD1; // rv 0
assign CPLLFREQLOCK_in = (CPLLFREQLOCK !== 1'bz) && CPLLFREQLOCK; // rv 0
assign CPLLLOCKDETCLK_in = (CPLLLOCKDETCLK !== 1'bz) && CPLLLOCKDETCLK; // rv 0
assign CPLLLOCKEN_in = (CPLLLOCKEN !== 1'bz) && CPLLLOCKEN; // rv 0
assign CPLLPD_in = (CPLLPD !== 1'bz) && CPLLPD; // rv 0
assign CPLLREFCLKSEL_in[0] = (CPLLREFCLKSEL[0] === 1'bz) || CPLLREFCLKSEL[0]; // rv 1
assign CPLLREFCLKSEL_in[1] = (CPLLREFCLKSEL[1] !== 1'bz) && CPLLREFCLKSEL[1]; // rv 0
assign CPLLREFCLKSEL_in[2] = (CPLLREFCLKSEL[2] !== 1'bz) && CPLLREFCLKSEL[2]; // rv 0
assign CPLLRESET_in = (CPLLRESET !== 1'bz) && CPLLRESET; // rv 0
assign DMONFIFORESET_in = (DMONFIFORESET !== 1'bz) && DMONFIFORESET; // rv 0
assign DMONITORCLK_in = (DMONITORCLK !== 1'bz) && DMONITORCLK; // rv 0
assign DRPRST_in = (DRPRST === 1'bz) || DRPRST; // rv 1
assign EYESCANRESET_in = (EYESCANRESET !== 1'bz) && EYESCANRESET; // rv 0
assign EYESCANTRIGGER_in = (EYESCANTRIGGER !== 1'bz) && EYESCANTRIGGER; // rv 0
assign FREQOS_in = (FREQOS !== 1'bz) && FREQOS; // rv 0
assign GTGREFCLK_in = GTGREFCLK;
assign GTHRXN_in = GTHRXN;
assign GTHRXP_in = GTHRXP;
assign GTNORTHREFCLK0_in = GTNORTHREFCLK0;
assign GTNORTHREFCLK1_in = GTNORTHREFCLK1;
assign GTREFCLK0_in = GTREFCLK0;
assign GTREFCLK1_in = GTREFCLK1;
assign GTRSVD_in[0] = (GTRSVD[0] !== 1'bz) && GTRSVD[0]; // rv 0
assign GTRSVD_in[10] = (GTRSVD[10] !== 1'bz) && GTRSVD[10]; // rv 0
assign GTRSVD_in[11] = (GTRSVD[11] !== 1'bz) && GTRSVD[11]; // rv 0
assign GTRSVD_in[12] = (GTRSVD[12] !== 1'bz) && GTRSVD[12]; // rv 0
assign GTRSVD_in[13] = (GTRSVD[13] !== 1'bz) && GTRSVD[13]; // rv 0
assign GTRSVD_in[14] = (GTRSVD[14] !== 1'bz) && GTRSVD[14]; // rv 0
assign GTRSVD_in[15] = (GTRSVD[15] !== 1'bz) && GTRSVD[15]; // rv 0
assign GTRSVD_in[1] = (GTRSVD[1] !== 1'bz) && GTRSVD[1]; // rv 0
assign GTRSVD_in[2] = (GTRSVD[2] !== 1'bz) && GTRSVD[2]; // rv 0
assign GTRSVD_in[3] = (GTRSVD[3] !== 1'bz) && GTRSVD[3]; // rv 0
assign GTRSVD_in[4] = (GTRSVD[4] !== 1'bz) && GTRSVD[4]; // rv 0
assign GTRSVD_in[5] = (GTRSVD[5] !== 1'bz) && GTRSVD[5]; // rv 0
assign GTRSVD_in[6] = (GTRSVD[6] !== 1'bz) && GTRSVD[6]; // rv 0
assign GTRSVD_in[7] = (GTRSVD[7] !== 1'bz) && GTRSVD[7]; // rv 0
assign GTRSVD_in[8] = (GTRSVD[8] !== 1'bz) && GTRSVD[8]; // rv 0
assign GTRSVD_in[9] = (GTRSVD[9] !== 1'bz) && GTRSVD[9]; // rv 0
assign GTRXRESETSEL_in = (GTRXRESETSEL !== 1'bz) && GTRXRESETSEL; // rv 0
assign GTRXRESET_in = (GTRXRESET !== 1'bz) && GTRXRESET; // rv 0
assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0;
assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1;
assign GTTXRESETSEL_in = (GTTXRESETSEL !== 1'bz) && GTTXRESETSEL; // rv 0
assign GTTXRESET_in = (GTTXRESET !== 1'bz) && GTTXRESET; // rv 0
assign INCPCTRL_in = (INCPCTRL !== 1'bz) && INCPCTRL; // rv 0
assign LOOPBACK_in[0] = (LOOPBACK[0] !== 1'bz) && LOOPBACK[0]; // rv 0
assign LOOPBACK_in[1] = (LOOPBACK[1] !== 1'bz) && LOOPBACK[1]; // rv 0
assign LOOPBACK_in[2] = (LOOPBACK[2] !== 1'bz) && LOOPBACK[2]; // rv 0
assign PCIEEQRXEQADAPTDONE_in = (PCIEEQRXEQADAPTDONE !== 1'bz) && PCIEEQRXEQADAPTDONE; // rv 0
assign PCIERSTIDLE_in = (PCIERSTIDLE !== 1'bz) && PCIERSTIDLE; // rv 0
assign PCIERSTTXSYNCSTART_in = (PCIERSTTXSYNCSTART !== 1'bz) && PCIERSTTXSYNCSTART; // rv 0
assign PCIEUSERRATEDONE_in = (PCIEUSERRATEDONE !== 1'bz) && PCIEUSERRATEDONE; // rv 0
assign PCSRSVDIN_in[0] = (PCSRSVDIN[0] === 1'bz) || PCSRSVDIN[0]; // rv 1
assign PCSRSVDIN_in[10] = (PCSRSVDIN[10] !== 1'bz) && PCSRSVDIN[10]; // rv 0
assign PCSRSVDIN_in[11] = (PCSRSVDIN[11] !== 1'bz) && PCSRSVDIN[11]; // rv 0
assign PCSRSVDIN_in[12] = (PCSRSVDIN[12] !== 1'bz) && PCSRSVDIN[12]; // rv 0
assign PCSRSVDIN_in[13] = (PCSRSVDIN[13] !== 1'bz) && PCSRSVDIN[13]; // rv 0
assign PCSRSVDIN_in[14] = (PCSRSVDIN[14] !== 1'bz) && PCSRSVDIN[14]; // rv 0
assign PCSRSVDIN_in[15] = (PCSRSVDIN[15] !== 1'bz) && PCSRSVDIN[15]; // rv 0
assign PCSRSVDIN_in[1] = (PCSRSVDIN[1] !== 1'bz) && PCSRSVDIN[1]; // rv 0
assign PCSRSVDIN_in[2] = (PCSRSVDIN[2] !== 1'bz) && PCSRSVDIN[2]; // rv 0
assign PCSRSVDIN_in[3] = (PCSRSVDIN[3] !== 1'bz) && PCSRSVDIN[3]; // rv 0
assign PCSRSVDIN_in[4] = (PCSRSVDIN[4] !== 1'bz) && PCSRSVDIN[4]; // rv 0
assign PCSRSVDIN_in[5] = (PCSRSVDIN[5] !== 1'bz) && PCSRSVDIN[5]; // rv 0
assign PCSRSVDIN_in[6] = (PCSRSVDIN[6] !== 1'bz) && PCSRSVDIN[6]; // rv 0
assign PCSRSVDIN_in[7] = (PCSRSVDIN[7] !== 1'bz) && PCSRSVDIN[7]; // rv 0
assign PCSRSVDIN_in[8] = (PCSRSVDIN[8] !== 1'bz) && PCSRSVDIN[8]; // rv 0
assign PCSRSVDIN_in[9] = (PCSRSVDIN[9] !== 1'bz) && PCSRSVDIN[9]; // rv 0
assign QPLL0CLK_in = QPLL0CLK;
assign QPLL0FREQLOCK_in = (QPLL0FREQLOCK !== 1'bz) && QPLL0FREQLOCK; // rv 0
assign QPLL0REFCLK_in = QPLL0REFCLK;
assign QPLL1CLK_in = QPLL1CLK;
assign QPLL1FREQLOCK_in = (QPLL1FREQLOCK !== 1'bz) && QPLL1FREQLOCK; // rv 0
assign QPLL1REFCLK_in = QPLL1REFCLK;
assign RESETOVRD_in = (RESETOVRD !== 1'bz) && RESETOVRD; // rv 0
assign RXAFECFOKEN_in = (RXAFECFOKEN === 1'bz) || RXAFECFOKEN; // rv 1
assign RXBUFRESET_in = (RXBUFRESET !== 1'bz) && RXBUFRESET; // rv 0
assign RXCDRFREQRESET_in = (RXCDRFREQRESET !== 1'bz) && RXCDRFREQRESET; // rv 0
assign RXCDRHOLD_in = (RXCDRHOLD !== 1'bz) && RXCDRHOLD; // rv 0
assign RXCDROVRDEN_in = (RXCDROVRDEN !== 1'bz) && RXCDROVRDEN; // rv 0
assign RXCDRRESET_in = (RXCDRRESET !== 1'bz) && RXCDRRESET; // rv 0
assign RXCKCALRESET_in = (RXCKCALRESET !== 1'bz) && RXCKCALRESET; // rv 0
assign RXCKCALSTART_in[0] = (RXCKCALSTART[0] !== 1'bz) && RXCKCALSTART[0]; // rv 0
assign RXCKCALSTART_in[1] = (RXCKCALSTART[1] !== 1'bz) && RXCKCALSTART[1]; // rv 0
assign RXCKCALSTART_in[2] = (RXCKCALSTART[2] !== 1'bz) && RXCKCALSTART[2]; // rv 0
assign RXCKCALSTART_in[3] = (RXCKCALSTART[3] !== 1'bz) && RXCKCALSTART[3]; // rv 0
assign RXCKCALSTART_in[4] = (RXCKCALSTART[4] !== 1'bz) && RXCKCALSTART[4]; // rv 0
assign RXCKCALSTART_in[5] = (RXCKCALSTART[5] !== 1'bz) && RXCKCALSTART[5]; // rv 0
assign RXCKCALSTART_in[6] = (RXCKCALSTART[6] !== 1'bz) && RXCKCALSTART[6]; // rv 0
assign RXDFEAGCCTRL_in[0] = (RXDFEAGCCTRL[0] !== 1'bz) && RXDFEAGCCTRL[0]; // rv 0
assign RXDFEAGCCTRL_in[1] = (RXDFEAGCCTRL[1] !== 1'bz) && RXDFEAGCCTRL[1]; // rv 0
assign RXDFEAGCHOLD_in = (RXDFEAGCHOLD !== 1'bz) && RXDFEAGCHOLD; // rv 0
assign RXDFEAGCOVRDEN_in = (RXDFEAGCOVRDEN !== 1'bz) && RXDFEAGCOVRDEN; // rv 0
assign RXDFECFOKFCNUM_in[0] = (RXDFECFOKFCNUM[0] !== 1'bz) && RXDFECFOKFCNUM[0]; // rv 0
assign RXDFECFOKFCNUM_in[1] = (RXDFECFOKFCNUM[1] === 1'bz) || RXDFECFOKFCNUM[1]; // rv 1
assign RXDFECFOKFCNUM_in[2] = (RXDFECFOKFCNUM[2] === 1'bz) || RXDFECFOKFCNUM[2]; // rv 1
assign RXDFECFOKFCNUM_in[3] = (RXDFECFOKFCNUM[3] !== 1'bz) && RXDFECFOKFCNUM[3]; // rv 0
assign RXDFECFOKFEN_in = (RXDFECFOKFEN !== 1'bz) && RXDFECFOKFEN; // rv 0
assign RXDFECFOKFPULSE_in = (RXDFECFOKFPULSE !== 1'bz) && RXDFECFOKFPULSE; // rv 0
assign RXDFECFOKHOLD_in = (RXDFECFOKHOLD !== 1'bz) && RXDFECFOKHOLD; // rv 0
assign RXDFECFOKOVREN_in = (RXDFECFOKOVREN !== 1'bz) && RXDFECFOKOVREN; // rv 0
assign RXDFEKHHOLD_in = (RXDFEKHHOLD !== 1'bz) && RXDFEKHHOLD; // rv 0
assign RXDFEKHOVRDEN_in = (RXDFEKHOVRDEN !== 1'bz) && RXDFEKHOVRDEN; // rv 0
assign RXDFELFHOLD_in = (RXDFELFHOLD !== 1'bz) && RXDFELFHOLD; // rv 0
assign RXDFELFOVRDEN_in = (RXDFELFOVRDEN !== 1'bz) && RXDFELFOVRDEN; // rv 0
assign RXDFELPMRESET_in = (RXDFELPMRESET !== 1'bz) && RXDFELPMRESET; // rv 0
assign RXDFETAP10HOLD_in = (RXDFETAP10HOLD !== 1'bz) && RXDFETAP10HOLD; // rv 0
assign RXDFETAP10OVRDEN_in = (RXDFETAP10OVRDEN !== 1'bz) && RXDFETAP10OVRDEN; // rv 0
assign RXDFETAP11HOLD_in = (RXDFETAP11HOLD !== 1'bz) && RXDFETAP11HOLD; // rv 0
assign RXDFETAP11OVRDEN_in = (RXDFETAP11OVRDEN !== 1'bz) && RXDFETAP11OVRDEN; // rv 0
assign RXDFETAP12HOLD_in = (RXDFETAP12HOLD !== 1'bz) && RXDFETAP12HOLD; // rv 0
assign RXDFETAP12OVRDEN_in = (RXDFETAP12OVRDEN !== 1'bz) && RXDFETAP12OVRDEN; // rv 0
assign RXDFETAP13HOLD_in = (RXDFETAP13HOLD !== 1'bz) && RXDFETAP13HOLD; // rv 0
assign RXDFETAP13OVRDEN_in = (RXDFETAP13OVRDEN !== 1'bz) && RXDFETAP13OVRDEN; // rv 0
assign RXDFETAP14HOLD_in = (RXDFETAP14HOLD !== 1'bz) && RXDFETAP14HOLD; // rv 0
assign RXDFETAP14OVRDEN_in = (RXDFETAP14OVRDEN !== 1'bz) && RXDFETAP14OVRDEN; // rv 0
assign RXDFETAP15HOLD_in = (RXDFETAP15HOLD !== 1'bz) && RXDFETAP15HOLD; // rv 0
assign RXDFETAP15OVRDEN_in = (RXDFETAP15OVRDEN !== 1'bz) && RXDFETAP15OVRDEN; // rv 0
assign RXDFETAP2HOLD_in = (RXDFETAP2HOLD !== 1'bz) && RXDFETAP2HOLD; // rv 0
assign RXDFETAP2OVRDEN_in = (RXDFETAP2OVRDEN !== 1'bz) && RXDFETAP2OVRDEN; // rv 0
assign RXDFETAP3HOLD_in = (RXDFETAP3HOLD !== 1'bz) && RXDFETAP3HOLD; // rv 0
assign RXDFETAP3OVRDEN_in = (RXDFETAP3OVRDEN !== 1'bz) && RXDFETAP3OVRDEN; // rv 0
assign RXDFETAP4HOLD_in = (RXDFETAP4HOLD !== 1'bz) && RXDFETAP4HOLD; // rv 0
assign RXDFETAP4OVRDEN_in = (RXDFETAP4OVRDEN !== 1'bz) && RXDFETAP4OVRDEN; // rv 0
assign RXDFETAP5HOLD_in = (RXDFETAP5HOLD !== 1'bz) && RXDFETAP5HOLD; // rv 0
assign RXDFETAP5OVRDEN_in = (RXDFETAP5OVRDEN !== 1'bz) && RXDFETAP5OVRDEN; // rv 0
assign RXDFETAP6HOLD_in = (RXDFETAP6HOLD !== 1'bz) && RXDFETAP6HOLD; // rv 0
assign RXDFETAP6OVRDEN_in = (RXDFETAP6OVRDEN !== 1'bz) && RXDFETAP6OVRDEN; // rv 0
assign RXDFETAP7HOLD_in = (RXDFETAP7HOLD !== 1'bz) && RXDFETAP7HOLD; // rv 0
assign RXDFETAP7OVRDEN_in = (RXDFETAP7OVRDEN !== 1'bz) && RXDFETAP7OVRDEN; // rv 0
assign RXDFETAP8HOLD_in = (RXDFETAP8HOLD !== 1'bz) && RXDFETAP8HOLD; // rv 0
assign RXDFETAP8OVRDEN_in = (RXDFETAP8OVRDEN !== 1'bz) && RXDFETAP8OVRDEN; // rv 0
assign RXDFETAP9HOLD_in = (RXDFETAP9HOLD !== 1'bz) && RXDFETAP9HOLD; // rv 0
assign RXDFETAP9OVRDEN_in = (RXDFETAP9OVRDEN !== 1'bz) && RXDFETAP9OVRDEN; // rv 0
assign RXDFEUTHOLD_in = (RXDFEUTHOLD !== 1'bz) && RXDFEUTHOLD; // rv 0
assign RXDFEUTOVRDEN_in = (RXDFEUTOVRDEN !== 1'bz) && RXDFEUTOVRDEN; // rv 0
assign RXDFEVPHOLD_in = (RXDFEVPHOLD !== 1'bz) && RXDFEVPHOLD; // rv 0
assign RXDFEVPOVRDEN_in = (RXDFEVPOVRDEN !== 1'bz) && RXDFEVPOVRDEN; // rv 0
assign RXDFEXYDEN_in = (RXDFEXYDEN !== 1'bz) && RXDFEXYDEN; // rv 0
assign RXDLYBYPASS_in = (RXDLYBYPASS !== 1'bz) && RXDLYBYPASS; // rv 0
assign RXDLYEN_in = (RXDLYEN !== 1'bz) && RXDLYEN; // rv 0
assign RXDLYOVRDEN_in = (RXDLYOVRDEN !== 1'bz) && RXDLYOVRDEN; // rv 0
assign RXDLYSRESET_in = (RXDLYSRESET !== 1'bz) && RXDLYSRESET; // rv 0
assign RXELECIDLEMODE_in[0] = (RXELECIDLEMODE[0] !== 1'bz) && RXELECIDLEMODE[0]; // rv 0
assign RXELECIDLEMODE_in[1] = (RXELECIDLEMODE[1] !== 1'bz) && RXELECIDLEMODE[1]; // rv 0
assign RXEQTRAINING_in = (RXEQTRAINING !== 1'bz) && RXEQTRAINING; // rv 0
assign RXLATCLK_in = (RXLATCLK !== 1'bz) && RXLATCLK; // rv 0
assign RXLPMEN_in = (RXLPMEN !== 1'bz) && RXLPMEN; // rv 0
assign RXLPMGCHOLD_in = (RXLPMGCHOLD !== 1'bz) && RXLPMGCHOLD; // rv 0
assign RXLPMGCOVRDEN_in = (RXLPMGCOVRDEN !== 1'bz) && RXLPMGCOVRDEN; // rv 0
assign RXLPMHFHOLD_in = (RXLPMHFHOLD !== 1'bz) && RXLPMHFHOLD; // rv 0
assign RXLPMHFOVRDEN_in = (RXLPMHFOVRDEN !== 1'bz) && RXLPMHFOVRDEN; // rv 0
assign RXLPMLFHOLD_in = (RXLPMLFHOLD !== 1'bz) && RXLPMLFHOLD; // rv 0
assign RXLPMLFKLOVRDEN_in = (RXLPMLFKLOVRDEN !== 1'bz) && RXLPMLFKLOVRDEN; // rv 0
assign RXLPMOSHOLD_in = (RXLPMOSHOLD !== 1'bz) && RXLPMOSHOLD; // rv 0
assign RXLPMOSOVRDEN_in = (RXLPMOSOVRDEN !== 1'bz) && RXLPMOSOVRDEN; // rv 0
assign RXMONITORSEL_in[0] = (RXMONITORSEL[0] !== 1'bz) && RXMONITORSEL[0]; // rv 0
assign RXMONITORSEL_in[1] = (RXMONITORSEL[1] !== 1'bz) && RXMONITORSEL[1]; // rv 0
assign RXOOBRESET_in = (RXOOBRESET !== 1'bz) && RXOOBRESET; // rv 0
assign RXOSCALRESET_in = (RXOSCALRESET !== 1'bz) && RXOSCALRESET; // rv 0
assign RXOSHOLD_in = (RXOSHOLD !== 1'bz) && RXOSHOLD; // rv 0
assign RXOSOVRDEN_in = (RXOSOVRDEN !== 1'bz) && RXOSOVRDEN; // rv 0
assign RXOUTCLKSEL_in[0] = (RXOUTCLKSEL[0] !== 1'bz) && RXOUTCLKSEL[0]; // rv 0
assign RXOUTCLKSEL_in[1] = (RXOUTCLKSEL[1] !== 1'bz) && RXOUTCLKSEL[1]; // rv 0
assign RXOUTCLKSEL_in[2] = (RXOUTCLKSEL[2] !== 1'bz) && RXOUTCLKSEL[2]; // rv 0
assign RXPCSRESET_in = (RXPCSRESET !== 1'bz) && RXPCSRESET; // rv 0
assign RXPD_in[0] = (RXPD[0] !== 1'bz) && RXPD[0]; // rv 0
assign RXPD_in[1] = (RXPD[1] !== 1'bz) && RXPD[1]; // rv 0
assign RXPHALIGNEN_in = (RXPHALIGNEN !== 1'bz) && RXPHALIGNEN; // rv 0
assign RXPHALIGN_in = (RXPHALIGN !== 1'bz) && RXPHALIGN; // rv 0
assign RXPHDLYPD_in = (RXPHDLYPD !== 1'bz) && RXPHDLYPD; // rv 0
assign RXPHDLYRESET_in = (RXPHDLYRESET !== 1'bz) && RXPHDLYRESET; // rv 0
assign RXPHOVRDEN_in = (RXPHOVRDEN !== 1'bz) && RXPHOVRDEN; // rv 0
assign RXPLLCLKSEL_in[0] = (RXPLLCLKSEL[0] !== 1'bz) && RXPLLCLKSEL[0]; // rv 0
assign RXPLLCLKSEL_in[1] = (RXPLLCLKSEL[1] !== 1'bz) && RXPLLCLKSEL[1]; // rv 0
assign RXPMARESET_in = (RXPMARESET !== 1'bz) && RXPMARESET; // rv 0
assign RXPROGDIVRESET_in = (RXPROGDIVRESET !== 1'bz) && RXPROGDIVRESET; // rv 0
assign RXQPIEN_in = (RXQPIEN !== 1'bz) && RXQPIEN; // rv 0
assign RXRATEMODE_in = (RXRATEMODE !== 1'bz) && RXRATEMODE; // rv 0
assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE[0]; // rv 0
assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE[1]; // rv 0
assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE[2]; // rv 0
assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA; // rv 0
assign RXSYNCALLIN_in = (RXSYNCALLIN !== 1'bz) && RXSYNCALLIN; // rv 0
assign RXSYNCIN_in = (RXSYNCIN !== 1'bz) && RXSYNCIN; // rv 0
assign RXSYNCMODE_in = (RXSYNCMODE === 1'bz) || RXSYNCMODE; // rv 1
assign RXSYSCLKSEL_in[0] = (RXSYSCLKSEL[0] !== 1'bz) && RXSYSCLKSEL[0]; // rv 0
assign RXSYSCLKSEL_in[1] = (RXSYSCLKSEL[1] !== 1'bz) && RXSYSCLKSEL[1]; // rv 0
assign RXTERMINATION_in = (RXTERMINATION !== 1'bz) && RXTERMINATION; // rv 0
assign RXUSERRDY_in = (RXUSERRDY !== 1'bz) && RXUSERRDY; // rv 0
assign SIGVALIDCLK_in = (SIGVALIDCLK !== 1'bz) && SIGVALIDCLK; // rv 0
assign TSTIN_in[0] = (TSTIN[0] !== 1'bz) && TSTIN[0]; // rv 0
assign TSTIN_in[10] = (TSTIN[10] !== 1'bz) && TSTIN[10]; // rv 0
assign TSTIN_in[11] = (TSTIN[11] !== 1'bz) && TSTIN[11]; // rv 0
assign TSTIN_in[12] = (TSTIN[12] !== 1'bz) && TSTIN[12]; // rv 0
assign TSTIN_in[13] = (TSTIN[13] !== 1'bz) && TSTIN[13]; // rv 0
assign TSTIN_in[14] = (TSTIN[14] !== 1'bz) && TSTIN[14]; // rv 0
assign TSTIN_in[15] = (TSTIN[15] !== 1'bz) && TSTIN[15]; // rv 0
assign TSTIN_in[16] = (TSTIN[16] !== 1'bz) && TSTIN[16]; // rv 0
assign TSTIN_in[17] = (TSTIN[17] !== 1'bz) && TSTIN[17]; // rv 0
assign TSTIN_in[18] = (TSTIN[18] !== 1'bz) && TSTIN[18]; // rv 0
assign TSTIN_in[19] = (TSTIN[19] !== 1'bz) && TSTIN[19]; // rv 0
assign TSTIN_in[1] = (TSTIN[1] !== 1'bz) && TSTIN[1]; // rv 0
assign TSTIN_in[2] = (TSTIN[2] !== 1'bz) && TSTIN[2]; // rv 0
assign TSTIN_in[3] = (TSTIN[3] !== 1'bz) && TSTIN[3]; // rv 0
assign TSTIN_in[4] = (TSTIN[4] !== 1'bz) && TSTIN[4]; // rv 0
assign TSTIN_in[5] = (TSTIN[5] !== 1'bz) && TSTIN[5]; // rv 0
assign TSTIN_in[6] = (TSTIN[6] !== 1'bz) && TSTIN[6]; // rv 0
assign TSTIN_in[7] = (TSTIN[7] !== 1'bz) && TSTIN[7]; // rv 0
assign TSTIN_in[8] = (TSTIN[8] !== 1'bz) && TSTIN[8]; // rv 0
assign TSTIN_in[9] = (TSTIN[9] !== 1'bz) && TSTIN[9]; // rv 0
assign TXDATAEXTENDRSVD_in[0] = (TXDATAEXTENDRSVD[0] !== 1'bz) && TXDATAEXTENDRSVD[0]; // rv 0
assign TXDATAEXTENDRSVD_in[1] = (TXDATAEXTENDRSVD[1] !== 1'bz) && TXDATAEXTENDRSVD[1]; // rv 0
assign TXDATAEXTENDRSVD_in[2] = (TXDATAEXTENDRSVD[2] !== 1'bz) && TXDATAEXTENDRSVD[2]; // rv 0
assign TXDATAEXTENDRSVD_in[3] = (TXDATAEXTENDRSVD[3] !== 1'bz) && TXDATAEXTENDRSVD[3]; // rv 0
assign TXDATAEXTENDRSVD_in[4] = (TXDATAEXTENDRSVD[4] !== 1'bz) && TXDATAEXTENDRSVD[4]; // rv 0
assign TXDATAEXTENDRSVD_in[5] = (TXDATAEXTENDRSVD[5] !== 1'bz) && TXDATAEXTENDRSVD[5]; // rv 0
assign TXDATAEXTENDRSVD_in[6] = (TXDATAEXTENDRSVD[6] !== 1'bz) && TXDATAEXTENDRSVD[6]; // rv 0
assign TXDATAEXTENDRSVD_in[7] = (TXDATAEXTENDRSVD[7] !== 1'bz) && TXDATAEXTENDRSVD[7]; // rv 0
assign TXDCCFORCESTART_in = (TXDCCFORCESTART !== 1'bz) && TXDCCFORCESTART; // rv 0
assign TXDCCRESET_in = (TXDCCRESET !== 1'bz) && TXDCCRESET; // rv 0
assign TXDEEMPH_in[0] = (TXDEEMPH[0] !== 1'bz) && TXDEEMPH[0]; // rv 0
assign TXDEEMPH_in[1] = (TXDEEMPH[1] !== 1'bz) && TXDEEMPH[1]; // rv 0
assign TXDIFFCTRL_in[0] = (TXDIFFCTRL[0] !== 1'bz) && TXDIFFCTRL[0]; // rv 0
assign TXDIFFCTRL_in[1] = (TXDIFFCTRL[1] !== 1'bz) && TXDIFFCTRL[1]; // rv 0
assign TXDIFFCTRL_in[2] = (TXDIFFCTRL[2] !== 1'bz) && TXDIFFCTRL[2]; // rv 0
assign TXDIFFCTRL_in[3] = (TXDIFFCTRL[3] !== 1'bz) && TXDIFFCTRL[3]; // rv 0
assign TXDIFFCTRL_in[4] = (TXDIFFCTRL[4] !== 1'bz) && TXDIFFCTRL[4]; // rv 0
assign TXDLYBYPASS_in = (TXDLYBYPASS !== 1'bz) && TXDLYBYPASS; // rv 0
assign TXDLYEN_in = (TXDLYEN !== 1'bz) && TXDLYEN; // rv 0
assign TXDLYHOLD_in = (TXDLYHOLD !== 1'bz) && TXDLYHOLD; // rv 0
assign TXDLYOVRDEN_in = (TXDLYOVRDEN !== 1'bz) && TXDLYOVRDEN; // rv 0
assign TXDLYSRESET_in = (TXDLYSRESET !== 1'bz) && TXDLYSRESET; // rv 0
assign TXDLYUPDOWN_in = (TXDLYUPDOWN !== 1'bz) && TXDLYUPDOWN; // rv 0
assign TXLATCLK_in = (TXLATCLK !== 1'bz) && TXLATCLK; // rv 0
assign TXLFPSTRESET_in = (TXLFPSTRESET !== 1'bz) && TXLFPSTRESET; // rv 0
assign TXLFPSU2LPEXIT_in = (TXLFPSU2LPEXIT !== 1'bz) && TXLFPSU2LPEXIT; // rv 0
assign TXLFPSU3WAKE_in = (TXLFPSU3WAKE !== 1'bz) && TXLFPSU3WAKE; // rv 0
assign TXMAINCURSOR_in[0] = (TXMAINCURSOR[0] !== 1'bz) && TXMAINCURSOR[0]; // rv 0
assign TXMAINCURSOR_in[1] = (TXMAINCURSOR[1] !== 1'bz) && TXMAINCURSOR[1]; // rv 0
assign TXMAINCURSOR_in[2] = (TXMAINCURSOR[2] !== 1'bz) && TXMAINCURSOR[2]; // rv 0
assign TXMAINCURSOR_in[3] = (TXMAINCURSOR[3] !== 1'bz) && TXMAINCURSOR[3]; // rv 0
assign TXMAINCURSOR_in[4] = (TXMAINCURSOR[4] !== 1'bz) && TXMAINCURSOR[4]; // rv 0
assign TXMAINCURSOR_in[5] = (TXMAINCURSOR[5] !== 1'bz) && TXMAINCURSOR[5]; // rv 0
assign TXMAINCURSOR_in[6] = (TXMAINCURSOR[6] !== 1'bz) && TXMAINCURSOR[6]; // rv 0
assign TXMARGIN_in[0] = (TXMARGIN[0] !== 1'bz) && TXMARGIN[0]; // rv 0
assign TXMARGIN_in[1] = (TXMARGIN[1] !== 1'bz) && TXMARGIN[1]; // rv 0
assign TXMARGIN_in[2] = (TXMARGIN[2] !== 1'bz) && TXMARGIN[2]; // rv 0
assign TXMUXDCDEXHOLD_in = (TXMUXDCDEXHOLD !== 1'bz) && TXMUXDCDEXHOLD; // rv 0
assign TXMUXDCDORWREN_in = (TXMUXDCDORWREN !== 1'bz) && TXMUXDCDORWREN; // rv 0
assign TXONESZEROS_in = (TXONESZEROS !== 1'bz) && TXONESZEROS; // rv 0
assign TXOUTCLKSEL_in[0] = (TXOUTCLKSEL[0] !== 1'bz) && TXOUTCLKSEL[0]; // rv 0
assign TXOUTCLKSEL_in[1] = (TXOUTCLKSEL[1] !== 1'bz) && TXOUTCLKSEL[1]; // rv 0
assign TXOUTCLKSEL_in[2] = (TXOUTCLKSEL[2] !== 1'bz) && TXOUTCLKSEL[2]; // rv 0
assign TXPCSRESET_in = (TXPCSRESET !== 1'bz) && TXPCSRESET; // rv 0
assign TXPDELECIDLEMODE_in = (TXPDELECIDLEMODE !== 1'bz) && TXPDELECIDLEMODE; // rv 0
assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD[0]; // rv 0
assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD[1]; // rv 0
assign TXPHALIGNEN_in = (TXPHALIGNEN !== 1'bz) && TXPHALIGNEN; // rv 0
assign TXPHALIGN_in = (TXPHALIGN !== 1'bz) && TXPHALIGN; // rv 0
assign TXPHDLYPD_in = (TXPHDLYPD !== 1'bz) && TXPHDLYPD; // rv 0
assign TXPHDLYRESET_in = (TXPHDLYRESET !== 1'bz) && TXPHDLYRESET; // rv 0
assign TXPHDLYTSTCLK_in = (TXPHDLYTSTCLK !== 1'bz) && TXPHDLYTSTCLK; // rv 0
assign TXPHINIT_in = (TXPHINIT !== 1'bz) && TXPHINIT; // rv 0
assign TXPHOVRDEN_in = (TXPHOVRDEN !== 1'bz) && TXPHOVRDEN; // rv 0
assign TXPIPPMEN_in = (TXPIPPMEN !== 1'bz) && TXPIPPMEN; // rv 0
assign TXPIPPMOVRDEN_in = (TXPIPPMOVRDEN !== 1'bz) && TXPIPPMOVRDEN; // rv 0
assign TXPIPPMPD_in = (TXPIPPMPD !== 1'bz) && TXPIPPMPD; // rv 0
assign TXPIPPMSEL_in = (TXPIPPMSEL !== 1'bz) && TXPIPPMSEL; // rv 0
assign TXPIPPMSTEPSIZE_in[0] = (TXPIPPMSTEPSIZE[0] !== 1'bz) && TXPIPPMSTEPSIZE[0]; // rv 0
assign TXPIPPMSTEPSIZE_in[1] = (TXPIPPMSTEPSIZE[1] !== 1'bz) && TXPIPPMSTEPSIZE[1]; // rv 0
assign TXPIPPMSTEPSIZE_in[2] = (TXPIPPMSTEPSIZE[2] !== 1'bz) && TXPIPPMSTEPSIZE[2]; // rv 0
assign TXPIPPMSTEPSIZE_in[3] = (TXPIPPMSTEPSIZE[3] !== 1'bz) && TXPIPPMSTEPSIZE[3]; // rv 0
assign TXPIPPMSTEPSIZE_in[4] = (TXPIPPMSTEPSIZE[4] !== 1'bz) && TXPIPPMSTEPSIZE[4]; // rv 0
assign TXPISOPD_in = (TXPISOPD !== 1'bz) && TXPISOPD; // rv 0
assign TXPLLCLKSEL_in[0] = (TXPLLCLKSEL[0] !== 1'bz) && TXPLLCLKSEL[0]; // rv 0
assign TXPLLCLKSEL_in[1] = (TXPLLCLKSEL[1] !== 1'bz) && TXPLLCLKSEL[1]; // rv 0
assign TXPMARESET_in = (TXPMARESET !== 1'bz) && TXPMARESET; // rv 0
assign TXPOSTCURSOR_in[0] = (TXPOSTCURSOR[0] !== 1'bz) && TXPOSTCURSOR[0]; // rv 0
assign TXPOSTCURSOR_in[1] = (TXPOSTCURSOR[1] !== 1'bz) && TXPOSTCURSOR[1]; // rv 0
assign TXPOSTCURSOR_in[2] = (TXPOSTCURSOR[2] !== 1'bz) && TXPOSTCURSOR[2]; // rv 0
assign TXPOSTCURSOR_in[3] = (TXPOSTCURSOR[3] !== 1'bz) && TXPOSTCURSOR[3]; // rv 0
assign TXPOSTCURSOR_in[4] = (TXPOSTCURSOR[4] !== 1'bz) && TXPOSTCURSOR[4]; // rv 0
assign TXPRECURSOR_in[0] = (TXPRECURSOR[0] !== 1'bz) && TXPRECURSOR[0]; // rv 0
assign TXPRECURSOR_in[1] = (TXPRECURSOR[1] !== 1'bz) && TXPRECURSOR[1]; // rv 0
assign TXPRECURSOR_in[2] = (TXPRECURSOR[2] !== 1'bz) && TXPRECURSOR[2]; // rv 0
assign TXPRECURSOR_in[3] = (TXPRECURSOR[3] !== 1'bz) && TXPRECURSOR[3]; // rv 0
assign TXPRECURSOR_in[4] = (TXPRECURSOR[4] !== 1'bz) && TXPRECURSOR[4]; // rv 0
assign TXPROGDIVRESET_in = (TXPROGDIVRESET !== 1'bz) && TXPROGDIVRESET; // rv 0
assign TXQPIBIASEN_in = (TXQPIBIASEN !== 1'bz) && TXQPIBIASEN; // rv 0
assign TXQPIWEAKPUP_in = (TXQPIWEAKPUP !== 1'bz) && TXQPIWEAKPUP; // rv 0
assign TXRATEMODE_in = (TXRATEMODE !== 1'bz) && TXRATEMODE; // rv 0
assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE[0]; // rv 0
assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE[1]; // rv 0
assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE[2]; // rv 0
assign TXSWING_in = (TXSWING !== 1'bz) && TXSWING; // rv 0
assign TXSYNCALLIN_in = (TXSYNCALLIN !== 1'bz) && TXSYNCALLIN; // rv 0
assign TXSYNCIN_in = (TXSYNCIN !== 1'bz) && TXSYNCIN; // rv 0
assign TXSYNCMODE_in = (TXSYNCMODE === 1'bz) || TXSYNCMODE; // rv 1
assign TXSYSCLKSEL_in[0] = (TXSYSCLKSEL[0] !== 1'bz) && TXSYSCLKSEL[0]; // rv 0
assign TXSYSCLKSEL_in[1] = (TXSYSCLKSEL[1] !== 1'bz) && TXSYSCLKSEL[1]; // rv 0
assign TXUSERRDY_in = (TXUSERRDY !== 1'bz) && TXUSERRDY; // rv 0
assign TXUSRCLK_in = (TXUSRCLK !== 1'bz) && TXUSRCLK; // rv 0
assign gt_intclk = gt_clk_int;
initial begin
#1;
trig_attr = ~trig_attr;
gt_clk_int = 1'b0;
forever #10000 gt_clk_int = ~gt_clk_int;
end
`ifdef XIL_XECLIB
assign RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000;
assign TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000;
`else
always @ (trig_attr) begin
#1;
RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000;
TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_DOUBLE_REG != "FALSE") &&
(ALIGN_COMMA_DOUBLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-130] ALIGN_COMMA_DOUBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_WORD_REG != 1) &&
(ALIGN_COMMA_WORD_REG != 2) &&
(ALIGN_COMMA_WORD_REG != 4))) begin
$display("Error: [Unisim %s-132] ALIGN_COMMA_WORD attribute is set to %d. Legal values for this attribute are 1, 2 or 4. Instance: %m", MODULE_NAME, ALIGN_COMMA_WORD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_MCOMMA_DET_REG != "TRUE") &&
(ALIGN_MCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-133] ALIGN_MCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_PCOMMA_DET_REG != "TRUE") &&
(ALIGN_PCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-135] ALIGN_PCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CBCC_DATA_SOURCE_SEL_REG != "DECODED") &&
(CBCC_DATA_SOURCE_SEL_REG != "ENCODED"))) begin
$display("Error: [Unisim %s-273] CBCC_DATA_SOURCE_SEL attribute is set to %s. Legal values for this attribute are DECODED or ENCODED. Instance: %m", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") &&
(CHAN_BOND_KEEP_ALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-276] CHAN_BOND_KEEP_ALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_MAX_SKEW_REG != 7) &&
(CHAN_BOND_MAX_SKEW_REG != 1) &&
(CHAN_BOND_MAX_SKEW_REG != 2) &&
(CHAN_BOND_MAX_SKEW_REG != 3) &&
(CHAN_BOND_MAX_SKEW_REG != 4) &&
(CHAN_BOND_MAX_SKEW_REG != 5) &&
(CHAN_BOND_MAX_SKEW_REG != 6) &&
(CHAN_BOND_MAX_SKEW_REG != 8) &&
(CHAN_BOND_MAX_SKEW_REG != 9) &&
(CHAN_BOND_MAX_SKEW_REG != 10) &&
(CHAN_BOND_MAX_SKEW_REG != 11) &&
(CHAN_BOND_MAX_SKEW_REG != 12) &&
(CHAN_BOND_MAX_SKEW_REG != 13) &&
(CHAN_BOND_MAX_SKEW_REG != 14))) begin
$display("Error: [Unisim %s-277] CHAN_BOND_MAX_SKEW attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13 or 14. Instance: %m", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_USE_REG != "FALSE") &&
(CHAN_BOND_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-288] CHAN_BOND_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_LEN_REG != 2) &&
(CHAN_BOND_SEQ_LEN_REG != 1) &&
(CHAN_BOND_SEQ_LEN_REG != 3) &&
(CHAN_BOND_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-289] CHAN_BOND_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_CORRECT_USE_REG != "TRUE") &&
(CLK_CORRECT_USE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-302] CLK_CORRECT_USE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_CORRECT_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_KEEP_IDLE_REG != "FALSE") &&
(CLK_COR_KEEP_IDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-303] CLK_COR_KEEP_IDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_KEEP_IDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60))) begin
$display("Error: [Unisim %s-304] CLK_COR_MAX_LAT attribute is set to %d. Legal values for this attribute are 3 to 60. Instance: %m", MODULE_NAME, CLK_COR_MAX_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63))) begin
$display("Error: [Unisim %s-305] CLK_COR_MIN_LAT attribute is set to %d. Legal values for this attribute are 3 to 63. Instance: %m", MODULE_NAME, CLK_COR_MIN_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_PRECEDENCE_REG != "TRUE") &&
(CLK_COR_PRECEDENCE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-306] CLK_COR_PRECEDENCE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_COR_PRECEDENCE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-307] CLK_COR_REPEAT_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_USE_REG != "FALSE") &&
(CLK_COR_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-318] CLK_COR_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_LEN_REG != 2) &&
(CLK_COR_SEQ_LEN_REG != 1) &&
(CLK_COR_SEQ_LEN_REG != 3) &&
(CLK_COR_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-319] CLK_COR_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CLK_COR_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_REG != 4) &&
(CPLL_FBDIV_REG != 1) &&
(CPLL_FBDIV_REG != 2) &&
(CPLL_FBDIV_REG != 3) &&
(CPLL_FBDIV_REG != 5) &&
(CPLL_FBDIV_REG != 6) &&
(CPLL_FBDIV_REG != 8) &&
(CPLL_FBDIV_REG != 10) &&
(CPLL_FBDIV_REG != 12) &&
(CPLL_FBDIV_REG != 16) &&
(CPLL_FBDIV_REG != 20))) begin
$display("Error: [Unisim %s-325] CPLL_FBDIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 3, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_FBDIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_45_REG != 4) &&
(CPLL_FBDIV_45_REG != 5))) begin
$display("Error: [Unisim %s-326] CPLL_FBDIV_45 attribute is set to %d. Legal values for this attribute are 4 or 5. Instance: %m", MODULE_NAME, CPLL_FBDIV_45_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_REFCLK_DIV_REG != 1) &&
(CPLL_REFCLK_DIV_REG != 2) &&
(CPLL_REFCLK_DIV_REG != 3) &&
(CPLL_REFCLK_DIV_REG != 4) &&
(CPLL_REFCLK_DIV_REG != 5) &&
(CPLL_REFCLK_DIV_REG != 6) &&
(CPLL_REFCLK_DIV_REG != 8) &&
(CPLL_REFCLK_DIV_REG != 10) &&
(CPLL_REFCLK_DIV_REG != 12) &&
(CPLL_REFCLK_DIV_REG != 16) &&
(CPLL_REFCLK_DIV_REG != 20))) begin
$display("Error: [Unisim %s-329] CPLL_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_REFCLK_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-346] DDI_REALIGN_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, DDI_REALIGN_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_MCOMMA_DETECT_REG != "TRUE") &&
(DEC_MCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-347] DEC_MCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_MCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_PCOMMA_DETECT_REG != "TRUE") &&
(DEC_PCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-348] DEC_PCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_PCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_VALID_COMMA_ONLY_REG != "TRUE") &&
(DEC_VALID_COMMA_ONLY_REG != "FALSE"))) begin
$display("Error: [Unisim %s-349] DEC_VALID_COMMA_ONLY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_ERRDET_EN_REG != "FALSE") &&
(ES_ERRDET_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-355] ES_ERRDET_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_ERRDET_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_EYE_SCAN_EN_REG != "FALSE") &&
(ES_EYE_SCAN_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-356] ES_EYE_SCAN_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_EYE_SCAN_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_LANE_DESKEW_EN_REG != "FALSE") &&
(FTS_LANE_DESKEW_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-392] FTS_LANE_DESKEW_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") &&
(PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_64_BLK"))) begin
$display("Error: [Unisim %s-410] PCI3_AUTO_REALIGN attribute is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK. Instance: %m", MODULE_NAME, PCI3_AUTO_REALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_PCIE_EN_REG != "FALSE") &&
(PCS_PCIE_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-432] PCS_PCIE_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCS_PCIE_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PREIQ_FREQ_BST_REG != 0) &&
(PREIQ_FREQ_BST_REG != 1) &&
(PREIQ_FREQ_BST_REG != 2) &&
(PREIQ_FREQ_BST_REG != 3))) begin
$display("Error: [Unisim %s-437] PREIQ_FREQ_BST attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, PREIQ_FREQ_BST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_ADDR_MODE_REG != "FULL") &&
(RXBUF_ADDR_MODE_REG != "FAST"))) begin
$display("Error: [Unisim %s-446] RXBUF_ADDR_MODE attribute is set to %s. Legal values for this attribute are FULL or FAST. Instance: %m", MODULE_NAME, RXBUF_ADDR_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EN_REG != "TRUE") &&
(RXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-449] RXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-450] RXBUF_RESET_ON_CB_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") &&
(RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-451] RXBUF_RESET_ON_COMMAALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_EIDLE_REG != "FALSE") &&
(RXBUF_RESET_ON_EIDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-452] RXBUF_RESET_ON_EIDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-453] RXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63))) begin
$display("Error: [Unisim %s-454] RXBUF_THRESH_OVFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVRD_REG != "FALSE") &&
(RXBUF_THRESH_OVRD_REG != "TRUE"))) begin
$display("Error: [Unisim %s-455] RXBUF_THRESH_OVRD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63))) begin
$display("Error: [Unisim %s-456] RXBUF_THRESH_UNDFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXELECIDLE_CFG_REG != "SIGCFG_4") &&
(RXELECIDLE_CFG_REG != "SIGCFG_1") &&
(RXELECIDLE_CFG_REG != "SIGCFG_2") &&
(RXELECIDLE_CFG_REG != "SIGCFG_3") &&
(RXELECIDLE_CFG_REG != "SIGCFG_6") &&
(RXELECIDLE_CFG_REG != "SIGCFG_8") &&
(RXELECIDLE_CFG_REG != "SIGCFG_12") &&
(RXELECIDLE_CFG_REG != "SIGCFG_16"))) begin
$display("Error: [Unisim %s-544] RXELECIDLE_CFG attribute is set to %s. Legal values for this attribute are SIGCFG_4, SIGCFG_1, SIGCFG_2, SIGCFG_3, SIGCFG_6, SIGCFG_8, SIGCFG_12 or SIGCFG_16. Instance: %m", MODULE_NAME, RXELECIDLE_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 5))) begin
$display("Error: [Unisim %s-545] RXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3 or 5. Instance: %m", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGEARBOX_EN_REG != "FALSE") &&
(RXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-546] RXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOOB_CLK_CFG_REG != "PMA") &&
(RXOOB_CLK_CFG_REG != "FABRIC"))) begin
$display("Error: [Unisim %s-555] RXOOB_CLK_CFG attribute is set to %s. Legal values for this attribute are PMA or FABRIC. Instance: %m", MODULE_NAME, RXOOB_CLK_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOUT_DIV_REG != 4) &&
(RXOUT_DIV_REG != 1) &&
(RXOUT_DIV_REG != 2) &&
(RXOUT_DIV_REG != 8) &&
(RXOUT_DIV_REG != 16))) begin
$display("Error: [Unisim %s-557] RXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, RXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPMACLK_SEL_REG != "DATA") &&
(RXPMACLK_SEL_REG != "CROSSING") &&
(RXPMACLK_SEL_REG != "EYESCAN"))) begin
$display("Error: [Unisim %s-571] RXPMACLK_SEL attribute is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN. Instance: %m", MODULE_NAME, RXPMACLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255))) begin
$display("Error: [Unisim %s-574] RXPRBS_LINKACQ_CNT attribute is set to %d. Legal values for this attribute are 15 to 255. Instance: %m", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_AUTO_WAIT_REG != 7) &&
(RXSLIDE_AUTO_WAIT_REG != 1) &&
(RXSLIDE_AUTO_WAIT_REG != 2) &&
(RXSLIDE_AUTO_WAIT_REG != 3) &&
(RXSLIDE_AUTO_WAIT_REG != 4) &&
(RXSLIDE_AUTO_WAIT_REG != 5) &&
(RXSLIDE_AUTO_WAIT_REG != 6) &&
(RXSLIDE_AUTO_WAIT_REG != 8) &&
(RXSLIDE_AUTO_WAIT_REG != 9) &&
(RXSLIDE_AUTO_WAIT_REG != 10) &&
(RXSLIDE_AUTO_WAIT_REG != 11) &&
(RXSLIDE_AUTO_WAIT_REG != 12) &&
(RXSLIDE_AUTO_WAIT_REG != 13) &&
(RXSLIDE_AUTO_WAIT_REG != 14) &&
(RXSLIDE_AUTO_WAIT_REG != 15))) begin
$display("Error: [Unisim %s-576] RXSLIDE_AUTO_WAIT attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_MODE_REG != "OFF") &&
(RXSLIDE_MODE_REG != "AUTO") &&
(RXSLIDE_MODE_REG != "PCS") &&
(RXSLIDE_MODE_REG != "PMA"))) begin
$display("Error: [Unisim %s-577] RXSLIDE_MODE attribute is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA. Instance: %m", MODULE_NAME, RXSLIDE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-585] RX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_SEL_REG != 3) &&
(RX_CM_SEL_REG != 0) &&
(RX_CM_SEL_REG != 1) &&
(RX_CM_SEL_REG != 2))) begin
$display("Error: [Unisim %s-590] RX_CM_SEL attribute is set to %d. Legal values for this attribute are 3, 0, 1 or 2. Instance: %m", MODULE_NAME, RX_CM_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_TRIM_REG != 12) &&
(RX_CM_TRIM_REG != 0) &&
(RX_CM_TRIM_REG != 1) &&
(RX_CM_TRIM_REG != 2) &&
(RX_CM_TRIM_REG != 3) &&
(RX_CM_TRIM_REG != 4) &&
(RX_CM_TRIM_REG != 5) &&
(RX_CM_TRIM_REG != 6) &&
(RX_CM_TRIM_REG != 7) &&
(RX_CM_TRIM_REG != 8) &&
(RX_CM_TRIM_REG != 9) &&
(RX_CM_TRIM_REG != 10) &&
(RX_CM_TRIM_REG != 11) &&
(RX_CM_TRIM_REG != 13) &&
(RX_CM_TRIM_REG != 14) &&
(RX_CM_TRIM_REG != 15))) begin
$display("Error: [Unisim %s-591] RX_CM_TRIM attribute is set to %d. Legal values for this attribute are 12, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_CM_TRIM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DATA_WIDTH_REG != 20) &&
(RX_DATA_WIDTH_REG != 16) &&
(RX_DATA_WIDTH_REG != 32) &&
(RX_DATA_WIDTH_REG != 40) &&
(RX_DATA_WIDTH_REG != 64) &&
(RX_DATA_WIDTH_REG != 80) &&
(RX_DATA_WIDTH_REG != 128) &&
(RX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-593] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DEFER_RESET_BUF_EN_REG != "TRUE") &&
(RX_DEFER_RESET_BUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-595] RX_DEFER_RESET_BUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_CFG0_REG != 0) &&
(RX_DFELPM_CFG0_REG != 1) &&
(RX_DFELPM_CFG0_REG != 2) &&
(RX_DFELPM_CFG0_REG != 3) &&
(RX_DFELPM_CFG0_REG != 4) &&
(RX_DFELPM_CFG0_REG != 5) &&
(RX_DFELPM_CFG0_REG != 6) &&
(RX_DFELPM_CFG0_REG != 7) &&
(RX_DFELPM_CFG0_REG != 8) &&
(RX_DFELPM_CFG0_REG != 9) &&
(RX_DFELPM_CFG0_REG != 10) &&
(RX_DFELPM_CFG0_REG != 11) &&
(RX_DFELPM_CFG0_REG != 12) &&
(RX_DFELPM_CFG0_REG != 13) &&
(RX_DFELPM_CFG0_REG != 14) &&
(RX_DFELPM_CFG0_REG != 15))) begin
$display("Error: [Unisim %s-598] RX_DFELPM_CFG0 attribute is set to %d. Legal values for this attribute are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_DFELPM_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_AGC_CFG1_REG != 4) &&
(RX_DFE_AGC_CFG1_REG != 0) &&
(RX_DFE_AGC_CFG1_REG != 1) &&
(RX_DFE_AGC_CFG1_REG != 2) &&
(RX_DFE_AGC_CFG1_REG != 3) &&
(RX_DFE_AGC_CFG1_REG != 5) &&
(RX_DFE_AGC_CFG1_REG != 6) &&
(RX_DFE_AGC_CFG1_REG != 7))) begin
$display("Error: [Unisim %s-602] RX_DFE_AGC_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG0_REG != 1) &&
(RX_DFE_KL_LPM_KH_CFG0_REG != 0) &&
(RX_DFE_KL_LPM_KH_CFG0_REG != 2) &&
(RX_DFE_KL_LPM_KH_CFG0_REG != 3))) begin
$display("Error: [Unisim %s-603] RX_DFE_KL_LPM_KH_CFG0 attribute is set to %d. Legal values for this attribute are 1, 0, 2 or 3. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG1_REG != 4) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 0) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 1) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 2) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 3) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 5) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 6) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 7))) begin
$display("Error: [Unisim %s-604] RX_DFE_KL_LPM_KH_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KL_CFG1_REG != 4) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 0) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 1) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 2) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 3) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 5) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 6) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 7))) begin
$display("Error: [Unisim %s-606] RX_DFE_KL_LPM_KL_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DISPERR_SEQ_MATCH_REG != "TRUE") &&
(RX_DISPERR_SEQ_MATCH_REG != "FALSE"))) begin
$display("Error: [Unisim %s-608] RX_DISPERR_SEQ_MATCH attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_INT_DATAWIDTH_REG != 1) &&
(RX_INT_DATAWIDTH_REG != 0) &&
(RX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-619] RX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, RX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_PROGDIV_CFG_REG != 0.0) &&
(RX_PROGDIV_CFG_REG != 4.0) &&
(RX_PROGDIV_CFG_REG != 5.0) &&
(RX_PROGDIV_CFG_REG != 8.0) &&
(RX_PROGDIV_CFG_REG != 10.0) &&
(RX_PROGDIV_CFG_REG != 16.0) &&
(RX_PROGDIV_CFG_REG != 16.5) &&
(RX_PROGDIV_CFG_REG != 20.0) &&
(RX_PROGDIV_CFG_REG != 32.0) &&
(RX_PROGDIV_CFG_REG != 33.0) &&
(RX_PROGDIV_CFG_REG != 40.0) &&
(RX_PROGDIV_CFG_REG != 64.0) &&
(RX_PROGDIV_CFG_REG != 66.0) &&
(RX_PROGDIV_CFG_REG != 80.0) &&
(RX_PROGDIV_CFG_REG != 100.0) &&
(RX_PROGDIV_CFG_REG != 128.0) &&
(RX_PROGDIV_CFG_REG != 132.0))) begin
$display("Error: [Unisim %s-622] RX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0, 100.0, 128.0 or 132.0. Instance: %m", MODULE_NAME, RX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32))) begin
$display("Error: [Unisim %s-627] RX_SIG_VALID_DLY attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_SIG_VALID_DLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_XCLK_SEL_REG != "RXDES") &&
(RX_XCLK_SEL_REG != "RXPMA") &&
(RX_XCLK_SEL_REG != "RXUSR"))) begin
$display("Error: [Unisim %s-640] RX_XCLK_SEL attribute is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR. Instance: %m", MODULE_NAME, RX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_CPLL_CFG_REG != "VCO_3000MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_750MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_1500MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_6000MHZ"))) begin
$display("Error: [Unisim %s-646] SATA_CPLL_CFG attribute is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, VCO_1500MHZ or VCO_6000MHZ. Instance: %m", MODULE_NAME, SATA_CPLL_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SHOW_REALIGN_COMMA_REG != "TRUE") &&
(SHOW_REALIGN_COMMA_REG != "FALSE"))) begin
$display("Error: [Unisim %s-648] SHOW_REALIGN_COMMA attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SHOW_REALIGN_COMMA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1p") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-649] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES1p or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_MODE_REG != "FAST") &&
(SIM_MODE_REG != "LEGACY"))) begin
$display("Error: [Unisim %s-650] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST or LEGACY. Instance: %m", MODULE_NAME, SIM_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") &&
(SIM_RECEIVER_DETECT_PASS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-651] SIM_RECEIVER_DETECT_PASS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RESET_SPEEDUP_REG != "TRUE") &&
(SIM_RESET_SPEEDUP_REG != "FALSE"))) begin
$display("Error: [Unisim %s-652] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_TX_EIDLE_DRIVE_LEVEL_REG != "Z") &&
(SIM_TX_EIDLE_DRIVE_LEVEL_REG != "HIGH") &&
(SIM_TX_EIDLE_DRIVE_LEVEL_REG != "LOW") &&
(SIM_TX_EIDLE_DRIVE_LEVEL_REG != "X"))) begin
$display("Error: [Unisim %s-653] SIM_TX_EIDLE_DRIVE_LEVEL attribute is set to %s. Legal values for this attribute are Z, HIGH, LOW or X. Instance: %m", MODULE_NAME, SIM_TX_EIDLE_DRIVE_LEVEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_EN_REG != "TRUE") &&
(TXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-662] TXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") &&
(TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-663] TXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXFIFO_ADDR_CFG_REG != "LOW") &&
(TXFIFO_ADDR_CFG_REG != "HIGH"))) begin
$display("Error: [Unisim %s-667] TXFIFO_ADDR_CFG attribute is set to %s. Legal values for this attribute are LOW or HIGH. Instance: %m", MODULE_NAME, TXFIFO_ADDR_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 6))) begin
$display("Error: [Unisim %s-668] TXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3, 5 or 6. Instance: %m", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGEARBOX_EN_REG != "FALSE") &&
(TXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-669] TXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXOUT_DIV_REG != 4) &&
(TXOUT_DIV_REG != 1) &&
(TXOUT_DIV_REG != 2) &&
(TXOUT_DIV_REG != 8) &&
(TXOUT_DIV_REG != 16))) begin
$display("Error: [Unisim %s-671] TXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8 or 16. Instance: %m", MODULE_NAME, TXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_PPMCLK_SEL_REG != "TXUSRCLK2") &&
(TXPI_PPMCLK_SEL_REG != "TXUSRCLK"))) begin
$display("Error: [Unisim %s-689] TXPI_PPMCLK_SEL attribute is set to %s. Legal values for this attribute are TXUSRCLK2 or TXUSRCLK. Instance: %m", MODULE_NAME, TXPI_PPMCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-698] TX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, TX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DATA_WIDTH_REG != 20) &&
(TX_DATA_WIDTH_REG != 16) &&
(TX_DATA_WIDTH_REG != 32) &&
(TX_DATA_WIDTH_REG != 40) &&
(TX_DATA_WIDTH_REG != 64) &&
(TX_DATA_WIDTH_REG != 80) &&
(TX_DATA_WIDTH_REG != 128) &&
(TX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-700] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DRIVE_MODE_REG != "DIRECT") &&
(TX_DRIVE_MODE_REG != "PIPE") &&
(TX_DRIVE_MODE_REG != "PIPEGEN3"))) begin
$display("Error: [Unisim %s-707] TX_DRIVE_MODE attribute is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3. Instance: %m", MODULE_NAME, TX_DRIVE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DRVMUX_CTRL_REG != 2) &&
(TX_DRVMUX_CTRL_REG != 0) &&
(TX_DRVMUX_CTRL_REG != 1) &&
(TX_DRVMUX_CTRL_REG != 3))) begin
$display("Error: [Unisim %s-708] TX_DRVMUX_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, TX_DRVMUX_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_INT_DATAWIDTH_REG != 1) &&
(TX_INT_DATAWIDTH_REG != 0) &&
(TX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-714] TX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, TX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") &&
(TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE"))) begin
$display("Error: [Unisim %s-715] TX_LOOPBACK_DRIVE_HIZ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PI_BIASSET_REG != 0) &&
(TX_PI_BIASSET_REG != 1) &&
(TX_PI_BIASSET_REG != 2) &&
(TX_PI_BIASSET_REG != 3))) begin
$display("Error: [Unisim %s-730] TX_PI_BIASSET attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, TX_PI_BIASSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PREDRV_CTRL_REG != 2) &&
(TX_PREDRV_CTRL_REG != 0) &&
(TX_PREDRV_CTRL_REG != 1) &&
(TX_PREDRV_CTRL_REG != 3))) begin
$display("Error: [Unisim %s-735] TX_PREDRV_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, TX_PREDRV_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGCLK_SEL_REG != "POSTPI") &&
(TX_PROGCLK_SEL_REG != "CPLL") &&
(TX_PROGCLK_SEL_REG != "PREPI"))) begin
$display("Error: [Unisim %s-736] TX_PROGCLK_SEL attribute is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI. Instance: %m", MODULE_NAME, TX_PROGCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGDIV_CFG_REG != 0.0) &&
(TX_PROGDIV_CFG_REG != 4.0) &&
(TX_PROGDIV_CFG_REG != 5.0) &&
(TX_PROGDIV_CFG_REG != 8.0) &&
(TX_PROGDIV_CFG_REG != 10.0) &&
(TX_PROGDIV_CFG_REG != 16.0) &&
(TX_PROGDIV_CFG_REG != 16.5) &&
(TX_PROGDIV_CFG_REG != 20.0) &&
(TX_PROGDIV_CFG_REG != 32.0) &&
(TX_PROGDIV_CFG_REG != 33.0) &&
(TX_PROGDIV_CFG_REG != 40.0) &&
(TX_PROGDIV_CFG_REG != 64.0) &&
(TX_PROGDIV_CFG_REG != 66.0) &&
(TX_PROGDIV_CFG_REG != 80.0) &&
(TX_PROGDIV_CFG_REG != 100.0) &&
(TX_PROGDIV_CFG_REG != 128.0) &&
(TX_PROGDIV_CFG_REG != 132.0))) begin
$display("Error: [Unisim %s-737] TX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0, 100.0, 128.0 or 132.0. Instance: %m", MODULE_NAME, TX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_RXDETECT_REF_REG != 3) &&
(TX_RXDETECT_REF_REG != 0) &&
(TX_RXDETECT_REF_REG != 1) &&
(TX_RXDETECT_REF_REG != 2) &&
(TX_RXDETECT_REF_REG != 4) &&
(TX_RXDETECT_REF_REG != 5) &&
(TX_RXDETECT_REF_REG != 6) &&
(TX_RXDETECT_REF_REG != 7))) begin
$display("Error: [Unisim %s-741] TX_RXDETECT_REF attribute is set to %d. Legal values for this attribute are 3, 0, 1, 2, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, TX_RXDETECT_REF_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_XCLK_SEL_REG != "TXOUT") &&
(TX_XCLK_SEL_REG != "TXUSR"))) begin
$display("Error: [Unisim %s-756] TX_XCLK_SEL attribute is set to %s. Legal values for this attribute are TXOUT or TXUSR. Instance: %m", MODULE_NAME, TX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_PING_SATA_MAX_INIT_REG < 1) || (USB_PING_SATA_MAX_INIT_REG > 63))) begin
$display("Error: [Unisim %s-774] USB_PING_SATA_MAX_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_PING_SATA_MAX_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_PING_SATA_MIN_INIT_REG < 1) || (USB_PING_SATA_MIN_INIT_REG > 63))) begin
$display("Error: [Unisim %s-775] USB_PING_SATA_MIN_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_PING_SATA_MIN_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_POLL_SATA_MAX_BURST_REG < 1) || (USB_POLL_SATA_MAX_BURST_REG > 63))) begin
$display("Error: [Unisim %s-776] USB_POLL_SATA_MAX_BURST attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_POLL_SATA_MAX_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_POLL_SATA_MIN_BURST_REG < 1) || (USB_POLL_SATA_MIN_BURST_REG > 61))) begin
$display("Error: [Unisim %s-777] USB_POLL_SATA_MIN_BURST attribute is set to %d. Legal values for this attribute are 1 to 61. Instance: %m", MODULE_NAME, USB_POLL_SATA_MIN_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_U1_SATA_MAX_WAKE_REG < 1) || (USB_U1_SATA_MAX_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-781] USB_U1_SATA_MAX_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U1_SATA_MAX_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_U1_SATA_MIN_WAKE_REG < 1) || (USB_U1_SATA_MIN_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-782] USB_U1_SATA_MIN_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U1_SATA_MIN_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_U2_SAS_MAX_COM_REG < 1) || (USB_U2_SAS_MAX_COM_REG > 127))) begin
$display("Error: [Unisim %s-783] USB_U2_SAS_MAX_COM attribute is set to %d. Legal values for this attribute are 1 to 127. Instance: %m", MODULE_NAME, USB_U2_SAS_MAX_COM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_U2_SAS_MIN_COM_REG < 1) || (USB_U2_SAS_MIN_COM_REG > 63))) begin
$display("Error: [Unisim %s-784] USB_U2_SAS_MIN_COM attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U2_SAS_MIN_COM_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
assign PMASCANCLK0_in = 1'b1; // tie off
assign PMASCANCLK1_in = 1'b1; // tie off
assign PMASCANCLK2_in = 1'b1; // tie off
assign PMASCANCLK3_in = 1'b1; // tie off
assign PMASCANCLK4_in = 1'b1; // tie off
assign PMASCANCLK5_in = 1'b1; // tie off
assign PMASCANCLK6_in = 1'b1; // tie off
assign PMASCANCLK7_in = 1'b1; // tie off
assign PMASCANCLK8_in = 1'b1; // tie off
assign SCANCLK_in = 1'b1; // tie off
assign TSTCLK0_in = 1'b1; // tie off
assign TSTCLK1_in = 1'b1; // tie off
assign BSR_SERIAL_in = 1'b1; // tie off
assign CSSDRSTB_in = 1'b1; // tie off
assign CSSDSTOPCLK_in = 1'b1; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 18'b111111111111111111; // tie off
assign PMASCANMODEB_in = 1'b1; // tie off
assign PMASCANRSTEN_in = 1'b1; // tie off
assign SARCCLK_in = 1'b1; // tie off
assign SCANENB_in = 1'b1; // tie off
assign SCANIN_in = 19'b1111111111111111111; // tie off
assign SCANMODEB_in = 1'b1; // tie off
assign SCANRSTB_in = 1'b1; // tie off
assign SCANRSTEN_in = 1'b1; // tie off
assign TSTPDOVRDB_in = 1'b1; // tie off
assign TSTPD_in = 5'b11111; // tie off
SIP_GTHE4_CHANNEL SIP_GTHE4_CHANNEL_INST (
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG),
.ACJTAG_MODE (ACJTAG_MODE_REG),
.ACJTAG_RESET (ACJTAG_RESET_REG),
.ADAPT_CFG0 (ADAPT_CFG0_REG),
.ADAPT_CFG1 (ADAPT_CFG1_REG),
.ADAPT_CFG2 (ADAPT_CFG2_REG),
.AEN_CDRSTEPSEL (AEN_CDRSTEPSEL_REG),
.AEN_CPLL (AEN_CPLL_REG),
.AEN_LOOPBACK (AEN_LOOPBACK_REG),
.AEN_MASTER (AEN_MASTER_REG),
.AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG),
.AEN_POLARITY (AEN_POLARITY_REG),
.AEN_PRBS (AEN_PRBS_REG),
.AEN_QPI (AEN_QPI_REG),
.AEN_RESET (AEN_RESET_REG),
.AEN_RXCDR (AEN_RXCDR_REG),
.AEN_RXDFE (AEN_RXDFE_REG),
.AEN_RXDFELPM (AEN_RXDFELPM_REG),
.AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG),
.AEN_RXPHDLY (AEN_RXPHDLY_REG),
.AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG),
.AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG),
.AEN_TXMUXDCD (AEN_TXMUXDCD_REG),
.AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG),
.AEN_TXPHDLY (AEN_TXPHDLY_REG),
.AEN_TXPI_PPM (AEN_TXPI_PPM_REG),
.AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG),
.AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG),
.AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG),
.AMONITOR_CFG (AMONITOR_CFG_REG),
.A_CPLLLOCKEN (A_CPLLLOCKEN_REG),
.A_CPLLPD (A_CPLLPD_REG),
.A_CPLLRESET (A_CPLLRESET_REG),
.A_EYESCANRESET (A_EYESCANRESET_REG),
.A_GTRESETSEL (A_GTRESETSEL_REG),
.A_GTRXRESET (A_GTRXRESET_REG),
.A_GTTXRESET (A_GTTXRESET_REG),
.A_LOOPBACK (A_LOOPBACK_REG),
.A_RXAFECFOKEN (A_RXAFECFOKEN_REG),
.A_RXBUFRESET (A_RXBUFRESET_REG),
.A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG),
.A_RXCDRHOLD (A_RXCDRHOLD_REG),
.A_RXCDROVRDEN (A_RXCDROVRDEN_REG),
.A_RXCDRRESET (A_RXCDRRESET_REG),
.A_RXCKCALRESET (A_RXCKCALRESET_REG),
.A_RXDFEAGCCTRL (A_RXDFEAGCCTRL_REG),
.A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG),
.A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG),
.A_RXDFECFOKFCNUM (A_RXDFECFOKFCNUM_REG),
.A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG),
.A_RXDFECFOKFPULSE (A_RXDFECFOKFPULSE_REG),
.A_RXDFECFOKHOLD (A_RXDFECFOKHOLD_REG),
.A_RXDFECFOKOVREN (A_RXDFECFOKOVREN_REG),
.A_RXDFEKHHOLD (A_RXDFEKHHOLD_REG),
.A_RXDFEKHOVRDEN (A_RXDFEKHOVRDEN_REG),
.A_RXDFELFHOLD (A_RXDFELFHOLD_REG),
.A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG),
.A_RXDFELPMRESET (A_RXDFELPMRESET_REG),
.A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG),
.A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG),
.A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG),
.A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG),
.A_RXDFETAP12HOLD (A_RXDFETAP12HOLD_REG),
.A_RXDFETAP12OVRDEN (A_RXDFETAP12OVRDEN_REG),
.A_RXDFETAP13HOLD (A_RXDFETAP13HOLD_REG),
.A_RXDFETAP13OVRDEN (A_RXDFETAP13OVRDEN_REG),
.A_RXDFETAP14HOLD (A_RXDFETAP14HOLD_REG),
.A_RXDFETAP14OVRDEN (A_RXDFETAP14OVRDEN_REG),
.A_RXDFETAP15HOLD (A_RXDFETAP15HOLD_REG),
.A_RXDFETAP15OVRDEN (A_RXDFETAP15OVRDEN_REG),
.A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG),
.A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG),
.A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG),
.A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG),
.A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG),
.A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG),
.A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG),
.A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG),
.A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG),
.A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG),
.A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG),
.A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG),
.A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG),
.A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG),
.A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG),
.A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG),
.A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG),
.A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG),
.A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG),
.A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG),
.A_RXDFEXYDEN (A_RXDFEXYDEN_REG),
.A_RXDLYBYPASS (A_RXDLYBYPASS_REG),
.A_RXDLYEN (A_RXDLYEN_REG),
.A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG),
.A_RXDLYSRESET (A_RXDLYSRESET_REG),
.A_RXLPMEN (A_RXLPMEN_REG),
.A_RXLPMGCHOLD (A_RXLPMGCHOLD_REG),
.A_RXLPMGCOVRDEN (A_RXLPMGCOVRDEN_REG),
.A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG),
.A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG),
.A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG),
.A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG),
.A_RXLPMOSHOLD (A_RXLPMOSHOLD_REG),
.A_RXLPMOSOVRDEN (A_RXLPMOSOVRDEN_REG),
.A_RXMONITORSEL (A_RXMONITORSEL_REG),
.A_RXOOBRESET (A_RXOOBRESET_REG),
.A_RXOSCALRESET (A_RXOSCALRESET_REG),
.A_RXOSHOLD (A_RXOSHOLD_REG),
.A_RXOSOVRDEN (A_RXOSOVRDEN_REG),
.A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG),
.A_RXPCSRESET (A_RXPCSRESET_REG),
.A_RXPD (A_RXPD_REG),
.A_RXPHALIGN (A_RXPHALIGN_REG),
.A_RXPHALIGNEN (A_RXPHALIGNEN_REG),
.A_RXPHDLYPD (A_RXPHDLYPD_REG),
.A_RXPHDLYRESET (A_RXPHDLYRESET_REG),
.A_RXPHOVRDEN (A_RXPHOVRDEN_REG),
.A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG),
.A_RXPMARESET (A_RXPMARESET_REG),
.A_RXPOLARITY (A_RXPOLARITY_REG),
.A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG),
.A_RXPRBSSEL (A_RXPRBSSEL_REG),
.A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG),
.A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG),
.A_RXTERMINATION (A_RXTERMINATION_REG),
.A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG),
.A_TXDCCRESET (A_TXDCCRESET_REG),
.A_TXDEEMPH (A_TXDEEMPH_REG),
.A_TXDIFFCTRL (A_TXDIFFCTRL_REG),
.A_TXDLYBYPASS (A_TXDLYBYPASS_REG),
.A_TXDLYEN (A_TXDLYEN_REG),
.A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG),
.A_TXDLYSRESET (A_TXDLYSRESET_REG),
.A_TXELECIDLE (A_TXELECIDLE_REG),
.A_TXINHIBIT (A_TXINHIBIT_REG),
.A_TXMAINCURSOR (A_TXMAINCURSOR_REG),
.A_TXMARGIN (A_TXMARGIN_REG),
.A_TXMUXDCDEXHOLD (A_TXMUXDCDEXHOLD_REG),
.A_TXMUXDCDORWREN (A_TXMUXDCDORWREN_REG),
.A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG),
.A_TXPCSRESET (A_TXPCSRESET_REG),
.A_TXPD (A_TXPD_REG),
.A_TXPHALIGN (A_TXPHALIGN_REG),
.A_TXPHALIGNEN (A_TXPHALIGNEN_REG),
.A_TXPHDLYPD (A_TXPHDLYPD_REG),
.A_TXPHDLYRESET (A_TXPHDLYRESET_REG),
.A_TXPHINIT (A_TXPHINIT_REG),
.A_TXPHOVRDEN (A_TXPHOVRDEN_REG),
.A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG),
.A_TXPIPPMPD (A_TXPIPPMPD_REG),
.A_TXPIPPMSEL (A_TXPIPPMSEL_REG),
.A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG),
.A_TXPMARESET (A_TXPMARESET_REG),
.A_TXPOLARITY (A_TXPOLARITY_REG),
.A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG),
.A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG),
.A_TXPRBSSEL (A_TXPRBSSEL_REG),
.A_TXPRECURSOR (A_TXPRECURSOR_REG),
.A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG),
.A_TXQPIBIASEN (A_TXQPIBIASEN_REG),
.A_TXRESETSEL (A_TXRESETSEL_REG),
.A_TXSWING (A_TXSWING_REG),
.A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG),
.BSR_ENABLE (BSR_ENABLE_REG),
.CAPBYPASS_FORCE (CAPBYPASS_FORCE_REG),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG),
.CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG),
.CFOK_PWRSVE_EN (CFOK_PWRSVE_EN_REG),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG),
.CH_HSPMUX (CH_HSPMUX_REG),
.CKCAL1_CFG_0 (CKCAL1_CFG_0_REG),
.CKCAL1_CFG_1 (CKCAL1_CFG_1_REG),
.CKCAL1_CFG_2 (CKCAL1_CFG_2_REG),
.CKCAL1_CFG_3 (CKCAL1_CFG_3_REG),
.CKCAL2_CFG_0 (CKCAL2_CFG_0_REG),
.CKCAL2_CFG_1 (CKCAL2_CFG_1_REG),
.CKCAL2_CFG_2 (CKCAL2_CFG_2_REG),
.CKCAL2_CFG_3 (CKCAL2_CFG_3_REG),
.CKCAL2_CFG_4 (CKCAL2_CFG_4_REG),
.CKCAL_RSVD0 (CKCAL_RSVD0_REG),
.CKCAL_RSVD1 (CKCAL_RSVD1_REG),
.CLK_CORRECT_USE (CLK_CORRECT_USE_REG),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG),
.COEREG_CLKCTRL (COEREG_CLKCTRL_REG),
.CPLL_CFG0 (CPLL_CFG0_REG),
.CPLL_CFG1 (CPLL_CFG1_REG),
.CPLL_CFG2 (CPLL_CFG2_REG),
.CPLL_CFG3 (CPLL_CFG3_REG),
.CPLL_FBDIV (CPLL_FBDIV_REG),
.CPLL_FBDIV_45 (CPLL_FBDIV_45_REG),
.CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG),
.CSSD_CLK_MASK0 (CSSD_CLK_MASK0_REG),
.CSSD_CLK_MASK1 (CSSD_CLK_MASK1_REG),
.CSSD_REG0 (CSSD_REG0_REG),
.CSSD_REG1 (CSSD_REG1_REG),
.CSSD_REG10 (CSSD_REG10_REG),
.CSSD_REG2 (CSSD_REG2_REG),
.CSSD_REG3 (CSSD_REG3_REG),
.CSSD_REG4 (CSSD_REG4_REG),
.CSSD_REG5 (CSSD_REG5_REG),
.CSSD_REG6 (CSSD_REG6_REG),
.CSSD_REG7 (CSSD_REG7_REG),
.CSSD_REG8 (CSSD_REG8_REG),
.CSSD_REG9 (CSSD_REG9_REG),
.CTLE3_OCAP_EXT_CTRL (CTLE3_OCAP_EXT_CTRL_REG),
.CTLE3_OCAP_EXT_EN (CTLE3_OCAP_EXT_EN_REG),
.DDI_CTRL (DDI_CTRL_REG),
.DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG),
.DELAY_ELEC (DELAY_ELEC_REG),
.DMONITOR_CFG0 (DMONITOR_CFG0_REG),
.DMONITOR_CFG1 (DMONITOR_CFG1_REG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG),
.ES_CONTROL (ES_CONTROL_REG),
.ES_ERRDET_EN (ES_ERRDET_EN_REG),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG),
.ES_PRESCALE (ES_PRESCALE_REG),
.ES_QUALIFIER0 (ES_QUALIFIER0_REG),
.ES_QUALIFIER1 (ES_QUALIFIER1_REG),
.ES_QUALIFIER2 (ES_QUALIFIER2_REG),
.ES_QUALIFIER3 (ES_QUALIFIER3_REG),
.ES_QUALIFIER4 (ES_QUALIFIER4_REG),
.ES_QUALIFIER5 (ES_QUALIFIER5_REG),
.ES_QUALIFIER6 (ES_QUALIFIER6_REG),
.ES_QUALIFIER7 (ES_QUALIFIER7_REG),
.ES_QUALIFIER8 (ES_QUALIFIER8_REG),
.ES_QUALIFIER9 (ES_QUALIFIER9_REG),
.ES_QUAL_MASK0 (ES_QUAL_MASK0_REG),
.ES_QUAL_MASK1 (ES_QUAL_MASK1_REG),
.ES_QUAL_MASK2 (ES_QUAL_MASK2_REG),
.ES_QUAL_MASK3 (ES_QUAL_MASK3_REG),
.ES_QUAL_MASK4 (ES_QUAL_MASK4_REG),
.ES_QUAL_MASK5 (ES_QUAL_MASK5_REG),
.ES_QUAL_MASK6 (ES_QUAL_MASK6_REG),
.ES_QUAL_MASK7 (ES_QUAL_MASK7_REG),
.ES_QUAL_MASK8 (ES_QUAL_MASK8_REG),
.ES_QUAL_MASK9 (ES_QUAL_MASK9_REG),
.ES_SDATA_MASK0 (ES_SDATA_MASK0_REG),
.ES_SDATA_MASK1 (ES_SDATA_MASK1_REG),
.ES_SDATA_MASK2 (ES_SDATA_MASK2_REG),
.ES_SDATA_MASK3 (ES_SDATA_MASK3_REG),
.ES_SDATA_MASK4 (ES_SDATA_MASK4_REG),
.ES_SDATA_MASK5 (ES_SDATA_MASK5_REG),
.ES_SDATA_MASK6 (ES_SDATA_MASK6_REG),
.ES_SDATA_MASK7 (ES_SDATA_MASK7_REG),
.ES_SDATA_MASK8 (ES_SDATA_MASK8_REG),
.ES_SDATA_MASK9 (ES_SDATA_MASK9_REG),
.EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG),
.GEARBOX_MODE (GEARBOX_MODE_REG),
.GEN_RXUSRCLK (GEN_RXUSRCLK_REG),
.GEN_TXUSRCLK (GEN_TXUSRCLK_REG),
.GT_INSTANTIATED (GT_INSTANTIATED_REG),
.INT_MASK_CFG0 (INT_MASK_CFG0_REG),
.INT_MASK_CFG1 (INT_MASK_CFG1_REG),
.ISCAN_CK_PH_SEL2 (ISCAN_CK_PH_SEL2_REG),
.LOCAL_MASTER (LOCAL_MASTER_REG),
.LPBK_BIAS_CTRL (LPBK_BIAS_CTRL_REG),
.LPBK_EN_RCAL_B (LPBK_EN_RCAL_B_REG),
.LPBK_EXT_RCAL (LPBK_EXT_RCAL_REG),
.LPBK_IND_CTRL0 (LPBK_IND_CTRL0_REG),
.LPBK_IND_CTRL1 (LPBK_IND_CTRL1_REG),
.LPBK_IND_CTRL2 (LPBK_IND_CTRL2_REG),
.LPBK_RG_CTRL (LPBK_RG_CTRL_REG),
.OOBDIVCTL (OOBDIVCTL_REG),
.OOB_PWRUP (OOB_PWRUP_REG),
.PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG),
.PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG),
.PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG),
.PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG),
.PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG),
.PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG),
.PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG),
.PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG),
.PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG),
.PCIE3_CLK_COR_EMPTY_THRSH (PCIE3_CLK_COR_EMPTY_THRSH_REG),
.PCIE3_CLK_COR_FULL_THRSH (PCIE3_CLK_COR_FULL_THRSH_REG),
.PCIE3_CLK_COR_MAX_LAT (PCIE3_CLK_COR_MAX_LAT_REG),
.PCIE3_CLK_COR_MIN_LAT (PCIE3_CLK_COR_MIN_LAT_REG),
.PCIE3_CLK_COR_THRSH_TIMER (PCIE3_CLK_COR_THRSH_TIMER_REG),
.PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG),
.PCIE_PLL_SEL_MODE_GEN12 (PCIE_PLL_SEL_MODE_GEN12_REG),
.PCIE_PLL_SEL_MODE_GEN3 (PCIE_PLL_SEL_MODE_GEN3_REG),
.PCIE_PLL_SEL_MODE_GEN4 (PCIE_PLL_SEL_MODE_GEN4_REG),
.PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG),
.PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG),
.PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG),
.PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG),
.PCS_PCIE_EN (PCS_PCIE_EN_REG),
.PCS_RSVD0 (PCS_RSVD0_REG),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST_REG),
.PROCESS_PAR (PROCESS_PAR_REG),
.RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG),
.RCLK_SIPO_DLY_ENB (RCLK_SIPO_DLY_ENB_REG),
.RCLK_SIPO_INV_EN (RCLK_SIPO_INV_EN_REG),
.RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE_REG),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL_REG),
.RTX_BUF_TERM_CTRL (RTX_BUF_TERM_CTRL_REG),
.RXBUFRESET_TIME (RXBUFRESET_TIME_REG),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG),
.RXBUF_EN (RXBUF_EN_REG),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG),
.RXCDR_CFG0 (RXCDR_CFG0_REG),
.RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG),
.RXCDR_CFG1 (RXCDR_CFG1_REG),
.RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG),
.RXCDR_CFG2 (RXCDR_CFG2_REG),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2_REG),
.RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4_REG),
.RXCDR_CFG3 (RXCDR_CFG3_REG),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2_REG),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4_REG),
.RXCDR_CFG4 (RXCDR_CFG4_REG),
.RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG),
.RXCDR_CFG5 (RXCDR_CFG5_REG),
.RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG),
.RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG),
.RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG),
.RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG),
.RXCDR_LOCK_CFG3 (RXCDR_LOCK_CFG3_REG),
.RXCDR_LOCK_CFG4 (RXCDR_LOCK_CFG4_REG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG),
.RXCFOK_CFG0 (RXCFOK_CFG0_REG),
.RXCFOK_CFG1 (RXCFOK_CFG1_REG),
.RXCFOK_CFG2 (RXCFOK_CFG2_REG),
.RXCKCAL1_IQ_LOOP_RST_CFG (RXCKCAL1_IQ_LOOP_RST_CFG_REG),
.RXCKCAL1_I_LOOP_RST_CFG (RXCKCAL1_I_LOOP_RST_CFG_REG),
.RXCKCAL1_Q_LOOP_RST_CFG (RXCKCAL1_Q_LOOP_RST_CFG_REG),
.RXCKCAL2_DX_LOOP_RST_CFG (RXCKCAL2_DX_LOOP_RST_CFG_REG),
.RXCKCAL2_D_LOOP_RST_CFG (RXCKCAL2_D_LOOP_RST_CFG_REG),
.RXCKCAL2_S_LOOP_RST_CFG (RXCKCAL2_S_LOOP_RST_CFG_REG),
.RXCKCAL2_X_LOOP_RST_CFG (RXCKCAL2_X_LOOP_RST_CFG_REG),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG),
.RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG),
.RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG),
.RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG),
.RXDFE_CFG0 (RXDFE_CFG0_REG),
.RXDFE_CFG1 (RXDFE_CFG1_REG),
.RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG),
.RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG),
.RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG),
.RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG),
.RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG),
.RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG),
.RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG),
.RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG),
.RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG),
.RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG),
.RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG),
.RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG),
.RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG),
.RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG),
.RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG),
.RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG),
.RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG),
.RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG),
.RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG),
.RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG),
.RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG),
.RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG),
.RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG),
.RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG),
.RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG),
.RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG),
.RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG),
.RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG),
.RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG),
.RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG),
.RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG),
.RXDFE_KH_CFG0 (RXDFE_KH_CFG0_REG),
.RXDFE_KH_CFG1 (RXDFE_KH_CFG1_REG),
.RXDFE_KH_CFG2 (RXDFE_KH_CFG2_REG),
.RXDFE_KH_CFG3 (RXDFE_KH_CFG3_REG),
.RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG),
.RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG),
.RXDFE_PWR_SAVING (RXDFE_PWR_SAVING_REG),
.RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG),
.RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG),
.RXDFE_UT_CFG2 (RXDFE_UT_CFG2_REG),
.RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG),
.RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG),
.RXDLY_CFG (RXDLY_CFG_REG),
.RXDLY_LCFG (RXDLY_LCFG_REG),
.RXELECIDLE_CFG (RXELECIDLE_CFG_REG),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG),
.RXGEARBOX_EN (RXGEARBOX_EN_REG),
.RXISCANRESET_TIME (RXISCANRESET_TIME_REG),
.RXLPM_CFG (RXLPM_CFG_REG),
.RXLPM_GC_CFG (RXLPM_GC_CFG_REG),
.RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG),
.RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG),
.RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG),
.RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG),
.RXOOB_CFG (RXOOB_CFG_REG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG),
.RXOUT_DIV (RXOUT_DIV_REG),
.RXPCSRESET_TIME (RXPCSRESET_TIME_REG),
.RXPHBEACON_CFG (RXPHBEACON_CFG_REG),
.RXPHDLY_CFG (RXPHDLY_CFG_REG),
.RXPHSAMP_CFG (RXPHSAMP_CFG_REG),
.RXPHSLIP_CFG (RXPHSLIP_CFG_REG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG),
.RXPI_AUTO_BW_SEL_BYPASS (RXPI_AUTO_BW_SEL_BYPASS_REG),
.RXPI_CFG0 (RXPI_CFG0_REG),
.RXPI_CFG1 (RXPI_CFG1_REG),
.RXPI_LPM (RXPI_LPM_REG),
.RXPI_SEL_LC (RXPI_SEL_LC_REG),
.RXPI_STARTCODE (RXPI_STARTCODE_REG),
.RXPI_VREFSEL (RXPI_VREFSEL_REG),
.RXPMACLK_SEL (RXPMACLK_SEL_REG),
.RXPMARESET_TIME (RXPMARESET_TIME_REG),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG),
.RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG),
.RXREFCLKDIV2_SEL (RXREFCLKDIV2_SEL_REG),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG),
.RXSLIDE_MODE (RXSLIDE_MODE_REG),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG),
.RXSYNC_OVRD (RXSYNC_OVRD_REG),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG),
.RX_AFE_CM_EN (RX_AFE_CM_EN_REG),
.RX_BIAS_CFG0 (RX_BIAS_CFG0_REG),
.RX_BUFFER_CFG (RX_BUFFER_CFG_REG),
.RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG),
.RX_CLK25_DIV (RX_CLK25_DIV_REG),
.RX_CLKMUX_EN (RX_CLKMUX_EN_REG),
.RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG),
.RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG),
.RX_CM_BUF_PD (RX_CM_BUF_PD_REG),
.RX_CM_SEL (RX_CM_SEL_REG),
.RX_CM_TRIM (RX_CM_TRIM_REG),
.RX_CTLE3_LPF (RX_CTLE3_LPF_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DDI_SEL (RX_DDI_SEL_REG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG),
.RX_DEGEN_CTRL (RX_DEGEN_CTRL_REG),
.RX_DFECFOKFCDAC (RX_DFECFOKFCDAC_REG),
.RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG),
.RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG),
.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG),
.RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0_REG),
.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG),
.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG),
.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG),
.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG),
.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG),
.RX_DIV2_MODE_B (RX_DIV2_MODE_B_REG),
.RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG),
.RX_EN_CTLE_RCAL_B (RX_EN_CTLE_RCAL_B_REG),
.RX_EN_HI_LR (RX_EN_HI_LR_REG),
.RX_EXT_RL_CTRL (RX_EXT_RL_CTRL_REG),
.RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG),
.RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG),
.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG),
.RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG),
.RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG),
.RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG),
.RX_PMA_RSV0 (RX_PMA_RSV0_REG),
.RX_PROGDIV_CFG (RX_PROGDIV_CFG_BIN),
.RX_PROGDIV_RATE (RX_PROGDIV_RATE_REG),
.RX_RESLOAD_CTRL (RX_RESLOAD_CTRL_REG),
.RX_RESLOAD_OVRD (RX_RESLOAD_OVRD_REG),
.RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG),
.RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG),
.RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG),
.RX_SUM_RESLOAD_CTRL (RX_SUM_RESLOAD_CTRL_REG),
.RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG),
.RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG),
.RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG),
.RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG),
.RX_VREG_CTRL (RX_VREG_CTRL_REG),
.RX_VREG_PDB (RX_VREG_PDB_REG),
.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG),
.RX_WIDEMODE_CDR_GEN3 (RX_WIDEMODE_CDR_GEN3_REG),
.RX_WIDEMODE_CDR_GEN4 (RX_WIDEMODE_CDR_GEN4_REG),
.RX_XCLK_SEL (RX_XCLK_SEL_REG),
.RX_XMODE_SEL (RX_XMODE_SEL_REG),
.SAMPLE_CLK_PHASE (SAMPLE_CLK_PHASE_REG),
.SAS_12G_MODE (SAS_12G_MODE_REG),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG),
.SATA_BURST_VAL (SATA_BURST_VAL_REG),
.SATA_CPLL_CFG (SATA_CPLL_CFG_REG),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG),
.SIM_DEVICE (SIM_DEVICE_REG),
.SIM_MODE (SIM_MODE_REG),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS_REG),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL_REG),
.SRSTMODE (SRSTMODE_REG),
.TAPDLY_SET_TX (TAPDLY_SET_TX_REG),
.TEMPERATURE_PAR (TEMPERATURE_PAR_REG),
.TERM_RCAL_CFG (TERM_RCAL_CFG_REG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG),
.TRANS_TIME_RATE (TRANS_TIME_RATE_REG),
.TST_RSV0 (TST_RSV0_REG),
.TST_RSV1 (TST_RSV1_REG),
.TXBUF_EN (TXBUF_EN_REG),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG),
.TXDLY_CFG (TXDLY_CFG_REG),
.TXDLY_LCFG (TXDLY_LCFG_REG),
.TXDRVBIAS_N (TXDRVBIAS_N_REG),
.TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG),
.TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG),
.TXGEARBOX_EN (TXGEARBOX_EN_REG),
.TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG),
.TXOUT_DIV (TXOUT_DIV_REG),
.TXPCSRESET_TIME (TXPCSRESET_TIME_REG),
.TXPHDLY_CFG0 (TXPHDLY_CFG0_REG),
.TXPHDLY_CFG1 (TXPHDLY_CFG1_REG),
.TXPH_CFG (TXPH_CFG_REG),
.TXPH_CFG2 (TXPH_CFG2_REG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG),
.TXPI_CFG (TXPI_CFG_REG),
.TXPI_CFG0 (TXPI_CFG0_REG),
.TXPI_CFG1 (TXPI_CFG1_REG),
.TXPI_CFG2 (TXPI_CFG2_REG),
.TXPI_CFG3 (TXPI_CFG3_REG),
.TXPI_CFG4 (TXPI_CFG4_REG),
.TXPI_CFG5 (TXPI_CFG5_REG),
.TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG),
.TXPI_LPM (TXPI_LPM_REG),
.TXPI_PPM (TXPI_PPM_REG),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL_REG),
.TXPI_PPM_CFG (TXPI_PPM_CFG_REG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG),
.TXPI_VREFSEL (TXPI_VREFSEL_REG),
.TXPMARESET_TIME (TXPMARESET_TIME_REG),
.TXREFCLKDIV2_SEL (TXREFCLKDIV2_SEL_REG),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG),
.TXSYNC_OVRD (TXSYNC_OVRD_REG),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG),
.TX_CLK25_DIV (TX_CLK25_DIV_REG),
.TX_CLKMUX_EN (TX_CLKMUX_EN_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DCC_LOOP_RST_CFG (TX_DCC_LOOP_RST_CFG_REG),
.TX_DEEMPH0 (TX_DEEMPH0_REG),
.TX_DEEMPH1 (TX_DEEMPH1_REG),
.TX_DEEMPH2 (TX_DEEMPH2_REG),
.TX_DEEMPH3 (TX_DEEMPH3_REG),
.TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG),
.TX_DRIVE_MODE (TX_DRIVE_MODE_REG),
.TX_DRVMUX_CTRL (TX_DRVMUX_CTRL_REG),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG),
.TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG),
.TX_FIFO_BYP_EN (TX_FIFO_BYP_EN_REG),
.TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG),
.TX_PHICAL_CFG0 (TX_PHICAL_CFG0_REG),
.TX_PHICAL_CFG1 (TX_PHICAL_CFG1_REG),
.TX_PHICAL_CFG2 (TX_PHICAL_CFG2_REG),
.TX_PI_BIASSET (TX_PI_BIASSET_REG),
.TX_PI_IBIAS_MID (TX_PI_IBIAS_MID_REG),
.TX_PMADATA_OPT (TX_PMADATA_OPT_REG),
.TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG),
.TX_PMA_RSV0 (TX_PMA_RSV0_REG),
.TX_PREDRV_CTRL (TX_PREDRV_CTRL_REG),
.TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG),
.TX_PROGDIV_CFG (TX_PROGDIV_CFG_BIN),
.TX_PROGDIV_RATE (TX_PROGDIV_RATE_REG),
.TX_QPI_STATUS_EN (TX_QPI_STATUS_EN_REG),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG),
.TX_RXDETECT_REF (TX_RXDETECT_REF_REG),
.TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG),
.TX_SARC_LPBK_ENB (TX_SARC_LPBK_ENB_REG),
.TX_SW_MEAS (TX_SW_MEAS_REG),
.TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG),
.TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG),
.TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG),
.TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG),
.TX_USERPATTERN_DATA4 (TX_USERPATTERN_DATA4_REG),
.TX_USERPATTERN_DATA5 (TX_USERPATTERN_DATA5_REG),
.TX_USERPATTERN_DATA6 (TX_USERPATTERN_DATA6_REG),
.TX_USERPATTERN_DATA7 (TX_USERPATTERN_DATA7_REG),
.TX_VREG_CTRL (TX_VREG_CTRL_REG),
.TX_VREG_PDB (TX_VREG_PDB_REG),
.TX_VREG_VREFSEL (TX_VREG_VREFSEL_REG),
.TX_XCLK_SEL (TX_XCLK_SEL_REG),
.USB_BOTH_BURST_IDLE (USB_BOTH_BURST_IDLE_REG),
.USB_BURSTMAX_U3WAKE (USB_BURSTMAX_U3WAKE_REG),
.USB_BURSTMIN_U3WAKE (USB_BURSTMIN_U3WAKE_REG),
.USB_CLK_COR_EQ_EN (USB_CLK_COR_EQ_EN_REG),
.USB_EXT_CNTL (USB_EXT_CNTL_REG),
.USB_IDLEMAX_POLLING (USB_IDLEMAX_POLLING_REG),
.USB_IDLEMIN_POLLING (USB_IDLEMIN_POLLING_REG),
.USB_LFPSPING_BURST (USB_LFPSPING_BURST_REG),
.USB_LFPSPOLLING_BURST (USB_LFPSPOLLING_BURST_REG),
.USB_LFPSPOLLING_IDLE_MS (USB_LFPSPOLLING_IDLE_MS_REG),
.USB_LFPSU1EXIT_BURST (USB_LFPSU1EXIT_BURST_REG),
.USB_LFPSU2LPEXIT_BURST_MS (USB_LFPSU2LPEXIT_BURST_MS_REG),
.USB_LFPSU3WAKE_BURST_MS (USB_LFPSU3WAKE_BURST_MS_REG),
.USB_LFPS_TPERIOD (USB_LFPS_TPERIOD_REG),
.USB_LFPS_TPERIOD_ACCURATE (USB_LFPS_TPERIOD_ACCURATE_REG),
.USB_MODE (USB_MODE_REG),
.USB_PCIE_ERR_REP_DIS (USB_PCIE_ERR_REP_DIS_REG),
.USB_PING_SATA_MAX_INIT (USB_PING_SATA_MAX_INIT_REG),
.USB_PING_SATA_MIN_INIT (USB_PING_SATA_MIN_INIT_REG),
.USB_POLL_SATA_MAX_BURST (USB_POLL_SATA_MAX_BURST_REG),
.USB_POLL_SATA_MIN_BURST (USB_POLL_SATA_MIN_BURST_REG),
.USB_RAW_ELEC (USB_RAW_ELEC_REG),
.USB_RXIDLE_P0_CTRL (USB_RXIDLE_P0_CTRL_REG),
.USB_TXIDLE_TUNE_ENABLE (USB_TXIDLE_TUNE_ENABLE_REG),
.USB_U1_SATA_MAX_WAKE (USB_U1_SATA_MAX_WAKE_REG),
.USB_U1_SATA_MIN_WAKE (USB_U1_SATA_MIN_WAKE_REG),
.USB_U2_SAS_MAX_COM (USB_U2_SAS_MAX_COM_REG),
.USB_U2_SAS_MIN_COM (USB_U2_SAS_MIN_COM_REG),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG),
.Y_ALL_MODE (Y_ALL_MODE_REG),
.BUFGTCE (BUFGTCE_out),
.BUFGTCEMASK (BUFGTCEMASK_out),
.BUFGTDIV (BUFGTDIV_out),
.BUFGTRESET (BUFGTRESET_out),
.BUFGTRSTMASK (BUFGTRSTMASK_out),
.CPLLFBCLKLOST (CPLLFBCLKLOST_out),
.CPLLLOCK (CPLLLOCK_out),
.CPLLREFCLKLOST (CPLLREFCLKLOST_out),
.CSSDSTOPCLKDONE (CSSDSTOPCLKDONE_out),
.DMONITOROUT (DMONITOROUT_out),
.DMONITOROUTCLK (DMONITOROUTCLK_out),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.EYESCANDATAERROR (EYESCANDATAERROR_out),
.GTHTXN (GTHTXN_out),
.GTHTXP (GTHTXP_out),
.GTPOWERGOOD (GTPOWERGOOD_out),
.GTREFCLKMONITOR (GTREFCLKMONITOR_out),
.PCIERATEGEN3 (PCIERATEGEN3_out),
.PCIERATEIDLE (PCIERATEIDLE_out),
.PCIERATEQPLLPD (PCIERATEQPLLPD_out),
.PCIERATEQPLLRESET (PCIERATEQPLLRESET_out),
.PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out),
.PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out),
.PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out),
.PCIEUSERRATESTART (PCIEUSERRATESTART_out),
.PCSRSVDOUT (PCSRSVDOUT_out),
.PHYSTATUS (PHYSTATUS_out),
.PINRSRVDAS (PINRSRVDAS_out),
.PMASCANOUT (PMASCANOUT_out),
.POWERPRESENT (POWERPRESENT_out),
.RESETEXCEPTION (RESETEXCEPTION_out),
.RXBUFSTATUS (RXBUFSTATUS_out),
.RXBYTEISALIGNED (RXBYTEISALIGNED_out),
.RXBYTEREALIGN (RXBYTEREALIGN_out),
.RXCDRLOCK (RXCDRLOCK_out),
.RXCDRPHDONE (RXCDRPHDONE_out),
.RXCHANBONDSEQ (RXCHANBONDSEQ_out),
.RXCHANISALIGNED (RXCHANISALIGNED_out),
.RXCHANREALIGN (RXCHANREALIGN_out),
.RXCHBONDO (RXCHBONDO_out),
.RXCKCALDONE (RXCKCALDONE_out),
.RXCLKCORCNT (RXCLKCORCNT_out),
.RXCOMINITDET (RXCOMINITDET_out),
.RXCOMMADET (RXCOMMADET_out),
.RXCOMSASDET (RXCOMSASDET_out),
.RXCOMWAKEDET (RXCOMWAKEDET_out),
.RXCTRL0 (RXCTRL0_out),
.RXCTRL1 (RXCTRL1_out),
.RXCTRL2 (RXCTRL2_out),
.RXCTRL3 (RXCTRL3_out),
.RXDATA (RXDATA_out),
.RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out),
.RXDATAVALID (RXDATAVALID_out),
.RXDLYSRESETDONE (RXDLYSRESETDONE_out),
.RXELECIDLE (RXELECIDLE_out),
.RXHEADER (RXHEADER_out),
.RXHEADERVALID (RXHEADERVALID_out),
.RXLFPSTRESETDET (RXLFPSTRESETDET_out),
.RXLFPSU2LPEXITDET (RXLFPSU2LPEXITDET_out),
.RXLFPSU3WAKEDET (RXLFPSU3WAKEDET_out),
.RXMONITOROUT (RXMONITOROUT_out),
.RXOSINTDONE (RXOSINTDONE_out),
.RXOSINTSTARTED (RXOSINTSTARTED_out),
.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out),
.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out),
.RXOUTCLK (RXOUTCLK_out),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC_out),
.RXOUTCLKPCS (RXOUTCLKPCS_out),
.RXPHALIGNDONE (RXPHALIGNDONE_out),
.RXPHALIGNERR (RXPHALIGNERR_out),
.RXPMARESETDONE (RXPMARESETDONE_out),
.RXPRBSERR (RXPRBSERR_out),
.RXPRBSLOCKED (RXPRBSLOCKED_out),
.RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out),
.RXQPISENN (RXQPISENN_out),
.RXQPISENP (RXQPISENP_out),
.RXRATEDONE (RXRATEDONE_out),
.RXRECCLKOUT (RXRECCLKOUT_out),
.RXRESETDONE (RXRESETDONE_out),
.RXSLIDERDY (RXSLIDERDY_out),
.RXSLIPDONE (RXSLIPDONE_out),
.RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out),
.RXSLIPPMARDY (RXSLIPPMARDY_out),
.RXSTARTOFSEQ (RXSTARTOFSEQ_out),
.RXSTATUS (RXSTATUS_out),
.RXSYNCDONE (RXSYNCDONE_out),
.RXSYNCOUT (RXSYNCOUT_out),
.RXVALID (RXVALID_out),
.SCANOUT (SCANOUT_out),
.TXBUFSTATUS (TXBUFSTATUS_out),
.TXCOMFINISH (TXCOMFINISH_out),
.TXDCCDONE (TXDCCDONE_out),
.TXDLYSRESETDONE (TXDLYSRESETDONE_out),
.TXOUTCLK (TXOUTCLK_out),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC_out),
.TXOUTCLKPCS (TXOUTCLKPCS_out),
.TXPHALIGNDONE (TXPHALIGNDONE_out),
.TXPHINITDONE (TXPHINITDONE_out),
.TXPMARESETDONE (TXPMARESETDONE_out),
.TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out),
.TXQPISENN (TXQPISENN_out),
.TXQPISENP (TXQPISENP_out),
.TXRATEDONE (TXRATEDONE_out),
.TXRESETDONE (TXRESETDONE_out),
.TXSYNCDONE (TXSYNCDONE_out),
.TXSYNCOUT (TXSYNCOUT_out),
.BSR_SERIAL (BSR_SERIAL_in),
.CDRSTEPDIR (CDRSTEPDIR_in),
.CDRSTEPSQ (CDRSTEPSQ_in),
.CDRSTEPSX (CDRSTEPSX_in),
.CFGRESET (CFGRESET_in),
.CLKRSVD0 (CLKRSVD0_in),
.CLKRSVD1 (CLKRSVD1_in),
.CPLLFREQLOCK (CPLLFREQLOCK_in),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK_in),
.CPLLLOCKEN (CPLLLOCKEN_in),
.CPLLPD (CPLLPD_in),
.CPLLREFCLKSEL (CPLLREFCLKSEL_in),
.CPLLRESET (CPLLRESET_in),
.CSSDRSTB (CSSDRSTB_in),
.CSSDSTOPCLK (CSSDSTOPCLK_in),
.DMONFIFORESET (DMONFIFORESET_in),
.DMONITORCLK (DMONITORCLK_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPRST (DRPRST_in),
.DRPWE (DRPWE_in),
.EYESCANRESET (EYESCANRESET_in),
.EYESCANTRIGGER (EYESCANTRIGGER_in),
.FREQOS (FREQOS_in),
.GTGREFCLK (GTGREFCLK_in),
.GTHRXN (GTHRXN_in),
.GTHRXP (GTHRXP_in),
.GTNORTHREFCLK0 (GTNORTHREFCLK0_in),
.GTNORTHREFCLK1 (GTNORTHREFCLK1_in),
.GTREFCLK0 (GTREFCLK0_in),
.GTREFCLK1 (GTREFCLK1_in),
.GTRSVD (GTRSVD_in),
.GTRXRESET (GTRXRESET_in),
.GTRXRESETSEL (GTRXRESETSEL_in),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in),
.GTTXRESET (GTTXRESET_in),
.GTTXRESETSEL (GTTXRESETSEL_in),
.INCPCTRL (INCPCTRL_in),
.LOOPBACK (LOOPBACK_in),
.PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in),
.PCIERSTIDLE (PCIERSTIDLE_in),
.PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in),
.PCIEUSERRATEDONE (PCIEUSERRATEDONE_in),
.PCSRSVDIN (PCSRSVDIN_in),
.PMASCANCLK0 (PMASCANCLK0_in),
.PMASCANCLK1 (PMASCANCLK1_in),
.PMASCANCLK2 (PMASCANCLK2_in),
.PMASCANCLK3 (PMASCANCLK3_in),
.PMASCANCLK4 (PMASCANCLK4_in),
.PMASCANCLK5 (PMASCANCLK5_in),
.PMASCANCLK6 (PMASCANCLK6_in),
.PMASCANCLK7 (PMASCANCLK7_in),
.PMASCANCLK8 (PMASCANCLK8_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.PMASCANMODEB (PMASCANMODEB_in),
.PMASCANRSTEN (PMASCANRSTEN_in),
.QPLL0CLK (QPLL0CLK_in),
.QPLL0FREQLOCK (QPLL0FREQLOCK_in),
.QPLL0REFCLK (QPLL0REFCLK_in),
.QPLL1CLK (QPLL1CLK_in),
.QPLL1FREQLOCK (QPLL1FREQLOCK_in),
.QPLL1REFCLK (QPLL1REFCLK_in),
.RESETOVRD (RESETOVRD_in),
.RX8B10BEN (RX8B10BEN_in),
.RXAFECFOKEN (RXAFECFOKEN_in),
.RXBUFRESET (RXBUFRESET_in),
.RXCDRFREQRESET (RXCDRFREQRESET_in),
.RXCDRHOLD (RXCDRHOLD_in),
.RXCDROVRDEN (RXCDROVRDEN_in),
.RXCDRRESET (RXCDRRESET_in),
.RXCHBONDEN (RXCHBONDEN_in),
.RXCHBONDI (RXCHBONDI_in),
.RXCHBONDLEVEL (RXCHBONDLEVEL_in),
.RXCHBONDMASTER (RXCHBONDMASTER_in),
.RXCHBONDSLAVE (RXCHBONDSLAVE_in),
.RXCKCALRESET (RXCKCALRESET_in),
.RXCKCALSTART (RXCKCALSTART_in),
.RXCOMMADETEN (RXCOMMADETEN_in),
.RXDFEAGCCTRL (RXDFEAGCCTRL_in),
.RXDFEAGCHOLD (RXDFEAGCHOLD_in),
.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in),
.RXDFECFOKFCNUM (RXDFECFOKFCNUM_in),
.RXDFECFOKFEN (RXDFECFOKFEN_in),
.RXDFECFOKFPULSE (RXDFECFOKFPULSE_in),
.RXDFECFOKHOLD (RXDFECFOKHOLD_in),
.RXDFECFOKOVREN (RXDFECFOKOVREN_in),
.RXDFEKHHOLD (RXDFEKHHOLD_in),
.RXDFEKHOVRDEN (RXDFEKHOVRDEN_in),
.RXDFELFHOLD (RXDFELFHOLD_in),
.RXDFELFOVRDEN (RXDFELFOVRDEN_in),
.RXDFELPMRESET (RXDFELPMRESET_in),
.RXDFETAP10HOLD (RXDFETAP10HOLD_in),
.RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in),
.RXDFETAP11HOLD (RXDFETAP11HOLD_in),
.RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in),
.RXDFETAP12HOLD (RXDFETAP12HOLD_in),
.RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in),
.RXDFETAP13HOLD (RXDFETAP13HOLD_in),
.RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in),
.RXDFETAP14HOLD (RXDFETAP14HOLD_in),
.RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in),
.RXDFETAP15HOLD (RXDFETAP15HOLD_in),
.RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in),
.RXDFETAP2HOLD (RXDFETAP2HOLD_in),
.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in),
.RXDFETAP3HOLD (RXDFETAP3HOLD_in),
.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in),
.RXDFETAP4HOLD (RXDFETAP4HOLD_in),
.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in),
.RXDFETAP5HOLD (RXDFETAP5HOLD_in),
.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in),
.RXDFETAP6HOLD (RXDFETAP6HOLD_in),
.RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in),
.RXDFETAP7HOLD (RXDFETAP7HOLD_in),
.RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in),
.RXDFETAP8HOLD (RXDFETAP8HOLD_in),
.RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in),
.RXDFETAP9HOLD (RXDFETAP9HOLD_in),
.RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in),
.RXDFEUTHOLD (RXDFEUTHOLD_in),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN_in),
.RXDFEVPHOLD (RXDFEVPHOLD_in),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN_in),
.RXDFEXYDEN (RXDFEXYDEN_in),
.RXDLYBYPASS (RXDLYBYPASS_in),
.RXDLYEN (RXDLYEN_in),
.RXDLYOVRDEN (RXDLYOVRDEN_in),
.RXDLYSRESET (RXDLYSRESET_in),
.RXELECIDLEMODE (RXELECIDLEMODE_in),
.RXEQTRAINING (RXEQTRAINING_in),
.RXGEARBOXSLIP (RXGEARBOXSLIP_in),
.RXLATCLK (RXLATCLK_in),
.RXLPMEN (RXLPMEN_in),
.RXLPMGCHOLD (RXLPMGCHOLD_in),
.RXLPMGCOVRDEN (RXLPMGCOVRDEN_in),
.RXLPMHFHOLD (RXLPMHFHOLD_in),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN_in),
.RXLPMLFHOLD (RXLPMLFHOLD_in),
.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in),
.RXLPMOSHOLD (RXLPMOSHOLD_in),
.RXLPMOSOVRDEN (RXLPMOSOVRDEN_in),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in),
.RXMONITORSEL (RXMONITORSEL_in),
.RXOOBRESET (RXOOBRESET_in),
.RXOSCALRESET (RXOSCALRESET_in),
.RXOSHOLD (RXOSHOLD_in),
.RXOSOVRDEN (RXOSOVRDEN_in),
.RXOUTCLKSEL (RXOUTCLKSEL_in),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in),
.RXPCSRESET (RXPCSRESET_in),
.RXPD (RXPD_in),
.RXPHALIGN (RXPHALIGN_in),
.RXPHALIGNEN (RXPHALIGNEN_in),
.RXPHDLYPD (RXPHDLYPD_in),
.RXPHDLYRESET (RXPHDLYRESET_in),
.RXPHOVRDEN (RXPHOVRDEN_in),
.RXPLLCLKSEL (RXPLLCLKSEL_in),
.RXPMARESET (RXPMARESET_in),
.RXPOLARITY (RXPOLARITY_in),
.RXPRBSCNTRESET (RXPRBSCNTRESET_in),
.RXPRBSSEL (RXPRBSSEL_in),
.RXPROGDIVRESET (RXPROGDIVRESET_in),
.RXQPIEN (RXQPIEN_in),
.RXRATE (RXRATE_in),
.RXRATEMODE (RXRATEMODE_in),
.RXSLIDE (RXSLIDE_in),
.RXSLIPOUTCLK (RXSLIPOUTCLK_in),
.RXSLIPPMA (RXSLIPPMA_in),
.RXSYNCALLIN (RXSYNCALLIN_in),
.RXSYNCIN (RXSYNCIN_in),
.RXSYNCMODE (RXSYNCMODE_in),
.RXSYSCLKSEL (RXSYSCLKSEL_in),
.RXTERMINATION (RXTERMINATION_in),
.RXUSERRDY (RXUSERRDY_in),
.RXUSRCLK (RXUSRCLK_in),
.RXUSRCLK2 (RXUSRCLK2_in),
.SARCCLK (SARCCLK_in),
.SCANCLK (SCANCLK_in),
.SCANENB (SCANENB_in),
.SCANIN (SCANIN_in),
.SCANMODEB (SCANMODEB_in),
.SCANRSTB (SCANRSTB_in),
.SCANRSTEN (SCANRSTEN_in),
.SIGVALIDCLK (SIGVALIDCLK_in),
.TSTCLK0 (TSTCLK0_in),
.TSTCLK1 (TSTCLK1_in),
.TSTIN (TSTIN_in),
.TSTPD (TSTPD_in),
.TSTPDOVRDB (TSTPDOVRDB_in),
.TX8B10BBYPASS (TX8B10BBYPASS_in),
.TX8B10BEN (TX8B10BEN_in),
.TXCOMINIT (TXCOMINIT_in),
.TXCOMSAS (TXCOMSAS_in),
.TXCOMWAKE (TXCOMWAKE_in),
.TXCTRL0 (TXCTRL0_in),
.TXCTRL1 (TXCTRL1_in),
.TXCTRL2 (TXCTRL2_in),
.TXDATA (TXDATA_in),
.TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in),
.TXDCCFORCESTART (TXDCCFORCESTART_in),
.TXDCCRESET (TXDCCRESET_in),
.TXDEEMPH (TXDEEMPH_in),
.TXDETECTRX (TXDETECTRX_in),
.TXDIFFCTRL (TXDIFFCTRL_in),
.TXDLYBYPASS (TXDLYBYPASS_in),
.TXDLYEN (TXDLYEN_in),
.TXDLYHOLD (TXDLYHOLD_in),
.TXDLYOVRDEN (TXDLYOVRDEN_in),
.TXDLYSRESET (TXDLYSRESET_in),
.TXDLYUPDOWN (TXDLYUPDOWN_in),
.TXELECIDLE (TXELECIDLE_in),
.TXHEADER (TXHEADER_in),
.TXINHIBIT (TXINHIBIT_in),
.TXLATCLK (TXLATCLK_in),
.TXLFPSTRESET (TXLFPSTRESET_in),
.TXLFPSU2LPEXIT (TXLFPSU2LPEXIT_in),
.TXLFPSU3WAKE (TXLFPSU3WAKE_in),
.TXMAINCURSOR (TXMAINCURSOR_in),
.TXMARGIN (TXMARGIN_in),
.TXMUXDCDEXHOLD (TXMUXDCDEXHOLD_in),
.TXMUXDCDORWREN (TXMUXDCDORWREN_in),
.TXONESZEROS (TXONESZEROS_in),
.TXOUTCLKSEL (TXOUTCLKSEL_in),
.TXPCSRESET (TXPCSRESET_in),
.TXPD (TXPD_in),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE_in),
.TXPHALIGN (TXPHALIGN_in),
.TXPHALIGNEN (TXPHALIGNEN_in),
.TXPHDLYPD (TXPHDLYPD_in),
.TXPHDLYRESET (TXPHDLYRESET_in),
.TXPHDLYTSTCLK (TXPHDLYTSTCLK_in),
.TXPHINIT (TXPHINIT_in),
.TXPHOVRDEN (TXPHOVRDEN_in),
.TXPIPPMEN (TXPIPPMEN_in),
.TXPIPPMOVRDEN (TXPIPPMOVRDEN_in),
.TXPIPPMPD (TXPIPPMPD_in),
.TXPIPPMSEL (TXPIPPMSEL_in),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in),
.TXPISOPD (TXPISOPD_in),
.TXPLLCLKSEL (TXPLLCLKSEL_in),
.TXPMARESET (TXPMARESET_in),
.TXPOLARITY (TXPOLARITY_in),
.TXPOSTCURSOR (TXPOSTCURSOR_in),
.TXPRBSFORCEERR (TXPRBSFORCEERR_in),
.TXPRBSSEL (TXPRBSSEL_in),
.TXPRECURSOR (TXPRECURSOR_in),
.TXPROGDIVRESET (TXPROGDIVRESET_in),
.TXQPIBIASEN (TXQPIBIASEN_in),
.TXQPIWEAKPUP (TXQPIWEAKPUP_in),
.TXRATE (TXRATE_in),
.TXRATEMODE (TXRATEMODE_in),
.TXSEQUENCE (TXSEQUENCE_in),
.TXSWING (TXSWING_in),
.TXSYNCALLIN (TXSYNCALLIN_in),
.TXSYNCIN (TXSYNCIN_in),
.TXSYNCMODE (TXSYNCMODE_in),
.TXSYSCLKSEL (TXSYSCLKSEL_in),
.TXUSERRDY (TXUSERRDY_in),
.TXUSRCLK (TXUSRCLK_in),
.TXUSRCLK2 (TXUSRCLK2_in),
.GSR (glblGSR)
);
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(DMONITORCLK => DMONITOROUT[0]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[10]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[11]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[12]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[13]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[14]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[15]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[1]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[2]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[3]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[4]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[5]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[6]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[7]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[8]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[9]) = (0:0:0, 0:0:0);
(DRPCLK => DMONITOROUTCLK) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100);
(DRPCLK => DRPRDY) = (100:100:100, 100:100:100);
(GTGREFCLK => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTGREFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTGREFCLK => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTGREFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTGREFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(QPLL0REFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(QPLL0REFCLK => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(QPLL0REFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(QPLL0REFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(QPLL1REFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(QPLL1REFCLK => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(QPLL1REFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(QPLL1REFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(RXUSRCLK => DMONITOROUTCLK) = (100:100:100, 100:100:100);
(RXUSRCLK => RXCHBONDO[0]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXCHBONDO[1]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXCHBONDO[2]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXCHBONDO[3]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXCHBONDO[4]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXPHALIGNERR) = (100:100:100, 100:100:100);
(RXUSRCLK2 => DMONITOROUTCLK) = (100:100:100, 100:100:100);
(RXUSRCLK2 => PHYSTATUS) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBUFSTATUS[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBUFSTATUS[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBUFSTATUS[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBYTEISALIGNED) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBYTEREALIGN) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHANBONDSEQ) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHANISALIGNED) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHANREALIGN) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCLKCORCNT[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCLKCORCNT[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCOMINITDET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCOMMADET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCOMSASDET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCOMWAKEDET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATAVALID[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATAVALID[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[10]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[11]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[12]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[13]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[14]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[15]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[16]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[17]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[18]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[19]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[20]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[21]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[22]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[23]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[24]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[25]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[26]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[27]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[28]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[29]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[30]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[31]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[32]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[33]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[34]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[35]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[36]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[37]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[38]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[39]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[40]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[41]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[42]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[43]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[44]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[45]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[46]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[47]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[48]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[49]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[50]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[51]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[52]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[53]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[54]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[55]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[56]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[57]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[58]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[59]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[60]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[61]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[62]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[63]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[8]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[9]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADERVALID[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADERVALID[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXLFPSTRESETDET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXPHALIGNERR) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXPRBSERR) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXPRBSLOCKED) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXRATEDONE) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSLIDERDY) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSLIPDONE) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSLIPOUTCLKRDY) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSLIPPMARDY) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTARTOFSEQ[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTARTOFSEQ[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTATUS[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTATUS[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTATUS[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXVALID) = (100:100:100, 100:100:100);
(TXUSRCLK => BUFGTRSTMASK[1]) = (0:0:0, 0:0:0);
(TXUSRCLK => DMONITOROUTCLK) = (0:0:0, 0:0:0);
(TXUSRCLK => RXPHALIGNERR) = (0:0:0, 0:0:0);
(TXUSRCLK2 => DMONITOROUTCLK) = (100:100:100, 100:100:100);
(TXUSRCLK2 => RXPHALIGNERR) = (100:100:100, 100:100:100);
(TXUSRCLK2 => TXBUFSTATUS[0]) = (100:100:100, 100:100:100);
(TXUSRCLK2 => TXBUFSTATUS[1]) = (100:100:100, 100:100:100);
(TXUSRCLK2 => TXCOMFINISH) = (100:100:100, 100:100:100);
(TXUSRCLK2 => TXRATEDONE) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge DRPCLK, 0:0:0, notifier);
$period (negedge RXUSRCLK, 0:0:0, notifier);
$period (negedge RXUSRCLK2, 0:0:0, notifier);
$period (negedge TXUSRCLK, 0:0:0, notifier);
$period (negedge TXUSRCLK2, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge RXUSRCLK, 0:0:0, notifier);
$period (posedge RXUSRCLK2, 0:0:0, notifier);
$period (posedge TXUSRCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK2, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
$width (negedge DRPCLK, 0:0:0, 0, notifier);
$width (negedge RXUSRCLK, 0:0:0, 0, notifier);
$width (negedge RXUSRCLK2, 0:0:0, 0, notifier);
$width (negedge TXUSRCLK, 0:0:0, 0, notifier);
$width (negedge TXUSRCLK2, 0:0:0, 0, notifier);
$width (posedge DRPCLK, 0:0:0, 0, notifier);
$width (posedge RXUSRCLK, 0:0:0, 0, notifier);
$width (posedge RXUSRCLK2, 0:0:0, 0, notifier);
$width (posedge TXUSRCLK, 0:0:0, 0, notifier);
$width (posedge TXUSRCLK2, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
//
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
module a5_multiexp ( input pcie_perstn
, input pcie_refclk
, input [3:0] pcie_rx
, output [3:0] pcie_tx
, output [3:0] user_led
, output [3:0] extra_led
, output hsma_tx_led
, output hsma_rx_led
/*//extra i/o
, input [3:0] user_dipsw
, output hsma_rx_led
*/
, input [2:0] user_pb // hard reset switch
, input clkin_100_p // xtal dedicated to RAM
/* memory interface i/o */
, output [12:0] ddr3_a // memory.mem_a
, output [2:0] ddr3_ba // .mem_ba
, output ddr3_ck_p // .mem_ck
, output ddr3_ck_n // .mem_ck_n
, output ddr3_cke // .mem_cke
, output ddr3_csn // .mem_cs_n
, output [3:0] ddr3_dm // .mem_dm
, output ddr3_rasn // .mem_ras_n
, output ddr3_casn // .mem_cas_n
, output ddr3_wen // .mem_we_n
, output ddr3_rstn // .mem_reset_n
, inout [31:0] ddr3_dq // .mem_dq
, inout [3:0] ddr3_dqs_p // .mem_dqs
, inout [3:0] ddr3_dqs_n // .mem_dqs_n
, output ddr3_odt // .mem_odt
, input ddr3_oct_rzq // oct.rzqin
);
wire bus_clk, quiesce;
wire [31:0] xrdata, xwdata;
wire xrden, xempty, xropen, xwren, xfull, xwopen;
wire [31:0] cdatao;
wire [11:0] cusedw_out;
wire cwren;
wire [31:0] cdatai;
wire [11:0] cusedw_in;
wire crden, cempty;
wire pll_clk, pll_core_locked, pcie_ready, pcie_writing, ctrl_reset_n;
assign hsma_tx_led = ~pll_core_locked;
assign hsma_rx_led = ctrl_reset_n;
localparam fifo_nwords = 2048;
localparam fifo_widthu = $clog2(fifo_nwords);
xillybus ixilly ( .user_r_r_rden (xrden) // FPGA -> HOST
, .user_r_r_empty (xempty)
, .user_r_r_data (xrdata)
, .user_r_r_eof (1'b0)
, .user_r_r_open (xropen)
, .user_w_w_wren (xwren) // HOST -> FPGA
, .user_w_w_full (xfull)
, .user_w_w_data (xwdata)
, .user_w_w_open (xwopen)
, .pcie_perstn (pcie_perstn) // general
, .pcie_refclk (pcie_refclk)
, .pcie_rx (pcie_rx)
, .bus_clk (bus_clk)
, .pcie_tx (pcie_tx)
, .quiesce (quiesce)
, .user_led (user_led)
);
// FIFO: host -> fpga
dcfifo #( .intended_device_family ("Arria V")
, .lpm_numwords (fifo_nwords)
, .lpm_showahead ("OFF")
, .lpm_type ("dcfifo")
, .lpm_width (32)
, .lpm_widthu (fifo_widthu)
, .overflow_checking ("ON")
, .underflow_checking ("ON")
, .rdsync_delaypipe (4)
, .wrsync_delaypipe (4)
, .read_aclr_synch ("OFF")
, .write_aclr_synch ("OFF")
, .use_eab ("ON")
, .add_ram_output_register ("ON")
) f_fromhost
( .aclr (quiesce)
, .data (xwdata)
, .wrfull (xfull)
, .wrreq (xwren)
, .wrclk (bus_clk)
, .wrusedw ()
, .wrempty ()
, .q (cdatai)
, .rdempty (cempty)
, .rdreq (crden)
, .rdclk (pll_clk)
, .rdusedw (cusedw_in[10:0])
, .rdfull (cusedw_in[11])
);
// FIFO: fpga -> host
dcfifo #( .intended_device_family ("Arria V")
, .lpm_numwords (fifo_nwords)
, .lpm_showahead ("OFF")
, .lpm_type ("dcfifo")
, .lpm_width (32)
, .lpm_widthu (fifo_widthu)
, .overflow_checking ("ON")
, .underflow_checking ("ON")
, .rdsync_delaypipe (4)
, .wrsync_delaypipe (4)
, .read_aclr_synch ("OFF")
, .write_aclr_synch ("OFF")
, .use_eab ("ON")
, .add_ram_output_register ("ON")
) f_tohost
( .aclr (~ctrl_reset_n)
, .data (cdatao)
, .wrfull (cusedw_out[11])
, .wrreq (cwren)
, .wrclk (pll_clk)
, .wrusedw (cusedw_out[10:0])
, .wrempty ()
, .q (xrdata)
, .rdempty (xempty)
, .rdreq (xrden)
, .rdclk (bus_clk)
, .rdusedw ()
, .rdfull ()
);
// PLL: make core clock related to Xillybus clock
// to minimize clock domain crossing headaches
// (viz., synchronizer issues)
pll_top ipll ( .ref_clk (bus_clk)
, .rst (~pcie_perstn)
, .out_clk (pll_clk)
, .locked (pll_core_locked)
, .pcie_ready (~quiesce)
, .pcie_ready_sync (pcie_ready)
, .xwopen (xwopen)
, .xwopen_sync (pcie_writing)
);
// And now, the actual multiexp piece.
// If we were using partial reconfiguration, this would be the piece
// we'd rip out and replace with something else. Sadly, I think we have
// to upgrade to a Stratix device for that to be reasonable.
multiexp_top #( .fifo_widthu (fifo_widthu)
, .n_mult (16)
) imexp
( .clk (pll_clk)
, .pcie_perstn (pcie_perstn)
, .pcie_ready (pcie_ready)
, .user_resetn (user_pb[0])
, .pll_core_locked (pll_core_locked)
, .ctrl_reset_n (ctrl_reset_n)
, .fifo_datai (cdatai)
, .fifo_empty (cempty)
, .fifo_rden (crden)
, .fifo_usedw_in (cusedw_in)
, .pcie_writing (pcie_writing)
, .fifo_datao (cdatao)
, .fifo_wren (cwren)
, .fifo_usedw_out (cusedw_out)
, .status_leds (extra_led)
, .ddr3_a (ddr3_a)
, .ddr3_ba (ddr3_ba)
, .ddr3_ck_p (ddr3_ck_p)
, .ddr3_ck_n (ddr3_ck_n)
, .ddr3_cke (ddr3_cke)
, .ddr3_csn (ddr3_csn)
, .ddr3_dm (ddr3_dm)
, .ddr3_rasn (ddr3_rasn)
, .ddr3_casn (ddr3_casn)
, .ddr3_wen (ddr3_wen)
, .ddr3_rstn (ddr3_rstn)
, .ddr3_dq (ddr3_dq)
, .ddr3_dqs_p (ddr3_dqs_p)
, .ddr3_dqs_n (ddr3_dqs_n)
, .ddr3_odt (ddr3_odt)
, .ddr3_oct_rzq (ddr3_oct_rzq)
, .clkin_100_p (clkin_100_p)
);
endmodule
|
//==================================================================================================
// Filename : CORDIC_FSM_v3.v
// Created On : 2016-10-03 15:59:21
// Last Modified : 2016-10-04 21:24:46
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : CORDIC's FSM Unit
//
//
//==================================================================================================
`timescale 1ns / 1ps
module CORDIC_FSM_v3
(
//Input Signals
input wire clk, // Reloj del sitema.
input wire reset, // Reset del sitema.
input wire beg_FSM_CORDIC, // Señal de inicio de la maquina de estados.
input wire ACK_FSM_CORDIC, // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
input wire exception,
input wire max_tick_iter, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
input wire max_tick_var, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
input wire enab_dff_z,
//Output Signals
output reg reset_reg_cordic,
output reg ready_CORDIC, // Señal que indica que el calculo CORDIC se ha terminado.
output reg beg_add_subt, // Señal que indica al modulo de suma/resta que inicie su operacion.
output reg enab_cont_iter, // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
output reg enab_cont_var, // Señales de habilitacion y carga, respectivamente, en el contador de variables.
output reg enab_RB1, enab_RB2, enab_RB3,
output reg enab_d_ff5_data_out
);
//symbolic state declaration
localparam [3:0] est0 = 0,
est1 = 1,
est2 = 2,
est3 = 3,
est4 = 4,
est5 = 5,
est6 = 6,
est7 = 7;
//signal declaration
reg [3:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge reset)
begin
if(reset) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
reset_reg_cordic = 0;
enab_RB1 = 0;
enab_RB2 = 0;
enab_RB3 = 0;
enab_cont_var = 0;
enab_cont_iter = 0;
enab_d_ff5_data_out = 0;
ready_CORDIC = 0;
beg_add_subt = 0;
case(state_reg)
est0:
begin
reset_reg_cordic = 1'b1;
enab_RB1 = 1'b1;
if(beg_FSM_CORDIC) begin
state_next = est1;
end else begin
state_next = est0;
end
end
est1:
begin
enab_RB1 = 1'b1;
state_next = est2;
end
est2:
begin
enab_RB2 = 1'b1;
if(exception) begin
state_next = est0;
end else begin
state_next = est3;
end
end
est3:
begin
enab_RB3 = 1'b1;
state_next = est4;
end
est4:
begin
enab_cont_var = 1'b1; //cont_var++
beg_add_subt = 1'b1;
if (max_tick_var) begin
state_next = est5;
end else begin
state_next = est4;
end
end
est5:
begin
beg_add_subt = 1'b1;
if (enab_dff_z) begin
state_next = est6;
end else begin
state_next = est5;
end
end
est6:
begin
enab_cont_iter = 1'b1; //cont_iter++
enab_cont_var = 1'b1; //rst cont to from 3 to 0
if (max_tick_iter) begin
state_next = est7; //Es la ultima iteracion, por lo tanto, seguimos a la siguiente etapa
enab_d_ff5_data_out = 1;
end else begin
state_next = est2; //Seguir las iteraciones
//
end
end
est7:
begin
ready_CORDIC = 1'b1;
enab_d_ff5_data_out = 1'b1;
if(ACK_FSM_CORDIC) begin
state_next = est0;
end else begin
state_next = est7;
end
end
default :
begin
state_next = est0;
end
endcase
end
endmodule
|
`include "../src/registers.v"
`include "../src/reg_interface.v"
`include "../src/clock.v"
module test_registros;
wire clk;
reg reset, ir_ri0_enb, ir_ri1_enb, ir_ri2_enb;
wire [7:0] ow_ri0_out_data, ow_ri1_out_data, ow_ri2_out_data;
reg [7:0] ir_ri0_in_data, ir_ri0_address, ir_ri1_in_data, ir_ri1_address, ir_ri2_in_data, ir_ri2_address;
clock c(clk);
REG_INTERFACE reg_interface(ow_ri0_out_data, ow_ri1_out_data, ow_ri2_out_data, ir_ri0_address, ir_ri1_address, ir_ri2_address, ir_ri0_in_data, ir_ri1_in_data, ir_ri2_in_data, ir_ri0_enb, ir_ri1_enb, ir_ri2_enb, reset, clk);
initial
begin
$dumpfile("test_registros.vcd");
$dumpvars;
reset=1;
#`PERIODO reset=0;
ir_ri0_enb=0;
ir_ri1_enb=0;
ir_ri2_enb=1;
ir_ri0_address=8'h00;
ir_ri1_address=8'h6F;
ir_ri2_address=8'h00;
ir_ri0_in_data=8'h00;
ir_ri1_in_data=8'h3F;
ir_ri2_in_data=8'h00;
while(ir_ri0_in_data< 8'h06)
begin
ir_ri0_address=0;
ir_ri1_address=8'h30;
while(ir_ri0_address<8'h20)
begin
#`PERIODO ir_ri0_address=ir_ri0_address+1;
ir_ri1_address=ir_ri1_address-1;
end
#`PERIODO ir_ri0_in_data=ir_ri0_in_data+1;
ir_ri1_in_data=ir_ri1_in_data-1;
end
reset=1;
#`PERIODO $finish;
end
endmodule
|
//=======================================================
// Ports generated by Terasic System Builder
//=======================================================
module vid_io_demo(
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
//////////// LED //////////
output [8:0] LEDG,
output [17:0] LEDR,
//////////// KEY //////////
input [3:0] KEY,
//////////// VGA //////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
//////////// I2C for Tv-Decoder //////////
output I2C_SCLK,
inout I2C_SDAT,
//////////// TV Decoder //////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [31:0] DRAM_DQ,
output [3:0] DRAM_DQM,
output DRAM_RAS_N,
output DRAM_WE_N
);
//Global Reset
wire aresetn;
assign aresetn = KEY[0];
//Video IO Pipeline
pipeline_wrapper pipeline_wrapper_inst
(
.clk (CLOCK_50),
.aresetn (aresetn),
//////// VGA //////////
.VGA_B (VGA_B),
.VGA_BLANK_N (VGA_BLANK_N),
.VGA_CLK (VGA_CLK),
.VGA_G (VGA_G),
.VGA_HS (VGA_HS),
.VGA_R (VGA_R),
.VGA_SYNC_N (VGA_SYNC_N),
.VGA_VS (VGA_VS),
//////// TV Decoder //////////
.TD_CLK27 (TD_CLK27),
.TD_DATA (TD_DATA),
.TD_HS (TD_HS),
.TD_RESET_N (TD_RESET_N),
.TD_VS (TD_VS),
//////// SDRAM //////////
.DRAM_ADDR (DRAM_ADDR),
.DRAM_BA (DRAM_BA),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_CKE (DRAM_CKE),
.DRAM_CLK (DRAM_CLK),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_DQ (DRAM_DQ),
.DRAM_DQM (DRAM_DQM),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_WE_N (DRAM_WE_N)
);
endmodule
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Basic Function Block for InjectorPumpsController
//defines for state names used internally
`define STATE_RejectCanister 0
`define STATE_AwaitPump 1
`define STATE_VacuumPump 2
`define STATE_FinishPump 3
`define STATE_StartPump 4
`define STATE_OpenValve 5
`define STATE_StopVacuum 6
module FB_InjectorPumpsController
(
input wire clk,
//input events
input wire StartPump_eI,
input wire EmergencyStopChanged_eI,
input wire CanisterPressureChanged_eI,
input wire FillContentsAvailableChanged_eI,
input wire VacuumTimerElapsed_eI,
//output events
output wire PumpFinished_eO,
output wire RejectCanister_eO,
output wire InjectorControlsChanged_eO,
output wire FillContentsChanged_eO,
output wire StartVacuumTimer_eO,
//input variables
input wire EmergencyStop_I,
input wire [7:0] CanisterPressure_I,
input wire [7:0] FillContentsAvailable_I,
//output variables
output reg InjectorContentsValveOpen_O ,
output reg InjectorVacuumRun_O ,
output reg InjectorPressurePumpRun_O ,
output reg FillContents_O ,
input reset
);
////BEGIN internal copies of I/O
//input events
wire StartPump;
assign StartPump = StartPump_eI;
wire EmergencyStopChanged;
assign EmergencyStopChanged = EmergencyStopChanged_eI;
wire CanisterPressureChanged;
assign CanisterPressureChanged = CanisterPressureChanged_eI;
wire FillContentsAvailableChanged;
assign FillContentsAvailableChanged = FillContentsAvailableChanged_eI;
wire VacuumTimerElapsed;
assign VacuumTimerElapsed = VacuumTimerElapsed_eI;
//output events
reg PumpFinished;
assign PumpFinished_eO = PumpFinished;
reg RejectCanister;
assign RejectCanister_eO = RejectCanister;
reg InjectorControlsChanged;
assign InjectorControlsChanged_eO = InjectorControlsChanged;
reg FillContentsChanged;
assign FillContentsChanged_eO = FillContentsChanged;
reg StartVacuumTimer;
assign StartVacuumTimer_eO = StartVacuumTimer;
//input variables
reg EmergencyStop ;
reg [7:0] CanisterPressure ;
reg [7:0] FillContentsAvailable ;
//output variables
reg InjectorContentsValveOpen ;
reg InjectorVacuumRun ;
reg InjectorPressurePumpRun ;
reg FillContents ;
////END internal copies of I/O
////BEGIN internal vars
////END internal vars
//BEGIN STATE variables
reg [2:0] state = `STATE_RejectCanister;
reg entered = 1'b0;
//END STATE variables
//BEGIN algorithm triggers
reg StartVacuum_alg_en = 1'b0;
reg ClearControls_alg_en = 1'b0;
reg OpenValve_alg_en = 1'b0;
reg StartPump_alg_en = 1'b0;
//END algorithm triggers
always@(posedge clk) begin
if(reset) begin
//reset state
state = `STATE_RejectCanister;
//reset I/O registers
PumpFinished = 1'b0;
RejectCanister = 1'b0;
InjectorControlsChanged = 1'b0;
FillContentsChanged = 1'b0;
StartVacuumTimer = 1'b0;
EmergencyStop = 0;
CanisterPressure = 0;
FillContentsAvailable = 0;
InjectorContentsValveOpen = 0;
InjectorVacuumRun = 0;
InjectorPressurePumpRun = 0;
FillContents = 0;
//reset internal vars
end else begin
//BEGIN clear output events
PumpFinished = 1'b0;
RejectCanister = 1'b0;
InjectorControlsChanged = 1'b0;
FillContentsChanged = 1'b0;
StartVacuumTimer = 1'b0;
//END clear output events
//BEGIN update internal inputs on relevant events
if(EmergencyStopChanged) begin
EmergencyStop = EmergencyStop_I;
end
if(CanisterPressureChanged) begin
CanisterPressure = CanisterPressure_I;
end
if(FillContentsAvailableChanged) begin
FillContentsAvailable = FillContentsAvailable_I;
end
//END update internal inputs
//BEGIN ecc
entered = 1'b0;
case(state)
`STATE_RejectCanister: begin
if(1) begin
state = `STATE_AwaitPump;
entered = 1'b1;
end
end
`STATE_AwaitPump: begin
if(StartPump) begin
state = `STATE_VacuumPump;
entered = 1'b1;
end
end
`STATE_VacuumPump: begin
if(VacuumTimerElapsed) begin
state = `STATE_RejectCanister;
entered = 1'b1;
end else if(CanisterPressureChanged && CanisterPressure <= 10) begin
state = `STATE_StopVacuum;
entered = 1'b1;
end
end
`STATE_FinishPump: begin
if(1) begin
state = `STATE_AwaitPump;
entered = 1'b1;
end
end
`STATE_StartPump: begin
if(CanisterPressureChanged && CanisterPressure >= 245) begin
state = `STATE_FinishPump;
entered = 1'b1;
end
end
`STATE_OpenValve: begin
if(1) begin
state = `STATE_StartPump;
entered = 1'b1;
end
end
`STATE_StopVacuum: begin
if(1) begin
state = `STATE_OpenValve;
entered = 1'b1;
end
end
default: begin
state = 0;
end
endcase
//END ecc
//BEGIN triggers
StartVacuum_alg_en = 1'b0;
ClearControls_alg_en = 1'b0;
OpenValve_alg_en = 1'b0;
StartPump_alg_en = 1'b0;
if(entered) begin
case(state)
`STATE_RejectCanister: begin
ClearControls_alg_en = 1'b1;
RejectCanister = 1'b1;
InjectorControlsChanged = 1'b1;
end
`STATE_AwaitPump: begin
PumpFinished = 1'b1;
end
`STATE_VacuumPump: begin
StartVacuum_alg_en = 1'b1;
InjectorControlsChanged = 1'b1;
StartVacuumTimer = 1'b1;
end
`STATE_FinishPump: begin
ClearControls_alg_en = 1'b1;
InjectorControlsChanged = 1'b1;
end
`STATE_StartPump: begin
StartPump_alg_en = 1'b1;
InjectorControlsChanged = 1'b1;
end
`STATE_OpenValve: begin
OpenValve_alg_en = 1'b1;
InjectorControlsChanged = 1'b1;
end
`STATE_StopVacuum: begin
ClearControls_alg_en = 1'b1;
InjectorControlsChanged = 1'b1;
end
default: begin
end
endcase
end
//END triggers
//BEGIN algorithms
if(StartVacuum_alg_en) begin
InjectorVacuumRun = 1;
end
if(ClearControls_alg_en) begin
InjectorContentsValveOpen = 0;
InjectorPressurePumpRun = 0;
InjectorVacuumRun = 0;
end
if(OpenValve_alg_en) begin
InjectorContentsValveOpen = 1;
end
if(StartPump_alg_en) begin
InjectorPressurePumpRun = 1;
end
//END algorithms
//BEGIN update external output variables on relevant events
if(InjectorControlsChanged) begin
InjectorContentsValveOpen_O = InjectorContentsValveOpen;
InjectorVacuumRun_O = InjectorVacuumRun;
InjectorPressurePumpRun_O = InjectorPressurePumpRun;
end
if(FillContentsChanged) begin
FillContents_O = FillContents;
end
//END update external output variables
end
end
endmodule |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:30 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_rst_ps7_0_100M_0/ip_design_rst_ps7_0_100M_0_sim_netlist.v
// Design : ip_design_rst_ps7_0_100M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
(* NotValidForBitStream *)
module ip_design_rst_ps7_0_100M_0
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
ip_design_rst_ps7_0_100M_0_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module ip_design_rst_ps7_0_100M_0_cdc_sync
(lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module ip_design_rst_ps7_0_100M_0_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* ORIG_REF_NAME = "lpf" *)
module ip_design_rst_ps7_0_100M_0_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
ip_design_rst_ps7_0_100M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
ip_design_rst_ps7_0_100M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
(* ORIG_REF_NAME = "proc_sys_reset" *)
module ip_design_rst_ps7_0_100M_0_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\BSR_OUT_DFF[0].FDRE_BSR
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Bsr_out),
.Q(bus_struct_reset),
.R(1'b0));
ip_design_rst_ps7_0_100M_0_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
FDRE_inst
(.C(slowest_sync_clk),
.CE(1'b1),
.D(MB_out),
.Q(mb_reset),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\PR_OUT_DFF[0].FDRE_PER
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Pr_out),
.Q(peripheral_reset),
.R(1'b0));
ip_design_rst_ps7_0_100M_0_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (SEQ_n_4),
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.lpf_int(lpf_int),
.slowest_sync_clk(slowest_sync_clk));
endmodule
(* ORIG_REF_NAME = "sequence_psr" *)
module ip_design_rst_ps7_0_100M_0_sequence_psr
(MB_out,
Bsr_out,
Pr_out,
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ,
lpf_int,
slowest_sync_clk);
output MB_out;
output Bsr_out;
output Pr_out;
output \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
output \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
wire Bsr_out;
wire Core_i_1_n_0;
wire MB_out;
wire Pr_out;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
(.I0(Bsr_out),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
(.I0(Pr_out),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(MB_out),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b1))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(MB_out),
.S(lpf_int));
ip_design_rst_ps7_0_100M_0_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(Bsr_out),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b1))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(Bsr_out),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(MB_out),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(Pr_out),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b1))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(Pr_out),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
(* ORIG_REF_NAME = "upcnt_n" *)
module ip_design_rst_ps7_0_100M_0_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLXTN_PP_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_SYMBOL_V
`define SKY130_FD_SC_HD__O22A_SYMBOL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_SYMBOL_V
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifndef PICORV32_REGS
`ifdef PICORV32_V
`error "picosoc.v must be read before picorv32.v!"
`endif
`define PICORV32_REGS picosoc_regs
`endif
module picosoc (
input clk,
input resetn,
output iomem_valid,
input iomem_ready,
output [ 3:0] iomem_wstrb,
output [31:0] iomem_addr,
output [31:0] iomem_wdata,
input [31:0] iomem_rdata,
input irq_5,
input irq_6,
input irq_7,
output ser_tx,
input ser_rx,
output flash_csb,
output flash_clk,
output flash_io0_oe,
output flash_io1_oe,
output flash_io2_oe,
output flash_io3_oe,
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
output flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di
);
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
reg [31:0] irq;
wire irq_stall = 0;
wire irq_uart = 0;
always @* begin
irq = 0;
irq[3] = irq_stall;
irq[4] = irq_uart;
irq[5] = irq_5;
irq[6] = irq_6;
irq[7] = irq_7;
end
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire spimem_ready;
wire [31:0] spimem_rdata;
reg ram_ready;
wire [31:0] ram_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
wire [31:0] spimemio_cfgreg_do;
wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
wire [31:0] simpleuart_reg_div_do;
wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
wire [31:0] simpleuart_reg_dat_do;
wire simpleuart_reg_dat_wait;
assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready || spimemio_cfgreg_sel ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata :
spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(1),
.COMPRESSED_ISA(1),
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_IRQ_QREGS(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.irq (irq )
);
spimemio spimemio (
.clk (clk),
.resetn (resetn),
.valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
.ready (spimem_ready),
.addr (mem_addr[23:0]),
.rdata (spimem_rdata),
.flash_csb (flash_csb ),
.flash_clk (flash_clk ),
.flash_io0_oe (flash_io0_oe),
.flash_io1_oe (flash_io1_oe),
.flash_io2_oe (flash_io2_oe),
.flash_io3_oe (flash_io3_oe),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di),
.cfgreg_we(spimemio_cfgreg_sel ? mem_wstrb : 4'b 0000),
.cfgreg_di(mem_wdata),
.cfgreg_do(spimemio_cfgreg_do)
);
simpleuart simpleuart (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
.reg_div_di (mem_wdata),
.reg_div_do (simpleuart_reg_div_do),
.reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
.reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
.reg_dat_di (mem_wdata),
.reg_dat_do (simpleuart_reg_dat_do),
.reg_dat_wait(simpleuart_reg_dat_wait)
);
always @(posedge clk)
ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
picosoc_mem #(.WORDS(MEM_WORDS)) memory (
.clk(clk),
.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
.addr(mem_addr[23:2]),
.wdata(mem_wdata),
.rdata(ram_rdata)
);
endmodule
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
module picosoc_mem #(
parameter integer WORDS = 256
) (
input clk,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output reg [31:0] rdata
);
reg [31:0] mem [0:WORDS-1];
always @(posedge clk) begin
rdata <= mem[addr];
if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
if (wen[2]) mem[addr][23:16] <= wdata[23:16];
if (wen[3]) mem[addr][31:24] <= wdata[31:24];
end
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:23:09 MST 2015
//Date : Fri Apr 24 21:57:30 2015
//Host : xps15 running 64-bit major release (build 9200)
//Command : generate_target tutorial_wrapper.bd
//Design : tutorial_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module tutorial_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
hdmio_io_clk,
hdmio_io_data,
hdmio_io_de,
hdmio_io_hsync,
hdmio_io_spdif,
hdmio_io_vsync,
zed_hdmi_iic_scl_io,
zed_hdmi_iic_sda_io);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output hdmio_io_clk;
output [15:0]hdmio_io_data;
output hdmio_io_de;
output hdmio_io_hsync;
output hdmio_io_spdif;
output hdmio_io_vsync;
inout zed_hdmi_iic_scl_io;
inout zed_hdmi_iic_sda_io;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire hdmio_io_clk;
wire [15:0]hdmio_io_data;
wire hdmio_io_de;
wire hdmio_io_hsync;
wire hdmio_io_spdif;
wire hdmio_io_vsync;
wire zed_hdmi_iic_scl_i;
wire zed_hdmi_iic_scl_io;
wire zed_hdmi_iic_scl_o;
wire zed_hdmi_iic_scl_t;
wire zed_hdmi_iic_sda_i;
wire zed_hdmi_iic_sda_io;
wire zed_hdmi_iic_sda_o;
wire zed_hdmi_iic_sda_t;
tutorial tutorial_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.hdmio_io_clk(hdmio_io_clk),
.hdmio_io_data(hdmio_io_data),
.hdmio_io_de(hdmio_io_de),
.hdmio_io_hsync(hdmio_io_hsync),
.hdmio_io_spdif(hdmio_io_spdif),
.hdmio_io_vsync(hdmio_io_vsync),
.zed_hdmi_iic_scl_i(zed_hdmi_iic_scl_i),
.zed_hdmi_iic_scl_o(zed_hdmi_iic_scl_o),
.zed_hdmi_iic_scl_t(zed_hdmi_iic_scl_t),
.zed_hdmi_iic_sda_i(zed_hdmi_iic_sda_i),
.zed_hdmi_iic_sda_o(zed_hdmi_iic_sda_o),
.zed_hdmi_iic_sda_t(zed_hdmi_iic_sda_t));
IOBUF zed_hdmi_iic_scl_iobuf
(.I(zed_hdmi_iic_scl_o),
.IO(zed_hdmi_iic_scl_io),
.O(zed_hdmi_iic_scl_i),
.T(zed_hdmi_iic_scl_t));
IOBUF zed_hdmi_iic_sda_iobuf
(.I(zed_hdmi_iic_sda_o),
.IO(zed_hdmi_iic_sda_io),
.O(zed_hdmi_iic_sda_i),
.T(zed_hdmi_iic_sda_t));
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:12.0
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fifo_async_104x32 (
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
dout,
full,
almost_full,
empty,
valid,
prog_full
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
input wire wr_clk;
input wire wr_rst;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
input wire rd_clk;
input wire rd_rst;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [103 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [103 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE ALMOST_FULL" *)
output wire almost_full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire valid;
output wire prog_full;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(104),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(104),
.C_ENABLE_RLOCS(0),
.C_FAMILY("zynq"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(1),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(1),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(16),
.C_PROG_FULL_THRESH_NEGATE_VAL(15),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(0),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(1'D0),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(wr_rst),
.rd_clk(rd_clk),
.rd_rst(rd_rst),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(5'B0),
.prog_empty_thresh_assert(5'B0),
.prog_empty_thresh_negate(5'B0),
.prog_full_thresh(5'B0),
.prog_full_thresh_assert(5'B0),
.prog_full_thresh_negate(5'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(almost_full),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(valid),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(prog_full),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:31:56 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, ADD_OVRFLW_NRM,
left_right_SHT2, bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563,
n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574,
n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585,
n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596,
n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618,
n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695,
n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706,
n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717,
n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728,
n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750,
n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761,
n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772,
n773, n774, n775, n776, n778, n779, n781, n782, n784, n785, n787,
n788, n790, n791, n793, n794, n796, n797, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858,
n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869,
n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880,
n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891,
n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, DP_OP_15J131_122_6956_n18,
DP_OP_15J131_122_6956_n17, DP_OP_15J131_122_6956_n16,
DP_OP_15J131_122_6956_n15, DP_OP_15J131_122_6956_n14,
DP_OP_15J131_122_6956_n8, DP_OP_15J131_122_6956_n7,
DP_OP_15J131_122_6956_n6, DP_OP_15J131_122_6956_n5,
DP_OP_15J131_122_6956_n4, DP_OP_15J131_122_6956_n3,
DP_OP_15J131_122_6956_n2, DP_OP_15J131_122_6956_n1, sub_x_5_n131,
n955, n956, n957, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329,
n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349,
n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359,
n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429,
n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459,
n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489,
n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499,
n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971,
n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981,
n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991,
n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001,
n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011,
n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021,
n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031,
n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041,
n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051,
n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061,
n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071,
n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081,
n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091,
n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [7:0] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:1] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n947), .CK(clk), .RN(n2081), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRXLTS inst_ShiftRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n2081), .Q(
Shift_reg_FLAGS_7[1]), .QN(n959) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n911), .CK(clk), .RN(n2085), .Q(
intAS) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n846), .CK(clk), .RN(n2091),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n845), .CK(clk), .RN(n2091),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n844), .CK(clk), .RN(n2091),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n843), .CK(clk), .RN(n2091),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n842), .CK(clk), .RN(n2092),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n833), .CK(clk), .RN(n2092), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n832), .CK(clk), .RN(n2092), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n831), .CK(clk), .RN(n2092), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n830), .CK(clk), .RN(n2092), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n829), .CK(clk), .RN(n2092), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n828), .CK(clk), .RN(n2092), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n827), .CK(clk), .RN(n2092), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n826), .CK(clk), .RN(n2092), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n825), .CK(clk), .RN(n2092), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n824), .CK(clk), .RN(n1155), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n823), .CK(clk), .RN(n2094), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n822), .CK(clk), .RN(n1156), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n821), .CK(clk), .RN(n1158), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n820), .CK(clk), .RN(n2096), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n819), .CK(clk), .RN(n2095), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n818), .CK(clk), .RN(n2093), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n817), .CK(clk), .RN(n2100), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n816), .CK(clk), .RN(n2099), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n815), .CK(clk), .RN(n1157), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n814), .CK(clk), .RN(n2096), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n813), .CK(clk), .RN(n2095), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n812), .CK(clk), .RN(n2093), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n811), .CK(clk), .RN(n2100), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n805), .CK(clk), .RN(n2099), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n804), .CK(clk), .RN(n1155), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n803), .CK(clk), .RN(n2094), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n802), .CK(clk), .RN(n1156), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n801), .CK(clk), .RN(n1158), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n800), .CK(clk), .RN(n2096), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n799), .CK(clk), .RN(n2095), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n2080), .CK(clk), .RN(n2119), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n796), .CK(clk), .RN(n2093), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n2079), .CK(clk), .RN(n2119), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n793), .CK(clk), .RN(n2100), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n2078), .CK(clk), .RN(n2119), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n790), .CK(clk), .RN(n2099), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n2077), .CK(clk), .RN(n2119), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n787), .CK(clk), .RN(n1157), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n2076), .CK(clk), .RN(n2120), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n784), .CK(clk), .RN(n1155), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n2075), .CK(clk), .RN(n2120), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n781), .CK(clk), .RN(n2094), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n2074), .CK(clk), .RN(n2120), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1156), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n2073), .CK(clk), .RN(n2120), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n775), .CK(clk), .RN(n1158), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n774), .CK(clk), .RN(n2096), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n772), .CK(clk), .RN(n2095), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n771), .CK(clk), .RN(n2093), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n769), .CK(clk), .RN(n2100), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n768), .CK(clk), .RN(n2099), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n766), .CK(clk), .RN(n1157), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n765), .CK(clk), .RN(n2097), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n763), .CK(clk), .RN(n2097), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n762), .CK(clk), .RN(n2097), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n760), .CK(clk), .RN(n2097), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n759), .CK(clk), .RN(n2097), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n757), .CK(clk), .RN(n2097), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n756), .CK(clk), .RN(n2097), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n754), .CK(clk), .RN(n2097), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n753), .CK(clk), .RN(n2097), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n751), .CK(clk), .RN(n2097), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n750), .CK(clk), .RN(n2098), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n748), .CK(clk), .RN(n2098), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n747), .CK(clk), .RN(n2098), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n745), .CK(clk), .RN(n2098), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n744), .CK(clk), .RN(n2098), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n742), .CK(clk), .RN(n2098), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n741), .CK(clk), .RN(n2098), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n739), .CK(clk), .RN(n2098), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n738), .CK(clk), .RN(n2098), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n736), .CK(clk), .RN(n2098), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n735), .CK(clk), .RN(n2094), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n733), .CK(clk), .RN(n1155), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n732), .CK(clk), .RN(n1156), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1158), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n729), .CK(clk), .RN(n2096), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n728), .CK(clk), .RN(n2095), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n727), .CK(clk), .RN(n2093), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n725), .CK(clk), .RN(n2100), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n724), .CK(clk), .RN(n2099), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n723), .CK(clk), .RN(n1157), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n2094), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n720), .CK(clk), .RN(n1155), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n1156), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n718), .CK(clk), .RN(n1158), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n717), .CK(clk), .RN(n2096), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n715), .CK(clk), .RN(n2095), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n714), .CK(clk), .RN(n2093), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n713), .CK(clk), .RN(n2100), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n712), .CK(clk), .RN(n2099), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n710), .CK(clk), .RN(n1157), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n2101), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n708), .CK(clk), .RN(n2101), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n2101), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n705), .CK(clk), .RN(n2101), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n704), .CK(clk), .RN(n2101), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n703), .CK(clk), .RN(n2101), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n2101), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n700), .CK(clk), .RN(n2101), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n699), .CK(clk), .RN(n2101), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n698), .CK(clk), .RN(n2101), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n697), .CK(clk), .RN(n2102), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n695), .CK(clk), .RN(n2102), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n694), .CK(clk), .RN(n2102), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n693), .CK(clk), .RN(n2102), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n692), .CK(clk), .RN(n2102), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n690), .CK(clk), .RN(n2102), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n689), .CK(clk), .RN(n2102), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n688), .CK(clk), .RN(n2102), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n687), .CK(clk), .RN(n2102), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n686), .CK(clk), .RN(n2102), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n685), .CK(clk), .RN(n2103), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n684), .CK(clk), .RN(n2103), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n683), .CK(clk), .RN(n2103), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n682), .CK(clk), .RN(n2103), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n681), .CK(clk), .RN(n2103), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n680), .CK(clk), .RN(n2103), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n679), .CK(clk), .RN(n2103), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n2103), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n677), .CK(clk), .RN(n2103), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n676), .CK(clk), .RN(n2103), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n675), .CK(clk), .RN(n2104), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n674), .CK(clk), .RN(n2104), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n673), .CK(clk), .RN(n2104), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n672), .CK(clk), .RN(n2104), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n671), .CK(clk), .RN(n2104), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n670), .CK(clk), .RN(n2104), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n669), .CK(clk), .RN(n2104), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n668), .CK(clk), .RN(n2104), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n667), .CK(clk), .RN(n2104), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n666), .CK(clk), .RN(n2104), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n665), .CK(clk), .RN(n2105), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n664), .CK(clk), .RN(n2105), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n663), .CK(clk), .RN(n2105), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n662), .CK(clk), .RN(n2105), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n661), .CK(clk), .RN(n2105), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n660), .CK(clk), .RN(n2105), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n659), .CK(clk), .RN(n2105), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n658), .CK(clk), .RN(n2105), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n657), .CK(clk), .RN(n2105), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n656), .CK(clk), .RN(n2105), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n655), .CK(clk), .RN(n2106), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n654), .CK(clk), .RN(n2106), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n653), .CK(clk), .RN(n2106), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n652), .CK(clk), .RN(n2106), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n651), .CK(clk), .RN(n2106), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n650), .CK(clk), .RN(n2106), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n649), .CK(clk), .RN(n2106), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n648), .CK(clk), .RN(n2106), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n647), .CK(clk), .RN(n2106), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n646), .CK(clk), .RN(n2106), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n645), .CK(clk), .RN(n2107), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n637), .CK(clk), .RN(n2107), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n636), .CK(clk), .RN(n2107), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n635), .CK(clk), .RN(n2107), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n634), .CK(clk), .RN(n2108), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n633), .CK(clk), .RN(n2108), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n631), .CK(clk), .RN(n2108), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n630), .CK(clk), .RN(n2108), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n626), .CK(clk), .RN(n2108), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n625), .CK(clk), .RN(n2108), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n624), .CK(clk), .RN(n2108), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n623), .CK(clk), .RN(n2108), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n622), .CK(clk), .RN(n2108), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n594), .CK(clk), .RN(n2112), .Q(
LZD_output_NRM2_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n592), .CK(clk), .RN(n2112), .Q(
LZD_output_NRM2_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n590), .CK(clk), .RN(n2112), .Q(
LZD_output_NRM2_EW[4]) );
CMPR32X2TS DP_OP_15J131_122_6956_U9 ( .A(DMP_exp_NRM2_EW[0]), .B(n1997), .C(
DP_OP_15J131_122_6956_n18), .CO(DP_OP_15J131_122_6956_n8), .S(
exp_rslt_NRM2_EW1[0]) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n2085),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n632), .CK(clk), .RN(n2108), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n2109), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n2109), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n587), .CK(clk), .RN(n2109), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n2109), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n585), .CK(clk), .RN(n2109), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n2109), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n583), .CK(clk), .RN(n2109), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n582), .CK(clk), .RN(n2109), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n581), .CK(clk), .RN(n2109), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n580), .CK(clk), .RN(n2109), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n579), .CK(clk), .RN(n2110), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n578), .CK(clk), .RN(n2110), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n577), .CK(clk), .RN(n2110), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n576), .CK(clk), .RN(n2110), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n575), .CK(clk), .RN(n2110), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n574), .CK(clk), .RN(n2110), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n573), .CK(clk), .RN(n2110), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n572), .CK(clk), .RN(n2110), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n571), .CK(clk), .RN(n2110), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n570), .CK(clk), .RN(n2110), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n2111), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n2111), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n567), .CK(clk), .RN(n2111), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n639), .CK(clk), .RN(n2107), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n638), .CK(clk), .RN(n2111), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n834), .CK(clk), .RN(n2111), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n621), .CK(clk), .RN(n2111), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n841), .CK(clk), .RN(n2112), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n840), .CK(clk), .RN(n2112), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n839), .CK(clk), .RN(n2112), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n838), .CK(clk), .RN(n2111), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n837), .CK(clk), .RN(n2111), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n836), .CK(clk), .RN(n2111), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n835), .CK(clk), .RN(n2111), .Q(
final_result_ieee[29]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n928), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[15]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n794), .CK(clk), .RN(n2119), .Q(
DMP_SFG[1]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n2081), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1982) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n944), .CK(clk), .RN(n2081), .Q(
Shift_reg_FLAGS_7[0]), .QN(n2040) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n605), .CK(clk), .RN(n2116), .Q(
Raw_mant_NRM_SWR[15]), .QN(n2072) );
DFFRX2TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n878), .CK(clk), .RN(n2088), .Q(
bit_shift_SHT2), .QN(n2006) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n915), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[28]), .QN(n2033) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n919), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[24]), .QN(n2041) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n917), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[26]), .QN(n1993) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n918), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[25]), .QN(n1992) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n896), .CK(clk), .RN(n2086),
.Q(intDY_EWSW[14]), .QN(n2028) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n897), .CK(clk), .RN(n2086),
.Q(intDY_EWSW[13]), .QN(n2022) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n898), .CK(clk), .RN(n2086),
.Q(intDY_EWSW[12]), .QN(n2027) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n893), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[17]), .QN(n2020) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n895), .CK(clk), .RN(n2086),
.Q(intDY_EWSW[15]), .QN(n1985) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n899), .CK(clk), .RN(n2086),
.Q(intDY_EWSW[11]), .QN(n2009) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n902), .CK(clk), .RN(n2086), .Q(
intDY_EWSW[8]), .QN(n2024) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n907), .CK(clk), .RN(n2085), .Q(
intDY_EWSW[3]), .QN(n2019) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n850), .CK(clk), .RN(n2088), .Q(
shift_value_SHT2_EWR[2]), .QN(n2005) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n887), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[23]), .QN(n2035) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n888), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[22]), .QN(n1986) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n889), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[21]), .QN(n2023) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n890), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[20]), .QN(n2030) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n884), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[26]), .QN(n2017) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n885), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[25]), .QN(n2018) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n892), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[18]), .QN(n2034) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n927), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[16]), .QN(n2003) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n936), .CK(clk), .RN(n2082), .Q(
intDX_EWSW[7]), .QN(n2000) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n937), .CK(clk), .RN(n2082), .Q(
intDX_EWSW[6]), .QN(n1978) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n938), .CK(clk), .RN(n2082), .Q(
intDX_EWSW[5]), .QN(n1999) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n939), .CK(clk), .RN(n2082), .Q(
intDX_EWSW[4]), .QN(n1974) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n607), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[13]), .QN(n2045) );
DFFRX2TS inst_ShiftRegister_Q_reg_6_ ( .D(n950), .CK(clk), .RN(n2081), .Q(
Shift_reg_FLAGS_7_6), .QN(n1991) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n609), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1994) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n608), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[12]), .QN(n2044) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n599), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[21]), .QN(n2016) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n617), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[3]), .QN(n2004) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n615), .CK(clk), .RN(n2113), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1975) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n849), .CK(clk), .RN(n2088), .Q(
shift_value_SHT2_EWR[3]), .QN(n1977) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n909), .CK(clk), .RN(n2085), .Q(
intDY_EWSW[1]), .QN(n2124) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n555), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[11]), .QN(n2069) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n628), .CK(clk), .RN(n2116), .Q(
ADD_OVRFLW_NRM), .QN(n2015) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n565), .CK(clk), .RN(n2116), .Q(
DmP_mant_SFG_SWR[1]), .QN(n1995) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n544), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[22]), .QN(n2064) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n891), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[19]), .QN(n1988) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n810), .CK(clk), .RN(n1157), .Q(
DMP_EXP_EWSW[23]), .QN(n2036) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n940), .CK(clk), .RN(n2082), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n920), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n922), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n930), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n935), .CK(clk), .RN(n2082), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n926), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n932), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n929), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n934), .CK(clk), .RN(n2082), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n916), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[27]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n952), .CK(clk), .RN(
n2081), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n925), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n943), .CK(clk), .RN(n2081), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n924), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n613), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[7]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n948), .CK(clk), .RN(n2081), .Q(
busy), .QN(n2123) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n767), .CK(clk), .RN(n2120), .Q(
DMP_SFG[10]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n875), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[24]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n869), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n863), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[12]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n864), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[13]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n734), .CK(clk), .RN(n2122), .Q(
DMP_SFG[21]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n740), .CK(clk), .RN(n2121), .Q(
DMP_SFG[19]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n746), .CK(clk), .RN(n2121), .Q(
DMP_SFG[17]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n752), .CK(clk), .RN(n2121), .Q(
DMP_SFG[15]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n758), .CK(clk), .RN(n2121), .Q(
DMP_SFG[13]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n764), .CK(clk), .RN(n2121), .Q(
DMP_SFG[11]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n618), .CK(clk), .RN(n2113), .Q(
Raw_mant_NRM_SWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n868), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[17]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n743), .CK(clk), .RN(n2121), .Q(
DMP_SFG[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n749), .CK(clk), .RN(n2121), .Q(
DMP_SFG[16]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n755), .CK(clk), .RN(n2121), .Q(
DMP_SFG[14]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n761), .CK(clk), .RN(n2121), .Q(
DMP_SFG[12]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n2122), .Q(
DMP_SFG[22]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n737), .CK(clk), .RN(n2121), .Q(
DMP_SFG[20]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n859), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[8]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n912), .CK(clk), .RN(n2085),
.Q(intDX_EWSW[31]) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n877), .CK(clk), .RN(n2088), .Q(
left_right_SHT2), .QN(n961) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n701), .CK(clk), .RN(n2113), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n711), .CK(clk), .RN(n2113), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n858), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[7]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n644), .CK(clk), .RN(n2107), .Q(
DmP_EXP_EWSW[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n610), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[10]) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n629), .CK(clk), .RN(n2116), .Q(
OP_FLAG_SFG) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n691), .CK(clk), .RN(n2113), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n776), .CK(clk), .RN(n2120), .Q(
DMP_SFG[7]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n779), .CK(clk), .RN(n2120), .Q(
DMP_SFG[6]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n788), .CK(clk), .RN(n2119), .Q(
DMP_SFG[3]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n791), .CK(clk), .RN(n2119), .Q(
DMP_SFG[2]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n773), .CK(clk), .RN(n2120), .Q(
DMP_SFG[8]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n782), .CK(clk), .RN(n2120), .Q(
DMP_SFG[5]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n785), .CK(clk), .RN(n2119), .Q(
DMP_SFG[4]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n797), .CK(clk), .RN(n2119), .Q(
DMP_SFG[0]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n770), .CK(clk), .RN(n2120), .Q(
DMP_SFG[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n872), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[21]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n721), .CK(clk), .RN(n2113), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n696), .CK(clk), .RN(n2113), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n2113), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n716), .CK(clk), .RN(n2113), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n726), .CK(clk), .RN(n2112), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n641), .CK(clk), .RN(n2107), .Q(
DmP_EXP_EWSW[26]), .QN(n963) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n854), .CK(clk), .RN(n2091), .Q(
Data_array_SWR[3]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n879), .CK(clk), .RN(n2088),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n942), .CK(clk), .RN(n2082), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n931), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n923), .CK(clk), .RN(n2083),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n921), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n941), .CK(clk), .RN(n2082), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n933), .CK(clk), .RN(n2082),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n882), .CK(clk), .RN(n2088),
.Q(intDY_EWSW[28]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n808), .CK(clk), .RN(n1158), .Q(
DMP_EXP_EWSW[25]), .QN(n994) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n806), .CK(clk), .RN(n1156), .Q(
DMP_EXP_EWSW[27]) );
DFFRX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n2112), .Q(
ADD_OVRFLW_NRM2), .QN(n1997) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n640), .CK(clk), .RN(n2107), .Q(
DmP_EXP_EWSW[27]) );
ADDFHX2TS DP_OP_15J131_122_6956_U8 ( .A(DP_OP_15J131_122_6956_n17), .B(
DMP_exp_NRM2_EW[1]), .CI(DP_OP_15J131_122_6956_n8), .CO(
DP_OP_15J131_122_6956_n7), .S(exp_rslt_NRM2_EW1[1]) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n847), .CK(clk), .RN(n2091), .Q(
shift_value_SHT2_EWR[4]), .QN(n1979) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n603), .CK(clk), .RN(n2116), .Q(
Raw_mant_NRM_SWR[17]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n601), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n600), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n596), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n2112), .Q(
LZD_output_NRM2_EW[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n558), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[8]), .QN(n2048) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n557), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[9]), .QN(n2058) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n559), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[7]), .QN(n2059) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n560), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[6]), .QN(n2049) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n561), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[5]), .QN(n2060) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n562), .CK(clk), .RN(n2116), .Q(
DmP_mant_SFG_SWR[4]), .QN(n2050) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n563), .CK(clk), .RN(n2116), .Q(
DmP_mant_SFG_SWR[3]), .QN(n2061) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n564), .CK(clk), .RN(n2116), .Q(
DmP_mant_SFG_SWR[2]), .QN(n2062) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n807), .CK(clk), .RN(n1155), .Q(
DMP_EXP_EWSW[26]), .QN(n2042) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n642), .CK(clk), .RN(n2107), .Q(
DmP_EXP_EWSW[25]), .QN(n2043) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n620), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[0]), .QN(n2046) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n951), .CK(clk), .RN(
n2081), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2012) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n619), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1980) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n616), .CK(clk), .RN(n2113), .Q(
Raw_mant_NRM_SWR[4]), .QN(n2008) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n614), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1998) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n606), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1996) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n552), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[14]), .QN(n2068) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n551), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[15]), .QN(n2055) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n556), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[10]), .QN(n2047) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n612), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1976) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n881), .CK(clk), .RN(n2088),
.Q(intDY_EWSW[29]), .QN(n2007) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n880), .CK(clk), .RN(n2088),
.Q(intDY_EWSW[30]), .QN(n1981) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n553), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[13]), .QN(n2056) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n554), .CK(clk), .RN(n2117), .Q(
DmP_mant_SFG_SWR[12]), .QN(n2057) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n549), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[17]), .QN(n2054) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n550), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[16]), .QN(n2067) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n547), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[19]), .QN(n2053) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n548), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[18]), .QN(n2066) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n546), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[20]), .QN(n2065) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n545), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[21]), .QN(n2052) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n611), .CK(clk), .RN(n2114), .Q(
Raw_mant_NRM_SWR[9]), .QN(n2001) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n542), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[24]), .QN(n2063) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n543), .CK(clk), .RN(n2118), .Q(
DmP_mant_SFG_SWR[23]), .QN(n2051) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n900), .CK(clk), .RN(n2086),
.Q(intDY_EWSW[10]), .QN(n2002) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n910), .CK(clk), .RN(n2085), .Q(
intDY_EWSW[0]), .QN(n1984) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n901), .CK(clk), .RN(n2086), .Q(
intDY_EWSW[9]), .QN(n2021) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n908), .CK(clk), .RN(n2085), .Q(
intDY_EWSW[2]), .QN(n2025) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n894), .CK(clk), .RN(n2086),
.Q(intDY_EWSW[16]), .QN(n2029) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n904), .CK(clk), .RN(n2085), .Q(
intDY_EWSW[6]), .QN(n2010) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n913), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[30]), .QN(n1987) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n914), .CK(clk), .RN(n2084),
.Q(intDX_EWSW[29]), .QN(n2032) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n906), .CK(clk), .RN(n2085), .Q(
intDY_EWSW[4]), .QN(n2026) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n903), .CK(clk), .RN(n2086), .Q(
intDY_EWSW[7]), .QN(n2011) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n905), .CK(clk), .RN(n2085), .Q(
intDY_EWSW[5]), .QN(n1983) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n602), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[18]), .QN(n2013) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n883), .CK(clk), .RN(n2088),
.Q(intDY_EWSW[27]), .QN(n2031) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n886), .CK(clk), .RN(n2087),
.Q(intDY_EWSW[24]), .QN(n1972) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n876), .CK(clk), .RN(n2088), .Q(
Data_array_SWR[25]), .QN(n2039) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n873), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[22]), .QN(n2037) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n809), .CK(clk), .RN(n2094), .Q(
DMP_EXP_EWSW[24]), .QN(n1990) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n2107), .Q(
DmP_EXP_EWSW[24]), .QN(n1989) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n874), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[23]), .QN(n2038) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n866), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n865), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n867), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n871), .CK(clk), .RN(n2089), .Q(
Data_array_SWR[20]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n862), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[11]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n861), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[10]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n860), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[9]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n857), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n855), .CK(clk), .RN(n2091), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n853), .CK(clk), .RN(n2091), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n852), .CK(clk), .RN(n2091), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n851), .CK(clk), .RN(n2091), .Q(
Data_array_SWR[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n2112), .Q(
LZD_output_NRM2_EW[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n595), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n604), .CK(clk), .RN(n2116), .Q(
Raw_mant_NRM_SWR[16]), .QN(n2014) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n598), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n597), .CK(clk), .RN(n2115), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n541), .CK(clk), .RN(n2119), .Q(
DmP_mant_SFG_SWR[25]), .QN(n2070) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n566), .CK(clk), .RN(n2116), .QN(
sub_x_5_n131) );
CMPR32X2TS DP_OP_15J131_122_6956_U7 ( .A(DP_OP_15J131_122_6956_n16), .B(
DMP_exp_NRM2_EW[2]), .C(DP_OP_15J131_122_6956_n7), .CO(
DP_OP_15J131_122_6956_n6), .S(exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J131_122_6956_U6 ( .A(DP_OP_15J131_122_6956_n15), .B(
DMP_exp_NRM2_EW[3]), .C(DP_OP_15J131_122_6956_n6), .CO(
DP_OP_15J131_122_6956_n5), .S(exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_15J131_122_6956_U5 ( .A(DP_OP_15J131_122_6956_n14), .B(
DMP_exp_NRM2_EW[4]), .C(DP_OP_15J131_122_6956_n5), .CO(
DP_OP_15J131_122_6956_n4), .S(exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_15J131_122_6956_U4 ( .A(n1997), .B(DMP_exp_NRM2_EW[5]), .C(
DP_OP_15J131_122_6956_n4), .CO(DP_OP_15J131_122_6956_n3), .S(
exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_15J131_122_6956_U3 ( .A(n1997), .B(DMP_exp_NRM2_EW[6]), .C(
DP_OP_15J131_122_6956_n3), .CO(DP_OP_15J131_122_6956_n2), .S(
exp_rslt_NRM2_EW1[6]) );
DFFRX2TS inst_ShiftRegister_Q_reg_2_ ( .D(n946), .CK(clk), .RN(n2122), .Q(
Shift_reg_FLAGS_7[2]), .QN(n996) );
CMPR32X2TS DP_OP_15J131_122_6956_U2 ( .A(n1997), .B(DMP_exp_NRM2_EW[7]), .C(
DP_OP_15J131_122_6956_n2), .CO(DP_OP_15J131_122_6956_n1), .S(
exp_rslt_NRM2_EW1[7]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n856), .CK(clk), .RN(n2090), .Q(
Data_array_SWR[5]) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n949), .CK(clk), .RN(n2081), .Q(
n1973), .QN(n2071) );
INVX2TS U958 ( .A(n1308), .Y(n1321) );
BUFX3TS U959 ( .A(n1354), .Y(n972) );
CLKINVX6TS U960 ( .A(n989), .Y(n970) );
NOR2X4TS U961 ( .A(n1909), .B(n1561), .Y(n1354) );
NOR2X4TS U962 ( .A(n1134), .B(n1571), .Y(n1377) );
INVX4TS U963 ( .A(n1353), .Y(n1564) );
NOR2X4TS U964 ( .A(n1561), .B(n1569), .Y(n1520) );
NAND2X1TS U965 ( .A(n1133), .B(n1132), .Y(n1134) );
OAI21X2TS U966 ( .A0(n1746), .A1(n1036), .B0(n1035), .Y(n1717) );
OR3X1TS U967 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[4]), .C(
n1977), .Y(n960) );
CLKBUFX2TS U968 ( .A(Shift_reg_FLAGS_7[2]), .Y(n974) );
NAND2X1TS U969 ( .A(n1118), .B(n1117), .Y(n1133) );
AOI211X1TS U970 ( .A0(n1292), .A1(Raw_mant_NRM_SWR[12]), .B0(n1346), .C0(
n1274), .Y(n1338) );
INVX2TS U971 ( .A(n992), .Y(n1472) );
INVX2TS U972 ( .A(n1941), .Y(n991) );
CLKINVX6TS U973 ( .A(n1278), .Y(n1304) );
BUFX3TS U974 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1941) );
NOR2X2TS U975 ( .A(n1272), .B(Raw_mant_NRM_SWR[15]), .Y(n1287) );
INVX2TS U976 ( .A(n1973), .Y(n955) );
INVX2TS U977 ( .A(n955), .Y(n956) );
INVX2TS U978 ( .A(n955), .Y(n957) );
OAI21XLTS U979 ( .A0(intDX_EWSW[3]), .A1(n2019), .B0(intDX_EWSW[2]), .Y(
n1087) );
OAI211XLTS U980 ( .A0(n2019), .A1(intDX_EWSW[3]), .B0(n1086), .C0(n1085),
.Y(n1089) );
NOR2XLTS U981 ( .A(n1102), .B(intDY_EWSW[16]), .Y(n1103) );
OAI21XLTS U982 ( .A0(intDX_EWSW[23]), .A1(n2035), .B0(intDX_EWSW[22]), .Y(
n1108) );
NOR2XLTS U983 ( .A(exp_rslt_NRM2_EW1[0]), .B(exp_rslt_NRM2_EW1[1]), .Y(n1148) );
NOR2XLTS U984 ( .A(n2056), .B(DMP_SFG[11]), .Y(n1020) );
OAI21X2TS U985 ( .A0(n1729), .A1(n1723), .B0(n1724), .Y(n1738) );
NAND2X1TS U986 ( .A(n991), .B(DmP_mant_SHT1_SW[3]), .Y(n1405) );
NAND2X1TS U987 ( .A(n991), .B(DmP_mant_SHT1_SW[5]), .Y(n1420) );
INVX2TS U988 ( .A(n1561), .Y(n1398) );
NOR2BX1TS U989 ( .AN(n1151), .B(exp_rslt_NRM2_EW1[7]), .Y(n1152) );
NOR2XLTS U990 ( .A(n1231), .B(n1632), .Y(n1233) );
NOR2XLTS U991 ( .A(n1231), .B(n1659), .Y(n1661) );
OAI21XLTS U992 ( .A0(n1650), .A1(n1144), .B0(n1145), .Y(n1616) );
AND2X2TS U993 ( .A(beg_OP), .B(n1892), .Y(n1895) );
INVX2TS U994 ( .A(exp_rslt_NRM2_EW1[6]), .Y(n1310) );
NOR2XLTS U995 ( .A(n1581), .B(SIGN_FLAG_SHT1SHT2), .Y(n1583) );
INVX2TS U996 ( .A(n1377), .Y(n1556) );
OAI211XLTS U997 ( .A0(n1434), .A1(n1564), .B0(n1427), .C0(n1426), .Y(n858)
);
OAI211XLTS U998 ( .A0(n1448), .A1(n1562), .B0(n1447), .C0(n1446), .Y(n859)
);
OAI21XLTS U999 ( .A0(n1283), .A1(n1153), .B0(n1281), .Y(n850) );
OAI211XLTS U1000 ( .A0(n1322), .A1(n1969), .B0(n1321), .C0(n1320), .Y(n839)
);
OAI21XLTS U1001 ( .A0(n2034), .A1(n1388), .B0(n1378), .Y(n654) );
OAI21XLTS U1002 ( .A0(n1983), .A1(n1391), .B0(n1358), .Y(n680) );
INVX2TS U1003 ( .A(n1399), .Y(n989) );
INVX2TS U1004 ( .A(n1354), .Y(n1562) );
INVX2TS U1005 ( .A(n990), .Y(n1523) );
CLKINVX6TS U1006 ( .A(n987), .Y(n988) );
INVX8TS U1007 ( .A(n987), .Y(n969) );
INVX2TS U1008 ( .A(n1520), .Y(n987) );
NOR2X2TS U1009 ( .A(n1398), .B(n1569), .Y(n1399) );
INVX4TS U1010 ( .A(n1530), .Y(n1930) );
CLKINVX2TS U1011 ( .A(n1942), .Y(n1581) );
INVX4TS U1012 ( .A(n1514), .Y(n1931) );
NOR2X2TS U1013 ( .A(n1942), .B(n1582), .Y(n1308) );
AND2X4TS U1014 ( .A(Shift_reg_FLAGS_7_6), .B(n1134), .Y(n1362) );
NAND3X1TS U1015 ( .A(Raw_mant_NRM_SWR[8]), .B(n1336), .C(n2001), .Y(n1337)
);
NOR2X1TS U1016 ( .A(Raw_mant_NRM_SWR[12]), .B(n1345), .Y(n1348) );
INVX6TS U1017 ( .A(n1292), .Y(n1345) );
NOR2X6TS U1018 ( .A(Raw_mant_NRM_SWR[13]), .B(n1275), .Y(n1292) );
AOI211X2TS U1019 ( .A0(Data_array_SWR[25]), .A1(n1595), .B0(n1594), .C0(
n1593), .Y(n1638) );
INVX4TS U1020 ( .A(n986), .Y(n1662) );
NAND2XLTS U1021 ( .A(n991), .B(DmP_mant_SHT1_SW[1]), .Y(n1402) );
NOR2X1TS U1022 ( .A(n1328), .B(Raw_mant_NRM_SWR[25]), .Y(n1334) );
OR2X2TS U1023 ( .A(shift_value_SHT2_EWR[4]), .B(n1606), .Y(n1141) );
NOR2X1TS U1024 ( .A(n1064), .B(intDY_EWSW[10]), .Y(n1065) );
INVX2TS U1025 ( .A(n1298), .Y(n1289) );
OAI211X1TS U1026 ( .A0(n1434), .A1(n973), .B0(n1433), .C0(n1432), .Y(n857)
);
OAI211X1TS U1027 ( .A0(n1412), .A1(n1564), .B0(n1411), .C0(n1410), .Y(n854)
);
OAI211X1TS U1028 ( .A0(n1440), .A1(n975), .B0(n1430), .C0(n1429), .Y(n856)
);
OAI211X1TS U1029 ( .A0(n1485), .A1(n1564), .B0(n1475), .C0(n1474), .Y(n868)
);
OAI211X1TS U1030 ( .A0(n1565), .A1(n1562), .B0(n1401), .C0(n1400), .Y(n873)
);
OAI211X1TS U1031 ( .A0(n1456), .A1(n973), .B0(n1455), .C0(n1454), .Y(n861)
);
OAI211X1TS U1032 ( .A0(n1502), .A1(n973), .B0(n1501), .C0(n1500), .Y(n865)
);
OAI211X1TS U1033 ( .A0(n1440), .A1(n973), .B0(n1439), .C0(n1438), .Y(n855)
);
OAI211X1TS U1034 ( .A0(n1480), .A1(n1564), .B0(n1479), .C0(n1478), .Y(n872)
);
OAI211X1TS U1035 ( .A0(n1494), .A1(n1562), .B0(n1493), .C0(n1492), .Y(n869)
);
OAI211X1TS U1036 ( .A0(n1448), .A1(n975), .B0(n1443), .C0(n1442), .Y(n860)
);
OAI211X1TS U1037 ( .A0(n1524), .A1(n1564), .B0(n1419), .C0(n1418), .Y(n853)
);
OAI211X1TS U1038 ( .A0(n1480), .A1(n973), .B0(n1463), .C0(n1462), .Y(n871)
);
OAI211X1TS U1039 ( .A0(n1456), .A1(n975), .B0(n1451), .C0(n1450), .Y(n862)
);
OAI211X1TS U1040 ( .A0(n1494), .A1(n1564), .B0(n1489), .C0(n1488), .Y(n870)
);
OAI211X1TS U1041 ( .A0(n1513), .A1(n1562), .B0(n1505), .C0(n1504), .Y(n863)
);
AOI22X1TS U1042 ( .A0(n1507), .A1(Data_array_SWR[15]), .B0(n990), .B1(n1499),
.Y(n1498) );
OAI21X1TS U1043 ( .A0(n1910), .A1(n1569), .B0(n1568), .Y(n874) );
OAI21X1TS U1044 ( .A0(n1563), .A1(n975), .B0(n1356), .Y(n875) );
OAI2BB1X1TS U1045 ( .A0N(n1752), .A1N(n1062), .B0(n1061), .Y(n595) );
AO22X1TS U1046 ( .A0(n1138), .A1(n1194), .B0(ADD_OVRFLW_NRM), .B1(n1935),
.Y(n628) );
OAI21X1TS U1047 ( .A0(n1307), .A1(n1890), .B0(n1305), .Y(n590) );
OAI21X1TS U1048 ( .A0(n1307), .A1(n1461), .B0(n1306), .Y(n847) );
OAI21X1TS U1049 ( .A0(n1295), .A1(n1890), .B0(n1293), .Y(n594) );
OAI21X1TS U1050 ( .A0(n1472), .A1(n1283), .B0(n1282), .Y(n592) );
OAI21X1TS U1051 ( .A0(n1295), .A1(n1153), .B0(n1294), .Y(n849) );
OAI21X1TS U1052 ( .A0(n2124), .A1(n1931), .B0(n1558), .Y(n832) );
OAI211X1TS U1053 ( .A0(n1314), .A1(n1969), .B0(n1321), .C0(n1313), .Y(n841)
);
OAI21X1TS U1054 ( .A0(n2031), .A1(n1931), .B0(n1557), .Y(n806) );
OAI211X1TS U1055 ( .A0(n1576), .A1(n1969), .B0(n1321), .C0(n1319), .Y(n836)
);
OAI211X1TS U1056 ( .A0(n1310), .A1(n1969), .B0(n1321), .C0(n1309), .Y(n835)
);
OAI211X1TS U1057 ( .A0(n1316), .A1(n1969), .B0(n1321), .C0(n1315), .Y(n840)
);
OAI21X1TS U1058 ( .A0(n2002), .A1(n1543), .B0(n1534), .Y(n823) );
OAI211X1TS U1059 ( .A0(n1312), .A1(n1969), .B0(n1321), .C0(n1311), .Y(n837)
);
OAI21X1TS U1060 ( .A0(n1983), .A1(n1543), .B0(n1536), .Y(n828) );
OAI21X1TS U1061 ( .A0(n2025), .A1(n1556), .B0(n1555), .Y(n831) );
OAI21X1TS U1062 ( .A0(n2011), .A1(n1543), .B0(n1532), .Y(n826) );
OAI21X1TS U1063 ( .A0(n2010), .A1(n1543), .B0(n1537), .Y(n827) );
OAI21X1TS U1064 ( .A0(n2021), .A1(n1543), .B0(n1539), .Y(n824) );
OAI211X1TS U1065 ( .A0(n1318), .A1(n1969), .B0(n1321), .C0(n1317), .Y(n838)
);
OAI21X1TS U1066 ( .A0(n2033), .A1(n1930), .B0(n1361), .Y(n805) );
OAI21X1TS U1067 ( .A0(n1986), .A1(n1931), .B0(n1515), .Y(n811) );
OAI21X1TS U1068 ( .A0(n2023), .A1(n1547), .B0(n1528), .Y(n812) );
OAI21X1TS U1069 ( .A0(n1987), .A1(n1549), .B0(n1384), .Y(n803) );
OAI21X1TS U1070 ( .A0(n2032), .A1(n1549), .B0(n1385), .Y(n804) );
OAI21X1TS U1071 ( .A0(n2029), .A1(n1547), .B0(n1531), .Y(n817) );
OAI21X1TS U1072 ( .A0(n2034), .A1(n1547), .B0(n1525), .Y(n815) );
OAI21X1TS U1073 ( .A0(n2030), .A1(n1547), .B0(n1527), .Y(n813) );
OAI21X1TS U1074 ( .A0(n1984), .A1(n1547), .B0(n1529), .Y(n833) );
OAI21X1TS U1075 ( .A0(n1985), .A1(n1388), .B0(n1387), .Y(n660) );
OAI21X1TS U1076 ( .A0(n2010), .A1(n1391), .B0(n1366), .Y(n678) );
OAI21X1TS U1077 ( .A0(n1988), .A1(n1388), .B0(n1379), .Y(n652) );
OAI21X1TS U1078 ( .A0(n2026), .A1(n1391), .B0(n1389), .Y(n682) );
OAI21X1TS U1079 ( .A0(n2124), .A1(n1391), .B0(n1390), .Y(n688) );
OAI21X1TS U1080 ( .A0(n2029), .A1(n1388), .B0(n1367), .Y(n658) );
OAI21X1TS U1081 ( .A0(n2020), .A1(n1388), .B0(n1381), .Y(n656) );
OAI21X1TS U1082 ( .A0(n2023), .A1(n1930), .B0(n1386), .Y(n648) );
OAI21X1TS U1083 ( .A0(n1984), .A1(n1549), .B0(n1359), .Y(n690) );
OAI21X1TS U1084 ( .A0(n1986), .A1(n1930), .B0(n1380), .Y(n646) );
OAI21X1TS U1085 ( .A0(n2030), .A1(n1930), .B0(n1382), .Y(n650) );
OAI21X1TS U1086 ( .A0(n2019), .A1(n1391), .B0(n1357), .Y(n684) );
AOI21X2TS U1087 ( .A0(n1738), .A1(n1734), .B0(n1057), .Y(n1748) );
INVX2TS U1088 ( .A(n1377), .Y(n1543) );
OAI21X1TS U1089 ( .A0(n1553), .A1(n1571), .B0(n1549), .Y(n1551) );
NAND2X6TS U1090 ( .A(n1335), .B(n1998), .Y(n1278) );
BUFX3TS U1091 ( .A(n1377), .Y(n1514) );
BUFX4TS U1092 ( .A(n1362), .Y(n1530) );
NAND4BX1TS U1093 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1148), .C(n1318), .D(n1322), .Y(n1149) );
NOR2X1TS U1094 ( .A(n1231), .B(n1638), .Y(n1639) );
OAI21X1TS U1095 ( .A0(n1100), .A1(n1099), .B0(n1098), .Y(n1114) );
NOR2X1TS U1096 ( .A(n1332), .B(Raw_mant_NRM_SWR[17]), .Y(n1333) );
OAI21X1TS U1097 ( .A0(n1659), .A1(n1144), .B0(n1145), .Y(n1598) );
OAI21X1TS U1098 ( .A0(n1653), .A1(n1144), .B0(n1145), .Y(n1607) );
OAI21X1TS U1099 ( .A0(n1638), .A1(n1144), .B0(n1145), .Y(n1628) );
OAI21X1TS U1100 ( .A0(n1635), .A1(n1144), .B0(n1145), .Y(n1633) );
OAI21X1TS U1101 ( .A0(n1641), .A1(n1144), .B0(n1145), .Y(n1625) );
OAI21X1TS U1102 ( .A0(n1644), .A1(n1144), .B0(n1145), .Y(n1622) );
OAI21X1TS U1103 ( .A0(n1656), .A1(n1144), .B0(n1145), .Y(n1602) );
OAI21X1TS U1104 ( .A0(n1647), .A1(n1144), .B0(n1145), .Y(n1619) );
NOR2X4TS U1105 ( .A(n1875), .B(OP_FLAG_SFG), .Y(n1194) );
AO22XLTS U1106 ( .A0(n1903), .A1(add_subt), .B0(n1896), .B1(intAS), .Y(n911)
);
NOR2X1TS U1107 ( .A(n1231), .B(n1656), .Y(n1657) );
AO22XLTS U1108 ( .A0(n1905), .A1(Data_X[3]), .B0(n1893), .B1(intDX_EWSW[3]),
.Y(n940) );
NOR2X1TS U1109 ( .A(n1231), .B(n1641), .Y(n1642) );
NOR2X1TS U1110 ( .A(n1231), .B(n1644), .Y(n1645) );
NOR2X1TS U1111 ( .A(n1231), .B(n1653), .Y(n1654) );
NOR2X1TS U1112 ( .A(n1231), .B(n1650), .Y(n1651) );
NOR2X1TS U1113 ( .A(n1231), .B(n1635), .Y(n1636) );
AO22XLTS U1114 ( .A0(n1894), .A1(Data_X[15]), .B0(n1906), .B1(intDX_EWSW[15]), .Y(n928) );
NOR2X1TS U1115 ( .A(n1231), .B(n1647), .Y(n1648) );
INVX2TS U1116 ( .A(n1791), .Y(n1820) );
NAND2X4TS U1117 ( .A(n977), .B(n1662), .Y(n1144) );
NAND2X4TS U1118 ( .A(n1232), .B(n1662), .Y(n1145) );
AND2X2TS U1119 ( .A(n974), .B(OP_FLAG_SFG), .Y(n1753) );
INVX4TS U1120 ( .A(n1590), .Y(n1664) );
NAND2XLTS U1121 ( .A(n1392), .B(Raw_mant_NRM_SWR[23]), .Y(n1395) );
CLKAND2X4TS U1122 ( .A(n1232), .B(n986), .Y(n1660) );
INVX2TS U1123 ( .A(n1829), .Y(n1874) );
OAI211X1TS U1124 ( .A0(n1125), .A1(n1124), .B0(n1123), .C0(n1122), .Y(n1131)
);
NAND2X4TS U1125 ( .A(n986), .B(n978), .Y(n1231) );
AO22XLTS U1126 ( .A0(Data_array_SWR[20]), .A1(n1609), .B0(Data_array_SWR[16]), .B1(n1615), .Y(n1140) );
INVX2TS U1127 ( .A(n1164), .Y(n1175) );
AO22XLTS U1128 ( .A0(Data_array_SWR[21]), .A1(n1609), .B0(Data_array_SWR[17]), .B1(n1615), .Y(n1593) );
NAND2XLTS U1129 ( .A(n991), .B(DmP_mant_SHT1_SW[0]), .Y(n1413) );
OAI31X1TS U1130 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[20]), .A2(
Raw_mant_NRM_SWR[21]), .B0(n1341), .Y(n1343) );
OAI211X1TS U1131 ( .A0(intDX_EWSW[8]), .A1(n2024), .B0(n1079), .C0(n1078),
.Y(n1080) );
NAND2XLTS U1132 ( .A(n991), .B(DmP_mant_SHT1_SW[15]), .Y(n1465) );
INVX2TS U1133 ( .A(n1179), .Y(n1191) );
INVX3TS U1134 ( .A(n1606), .Y(n1615) );
XOR2X2TS U1135 ( .A(n1997), .B(n995), .Y(DP_OP_15J131_122_6956_n18) );
INVX2TS U1136 ( .A(n1340), .Y(n1272) );
NOR2X4TS U1137 ( .A(n1589), .B(Shift_reg_FLAGS_7[0]), .Y(n1591) );
OAI211X2TS U1138 ( .A0(intDX_EWSW[12]), .A1(n2027), .B0(n1075), .C0(n1066),
.Y(n1077) );
NAND3X1TS U1139 ( .A(n2017), .B(n1121), .C(intDX_EWSW[26]), .Y(n1123) );
NOR2X1TS U1140 ( .A(n1119), .B(intDY_EWSW[24]), .Y(n1120) );
OAI211X2TS U1141 ( .A0(intDX_EWSW[20]), .A1(n2030), .B0(n1112), .C0(n1096),
.Y(n1107) );
NOR2X2TS U1142 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1341) );
OR2X2TS U1143 ( .A(n959), .B(ADD_OVRFLW_NRM), .Y(n1153) );
NOR2X1TS U1144 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1588) );
NAND2BX1TS U1145 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1079) );
NAND2BX1TS U1146 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1066) );
NAND2BX1TS U1147 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1121) );
NAND2BX1TS U1148 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1122) );
OAI21X1TS U1149 ( .A0(intDX_EWSW[15]), .A1(n1985), .B0(intDX_EWSW[14]), .Y(
n1071) );
OAI21X1TS U1150 ( .A0(intDX_EWSW[21]), .A1(n2023), .B0(intDX_EWSW[20]), .Y(
n1101) );
NAND2BX1TS U1151 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1096) );
NAND2BX1TS U1152 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1104) );
NAND2BX1TS U1153 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1115) );
NAND3X1TS U1154 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1982), .C(
n2012), .Y(n1884) );
CLKINVX2TS U1155 ( .A(Shift_reg_FLAGS_7[3]), .Y(n1589) );
AOI21X1TS U1156 ( .A0(n1698), .A1(n1042), .B0(n1041), .Y(n1043) );
OAI21X2TS U1157 ( .A0(n1184), .A1(n1010), .B0(n1009), .Y(n1782) );
OAI21X2TS U1158 ( .A0(n1708), .A1(n1040), .B0(n1039), .Y(n1698) );
AOI21X2TS U1159 ( .A0(n1717), .A1(n1038), .B0(n1037), .Y(n1708) );
NOR3X4TS U1160 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .C(
Raw_mant_NRM_SWR[19]), .Y(n1276) );
OAI21X4TS U1161 ( .A0(n1778), .A1(n1772), .B0(n1773), .Y(n1768) );
OAI21X2TS U1162 ( .A0(n1165), .A1(n1198), .B0(n1166), .Y(n1179) );
OAI21X2TS U1163 ( .A0(n1691), .A1(n1685), .B0(n1686), .Y(n1759) );
NOR2X4TS U1164 ( .A(Raw_mant_NRM_SWR[25]), .B(Raw_mant_NRM_SWR[24]), .Y(
n1344) );
AND2X4TS U1165 ( .A(n1344), .B(n1341), .Y(n1277) );
OAI211X1TS U1166 ( .A0(n1524), .A1(n973), .B0(n1417), .C0(n1416), .Y(n852)
);
OAI211X1TS U1167 ( .A0(n1513), .A1(n1564), .B0(n1512), .C0(n1511), .Y(n864)
);
OAI211X1TS U1168 ( .A0(n1485), .A1(n973), .B0(n1484), .C0(n1483), .Y(n867)
);
NAND2X6TS U1169 ( .A(n1943), .B(n1942), .Y(n1944) );
OAI211X1TS U1170 ( .A0(n1502), .A1(n1564), .B0(n1498), .C0(n1497), .Y(n866)
);
OAI211X1TS U1171 ( .A0(n1524), .A1(n1523), .B0(n1522), .C0(n1521), .Y(n851)
);
AOI21X2TS U1172 ( .A0(n1179), .A1(n1045), .B0(n1044), .Y(n1829) );
AOI21X4TS U1173 ( .A0(n1681), .A1(n1677), .B0(n1055), .Y(n1691) );
OAI21X4TS U1174 ( .A0(n1672), .A1(n1666), .B0(n1667), .Y(n1681) );
OAI21X1TS U1175 ( .A0(n1185), .A1(n1189), .B0(n1186), .Y(n1044) );
CLKAND2X2TS U1176 ( .A(n2065), .B(DMP_SFG[18]), .Y(n1033) );
CLKBUFX2TS U1177 ( .A(n1153), .Y(n1461) );
CLKAND2X2TS U1178 ( .A(n2068), .B(DMP_SFG[12]), .Y(n1021) );
CLKAND2X2TS U1179 ( .A(n2066), .B(DMP_SFG[16]), .Y(n1029) );
NAND2BXLTS U1180 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1085) );
NAND3XLTS U1181 ( .A(n2024), .B(n1079), .C(intDX_EWSW[8]), .Y(n1067) );
NAND2BXLTS U1182 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1068) );
NOR2BX1TS U1183 ( .AN(n1095), .B(n1094), .Y(n1099) );
NOR2BX1TS U1184 ( .AN(n1081), .B(n1080), .Y(n1095) );
INVX2TS U1185 ( .A(n1076), .Y(n1100) );
NOR2BX1TS U1186 ( .AN(n1097), .B(n1102), .Y(n1098) );
AOI2BB1XLTS U1187 ( .A0N(n1327), .A1N(Raw_mant_NRM_SWR[23]), .B0(
Raw_mant_NRM_SWR[24]), .Y(n1328) );
AOI2BB1XLTS U1188 ( .A0N(n2014), .A1N(n1331), .B0(n1330), .Y(n1332) );
NOR3XLTS U1189 ( .A(n1329), .B(Raw_mant_NRM_SWR[15]), .C(n1996), .Y(n1330)
);
AOI21X2TS U1190 ( .A0(n1719), .A1(n1715), .B0(n1058), .Y(n1710) );
AOI21X2TS U1191 ( .A0(n1759), .A1(n1755), .B0(n1056), .Y(n1729) );
INVX2TS U1192 ( .A(n1354), .Y(n973) );
CLKINVX6TS U1193 ( .A(n989), .Y(n990) );
BUFX3TS U1194 ( .A(n1353), .Y(n971) );
OAI21XLTS U1195 ( .A0(n1848), .A1(n1842), .B0(n1843), .Y(n1833) );
INVX2TS U1196 ( .A(n1772), .Y(n1774) );
NOR2XLTS U1197 ( .A(n1800), .B(n1016), .Y(n1018) );
OAI21XLTS U1198 ( .A0(n1799), .A1(n1016), .B0(n1015), .Y(n1017) );
INVX2TS U1199 ( .A(n1666), .Y(n1668) );
AND3X1TS U1200 ( .A(exp_rslt_NRM2_EW1[4]), .B(exp_rslt_NRM2_EW1[3]), .C(
n1574), .Y(n1575) );
CLKAND2X2TS U1201 ( .A(n2064), .B(DMP_SFG[20]), .Y(n1037) );
CLKAND2X2TS U1202 ( .A(n2067), .B(DMP_SFG[14]), .Y(n1025) );
INVX2TS U1203 ( .A(n991), .Y(n992) );
INVX2TS U1204 ( .A(n1362), .Y(n1391) );
NAND4XLTS U1205 ( .A(n1242), .B(n1241), .C(n1240), .D(n1239), .Y(n1270) );
NAND4XLTS U1206 ( .A(n1266), .B(n1265), .C(n1264), .D(n1263), .Y(n1267) );
NAND4XLTS U1207 ( .A(n1258), .B(n1257), .C(n1256), .D(n1255), .Y(n1268) );
BUFX3TS U1208 ( .A(n1530), .Y(n1545) );
BUFX3TS U1209 ( .A(n1530), .Y(n1572) );
INVX2TS U1210 ( .A(n1377), .Y(n1547) );
AO22XLTS U1211 ( .A0(n1894), .A1(Data_X[10]), .B0(n1893), .B1(intDX_EWSW[10]), .Y(n933) );
AO22XLTS U1212 ( .A0(n1905), .A1(Data_X[2]), .B0(n1893), .B1(intDX_EWSW[2]),
.Y(n941) );
AO22XLTS U1213 ( .A0(n1894), .A1(Data_X[22]), .B0(n1896), .B1(intDX_EWSW[22]), .Y(n921) );
AO22XLTS U1214 ( .A0(n1903), .A1(Data_X[20]), .B0(n1906), .B1(intDX_EWSW[20]), .Y(n923) );
AO22XLTS U1215 ( .A0(n1894), .A1(Data_X[12]), .B0(n1906), .B1(intDX_EWSW[12]), .Y(n931) );
AO22XLTS U1216 ( .A0(n1903), .A1(Data_X[31]), .B0(n1896), .B1(intDX_EWSW[31]), .Y(n912) );
AO22XLTS U1217 ( .A0(n1894), .A1(Data_X[19]), .B0(n1906), .B1(intDX_EWSW[19]), .Y(n924) );
AO22XLTS U1218 ( .A0(n1905), .A1(Data_X[18]), .B0(n1906), .B1(intDX_EWSW[18]), .Y(n925) );
AO22XLTS U1219 ( .A0(n1903), .A1(Data_X[9]), .B0(n1893), .B1(intDX_EWSW[9]),
.Y(n934) );
AO22XLTS U1220 ( .A0(n1895), .A1(Data_X[14]), .B0(n1906), .B1(intDX_EWSW[14]), .Y(n929) );
AO22XLTS U1221 ( .A0(n1894), .A1(Data_X[11]), .B0(n1893), .B1(intDX_EWSW[11]), .Y(n932) );
AO22XLTS U1222 ( .A0(n1894), .A1(Data_X[17]), .B0(n1906), .B1(intDX_EWSW[17]), .Y(n926) );
AO22XLTS U1223 ( .A0(n1903), .A1(Data_X[8]), .B0(n1893), .B1(intDX_EWSW[8]),
.Y(n935) );
AO22XLTS U1224 ( .A0(n1894), .A1(Data_X[13]), .B0(n1906), .B1(intDX_EWSW[13]), .Y(n930) );
AO22XLTS U1225 ( .A0(n1903), .A1(Data_X[21]), .B0(n1896), .B1(intDX_EWSW[21]), .Y(n922) );
AO22XLTS U1226 ( .A0(n1902), .A1(intDY_EWSW[19]), .B0(n1899), .B1(Data_Y[19]), .Y(n891) );
AO22XLTS U1227 ( .A0(n1897), .A1(intDY_EWSW[5]), .B0(n1900), .B1(Data_Y[5]),
.Y(n905) );
AO22XLTS U1228 ( .A0(n1897), .A1(intDY_EWSW[7]), .B0(n1900), .B1(Data_Y[7]),
.Y(n903) );
AO22XLTS U1229 ( .A0(n1897), .A1(intDY_EWSW[4]), .B0(n1899), .B1(Data_Y[4]),
.Y(n906) );
AO22XLTS U1230 ( .A0(n1897), .A1(intDX_EWSW[29]), .B0(n1899), .B1(Data_X[29]), .Y(n914) );
AO22XLTS U1231 ( .A0(n1897), .A1(intDX_EWSW[30]), .B0(n1899), .B1(Data_X[30]), .Y(n913) );
AO22XLTS U1232 ( .A0(n1897), .A1(intDY_EWSW[6]), .B0(n1900), .B1(Data_Y[6]),
.Y(n904) );
AO22XLTS U1233 ( .A0(n1898), .A1(intDY_EWSW[16]), .B0(n1901), .B1(Data_Y[16]), .Y(n894) );
AO22XLTS U1234 ( .A0(n1897), .A1(intDY_EWSW[2]), .B0(n1899), .B1(Data_Y[2]),
.Y(n908) );
AO22XLTS U1235 ( .A0(n1898), .A1(intDY_EWSW[9]), .B0(n1899), .B1(Data_Y[9]),
.Y(n901) );
AO22XLTS U1236 ( .A0(n1897), .A1(intDY_EWSW[0]), .B0(n1899), .B1(Data_Y[0]),
.Y(n910) );
AO22XLTS U1237 ( .A0(n1897), .A1(intDY_EWSW[1]), .B0(n1899), .B1(Data_Y[1]),
.Y(n909) );
AO22XLTS U1238 ( .A0(n1898), .A1(intDY_EWSW[10]), .B0(n1901), .B1(Data_Y[10]), .Y(n900) );
AO22XLTS U1239 ( .A0(n1905), .A1(Data_X[4]), .B0(n1893), .B1(intDX_EWSW[4]),
.Y(n939) );
AO22XLTS U1240 ( .A0(n1900), .A1(Data_X[5]), .B0(n1893), .B1(intDX_EWSW[5]),
.Y(n938) );
AO22XLTS U1241 ( .A0(n1900), .A1(Data_X[6]), .B0(n1893), .B1(intDX_EWSW[6]),
.Y(n937) );
AO22XLTS U1242 ( .A0(n1903), .A1(Data_X[7]), .B0(n1893), .B1(intDX_EWSW[7]),
.Y(n936) );
AO22XLTS U1243 ( .A0(n1894), .A1(Data_X[16]), .B0(n1906), .B1(intDX_EWSW[16]), .Y(n927) );
AO22XLTS U1244 ( .A0(n1902), .A1(intDY_EWSW[18]), .B0(n1899), .B1(Data_Y[18]), .Y(n892) );
AO22XLTS U1245 ( .A0(n1902), .A1(intDY_EWSW[20]), .B0(n1900), .B1(Data_Y[20]), .Y(n890) );
AO22XLTS U1246 ( .A0(n1902), .A1(intDY_EWSW[21]), .B0(n1907), .B1(Data_Y[21]), .Y(n889) );
AO22XLTS U1247 ( .A0(n1902), .A1(intDY_EWSW[22]), .B0(n1907), .B1(Data_Y[22]), .Y(n888) );
AO22XLTS U1248 ( .A0(n1897), .A1(intDY_EWSW[3]), .B0(n1899), .B1(Data_Y[3]),
.Y(n907) );
AO22XLTS U1249 ( .A0(n1898), .A1(intDY_EWSW[8]), .B0(n1900), .B1(Data_Y[8]),
.Y(n902) );
AO22XLTS U1250 ( .A0(n1898), .A1(intDY_EWSW[11]), .B0(n1901), .B1(Data_Y[11]), .Y(n899) );
AO22XLTS U1251 ( .A0(n1898), .A1(intDY_EWSW[15]), .B0(n1901), .B1(Data_Y[15]), .Y(n895) );
AO22XLTS U1252 ( .A0(n1898), .A1(intDY_EWSW[17]), .B0(n1901), .B1(Data_Y[17]), .Y(n893) );
AO22XLTS U1253 ( .A0(n1898), .A1(intDY_EWSW[12]), .B0(n1901), .B1(Data_Y[12]), .Y(n898) );
AO22XLTS U1254 ( .A0(n1898), .A1(intDY_EWSW[13]), .B0(n1901), .B1(Data_Y[13]), .Y(n897) );
AO22XLTS U1255 ( .A0(n1898), .A1(intDY_EWSW[14]), .B0(n1901), .B1(Data_Y[14]), .Y(n896) );
AO22XLTS U1256 ( .A0(n1896), .A1(intDX_EWSW[28]), .B0(n1900), .B1(Data_X[28]), .Y(n915) );
AOI222X1TS U1257 ( .A0(intDY_EWSW[4]), .A1(n1974), .B0(n1089), .B1(n1088),
.C0(intDY_EWSW[5]), .C1(n1999), .Y(n1091) );
AOI2BB2XLTS U1258 ( .B0(intDX_EWSW[3]), .B1(n2019), .A0N(intDY_EWSW[2]),
.A1N(n1087), .Y(n1088) );
INVX2TS U1259 ( .A(n1077), .Y(n1081) );
OAI2BB2XLTS U1260 ( .B0(n1070), .B1(n1077), .A0N(n1069), .A1N(n1078), .Y(
n1073) );
AOI21X1TS U1261 ( .A0(n1068), .A1(n1067), .B0(n1077), .Y(n1069) );
OAI21XLTS U1262 ( .A0(n1824), .A1(n1843), .B0(n1825), .Y(n1046) );
NOR2XLTS U1263 ( .A(n1190), .B(n1185), .Y(n1045) );
OAI21XLTS U1264 ( .A0(n1006), .A1(n1840), .B0(n1005), .Y(n1007) );
NAND2X4TS U1265 ( .A(n1284), .B(n1996), .Y(n1275) );
NAND2X1TS U1266 ( .A(n1114), .B(n1113), .Y(n1118) );
INVX2TS U1267 ( .A(n1116), .Y(n1117) );
AOI21X1TS U1268 ( .A0(n1164), .A1(n1002), .B0(n1001), .Y(n1184) );
NOR2XLTS U1269 ( .A(n1174), .B(n1000), .Y(n1002) );
OAI21XLTS U1270 ( .A0(n1000), .A1(n1173), .B0(n999), .Y(n1001) );
CLKAND2X2TS U1271 ( .A(n2069), .B(DMP_SFG[9]), .Y(n1013) );
AND3X1TS U1272 ( .A(exp_rslt_NRM2_EW1[2]), .B(exp_rslt_NRM2_EW1[0]), .C(
exp_rslt_NRM2_EW1[1]), .Y(n1574) );
OR2X4TS U1273 ( .A(n1331), .B(Raw_mant_NRM_SWR[18]), .Y(n1329) );
OAI21X1TS U1274 ( .A0(n1748), .A1(n1742), .B0(n1743), .Y(n1719) );
INVX2TS U1275 ( .A(n964), .Y(n965) );
AOI2BB2XLTS U1276 ( .B0(intDX_EWSW[7]), .B1(n2011), .A0N(n2011), .A1N(
intDX_EWSW[7]), .Y(n1239) );
NAND4XLTS U1277 ( .A(n1250), .B(n1249), .C(n1248), .D(n1247), .Y(n1269) );
CLKAND2X2TS U1278 ( .A(n2063), .B(DMP_SFG[22]), .Y(n1041) );
OAI211X1TS U1279 ( .A0(n1352), .A1(n1351), .B0(n1350), .C0(n1349), .Y(n1881)
);
INVX2TS U1280 ( .A(n1344), .Y(n1351) );
AOI211X1TS U1281 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1348), .B0(n1347), .C0(
n1346), .Y(n1350) );
OAI21XLTS U1282 ( .A0(n1828), .A1(n1814), .B0(n1813), .Y(n1818) );
OAI21XLTS U1283 ( .A0(n1856), .A1(n1841), .B0(n1840), .Y(n1846) );
OAI21XLTS U1284 ( .A0(n1191), .A1(n1190), .B0(n1189), .Y(n1193) );
INVX2TS U1285 ( .A(n1184), .Y(n1868) );
OAI21XLTS U1286 ( .A0(n1175), .A1(n1174), .B0(n1173), .Y(n1178) );
INVX2TS U1287 ( .A(n1801), .Y(n1803) );
OAI21XLTS U1288 ( .A0(n1820), .A1(n1807), .B0(n1806), .Y(n1809) );
OAI21XLTS U1289 ( .A0(n1828), .A1(n1800), .B0(n1799), .Y(n1805) );
OAI21XLTS U1290 ( .A0(n1820), .A1(n1792), .B0(n1815), .Y(n1794) );
OAI21XLTS U1291 ( .A0(n1828), .A1(n1786), .B0(n1785), .Y(n1790) );
INVX2TS U1292 ( .A(n1886), .Y(n1885) );
CLKINVX3TS U1293 ( .A(rst), .Y(n1154) );
MX2X1TS U1294 ( .A(n1881), .B(LZD_output_NRM2_EW[1]), .S0(n1890), .Y(n591)
);
AO22XLTS U1295 ( .A0(n1903), .A1(Data_Y[28]), .B0(n1904), .B1(intDY_EWSW[28]), .Y(n882) );
AO22XLTS U1296 ( .A0(n1905), .A1(Data_X[1]), .B0(n1904), .B1(intDX_EWSW[1]),
.Y(n942) );
AO22XLTS U1297 ( .A0(n1907), .A1(Data_Y[31]), .B0(n1906), .B1(intDY_EWSW[31]), .Y(n879) );
MX2X1TS U1298 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1941),
.Y(n726) );
MX2X1TS U1299 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1941),
.Y(n716) );
MX2X1TS U1300 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1941),
.Y(n706) );
MX2X1TS U1301 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1941),
.Y(n696) );
MX2X1TS U1302 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1941),
.Y(n721) );
MX2X1TS U1303 ( .A(DMP_SFG[9]), .B(DMP_SHT2_EWSW[9]), .S0(n1592), .Y(n770)
);
MX2X1TS U1304 ( .A(DMP_SFG[0]), .B(DMP_SHT2_EWSW[0]), .S0(n1924), .Y(n797)
);
MX2X1TS U1305 ( .A(DMP_SFG[4]), .B(DMP_SHT2_EWSW[4]), .S0(n1592), .Y(n785)
);
MX2X1TS U1306 ( .A(DMP_SFG[5]), .B(DMP_SHT2_EWSW[5]), .S0(n1592), .Y(n782)
);
MX2X1TS U1307 ( .A(DMP_SFG[8]), .B(DMP_SHT2_EWSW[8]), .S0(n1592), .Y(n773)
);
MX2X1TS U1308 ( .A(DMP_SFG[2]), .B(DMP_SHT2_EWSW[2]), .S0(n1592), .Y(n791)
);
MX2X1TS U1309 ( .A(DMP_SFG[3]), .B(DMP_SHT2_EWSW[3]), .S0(n1592), .Y(n788)
);
MX2X1TS U1310 ( .A(DMP_SFG[6]), .B(DMP_SHT2_EWSW[6]), .S0(n1592), .Y(n779)
);
MX2X1TS U1311 ( .A(DMP_SFG[7]), .B(DMP_SHT2_EWSW[7]), .S0(n1592), .Y(n776)
);
MX2X1TS U1312 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n1941),
.Y(n691) );
MX2X1TS U1313 ( .A(OP_FLAG_SFG), .B(OP_FLAG_SHT2), .S0(n1924), .Y(n629) );
MX2X1TS U1314 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1941),
.Y(n711) );
MX2X1TS U1315 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n1941),
.Y(n701) );
OAI21XLTS U1316 ( .A0(n1908), .A1(n985), .B0(n1153), .Y(n877) );
MX2X1TS U1317 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n1590), .Y(n737)
);
MX2X1TS U1318 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n1590), .Y(n731)
);
MX2X1TS U1319 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n1591), .Y(n761)
);
MX2X1TS U1320 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n1590), .Y(n755)
);
MX2X1TS U1321 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n1590), .Y(n749)
);
MX2X1TS U1322 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n1590), .Y(n743)
);
XOR2XLTS U1323 ( .A(n1201), .B(n1200), .Y(n1203) );
CLKAND2X2TS U1324 ( .A(n1199), .B(n1198), .Y(n1201) );
MX2X1TS U1325 ( .A(DMP_SFG[11]), .B(DMP_SHT2_EWSW[11]), .S0(n1592), .Y(n764)
);
MX2X1TS U1326 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n1924), .Y(n758)
);
MX2X1TS U1327 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n1591), .Y(n752)
);
MX2X1TS U1328 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n1591), .Y(n746)
);
MX2X1TS U1329 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n1590), .Y(n740)
);
MX2X1TS U1330 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n1590), .Y(n734)
);
MX2X1TS U1331 ( .A(DMP_SFG[10]), .B(DMP_SHT2_EWSW[10]), .S0(n1592), .Y(n767)
);
XOR2XLTS U1332 ( .A(n1856), .B(n1855), .Y(n1863) );
AO22XLTS U1333 ( .A0(n1905), .A1(Data_X[0]), .B0(n1904), .B1(intDX_EWSW[0]),
.Y(n943) );
AO22XLTS U1334 ( .A0(n1894), .A1(Data_X[27]), .B0(n1896), .B1(intDX_EWSW[27]), .Y(n916) );
AO22XLTS U1335 ( .A0(n1903), .A1(Data_X[23]), .B0(n1896), .B1(intDX_EWSW[23]), .Y(n920) );
OAI22X1TS U1336 ( .A0(n1565), .A1(n1564), .B0(n1563), .B1(n1562), .Y(n1566)
);
AO22XLTS U1337 ( .A0(n1902), .A1(intDY_EWSW[24]), .B0(n1907), .B1(Data_Y[24]), .Y(n886) );
AO22XLTS U1338 ( .A0(n1902), .A1(intDY_EWSW[27]), .B0(n1901), .B1(Data_Y[27]), .Y(n883) );
AO21XLTS U1339 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1629), .B0(n1147), .Y(n541)
);
AOI2BB2XLTS U1340 ( .B0(n986), .B1(n1234), .A0N(n1632), .A1N(n1144), .Y(
n1146) );
XOR2XLTS U1341 ( .A(n1828), .B(n1827), .Y(n1837) );
AO22XLTS U1342 ( .A0(n1905), .A1(Data_Y[30]), .B0(n1904), .B1(intDY_EWSW[30]), .Y(n880) );
AO22XLTS U1343 ( .A0(n1903), .A1(Data_Y[29]), .B0(n1904), .B1(intDY_EWSW[29]), .Y(n881) );
XOR2XLTS U1344 ( .A(n1872), .B(n1871), .Y(n1879) );
XOR2XLTS U1345 ( .A(n1175), .B(n1168), .Y(n1172) );
AOI2BB2XLTS U1346 ( .B0(beg_OP), .B1(n1982), .A0N(n1982), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1139) );
XOR2XLTS U1347 ( .A(n1746), .B(n1745), .Y(n1751) );
AO22XLTS U1348 ( .A0(n1889), .A1(Shift_reg_FLAGS_7_6), .B0(n1891), .B1(n1892), .Y(n950) );
XOR2XLTS U1349 ( .A(n1776), .B(n1775), .Y(n1781) );
AO22XLTS U1350 ( .A0(n1902), .A1(intDY_EWSW[25]), .B0(n1907), .B1(Data_Y[25]), .Y(n885) );
AO22XLTS U1351 ( .A0(n1902), .A1(intDY_EWSW[26]), .B0(n1907), .B1(Data_Y[26]), .Y(n884) );
AO22XLTS U1352 ( .A0(n1902), .A1(intDY_EWSW[23]), .B0(n1895), .B1(Data_Y[23]), .Y(n887) );
AO22XLTS U1353 ( .A0(n1896), .A1(intDX_EWSW[25]), .B0(n1900), .B1(Data_X[25]), .Y(n918) );
AO22XLTS U1354 ( .A0(n1896), .A1(intDX_EWSW[26]), .B0(n1900), .B1(Data_X[26]), .Y(n917) );
AO22XLTS U1355 ( .A0(n1896), .A1(intDX_EWSW[24]), .B0(n1901), .B1(Data_X[24]), .Y(n919) );
OAI21XLTS U1356 ( .A0(n1908), .A1(n2006), .B0(n1482), .Y(n878) );
XOR2XLTS U1357 ( .A(n1670), .B(n1669), .Y(n1675) );
MX2X1TS U1358 ( .A(DMP_SFG[1]), .B(DMP_SHT2_EWSW[1]), .S0(n1924), .Y(n794)
);
AO21XLTS U1359 ( .A0(LZD_output_NRM2_EW[0]), .A1(n1890), .B0(n1882), .Y(n593) );
AOI2BB1XLTS U1360 ( .A0N(Shift_reg_FLAGS_7[0]), .A1N(overflow_flag), .B0(
n1943), .Y(n638) );
AO21XLTS U1361 ( .A0(underflow_flag), .A1(n1967), .B0(n1308), .Y(n639) );
AO22XLTS U1362 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1967), .B1(zero_flag), .Y(n632) );
XOR2XLTS U1363 ( .A(n1708), .B(n1707), .Y(n1713) );
XOR2XLTS U1364 ( .A(n1727), .B(n1726), .Y(n1732) );
XOR2XLTS U1365 ( .A(n1689), .B(n1688), .Y(n1694) );
AO22XLTS U1366 ( .A0(n1941), .A1(SIGN_FLAG_NRM), .B0(n1940), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n622) );
AO22XLTS U1367 ( .A0(Shift_reg_FLAGS_7[2]), .A1(SIGN_FLAG_SFG), .B0(n1921),
.B1(SIGN_FLAG_NRM), .Y(n623) );
AO22XLTS U1368 ( .A0(n1591), .A1(SIGN_FLAG_SHT2), .B0(n1938), .B1(
SIGN_FLAG_SFG), .Y(n624) );
AO22XLTS U1369 ( .A0(n964), .A1(SIGN_FLAG_SHT1), .B0(n1937), .B1(
SIGN_FLAG_SHT2), .Y(n625) );
AO22XLTS U1370 ( .A0(n956), .A1(SIGN_FLAG_EXP), .B0(n1920), .B1(
SIGN_FLAG_SHT1), .Y(n626) );
AO22XLTS U1371 ( .A0(n964), .A1(OP_FLAG_SHT1), .B0(n1937), .B1(OP_FLAG_SHT2),
.Y(n630) );
AO22XLTS U1372 ( .A0(n957), .A1(OP_FLAG_EXP), .B0(n2071), .B1(OP_FLAG_SHT1),
.Y(n631) );
AO22XLTS U1373 ( .A0(n992), .A1(ZERO_FLAG_NRM), .B0(n1940), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n633) );
AO22XLTS U1374 ( .A0(n974), .A1(ZERO_FLAG_SFG), .B0(n1935), .B1(
ZERO_FLAG_NRM), .Y(n634) );
AO22XLTS U1375 ( .A0(n1924), .A1(ZERO_FLAG_SHT2), .B0(n1629), .B1(
ZERO_FLAG_SFG), .Y(n635) );
AO22XLTS U1376 ( .A0(n1934), .A1(ZERO_FLAG_SHT1), .B0(n966), .B1(
ZERO_FLAG_SHT2), .Y(n636) );
AO22XLTS U1377 ( .A0(n1933), .A1(ZERO_FLAG_EXP), .B0(n1927), .B1(
ZERO_FLAG_SHT1), .Y(n637) );
AO22XLTS U1378 ( .A0(n1933), .A1(DmP_EXP_EWSW[22]), .B0(n1927), .B1(
DmP_mant_SHT1_SW[22]), .Y(n645) );
AO22XLTS U1379 ( .A0(n1933), .A1(DmP_EXP_EWSW[21]), .B0(n1932), .B1(
DmP_mant_SHT1_SW[21]), .Y(n647) );
AO22XLTS U1380 ( .A0(n1933), .A1(DmP_EXP_EWSW[20]), .B0(n1926), .B1(
DmP_mant_SHT1_SW[20]), .Y(n649) );
AO22XLTS U1381 ( .A0(n1933), .A1(DmP_EXP_EWSW[19]), .B0(n1936), .B1(
DmP_mant_SHT1_SW[19]), .Y(n651) );
AO22XLTS U1382 ( .A0(n1933), .A1(DmP_EXP_EWSW[18]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[18]), .Y(n653) );
AO22XLTS U1383 ( .A0(n1933), .A1(DmP_EXP_EWSW[17]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[17]), .Y(n655) );
AO22XLTS U1384 ( .A0(n1933), .A1(DmP_EXP_EWSW[16]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[16]), .Y(n657) );
AO22XLTS U1385 ( .A0(n1933), .A1(DmP_EXP_EWSW[15]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[15]), .Y(n659) );
AO22XLTS U1386 ( .A0(n1933), .A1(DmP_EXP_EWSW[14]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[14]), .Y(n661) );
AO22XLTS U1387 ( .A0(n1928), .A1(DmP_EXP_EWSW[13]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[13]), .Y(n663) );
AO22XLTS U1388 ( .A0(n1928), .A1(DmP_EXP_EWSW[12]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[12]), .Y(n665) );
AO22XLTS U1389 ( .A0(n1928), .A1(DmP_EXP_EWSW[11]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[11]), .Y(n667) );
AO22XLTS U1390 ( .A0(n1928), .A1(DmP_EXP_EWSW[10]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[10]), .Y(n669) );
OAI21XLTS U1391 ( .A0(n2002), .A1(n1391), .B0(n1368), .Y(n670) );
AO22XLTS U1392 ( .A0(n1928), .A1(DmP_EXP_EWSW[9]), .B0(n1929), .B1(
DmP_mant_SHT1_SW[9]), .Y(n671) );
OAI21XLTS U1393 ( .A0(n2021), .A1(n1391), .B0(n1373), .Y(n672) );
AO22XLTS U1394 ( .A0(n1928), .A1(DmP_EXP_EWSW[8]), .B0(n1927), .B1(
DmP_mant_SHT1_SW[8]), .Y(n673) );
OAI21XLTS U1395 ( .A0(n2024), .A1(n1391), .B0(n1372), .Y(n674) );
AO22XLTS U1396 ( .A0(n1928), .A1(DmP_EXP_EWSW[7]), .B0(n1936), .B1(
DmP_mant_SHT1_SW[7]), .Y(n675) );
OAI21XLTS U1397 ( .A0(n2011), .A1(n1391), .B0(n1365), .Y(n676) );
AO22XLTS U1398 ( .A0(n1928), .A1(DmP_EXP_EWSW[6]), .B0(n1920), .B1(
DmP_mant_SHT1_SW[6]), .Y(n677) );
AO22XLTS U1399 ( .A0(n1928), .A1(DmP_EXP_EWSW[5]), .B0(n1926), .B1(
DmP_mant_SHT1_SW[5]), .Y(n679) );
AO22XLTS U1400 ( .A0(n1928), .A1(DmP_EXP_EWSW[4]), .B0(n1927), .B1(
DmP_mant_SHT1_SW[4]), .Y(n681) );
AO22XLTS U1401 ( .A0(n1925), .A1(DmP_EXP_EWSW[3]), .B0(n1932), .B1(
DmP_mant_SHT1_SW[3]), .Y(n683) );
AO22XLTS U1402 ( .A0(n1925), .A1(DmP_EXP_EWSW[2]), .B0(n1920), .B1(
DmP_mant_SHT1_SW[2]), .Y(n685) );
OAI21XLTS U1403 ( .A0(n2025), .A1(n1391), .B0(n1360), .Y(n686) );
AO22XLTS U1404 ( .A0(n1925), .A1(DmP_EXP_EWSW[1]), .B0(n1936), .B1(
DmP_mant_SHT1_SW[1]), .Y(n687) );
AO22XLTS U1405 ( .A0(n1925), .A1(DmP_EXP_EWSW[0]), .B0(n1936), .B1(
DmP_mant_SHT1_SW[0]), .Y(n689) );
AO22XLTS U1406 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[30]), .B0(n1921),
.B1(DMP_exp_NRM_EW[7]), .Y(n692) );
AO22XLTS U1407 ( .A0(n1924), .A1(DMP_SHT2_EWSW[30]), .B0(n1938), .B1(
DMP_SFG[30]), .Y(n693) );
AO22XLTS U1408 ( .A0(n1934), .A1(DMP_SHT1_EWSW[30]), .B0(n2123), .B1(
DMP_SHT2_EWSW[30]), .Y(n694) );
AO22XLTS U1409 ( .A0(n1925), .A1(DMP_EXP_EWSW[30]), .B0(n1936), .B1(
DMP_SHT1_EWSW[30]), .Y(n695) );
AO22XLTS U1410 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[29]), .B0(n1921),
.B1(DMP_exp_NRM_EW[6]), .Y(n697) );
AO22XLTS U1411 ( .A0(n1924), .A1(DMP_SHT2_EWSW[29]), .B0(n1629), .B1(
DMP_SFG[29]), .Y(n698) );
AO22XLTS U1412 ( .A0(n1934), .A1(DMP_SHT1_EWSW[29]), .B0(n2123), .B1(
DMP_SHT2_EWSW[29]), .Y(n699) );
AO22XLTS U1413 ( .A0(n1925), .A1(DMP_EXP_EWSW[29]), .B0(n1932), .B1(
DMP_SHT1_EWSW[29]), .Y(n700) );
AO22XLTS U1414 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[28]), .B0(n1921),
.B1(DMP_exp_NRM_EW[5]), .Y(n702) );
AO22XLTS U1415 ( .A0(n1924), .A1(DMP_SHT2_EWSW[28]), .B0(n1938), .B1(
DMP_SFG[28]), .Y(n703) );
AO22XLTS U1416 ( .A0(n1934), .A1(DMP_SHT1_EWSW[28]), .B0(n965), .B1(
DMP_SHT2_EWSW[28]), .Y(n704) );
AO22XLTS U1417 ( .A0(n1925), .A1(DMP_EXP_EWSW[28]), .B0(n1920), .B1(
DMP_SHT1_EWSW[28]), .Y(n705) );
AO22XLTS U1418 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[27]), .B0(n1921),
.B1(DMP_exp_NRM_EW[4]), .Y(n707) );
AO22XLTS U1419 ( .A0(n1924), .A1(DMP_SHT2_EWSW[27]), .B0(n1923), .B1(
DMP_SFG[27]), .Y(n708) );
AO22XLTS U1420 ( .A0(n1934), .A1(DMP_SHT1_EWSW[27]), .B0(n965), .B1(
DMP_SHT2_EWSW[27]), .Y(n709) );
AO22XLTS U1421 ( .A0(n1925), .A1(DMP_EXP_EWSW[27]), .B0(n1932), .B1(
DMP_SHT1_EWSW[27]), .Y(n710) );
AO22XLTS U1422 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[26]), .B0(n1921),
.B1(DMP_exp_NRM_EW[3]), .Y(n712) );
AO22XLTS U1423 ( .A0(n1924), .A1(DMP_SHT2_EWSW[26]), .B0(n1938), .B1(
DMP_SFG[26]), .Y(n713) );
AO22XLTS U1424 ( .A0(n1922), .A1(DMP_SHT1_EWSW[26]), .B0(n966), .B1(
DMP_SHT2_EWSW[26]), .Y(n714) );
AO22XLTS U1425 ( .A0(n1925), .A1(DMP_EXP_EWSW[26]), .B0(n1927), .B1(
DMP_SHT1_EWSW[26]), .Y(n715) );
AO22XLTS U1426 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[25]), .B0(n1921),
.B1(DMP_exp_NRM_EW[2]), .Y(n717) );
AO22XLTS U1427 ( .A0(n1591), .A1(DMP_SHT2_EWSW[25]), .B0(n1938), .B1(
DMP_SFG[25]), .Y(n718) );
AO22XLTS U1428 ( .A0(n1934), .A1(DMP_SHT1_EWSW[25]), .B0(n965), .B1(
DMP_SHT2_EWSW[25]), .Y(n719) );
AO22XLTS U1429 ( .A0(n1925), .A1(DMP_EXP_EWSW[25]), .B0(n1936), .B1(
DMP_SHT1_EWSW[25]), .Y(n720) );
AO22XLTS U1430 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[24]), .B0(n996),
.B1(DMP_exp_NRM_EW[1]), .Y(n722) );
AO22XLTS U1431 ( .A0(n1590), .A1(DMP_SHT2_EWSW[24]), .B0(n1923), .B1(
DMP_SFG[24]), .Y(n723) );
AO22XLTS U1432 ( .A0(n1934), .A1(DMP_SHT1_EWSW[24]), .B0(n965), .B1(
DMP_SHT2_EWSW[24]), .Y(n724) );
AO22XLTS U1433 ( .A0(n957), .A1(DMP_EXP_EWSW[24]), .B0(n1920), .B1(
DMP_SHT1_EWSW[24]), .Y(n725) );
AO22XLTS U1434 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[23]), .B0(n996),
.B1(DMP_exp_NRM_EW[0]), .Y(n727) );
AO22XLTS U1435 ( .A0(n1590), .A1(DMP_SHT2_EWSW[23]), .B0(n1629), .B1(
DMP_SFG[23]), .Y(n728) );
AO22XLTS U1436 ( .A0(n1934), .A1(DMP_SHT1_EWSW[23]), .B0(n965), .B1(
DMP_SHT2_EWSW[23]), .Y(n729) );
AO22XLTS U1437 ( .A0(n956), .A1(DMP_EXP_EWSW[23]), .B0(n1927), .B1(
DMP_SHT1_EWSW[23]), .Y(n730) );
AO22XLTS U1438 ( .A0(n1934), .A1(DMP_SHT1_EWSW[22]), .B0(n965), .B1(
DMP_SHT2_EWSW[22]), .Y(n732) );
AO22XLTS U1439 ( .A0(n956), .A1(DMP_EXP_EWSW[22]), .B0(n1936), .B1(
DMP_SHT1_EWSW[22]), .Y(n733) );
AO22XLTS U1440 ( .A0(n1934), .A1(DMP_SHT1_EWSW[21]), .B0(n965), .B1(
DMP_SHT2_EWSW[21]), .Y(n735) );
AO22XLTS U1441 ( .A0(n956), .A1(DMP_EXP_EWSW[21]), .B0(n1932), .B1(
DMP_SHT1_EWSW[21]), .Y(n736) );
AO22XLTS U1442 ( .A0(n1922), .A1(DMP_SHT1_EWSW[20]), .B0(n2123), .B1(
DMP_SHT2_EWSW[20]), .Y(n738) );
AO22XLTS U1443 ( .A0(n956), .A1(DMP_EXP_EWSW[20]), .B0(n1936), .B1(
DMP_SHT1_EWSW[20]), .Y(n739) );
AO22XLTS U1444 ( .A0(n1922), .A1(DMP_SHT1_EWSW[19]), .B0(n2123), .B1(
DMP_SHT2_EWSW[19]), .Y(n741) );
AO22XLTS U1445 ( .A0(n956), .A1(DMP_EXP_EWSW[19]), .B0(n1927), .B1(
DMP_SHT1_EWSW[19]), .Y(n742) );
AO22XLTS U1446 ( .A0(n1922), .A1(DMP_SHT1_EWSW[18]), .B0(n2123), .B1(
DMP_SHT2_EWSW[18]), .Y(n744) );
AO22XLTS U1447 ( .A0(n957), .A1(DMP_EXP_EWSW[18]), .B0(n1927), .B1(
DMP_SHT1_EWSW[18]), .Y(n745) );
AO22XLTS U1448 ( .A0(n1922), .A1(DMP_SHT1_EWSW[17]), .B0(n2123), .B1(
DMP_SHT2_EWSW[17]), .Y(n747) );
AO22XLTS U1449 ( .A0(n957), .A1(DMP_EXP_EWSW[17]), .B0(n1927), .B1(
DMP_SHT1_EWSW[17]), .Y(n748) );
AO22XLTS U1450 ( .A0(n1922), .A1(DMP_SHT1_EWSW[16]), .B0(n2123), .B1(
DMP_SHT2_EWSW[16]), .Y(n750) );
AO22XLTS U1451 ( .A0(n957), .A1(DMP_EXP_EWSW[16]), .B0(n1926), .B1(
DMP_SHT1_EWSW[16]), .Y(n751) );
AO22XLTS U1452 ( .A0(n1922), .A1(DMP_SHT1_EWSW[15]), .B0(n2123), .B1(
DMP_SHT2_EWSW[15]), .Y(n753) );
AO22XLTS U1453 ( .A0(n957), .A1(DMP_EXP_EWSW[15]), .B0(n1932), .B1(
DMP_SHT1_EWSW[15]), .Y(n754) );
AO22XLTS U1454 ( .A0(n1922), .A1(DMP_SHT1_EWSW[14]), .B0(n2123), .B1(
DMP_SHT2_EWSW[14]), .Y(n756) );
AO22XLTS U1455 ( .A0(n1919), .A1(DMP_EXP_EWSW[14]), .B0(n1926), .B1(
DMP_SHT1_EWSW[14]), .Y(n757) );
AO22XLTS U1456 ( .A0(n1922), .A1(DMP_SHT1_EWSW[13]), .B0(n966), .B1(
DMP_SHT2_EWSW[13]), .Y(n759) );
AO22XLTS U1457 ( .A0(n1919), .A1(DMP_EXP_EWSW[13]), .B0(n1926), .B1(
DMP_SHT1_EWSW[13]), .Y(n760) );
AO22XLTS U1458 ( .A0(n964), .A1(DMP_SHT1_EWSW[12]), .B0(n966), .B1(
DMP_SHT2_EWSW[12]), .Y(n762) );
AO22XLTS U1459 ( .A0(n1919), .A1(DMP_EXP_EWSW[12]), .B0(n1932), .B1(
DMP_SHT1_EWSW[12]), .Y(n763) );
AO22XLTS U1460 ( .A0(n1922), .A1(DMP_SHT1_EWSW[11]), .B0(n966), .B1(
DMP_SHT2_EWSW[11]), .Y(n765) );
AO22XLTS U1461 ( .A0(n1919), .A1(DMP_EXP_EWSW[11]), .B0(n1920), .B1(
DMP_SHT1_EWSW[11]), .Y(n766) );
AO22XLTS U1462 ( .A0(n964), .A1(DMP_SHT1_EWSW[10]), .B0(n1937), .B1(
DMP_SHT2_EWSW[10]), .Y(n768) );
AO22XLTS U1463 ( .A0(n1919), .A1(DMP_EXP_EWSW[10]), .B0(n1918), .B1(
DMP_SHT1_EWSW[10]), .Y(n769) );
AO22XLTS U1464 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n1937), .B1(
DMP_SHT2_EWSW[9]), .Y(n771) );
AO22XLTS U1465 ( .A0(n1919), .A1(DMP_EXP_EWSW[9]), .B0(n1918), .B1(
DMP_SHT1_EWSW[9]), .Y(n772) );
AO22XLTS U1466 ( .A0(n964), .A1(DMP_SHT1_EWSW[8]), .B0(n966), .B1(
DMP_SHT2_EWSW[8]), .Y(n774) );
AO22XLTS U1467 ( .A0(n1919), .A1(DMP_EXP_EWSW[8]), .B0(n1918), .B1(
DMP_SHT1_EWSW[8]), .Y(n775) );
AO22XLTS U1468 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(DMP_SHT2_EWSW[7]),
.B1(n966), .Y(n2073) );
AO22XLTS U1469 ( .A0(n1919), .A1(DMP_EXP_EWSW[7]), .B0(n1918), .B1(
DMP_SHT1_EWSW[7]), .Y(n778) );
AO22XLTS U1470 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(DMP_SHT2_EWSW[6]),
.B1(n966), .Y(n2074) );
AO22XLTS U1471 ( .A0(n1919), .A1(DMP_EXP_EWSW[6]), .B0(n1918), .B1(
DMP_SHT1_EWSW[6]), .Y(n781) );
AO22XLTS U1472 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(DMP_SHT2_EWSW[5]),
.B1(n966), .Y(n2075) );
AO22XLTS U1473 ( .A0(n1919), .A1(DMP_EXP_EWSW[5]), .B0(n1918), .B1(
DMP_SHT1_EWSW[5]), .Y(n784) );
AO22XLTS U1474 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(DMP_SHT2_EWSW[4]),
.B1(n966), .Y(n2076) );
AO22XLTS U1475 ( .A0(n1917), .A1(DMP_EXP_EWSW[4]), .B0(n1918), .B1(
DMP_SHT1_EWSW[4]), .Y(n787) );
AO22XLTS U1476 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(DMP_SHT2_EWSW[3]),
.B1(n1937), .Y(n2077) );
AO22XLTS U1477 ( .A0(n1917), .A1(DMP_EXP_EWSW[3]), .B0(n1918), .B1(
DMP_SHT1_EWSW[3]), .Y(n790) );
AO22XLTS U1478 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(DMP_SHT2_EWSW[2]),
.B1(n1937), .Y(n2078) );
AO22XLTS U1479 ( .A0(n1917), .A1(DMP_EXP_EWSW[2]), .B0(n1918), .B1(
DMP_SHT1_EWSW[2]), .Y(n793) );
AO22XLTS U1480 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(DMP_SHT2_EWSW[1]),
.B1(n1937), .Y(n2079) );
AO22XLTS U1481 ( .A0(n1917), .A1(DMP_EXP_EWSW[1]), .B0(n1918), .B1(
DMP_SHT1_EWSW[1]), .Y(n796) );
AO22XLTS U1482 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(DMP_SHT2_EWSW[0]),
.B1(n1937), .Y(n2080) );
AO22XLTS U1483 ( .A0(n1917), .A1(DMP_EXP_EWSW[0]), .B0(n1932), .B1(
DMP_SHT1_EWSW[0]), .Y(n799) );
AO22XLTS U1484 ( .A0(n1554), .A1(n1271), .B0(ZERO_FLAG_EXP), .B1(n1571), .Y(
n801) );
AO21XLTS U1485 ( .A0(OP_FLAG_EXP), .A1(n1571), .B0(n1271), .Y(n802) );
OAI21XLTS U1486 ( .A0(n1988), .A1(n1547), .B0(n1533), .Y(n814) );
OAI21XLTS U1487 ( .A0(n2020), .A1(n1547), .B0(n1526), .Y(n816) );
OAI21XLTS U1488 ( .A0(n1985), .A1(n1547), .B0(n1546), .Y(n818) );
OAI21XLTS U1489 ( .A0(n2028), .A1(n1547), .B0(n1538), .Y(n819) );
OAI21XLTS U1490 ( .A0(n2022), .A1(n1547), .B0(n1136), .Y(n820) );
OAI21XLTS U1491 ( .A0(n2027), .A1(n1543), .B0(n1542), .Y(n821) );
OAI21XLTS U1492 ( .A0(n2009), .A1(n1543), .B0(n1540), .Y(n822) );
OAI21XLTS U1493 ( .A0(n2024), .A1(n1543), .B0(n1541), .Y(n825) );
OAI21XLTS U1494 ( .A0(n2026), .A1(n1543), .B0(n1535), .Y(n829) );
OAI21XLTS U1495 ( .A0(n2019), .A1(n1543), .B0(n1135), .Y(n830) );
AO22XLTS U1496 ( .A0(n1917), .A1(n1212), .B0(n1932), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n842) );
AO22XLTS U1497 ( .A0(n1917), .A1(n1207), .B0(n1920), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n843) );
AO22XLTS U1498 ( .A0(n1917), .A1(n1161), .B0(n1936), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n844) );
AO22XLTS U1499 ( .A0(n1917), .A1(n1916), .B0(n1936), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n845) );
AO22XLTS U1500 ( .A0(n1917), .A1(n1912), .B0(n2071), .B1(
Shift_amount_SHT1_EWR[0]), .Y(n846) );
AO22XLTS U1501 ( .A0(n1891), .A1(busy), .B0(n1889), .B1(Shift_reg_FLAGS_7[3]), .Y(n947) );
NOR2BX4TS U1502 ( .AN(n1296), .B(Raw_mant_NRM_SWR[7]), .Y(n1335) );
AOI22X1TS U1503 ( .A0(n1507), .A1(Data_array_SWR[12]), .B0(n1399), .B1(n1509), .Y(n1505) );
INVX2TS U1504 ( .A(n2123), .Y(n964) );
OR2X1TS U1505 ( .A(shift_value_SHT2_EWR[4]), .B(n1613), .Y(n962) );
BUFX3TS U1506 ( .A(left_right_SHT2), .Y(n1634) );
NOR3BX4TS U1507 ( .AN(n1336), .B(Raw_mant_NRM_SWR[12]), .C(
Raw_mant_NRM_SWR[10]), .Y(n1300) );
AO22X2TS U1508 ( .A0(n1516), .A1(n1881), .B0(Shift_amount_SHT1_EWR[1]), .B1(
n1940), .Y(n1397) );
INVX2TS U1509 ( .A(n964), .Y(n966) );
INVX2TS U1510 ( .A(n1228), .Y(n967) );
INVX2TS U1511 ( .A(n1228), .Y(n968) );
NOR2X4TS U1512 ( .A(n1398), .B(n1909), .Y(n1353) );
BUFX3TS U1513 ( .A(n2071), .Y(n1936) );
INVX2TS U1514 ( .A(n1353), .Y(n975) );
INVX2TS U1515 ( .A(n1979), .Y(n976) );
INVX2TS U1516 ( .A(n976), .Y(n977) );
INVX2TS U1517 ( .A(n976), .Y(n978) );
INVX2TS U1518 ( .A(n960), .Y(n979) );
INVX2TS U1519 ( .A(n960), .Y(n980) );
INVX2TS U1520 ( .A(n1141), .Y(n981) );
INVX2TS U1521 ( .A(n1141), .Y(n982) );
INVX2TS U1522 ( .A(n962), .Y(n983) );
INVX2TS U1523 ( .A(n962), .Y(n984) );
INVX2TS U1524 ( .A(n1634), .Y(n985) );
INVX2TS U1525 ( .A(n985), .Y(n986) );
OAI21X1TS U1526 ( .A0(n1613), .A1(n2039), .B0(n1612), .Y(n1614) );
AOI211X2TS U1527 ( .A0(Data_array_SWR[24]), .A1(n1595), .B0(n1594), .C0(
n1140), .Y(n1635) );
NOR2X2TS U1528 ( .A(n2005), .B(n1612), .Y(n1594) );
OAI21X2TS U1529 ( .A0(n1153), .A1(n2046), .B0(n1355), .Y(n1560) );
AOI22X2TS U1530 ( .A0(n1615), .A1(Data_array_SWR[25]), .B0(bit_shift_SHT2),
.B1(n1606), .Y(n1632) );
AOI22X2TS U1531 ( .A0(n1615), .A1(Data_array_SWR[23]), .B0(bit_shift_SHT2),
.B1(n1606), .Y(n1656) );
CLKBUFX3TS U1532 ( .A(n2094), .Y(n2122) );
NAND2X4TS U1533 ( .A(n1940), .B(n1937), .Y(n1908) );
OAI21XLTS U1534 ( .A0(n992), .A1(n1997), .B0(n1482), .Y(n627) );
BUFX3TS U1535 ( .A(n1154), .Y(n1158) );
OAI21XLTS U1536 ( .A0(DmP_EXP_EWSW[25]), .A1(n994), .B0(n1205), .Y(n1160) );
NOR2X4TS U1537 ( .A(n977), .B(n2006), .Y(n1232) );
OAI21X2TS U1538 ( .A0(n2072), .A1(n1153), .B0(n1425), .Y(n1453) );
OAI21X2TS U1539 ( .A0(n2044), .A1(n1482), .B0(n1441), .Y(n1503) );
OAI21X2TS U1540 ( .A0(n2014), .A1(n1482), .B0(n1481), .Y(n1508) );
OAI21X2TS U1541 ( .A0(n1482), .A1(n2013), .B0(n1473), .Y(n1496) );
OAI21X2TS U1542 ( .A0(n1998), .A1(n1482), .B0(n1409), .Y(n1435) );
OAI21X2TS U1543 ( .A0(n1996), .A1(n1482), .B0(n1449), .Y(n1509) );
OAI21X2TS U1544 ( .A0(n1975), .A1(n1461), .B0(n1460), .Y(n1490) );
BUFX3TS U1545 ( .A(n2071), .Y(n1927) );
AOI221X1TS U1546 ( .A0(n2031), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n2033), .C0(n1237), .Y(n1241) );
AOI221X1TS U1547 ( .A0(n2002), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]),
.B1(n2009), .C0(n1252), .Y(n1257) );
AOI221X1TS U1548 ( .A0(n2025), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n2019), .C0(n1260), .Y(n1265) );
AOI221X1TS U1549 ( .A0(n1986), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n2035), .C0(n1246), .Y(n1247) );
AOI221X1TS U1550 ( .A0(n2030), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n2023), .C0(n1245), .Y(n1248) );
AOI221X1TS U1551 ( .A0(n2027), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n2022), .C0(n1253), .Y(n1256) );
OAI2BB2XLTS U1552 ( .B0(intDY_EWSW[0]), .B1(n1084), .A0N(intDX_EWSW[1]),
.A1N(n2124), .Y(n1086) );
AOI221X1TS U1553 ( .A0(n2124), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n2020), .C0(n1243), .Y(n1250) );
BUFX3TS U1554 ( .A(n1944), .Y(n993) );
BUFX3TS U1555 ( .A(n1944), .Y(n1970) );
AOI21X1TS U1556 ( .A0(n1782), .A1(n1018), .B0(n1017), .Y(n1776) );
OAI31XLTS U1557 ( .A0(n1554), .A1(n1553), .A2(n1931), .B0(n1552), .Y(n800)
);
NOR4BX2TS U1558 ( .AN(n1338), .B(n1285), .C(n1280), .D(n1279), .Y(n1283) );
OAI21XLTS U1559 ( .A0(n2022), .A1(n1388), .B0(n1376), .Y(n664) );
OAI21XLTS U1560 ( .A0(n2027), .A1(n1388), .B0(n1371), .Y(n666) );
OAI21XLTS U1561 ( .A0(n2009), .A1(n1388), .B0(n1370), .Y(n668) );
OAI21XLTS U1562 ( .A0(n2028), .A1(n1388), .B0(n1369), .Y(n662) );
OAI21XLTS U1563 ( .A0(n2031), .A1(n1388), .B0(n1364), .Y(n640) );
NAND3X2TS U1564 ( .A(n1404), .B(n1403), .C(n1402), .Y(n1519) );
AOI21X2TS U1565 ( .A0(Data_array_SWR[21]), .A1(n1615), .B0(n1614), .Y(n1650)
);
NAND3X2TS U1566 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n977), .Y(n1228) );
AOI22X2TS U1567 ( .A0(n1615), .A1(Data_array_SWR[22]), .B0(bit_shift_SHT2),
.B1(n1606), .Y(n1653) );
OR2X1TS U1568 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n1788) );
NOR2XLTS U1569 ( .A(n2062), .B(DMP_SFG[0]), .Y(n998) );
NOR2X2TS U1570 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n1852) );
BUFX3TS U1571 ( .A(n1154), .Y(n1157) );
AOI222X1TS U1572 ( .A0(n1377), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1571), .C0(intDY_EWSW[23]), .C1(n1572), .Y(n1570) );
OAI21XLTS U1573 ( .A0(DmP_EXP_EWSW[23]), .A1(n2036), .B0(n1911), .Y(n1912)
);
OAI21X2TS U1574 ( .A0(n2004), .A1(n1461), .B0(n1396), .Y(n1487) );
OAI21X2TS U1575 ( .A0(n1976), .A1(n1482), .B0(n1424), .Y(n1445) );
OAI21X2TS U1576 ( .A0(n2008), .A1(n1482), .B0(n1408), .Y(n1437) );
INVX4TS U1577 ( .A(n1464), .Y(n1482) );
BUFX3TS U1578 ( .A(n2071), .Y(n1926) );
OAI21XLTS U1579 ( .A0(n1548), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1159) );
OR2X1TS U1580 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n1715) );
OR2X1TS U1581 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n1696) );
OR2X1TS U1582 ( .A(n2068), .B(DMP_SFG[12]), .Y(n1022) );
OR2X1TS U1583 ( .A(n2067), .B(DMP_SFG[14]), .Y(n1026) );
OR2X1TS U1584 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n1677) );
OR2X1TS U1585 ( .A(n2066), .B(DMP_SFG[16]), .Y(n1030) );
OR2X1TS U1586 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n1755) );
OR2X1TS U1587 ( .A(n2065), .B(DMP_SFG[18]), .Y(n1034) );
OR2X1TS U1588 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n1734) );
NOR2XLTS U1589 ( .A(n2051), .B(DMP_SFG[21]), .Y(n1040) );
AOI21X2TS U1590 ( .A0(Data_array_SWR[19]), .A1(n1615), .B0(n1603), .Y(n1644)
);
AOI21X2TS U1591 ( .A0(Data_array_SWR[18]), .A1(n1615), .B0(n1599), .Y(n1641)
);
AOI22X2TS U1592 ( .A0(n1615), .A1(Data_array_SWR[24]), .B0(bit_shift_SHT2),
.B1(n1606), .Y(n1659) );
AOI21X2TS U1593 ( .A0(Data_array_SWR[24]), .A1(n1609), .B0(n1608), .Y(n1647)
);
AOI221X1TS U1594 ( .A0(n2034), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1988), .C0(n1244), .Y(n1249) );
AOI32X1TS U1595 ( .A0(n2034), .A1(n1104), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1988), .Y(n1105) );
OAI21X2TS U1596 ( .A0(intDX_EWSW[18]), .A1(n2034), .B0(n1104), .Y(n1244) );
OA22X1TS U1597 ( .A0(n2028), .A1(intDX_EWSW[14]), .B0(n1985), .B1(
intDX_EWSW[15]), .Y(n1075) );
NOR2XLTS U1598 ( .A(n2009), .B(intDX_EWSW[11]), .Y(n1064) );
OAI21XLTS U1599 ( .A0(intDX_EWSW[13]), .A1(n2022), .B0(intDX_EWSW[12]), .Y(
n1063) );
OA22X1TS U1600 ( .A0(n1986), .A1(intDX_EWSW[22]), .B0(n2035), .B1(
intDX_EWSW[23]), .Y(n1112) );
OR2X1TS U1601 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n995) );
BUFX3TS U1602 ( .A(n1377), .Y(n1383) );
OAI21XLTS U1603 ( .A0(intDX_EWSW[1]), .A1(n2124), .B0(intDX_EWSW[0]), .Y(
n1084) );
OR2X1TS U1604 ( .A(n2069), .B(DMP_SFG[9]), .Y(n1014) );
OR2X1TS U1605 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n1764) );
AOI21X2TS U1606 ( .A0(n1791), .A1(n1053), .B0(n1052), .Y(n1778) );
NAND2X1TS U1607 ( .A(Raw_mant_NRM_SWR[10]), .B(n1336), .Y(n1288) );
OAI21X2TS U1608 ( .A0(n1776), .A1(n1020), .B0(n1019), .Y(n1766) );
NAND2BX2TS U1609 ( .AN(n1397), .B(n1908), .Y(n1909) );
AOI22X1TS U1610 ( .A0(intDX_EWSW[15]), .A1(n1545), .B0(DMP_EXP_EWSW[15]),
.B1(n1544), .Y(n1546) );
AND3X1TS U1611 ( .A(n1415), .B(n1414), .C(n1413), .Y(n1524) );
BUFX3TS U1612 ( .A(n1753), .Y(n1752) );
NAND2X1TS U1613 ( .A(n1995), .B(sub_x_5_n131), .Y(n1200) );
NAND2X1TS U1614 ( .A(n2062), .B(DMP_SFG[0]), .Y(n997) );
OAI21X1TS U1615 ( .A0(n1200), .A1(n998), .B0(n997), .Y(n1164) );
NOR2X1TS U1616 ( .A(n2061), .B(DMP_SFG[1]), .Y(n1174) );
NOR2X1TS U1617 ( .A(n2050), .B(DMP_SFG[2]), .Y(n1000) );
NAND2X1TS U1618 ( .A(n2061), .B(DMP_SFG[1]), .Y(n1173) );
NAND2X1TS U1619 ( .A(n2050), .B(DMP_SFG[2]), .Y(n999) );
NOR2X1TS U1620 ( .A(n2060), .B(DMP_SFG[3]), .Y(n1864) );
NOR2X1TS U1621 ( .A(n2049), .B(DMP_SFG[4]), .Y(n1004) );
NOR2X1TS U1622 ( .A(n1864), .B(n1004), .Y(n1839) );
NOR2X1TS U1623 ( .A(n2059), .B(DMP_SFG[5]), .Y(n1841) );
NOR2X1TS U1624 ( .A(n2048), .B(DMP_SFG[6]), .Y(n1006) );
NOR2X1TS U1625 ( .A(n1841), .B(n1006), .Y(n1008) );
NAND2X1TS U1626 ( .A(n1839), .B(n1008), .Y(n1010) );
NAND2X1TS U1627 ( .A(n2060), .B(DMP_SFG[3]), .Y(n1865) );
NAND2X1TS U1628 ( .A(n2049), .B(DMP_SFG[4]), .Y(n1003) );
OAI21X1TS U1629 ( .A0(n1004), .A1(n1865), .B0(n1003), .Y(n1838) );
NAND2X1TS U1630 ( .A(n2059), .B(DMP_SFG[5]), .Y(n1840) );
NAND2X1TS U1631 ( .A(n2048), .B(DMP_SFG[6]), .Y(n1005) );
AOI21X1TS U1632 ( .A0(n1838), .A1(n1008), .B0(n1007), .Y(n1009) );
NOR2X1TS U1633 ( .A(n2058), .B(DMP_SFG[7]), .Y(n1814) );
NOR2X1TS U1634 ( .A(n2047), .B(DMP_SFG[8]), .Y(n1012) );
NOR2X1TS U1635 ( .A(n1814), .B(n1012), .Y(n1783) );
NAND2X1TS U1636 ( .A(n1783), .B(n1014), .Y(n1800) );
NOR2X1TS U1637 ( .A(n2057), .B(DMP_SFG[10]), .Y(n1016) );
NAND2X1TS U1638 ( .A(n2058), .B(DMP_SFG[7]), .Y(n1813) );
NAND2X1TS U1639 ( .A(n2047), .B(DMP_SFG[8]), .Y(n1011) );
OAI21X1TS U1640 ( .A0(n1012), .A1(n1813), .B0(n1011), .Y(n1784) );
AOI21X1TS U1641 ( .A0(n1784), .A1(n1014), .B0(n1013), .Y(n1799) );
NAND2X1TS U1642 ( .A(n2057), .B(DMP_SFG[10]), .Y(n1015) );
NAND2X1TS U1643 ( .A(n2056), .B(DMP_SFG[11]), .Y(n1019) );
AOI21X4TS U1644 ( .A0(n1766), .A1(n1022), .B0(n1021), .Y(n1670) );
NOR2X1TS U1645 ( .A(n2055), .B(DMP_SFG[13]), .Y(n1024) );
NAND2X1TS U1646 ( .A(n2055), .B(DMP_SFG[13]), .Y(n1023) );
OAI21X4TS U1647 ( .A0(n1670), .A1(n1024), .B0(n1023), .Y(n1679) );
AOI21X4TS U1648 ( .A0(n1679), .A1(n1026), .B0(n1025), .Y(n1689) );
NOR2X1TS U1649 ( .A(n2054), .B(DMP_SFG[15]), .Y(n1028) );
NAND2X1TS U1650 ( .A(n2054), .B(DMP_SFG[15]), .Y(n1027) );
OAI21X4TS U1651 ( .A0(n1689), .A1(n1028), .B0(n1027), .Y(n1757) );
AOI21X4TS U1652 ( .A0(n1757), .A1(n1030), .B0(n1029), .Y(n1727) );
NOR2X1TS U1653 ( .A(n2053), .B(DMP_SFG[17]), .Y(n1032) );
NAND2X1TS U1654 ( .A(n2053), .B(DMP_SFG[17]), .Y(n1031) );
OAI21X4TS U1655 ( .A0(n1727), .A1(n1032), .B0(n1031), .Y(n1736) );
AOI21X4TS U1656 ( .A0(n1736), .A1(n1034), .B0(n1033), .Y(n1746) );
NOR2X1TS U1657 ( .A(n2052), .B(DMP_SFG[19]), .Y(n1036) );
NAND2X1TS U1658 ( .A(n2052), .B(DMP_SFG[19]), .Y(n1035) );
OR2X1TS U1659 ( .A(n2064), .B(DMP_SFG[20]), .Y(n1038) );
NAND2X1TS U1660 ( .A(n2051), .B(DMP_SFG[21]), .Y(n1039) );
OR2X1TS U1661 ( .A(n2063), .B(DMP_SFG[22]), .Y(n1042) );
XOR2X1TS U1662 ( .A(n1043), .B(n2070), .Y(n1062) );
NOR2X1TS U1663 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n1165) );
NAND2X1TS U1664 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n1198) );
NAND2X1TS U1665 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n1166) );
NOR2X2TS U1666 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n1190) );
NOR2X2TS U1667 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n1185) );
NAND2X1TS U1668 ( .A(DMP_SFG[2]), .B(DmP_mant_SFG_SWR[4]), .Y(n1189) );
NAND2X1TS U1669 ( .A(DMP_SFG[3]), .B(DmP_mant_SFG_SWR[5]), .Y(n1186) );
NOR2X1TS U1670 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n1857) );
NOR2X1TS U1671 ( .A(n1857), .B(n1852), .Y(n1831) );
NOR2X2TS U1672 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n1842) );
NOR2X2TS U1673 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n1824) );
NOR2X1TS U1674 ( .A(n1842), .B(n1824), .Y(n1047) );
NAND2X1TS U1675 ( .A(n1831), .B(n1047), .Y(n1049) );
NAND2X1TS U1676 ( .A(DMP_SFG[4]), .B(DmP_mant_SFG_SWR[6]), .Y(n1869) );
NAND2X1TS U1677 ( .A(DMP_SFG[5]), .B(DmP_mant_SFG_SWR[7]), .Y(n1853) );
OAI21X1TS U1678 ( .A0(n1852), .A1(n1869), .B0(n1853), .Y(n1830) );
NAND2X1TS U1679 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n1843) );
NAND2X1TS U1680 ( .A(DMP_SFG[7]), .B(DmP_mant_SFG_SWR[9]), .Y(n1825) );
AOI21X1TS U1681 ( .A0(n1830), .A1(n1047), .B0(n1046), .Y(n1048) );
OAI21X2TS U1682 ( .A0(n1829), .A1(n1049), .B0(n1048), .Y(n1791) );
NOR2X1TS U1683 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n1792) );
INVX2TS U1684 ( .A(n1792), .Y(n1816) );
NAND2X1TS U1685 ( .A(n1816), .B(n1788), .Y(n1807) );
NOR2X2TS U1686 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n1801) );
NOR2X1TS U1687 ( .A(n1807), .B(n1801), .Y(n1053) );
NAND2X1TS U1688 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR[10]), .Y(n1815) );
INVX2TS U1689 ( .A(n1815), .Y(n1051) );
NAND2X1TS U1690 ( .A(DMP_SFG[9]), .B(DmP_mant_SFG_SWR[11]), .Y(n1787) );
INVX2TS U1691 ( .A(n1787), .Y(n1050) );
AOI21X1TS U1692 ( .A0(n1788), .A1(n1051), .B0(n1050), .Y(n1806) );
NAND2X1TS U1693 ( .A(DMP_SFG[10]), .B(DmP_mant_SFG_SWR[12]), .Y(n1802) );
OAI21X1TS U1694 ( .A0(n1806), .A1(n1801), .B0(n1802), .Y(n1052) );
NOR2X1TS U1695 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n1772) );
NAND2X1TS U1696 ( .A(DMP_SFG[11]), .B(DmP_mant_SFG_SWR[13]), .Y(n1773) );
NAND2X1TS U1697 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n1763) );
INVX2TS U1698 ( .A(n1763), .Y(n1054) );
AOI21X4TS U1699 ( .A0(n1768), .A1(n1764), .B0(n1054), .Y(n1672) );
NOR2X1TS U1700 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n1666) );
NAND2X1TS U1701 ( .A(DMP_SFG[13]), .B(DmP_mant_SFG_SWR[15]), .Y(n1667) );
NAND2X1TS U1702 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n1676) );
INVX2TS U1703 ( .A(n1676), .Y(n1055) );
NOR2X1TS U1704 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n1685) );
NAND2X1TS U1705 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n1686) );
NAND2X1TS U1706 ( .A(DMP_SFG[16]), .B(DmP_mant_SFG_SWR[18]), .Y(n1754) );
INVX2TS U1707 ( .A(n1754), .Y(n1056) );
NOR2X1TS U1708 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n1723) );
NAND2X1TS U1709 ( .A(DMP_SFG[17]), .B(DmP_mant_SFG_SWR[19]), .Y(n1724) );
NAND2X1TS U1710 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .Y(n1733) );
INVX2TS U1711 ( .A(n1733), .Y(n1057) );
NOR2X1TS U1712 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n1742) );
NAND2X1TS U1713 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .Y(n1743) );
NAND2X1TS U1714 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n1714) );
INVX2TS U1715 ( .A(n1714), .Y(n1058) );
NOR2X1TS U1716 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n1704) );
NAND2X1TS U1717 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n1705) );
OAI21X2TS U1718 ( .A0(n1710), .A1(n1704), .B0(n1705), .Y(n1700) );
NAND2X1TS U1719 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n1695) );
INVX2TS U1720 ( .A(n1695), .Y(n1059) );
AOI21X2TS U1721 ( .A0(n1700), .A1(n1696), .B0(n1059), .Y(n1137) );
XOR2X1TS U1722 ( .A(n1137), .B(DmP_mant_SFG_SWR[25]), .Y(n1060) );
INVX2TS U1723 ( .A(n974), .Y(n1921) );
BUFX3TS U1724 ( .A(n1921), .Y(n1875) );
BUFX3TS U1725 ( .A(n1921), .Y(n1935) );
AOI22X1TS U1726 ( .A0(n1060), .A1(n1194), .B0(Raw_mant_NRM_SWR[25]), .B1(
n1935), .Y(n1061) );
OAI2BB2XLTS U1727 ( .B0(intDY_EWSW[12]), .B1(n1063), .A0N(intDX_EWSW[13]),
.A1N(n2022), .Y(n1074) );
AOI22X1TS U1728 ( .A0(intDX_EWSW[11]), .A1(n2009), .B0(intDX_EWSW[10]), .B1(
n1065), .Y(n1070) );
OAI22X1TS U1729 ( .A0(n2002), .A1(intDX_EWSW[10]), .B0(n2009), .B1(
intDX_EWSW[11]), .Y(n1252) );
INVX2TS U1730 ( .A(n1252), .Y(n1078) );
OAI2BB2XLTS U1731 ( .B0(intDY_EWSW[14]), .B1(n1071), .A0N(intDX_EWSW[15]),
.A1N(n1985), .Y(n1072) );
AOI211X1TS U1732 ( .A0(n1075), .A1(n1074), .B0(n1073), .C0(n1072), .Y(n1076)
);
OAI2BB1X1TS U1733 ( .A0N(n1999), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1082) );
OAI22X1TS U1734 ( .A0(intDY_EWSW[4]), .A1(n1082), .B0(n1999), .B1(
intDY_EWSW[5]), .Y(n1093) );
OAI2BB1X1TS U1735 ( .A0N(n2000), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1083) );
OAI22X1TS U1736 ( .A0(intDY_EWSW[6]), .A1(n1083), .B0(n2000), .B1(
intDY_EWSW[7]), .Y(n1092) );
AOI22X1TS U1737 ( .A0(intDY_EWSW[7]), .A1(n2000), .B0(intDY_EWSW[6]), .B1(
n1978), .Y(n1090) );
OAI32X1TS U1738 ( .A0(n1093), .A1(n1092), .A2(n1091), .B0(n1090), .B1(n1092),
.Y(n1094) );
AOI211X1TS U1739 ( .A0(intDY_EWSW[16]), .A1(n2003), .B0(n1107), .C0(n1244),
.Y(n1097) );
NOR2X1TS U1740 ( .A(n2020), .B(intDX_EWSW[17]), .Y(n1102) );
OAI2BB2XLTS U1741 ( .B0(intDY_EWSW[20]), .B1(n1101), .A0N(intDX_EWSW[21]),
.A1N(n2023), .Y(n1111) );
AOI22X1TS U1742 ( .A0(intDX_EWSW[17]), .A1(n2020), .B0(intDX_EWSW[16]), .B1(
n1103), .Y(n1106) );
OAI32X1TS U1743 ( .A0(n1244), .A1(n1107), .A2(n1106), .B0(n1105), .B1(n1107),
.Y(n1110) );
OAI2BB2XLTS U1744 ( .B0(intDY_EWSW[22]), .B1(n1108), .A0N(intDX_EWSW[23]),
.A1N(n2035), .Y(n1109) );
AOI211X1TS U1745 ( .A0(n1112), .A1(n1111), .B0(n1110), .C0(n1109), .Y(n1113)
);
OAI21X1TS U1746 ( .A0(intDX_EWSW[26]), .A1(n2017), .B0(n1121), .Y(n1124) );
NOR2X1TS U1747 ( .A(n2018), .B(intDX_EWSW[25]), .Y(n1119) );
NOR2X1TS U1748 ( .A(n1981), .B(intDX_EWSW[30]), .Y(n1128) );
NOR2X1TS U1749 ( .A(n2007), .B(intDX_EWSW[29]), .Y(n1126) );
AOI211X1TS U1750 ( .A0(intDY_EWSW[28]), .A1(n2033), .B0(n1128), .C0(n1126),
.Y(n1130) );
NAND4BBX1TS U1751 ( .AN(n1124), .BN(n1119), .C(n1130), .D(n1115), .Y(n1116)
);
AOI22X1TS U1752 ( .A0(intDX_EWSW[25]), .A1(n2018), .B0(intDX_EWSW[24]), .B1(
n1120), .Y(n1125) );
NOR3X1TS U1753 ( .A(n2033), .B(n1126), .C(intDY_EWSW[28]), .Y(n1127) );
AOI221X1TS U1754 ( .A0(intDX_EWSW[30]), .A1(n1981), .B0(intDX_EWSW[29]),
.B1(n2007), .C0(n1127), .Y(n1129) );
AOI2BB2X1TS U1755 ( .B0(n1131), .B1(n1130), .A0N(n1129), .A1N(n1128), .Y(
n1132) );
BUFX3TS U1756 ( .A(n1991), .Y(n1571) );
CLKBUFX2TS U1757 ( .A(n1991), .Y(n1363) );
BUFX3TS U1758 ( .A(n1363), .Y(n1544) );
AOI22X1TS U1759 ( .A0(intDX_EWSW[3]), .A1(n1572), .B0(DMP_EXP_EWSW[3]), .B1(
n1544), .Y(n1135) );
AOI22X1TS U1760 ( .A0(intDX_EWSW[13]), .A1(n1545), .B0(DMP_EXP_EWSW[13]),
.B1(n1991), .Y(n1136) );
NAND2X1TS U1761 ( .A(n1137), .B(n2070), .Y(n1138) );
NOR2X2TS U1762 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2012), .Y(n1886) );
OAI21XLTS U1763 ( .A0(n1886), .A1(n1139), .B0(n1884), .Y(n951) );
INVX2TS U1764 ( .A(n1591), .Y(n1923) );
BUFX3TS U1765 ( .A(n1923), .Y(n1629) );
NOR2X1TS U1766 ( .A(shift_value_SHT2_EWR[2]), .B(n1977), .Y(n1595) );
NAND2X2TS U1767 ( .A(shift_value_SHT2_EWR[3]), .B(bit_shift_SHT2), .Y(n1612)
);
NAND2X2TS U1768 ( .A(shift_value_SHT2_EWR[2]), .B(n1977), .Y(n1613) );
INVX2TS U1769 ( .A(n1613), .Y(n1609) );
NAND2X2TS U1770 ( .A(n2005), .B(n1977), .Y(n1606) );
AOI22X1TS U1771 ( .A0(Data_array_SWR[8]), .A1(n979), .B0(Data_array_SWR[0]),
.B1(n981), .Y(n1143) );
AOI22X1TS U1772 ( .A0(Data_array_SWR[12]), .A1(n967), .B0(Data_array_SWR[4]),
.B1(n983), .Y(n1142) );
OAI211X1TS U1773 ( .A0(n1635), .A1(n978), .B0(n1143), .C0(n1142), .Y(n1234)
);
AOI21X1TS U1774 ( .A0(n1146), .A1(n1145), .B0(n1923), .Y(n1147) );
CLKBUFX2TS U1775 ( .A(n2040), .Y(n1967) );
XNOR2X2TS U1776 ( .A(DP_OP_15J131_122_6956_n1), .B(ADD_OVRFLW_NRM2), .Y(
n1578) );
INVX2TS U1777 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1318) );
INVX2TS U1778 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1322) );
NOR2X1TS U1779 ( .A(n1149), .B(exp_rslt_NRM2_EW1[5]), .Y(n1150) );
NOR2BX1TS U1780 ( .AN(n1150), .B(exp_rslt_NRM2_EW1[6]), .Y(n1151) );
NAND2BX2TS U1781 ( .AN(n1578), .B(n1152), .Y(n1942) );
BUFX3TS U1782 ( .A(n2040), .Y(n1582) );
BUFX3TS U1783 ( .A(n1472), .Y(n1940) );
BUFX3TS U1784 ( .A(n965), .Y(n1937) );
BUFX3TS U1785 ( .A(n1157), .Y(n2098) );
BUFX3TS U1786 ( .A(n1154), .Y(n2099) );
BUFX3TS U1787 ( .A(n1154), .Y(n2100) );
CLKBUFX2TS U1788 ( .A(n1154), .Y(n1155) );
BUFX3TS U1789 ( .A(n1157), .Y(n2101) );
BUFX3TS U1790 ( .A(n1157), .Y(n2102) );
CLKBUFX2TS U1791 ( .A(n1154), .Y(n1156) );
BUFX3TS U1792 ( .A(n2122), .Y(n2103) );
BUFX3TS U1793 ( .A(n1157), .Y(n2104) );
BUFX3TS U1794 ( .A(n2099), .Y(n2105) );
BUFX3TS U1795 ( .A(n2100), .Y(n2106) );
BUFX3TS U1796 ( .A(n2099), .Y(n2090) );
BUFX3TS U1797 ( .A(n2099), .Y(n2092) );
BUFX3TS U1798 ( .A(n1154), .Y(n2093) );
BUFX3TS U1799 ( .A(n1154), .Y(n2095) );
BUFX3TS U1800 ( .A(n2099), .Y(n2120) );
BUFX3TS U1801 ( .A(n1154), .Y(n2096) );
BUFX3TS U1802 ( .A(n2100), .Y(n2121) );
BUFX3TS U1803 ( .A(n2093), .Y(n2097) );
BUFX3TS U1804 ( .A(n2100), .Y(n2083) );
BUFX3TS U1805 ( .A(n2093), .Y(n2086) );
BUFX3TS U1806 ( .A(n1154), .Y(n2094) );
BUFX3TS U1807 ( .A(n2093), .Y(n2089) );
BUFX3TS U1808 ( .A(n2095), .Y(n2084) );
BUFX3TS U1809 ( .A(n2122), .Y(n2091) );
BUFX3TS U1810 ( .A(n2100), .Y(n2114) );
BUFX3TS U1811 ( .A(n2122), .Y(n2088) );
BUFX3TS U1812 ( .A(n2093), .Y(n2113) );
BUFX3TS U1813 ( .A(n2096), .Y(n2082) );
BUFX3TS U1814 ( .A(n2122), .Y(n2087) );
BUFX3TS U1815 ( .A(n1158), .Y(n2085) );
BUFX3TS U1816 ( .A(n2095), .Y(n2108) );
BUFX3TS U1817 ( .A(n2094), .Y(n2081) );
BUFX3TS U1818 ( .A(n2095), .Y(n2119) );
BUFX3TS U1819 ( .A(n2096), .Y(n2109) );
BUFX3TS U1820 ( .A(n2095), .Y(n2115) );
BUFX3TS U1821 ( .A(n2096), .Y(n2117) );
BUFX3TS U1822 ( .A(n1158), .Y(n2107) );
BUFX3TS U1823 ( .A(n1158), .Y(n2118) );
BUFX3TS U1824 ( .A(n2096), .Y(n2112) );
BUFX3TS U1825 ( .A(n2094), .Y(n2110) );
BUFX3TS U1826 ( .A(n1158), .Y(n2111) );
BUFX3TS U1827 ( .A(n2094), .Y(n2116) );
CLKXOR2X2TS U1828 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1548) );
AOI21X1TS U1829 ( .A0(n1548), .A1(intDX_EWSW[31]), .B0(n1159), .Y(n1271) );
BUFX3TS U1830 ( .A(n2071), .Y(n1932) );
INVX2TS U1831 ( .A(n1926), .Y(n1917) );
NAND2X1TS U1832 ( .A(DmP_EXP_EWSW[23]), .B(n2036), .Y(n1911) );
INVX2TS U1833 ( .A(n1911), .Y(n1915) );
NOR2X1TS U1834 ( .A(n1989), .B(DMP_EXP_EWSW[24]), .Y(n1913) );
OAI22X1TS U1835 ( .A0(n1915), .A1(n1913), .B0(DmP_EXP_EWSW[24]), .B1(n1990),
.Y(n1204) );
NAND2X1TS U1836 ( .A(DmP_EXP_EWSW[25]), .B(n994), .Y(n1205) );
XNOR2X1TS U1837 ( .A(n1204), .B(n1160), .Y(n1161) );
XNOR2X1TS U1838 ( .A(DmP_mant_SFG_SWR[1]), .B(sub_x_5_n131), .Y(n1163) );
BUFX3TS U1839 ( .A(n1194), .Y(n1876) );
AOI22X1TS U1840 ( .A0(n1876), .A1(DmP_mant_SFG_SWR[1]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n1875), .Y(n1162) );
OAI2BB1X1TS U1841 ( .A0N(n1753), .A1N(n1163), .B0(n1162), .Y(n619) );
INVX2TS U1842 ( .A(n1165), .Y(n1167) );
NAND2X1TS U1843 ( .A(n1167), .B(n1166), .Y(n1169) );
INVX2TS U1844 ( .A(n1169), .Y(n1168) );
XOR2X1TS U1845 ( .A(n1169), .B(n1198), .Y(n1170) );
AOI22X1TS U1846 ( .A0(n1170), .A1(n1876), .B0(Raw_mant_NRM_SWR[3]), .B1(
n1875), .Y(n1171) );
OAI2BB1X1TS U1847 ( .A0N(n1753), .A1N(n1172), .B0(n1171), .Y(n617) );
INVX2TS U1848 ( .A(n1190), .Y(n1176) );
NAND2X1TS U1849 ( .A(n1176), .B(n1189), .Y(n1180) );
INVX2TS U1850 ( .A(n1180), .Y(n1177) );
XNOR2X1TS U1851 ( .A(n1178), .B(n1177), .Y(n1183) );
XOR2X1TS U1852 ( .A(n1191), .B(n1180), .Y(n1181) );
AOI22X1TS U1853 ( .A0(n1181), .A1(n1876), .B0(Raw_mant_NRM_SWR[4]), .B1(
n1875), .Y(n1182) );
OAI2BB1X1TS U1854 ( .A0N(n1753), .A1N(n1183), .B0(n1182), .Y(n616) );
INVX2TS U1855 ( .A(n1185), .Y(n1187) );
NAND2X1TS U1856 ( .A(n1187), .B(n1186), .Y(n1192) );
INVX2TS U1857 ( .A(n1192), .Y(n1188) );
XNOR2X1TS U1858 ( .A(n1868), .B(n1188), .Y(n1197) );
XNOR2X1TS U1859 ( .A(n1193), .B(n1192), .Y(n1195) );
BUFX3TS U1860 ( .A(n1194), .Y(n1795) );
AOI22X1TS U1861 ( .A0(n1195), .A1(n1795), .B0(Raw_mant_NRM_SWR[5]), .B1(
n1875), .Y(n1196) );
OAI2BB1X1TS U1862 ( .A0N(n1753), .A1N(n1197), .B0(n1196), .Y(n615) );
OR2X1TS U1863 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n1199) );
AOI22X1TS U1864 ( .A0(n1201), .A1(n1876), .B0(Raw_mant_NRM_SWR[2]), .B1(
n1875), .Y(n1202) );
OAI2BB1X1TS U1865 ( .A0N(n1753), .A1N(n1203), .B0(n1202), .Y(n618) );
BUFX3TS U1866 ( .A(n1923), .Y(n1938) );
BUFX3TS U1867 ( .A(n1591), .Y(n1924) );
AOI22X1TS U1868 ( .A0(DMP_EXP_EWSW[25]), .A1(n2043), .B0(n1205), .B1(n1204),
.Y(n1208) );
NOR2X1TS U1869 ( .A(n963), .B(DMP_EXP_EWSW[26]), .Y(n1209) );
AOI21X1TS U1870 ( .A0(DMP_EXP_EWSW[26]), .A1(n963), .B0(n1209), .Y(n1206) );
XNOR2X1TS U1871 ( .A(n1208), .B(n1206), .Y(n1207) );
OAI22X1TS U1872 ( .A0(n1209), .A1(n1208), .B0(DmP_EXP_EWSW[26]), .B1(n2042),
.Y(n1211) );
XNOR2X1TS U1873 ( .A(DmP_EXP_EWSW[27]), .B(DMP_EXP_EWSW[27]), .Y(n1210) );
XOR2X1TS U1874 ( .A(n1211), .B(n1210), .Y(n1212) );
NOR2X1TS U1875 ( .A(n1232), .B(n1594), .Y(n1217) );
AOI22X1TS U1876 ( .A0(Data_array_SWR[19]), .A1(n984), .B0(Data_array_SWR[15]), .B1(n982), .Y(n1213) );
OAI211X1TS U1877 ( .A0(n2038), .A1(n960), .B0(n1217), .C0(n1213), .Y(n1222)
);
AOI21X1TS U1878 ( .A0(Data_array_SWR[14]), .A1(n984), .B0(n1232), .Y(n1215)
);
AOI22X1TS U1879 ( .A0(Data_array_SWR[18]), .A1(n980), .B0(Data_array_SWR[10]), .B1(n982), .Y(n1214) );
OAI211X1TS U1880 ( .A0(n2037), .A1(n1228), .B0(n1215), .C0(n1214), .Y(n1223)
);
AOI22X1TS U1881 ( .A0(n986), .A1(n1222), .B0(n1223), .B1(n961), .Y(n1949) );
MXI2X1TS U1882 ( .A(n1949), .B(n2047), .S0(n1629), .Y(n556) );
AOI22X1TS U1883 ( .A0(Data_array_SWR[18]), .A1(n984), .B0(Data_array_SWR[14]), .B1(n982), .Y(n1216) );
OAI211X1TS U1884 ( .A0(n2037), .A1(n960), .B0(n1217), .C0(n1216), .Y(n1220)
);
AOI21X1TS U1885 ( .A0(Data_array_SWR[15]), .A1(n984), .B0(n1232), .Y(n1219)
);
AOI22X1TS U1886 ( .A0(Data_array_SWR[19]), .A1(n980), .B0(Data_array_SWR[11]), .B1(n982), .Y(n1218) );
OAI211X1TS U1887 ( .A0(n2038), .A1(n1228), .B0(n1219), .C0(n1218), .Y(n1221)
);
AOI22X1TS U1888 ( .A0(n1634), .A1(n1220), .B0(n1221), .B1(n961), .Y(n1947)
);
MXI2X1TS U1889 ( .A(n1947), .B(n2069), .S0(n1938), .Y(n555) );
AOI22X1TS U1890 ( .A0(n986), .A1(n1221), .B0(n1220), .B1(n985), .Y(n1948) );
MXI2X1TS U1891 ( .A(n1948), .B(n2068), .S0(n1938), .Y(n552) );
AOI22X1TS U1892 ( .A0(n1634), .A1(n1223), .B0(n1222), .B1(n985), .Y(n1950)
);
MXI2X1TS U1893 ( .A(n1950), .B(n2055), .S0(n1629), .Y(n551) );
AOI22X1TS U1894 ( .A0(Data_array_SWR[20]), .A1(n980), .B0(Data_array_SWR[12]), .B1(n982), .Y(n1225) );
AOI22X1TS U1895 ( .A0(Data_array_SWR[16]), .A1(n983), .B0(Data_array_SWR[24]), .B1(n968), .Y(n1224) );
NAND2X1TS U1896 ( .A(n1225), .B(n1224), .Y(n1229) );
AOI22X1TS U1897 ( .A0(Data_array_SWR[21]), .A1(n979), .B0(Data_array_SWR[13]), .B1(n981), .Y(n1227) );
NAND2X1TS U1898 ( .A(Data_array_SWR[17]), .B(n983), .Y(n1226) );
OAI211X1TS U1899 ( .A0(n1228), .A1(n2039), .B0(n1227), .C0(n1226), .Y(n1230)
);
AOI221X1TS U1900 ( .A0(n986), .A1(n1229), .B0(n1662), .B1(n1230), .C0(n1232),
.Y(n1946) );
MXI2X1TS U1901 ( .A(n1946), .B(n2056), .S0(n1629), .Y(n553) );
AOI221X1TS U1902 ( .A0(n1634), .A1(n1230), .B0(n1662), .B1(n1229), .C0(n1232), .Y(n1945) );
MXI2X1TS U1903 ( .A(n1945), .B(n2057), .S0(n1629), .Y(n554) );
AOI211X1TS U1904 ( .A0(n1234), .A1(n985), .B0(n1233), .C0(n1660), .Y(n1235)
);
BUFX3TS U1905 ( .A(n1591), .Y(n1590) );
MXI2X1TS U1906 ( .A(n1235), .B(sub_x_5_n131), .S0(n1664), .Y(n566) );
OAI22X1TS U1907 ( .A0(n2018), .A1(intDX_EWSW[25]), .B0(n2017), .B1(
intDX_EWSW[26]), .Y(n1236) );
AOI221X1TS U1908 ( .A0(n2018), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n2017), .C0(n1236), .Y(n1242) );
OAI22X1TS U1909 ( .A0(n2031), .A1(intDX_EWSW[27]), .B0(n2033), .B1(
intDY_EWSW[28]), .Y(n1237) );
OAI22X1TS U1910 ( .A0(n2032), .A1(intDY_EWSW[29]), .B0(n1987), .B1(
intDY_EWSW[30]), .Y(n1238) );
AOI221X1TS U1911 ( .A0(n2032), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1987), .C0(n1238), .Y(n1240) );
OAI22X1TS U1912 ( .A0(n2124), .A1(intDX_EWSW[1]), .B0(n2020), .B1(
intDX_EWSW[17]), .Y(n1243) );
OAI22X1TS U1913 ( .A0(n2030), .A1(intDX_EWSW[20]), .B0(n2023), .B1(
intDX_EWSW[21]), .Y(n1245) );
OAI22X1TS U1914 ( .A0(n1986), .A1(intDX_EWSW[22]), .B0(n2035), .B1(
intDX_EWSW[23]), .Y(n1246) );
OAI22X1TS U1915 ( .A0(n1972), .A1(intDX_EWSW[24]), .B0(n2021), .B1(
intDX_EWSW[9]), .Y(n1251) );
AOI221X1TS U1916 ( .A0(n1972), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n2021), .C0(n1251), .Y(n1258) );
OAI22X1TS U1917 ( .A0(n2027), .A1(intDX_EWSW[12]), .B0(n2022), .B1(
intDX_EWSW[13]), .Y(n1253) );
OAI22X1TS U1918 ( .A0(n2028), .A1(intDX_EWSW[14]), .B0(n1985), .B1(
intDX_EWSW[15]), .Y(n1254) );
AOI221X1TS U1919 ( .A0(n2028), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1985), .C0(n1254), .Y(n1255) );
OAI22X1TS U1920 ( .A0(n2029), .A1(intDX_EWSW[16]), .B0(n1984), .B1(
intDX_EWSW[0]), .Y(n1259) );
AOI221X1TS U1921 ( .A0(n2029), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1984), .C0(n1259), .Y(n1266) );
OAI22X1TS U1922 ( .A0(n2025), .A1(intDX_EWSW[2]), .B0(n2019), .B1(
intDX_EWSW[3]), .Y(n1260) );
OAI22X1TS U1923 ( .A0(n2026), .A1(intDX_EWSW[4]), .B0(n1983), .B1(
intDX_EWSW[5]), .Y(n1261) );
AOI221X1TS U1924 ( .A0(n2026), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1983), .C0(n1261), .Y(n1264) );
OAI22X1TS U1925 ( .A0(n2024), .A1(intDX_EWSW[8]), .B0(n2010), .B1(
intDX_EWSW[6]), .Y(n1262) );
AOI221X1TS U1926 ( .A0(n2024), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n2010), .C0(n1262), .Y(n1263) );
NOR4X1TS U1927 ( .A(n1270), .B(n1269), .C(n1268), .D(n1267), .Y(n1554) );
NOR2X1TS U1928 ( .A(n991), .B(n2015), .Y(n1392) );
INVX2TS U1929 ( .A(n1392), .Y(n1323) );
INVX2TS U1930 ( .A(n1323), .Y(n1464) );
NOR2X2TS U1931 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[17]), .Y(
n1340) );
NAND2X4TS U1932 ( .A(n1277), .B(n1276), .Y(n1331) );
NOR2BX4TS U1933 ( .AN(n1287), .B(n1329), .Y(n1284) );
NOR2X8TS U1934 ( .A(n1345), .B(Raw_mant_NRM_SWR[11]), .Y(n1336) );
OAI22X1TS U1935 ( .A0(n1288), .A1(Raw_mant_NRM_SWR[12]), .B0(n2013), .B1(
n1331), .Y(n1346) );
AOI32X1TS U1936 ( .A0(Raw_mant_NRM_SWR[0]), .A1(n2004), .A2(n1980), .B0(
Raw_mant_NRM_SWR[2]), .B1(n2004), .Y(n1273) );
NAND2X1TS U1937 ( .A(n2001), .B(n1976), .Y(n1299) );
NOR2BX4TS U1938 ( .AN(n1300), .B(n1299), .Y(n1296) );
AOI211X2TS U1939 ( .A0(n2008), .A1(n1273), .B0(Raw_mant_NRM_SWR[5]), .C0(
n1278), .Y(n1274) );
AOI21X1TS U1940 ( .A0(n2045), .A1(n1994), .B0(n1275), .Y(n1285) );
NOR2BX1TS U1941 ( .AN(n1277), .B(n1276), .Y(n1280) );
NAND3X4TS U1942 ( .A(n1304), .B(n1975), .C(n2008), .Y(n1301) );
OAI22X1TS U1943 ( .A0(n2004), .A1(n1301), .B0(n1278), .B1(n1975), .Y(n1279)
);
BUFX3TS U1944 ( .A(n1472), .Y(n1888) );
INVX2TS U1945 ( .A(n1908), .Y(n1517) );
CLKBUFX2TS U1946 ( .A(n1517), .Y(n1423) );
BUFX3TS U1947 ( .A(n1423), .Y(n1567) );
AOI32X1TS U1948 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1908), .A2(n1888),
.B0(shift_value_SHT2_EWR[2]), .B1(n1567), .Y(n1281) );
NAND2X1TS U1949 ( .A(n991), .B(LZD_output_NRM2_EW[2]), .Y(n1282) );
NAND2X1TS U1950 ( .A(n1284), .B(Raw_mant_NRM_SWR[14]), .Y(n1349) );
INVX2TS U1951 ( .A(n1285), .Y(n1286) );
OAI211XLTS U1952 ( .A0(n1287), .A1(n1329), .B0(n1349), .C0(n1286), .Y(n1291)
);
NOR2X1TS U1953 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1298)
);
OAI31X1TS U1954 ( .A0(n1301), .A1(n1289), .A2(n1980), .B0(n1288), .Y(n1290)
);
AOI211X1TS U1955 ( .A0(n1292), .A1(Raw_mant_NRM_SWR[12]), .B0(n1291), .C0(
n1290), .Y(n1295) );
BUFX3TS U1956 ( .A(n1472), .Y(n1890) );
NAND2X1TS U1957 ( .A(n991), .B(LZD_output_NRM2_EW[3]), .Y(n1293) );
AOI32X1TS U1958 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1908), .A2(n1890),
.B0(shift_value_SHT2_EWR[3]), .B1(n1517), .Y(n1294) );
OAI21X1TS U1959 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1296), .Y(n1297) );
OAI21X4TS U1960 ( .A0(n1298), .A1(n1301), .B0(n1297), .Y(n1347) );
AOI22X1TS U1961 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1335), .B0(n1300), .B1(
n1299), .Y(n1302) );
AOI32X1TS U1962 ( .A0(n1980), .A1(n1302), .A2(n2046), .B0(n1301), .B1(n1302),
.Y(n1303) );
AOI211X1TS U1963 ( .A0(n1304), .A1(Raw_mant_NRM_SWR[4]), .B0(n1347), .C0(
n1303), .Y(n1307) );
NAND2X1TS U1964 ( .A(n1472), .B(LZD_output_NRM2_EW[4]), .Y(n1305) );
AOI32X1TS U1965 ( .A0(Shift_amount_SHT1_EWR[4]), .A1(n1908), .A2(n1890),
.B0(shift_value_SHT2_EWR[4]), .B1(n1517), .Y(n1306) );
BUFX3TS U1966 ( .A(n2040), .Y(n1969) );
NAND2X1TS U1967 ( .A(n1582), .B(final_result_ieee[29]), .Y(n1309) );
INVX2TS U1968 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n1312) );
NAND2X1TS U1969 ( .A(n1582), .B(final_result_ieee[27]), .Y(n1311) );
INVX2TS U1970 ( .A(exp_rslt_NRM2_EW1[0]), .Y(n1314) );
NAND2X1TS U1971 ( .A(n1582), .B(final_result_ieee[23]), .Y(n1313) );
INVX2TS U1972 ( .A(exp_rslt_NRM2_EW1[1]), .Y(n1316) );
NAND2X1TS U1973 ( .A(n1582), .B(final_result_ieee[24]), .Y(n1315) );
NAND2X1TS U1974 ( .A(n1582), .B(final_result_ieee[26]), .Y(n1317) );
INVX2TS U1975 ( .A(exp_rslt_NRM2_EW1[5]), .Y(n1576) );
NAND2X1TS U1976 ( .A(n1582), .B(final_result_ieee[28]), .Y(n1319) );
NAND2X1TS U1977 ( .A(n1582), .B(final_result_ieee[25]), .Y(n1320) );
INVX2TS U1978 ( .A(n1323), .Y(n1559) );
NAND2X1TS U1979 ( .A(n1559), .B(Raw_mant_NRM_SWR[24]), .Y(n1326) );
INVX2TS U1980 ( .A(n1461), .Y(n1468) );
NAND2X1TS U1981 ( .A(n1495), .B(Raw_mant_NRM_SWR[1]), .Y(n1325) );
NAND2X1TS U1982 ( .A(n1940), .B(DmP_mant_SHT1_SW[22]), .Y(n1324) );
NAND3X1TS U1983 ( .A(n1326), .B(n1325), .C(n1324), .Y(n1477) );
INVX2TS U1984 ( .A(n1477), .Y(n1563) );
AOI21X1TS U1985 ( .A0(n2016), .A1(Raw_mant_NRM_SWR[20]), .B0(
Raw_mant_NRM_SWR[22]), .Y(n1327) );
AOI211X1TS U1986 ( .A0(n1335), .A1(Raw_mant_NRM_SWR[6]), .B0(n1334), .C0(
n1333), .Y(n1339) );
AOI31X1TS U1987 ( .A0(n1339), .A1(n1338), .A2(n1337), .B0(n1888), .Y(n1882)
);
AOI211X4TS U1988 ( .A0(Shift_amount_SHT1_EWR[0]), .A1(n1890), .B0(n1882),
.C0(n1464), .Y(n1561) );
INVX2TS U1989 ( .A(n1461), .Y(n1495) );
AOI21X1TS U1990 ( .A0(n1340), .A1(Raw_mant_NRM_SWR[15]), .B0(
Raw_mant_NRM_SWR[19]), .Y(n1342) );
INVX2TS U1991 ( .A(n1343), .Y(n1352) );
AOI21X1TS U1992 ( .A0(n1153), .A1(Raw_mant_NRM_SWR[25]), .B0(n1890), .Y(
n1355) );
AOI22X1TS U1993 ( .A0(n1517), .A1(Data_array_SWR[24]), .B0(n972), .B1(n1560),
.Y(n1356) );
BUFX3TS U1994 ( .A(n1571), .Y(n1550) );
AOI22X1TS U1995 ( .A0(intDX_EWSW[3]), .A1(n1377), .B0(DmP_EXP_EWSW[3]), .B1(
n1550), .Y(n1357) );
BUFX3TS U1996 ( .A(n1363), .Y(n1374) );
AOI22X1TS U1997 ( .A0(intDX_EWSW[5]), .A1(n1383), .B0(DmP_EXP_EWSW[5]), .B1(
n1374), .Y(n1358) );
INVX2TS U1998 ( .A(n1362), .Y(n1549) );
AOI22X1TS U1999 ( .A0(intDX_EWSW[0]), .A1(n1383), .B0(DmP_EXP_EWSW[0]), .B1(
n1550), .Y(n1359) );
AOI22X1TS U2000 ( .A0(intDX_EWSW[2]), .A1(n1383), .B0(DmP_EXP_EWSW[2]), .B1(
n1550), .Y(n1360) );
AOI22X1TS U2001 ( .A0(intDY_EWSW[28]), .A1(n1383), .B0(DMP_EXP_EWSW[28]),
.B1(n1550), .Y(n1361) );
INVX2TS U2002 ( .A(n1362), .Y(n1388) );
BUFX3TS U2003 ( .A(n1363), .Y(n1887) );
AOI22X1TS U2004 ( .A0(DmP_EXP_EWSW[27]), .A1(n1887), .B0(intDX_EWSW[27]),
.B1(n1383), .Y(n1364) );
BUFX3TS U2005 ( .A(n1377), .Y(n1375) );
AOI22X1TS U2006 ( .A0(intDX_EWSW[7]), .A1(n1375), .B0(DmP_EXP_EWSW[7]), .B1(
n1374), .Y(n1365) );
AOI22X1TS U2007 ( .A0(intDX_EWSW[6]), .A1(n1375), .B0(DmP_EXP_EWSW[6]), .B1(
n1374), .Y(n1366) );
AOI22X1TS U2008 ( .A0(intDX_EWSW[16]), .A1(n1375), .B0(DmP_EXP_EWSW[16]),
.B1(n1374), .Y(n1367) );
AOI22X1TS U2009 ( .A0(intDX_EWSW[10]), .A1(n1375), .B0(DmP_EXP_EWSW[10]),
.B1(n1550), .Y(n1368) );
AOI22X1TS U2010 ( .A0(intDX_EWSW[14]), .A1(n1375), .B0(DmP_EXP_EWSW[14]),
.B1(n1374), .Y(n1369) );
AOI22X1TS U2011 ( .A0(intDX_EWSW[11]), .A1(n1375), .B0(DmP_EXP_EWSW[11]),
.B1(n1374), .Y(n1370) );
AOI22X1TS U2012 ( .A0(intDX_EWSW[12]), .A1(n1375), .B0(DmP_EXP_EWSW[12]),
.B1(n1374), .Y(n1371) );
AOI22X1TS U2013 ( .A0(intDX_EWSW[8]), .A1(n1375), .B0(DmP_EXP_EWSW[8]), .B1(
n1374), .Y(n1372) );
AOI22X1TS U2014 ( .A0(intDX_EWSW[9]), .A1(n1375), .B0(DmP_EXP_EWSW[9]), .B1(
n1374), .Y(n1373) );
AOI22X1TS U2015 ( .A0(intDX_EWSW[13]), .A1(n1375), .B0(DmP_EXP_EWSW[13]),
.B1(n1374), .Y(n1376) );
AOI22X1TS U2016 ( .A0(intDX_EWSW[18]), .A1(n1514), .B0(DmP_EXP_EWSW[18]),
.B1(n1887), .Y(n1378) );
AOI22X1TS U2017 ( .A0(intDX_EWSW[19]), .A1(n1514), .B0(DmP_EXP_EWSW[19]),
.B1(n1887), .Y(n1379) );
AOI22X1TS U2018 ( .A0(intDX_EWSW[22]), .A1(n1514), .B0(DmP_EXP_EWSW[22]),
.B1(n1887), .Y(n1380) );
AOI22X1TS U2019 ( .A0(intDX_EWSW[17]), .A1(n1514), .B0(DmP_EXP_EWSW[17]),
.B1(n1887), .Y(n1381) );
AOI22X1TS U2020 ( .A0(intDX_EWSW[20]), .A1(n1514), .B0(DmP_EXP_EWSW[20]),
.B1(n1887), .Y(n1382) );
AOI22X1TS U2021 ( .A0(intDY_EWSW[30]), .A1(n1383), .B0(DMP_EXP_EWSW[30]),
.B1(n1550), .Y(n1384) );
AOI22X1TS U2022 ( .A0(intDY_EWSW[29]), .A1(n1377), .B0(DMP_EXP_EWSW[29]),
.B1(n1550), .Y(n1385) );
AOI22X1TS U2023 ( .A0(intDX_EWSW[21]), .A1(n1514), .B0(DmP_EXP_EWSW[21]),
.B1(n1887), .Y(n1386) );
AOI22X1TS U2024 ( .A0(intDX_EWSW[15]), .A1(n1514), .B0(DmP_EXP_EWSW[15]),
.B1(n1887), .Y(n1387) );
AOI22X1TS U2025 ( .A0(intDX_EWSW[4]), .A1(n1377), .B0(DmP_EXP_EWSW[4]), .B1(
n1550), .Y(n1389) );
AOI22X1TS U2026 ( .A0(intDX_EWSW[1]), .A1(n1383), .B0(DmP_EXP_EWSW[1]), .B1(
n1550), .Y(n1390) );
NAND2X1TS U2027 ( .A(n1468), .B(Raw_mant_NRM_SWR[2]), .Y(n1394) );
NAND2X1TS U2028 ( .A(n1472), .B(DmP_mant_SHT1_SW[21]), .Y(n1393) );
NAND3X1TS U2029 ( .A(n1395), .B(n1394), .C(n1393), .Y(n1476) );
INVX2TS U2030 ( .A(n1476), .Y(n1565) );
AOI22X1TS U2031 ( .A0(n1559), .A1(Raw_mant_NRM_SWR[22]), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1890), .Y(n1396) );
AOI22X1TS U2032 ( .A0(n1567), .A1(Data_array_SWR[22]), .B0(n1353), .B1(n1487), .Y(n1401) );
NAND2X4TS U2033 ( .A(n1908), .B(n1397), .Y(n1569) );
AOI22X1TS U2034 ( .A0(n970), .A1(n1477), .B0(n988), .B1(n1560), .Y(n1400) );
NAND2X1TS U2035 ( .A(n1559), .B(Raw_mant_NRM_SWR[3]), .Y(n1404) );
NAND2X1TS U2036 ( .A(n1468), .B(Raw_mant_NRM_SWR[22]), .Y(n1403) );
INVX2TS U2037 ( .A(n1519), .Y(n1412) );
NAND2X1TS U2038 ( .A(n1464), .B(Raw_mant_NRM_SWR[5]), .Y(n1407) );
NAND2X1TS U2039 ( .A(n1468), .B(Raw_mant_NRM_SWR[20]), .Y(n1406) );
NAND3X1TS U2040 ( .A(n1407), .B(n1406), .C(n1405), .Y(n1428) );
AOI22X1TS U2041 ( .A0(n1423), .A1(Data_array_SWR[3]), .B0(n990), .B1(n1428),
.Y(n1411) );
INVX2TS U2042 ( .A(n1461), .Y(n1516) );
AOI22X1TS U2043 ( .A0(n1495), .A1(Raw_mant_NRM_SWR[21]), .B0(
DmP_mant_SHT1_SW[2]), .B1(n1940), .Y(n1408) );
AOI22X1TS U2044 ( .A0(n1516), .A1(Raw_mant_NRM_SWR[19]), .B0(
DmP_mant_SHT1_SW[4]), .B1(n1940), .Y(n1409) );
AOI22X1TS U2045 ( .A0(n972), .A1(n1437), .B0(n1520), .B1(n1435), .Y(n1410)
);
NAND2X1TS U2046 ( .A(n1464), .B(Raw_mant_NRM_SWR[2]), .Y(n1415) );
NAND2X1TS U2047 ( .A(n1468), .B(Raw_mant_NRM_SWR[23]), .Y(n1414) );
AOI22X1TS U2048 ( .A0(n1517), .A1(Data_array_SWR[1]), .B0(n990), .B1(n1519),
.Y(n1417) );
OAI2BB2X1TS U2049 ( .B0(n1482), .B1(n1980), .A0N(Raw_mant_NRM_SWR[24]),
.A1N(n1516), .Y(n1518) );
AOI22X1TS U2050 ( .A0(n971), .A1(n1518), .B0(n988), .B1(n1437), .Y(n1416) );
AOI22X1TS U2051 ( .A0(n1517), .A1(Data_array_SWR[2]), .B0(n970), .B1(n1437),
.Y(n1419) );
AOI22X1TS U2052 ( .A0(n1354), .A1(n1519), .B0(n988), .B1(n1428), .Y(n1418)
);
NAND2X1TS U2053 ( .A(n1559), .B(Raw_mant_NRM_SWR[7]), .Y(n1422) );
NAND2X1TS U2054 ( .A(n1495), .B(Raw_mant_NRM_SWR[18]), .Y(n1421) );
NAND3X1TS U2055 ( .A(n1422), .B(n1421), .C(n1420), .Y(n1436) );
INVX2TS U2056 ( .A(n1436), .Y(n1434) );
BUFX3TS U2057 ( .A(n1423), .Y(n1507) );
AOI222X4TS U2058 ( .A0(n1888), .A1(DmP_mant_SHT1_SW[7]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1464), .C0(n1468), .C1(Raw_mant_NRM_SWR[16]), .Y(n1448) );
INVX2TS U2059 ( .A(n1448), .Y(n1431) );
AOI22X1TS U2060 ( .A0(n1507), .A1(Data_array_SWR[7]), .B0(n1399), .B1(n1431),
.Y(n1427) );
AOI22X1TS U2061 ( .A0(n1495), .A1(Raw_mant_NRM_SWR[17]), .B0(
DmP_mant_SHT1_SW[6]), .B1(n1940), .Y(n1424) );
AOI22X1TS U2062 ( .A0(n1559), .A1(Raw_mant_NRM_SWR[10]), .B0(
DmP_mant_SHT1_SW[8]), .B1(n1888), .Y(n1425) );
AOI22X1TS U2063 ( .A0(n972), .A1(n1445), .B0(n1520), .B1(n1453), .Y(n1426)
);
INVX2TS U2064 ( .A(n1428), .Y(n1440) );
AOI22X1TS U2065 ( .A0(n1517), .A1(Data_array_SWR[5]), .B0(n990), .B1(n1436),
.Y(n1430) );
AOI22X1TS U2066 ( .A0(n1354), .A1(n1435), .B0(n1520), .B1(n1445), .Y(n1429)
);
AOI22X1TS U2067 ( .A0(n1517), .A1(Data_array_SWR[6]), .B0(n970), .B1(n1445),
.Y(n1433) );
AOI22X1TS U2068 ( .A0(n1353), .A1(n1435), .B0(n969), .B1(n1431), .Y(n1432)
);
AOI22X1TS U2069 ( .A0(n1507), .A1(Data_array_SWR[4]), .B0(n970), .B1(n1435),
.Y(n1439) );
AOI22X1TS U2070 ( .A0(n971), .A1(n1437), .B0(n988), .B1(n1436), .Y(n1438) );
AOI222X4TS U2071 ( .A0(n1888), .A1(DmP_mant_SHT1_SW[9]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1559), .C0(n1516), .C1(
Raw_mant_NRM_SWR[14]), .Y(n1456) );
INVX2TS U2072 ( .A(n1456), .Y(n1444) );
AOI22X1TS U2073 ( .A0(n1507), .A1(Data_array_SWR[9]), .B0(n970), .B1(n1444),
.Y(n1443) );
AOI22X1TS U2074 ( .A0(n1468), .A1(Raw_mant_NRM_SWR[13]), .B0(
DmP_mant_SHT1_SW[10]), .B1(n1888), .Y(n1441) );
AOI22X1TS U2075 ( .A0(n1354), .A1(n1453), .B0(n969), .B1(n1503), .Y(n1442)
);
AOI22X1TS U2076 ( .A0(n1507), .A1(Data_array_SWR[8]), .B0(n1399), .B1(n1453),
.Y(n1447) );
AOI22X1TS U2077 ( .A0(n1353), .A1(n1445), .B0(n969), .B1(n1444), .Y(n1446)
);
AOI222X4TS U2078 ( .A0(n1888), .A1(DmP_mant_SHT1_SW[11]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1464), .C0(n1468), .C1(
Raw_mant_NRM_SWR[12]), .Y(n1513) );
INVX2TS U2079 ( .A(n1513), .Y(n1452) );
AOI22X1TS U2080 ( .A0(n1507), .A1(Data_array_SWR[11]), .B0(n990), .B1(n1452),
.Y(n1451) );
AOI22X1TS U2081 ( .A0(n1516), .A1(Raw_mant_NRM_SWR[11]), .B0(
DmP_mant_SHT1_SW[12]), .B1(n1888), .Y(n1449) );
AOI22X1TS U2082 ( .A0(n1354), .A1(n1503), .B0(n969), .B1(n1509), .Y(n1450)
);
AOI22X1TS U2083 ( .A0(n1507), .A1(Data_array_SWR[10]), .B0(n990), .B1(n1503),
.Y(n1455) );
AOI22X1TS U2084 ( .A0(n971), .A1(n1453), .B0(n969), .B1(n1452), .Y(n1454) );
NAND2X1TS U2085 ( .A(n1464), .B(Raw_mant_NRM_SWR[21]), .Y(n1459) );
NAND2X1TS U2086 ( .A(n1495), .B(Raw_mant_NRM_SWR[4]), .Y(n1458) );
NAND2X1TS U2087 ( .A(n1472), .B(DmP_mant_SHT1_SW[19]), .Y(n1457) );
NAND3X1TS U2088 ( .A(n1459), .B(n1458), .C(n1457), .Y(n1491) );
INVX2TS U2089 ( .A(n1491), .Y(n1480) );
AOI22X1TS U2090 ( .A0(n1567), .A1(Data_array_SWR[20]), .B0(n970), .B1(n1487),
.Y(n1463) );
AOI22X1TS U2091 ( .A0(n1464), .A1(Raw_mant_NRM_SWR[20]), .B0(
DmP_mant_SHT1_SW[18]), .B1(n1940), .Y(n1460) );
AOI22X1TS U2092 ( .A0(n1353), .A1(n1490), .B0(n1520), .B1(n1476), .Y(n1462)
);
NAND2X1TS U2093 ( .A(n1464), .B(Raw_mant_NRM_SWR[17]), .Y(n1467) );
NAND2X1TS U2094 ( .A(n1516), .B(Raw_mant_NRM_SWR[8]), .Y(n1466) );
NAND3X1TS U2095 ( .A(n1467), .B(n1466), .C(n1465), .Y(n1499) );
INVX2TS U2096 ( .A(n1499), .Y(n1485) );
NAND2X1TS U2097 ( .A(n1559), .B(Raw_mant_NRM_SWR[19]), .Y(n1471) );
NAND2X1TS U2098 ( .A(n1516), .B(Raw_mant_NRM_SWR[6]), .Y(n1470) );
NAND2X1TS U2099 ( .A(n1472), .B(DmP_mant_SHT1_SW[17]), .Y(n1469) );
NAND3X1TS U2100 ( .A(n1471), .B(n1470), .C(n1469), .Y(n1486) );
AOI22X1TS U2101 ( .A0(n1567), .A1(Data_array_SWR[17]), .B0(n970), .B1(n1486),
.Y(n1475) );
AOI22X1TS U2102 ( .A0(n1516), .A1(Raw_mant_NRM_SWR[7]), .B0(
DmP_mant_SHT1_SW[16]), .B1(n1472), .Y(n1473) );
AOI22X1TS U2103 ( .A0(n972), .A1(n1496), .B0(n988), .B1(n1490), .Y(n1474) );
AOI22X1TS U2104 ( .A0(n1567), .A1(Data_array_SWR[21]), .B0(n990), .B1(n1476),
.Y(n1479) );
AOI22X1TS U2105 ( .A0(n972), .A1(n1487), .B0(n988), .B1(n1477), .Y(n1478) );
AOI22X1TS U2106 ( .A0(n1567), .A1(Data_array_SWR[16]), .B0(n990), .B1(n1496),
.Y(n1484) );
AOI22X1TS U2107 ( .A0(n1495), .A1(Raw_mant_NRM_SWR[9]), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1888), .Y(n1481) );
AOI22X1TS U2108 ( .A0(n971), .A1(n1508), .B0(n988), .B1(n1486), .Y(n1483) );
INVX2TS U2109 ( .A(n1486), .Y(n1494) );
AOI22X1TS U2110 ( .A0(n1567), .A1(Data_array_SWR[19]), .B0(n970), .B1(n1491),
.Y(n1489) );
AOI22X1TS U2111 ( .A0(n972), .A1(n1490), .B0(n1520), .B1(n1487), .Y(n1488)
);
AOI22X1TS U2112 ( .A0(n1567), .A1(Data_array_SWR[18]), .B0(n970), .B1(n1490),
.Y(n1493) );
AOI22X1TS U2113 ( .A0(n971), .A1(n1496), .B0(n1520), .B1(n1491), .Y(n1492)
);
AOI222X4TS U2114 ( .A0(n1940), .A1(DmP_mant_SHT1_SW[13]), .B0(
Raw_mant_NRM_SWR[15]), .B1(n1559), .C0(n1495), .C1(
Raw_mant_NRM_SWR[10]), .Y(n1502) );
AOI22X1TS U2115 ( .A0(n1354), .A1(n1508), .B0(n969), .B1(n1496), .Y(n1497)
);
AOI22X1TS U2116 ( .A0(n1507), .A1(Data_array_SWR[14]), .B0(n970), .B1(n1508),
.Y(n1501) );
AOI22X1TS U2117 ( .A0(n1353), .A1(n1509), .B0(n1520), .B1(n1499), .Y(n1500)
);
INVX2TS U2118 ( .A(n1502), .Y(n1506) );
AOI22X1TS U2119 ( .A0(n971), .A1(n1503), .B0(n969), .B1(n1506), .Y(n1504) );
AOI22X1TS U2120 ( .A0(n1507), .A1(Data_array_SWR[13]), .B0(n990), .B1(n1506),
.Y(n1512) );
AOI22X1TS U2121 ( .A0(n972), .A1(n1509), .B0(n969), .B1(n1508), .Y(n1511) );
AOI22X1TS U2122 ( .A0(intDX_EWSW[22]), .A1(n1530), .B0(DMP_EXP_EWSW[22]),
.B1(n1363), .Y(n1515) );
AOI22X1TS U2123 ( .A0(n1517), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1495), .Y(n1522) );
AOI21X1TS U2124 ( .A0(n988), .A1(n1519), .B0(n1518), .Y(n1521) );
AOI22X1TS U2125 ( .A0(intDX_EWSW[18]), .A1(n1530), .B0(DMP_EXP_EWSW[18]),
.B1(n1991), .Y(n1525) );
AOI22X1TS U2126 ( .A0(intDX_EWSW[17]), .A1(n1530), .B0(DMP_EXP_EWSW[17]),
.B1(n1363), .Y(n1526) );
AOI22X1TS U2127 ( .A0(intDX_EWSW[20]), .A1(n1530), .B0(DMP_EXP_EWSW[20]),
.B1(n1991), .Y(n1527) );
AOI22X1TS U2128 ( .A0(intDX_EWSW[21]), .A1(n1530), .B0(DMP_EXP_EWSW[21]),
.B1(n1363), .Y(n1528) );
AOI22X1TS U2129 ( .A0(intDX_EWSW[0]), .A1(n1530), .B0(DMP_EXP_EWSW[0]), .B1(
n1571), .Y(n1529) );
AOI22X1TS U2130 ( .A0(intDX_EWSW[16]), .A1(n1530), .B0(DMP_EXP_EWSW[16]),
.B1(n1991), .Y(n1531) );
AOI22X1TS U2131 ( .A0(intDX_EWSW[7]), .A1(n1545), .B0(DMP_EXP_EWSW[7]), .B1(
n1544), .Y(n1532) );
AOI22X1TS U2132 ( .A0(intDX_EWSW[19]), .A1(n1545), .B0(DMP_EXP_EWSW[19]),
.B1(n1991), .Y(n1533) );
AOI22X1TS U2133 ( .A0(intDX_EWSW[10]), .A1(n1545), .B0(DMP_EXP_EWSW[10]),
.B1(n1544), .Y(n1534) );
AOI22X1TS U2134 ( .A0(intDX_EWSW[4]), .A1(n1572), .B0(DMP_EXP_EWSW[4]), .B1(
n1544), .Y(n1535) );
AOI22X1TS U2135 ( .A0(intDX_EWSW[5]), .A1(n1572), .B0(DMP_EXP_EWSW[5]), .B1(
n1544), .Y(n1536) );
AOI22X1TS U2136 ( .A0(intDX_EWSW[6]), .A1(n1572), .B0(DMP_EXP_EWSW[6]), .B1(
n1544), .Y(n1537) );
AOI22X1TS U2137 ( .A0(intDX_EWSW[14]), .A1(n1545), .B0(DMP_EXP_EWSW[14]),
.B1(n1991), .Y(n1538) );
AOI22X1TS U2138 ( .A0(intDX_EWSW[9]), .A1(n1545), .B0(DMP_EXP_EWSW[9]), .B1(
n1544), .Y(n1539) );
AOI22X1TS U2139 ( .A0(intDX_EWSW[11]), .A1(n1545), .B0(DMP_EXP_EWSW[11]),
.B1(n1991), .Y(n1540) );
AOI22X1TS U2140 ( .A0(intDX_EWSW[8]), .A1(n1545), .B0(DMP_EXP_EWSW[8]), .B1(
n1544), .Y(n1541) );
AOI22X1TS U2141 ( .A0(intDX_EWSW[12]), .A1(n1545), .B0(DMP_EXP_EWSW[12]),
.B1(n1544), .Y(n1542) );
INVX2TS U2142 ( .A(n1548), .Y(n1553) );
AOI22X1TS U2143 ( .A0(intDX_EWSW[31]), .A1(n1551), .B0(SIGN_FLAG_EXP), .B1(
n1550), .Y(n1552) );
AOI22X1TS U2144 ( .A0(intDX_EWSW[2]), .A1(n1572), .B0(DMP_EXP_EWSW[2]), .B1(
n1571), .Y(n1555) );
AOI22X1TS U2145 ( .A0(DMP_EXP_EWSW[27]), .A1(n1887), .B0(intDX_EWSW[27]),
.B1(n1572), .Y(n1557) );
AOI22X1TS U2146 ( .A0(intDX_EWSW[1]), .A1(n1572), .B0(DMP_EXP_EWSW[1]), .B1(
n1571), .Y(n1558) );
AOI21X1TS U2147 ( .A0(n1561), .A1(n1560), .B0(n1559), .Y(n1910) );
AOI21X1TS U2148 ( .A0(n1567), .A1(Data_array_SWR[23]), .B0(n1566), .Y(n1568)
);
INVX2TS U2149 ( .A(n1570), .Y(n644) );
AOI222X1TS U2150 ( .A0(n1572), .A1(intDX_EWSW[23]), .B0(DMP_EXP_EWSW[23]),
.B1(n1571), .C0(intDY_EWSW[23]), .C1(n1383), .Y(n1573) );
INVX2TS U2151 ( .A(n1573), .Y(n810) );
INVX2TS U2152 ( .A(exp_rslt_NRM2_EW1[7]), .Y(n1580) );
NAND3BX1TS U2153 ( .AN(n1576), .B(exp_rslt_NRM2_EW1[6]), .C(n1575), .Y(n1577) );
NOR2X2TS U2154 ( .A(n1580), .B(n1577), .Y(n1579) );
OAI2BB1X4TS U2155 ( .A0N(n1579), .A1N(n1578), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1883) );
OAI2BB2XLTS U2156 ( .B0(n1883), .B1(n1580), .A0N(final_result_ieee[30]),
.A1N(n1582), .Y(n834) );
OAI2BB2XLTS U2157 ( .B0(n1583), .B1(n1883), .A0N(final_result_ieee[31]),
.A1N(n1582), .Y(n621) );
NOR2BX1TS U2158 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n1584)
);
XOR2X1TS U2159 ( .A(n1997), .B(n1584), .Y(DP_OP_15J131_122_6956_n14) );
NOR2BX1TS U2160 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n1585)
);
XOR2X1TS U2161 ( .A(n1997), .B(n1585), .Y(DP_OP_15J131_122_6956_n15) );
NOR2BX1TS U2162 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n1586)
);
XOR2X1TS U2163 ( .A(n1997), .B(n1586), .Y(DP_OP_15J131_122_6956_n16) );
NOR2BX1TS U2164 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n1587)
);
XOR2X1TS U2165 ( .A(n1997), .B(n1587), .Y(DP_OP_15J131_122_6956_n17) );
AOI32X4TS U2166 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1588), .B1(n2012), .Y(n1891)
);
MXI2X1TS U2167 ( .A(n1875), .B(n1589), .S0(n1891), .Y(n946) );
BUFX3TS U2168 ( .A(n1591), .Y(n1592) );
AOI22X1TS U2169 ( .A0(Data_array_SWR[9]), .A1(n980), .B0(Data_array_SWR[1]),
.B1(n982), .Y(n1597) );
AOI22X1TS U2170 ( .A0(Data_array_SWR[13]), .A1(n968), .B0(Data_array_SWR[5]),
.B1(n984), .Y(n1596) );
OAI211X1TS U2171 ( .A0(n1638), .A1(n1979), .B0(n1597), .C0(n1596), .Y(n1663)
);
AOI21X1TS U2172 ( .A0(left_right_SHT2), .A1(n1663), .B0(n1598), .Y(n1971) );
MXI2X1TS U2173 ( .A(n1971), .B(n2063), .S0(n1629), .Y(n542) );
OAI21X1TS U2174 ( .A0(n1613), .A1(n2037), .B0(n1612), .Y(n1599) );
AOI22X1TS U2175 ( .A0(Data_array_SWR[10]), .A1(n979), .B0(Data_array_SWR[2]),
.B1(n981), .Y(n1601) );
AOI22X1TS U2176 ( .A0(Data_array_SWR[14]), .A1(n967), .B0(Data_array_SWR[6]),
.B1(n983), .Y(n1600) );
OAI211X1TS U2177 ( .A0(n1641), .A1(n978), .B0(n1601), .C0(n1600), .Y(n1658)
);
AOI21X1TS U2178 ( .A0(n1634), .A1(n1658), .B0(n1602), .Y(n1968) );
MXI2X1TS U2179 ( .A(n1968), .B(n2051), .S0(n1923), .Y(n543) );
OAI21X1TS U2180 ( .A0(n1613), .A1(n2038), .B0(n1612), .Y(n1603) );
AOI22X1TS U2181 ( .A0(Data_array_SWR[11]), .A1(n979), .B0(Data_array_SWR[3]),
.B1(n981), .Y(n1605) );
AOI22X1TS U2182 ( .A0(Data_array_SWR[15]), .A1(n967), .B0(Data_array_SWR[7]),
.B1(n983), .Y(n1604) );
OAI211X1TS U2183 ( .A0(n1644), .A1(n978), .B0(n1605), .C0(n1604), .Y(n1655)
);
AOI21X1TS U2184 ( .A0(n1634), .A1(n1655), .B0(n1607), .Y(n1966) );
MXI2X1TS U2185 ( .A(n1966), .B(n2064), .S0(n1923), .Y(n544) );
OAI2BB1X1TS U2186 ( .A0N(n1615), .A1N(Data_array_SWR[20]), .B0(n1612), .Y(
n1608) );
AOI22X1TS U2187 ( .A0(Data_array_SWR[12]), .A1(n980), .B0(Data_array_SWR[4]),
.B1(n982), .Y(n1611) );
AOI22X1TS U2188 ( .A0(Data_array_SWR[16]), .A1(n967), .B0(Data_array_SWR[8]),
.B1(n983), .Y(n1610) );
OAI211X1TS U2189 ( .A0(n1647), .A1(n1979), .B0(n1611), .C0(n1610), .Y(n1652)
);
AOI21X1TS U2190 ( .A0(n1634), .A1(n1652), .B0(n1616), .Y(n1964) );
MXI2X1TS U2191 ( .A(n1964), .B(n2052), .S0(n1923), .Y(n545) );
AOI22X1TS U2192 ( .A0(Data_array_SWR[13]), .A1(n980), .B0(Data_array_SWR[5]),
.B1(n982), .Y(n1618) );
AOI22X1TS U2193 ( .A0(Data_array_SWR[17]), .A1(n967), .B0(Data_array_SWR[9]),
.B1(n983), .Y(n1617) );
OAI211X1TS U2194 ( .A0(n1650), .A1(n978), .B0(n1618), .C0(n1617), .Y(n1649)
);
AOI21X1TS U2195 ( .A0(left_right_SHT2), .A1(n1649), .B0(n1619), .Y(n1963) );
MXI2X1TS U2196 ( .A(n1963), .B(n2065), .S0(n1923), .Y(n546) );
AOI22X1TS U2197 ( .A0(Data_array_SWR[18]), .A1(n968), .B0(Data_array_SWR[10]), .B1(n983), .Y(n1621) );
AOI22X1TS U2198 ( .A0(Data_array_SWR[14]), .A1(n979), .B0(Data_array_SWR[6]),
.B1(n981), .Y(n1620) );
OAI211X1TS U2199 ( .A0(n1653), .A1(n978), .B0(n1621), .C0(n1620), .Y(n1646)
);
AOI21X1TS U2200 ( .A0(n1634), .A1(n1646), .B0(n1622), .Y(n1962) );
MXI2X1TS U2201 ( .A(n1962), .B(n2053), .S0(n1938), .Y(n547) );
AOI22X1TS U2202 ( .A0(Data_array_SWR[19]), .A1(n968), .B0(Data_array_SWR[11]), .B1(n984), .Y(n1624) );
AOI22X1TS U2203 ( .A0(Data_array_SWR[15]), .A1(n979), .B0(Data_array_SWR[7]),
.B1(n981), .Y(n1623) );
OAI211X1TS U2204 ( .A0(n1656), .A1(n978), .B0(n1624), .C0(n1623), .Y(n1643)
);
AOI21X1TS U2205 ( .A0(n986), .A1(n1643), .B0(n1625), .Y(n1961) );
MXI2X1TS U2206 ( .A(n1961), .B(n2066), .S0(n1938), .Y(n548) );
AOI22X1TS U2207 ( .A0(Data_array_SWR[20]), .A1(n968), .B0(Data_array_SWR[12]), .B1(n984), .Y(n1627) );
AOI22X1TS U2208 ( .A0(Data_array_SWR[16]), .A1(n979), .B0(Data_array_SWR[8]),
.B1(n981), .Y(n1626) );
OAI211X1TS U2209 ( .A0(n1659), .A1(n978), .B0(n1627), .C0(n1626), .Y(n1640)
);
AOI21X1TS U2210 ( .A0(n1634), .A1(n1640), .B0(n1628), .Y(n1960) );
MXI2X1TS U2211 ( .A(n1960), .B(n2054), .S0(n1629), .Y(n549) );
AOI22X1TS U2212 ( .A0(Data_array_SWR[21]), .A1(n968), .B0(Data_array_SWR[13]), .B1(n984), .Y(n1631) );
AOI22X1TS U2213 ( .A0(Data_array_SWR[17]), .A1(n979), .B0(Data_array_SWR[9]),
.B1(n981), .Y(n1630) );
OAI211X1TS U2214 ( .A0(n1632), .A1(n978), .B0(n1631), .C0(n1630), .Y(n1637)
);
AOI21X1TS U2215 ( .A0(n1634), .A1(n1637), .B0(n1633), .Y(n1959) );
MXI2X1TS U2216 ( .A(n1959), .B(n2067), .S0(n1938), .Y(n550) );
AOI211X1TS U2217 ( .A0(n1637), .A1(n1662), .B0(n1636), .C0(n1660), .Y(n1951)
);
MXI2X1TS U2218 ( .A(n1951), .B(n2058), .S0(n1664), .Y(n557) );
AOI211X1TS U2219 ( .A0(n1640), .A1(n1662), .B0(n1639), .C0(n1660), .Y(n1952)
);
MXI2X1TS U2220 ( .A(n1952), .B(n2048), .S0(n1664), .Y(n558) );
AOI211X1TS U2221 ( .A0(n1643), .A1(n1662), .B0(n1642), .C0(n1660), .Y(n1953)
);
MXI2X1TS U2222 ( .A(n1953), .B(n2059), .S0(n1664), .Y(n559) );
AOI211X1TS U2223 ( .A0(n1646), .A1(n1662), .B0(n1645), .C0(n1660), .Y(n1954)
);
MXI2X1TS U2224 ( .A(n1954), .B(n2049), .S0(n1664), .Y(n560) );
AOI211X1TS U2225 ( .A0(n1649), .A1(n1662), .B0(n1648), .C0(n1660), .Y(n1955)
);
MXI2X1TS U2226 ( .A(n1955), .B(n2060), .S0(n1664), .Y(n561) );
AOI211X1TS U2227 ( .A0(n1652), .A1(n1662), .B0(n1651), .C0(n1660), .Y(n1956)
);
MXI2X1TS U2228 ( .A(n1956), .B(n2050), .S0(n1664), .Y(n562) );
AOI211X1TS U2229 ( .A0(n1655), .A1(n961), .B0(n1654), .C0(n1660), .Y(n1957)
);
MXI2X1TS U2230 ( .A(n1957), .B(n2061), .S0(n1664), .Y(n563) );
AOI211X1TS U2231 ( .A0(n1658), .A1(n961), .B0(n1657), .C0(n1660), .Y(n1958)
);
MXI2X1TS U2232 ( .A(n1958), .B(n2062), .S0(n1664), .Y(n564) );
AOI211X1TS U2233 ( .A0(n1663), .A1(n985), .B0(n1661), .C0(n1660), .Y(n1665)
);
MXI2X1TS U2234 ( .A(n1665), .B(n1995), .S0(n1664), .Y(n565) );
NAND2X1TS U2235 ( .A(n1668), .B(n1667), .Y(n1671) );
INVX2TS U2236 ( .A(n1671), .Y(n1669) );
XOR2X1TS U2237 ( .A(n1672), .B(n1671), .Y(n1673) );
AOI22X1TS U2238 ( .A0(n1673), .A1(n1194), .B0(Raw_mant_NRM_SWR[15]), .B1(
n1935), .Y(n1674) );
OAI2BB1X1TS U2239 ( .A0N(n1752), .A1N(n1675), .B0(n1674), .Y(n605) );
NAND2X1TS U2240 ( .A(n1677), .B(n1676), .Y(n1680) );
INVX2TS U2241 ( .A(n1680), .Y(n1678) );
XNOR2X1TS U2242 ( .A(n1679), .B(n1678), .Y(n1684) );
XNOR2X1TS U2243 ( .A(n1681), .B(n1680), .Y(n1682) );
AOI22X1TS U2244 ( .A0(n1682), .A1(n1194), .B0(Raw_mant_NRM_SWR[16]), .B1(
n1935), .Y(n1683) );
OAI2BB1X1TS U2245 ( .A0N(n1752), .A1N(n1684), .B0(n1683), .Y(n604) );
INVX2TS U2246 ( .A(n1685), .Y(n1687) );
NAND2X1TS U2247 ( .A(n1687), .B(n1686), .Y(n1690) );
INVX2TS U2248 ( .A(n1690), .Y(n1688) );
XOR2X1TS U2249 ( .A(n1691), .B(n1690), .Y(n1692) );
AOI22X1TS U2250 ( .A0(n1692), .A1(n1194), .B0(Raw_mant_NRM_SWR[17]), .B1(
n1935), .Y(n1693) );
OAI2BB1X1TS U2251 ( .A0N(n1752), .A1N(n1694), .B0(n1693), .Y(n603) );
NAND2X1TS U2252 ( .A(n1696), .B(n1695), .Y(n1699) );
INVX2TS U2253 ( .A(n1699), .Y(n1697) );
XNOR2X1TS U2254 ( .A(n1698), .B(n1697), .Y(n1703) );
XNOR2X1TS U2255 ( .A(n1700), .B(n1699), .Y(n1701) );
AOI22X1TS U2256 ( .A0(n1701), .A1(n1194), .B0(Raw_mant_NRM_SWR[24]), .B1(
n1935), .Y(n1702) );
OAI2BB1X1TS U2257 ( .A0N(n1752), .A1N(n1703), .B0(n1702), .Y(n596) );
INVX2TS U2258 ( .A(n1704), .Y(n1706) );
NAND2X1TS U2259 ( .A(n1706), .B(n1705), .Y(n1709) );
INVX2TS U2260 ( .A(n1709), .Y(n1707) );
XOR2X1TS U2261 ( .A(n1710), .B(n1709), .Y(n1711) );
BUFX3TS U2262 ( .A(n1921), .Y(n1834) );
AOI22X1TS U2263 ( .A0(n1711), .A1(n1795), .B0(Raw_mant_NRM_SWR[23]), .B1(
n1834), .Y(n1712) );
OAI2BB1X1TS U2264 ( .A0N(n1752), .A1N(n1713), .B0(n1712), .Y(n597) );
NAND2X1TS U2265 ( .A(n1715), .B(n1714), .Y(n1718) );
INVX2TS U2266 ( .A(n1718), .Y(n1716) );
XNOR2X1TS U2267 ( .A(n1717), .B(n1716), .Y(n1722) );
XNOR2X1TS U2268 ( .A(n1719), .B(n1718), .Y(n1720) );
AOI22X1TS U2269 ( .A0(n1720), .A1(n1795), .B0(Raw_mant_NRM_SWR[22]), .B1(
n1935), .Y(n1721) );
OAI2BB1X1TS U2270 ( .A0N(n1752), .A1N(n1722), .B0(n1721), .Y(n598) );
INVX2TS U2271 ( .A(n1723), .Y(n1725) );
NAND2X1TS U2272 ( .A(n1725), .B(n1724), .Y(n1728) );
INVX2TS U2273 ( .A(n1728), .Y(n1726) );
XOR2X1TS U2274 ( .A(n1729), .B(n1728), .Y(n1730) );
AOI22X1TS U2275 ( .A0(n1730), .A1(n1795), .B0(Raw_mant_NRM_SWR[19]), .B1(
n1935), .Y(n1731) );
OAI2BB1X1TS U2276 ( .A0N(n1752), .A1N(n1732), .B0(n1731), .Y(n601) );
NAND2X1TS U2277 ( .A(n1734), .B(n1733), .Y(n1737) );
INVX2TS U2278 ( .A(n1737), .Y(n1735) );
XNOR2X1TS U2279 ( .A(n1736), .B(n1735), .Y(n1741) );
XNOR2X1TS U2280 ( .A(n1738), .B(n1737), .Y(n1739) );
AOI22X1TS U2281 ( .A0(n1739), .A1(n1795), .B0(Raw_mant_NRM_SWR[20]), .B1(
n1834), .Y(n1740) );
OAI2BB1X1TS U2282 ( .A0N(n1752), .A1N(n1741), .B0(n1740), .Y(n600) );
INVX2TS U2283 ( .A(n1742), .Y(n1744) );
NAND2X1TS U2284 ( .A(n1744), .B(n1743), .Y(n1747) );
INVX2TS U2285 ( .A(n1747), .Y(n1745) );
XOR2X1TS U2286 ( .A(n1748), .B(n1747), .Y(n1749) );
AOI22X1TS U2287 ( .A0(n1749), .A1(n1795), .B0(Raw_mant_NRM_SWR[21]), .B1(
n1834), .Y(n1750) );
OAI2BB1X1TS U2288 ( .A0N(n1752), .A1N(n1751), .B0(n1750), .Y(n599) );
BUFX3TS U2289 ( .A(n1753), .Y(n1880) );
NAND2X1TS U2290 ( .A(n1755), .B(n1754), .Y(n1758) );
INVX2TS U2291 ( .A(n1758), .Y(n1756) );
XNOR2X1TS U2292 ( .A(n1757), .B(n1756), .Y(n1762) );
XNOR2X1TS U2293 ( .A(n1759), .B(n1758), .Y(n1760) );
AOI22X1TS U2294 ( .A0(n1760), .A1(n1795), .B0(Raw_mant_NRM_SWR[18]), .B1(
n1834), .Y(n1761) );
OAI2BB1X1TS U2295 ( .A0N(n1880), .A1N(n1762), .B0(n1761), .Y(n602) );
NAND2X1TS U2296 ( .A(n1764), .B(n1763), .Y(n1767) );
INVX2TS U2297 ( .A(n1767), .Y(n1765) );
XNOR2X1TS U2298 ( .A(n1766), .B(n1765), .Y(n1771) );
XNOR2X1TS U2299 ( .A(n1768), .B(n1767), .Y(n1769) );
AOI22X1TS U2300 ( .A0(n1769), .A1(n1795), .B0(Raw_mant_NRM_SWR[14]), .B1(
n1834), .Y(n1770) );
OAI2BB1X1TS U2301 ( .A0N(n1880), .A1N(n1771), .B0(n1770), .Y(n606) );
NAND2X1TS U2302 ( .A(n1774), .B(n1773), .Y(n1777) );
INVX2TS U2303 ( .A(n1777), .Y(n1775) );
XOR2X1TS U2304 ( .A(n1778), .B(n1777), .Y(n1779) );
AOI22X1TS U2305 ( .A0(n1779), .A1(n1795), .B0(Raw_mant_NRM_SWR[13]), .B1(
n1834), .Y(n1780) );
OAI2BB1X1TS U2306 ( .A0N(n1880), .A1N(n1781), .B0(n1780), .Y(n607) );
INVX2TS U2307 ( .A(n1782), .Y(n1828) );
INVX2TS U2308 ( .A(n1783), .Y(n1786) );
INVX2TS U2309 ( .A(n1784), .Y(n1785) );
NAND2X1TS U2310 ( .A(n1788), .B(n1787), .Y(n1793) );
INVX2TS U2311 ( .A(n1793), .Y(n1789) );
XNOR2X1TS U2312 ( .A(n1790), .B(n1789), .Y(n1798) );
XNOR2X1TS U2313 ( .A(n1794), .B(n1793), .Y(n1796) );
AOI22X1TS U2314 ( .A0(n1796), .A1(n1795), .B0(Raw_mant_NRM_SWR[11]), .B1(
n1834), .Y(n1797) );
OAI2BB1X1TS U2315 ( .A0N(n1880), .A1N(n1798), .B0(n1797), .Y(n609) );
NAND2X1TS U2316 ( .A(n1803), .B(n1802), .Y(n1808) );
INVX2TS U2317 ( .A(n1808), .Y(n1804) );
XNOR2X1TS U2318 ( .A(n1805), .B(n1804), .Y(n1812) );
XNOR2X1TS U2319 ( .A(n1809), .B(n1808), .Y(n1810) );
AOI22X1TS U2320 ( .A0(n1810), .A1(n1876), .B0(Raw_mant_NRM_SWR[12]), .B1(
n1834), .Y(n1811) );
OAI2BB1X1TS U2321 ( .A0N(n1880), .A1N(n1812), .B0(n1811), .Y(n608) );
NAND2X1TS U2322 ( .A(n1816), .B(n1815), .Y(n1819) );
INVX2TS U2323 ( .A(n1819), .Y(n1817) );
XNOR2X1TS U2324 ( .A(n1818), .B(n1817), .Y(n1823) );
XOR2X1TS U2325 ( .A(n1820), .B(n1819), .Y(n1821) );
AOI22X1TS U2326 ( .A0(n1821), .A1(n1876), .B0(Raw_mant_NRM_SWR[10]), .B1(
n1834), .Y(n1822) );
OAI2BB1X1TS U2327 ( .A0N(n1880), .A1N(n1823), .B0(n1822), .Y(n610) );
INVX2TS U2328 ( .A(n1824), .Y(n1826) );
NAND2X1TS U2329 ( .A(n1826), .B(n1825), .Y(n1832) );
INVX2TS U2330 ( .A(n1832), .Y(n1827) );
AOI21X1TS U2331 ( .A0(n1874), .A1(n1831), .B0(n1830), .Y(n1848) );
XNOR2X1TS U2332 ( .A(n1833), .B(n1832), .Y(n1835) );
AOI22X1TS U2333 ( .A0(n1835), .A1(n1876), .B0(Raw_mant_NRM_SWR[9]), .B1(
n1834), .Y(n1836) );
OAI2BB1X1TS U2334 ( .A0N(n1880), .A1N(n1837), .B0(n1836), .Y(n611) );
AOI21X1TS U2335 ( .A0(n1868), .A1(n1839), .B0(n1838), .Y(n1856) );
INVX2TS U2336 ( .A(n1842), .Y(n1844) );
NAND2X1TS U2337 ( .A(n1844), .B(n1843), .Y(n1847) );
INVX2TS U2338 ( .A(n1847), .Y(n1845) );
XNOR2X1TS U2339 ( .A(n1846), .B(n1845), .Y(n1851) );
XOR2X1TS U2340 ( .A(n1848), .B(n1847), .Y(n1849) );
AOI22X1TS U2341 ( .A0(n1849), .A1(n1876), .B0(Raw_mant_NRM_SWR[8]), .B1(
n1875), .Y(n1850) );
OAI2BB1X1TS U2342 ( .A0N(n1880), .A1N(n1851), .B0(n1850), .Y(n612) );
INVX2TS U2343 ( .A(n1852), .Y(n1854) );
NAND2X1TS U2344 ( .A(n1854), .B(n1853), .Y(n1859) );
INVX2TS U2345 ( .A(n1859), .Y(n1855) );
INVX2TS U2346 ( .A(n1857), .Y(n1870) );
INVX2TS U2347 ( .A(n1869), .Y(n1858) );
AOI21X1TS U2348 ( .A0(n1874), .A1(n1870), .B0(n1858), .Y(n1860) );
XOR2X1TS U2349 ( .A(n1860), .B(n1859), .Y(n1861) );
AOI22X1TS U2350 ( .A0(n1861), .A1(n1876), .B0(Raw_mant_NRM_SWR[7]), .B1(
n1875), .Y(n1862) );
OAI2BB1X1TS U2351 ( .A0N(n1880), .A1N(n1863), .B0(n1862), .Y(n613) );
INVX2TS U2352 ( .A(n1864), .Y(n1867) );
INVX2TS U2353 ( .A(n1865), .Y(n1866) );
AOI21X1TS U2354 ( .A0(n1868), .A1(n1867), .B0(n1866), .Y(n1872) );
NAND2X1TS U2355 ( .A(n1870), .B(n1869), .Y(n1873) );
INVX2TS U2356 ( .A(n1873), .Y(n1871) );
XNOR2X1TS U2357 ( .A(n1874), .B(n1873), .Y(n1877) );
AOI22X1TS U2358 ( .A0(n1877), .A1(n1876), .B0(Raw_mant_NRM_SWR[6]), .B1(
n1875), .Y(n1878) );
OAI2BB1X1TS U2359 ( .A0N(n1880), .A1N(n1879), .B0(n1878), .Y(n614) );
MXI2X1TS U2360 ( .A(n2046), .B(sub_x_5_n131), .S0(n974), .Y(n620) );
INVX2TS U2361 ( .A(n1883), .Y(n1943) );
AOI22X1TS U2362 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1885), .B1(n1982), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U2363 ( .A(n1885), .B(n1884), .Y(n952) );
INVX2TS U2364 ( .A(n1891), .Y(n1889) );
AOI22X1TS U2365 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1886), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1982), .Y(n1892) );
AOI22X1TS U2366 ( .A0(n1891), .A1(n1887), .B0(n1927), .B1(n1889), .Y(n949)
);
AOI22X1TS U2367 ( .A0(n1891), .A1(n1932), .B0(n1937), .B1(n1889), .Y(n948)
);
AOI22X1TS U2368 ( .A0(n1891), .A1(n1935), .B0(n1888), .B1(n1889), .Y(n945)
);
AOI22X1TS U2369 ( .A0(n1891), .A1(n1890), .B0(n1969), .B1(n1889), .Y(n944)
);
BUFX3TS U2370 ( .A(n1895), .Y(n1905) );
INVX2TS U2371 ( .A(n1895), .Y(n1904) );
INVX2TS U2372 ( .A(n1905), .Y(n1893) );
BUFX3TS U2373 ( .A(n1895), .Y(n1900) );
BUFX3TS U2374 ( .A(n1895), .Y(n1903) );
BUFX3TS U2375 ( .A(n1895), .Y(n1907) );
BUFX3TS U2376 ( .A(n1907), .Y(n1894) );
INVX2TS U2377 ( .A(n1905), .Y(n1906) );
INVX2TS U2378 ( .A(n1907), .Y(n1896) );
BUFX3TS U2379 ( .A(n1895), .Y(n1901) );
INVX2TS U2380 ( .A(n1907), .Y(n1897) );
BUFX3TS U2381 ( .A(n1895), .Y(n1899) );
INVX2TS U2382 ( .A(n1907), .Y(n1898) );
INVX2TS U2383 ( .A(n1905), .Y(n1902) );
OAI22X1TS U2384 ( .A0(n1910), .A1(n1909), .B0(n1908), .B1(n2039), .Y(n876)
);
AOI21X1TS U2385 ( .A0(DMP_EXP_EWSW[24]), .A1(n1989), .B0(n1913), .Y(n1914)
);
XNOR2X1TS U2386 ( .A(n1915), .B(n1914), .Y(n1916) );
OAI222X1TS U2387 ( .A0(n1930), .A1(n2041), .B0(n1990), .B1(
Shift_reg_FLAGS_7_6), .C0(n1972), .C1(n1931), .Y(n809) );
OAI222X1TS U2388 ( .A0(n1930), .A1(n1992), .B0(n994), .B1(
Shift_reg_FLAGS_7_6), .C0(n2018), .C1(n1931), .Y(n808) );
OAI222X1TS U2389 ( .A0(n1930), .A1(n1993), .B0(n2042), .B1(
Shift_reg_FLAGS_7_6), .C0(n2017), .C1(n1931), .Y(n807) );
BUFX3TS U2390 ( .A(n1926), .Y(n1918) );
INVX2TS U2391 ( .A(n1926), .Y(n1919) );
CLKBUFX2TS U2392 ( .A(n2071), .Y(n1920) );
INVX2TS U2393 ( .A(n965), .Y(n1922) );
INVX2TS U2394 ( .A(n965), .Y(n1934) );
INVX2TS U2395 ( .A(n1926), .Y(n1925) );
INVX2TS U2396 ( .A(n2071), .Y(n1928) );
BUFX3TS U2397 ( .A(n1926), .Y(n1929) );
INVX2TS U2398 ( .A(n2071), .Y(n1933) );
OAI222X1TS U2399 ( .A0(n1931), .A1(n2041), .B0(n1989), .B1(
Shift_reg_FLAGS_7_6), .C0(n1972), .C1(n1930), .Y(n643) );
OAI222X1TS U2400 ( .A0(n1931), .A1(n1992), .B0(n2043), .B1(
Shift_reg_FLAGS_7_6), .C0(n2018), .C1(n1930), .Y(n642) );
OAI222X1TS U2401 ( .A0(n1931), .A1(n1993), .B0(n963), .B1(
Shift_reg_FLAGS_7_6), .C0(n2017), .C1(n1930), .Y(n641) );
OAI2BB2XLTS U2402 ( .B0(n1945), .B1(n1970), .A0N(final_result_ieee[10]),
.A1N(n1969), .Y(n589) );
OAI2BB2XLTS U2403 ( .B0(n1946), .B1(n1970), .A0N(final_result_ieee[11]),
.A1N(n2040), .Y(n588) );
OAI2BB2XLTS U2404 ( .B0(n1947), .B1(n1970), .A0N(final_result_ieee[9]),
.A1N(n2040), .Y(n587) );
OAI2BB2XLTS U2405 ( .B0(n1948), .B1(n1970), .A0N(final_result_ieee[12]),
.A1N(n2040), .Y(n586) );
OAI2BB2XLTS U2406 ( .B0(n1949), .B1(n1970), .A0N(final_result_ieee[8]),
.A1N(n2040), .Y(n585) );
OAI2BB2XLTS U2407 ( .B0(n1950), .B1(n1970), .A0N(final_result_ieee[13]),
.A1N(n1967), .Y(n584) );
OAI2BB2XLTS U2408 ( .B0(n1951), .B1(n1970), .A0N(final_result_ieee[7]),
.A1N(n1967), .Y(n583) );
OAI2BB2XLTS U2409 ( .B0(n1952), .B1(n1944), .A0N(final_result_ieee[6]),
.A1N(n2040), .Y(n582) );
OAI2BB2XLTS U2410 ( .B0(n1953), .B1(n993), .A0N(final_result_ieee[5]), .A1N(
n1967), .Y(n581) );
OAI2BB2XLTS U2411 ( .B0(n1954), .B1(n1944), .A0N(final_result_ieee[4]),
.A1N(n1967), .Y(n580) );
OAI2BB2XLTS U2412 ( .B0(n1955), .B1(n993), .A0N(final_result_ieee[3]), .A1N(
n2040), .Y(n579) );
BUFX3TS U2413 ( .A(n2040), .Y(n1965) );
OAI2BB2XLTS U2414 ( .B0(n1956), .B1(n1944), .A0N(final_result_ieee[2]),
.A1N(n1965), .Y(n578) );
OAI2BB2XLTS U2415 ( .B0(n1957), .B1(n993), .A0N(final_result_ieee[1]), .A1N(
n1965), .Y(n577) );
OAI2BB2XLTS U2416 ( .B0(n1958), .B1(n1944), .A0N(final_result_ieee[0]),
.A1N(n1965), .Y(n576) );
OAI2BB2XLTS U2417 ( .B0(n1959), .B1(n993), .A0N(final_result_ieee[14]),
.A1N(n1965), .Y(n575) );
OAI2BB2XLTS U2418 ( .B0(n1960), .B1(n1944), .A0N(final_result_ieee[15]),
.A1N(n1965), .Y(n574) );
OAI2BB2XLTS U2419 ( .B0(n1961), .B1(n993), .A0N(final_result_ieee[16]),
.A1N(n1965), .Y(n573) );
OAI2BB2XLTS U2420 ( .B0(n1962), .B1(n1944), .A0N(final_result_ieee[17]),
.A1N(n1965), .Y(n572) );
OAI2BB2XLTS U2421 ( .B0(n1963), .B1(n993), .A0N(final_result_ieee[18]),
.A1N(n1965), .Y(n571) );
OAI2BB2XLTS U2422 ( .B0(n1964), .B1(n1944), .A0N(final_result_ieee[19]),
.A1N(n1965), .Y(n570) );
OAI2BB2XLTS U2423 ( .B0(n1966), .B1(n993), .A0N(final_result_ieee[20]),
.A1N(n1965), .Y(n569) );
OAI2BB2XLTS U2424 ( .B0(n1968), .B1(n1970), .A0N(final_result_ieee[21]),
.A1N(n1967), .Y(n568) );
OAI2BB2XLTS U2425 ( .B0(n1971), .B1(n993), .A0N(final_result_ieee[22]),
.A1N(n1969), .Y(n567) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk10.tcl_syn.sdf");
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:39:26 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, underflow_flag_mult, overflow_flag_addsubt,
underflow_flag_addsubt, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_operation_out, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_exp_operation_A_S,
FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag, FPADDSUB_OP_FLAG_SFG,
FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1483, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2193,
DP_OP_26J217_122_5882_n18, DP_OP_26J217_122_5882_n17,
DP_OP_26J217_122_5882_n16, DP_OP_26J217_122_5882_n15,
DP_OP_26J217_122_5882_n14, DP_OP_26J217_122_5882_n8,
DP_OP_26J217_122_5882_n7, DP_OP_26J217_122_5882_n6,
DP_OP_26J217_122_5882_n5, DP_OP_26J217_122_5882_n4,
DP_OP_26J217_122_5882_n3, DP_OP_26J217_122_5882_n2,
DP_OP_26J217_122_5882_n1, DP_OP_230J217_125_7006_n22,
DP_OP_230J217_125_7006_n21, DP_OP_230J217_125_7006_n20,
DP_OP_230J217_125_7006_n19, DP_OP_230J217_125_7006_n18,
DP_OP_230J217_125_7006_n17, DP_OP_230J217_125_7006_n16,
DP_OP_230J217_125_7006_n15, DP_OP_230J217_125_7006_n9,
DP_OP_230J217_125_7006_n8, DP_OP_230J217_125_7006_n7,
DP_OP_230J217_125_7006_n6, DP_OP_230J217_125_7006_n5,
DP_OP_230J217_125_7006_n4, DP_OP_230J217_125_7006_n3,
DP_OP_230J217_125_7006_n2, DP_OP_230J217_125_7006_n1, intadd_491_B_1_,
intadd_491_CI, intadd_491_SUM_2_, intadd_491_SUM_1_,
intadd_491_SUM_0_, intadd_491_n3, intadd_491_n2, intadd_491_n1,
intadd_492_CI, intadd_492_SUM_2_, intadd_492_SUM_1_,
intadd_492_SUM_0_, intadd_492_n3, intadd_492_n2, intadd_492_n1,
mult_x_69_n779, mult_x_69_n771, mult_x_69_n770, mult_x_69_n769,
mult_x_69_n768, mult_x_69_n767, mult_x_69_n766, mult_x_69_n765,
mult_x_69_n764, mult_x_69_n763, mult_x_69_n762, mult_x_69_n761,
mult_x_69_n760, mult_x_69_n759, mult_x_69_n758, mult_x_69_n757,
mult_x_69_n756, mult_x_69_n755, mult_x_69_n753, mult_x_69_n752,
mult_x_69_n747, mult_x_69_n746, mult_x_69_n745, mult_x_69_n744,
mult_x_69_n743, mult_x_69_n742, mult_x_69_n741, mult_x_69_n740,
mult_x_69_n739, mult_x_69_n738, mult_x_69_n737, mult_x_69_n736,
mult_x_69_n735, mult_x_69_n734, mult_x_69_n733, mult_x_69_n732,
mult_x_69_n731, mult_x_69_n730, mult_x_69_n729, mult_x_69_n728,
mult_x_69_n726, mult_x_69_n725, mult_x_69_n717, mult_x_69_n716,
mult_x_69_n715, mult_x_69_n714, mult_x_69_n713, mult_x_69_n712,
mult_x_69_n711, mult_x_69_n710, mult_x_69_n709, mult_x_69_n708,
mult_x_69_n707, mult_x_69_n706, mult_x_69_n705, mult_x_69_n704,
mult_x_69_n703, mult_x_69_n702, mult_x_69_n701, mult_x_69_n699,
mult_x_69_n698, mult_x_69_n693, mult_x_69_n692, mult_x_69_n691,
mult_x_69_n690, mult_x_69_n689, mult_x_69_n688, mult_x_69_n687,
mult_x_69_n686, mult_x_69_n685, mult_x_69_n684, mult_x_69_n683,
mult_x_69_n682, mult_x_69_n681, mult_x_69_n680, mult_x_69_n679,
mult_x_69_n678, mult_x_69_n677, mult_x_69_n676, mult_x_69_n675,
mult_x_69_n674, mult_x_69_n672, mult_x_69_n671, mult_x_69_n663,
mult_x_69_n662, mult_x_69_n661, mult_x_69_n660, mult_x_69_n659,
mult_x_69_n658, mult_x_69_n657, mult_x_69_n656, mult_x_69_n655,
mult_x_69_n654, mult_x_69_n653, mult_x_69_n652, mult_x_69_n651,
mult_x_69_n650, mult_x_69_n649, mult_x_69_n648, mult_x_69_n647,
mult_x_69_n645, mult_x_69_n644, mult_x_69_n639, mult_x_69_n638,
mult_x_69_n637, mult_x_69_n636, mult_x_69_n635, mult_x_69_n634,
mult_x_69_n633, mult_x_69_n632, mult_x_69_n631, mult_x_69_n630,
mult_x_69_n629, mult_x_69_n628, mult_x_69_n627, mult_x_69_n626,
mult_x_69_n625, mult_x_69_n624, mult_x_69_n623, mult_x_69_n622,
mult_x_69_n621, mult_x_69_n620, mult_x_69_n618, mult_x_69_n617,
mult_x_69_n608, mult_x_69_n607, mult_x_69_n606, mult_x_69_n605,
mult_x_69_n602, mult_x_69_n601, mult_x_69_n600, mult_x_69_n599,
mult_x_69_n597, mult_x_69_n596, mult_x_69_n595, mult_x_69_n594,
mult_x_69_n593, mult_x_69_n474, mult_x_69_n472, mult_x_69_n471,
mult_x_69_n469, mult_x_69_n468, mult_x_69_n467, mult_x_69_n466,
mult_x_69_n464, mult_x_69_n463, mult_x_69_n462, mult_x_69_n461,
mult_x_69_n459, mult_x_69_n458, mult_x_69_n457, mult_x_69_n454,
mult_x_69_n452, mult_x_69_n451, mult_x_69_n450, mult_x_69_n447,
mult_x_69_n445, mult_x_69_n444, mult_x_69_n443, mult_x_69_n441,
mult_x_69_n440, mult_x_69_n439, mult_x_69_n438, mult_x_69_n437,
mult_x_69_n436, mult_x_69_n435, mult_x_69_n433, mult_x_69_n432,
mult_x_69_n431, mult_x_69_n430, mult_x_69_n429, mult_x_69_n428,
mult_x_69_n427, mult_x_69_n425, mult_x_69_n424, mult_x_69_n423,
mult_x_69_n422, mult_x_69_n421, mult_x_69_n420, mult_x_69_n419,
mult_x_69_n417, mult_x_69_n416, mult_x_69_n415, mult_x_69_n414,
mult_x_69_n413, mult_x_69_n412, mult_x_69_n409, mult_x_69_n407,
mult_x_69_n406, mult_x_69_n405, mult_x_69_n404, mult_x_69_n403,
mult_x_69_n402, mult_x_69_n399, mult_x_69_n397, mult_x_69_n396,
mult_x_69_n395, mult_x_69_n394, mult_x_69_n393, mult_x_69_n392,
mult_x_69_n390, mult_x_69_n389, mult_x_69_n388, mult_x_69_n387,
mult_x_69_n386, mult_x_69_n385, mult_x_69_n384, mult_x_69_n383,
mult_x_69_n382, mult_x_69_n381, mult_x_69_n379, mult_x_69_n378,
mult_x_69_n377, mult_x_69_n376, mult_x_69_n375, mult_x_69_n374,
mult_x_69_n373, mult_x_69_n372, mult_x_69_n371, mult_x_69_n370,
mult_x_69_n368, mult_x_69_n367, mult_x_69_n366, mult_x_69_n365,
mult_x_69_n364, mult_x_69_n363, mult_x_69_n362, mult_x_69_n361,
mult_x_69_n360, mult_x_69_n359, mult_x_69_n357, mult_x_69_n356,
mult_x_69_n355, mult_x_69_n354, mult_x_69_n353, mult_x_69_n352,
mult_x_69_n351, mult_x_69_n350, mult_x_69_n349, mult_x_69_n348,
mult_x_69_n346, mult_x_69_n345, mult_x_69_n344, mult_x_69_n343,
mult_x_69_n342, mult_x_69_n341, mult_x_69_n340, mult_x_69_n339,
mult_x_69_n338, mult_x_69_n337, mult_x_69_n336, mult_x_69_n335,
mult_x_69_n334, mult_x_69_n333, mult_x_69_n332, mult_x_69_n331,
mult_x_69_n330, mult_x_69_n329, mult_x_69_n328, mult_x_69_n327,
mult_x_69_n326, mult_x_69_n325, mult_x_69_n324, mult_x_69_n323,
mult_x_69_n322, mult_x_69_n321, mult_x_69_n320, mult_x_69_n319,
mult_x_69_n318, mult_x_69_n317, mult_x_69_n316, mult_x_69_n315,
mult_x_69_n314, mult_x_69_n313, mult_x_69_n312, mult_x_69_n311,
mult_x_69_n310, mult_x_69_n309, mult_x_69_n308, mult_x_69_n307,
mult_x_69_n306, mult_x_69_n305, mult_x_69_n304, mult_x_69_n303,
mult_x_69_n302, mult_x_69_n301, mult_x_69_n300, mult_x_69_n299,
mult_x_69_n298, mult_x_69_n297, mult_x_69_n296, mult_x_69_n295,
mult_x_69_n294, mult_x_69_n293, mult_x_69_n292, mult_x_69_n291,
mult_x_69_n290, mult_x_69_n289, mult_x_69_n288, mult_x_69_n287,
mult_x_69_n286, mult_x_69_n285, mult_x_69_n284, mult_x_69_n283,
mult_x_69_n281, mult_x_69_n280, mult_x_69_n279, mult_x_69_n278,
mult_x_69_n277, mult_x_69_n276, mult_x_69_n275, mult_x_69_n274,
mult_x_69_n273, mult_x_69_n272, mult_x_69_n271, mult_x_69_n270,
mult_x_69_n269, mult_x_69_n268, mult_x_69_n267, mult_x_69_n266,
mult_x_69_n265, mult_x_69_n264, mult_x_69_n263, mult_x_69_n262,
mult_x_69_n261, mult_x_69_n260, mult_x_69_n259, mult_x_69_n258,
mult_x_69_n257, mult_x_69_n256, mult_x_69_n255, mult_x_69_n254,
mult_x_69_n252, mult_x_69_n251, mult_x_69_n250, mult_x_69_n249,
mult_x_69_n248, mult_x_69_n247, mult_x_69_n246, mult_x_69_n245,
mult_x_69_n243, mult_x_69_n242, mult_x_69_n241, mult_x_69_n240,
mult_x_69_n239, mult_x_69_n238, mult_x_69_n237, mult_x_69_n236,
mult_x_69_n235, mult_x_69_n234, mult_x_69_n233, mult_x_69_n232,
mult_x_69_n231, mult_x_69_n230, mult_x_69_n229, mult_x_69_n228,
mult_x_69_n226, mult_x_69_n225, mult_x_69_n224, mult_x_69_n223,
mult_x_69_n222, mult_x_69_n221, mult_x_69_n220, mult_x_69_n219,
mult_x_69_n218, mult_x_69_n217, mult_x_69_n216, mult_x_69_n215,
mult_x_69_n214, mult_x_69_n213, mult_x_69_n212, mult_x_69_n211,
mult_x_69_n210, mult_x_69_n209, mult_x_69_n208, mult_x_69_n206,
mult_x_69_n204, mult_x_69_n203, mult_x_69_n202, mult_x_69_n200,
mult_x_69_n199, mult_x_69_n198, mult_x_69_n197, mult_x_69_n196,
mult_x_69_n195, mult_x_69_n194, mult_x_69_n193, mult_x_69_n192,
mult_x_69_n191, mult_x_69_n189, mult_x_69_n188, mult_x_69_n187,
mult_x_69_n185, mult_x_69_n184, mult_x_69_n183, mult_x_69_n182,
mult_x_69_n181, mult_x_69_n180, n2196, n2197, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2327, n2328, n2329, n2330, n2331, n2332, n2333,
n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343,
n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353,
n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873,
n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883,
n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893,
n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903,
n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913,
n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923,
n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933,
n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943,
n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043,
n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053,
n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3948, n3949, n3950, n3951, n3952, n3953, n3955, n3957,
n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965, n3966, n3967,
n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975, n3976, n3977,
n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985, n3986, n3987,
n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995, n3996, n3997,
n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005, n4006, n4007,
n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017,
n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027,
n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035, n4036, n4037,
n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045, n4046, n4047,
n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057,
n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067,
n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077,
n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087,
n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097,
n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107,
n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117,
n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127,
n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137,
n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147,
n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157,
n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167,
n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177,
n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187,
n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197,
n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207,
n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217,
n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227,
n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237,
n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247,
n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257,
n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267,
n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277,
n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287,
n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297,
n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307,
n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317,
n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327,
n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337,
n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347,
n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357,
n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4367, n4368,
n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378,
n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388,
n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398,
n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408,
n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418,
n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428,
n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438,
n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448,
n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458,
n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468,
n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478,
n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488,
n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498,
n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508,
n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518,
n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528,
n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538,
n4539, n4540, n4541, n4542, n4543, n4545, n4546, n4547, n4548, n4549,
n4550, n4551, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560,
n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570,
n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580,
n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590,
n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600,
n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610,
n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620,
n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630,
n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640,
n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650,
n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660,
n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670,
n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680,
n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690,
n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700,
n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710,
n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720,
n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730,
n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740,
n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750,
n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760,
n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770,
n4771, n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780,
n4781, n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790,
n4791, n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800,
n4801, n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810,
n4811, n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820,
n4821, n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830,
n4831, n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840,
n4841, n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850,
n4851, n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860,
n4861, n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870,
n4871, n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880,
n4881, n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890,
n4891, n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900,
n4901, n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910,
n4911, n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920,
n4921, n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930,
n4931, n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940,
n4941, n4942, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951,
n4952;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:1] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:1] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [23:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n4921), .Q(
dataA[25]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n4921), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n4921), .Q(
dataA[27]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n4921), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n4912), .Q(
dataB[23]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n4920), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n4920), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n4920), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n4920), .Q(
dataB[28]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n4920), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n4920), .Q(
dataB[31]) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n4920), .Q(NaN_flag)
);
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2141), .CK(clk), .RN(n4906),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n2323) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2133), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[2]), .QN(n2305) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2132), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n4844) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2129), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2127), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2126), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n4843) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2124), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[12]), .QN(n4859) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2123), .CK(clk), .RN(n4901), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2122), .CK(clk), .RN(n4924), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n4845) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2121), .CK(clk), .RN(n4928), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2120), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[21]), .QN(n4860) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2119), .CK(clk), .RN(n4922), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2115), .CK(clk), .RN(n4924), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1854), .CK(clk), .RN(n4907),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1853), .CK(clk), .RN(n4914),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1852), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1851), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1850), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1849), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1848), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1953), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_x_out[23]), .QN(n4842) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1952), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_x_out[24]), .QN(n4856) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1951), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_x_out[25]), .QN(n4857) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1950), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_x_out[26]), .QN(n4858) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1949), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1948), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1947), .CK(clk), .RN(n4917),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1946), .CK(clk), .RN(n4916),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2114), .CK(clk), .RN(n4920), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2113), .CK(clk), .RN(n4927), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2112), .CK(clk), .RN(n4914), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2111), .CK(clk), .RN(n4927), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2110), .CK(clk), .RN(n4901), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2109), .CK(clk), .RN(n4914), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2108), .CK(clk), .RN(n4901), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2107), .CK(clk), .RN(n4927), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2106), .CK(clk), .RN(n4914), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2105), .CK(clk), .RN(n4901), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2104), .CK(clk), .RN(n4907), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2103), .CK(clk), .RN(n4908), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2102), .CK(clk), .RN(n4926), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2101), .CK(clk), .RN(n4927), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2100), .CK(clk), .RN(n4919), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2099), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2098), .CK(clk), .RN(n4919), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2097), .CK(clk), .RN(n4906), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2096), .CK(clk), .RN(n4915), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2095), .CK(clk), .RN(n4910), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2094), .CK(clk), .RN(n4926), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2093), .CK(clk), .RN(n4910), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2092), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2091), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2090), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2089), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2088), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2087), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2086), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2085), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2084), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2083), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1788), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1743), .CK(clk), .RN(
n4901), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1785), .CK(clk), .RN(n4924), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1742), .CK(clk), .RN(
n4905), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1782), .CK(clk), .RN(n4929), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1741), .CK(clk), .RN(
n4926), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1779), .CK(clk), .RN(n4919), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1740), .CK(clk), .RN(
n4906), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1776), .CK(clk), .RN(n4906), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1739), .CK(clk), .RN(
n4915), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1773), .CK(clk), .RN(n4909), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1738), .CK(clk), .RN(
n4909), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1770), .CK(clk), .RN(n4922), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1737), .CK(clk), .RN(
n4924), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1767), .CK(clk), .RN(n4915), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1736), .CK(clk), .RN(
n4927), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2010), .CK(clk), .RN(n4922), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1744), .CK(clk), .RN(
n4924), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1865), .CK(clk), .RN(
n4922), .Q(FPSENCOS_d_ff2_Y[22]), .QN(n4841) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1864), .CK(clk), .RN(n4923),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1962), .CK(clk), .RN(n4923),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2031), .CK(clk), .RN(n4923), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1751), .CK(clk), .RN(
n4923), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1879), .CK(clk), .RN(
n4923), .Q(FPSENCOS_d_ff2_Y[15]), .QN(n4834) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1878), .CK(clk), .RN(n4923),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1976), .CK(clk), .RN(n4923),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2022), .CK(clk), .RN(n4906), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1748), .CK(clk), .RN(
n4904), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1873), .CK(clk), .RN(
n4912), .Q(FPSENCOS_d_ff2_Y[18]), .QN(n4837) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1872), .CK(clk), .RN(n4905),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1970), .CK(clk), .RN(n4926),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2013), .CK(clk), .RN(n4911), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1745), .CK(clk), .RN(
n4919), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1867), .CK(clk), .RN(
n4919), .Q(FPSENCOS_d_ff2_Y[21]), .QN(n4840) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1866), .CK(clk), .RN(n4928),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1964), .CK(clk), .RN(n4909),
.Q(FPSENCOS_d_ff3_sh_x_out[21]), .QN(n4855) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2019), .CK(clk), .RN(n4909), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1747), .CK(clk), .RN(
n4909), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1871), .CK(clk), .RN(
n4909), .Q(FPSENCOS_d_ff2_Y[19]), .QN(n4838) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1870), .CK(clk), .RN(n4909),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1968), .CK(clk), .RN(n4909),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2016), .CK(clk), .RN(n4909), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1746), .CK(clk), .RN(
n4909), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1869), .CK(clk), .RN(
n4908), .Q(FPSENCOS_d_ff2_Y[20]), .QN(n4839) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1868), .CK(clk), .RN(n4908),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1966), .CK(clk), .RN(n4908),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2025), .CK(clk), .RN(n4908), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1749), .CK(clk), .RN(
n4908), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1875), .CK(clk), .RN(
n4908), .Q(FPSENCOS_d_ff2_Y[17]), .QN(n4836) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1874), .CK(clk), .RN(n4908),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1972), .CK(clk), .RN(n4907),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2064), .CK(clk), .RN(n4907), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1762), .CK(clk), .RN(
n4907), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1901), .CK(clk), .RN(
n4907), .Q(FPSENCOS_d_ff2_Y[4]), .QN(n4823) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1900), .CK(clk), .RN(n4907),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1998), .CK(clk), .RN(n4907),
.Q(FPSENCOS_d_ff3_sh_x_out[4]), .QN(n4849) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2058), .CK(clk), .RN(n4907), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1760), .CK(clk), .RN(
n4907), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1897), .CK(clk), .RN(
n4912), .Q(FPSENCOS_d_ff2_Y[6]), .QN(n4825) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1896), .CK(clk), .RN(n4910),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1994), .CK(clk), .RN(n4919),
.Q(FPSENCOS_d_ff3_sh_x_out[6]), .QN(n4850) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1803), .CK(clk), .RN(n4879), .QN(n2237) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2037), .CK(clk), .RN(n4926), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1753), .CK(clk), .RN(
n4902), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1883), .CK(clk), .RN(
n4906), .Q(FPSENCOS_d_ff2_Y[13]), .QN(n4832) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1882), .CK(clk), .RN(n4919),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1980), .CK(clk), .RN(n4910),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2028), .CK(clk), .RN(n4921), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1750), .CK(clk), .RN(
n4905), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1877), .CK(clk), .RN(
n3151), .Q(FPSENCOS_d_ff2_Y[16]), .QN(n4835) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1876), .CK(clk), .RN(n3151),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1974), .CK(clk), .RN(n4929),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1804), .CK(clk), .RN(n4879), .QN(n2238) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2052), .CK(clk), .RN(n4929), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1758), .CK(clk), .RN(
n4910), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1893), .CK(clk), .RN(
n4929), .Q(FPSENCOS_d_ff2_Y[8]), .QN(n4827) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1892), .CK(clk), .RN(n4905),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1990), .CK(clk), .RN(n4910),
.Q(FPSENCOS_d_ff3_sh_x_out[8]), .QN(n4851) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2043), .CK(clk), .RN(n4929), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1755), .CK(clk), .RN(
n4910), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1887), .CK(clk), .RN(
n4905), .Q(FPSENCOS_d_ff2_Y[11]), .QN(n4830) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1886), .CK(clk), .RN(n4905),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1984), .CK(clk), .RN(n4904),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2034), .CK(clk), .RN(n4904), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1881), .CK(clk), .RN(
n4904), .Q(FPSENCOS_d_ff2_Y[14]), .QN(n4833) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1880), .CK(clk), .RN(n4904),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1978), .CK(clk), .RN(n4904),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2046), .CK(clk), .RN(n4904), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1756), .CK(clk), .RN(
n4904), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1889), .CK(clk), .RN(
n4903), .Q(FPSENCOS_d_ff2_Y[10]), .QN(n4829) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1888), .CK(clk), .RN(n4903),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1986), .CK(clk), .RN(n4903),
.Q(FPSENCOS_d_ff3_sh_x_out[10]), .QN(n4853) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2040), .CK(clk), .RN(n4903), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1754), .CK(clk), .RN(
n4903), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1885), .CK(clk), .RN(
n4903), .Q(FPSENCOS_d_ff2_Y[12]), .QN(n4831) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1884), .CK(clk), .RN(n4903),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1982), .CK(clk), .RN(n4902),
.Q(FPSENCOS_d_ff3_sh_x_out[12]), .QN(n4854) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1911), .CK(clk), .RN(n4902), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1847), .CK(clk), .RN(
n4902), .Q(FPSENCOS_d_ff2_Y[31]), .QN(n2310) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1846), .CK(clk), .RN(n4902),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n4902), .Q(
FPSENCOS_d_ff_Xn[31]), .QN(n4803) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1944), .CK(clk), .RN(n4902),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2080), .CK(clk), .RN(
n4896), .Q(FPADDSUB_left_right_SHT2) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2067), .CK(clk), .RN(n4902), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1903), .CK(clk), .RN(
n4927), .Q(FPSENCOS_d_ff2_Y[3]), .QN(n4822) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1902), .CK(clk), .RN(n4901),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n2000), .CK(clk), .RN(n4927),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2070), .CK(clk), .RN(n4901), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1764), .CK(clk), .RN(
n4927), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1905), .CK(clk), .RN(
n4910), .Q(FPSENCOS_d_ff2_Y[2]), .QN(n4821) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1904), .CK(clk), .RN(n4916),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2002), .CK(clk), .RN(n4916),
.Q(FPSENCOS_d_ff3_sh_x_out[2]), .QN(n4848) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n4916),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2055), .CK(clk), .RN(n4916), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1759), .CK(clk), .RN(
n4916), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1895), .CK(clk), .RN(
n4916), .Q(FPSENCOS_d_ff2_Y[7]), .QN(n4826) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1894), .CK(clk), .RN(n4916),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1992), .CK(clk), .RN(n3149),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n3149),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2076), .CK(clk), .RN(n3149), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1766), .CK(clk), .RN(
n3149), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1909), .CK(clk), .RN(
n3149), .Q(FPSENCOS_d_ff2_Y[0]), .QN(n4819) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1908), .CK(clk), .RN(n3149),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2006), .CK(clk), .RN(n3149),
.Q(FPSENCOS_d_ff3_sh_x_out[0]), .QN(n4846) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2073), .CK(clk), .RN(n4902), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1765), .CK(clk), .RN(
n4920), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1907), .CK(clk), .RN(
n4923), .Q(FPSENCOS_d_ff2_Y[1]), .QN(n4820) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1906), .CK(clk), .RN(n4903),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2004), .CK(clk), .RN(n4915),
.Q(FPSENCOS_d_ff3_sh_x_out[1]), .QN(n4847) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n4927),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2049), .CK(clk), .RN(n4916), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1757), .CK(clk), .RN(
n4914), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1891), .CK(clk), .RN(
n4915), .Q(FPSENCOS_d_ff2_Y[9]), .QN(n4828) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1890), .CK(clk), .RN(n4915),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1988), .CK(clk), .RN(n4915),
.Q(FPSENCOS_d_ff3_sh_x_out[9]), .QN(n4852) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n4915),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2061), .CK(clk), .RN(n4915), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1761), .CK(clk), .RN(
n4915), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1899), .CK(clk), .RN(
n4915), .Q(FPSENCOS_d_ff2_Y[5]), .QN(n4824) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1898), .CK(clk), .RN(n4915),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1996), .CK(clk), .RN(n4927),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n4901),
.Q(cordic_result[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n4927),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n4914),
.Q(cordic_result[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n4901),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n4927),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n4914),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n4901),
.Q(cordic_result[13]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1696), .CK(clk),
.RN(n4930), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1626), .CK(
clk), .RN(n4930), .Q(FPMULT_zero_flag) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1658), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1624), .CK(clk), .RN(
n4933), .Q(FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1601), .CK(clk),
.RN(n4931), .Q(FPMULT_Add_result[23]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_46_ ( .D(n1599), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[46]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_45_ ( .D(n1598), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[45]), .QN(n4802) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_44_ ( .D(n1597), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[44]), .QN(n4796) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_43_ ( .D(n1596), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[43]), .QN(n4804) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_42_ ( .D(n1595), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[42]), .QN(n4805) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_41_ ( .D(n1594), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[41]), .QN(n4806) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_40_ ( .D(n1593), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[40]), .QN(n4807) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_39_ ( .D(n1592), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[39]), .QN(n4808) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_38_ ( .D(n1591), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[38]), .QN(n4809) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_37_ ( .D(n1590), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[37]), .QN(n4810) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_36_ ( .D(n1589), .CK(clk), .RN(
n4912), .Q(FPMULT_P_Sgf[36]), .QN(n4811) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_35_ ( .D(n1588), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[35]), .QN(n4812) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_34_ ( .D(n1587), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[34]), .QN(n4813) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_33_ ( .D(n1586), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[33]), .QN(n4814) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_32_ ( .D(n1585), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[32]), .QN(n4815) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_31_ ( .D(n1584), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[31]), .QN(n4816) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_30_ ( .D(n1583), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[30]), .QN(n4817) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_29_ ( .D(n1582), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[29]), .QN(n4818) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_28_ ( .D(n1581), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[28]), .QN(n4797) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_27_ ( .D(n1580), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[27]), .QN(n4798) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_26_ ( .D(n1579), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[26]), .QN(n4799) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_25_ ( .D(n1578), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[25]), .QN(n4800) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_24_ ( .D(n1577), .CK(clk), .RN(
n4911), .Q(FPMULT_P_Sgf[24]), .QN(n4801) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_23_ ( .D(n1576), .CK(clk), .RN(
n3149), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_22_ ( .D(n1575), .CK(clk), .RN(
n3149), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_21_ ( .D(n1574), .CK(clk), .RN(
n3149), .Q(FPMULT_P_Sgf[21]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_19_ ( .D(n1572), .CK(clk), .RN(
n3149), .Q(FPMULT_P_Sgf[19]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_17_ ( .D(n1570), .CK(clk), .RN(
n3149), .Q(FPMULT_P_Sgf[17]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_11_ ( .D(n1564), .CK(clk), .RN(
n4929), .Q(FPMULT_P_Sgf[11]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_10_ ( .D(n1563), .CK(clk), .RN(
n4910), .Q(FPMULT_P_Sgf[10]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_8_ ( .D(n1561), .CK(clk), .RN(
n4929), .Q(FPMULT_P_Sgf[8]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_7_ ( .D(n1560), .CK(clk), .RN(
n4910), .Q(FPMULT_P_Sgf[7]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_6_ ( .D(n1559), .CK(clk), .RN(
n4905), .Q(FPMULT_P_Sgf[6]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_5_ ( .D(n1558), .CK(clk), .RN(
n4929), .Q(FPMULT_P_Sgf[5]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_4_ ( .D(n1557), .CK(clk), .RN(
n4910), .Q(FPMULT_P_Sgf[4]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_3_ ( .D(n1556), .CK(clk), .RN(
n4905), .Q(FPMULT_P_Sgf[3]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_2_ ( .D(n1555), .CK(clk), .RN(
n4929), .Q(FPMULT_P_Sgf[2]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_1_ ( .D(n1554), .CK(clk), .RN(
n4910), .Q(FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_0_ ( .D(n1553), .CK(clk), .RN(
n4905), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1515), .CK(clk), .RN(n4932), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1514), .CK(clk), .RN(n4931), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1513), .CK(clk), .RN(n4931), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1512), .CK(clk), .RN(n4931), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1511), .CK(clk), .RN(n4931), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1510), .CK(clk), .RN(n4931), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1509), .CK(clk), .RN(n4931), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1508), .CK(clk), .RN(n4931), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1507), .CK(clk), .RN(n4931), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1506), .CK(clk), .RN(n4931), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1505), .CK(clk), .RN(n4931), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1504), .CK(clk), .RN(n4931), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1503), .CK(clk), .RN(n4931), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1502), .CK(clk), .RN(n4931), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1501), .CK(clk), .RN(n4937), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1500), .CK(clk), .RN(n4937), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1499), .CK(clk), .RN(n4930), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1498), .CK(clk), .RN(n4933), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1497), .CK(clk), .RN(n4935), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1496), .CK(clk), .RN(n4932), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1495), .CK(clk), .RN(n4931), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1494), .CK(clk), .RN(n4936), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1493), .CK(clk), .RN(n4938), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1492), .CK(clk), .RN(n4934), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1491), .CK(clk), .RN(n4931), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1490), .CK(clk), .RN(n4930), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1489), .CK(clk), .RN(n4930), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1488), .CK(clk), .RN(n4930), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1487), .CK(clk), .RN(n4930), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1486), .CK(clk), .RN(n4930), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1485), .CK(clk), .RN(n4930), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1483), .CK(clk), .RN(n4930), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1480), .CK(clk), .RN(
n3152), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1479), .CK(clk), .RN(
n4872), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1478), .CK(clk), .RN(
n4893), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1477), .CK(clk), .RN(
n4891), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1476), .CK(clk), .RN(
n4892), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1462), .CK(clk), .RN(n4896),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1461), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1460), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1459), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1458), .CK(clk), .RN(n4894),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1456), .CK(clk), .RN(
n4876), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1454), .CK(clk), .RN(n4877),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1453), .CK(clk), .RN(n3213),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1451), .CK(clk), .RN(
n4879), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1449), .CK(clk), .RN(n4900),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1448), .CK(clk), .RN(n3152),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n3213),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1446), .CK(clk), .RN(
n4897), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1444), .CK(clk), .RN(n4899),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n4880),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1441), .CK(clk), .RN(
n4899), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n3152),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n4897),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n4873),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1436), .CK(clk), .RN(
n4899), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1434), .CK(clk), .RN(n4876),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n4900),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n4872),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1431), .CK(clk), .RN(
n4900), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1429), .CK(clk), .RN(n4898),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1428), .CK(clk), .RN(n4897),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n4879),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1426), .CK(clk), .RN(
n4899), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1424), .CK(clk), .RN(n4899),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n4872),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n4873),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1421), .CK(clk), .RN(
n4873), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1414), .CK(clk), .RN(n4883), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1413), .CK(clk), .RN(n4872), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1411), .CK(clk), .RN(
n4898), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1409), .CK(clk), .RN(n4875),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n4875), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1406), .CK(clk), .RN(n4885),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n4881), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1403), .CK(clk), .RN(n4882),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n4884), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1400), .CK(clk), .RN(n4884),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n4883), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1397), .CK(clk), .RN(n4880),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n4885), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1394), .CK(clk), .RN(n4875),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n4881), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1391), .CK(clk), .RN(n4882),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n4882), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1388), .CK(clk), .RN(n4882),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n4884), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n4883),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n4883), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1382), .CK(clk), .RN(n4875),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n4881), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1379), .CK(clk), .RN(n4881),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n4880), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1376), .CK(clk), .RN(n4885),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n4882), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1373), .CK(clk), .RN(n4880),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n4885), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1370), .CK(clk), .RN(n4875),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n4875), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1367), .CK(clk), .RN(n4881),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n4882), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1364), .CK(clk), .RN(n4881),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n4884), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n4883), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n4885),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1360), .CK(clk), .RN(n4885),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1359), .CK(clk), .RN(
n4872), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n4885),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n4881), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n4875), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n4882),
.Q(FPADDSUB_OP_FLAG_SFG), .QN(n4788) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1332), .CK(clk), .RN(
n4897), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(n4887),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n4886), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n4886),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(n4890),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n4888),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1324), .CK(clk), .RN(
n4876), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1320), .CK(clk), .RN(
n4897), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1316), .CK(clk), .RN(
n4898), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1314), .CK(clk), .RN(n4890),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n4887), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n4886),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(n4874),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n4889),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1307), .CK(clk), .RN(n4889),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n3213), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n4886),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n4886),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n4888),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1300), .CK(clk), .RN(n4874),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n4889), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n4888),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n4888),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n4886),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1293), .CK(clk), .RN(n4890),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n4888), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n4890),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(n4886),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n4874),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1286), .CK(clk), .RN(n4874),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n4874), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n4874),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(n4874),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n3213),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1279), .CK(clk), .RN(n4888),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n4890), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n3213),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(n4888),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n3213),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1273), .CK(clk), .RN(n3213),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1272), .CK(clk), .RN(
n4890), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n3213),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(n4887),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n4890),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1267), .CK(clk), .RN(n4887),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1266), .CK(clk), .RN(n4889),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n4896),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1263), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1262), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1259), .CK(clk), .RN(n4894),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n4877),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n4891),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1255), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1254), .CK(clk), .RN(n4896),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n4877),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1251), .CK(clk), .RN(n4891),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1250), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n4896),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1247), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1246), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1243), .CK(clk), .RN(n4891),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1242), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1239), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1238), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n4894),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1235), .CK(clk), .RN(n4877),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1234), .CK(clk), .RN(n4891),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1231), .CK(clk), .RN(n4896),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1230), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1227), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1226), .CK(clk), .RN(n4894),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n4877),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1223), .CK(clk), .RN(n4891),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1222), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n4896),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1219), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1218), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n4877),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1215), .CK(clk), .RN(n4891),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1214), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n4896),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1211), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1210), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(
n4894), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]) );
CMPR32X2TS DP_OP_230J217_125_7006_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_230J217_125_7006_n22), .CO(
DP_OP_230J217_125_7006_n9), .S(FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_230J217_125_7006_U9 ( .A(DP_OP_230J217_125_7006_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_230J217_125_7006_n9), .CO(
DP_OP_230J217_125_7006_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_230J217_125_7006_U8 ( .A(DP_OP_230J217_125_7006_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_230J217_125_7006_n8), .CO(
DP_OP_230J217_125_7006_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_230J217_125_7006_U7 ( .A(DP_OP_230J217_125_7006_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_230J217_125_7006_n7), .CO(
DP_OP_230J217_125_7006_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_230J217_125_7006_U6 ( .A(DP_OP_230J217_125_7006_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_230J217_125_7006_n6), .CO(
DP_OP_230J217_125_7006_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_230J217_125_7006_U5 ( .A(DP_OP_230J217_125_7006_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_230J217_125_7006_n5), .CO(
DP_OP_230J217_125_7006_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_230J217_125_7006_U4 ( .A(DP_OP_230J217_125_7006_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_230J217_125_7006_n4), .CO(
DP_OP_230J217_125_7006_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_230J217_125_7006_U3 ( .A(DP_OP_230J217_125_7006_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_230J217_125_7006_n3), .CO(
DP_OP_230J217_125_7006_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_230J217_125_7006_U2 ( .A(FPMULT_FSM_exp_operation_A_S), .B(
FPMULT_S_Oper_A_exp[8]), .C(DP_OP_230J217_125_7006_n2), .CO(
DP_OP_230J217_125_7006_n1), .S(FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_491_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n4704), .C(
intadd_491_CI), .CO(intadd_491_n3), .S(intadd_491_SUM_0_) );
CMPR32X2TS intadd_491_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(intadd_491_B_1_),
.C(intadd_491_n3), .CO(intadd_491_n2), .S(intadd_491_SUM_1_) );
DFFSX2TS R_2 ( .D(n4866), .CK(clk), .SN(n4928), .Q(n4950) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1860), .CK(clk), .RN(
n4929), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n4793) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1861), .CK(clk), .RN(
n4919), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n4792) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1862), .CK(clk), .RN(
n4903), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n4791) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1516), .CK(clk), .RN(
n4932), .Q(underflow_flag_mult), .QN(n4787) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1820), .CK(clk), .RN(
n4879), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n4782) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1819), .CK(clk), .RN(
n4876), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n4781) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1539), .CK(
clk), .RN(n4933), .Q(FPMULT_Sgf_normalized_result[22]), .QN(n4779) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2137), .CK(clk), .RN(n4926),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n4778) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1809), .CK(clk), .RN(n4883), .Q(FPADDSUB_Data_array_SWR[18]), .QN(n4777) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1814), .CK(clk), .RN(n4887), .Q(FPADDSUB_Data_array_SWR[23]), .QN(n4772) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1812), .CK(clk), .RN(n3213), .Q(FPADDSUB_Data_array_SWR[21]), .QN(n4771) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1811), .CK(clk), .RN(n4891), .Q(FPADDSUB_Data_array_SWR[20]), .QN(n4770) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1690), .CK(clk), .RN(n4933), .Q(
FPMULT_FSM_selector_C), .QN(n4769) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1467), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n4768) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1914), .CK(clk), .RN(
n4872), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n4765) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1926), .CK(clk), .RN(
n4882), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n4762) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1932), .CK(clk), .RN(
n4891), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n4761) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1934), .CK(clk), .RN(
n4894), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n4760) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1942), .CK(clk), .RN(
n4873), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n4759) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1916), .CK(clk), .RN(
n4876), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n4758) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1921), .CK(clk), .RN(
n4874), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n4757) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1929), .CK(clk), .RN(
n4896), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n4755) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1924), .CK(clk), .RN(
n4875), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n4753) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1941), .CK(clk), .RN(
n4884), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n4751) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1943), .CK(clk), .RN(
n4890), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n4750) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1935), .CK(clk), .RN(
n4892), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n4749) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2079), .CK(clk), .RN(
n3213), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n4748) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1928), .CK(clk), .RN(
n4874), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n4744) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1472), .CK(clk), .RN(
n4900), .Q(result_add_subt[26]), .QN(n4739) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1474), .CK(clk), .RN(
n4879), .Q(result_add_subt[24]), .QN(n4738) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1471), .CK(clk), .RN(
n4897), .Q(result_add_subt[27]), .QN(n4737) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1470), .CK(clk), .RN(
n4879), .Q(result_add_subt[28]), .QN(n4736) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1815), .CK(clk), .RN(
n4888), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n4735) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1280), .CK(clk), .RN(
n4888), .Q(result_add_subt[5]), .QN(n4731) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1287), .CK(clk), .RN(
n3213), .Q(result_add_subt[9]), .QN(n4730) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1294), .CK(clk), .RN(
n4890), .Q(result_add_subt[1]), .QN(n4729) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1301), .CK(clk), .RN(
n4889), .Q(result_add_subt[0]), .QN(n4728) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1308), .CK(clk), .RN(
n4886), .Q(result_add_subt[7]), .QN(n4727) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1315), .CK(clk), .RN(
n4874), .Q(result_add_subt[2]), .QN(n4726) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1331), .CK(clk), .RN(
n4874), .Q(result_add_subt[3]), .QN(n4725) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1365), .CK(clk), .RN(
n4881), .Q(result_add_subt[12]), .QN(n4724) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1368), .CK(clk), .RN(
n4882), .Q(result_add_subt[10]), .QN(n4723) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1371), .CK(clk), .RN(
n4885), .Q(result_add_subt[14]), .QN(n4722) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1374), .CK(clk), .RN(
n4881), .Q(result_add_subt[11]), .QN(n4721) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1377), .CK(clk), .RN(
n4880), .Q(result_add_subt[8]), .QN(n4720) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1380), .CK(clk), .RN(
n4885), .Q(result_add_subt[16]), .QN(n4719) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1383), .CK(clk), .RN(
n4880), .Q(result_add_subt[13]), .QN(n4718) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(
n4875), .Q(result_add_subt[6]), .QN(n4717) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(
n4884), .Q(result_add_subt[4]), .QN(n4716) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1392), .CK(clk), .RN(
n4881), .Q(result_add_subt[17]), .QN(n4715) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1395), .CK(clk), .RN(
n4875), .Q(result_add_subt[20]), .QN(n4714) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1398), .CK(clk), .RN(
n4883), .Q(result_add_subt[19]), .QN(n4713) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1401), .CK(clk), .RN(
n4885), .Q(result_add_subt[21]), .QN(n4712) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1404), .CK(clk), .RN(
n4875), .Q(result_add_subt[18]), .QN(n4711) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1407), .CK(clk), .RN(
n4880), .Q(result_add_subt[15]), .QN(n4710) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1410), .CK(clk), .RN(
n4881), .Q(result_add_subt[22]), .QN(n4709) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1337), .CK(clk), .RN(
n4887), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n4707) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1333), .CK(clk), .RN(
n4886), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n4706) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1321), .CK(clk), .RN(
n4890), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n4700) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2151), .CK(
clk), .RN(n4899), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n4689) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1525), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n4678) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1336), .CK(clk), .RN(
n4889), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n4677) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1523), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n4674) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1317), .CK(clk), .RN(
n3213), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n4673) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1417), .CK(clk), .RN(n4884),
.Q(FPADDSUB_DmP_EXP_EWSW[25]), .QN(n4663) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1464), .CK(clk), .RN(n4891),
.Q(FPADDSUB_DMP_EXP_EWSW[26]), .QN(n4662) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1416), .CK(clk), .RN(n4885),
.Q(FPADDSUB_DmP_EXP_EWSW[26]), .QN(n4660) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1541), .CK(clk), .RN(
n4933), .Q(FPMULT_exp_oper_result[8]), .QN(n4659) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1338), .CK(clk), .RN(
n4874), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n4658) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1341), .CK(clk), .RN(
n4888), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n4657) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1813), .CK(clk), .RN(n4876), .Q(FPADDSUB_Data_array_SWR[22]), .QN(n4656) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1465), .CK(clk), .RN(n4896),
.Q(FPADDSUB_DMP_EXP_EWSW[25]), .QN(n4655) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2136), .CK(clk), .RN(n4918),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n4654) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1810), .CK(clk), .RN(n3213), .Q(FPADDSUB_Data_array_SWR[19]), .QN(n4653) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1913), .CK(clk), .RN(
n4897), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n4652) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1925), .CK(clk), .RN(
n4889), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n4650) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1931), .CK(clk), .RN(
n4892), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n4649) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1923), .CK(clk), .RN(
n4883), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n4647) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1863), .CK(clk), .RN(
n4920), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n4645) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1922), .CK(clk), .RN(
n4882), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n4643) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1930), .CK(clk), .RN(
n4899), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n4642) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1940), .CK(clk), .RN(
n4889), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n4641) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1358), .CK(clk), .RN(
n4883), .Q(result_add_subt[31]), .QN(n4640) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1816), .CK(clk), .RN(
n4900), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n4639) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1339), .CK(clk), .RN(
n4888), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n4635) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1322), .CK(clk), .RN(
n4886), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n4632) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n4919), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n4631) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1342), .CK(clk), .RN(
n4881), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n4624) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1334), .CK(clk), .RN(
n4890), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n4619) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1318), .CK(clk), .RN(
n4886), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]), .QN(n4618) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2082), .CK(clk), .RN(n4925),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n4613) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1466), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_EXP_EWSW[24]), .QN(n4612) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1418), .CK(clk), .RN(n4899),
.Q(FPADDSUB_DmP_EXP_EWSW[24]), .QN(n4610) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1918), .CK(clk), .RN(
n4879), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n4609) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1917), .CK(clk), .RN(
n4876), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n4608) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1207), .CK(clk), .RN(
n4891), .QN(n4603) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1919), .CK(clk), .RN(
n4872), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n4602) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1340), .CK(clk), .RN(
n4887), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n4601) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(
n4874), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n4597) );
CMPR42X1TS mult_x_69_U292 ( .A(mult_x_69_n471), .B(mult_x_69_n747), .C(
mult_x_69_n474), .D(mult_x_69_n771), .ICI(mult_x_69_n472), .S(
mult_x_69_n469), .ICO(mult_x_69_n467), .CO(mult_x_69_n468) );
CMPR42X1TS mult_x_69_U290 ( .A(mult_x_69_n746), .B(mult_x_69_n466), .C(
mult_x_69_n467), .D(mult_x_69_n770), .ICI(mult_x_69_n468), .S(
mult_x_69_n464), .ICO(mult_x_69_n462), .CO(mult_x_69_n463) );
CMPR42X1TS mult_x_69_U285 ( .A(mult_x_69_n744), .B(mult_x_69_n454), .C(
mult_x_69_n457), .D(mult_x_69_n768), .ICI(mult_x_69_n458), .S(
mult_x_69_n452), .ICO(mult_x_69_n450), .CO(mult_x_69_n451) );
CMPR42X1TS mult_x_69_U277 ( .A(mult_x_69_n435), .B(mult_x_69_n693), .C(
mult_x_69_n441), .D(mult_x_69_n717), .ICI(mult_x_69_n439), .S(
mult_x_69_n433), .ICO(mult_x_69_n431), .CO(mult_x_69_n432) );
CMPR42X1TS mult_x_69_U276 ( .A(mult_x_69_n741), .B(mult_x_69_n433), .C(
mult_x_69_n436), .D(mult_x_69_n765), .ICI(mult_x_69_n437), .S(
mult_x_69_n430), .ICO(mult_x_69_n428), .CO(mult_x_69_n429) );
CMPR42X1TS mult_x_69_U274 ( .A(mult_x_69_n692), .B(mult_x_69_n427), .C(
mult_x_69_n431), .D(mult_x_69_n716), .ICI(mult_x_69_n432), .S(
mult_x_69_n425), .ICO(mult_x_69_n423), .CO(mult_x_69_n424) );
CMPR42X1TS mult_x_69_U273 ( .A(mult_x_69_n740), .B(mult_x_69_n425), .C(
mult_x_69_n428), .D(mult_x_69_n764), .ICI(mult_x_69_n429), .S(
mult_x_69_n422), .ICO(mult_x_69_n420), .CO(mult_x_69_n421) );
CMPR42X1TS mult_x_69_U271 ( .A(mult_x_69_n691), .B(mult_x_69_n419), .C(
mult_x_69_n423), .D(mult_x_69_n715), .ICI(mult_x_69_n424), .S(
mult_x_69_n417), .ICO(mult_x_69_n415), .CO(mult_x_69_n416) );
CMPR42X1TS mult_x_69_U270 ( .A(mult_x_69_n739), .B(mult_x_69_n417), .C(
mult_x_69_n420), .D(mult_x_69_n763), .ICI(mult_x_69_n421), .S(
mult_x_69_n414), .ICO(mult_x_69_n412), .CO(mult_x_69_n413) );
CMPR42X1TS mult_x_69_U267 ( .A(mult_x_69_n690), .B(mult_x_69_n409), .C(
mult_x_69_n415), .D(mult_x_69_n714), .ICI(mult_x_69_n416), .S(
mult_x_69_n407), .ICO(mult_x_69_n405), .CO(mult_x_69_n406) );
CMPR42X1TS mult_x_69_U266 ( .A(mult_x_69_n738), .B(mult_x_69_n407), .C(
mult_x_69_n412), .D(mult_x_69_n762), .ICI(mult_x_69_n413), .S(
mult_x_69_n404), .ICO(mult_x_69_n402), .CO(mult_x_69_n403) );
CMPR42X1TS mult_x_69_U263 ( .A(mult_x_69_n689), .B(mult_x_69_n399), .C(
mult_x_69_n405), .D(mult_x_69_n713), .ICI(mult_x_69_n406), .S(
mult_x_69_n397), .ICO(mult_x_69_n395), .CO(mult_x_69_n396) );
CMPR42X1TS mult_x_69_U259 ( .A(mult_x_69_n688), .B(mult_x_69_n389), .C(
mult_x_69_n395), .D(mult_x_69_n712), .ICI(mult_x_69_n396), .S(
mult_x_69_n387), .ICO(mult_x_69_n385), .CO(mult_x_69_n386) );
CMPR42X1TS mult_x_69_U258 ( .A(mult_x_69_n387), .B(mult_x_69_n736), .C(
mult_x_69_n392), .D(mult_x_69_n760), .ICI(mult_x_69_n393), .S(
mult_x_69_n384), .ICO(mult_x_69_n382), .CO(mult_x_69_n383) );
CMPR42X1TS mult_x_69_U256 ( .A(mult_x_69_n381), .B(mult_x_69_n639), .C(
mult_x_69_n390), .D(mult_x_69_n663), .ICI(mult_x_69_n388), .S(
mult_x_69_n379), .ICO(mult_x_69_n377), .CO(mult_x_69_n378) );
CMPR42X1TS mult_x_69_U255 ( .A(mult_x_69_n687), .B(mult_x_69_n379), .C(
mult_x_69_n385), .D(mult_x_69_n711), .ICI(mult_x_69_n386), .S(
mult_x_69_n376), .ICO(mult_x_69_n374), .CO(mult_x_69_n375) );
CMPR42X1TS mult_x_69_U254 ( .A(mult_x_69_n376), .B(mult_x_69_n735), .C(
mult_x_69_n382), .D(mult_x_69_n759), .ICI(mult_x_69_n383), .S(
mult_x_69_n373), .ICO(mult_x_69_n371), .CO(mult_x_69_n372) );
CMPR42X1TS mult_x_69_U252 ( .A(mult_x_69_n370), .B(mult_x_69_n638), .C(
mult_x_69_n377), .D(mult_x_69_n662), .ICI(mult_x_69_n378), .S(
mult_x_69_n368), .ICO(mult_x_69_n366), .CO(mult_x_69_n367) );
CMPR42X1TS mult_x_69_U251 ( .A(mult_x_69_n686), .B(mult_x_69_n368), .C(
mult_x_69_n374), .D(mult_x_69_n710), .ICI(mult_x_69_n375), .S(
mult_x_69_n365), .ICO(mult_x_69_n363), .CO(mult_x_69_n364) );
CMPR42X1TS mult_x_69_U250 ( .A(mult_x_69_n365), .B(mult_x_69_n734), .C(
mult_x_69_n371), .D(mult_x_69_n758), .ICI(mult_x_69_n372), .S(
mult_x_69_n362), .ICO(mult_x_69_n360), .CO(mult_x_69_n361) );
CMPR42X1TS mult_x_69_U248 ( .A(mult_x_69_n359), .B(mult_x_69_n637), .C(
mult_x_69_n366), .D(mult_x_69_n661), .ICI(mult_x_69_n367), .S(
mult_x_69_n357), .ICO(mult_x_69_n355), .CO(mult_x_69_n356) );
CMPR42X1TS mult_x_69_U247 ( .A(mult_x_69_n685), .B(mult_x_69_n357), .C(
mult_x_69_n363), .D(mult_x_69_n709), .ICI(mult_x_69_n364), .S(
mult_x_69_n354), .ICO(mult_x_69_n352), .CO(mult_x_69_n353) );
CMPR42X1TS mult_x_69_U246 ( .A(mult_x_69_n354), .B(mult_x_69_n733), .C(
mult_x_69_n360), .D(mult_x_69_n757), .ICI(mult_x_69_n361), .S(
mult_x_69_n351), .ICO(mult_x_69_n349), .CO(mult_x_69_n350) );
CMPR42X1TS mult_x_69_U244 ( .A(mult_x_69_n348), .B(mult_x_69_n636), .C(
mult_x_69_n355), .D(mult_x_69_n660), .ICI(mult_x_69_n356), .S(
mult_x_69_n346), .ICO(mult_x_69_n344), .CO(mult_x_69_n345) );
CMPR42X1TS mult_x_69_U243 ( .A(mult_x_69_n684), .B(mult_x_69_n346), .C(
mult_x_69_n352), .D(mult_x_69_n708), .ICI(mult_x_69_n353), .S(
mult_x_69_n343), .ICO(mult_x_69_n341), .CO(mult_x_69_n342) );
CMPR42X1TS mult_x_69_U242 ( .A(mult_x_69_n343), .B(mult_x_69_n732), .C(
mult_x_69_n349), .D(mult_x_69_n756), .ICI(mult_x_69_n350), .S(
mult_x_69_n340), .ICO(mult_x_69_n338), .CO(mult_x_69_n339) );
CMPR42X1TS mult_x_69_U240 ( .A(mult_x_69_n337), .B(mult_x_69_n635), .C(
mult_x_69_n344), .D(mult_x_69_n659), .ICI(mult_x_69_n345), .S(
mult_x_69_n335), .ICO(mult_x_69_n333), .CO(mult_x_69_n334) );
CMPR42X1TS mult_x_69_U239 ( .A(mult_x_69_n335), .B(mult_x_69_n683), .C(
mult_x_69_n341), .D(mult_x_69_n707), .ICI(mult_x_69_n342), .S(
mult_x_69_n332), .ICO(mult_x_69_n330), .CO(mult_x_69_n331) );
CMPR42X1TS mult_x_69_U236 ( .A(mult_x_69_n326), .B(mult_x_69_n336), .C(
mult_x_69_n634), .D(mult_x_69_n333), .ICI(mult_x_69_n658), .S(
mult_x_69_n324), .ICO(mult_x_69_n322), .CO(mult_x_69_n323) );
CMPR42X1TS mult_x_69_U235 ( .A(mult_x_69_n324), .B(mult_x_69_n334), .C(
mult_x_69_n682), .D(mult_x_69_n330), .ICI(mult_x_69_n706), .S(
mult_x_69_n321), .ICO(mult_x_69_n319), .CO(mult_x_69_n320) );
CMPR42X1TS mult_x_69_U234 ( .A(mult_x_69_n331), .B(mult_x_69_n321), .C(
mult_x_69_n730), .D(mult_x_69_n327), .ICI(mult_x_69_n328), .S(
mult_x_69_n318), .ICO(mult_x_69_n316), .CO(mult_x_69_n317) );
CMPR42X1TS mult_x_69_U232 ( .A(mult_x_69_n325), .B(mult_x_69_n315), .C(
mult_x_69_n322), .D(mult_x_69_n633), .ICI(mult_x_69_n323), .S(
mult_x_69_n313), .ICO(mult_x_69_n311), .CO(mult_x_69_n312) );
CMPR42X1TS mult_x_69_U231 ( .A(mult_x_69_n657), .B(mult_x_69_n313), .C(
mult_x_69_n319), .D(mult_x_69_n681), .ICI(mult_x_69_n320), .S(
mult_x_69_n310), .ICO(mult_x_69_n308), .CO(mult_x_69_n309) );
CMPR42X1TS mult_x_69_U230 ( .A(mult_x_69_n705), .B(mult_x_69_n310), .C(
mult_x_69_n316), .D(mult_x_69_n729), .ICI(mult_x_69_n753), .S(
mult_x_69_n307), .ICO(mult_x_69_n305), .CO(mult_x_69_n306) );
CMPR42X1TS mult_x_69_U228 ( .A(mult_x_69_n314), .B(mult_x_69_n304), .C(
mult_x_69_n311), .D(mult_x_69_n632), .ICI(mult_x_69_n312), .S(
mult_x_69_n302), .ICO(mult_x_69_n300), .CO(mult_x_69_n301) );
CMPR42X1TS mult_x_69_U227 ( .A(mult_x_69_n656), .B(mult_x_69_n302), .C(
mult_x_69_n308), .D(mult_x_69_n680), .ICI(mult_x_69_n309), .S(
mult_x_69_n299), .ICO(mult_x_69_n297), .CO(mult_x_69_n298) );
CMPR42X1TS mult_x_69_U226 ( .A(mult_x_69_n704), .B(mult_x_69_n299), .C(
mult_x_69_n305), .D(mult_x_69_n728), .ICI(mult_x_69_n752), .S(
mult_x_69_n296), .ICO(mult_x_69_n294), .CO(mult_x_69_n295) );
CMPR42X1TS mult_x_69_U224 ( .A(mult_x_69_n293), .B(mult_x_69_n608), .C(
mult_x_69_n303), .D(mult_x_69_n300), .ICI(mult_x_69_n631), .S(
mult_x_69_n291), .ICO(mult_x_69_n289), .CO(mult_x_69_n290) );
CMPR42X1TS mult_x_69_U223 ( .A(mult_x_69_n291), .B(mult_x_69_n301), .C(
mult_x_69_n655), .D(mult_x_69_n297), .ICI(mult_x_69_n679), .S(
mult_x_69_n288), .ICO(mult_x_69_n286), .CO(mult_x_69_n287) );
CMPR42X1TS mult_x_69_U222 ( .A(mult_x_69_n288), .B(mult_x_69_n298), .C(
mult_x_69_n703), .D(mult_x_69_n294), .ICI(mult_x_69_n295), .S(
mult_x_69_n285), .ICO(mult_x_69_n283), .CO(mult_x_69_n284) );
CMPR42X1TS mult_x_69_U220 ( .A(n2272), .B(mult_x_69_n292), .C(mult_x_69_n289), .D(mult_x_69_n607), .ICI(mult_x_69_n630), .S(mult_x_69_n281), .ICO(
mult_x_69_n279), .CO(mult_x_69_n280) );
CMPR42X1TS mult_x_69_U219 ( .A(mult_x_69_n290), .B(mult_x_69_n281), .C(
mult_x_69_n286), .D(mult_x_69_n654), .ICI(mult_x_69_n678), .S(
mult_x_69_n278), .ICO(mult_x_69_n276), .CO(mult_x_69_n277) );
CMPR42X1TS mult_x_69_U218 ( .A(mult_x_69_n287), .B(mult_x_69_n278), .C(
mult_x_69_n283), .D(mult_x_69_n702), .ICI(mult_x_69_n726), .S(
mult_x_69_n275), .ICO(mult_x_69_n273), .CO(mult_x_69_n274) );
CMPR42X1TS mult_x_69_U216 ( .A(FPMULT_Op_MY[6]), .B(mult_x_69_n272), .C(
mult_x_69_n279), .D(mult_x_69_n606), .ICI(mult_x_69_n280), .S(
mult_x_69_n271), .ICO(mult_x_69_n269), .CO(mult_x_69_n270) );
CMPR42X1TS mult_x_69_U215 ( .A(mult_x_69_n629), .B(mult_x_69_n271), .C(
mult_x_69_n276), .D(mult_x_69_n653), .ICI(mult_x_69_n277), .S(
mult_x_69_n268), .ICO(mult_x_69_n266), .CO(mult_x_69_n267) );
CMPR42X1TS mult_x_69_U214 ( .A(mult_x_69_n677), .B(mult_x_69_n268), .C(
mult_x_69_n273), .D(mult_x_69_n701), .ICI(mult_x_69_n725), .S(
mult_x_69_n265), .ICO(mult_x_69_n263), .CO(mult_x_69_n264) );
CMPR42X1TS mult_x_69_U213 ( .A(n4596), .B(FPMULT_Op_MY[8]), .C(
FPMULT_Op_MY[7]), .D(mult_x_69_n269), .ICI(mult_x_69_n605), .S(
mult_x_69_n262), .ICO(mult_x_69_n260), .CO(mult_x_69_n261) );
CMPR42X1TS mult_x_69_U212 ( .A(mult_x_69_n262), .B(mult_x_69_n270), .C(
mult_x_69_n628), .D(mult_x_69_n266), .ICI(mult_x_69_n652), .S(
mult_x_69_n259), .ICO(mult_x_69_n257), .CO(mult_x_69_n258) );
CMPR42X1TS mult_x_69_U211 ( .A(mult_x_69_n259), .B(mult_x_69_n267), .C(
mult_x_69_n676), .D(mult_x_69_n263), .ICI(mult_x_69_n264), .S(
mult_x_69_n256), .ICO(mult_x_69_n254), .CO(mult_x_69_n255) );
CMPR42X1TS mult_x_69_U208 ( .A(mult_x_69_n261), .B(mult_x_69_n252), .C(
mult_x_69_n257), .D(mult_x_69_n627), .ICI(mult_x_69_n651), .S(
mult_x_69_n250), .ICO(mult_x_69_n248), .CO(mult_x_69_n249) );
CMPR42X1TS mult_x_69_U207 ( .A(mult_x_69_n258), .B(mult_x_69_n250), .C(
mult_x_69_n254), .D(mult_x_69_n675), .ICI(mult_x_69_n699), .S(
mult_x_69_n247), .ICO(mult_x_69_n245), .CO(mult_x_69_n246) );
CMPR42X1TS mult_x_69_U204 ( .A(mult_x_69_n251), .B(mult_x_69_n243), .C(
mult_x_69_n248), .D(mult_x_69_n626), .ICI(mult_x_69_n249), .S(
mult_x_69_n241), .ICO(mult_x_69_n239), .CO(mult_x_69_n240) );
CMPR42X1TS mult_x_69_U203 ( .A(mult_x_69_n650), .B(mult_x_69_n241), .C(
mult_x_69_n245), .D(mult_x_69_n674), .ICI(mult_x_69_n698), .S(
mult_x_69_n238), .ICO(mult_x_69_n236), .CO(mult_x_69_n237) );
CMPR42X1TS mult_x_69_U201 ( .A(mult_x_69_n235), .B(mult_x_69_n242), .C(
mult_x_69_n602), .D(mult_x_69_n239), .ICI(mult_x_69_n625), .S(
mult_x_69_n233), .ICO(mult_x_69_n231), .CO(mult_x_69_n232) );
CMPR42X1TS mult_x_69_U200 ( .A(mult_x_69_n233), .B(mult_x_69_n240), .C(
mult_x_69_n649), .D(mult_x_69_n236), .ICI(mult_x_69_n237), .S(
mult_x_69_n230), .ICO(mult_x_69_n228), .CO(mult_x_69_n229) );
CMPR42X1TS mult_x_69_U198 ( .A(n2271), .B(mult_x_69_n234), .C(mult_x_69_n231), .D(mult_x_69_n601), .ICI(mult_x_69_n624), .S(mult_x_69_n226), .ICO(
mult_x_69_n224), .CO(mult_x_69_n225) );
CMPR42X1TS mult_x_69_U197 ( .A(mult_x_69_n232), .B(mult_x_69_n226), .C(
mult_x_69_n228), .D(mult_x_69_n648), .ICI(mult_x_69_n672), .S(
mult_x_69_n223), .ICO(mult_x_69_n221), .CO(mult_x_69_n222) );
CMPR42X1TS mult_x_69_U195 ( .A(FPMULT_Op_MY[12]), .B(mult_x_69_n220), .C(
mult_x_69_n224), .D(mult_x_69_n600), .ICI(mult_x_69_n225), .S(
mult_x_69_n219), .ICO(mult_x_69_n217), .CO(mult_x_69_n218) );
CMPR42X1TS mult_x_69_U194 ( .A(mult_x_69_n623), .B(mult_x_69_n219), .C(
mult_x_69_n221), .D(mult_x_69_n647), .ICI(mult_x_69_n671), .S(
mult_x_69_n216), .ICO(mult_x_69_n214), .CO(mult_x_69_n215) );
CMPR42X1TS mult_x_69_U193 ( .A(n2348), .B(FPMULT_Op_MY[13]), .C(
FPMULT_Op_MY[14]), .D(mult_x_69_n217), .ICI(mult_x_69_n599), .S(
mult_x_69_n213), .ICO(mult_x_69_n211), .CO(mult_x_69_n212) );
CMPR42X1TS mult_x_69_U192 ( .A(mult_x_69_n213), .B(mult_x_69_n218), .C(
mult_x_69_n622), .D(mult_x_69_n214), .ICI(mult_x_69_n215), .S(
mult_x_69_n210), .ICO(mult_x_69_n208), .CO(mult_x_69_n209) );
CMPR42X1TS mult_x_69_U189 ( .A(mult_x_69_n212), .B(mult_x_69_n206), .C(
mult_x_69_n208), .D(mult_x_69_n621), .ICI(mult_x_69_n645), .S(
mult_x_69_n204), .ICO(mult_x_69_n202), .CO(mult_x_69_n203) );
CMPR42X1TS mult_x_69_U186 ( .A(mult_x_69_n597), .B(mult_x_69_n200), .C(
mult_x_69_n202), .D(mult_x_69_n620), .ICI(mult_x_69_n644), .S(
mult_x_69_n198), .ICO(mult_x_69_n196), .CO(mult_x_69_n197) );
CMPR42X1TS mult_x_69_U184 ( .A(mult_x_69_n195), .B(mult_x_69_n199), .C(
mult_x_69_n596), .D(mult_x_69_n196), .ICI(mult_x_69_n197), .S(
mult_x_69_n193), .ICO(mult_x_69_n191), .CO(mult_x_69_n192) );
CMPR42X1TS mult_x_69_U182 ( .A(n4595), .B(mult_x_69_n194), .C(mult_x_69_n191), .D(mult_x_69_n595), .ICI(mult_x_69_n618), .S(mult_x_69_n189), .ICO(
mult_x_69_n187), .CO(mult_x_69_n188) );
CMPR42X1TS mult_x_69_U180 ( .A(FPMULT_Op_MY[19]), .B(n4595), .C(
mult_x_69_n187), .D(mult_x_69_n594), .ICI(mult_x_69_n617), .S(
mult_x_69_n185), .ICO(mult_x_69_n183), .CO(mult_x_69_n184) );
CMPR42X1TS mult_x_69_U179 ( .A(n2316), .B(FPMULT_Op_MY[18]), .C(
FPMULT_Op_MY[20]), .D(mult_x_69_n183), .ICI(mult_x_69_n593), .S(
mult_x_69_n182), .ICO(mult_x_69_n180), .CO(mult_x_69_n181) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2150), .CK(clk), .RN(
n4897), .Q(n4870), .QN(n4952) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2143), .CK(clk), .RN(n4920),
.Q(n4871), .QN(n4951) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1627), .CK(clk),
.RN(n4934), .Q(FPMULT_Op_MY[0]), .QN(n2203) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n4872),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n4604) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1691), .CK(clk), .RN(n4930), .Q(
FPMULT_FSM_selector_A), .QN(n4780) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1348), .CK(clk), .RN(
n4885), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n4600) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2142), .CK(clk), .RN(n4920),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n4704) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2140), .CK(clk), .RN(n4923),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n4623) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2139), .CK(clk), .RN(n4919),
.Q(FPSENCOS_cont_var_out[0]), .QN(n4611) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1550), .CK(clk), .RN(n4934), .Q(
FPMULT_FSM_selector_B[1]), .QN(n4708) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1693), .CK(clk), .RN(n4916),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n4599) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1694), .CK(clk), .RN(n4912),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n4685) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1695), .CK(clk), .RN(n4913),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n4621) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1335), .CK(clk), .RN(
n4887), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n4598) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1842), .CK(clk), .RN(
n4875), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n4688) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1915), .CK(clk), .RN(
n4898), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n4774) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1826), .CK(clk), .RN(
n4884), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n4637) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1831), .CK(clk), .RN(
n4896), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n4684) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1834), .CK(clk), .RN(
n4895), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n4693) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1828), .CK(clk), .RN(
n4881), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n4702) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1830), .CK(clk), .RN(
n4874), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n4628) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1939), .CK(clk), .RN(
n4872), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n4752) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1937), .CK(clk), .RN(
n4876), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n4648) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1933), .CK(clk), .RN(
n4878), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n4754) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1936), .CK(clk), .RN(
n3152), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n4766) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1938), .CK(clk), .RN(
n3152), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n4646) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1823), .CK(clk), .RN(
n4889), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n4633) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1825), .CK(clk), .RN(
n4882), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n4696) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1844), .CK(clk), .RN(
n4900), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n4691) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1837), .CK(clk), .RN(
n4876), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n4701) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1821), .CK(clk), .RN(
n4900), .Q(FPADDSUB_intDY_EWSW[24]), .QN(n4661) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1822), .CK(clk), .RN(
n4879), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n4695) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1824), .CK(clk), .RN(
n4890), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n4698) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1827), .CK(clk), .RN(
n4890), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n4733) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1832), .CK(clk), .RN(
n4873), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n4697) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1838), .CK(clk), .RN(
n4878), .Q(FPADDSUB_intDY_EWSW[7]), .QN(n4746) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1833), .CK(clk), .RN(
n4893), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n4690) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1927), .CK(clk), .RN(
n4900), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n4756) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1920), .CK(clk), .RN(
n4873), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n4747) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2193), .CK(
clk), .RN(n4876), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n4625) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n4898), .Q(ready_add_subt), .QN(n4776) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2149), .CK(clk), .RN(
n4899), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n4941) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1351), .CK(clk), .RN(
n4875), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n4775) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1350), .CK(clk), .RN(
n4884), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n4627) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2081), .CK(clk), .RN(
n3152), .Q(FPADDSUB_bit_shift_SHT2), .QN(n4742) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_SFG[15]), .QN(n4694) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SFG[22]), .QN(n4773) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_SFG[21]), .QN(n4763) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_SFG[17]), .QN(n4636) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_SFG[13]), .QN(n4686) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n4896),
.Q(FPADDSUB_DMP_SFG[11]), .QN(n4622) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n4886),
.Q(FPADDSUB_DMP_SFG[5]), .QN(n4667) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n4887),
.Q(FPADDSUB_DMP_SFG[1]), .QN(n4664) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SFG[19]), .QN(n4745) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n4890),
.Q(FPADDSUB_DMP_SFG[7]), .QN(n4670) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n4887),
.Q(FPADDSUB_DMP_SFG[0]), .QN(n4666) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n4888),
.Q(FPADDSUB_DMP_SFG[9]), .QN(n4676) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n4890),
.Q(FPADDSUB_DMP_SFG[3]), .QN(n4665) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n4908), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n4699) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n4914), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .QN(n4634) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1346), .CK(clk), .RN(
n4884), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n4607) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(n4902), .Q(
FPSENCOS_d_ff_Yn[31]), .QN(n4789) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1551), .CK(clk), .RN(n4934), .Q(
FPMULT_FSM_selector_B[0]), .QN(n4703) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1956), .CK(clk), .RN(
n4922), .Q(FPSENCOS_d_ff2_X[28]), .QN(n4785) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1345), .CK(clk), .RN(
n4882), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n4606) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1622), .CK(clk), .RN(
n4930), .Q(FPMULT_Add_result[2]), .QN(n4794) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1625), .CK(
clk), .RN(n4933), .Q(FPMULT_Sgf_normalized_result[23]), .QN(n4795) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1182), .CK(clk), .RN(
n4876), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n4790) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1344), .CK(clk), .RN(
n4875), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n4638) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1194), .CK(clk), .RN(
n4894), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n4682) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1195), .CK(clk), .RN(
n4877), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n4680) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1184), .CK(clk), .RN(
n4873), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n4651) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1204), .CK(clk), .RN(
n4891), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n4614) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1185), .CK(clk), .RN(
n4873), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n4764) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1196), .CK(clk), .RN(
n4892), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n4620) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1197), .CK(clk), .RN(
n4896), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n4675) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1203), .CK(clk), .RN(
n4895), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n4668) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1186), .CK(clk), .RN(
n4898), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n4644) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1187), .CK(clk), .RN(
n4900), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n4741) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1202), .CK(clk), .RN(
n4878), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n4615) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1192), .CK(clk), .RN(
n4897), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n4626) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1193), .CK(clk), .RN(
n4898), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n4683) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1200), .CK(clk), .RN(
n4893), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n4616) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1201), .CK(clk), .RN(
n4894), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n4669) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1188), .CK(clk), .RN(
n4873), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n4740) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1189), .CK(clk), .RN(
n4873), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n4705) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1198), .CK(clk), .RN(
n4877), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n4617) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1199), .CK(clk), .RN(
n4891), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n4672) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1190), .CK(clk), .RN(
n4898), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n4630) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(
n4876), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n4687) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1856), .CK(clk), .RN(
n4927), .Q(FPSENCOS_d_ff2_Y[30]), .QN(n4786) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1857), .CK(clk), .RN(
n4928), .Q(FPSENCOS_d_ff2_Y[29]), .QN(n4783) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1859), .CK(clk), .RN(
n4919), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n4784) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(
n4880), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n4605) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1521), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n4671) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1535), .CK(
clk), .RN(n4934), .Q(FPMULT_Sgf_normalized_result[18]), .QN(n4743) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1533), .CK(
clk), .RN(n4938), .Q(FPMULT_Sgf_normalized_result[16]), .QN(n4732) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1531), .CK(
clk), .RN(n4933), .Q(FPMULT_Sgf_normalized_result[14]), .QN(n4692) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1537), .CK(
clk), .RN(n4935), .Q(FPMULT_Sgf_normalized_result[20]), .QN(n4767) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1529), .CK(
clk), .RN(n4936), .Q(FPMULT_Sgf_normalized_result[12]), .QN(n4681) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1527), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n4679) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n4914), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .QN(n4734) );
DFFSX1TS R_1 ( .D(n4867), .CK(clk), .SN(n4929), .Q(n4949) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1649), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[22]), .QN(n2224) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1661), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[2]), .QN(n2317) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1640), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[13]), .QN(n2215) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1635), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[8]), .QN(n2210) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1632), .CK(clk),
.RN(n4934), .Q(FPMULT_Op_MY[5]), .QN(n2209) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1648), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[21]), .QN(n2311) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1646), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[19]), .QN(n2218) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1643), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[16]), .QN(n2217) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1840), .CK(clk), .RN(
n4889), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2138), .CK(clk), .RN(n4919),
.Q(FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1839), .CK(clk), .RN(
n4879), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1673), .CK(clk),
.RN(n4939), .Q(FPMULT_Op_MX[14]), .QN(n2320) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1835), .CK(clk), .RN(
n4894), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1843), .CK(clk), .RN(
n4876), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1667), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[8]), .QN(n2321) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1829), .CK(clk), .RN(
n4897), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1818), .CK(clk), .RN(
n4879), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1517), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1692), .CK(clk), .RN(n4913),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n2225) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2078), .CK(clk), .RN(
n4891), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1183), .CK(clk), .RN(
n4879), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1845), .CK(clk), .RN(
n4887), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1659), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[0]), .QN(n2202) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1681), .CK(clk),
.RN(n4869), .Q(FPMULT_Op_MX[22]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n4892),
.Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n4877),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n4891),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n4878),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n4893),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n4894),
.Q(FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n4886),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n4888),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1323), .CK(clk), .RN(
n3213), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1628), .CK(clk),
.RN(n4934), .Q(FPMULT_Op_MY[1]), .QN(n2204) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1806), .CK(clk), .RN(n4898), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1805), .CK(clk), .RN(n4873), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1807), .CK(clk), .RN(n4898), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1808), .CK(clk), .RN(n4875), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1802), .CK(clk), .RN(n4877), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1801), .CK(clk), .RN(n4893), .Q(FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1205), .CK(clk), .RN(
n4896), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1349), .CK(clk), .RN(
n4880), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1957), .CK(clk), .RN(
n4926), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1468), .CK(clk), .RN(
n4873), .Q(result_add_subt[30]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1469), .CK(clk), .RN(
n4872), .Q(result_add_subt[29]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1473), .CK(clk), .RN(
n4899), .Q(result_add_subt[25]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1475), .CK(clk), .RN(
n4899), .Q(result_add_subt[23]) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2146), .CK(clk), .RN(
n4899), .QN(n4942) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n4903), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n4920), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1955), .CK(clk), .RN(
n4903), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(
n4934), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1961), .CK(clk), .RN(
n4918), .Q(FPSENCOS_d_ff2_X[23]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1520), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[3]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1522), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[5]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1524), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[7]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1526), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[9]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1528), .CK(
clk), .RN(n4937), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1530), .CK(
clk), .RN(n4930), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1532), .CK(
clk), .RN(n4934), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1534), .CK(
clk), .RN(n4938), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1536), .CK(
clk), .RN(n4935), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1538), .CK(
clk), .RN(n4936), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1912), .CK(clk), .RN(
n4885), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX2TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1353), .CK(clk), .RN(n4883),
.Q(FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1678), .CK(clk),
.RN(n4869), .Q(FPMULT_Op_MX[19]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1674), .CK(clk),
.RN(n4869), .Q(FPMULT_Op_MX[15]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1680), .CK(clk),
.RN(n4869), .Q(FPMULT_Op_MX[21]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1677), .CK(clk),
.RN(n4869), .Q(FPMULT_Op_MX[18]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1676), .CK(clk),
.RN(n4869), .Q(FPMULT_Op_MX[17]), .QN(n2318) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1958), .CK(clk), .RN(
n4905), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1959), .CK(clk), .RN(
n4926), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1960), .CK(clk), .RN(
n4916), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1412), .CK(clk), .RN(
n4885), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n2220) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_47_ ( .D(n1552), .CK(clk), .RN(
n4913), .Q(FPMULT_P_Sgf[47]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1796), .CK(clk), .RN(n4899),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1795), .CK(clk), .RN(n4882),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n2233), .CK(clk),
.RN(n4939), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n2232), .CK(clk),
.RN(n4934), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n2231), .CK(clk),
.RN(n4930), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1419), .CK(clk), .RN(n4899),
.Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1735), .CK(clk), .RN(
n4902), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n4901),
.Q(operation_reg[0]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1657), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1954), .CK(clk), .RN(
n4924), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n4924),
.Q(operation_reg[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n4927), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n4907), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n3149), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n4916), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n4914), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n4903), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n4903), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n4904), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n4929), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n4929), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n4919), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n4908), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n4908), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n4909), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n4915), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n3149), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n4910), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n4929), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n4907), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n4928), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n4926), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n4923), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n4923), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1544), .CK(clk), .RN(
n4933), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1546), .CK(clk), .RN(
n4933), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1547), .CK(clk), .RN(
n4933), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1548), .CK(clk), .RN(
n4933), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1549), .CK(clk), .RN(
n4933), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2060), .CK(clk), .RN(n4915), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2048), .CK(clk), .RN(n4915), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2072), .CK(clk), .RN(n4904), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2075), .CK(clk), .RN(n3149), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2054), .CK(clk), .RN(n4916), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2069), .CK(clk), .RN(n4927), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2066), .CK(clk), .RN(n4901), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2039), .CK(clk), .RN(n4903), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2045), .CK(clk), .RN(n4903), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2033), .CK(clk), .RN(n4904), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2042), .CK(clk), .RN(n4905), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2051), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2027), .CK(clk), .RN(n4921), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2036), .CK(clk), .RN(n4917), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2057), .CK(clk), .RN(n4907), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2063), .CK(clk), .RN(n4907), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2024), .CK(clk), .RN(n4908), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2015), .CK(clk), .RN(n4909), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2018), .CK(clk), .RN(n4909), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2012), .CK(clk), .RN(n4925), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2021), .CK(clk), .RN(n4906), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2030), .CK(clk), .RN(n4923), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2009), .CK(clk), .RN(n4928), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1772), .CK(clk), .RN(n4924), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n4926), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1778), .CK(clk), .RN(n4920), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1784), .CK(clk), .RN(n4904), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1600), .CK(clk),
.RN(n4936), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1663), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[4]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1662), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[3]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1730), .CK(clk), .RN(
n4885), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1420), .CK(clk), .RN(
n4873), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1425), .CK(clk), .RN(
n4900), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1430), .CK(clk), .RN(
n4879), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1435), .CK(clk), .RN(
n4899), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1440), .CK(clk), .RN(
n4879), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1445), .CK(clk), .RN(
n4873), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1450), .CK(clk), .RN(
n4897), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1455), .CK(clk), .RN(
n4872), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1666), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[7]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1665), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[6]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n4901),
.Q(cordic_result[31]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n4921), .Q(
dataA[29]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1792), .CK(clk), .RN(n4882),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1791), .CK(clk), .RN(n4889),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1790), .CK(clk), .RN(n4888),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1855), .CK(clk), .RN(n4911),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2117), .CK(clk), .RN(n4924), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2118), .CK(clk), .RN(n4928), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2125), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2130), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2116), .CK(clk), .RN(n4929), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n4868), .Q(
dataB[24]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1641), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[14]), .QN(n2216) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1639), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[12]), .QN(n2213) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1633), .CK(clk),
.RN(n4934), .Q(FPMULT_Op_MY[6]), .QN(n2208) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1637), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[10]), .QN(n2212) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1634), .CK(clk),
.RN(n4934), .Q(FPMULT_Op_MY[7]), .QN(n2211) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1638), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[11]), .QN(n2214) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1629), .CK(clk),
.RN(n4934), .Q(FPMULT_Op_MY[2]), .QN(n2207) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1630), .CK(clk),
.RN(n4934), .Q(FPMULT_Op_MY[3]), .QN(n2206) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1631), .CK(clk),
.RN(n4934), .Q(FPMULT_Op_MY[4]), .QN(n2205) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1647), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[20]), .QN(n2223) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1644), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[17]), .QN(n2219) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1642), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[15]), .QN(n2315) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1636), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[9]), .QN(n2313) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1664), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[5]), .QN(n2319) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1841), .CK(clk), .RN(
n4885), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1836), .CK(clk), .RN(
n4890), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1817), .CK(clk), .RN(
n4876), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1518), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1669), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[10]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1672), .CK(clk),
.RN(n4939), .Q(FPMULT_Op_MX[13]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1668), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[9]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1675), .CK(clk),
.RN(n4944), .Q(FPMULT_Op_MX[16]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1671), .CK(clk),
.RN(n4939), .Q(FPMULT_Op_MX[12]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1798), .CK(clk), .RN(n4895),
.Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1800), .CK(clk), .RN(n4878), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1799), .CK(clk), .RN(n4881), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1797), .CK(clk), .RN(n4878),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1519), .CK(
clk), .RN(n4932), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1645), .CK(clk),
.RN(n4935), .Q(FPMULT_Op_MY[18]), .QN(n2312) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1794), .CK(clk), .RN(n4886),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1793), .CK(clk), .RN(n4881),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n4940), .CK(clk),
.RN(n4917), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n2230), .CK(clk),
.RN(n4939), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n2229), .CK(clk),
.RN(n4939), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n2228), .CK(clk),
.RN(n4930), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n2227), .CK(clk),
.RN(n4939), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n4906), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1604), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1606), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1608), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1610), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1612), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1614), .CK(clk),
.RN(n4934), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1616), .CK(clk), .RN(
n4938), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1618), .CK(clk), .RN(
n4935), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1602), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[22]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1623), .CK(clk), .RN(
n4936), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1463), .CK(clk), .RN(n4895),
.Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1603), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1605), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1607), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1609), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1611), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1613), .CK(clk),
.RN(n4937), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1615), .CK(clk), .RN(
n4932), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1617), .CK(clk), .RN(
n4932), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1653), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1620), .CK(clk), .RN(
n4933), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1652), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1619), .CK(clk), .RN(
n4937), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1621), .CK(clk), .RN(
n4930), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n2226), .CK(clk),
.RN(n4939), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1651), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1969), .CK(clk), .RN(
n4909), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1967), .CK(clk), .RN(
n4908), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1973), .CK(clk), .RN(
n4908), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1981), .CK(clk), .RN(
n4919), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1975), .CK(clk), .RN(
n4905), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1979), .CK(clk), .RN(
n4904), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n2001), .CK(clk), .RN(
n4914), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1993), .CK(clk), .RN(
n3149), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1997), .CK(clk), .RN(
n4914), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1995), .CK(clk), .RN(
n4920), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1987), .CK(clk), .RN(
n4903), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1983), .CK(clk), .RN(
n4902), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2003), .CK(clk), .RN(
n4916), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2005), .CK(clk), .RN(
n4909), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1963), .CK(clk), .RN(
n4923), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1977), .CK(clk), .RN(
n4923), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1971), .CK(clk), .RN(
n4868), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1985), .CK(clk), .RN(
n4904), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1965), .CK(clk), .RN(
n4917), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1999), .CK(clk), .RN(
n4907), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1991), .CK(clk), .RN(
n4910), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2007), .CK(clk), .RN(
n3149), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1989), .CK(clk), .RN(
n4915), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1945), .CK(clk), .RN(
n4902), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1545), .CK(clk), .RN(
n4933), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1543), .CK(clk), .RN(
n4933), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1542), .CK(clk), .RN(
n4933), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1650), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1654), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1655), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1656), .CK(clk),
.RN(n4936), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2147), .CK(clk), .RN(
n4900), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n4908), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n4906), .Q(
FPSENCOS_d_ff_Xn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n4906), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n3151), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n4928), .Q(
FPSENCOS_d_ff_Xn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1787), .CK(clk), .RN(n4909), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1781), .CK(clk), .RN(n4868), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(n4916), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1732), .CK(clk), .RN(n4902), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n4908), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1731), .CK(clk), .RN(n4901), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1734), .CK(clk), .RN(n4902), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n4923),
.Q(cordic_result[6]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n4913),
.Q(cordic_result[4]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n4913),
.Q(cordic_result[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n4913),
.Q(cordic_result[20]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n4913),
.Q(cordic_result[19]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n4913),
.Q(cordic_result[21]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n4913),
.Q(cordic_result[18]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n4913),
.Q(cordic_result[15]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n4913),
.Q(cordic_result[22]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1752), .CK(clk), .RN(
n4904), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n4922),
.Q(cordic_result[0]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2128), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_13_ ( .D(n1566), .CK(clk), .RN(
n3151), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_20_ ( .D(n1573), .CK(clk), .RN(
n4868), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_18_ ( .D(n1571), .CK(clk), .RN(
n4868), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_16_ ( .D(n1569), .CK(clk), .RN(
n4868), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_15_ ( .D(n1568), .CK(clk), .RN(
n3151), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_12_ ( .D(n1565), .CK(clk), .RN(
n3151), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_9_ ( .D(n1562), .CK(clk), .RN(
n4905), .Q(FPMULT_P_Sgf[9]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1347), .CK(clk), .RN(
n4881), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n4629) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n4914),
.Q(cordic_result[5]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1763), .CK(clk), .RN(
n4914), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n4914),
.Q(cordic_result[3]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1733), .CK(clk), .RN(
n3213), .Q(FPADDSUB_intAS) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n4920), .Q(
dataB[30]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1858), .CK(clk), .RN(
n4904), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n2239) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2131), .CK(clk), .RN(n4918), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n4921), .Q(
dataA[30]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1415), .CK(clk), .RN(n4880),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n4921), .Q(
dataA[28]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1789), .CK(clk), .RN(n4894),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n4921), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n4921), .Q(
dataA[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n4907),
.Q(cordic_result[23]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n4906),
.Q(cordic_result[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n4916),
.Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n4919),
.Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n4905),
.Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n4928),
.Q(cordic_result[28]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n4924),
.Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n4928),
.Q(cordic_result[30]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1670), .CK(clk),
.RN(n4939), .Q(FPMULT_Op_MX[11]), .QN(n2322) );
DFFSX1TS R_3 ( .D(n4865), .CK(clk), .SN(n4910), .Q(n4945) );
DFFSX1TS R_11 ( .D(n4863), .CK(clk), .SN(n4902), .Q(n4948) );
DFFRX1TS R_12 ( .D(n4862), .CK(clk), .RN(n4914), .Q(n4947) );
DFFSX1TS R_4 ( .D(n4864), .CK(clk), .SN(n3149), .Q(n4946) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1660), .CK(clk),
.RN(n4938), .Q(FPMULT_Op_MX[1]), .QN(n2201) );
CMPR42X1TS mult_x_69_U238 ( .A(mult_x_69_n332), .B(mult_x_69_n731), .C(
mult_x_69_n338), .D(mult_x_69_n755), .ICI(mult_x_69_n779), .S(
mult_x_69_n329), .ICO(mult_x_69_n327), .CO(mult_x_69_n328) );
DFFRHQX4TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2144), .CK(clk), .RN(
n4898), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_14_ ( .D(n1567), .CK(clk), .RN(
n3151), .Q(FPMULT_P_Sgf[14]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1679), .CK(clk),
.RN(n4869), .Q(FPMULT_Op_MX[20]), .QN(n2316) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(
n4876), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n2197) );
CMPR32X2TS DP_OP_26J217_122_5882_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n2197), .C(DP_OP_26J217_122_5882_n18), .CO(DP_OP_26J217_122_5882_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J217_122_5882_U8 ( .A(DP_OP_26J217_122_5882_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J217_122_5882_n8), .CO(
DP_OP_26J217_122_5882_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J217_122_5882_U7 ( .A(DP_OP_26J217_122_5882_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J217_122_5882_n7), .CO(
DP_OP_26J217_122_5882_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2145), .CK(clk), .RN(
n4873), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]) );
CMPR32X2TS DP_OP_26J217_122_5882_U6 ( .A(DP_OP_26J217_122_5882_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J217_122_5882_n6), .CO(
DP_OP_26J217_122_5882_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J217_122_5882_U5 ( .A(DP_OP_26J217_122_5882_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J217_122_5882_n5), .CO(
DP_OP_26J217_122_5882_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J217_122_5882_U4 ( .A(n2197), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J217_122_5882_n4), .CO(
DP_OP_26J217_122_5882_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J217_122_5882_U3 ( .A(n2197), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J217_122_5882_n3), .CO(
DP_OP_26J217_122_5882_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J217_122_5882_U2 ( .A(n2197), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J217_122_5882_n2), .CO(
DP_OP_26J217_122_5882_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2148), .CK(clk), .RN(
n4876), .Q(busy), .QN(n4861) );
CMPR32X2TS intadd_492_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n4704), .C(
intadd_492_CI), .CO(intadd_492_n3), .S(intadd_492_SUM_0_) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2077), .CK(clk), .RN(
n4882), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2196) );
CMPR32X2TS intadd_491_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n4623), .C(
intadd_491_n2), .CO(intadd_491_n1), .S(intadd_491_SUM_2_) );
CMPR32X2TS intadd_492_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(intadd_491_B_1_),
.C(intadd_492_n3), .CO(intadd_492_n2), .S(intadd_492_SUM_1_) );
CMPR32X2TS intadd_492_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n4623), .C(
intadd_492_n2), .CO(intadd_492_n1), .S(intadd_492_SUM_2_) );
AO22X1TS U2219 ( .A0(n4170), .A1(FPMULT_P_Sgf[46]), .B0(n4200), .B1(n3135),
.Y(n1599) );
AO22X1TS U2220 ( .A0(n4170), .A1(FPMULT_P_Sgf[45]), .B0(n4219), .B1(n3131),
.Y(n1598) );
AO22X1TS U2221 ( .A0(n4170), .A1(FPMULT_P_Sgf[44]), .B0(n4187), .B1(n3128),
.Y(n1597) );
NAND3X4TS U2222 ( .A(FPSENCOS_cont_var_out[1]), .B(ready_add_subt), .C(n4611), .Y(n3897) );
OR3X4TS U2223 ( .A(FPSENCOS_cont_var_out[1]), .B(n4611), .C(n4776), .Y(n3952) );
AOI32X1TS U2224 ( .A0(n4871), .A1(n3978), .A2(n3937), .B0(
FPSENCOS_d_ff3_LUT_out[23]), .B1(n3983), .Y(n3222) );
AOI222X1TS U2225 ( .A0(n3512), .A1(cordic_result[13]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[13]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[13]), .Y(n3503) );
AOI222X1TS U2226 ( .A0(n3512), .A1(cordic_result[14]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[14]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[14]), .Y(n3507) );
AOI222X1TS U2227 ( .A0(n3512), .A1(cordic_result[12]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[12]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[12]), .Y(n3504) );
AOI222X1TS U2228 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n3476) );
AOI222X1TS U2229 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n3474) );
AOI222X1TS U2230 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n3473) );
AOI222X1TS U2231 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n3471) );
AOI222X1TS U2232 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n3470) );
AOI222X1TS U2233 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n3469) );
AOI222X1TS U2234 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n3468) );
AOI222X1TS U2235 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n3467) );
AOI222X1TS U2236 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n3466) );
AOI222X1TS U2237 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n3464) );
AOI222X1TS U2238 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n3463) );
AOI222X1TS U2239 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n3483) );
AOI222X1TS U2240 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n3480) );
AOI222X1TS U2241 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n3478)
);
AOI222X1TS U2242 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n3477)
);
AOI222X1TS U2243 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n3475) );
AOI222X1TS U2244 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n3472) );
AOI222X1TS U2245 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n3465) );
AOI222X1TS U2246 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n3386), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n3972), .Y(n3317)
);
AOI222X1TS U2247 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n3972), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n3312)
);
AOI222X1TS U2248 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n3972), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n3311)
);
AOI222X1TS U2249 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n3972), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n3313)
);
AOI222X1TS U2250 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n3972), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n3310)
);
AOI222X1TS U2251 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n3388) );
AOI222X1TS U2252 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n3392) );
AOI222X1TS U2253 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n3390) );
AOI222X1TS U2254 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n3387) );
AOI222X1TS U2255 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n3389)
);
AOI222X1TS U2256 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n3316)
);
AOI222X1TS U2257 ( .A0(n3512), .A1(cordic_result[11]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[11]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[11]), .Y(n3513) );
AOI222X1TS U2258 ( .A0(n3516), .A1(cordic_result[8]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[8]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[8]), .Y(n3514)
);
AOI222X1TS U2259 ( .A0(n3516), .A1(cordic_result[10]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[10]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[10]), .Y(n3517) );
AOI222X1TS U2260 ( .A0(n3516), .A1(cordic_result[1]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[1]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[1]), .Y(n3498)
);
AOI211X1TS U2261 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n3983), .B0(n3224),
.C0(n3223), .Y(n3225) );
CMPR32X2TS U2262 ( .A(mult_x_69_n181), .B(n3130), .C(n3129), .CO(n3132), .S(
n3131) );
OAI31X4TS U2263 ( .A0(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .A1(n4631),
.A2(n3894), .B0(n3892), .Y(n3950) );
CMPR32X2TS U2264 ( .A(mult_x_69_n182), .B(mult_x_69_n184), .C(n3127), .CO(
n3129), .S(n3128) );
NOR2X1TS U2265 ( .A(n3802), .B(operation[2]), .Y(n3804) );
CMPR32X2TS U2266 ( .A(mult_x_69_n188), .B(mult_x_69_n185), .C(n3125), .CO(
n3127), .S(n3126) );
CMPR32X2TS U2267 ( .A(mult_x_69_n192), .B(mult_x_69_n189), .C(n4144), .CO(
n3125), .S(n4145) );
AOI211X2TS U2268 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n3918), .B0(
n3855), .C0(n3618), .Y(n3793) );
CMPR32X2TS U2269 ( .A(mult_x_69_n193), .B(n4147), .C(n4146), .CO(n4144), .S(
n4148) );
AO22X1TS U2270 ( .A0(operation[1]), .A1(n3526), .B0(begin_operation), .B1(
n3911), .Y(n3567) );
CMPR32X2TS U2271 ( .A(FPMULT_Op_MY[17]), .B(n2524), .C(FPMULT_Op_MY[15]),
.CO(mult_x_69_n194), .S(mult_x_69_n195) );
AOI222X4TS U2272 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(
FPADDSUB_DMP_SFG[16]), .B0(FPADDSUB_DmP_mant_SFG_SWR[18]), .B1(n4470),
.C0(FPADDSUB_DMP_SFG[16]), .C1(n4470), .Y(n4478) );
CMPR32X2TS U2273 ( .A(mult_x_69_n210), .B(n4154), .C(n4153), .CO(n4151), .S(
n4155) );
CMPR32X2TS U2274 ( .A(n3049), .B(FPMULT_Op_MY[16]), .C(n2529), .CO(
mult_x_69_n199), .S(mult_x_69_n200) );
ADDFHX2TS U2275 ( .A(mult_x_69_n229), .B(mult_x_69_n223), .CI(n4158), .CO(
n4156), .S(n4159) );
CMPR32X2TS U2276 ( .A(mult_x_69_n230), .B(n4161), .C(n4160), .CO(n4158), .S(
n4162) );
CMPR32X2TS U2277 ( .A(mult_x_69_n246), .B(mult_x_69_n238), .C(n4163), .CO(
n4160), .S(n4164) );
ADDFHX2TS U2278 ( .A(mult_x_69_n255), .B(mult_x_69_n247), .CI(n4165), .CO(
n4163), .S(n4166) );
CMPR32X2TS U2279 ( .A(FPMULT_Op_MY[11]), .B(n2356), .C(FPMULT_Op_MY[9]),
.CO(mult_x_69_n234), .S(mult_x_69_n235) );
CMPR32X2TS U2280 ( .A(n2974), .B(FPMULT_Op_MY[10]), .C(n2535), .CO(
mult_x_69_n242), .S(mult_x_69_n243) );
ADDFHX2TS U2281 ( .A(mult_x_69_n274), .B(mult_x_69_n265), .CI(n4171), .CO(
n4167), .S(n4172) );
AOI222X4TS U2282 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(
FPADDSUB_DMP_SFG[6]), .B0(FPADDSUB_DmP_mant_SFG_SWR[8]), .B1(n4409),
.C0(FPADDSUB_DMP_SFG[6]), .C1(n4409), .Y(n4414) );
CMPR32X2TS U2283 ( .A(n2373), .B(n2317), .C(FPMULT_Op_MY[5]), .CO(
mult_x_69_n292), .S(mult_x_69_n293) );
AOI222X4TS U2284 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(
FPADDSUB_DMP_SFG[2]), .B0(FPADDSUB_DmP_mant_SFG_SWR[4]), .B1(n4385),
.C0(FPADDSUB_DMP_SFG[2]), .C1(n4385), .Y(n4390) );
CMPR32X2TS U2285 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MX[2]), .C(n2544), .CO(
mult_x_69_n303), .S(mult_x_69_n304) );
CMPR32X2TS U2286 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MX[2]), .C(n2548), .CO(
mult_x_69_n314), .S(mult_x_69_n315) );
CMPR32X2TS U2287 ( .A(n4192), .B(mult_x_69_n351), .C(n4191), .CO(n4188), .S(
n4193) );
CMPR32X2TS U2288 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[2]), .C(n2552), .CO(
mult_x_69_n325), .S(mult_x_69_n326) );
INVX2TS U2289 ( .A(n2646), .Y(n3019) );
CMPR32X2TS U2290 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[22]), .C(n2389),
.CO(n2334), .S(n2646) );
CMPR32X2TS U2291 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[21]), .C(n2393),
.CO(n2389), .S(n2649) );
INVX2TS U2292 ( .A(n2652), .Y(n3011) );
CMPR32X2TS U2293 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MY[20]), .C(n2397),
.CO(n2393), .S(n2652) );
INVX2TS U2294 ( .A(n2655), .Y(n3007) );
CMPR32X2TS U2295 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[19]), .C(n2401),
.CO(n2397), .S(n2655) );
CMPR32X2TS U2296 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[18]), .C(n2405),
.CO(n2401), .S(n2526) );
CMPR32X2TS U2297 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[17]), .C(n2409),
.CO(n2405), .S(n2658) );
CMPR32X2TS U2298 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[16]), .C(n2413),
.CO(n2409), .S(n2661) );
CMPR32X2TS U2299 ( .A(mult_x_69_n459), .B(n3201), .C(n3200), .CO(n3203), .S(
n3202) );
CMPR32X2TS U2300 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[15]), .C(n2417),
.CO(n2413), .S(n2664) );
CMPR32X2TS U2301 ( .A(mult_x_69_n464), .B(n3198), .C(n3197), .CO(n3200), .S(
n3199) );
CMPR32X2TS U2302 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[14]), .C(n2421),
.CO(n2417), .S(n2667) );
CMPR32X2TS U2303 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[13]), .C(n2425),
.CO(n2421), .S(n2532) );
CMPR32X2TS U2304 ( .A(n3192), .B(n3191), .C(n3190), .CO(n3194), .S(n3193) );
CMPR32X2TS U2305 ( .A(n3113), .B(n3112), .C(n3111), .CO(mult_x_69_n472), .S(
n3192) );
CMPR32X2TS U2306 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MY[12]), .C(n2429),
.CO(n2425), .S(n2536) );
CMPR32X2TS U2307 ( .A(n3188), .B(n3187), .C(n3186), .CO(n3190), .S(n3189) );
ADDHXLTS U2308 ( .A(n3110), .B(n3109), .CO(mult_x_69_n474), .S(n3113) );
CMPR32X2TS U2309 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[11]), .C(n2433),
.CO(n2429), .S(n2671) );
CMPR32X2TS U2310 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[10]), .C(n2437),
.CO(n2433), .S(n2674) );
CMPR32X2TS U2311 ( .A(n3180), .B(n3179), .C(n3178), .CO(n3182), .S(n3181) );
CMPR32X2TS U2312 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[9]), .C(n2441), .CO(
n2437), .S(n2677) );
CMPR32X2TS U2313 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[8]), .C(n2478), .CO(
n2441), .S(n2681) );
CMPR32X2TS U2314 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[7]), .C(n2485), .CO(
n2478), .S(n2541) );
CMPR32X2TS U2315 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MY[6]), .C(n2492), .CO(
n2485), .S(n2545) );
OAI21XLTS U2316 ( .A0(n2273), .A1(n2260), .B0(n2546), .Y(n2547) );
OAI21XLTS U2317 ( .A0(n2933), .A1(n2932), .B0(n3085), .Y(n2931) );
OAI21XLTS U2318 ( .A0(n2949), .A1(n2948), .B0(n3085), .Y(n2947) );
OAI21XLTS U2319 ( .A0(n3057), .A1(n3056), .B0(n3085), .Y(n3055) );
OAI21XLTS U2320 ( .A0(n2883), .A1(n2882), .B0(n3038), .Y(n2881) );
OAI21XLTS U2321 ( .A0(n2841), .A1(n2840), .B0(n3027), .Y(n2839) );
OAI21XLTS U2322 ( .A0(n3000), .A1(n2999), .B0(n3085), .Y(n2998) );
OAI21XLTS U2323 ( .A0(n3006), .A1(n3005), .B0(n3085), .Y(n3004) );
OAI21XLTS U2324 ( .A0(n2224), .A1(n3082), .B0(n2262), .Y(n2686) );
OR2X1TS U2325 ( .A(n3542), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n3534) );
OAI21XLTS U2326 ( .A0(n2751), .A1(n2750), .B0(n2720), .Y(n2749) );
OAI21XLTS U2327 ( .A0(n2823), .A1(n2822), .B0(n2357), .Y(n2821) );
OAI21XLTS U2328 ( .A0(n2892), .A1(n2891), .B0(n2322), .Y(n2890) );
OAI21XLTS U2329 ( .A0(n2908), .A1(n2907), .B0(n3027), .Y(n2906) );
OAI21XLTS U2330 ( .A0(n2302), .A1(n2325), .B0(n3024), .Y(n2695) );
OAI21XLTS U2331 ( .A0(n2311), .A1(n3036), .B0(n2353), .Y(n2354) );
OAI21XLTS U2332 ( .A0(n3010), .A1(n3009), .B0(n3085), .Y(n3008) );
OAI21XLTS U2333 ( .A0(n2311), .A1(n3065), .B0(n2345), .Y(n2346) );
OAI21XLTS U2334 ( .A0(n3018), .A1(n3017), .B0(n3088), .Y(n3016) );
OAI21XLTS U2335 ( .A0(n2275), .A1(n2325), .B0(n3082), .Y(n2685) );
OAI21XLTS U2336 ( .A0(n2408), .A1(n2407), .B0(n2317), .Y(n2406) );
OAI21XLTS U2337 ( .A0(n2400), .A1(n2399), .B0(n2507), .Y(n2398) );
OAI21XLTS U2338 ( .A0(n2510), .A1(n2509), .B0(n2507), .Y(n2508) );
ADDHXLTS U2339 ( .A(n2460), .B(n2459), .CO(n3109), .S(n2484) );
OAI21XLTS U2340 ( .A0(n2404), .A1(n2403), .B0(n2507), .Y(n2402) );
OAI21XLTS U2341 ( .A0(n2392), .A1(n2391), .B0(n2855), .Y(n2390) );
OR2X1TS U2342 ( .A(n3793), .B(n3800), .Y(n2222) );
CMPR42X1TS U2343 ( .A(mult_x_69_n743), .B(mult_x_69_n447), .C(mult_x_69_n450), .D(mult_x_69_n767), .ICI(mult_x_69_n451), .S(mult_x_69_n445), .ICO(
mult_x_69_n443), .CO(mult_x_69_n444) );
AO22X2TS U2344 ( .A0(n3852), .A1(FPMULT_P_Sgf[47]), .B0(n4219), .B1(n2523),
.Y(n1552) );
AO22X1TS U2345 ( .A0(n4170), .A1(FPMULT_P_Sgf[43]), .B0(n4219), .B1(n3126),
.Y(n1596) );
AO22XLTS U2346 ( .A0(n4220), .A1(FPMULT_P_Sgf[23]), .B0(n4200), .B1(n4193),
.Y(n1576) );
OAI211XLTS U2347 ( .A0(n3706), .A1(n3794), .B0(n3705), .C0(n3704), .Y(n1795)
);
OAI211XLTS U2348 ( .A0(n3720), .A1(n3794), .B0(n3697), .C0(n3696), .Y(n1797)
);
OAI211XLTS U2349 ( .A0(n3706), .A1(n3796), .B0(n3702), .C0(n3701), .Y(n1796)
);
OAI211XLTS U2350 ( .A0(n3715), .A1(n3796), .B0(n3714), .C0(n3713), .Y(n1794)
);
OAI211XLTS U2351 ( .A0(n3753), .A1(n3796), .B0(n3736), .C0(n3735), .Y(n1810)
);
OAI211XLTS U2352 ( .A0(n3720), .A1(n3796), .B0(n3719), .C0(n3718), .Y(n1798)
);
OAI211XLTS U2353 ( .A0(n3725), .A1(n3794), .B0(n3700), .C0(n3699), .Y(n1799)
);
OAI211XLTS U2354 ( .A0(n3777), .A1(n3794), .B0(n3755), .C0(n3754), .Y(n1807)
);
OAI211XLTS U2355 ( .A0(n3773), .A1(n3796), .B0(n3767), .C0(n3766), .Y(n1802)
);
OAI211XLTS U2356 ( .A0(n3786), .A1(n3794), .B0(n3785), .C0(n3784), .Y(n1805)
);
OAI211XLTS U2357 ( .A0(n3693), .A1(n3796), .B0(n3692), .C0(n3691), .Y(n1792)
);
OAI211XLTS U2358 ( .A0(n3797), .A1(n3794), .B0(n3791), .C0(n3790), .Y(n1811)
);
OAI211XLTS U2359 ( .A0(n3773), .A1(n3794), .B0(n3772), .C0(n3771), .Y(n1801)
);
OAI211XLTS U2360 ( .A0(n3786), .A1(n3796), .B0(n3780), .C0(n3779), .Y(n1806)
);
OAI211XLTS U2361 ( .A0(n3777), .A1(n3796), .B0(n3776), .C0(n3775), .Y(n1808)
);
OAI211XLTS U2362 ( .A0(n3725), .A1(n3796), .B0(n3724), .C0(n3723), .Y(n1800)
);
OAI211XLTS U2363 ( .A0(n3693), .A1(n3794), .B0(n3678), .C0(n3677), .Y(n1791)
);
OAI211XLTS U2364 ( .A0(n4047), .A1(n3796), .B0(n3680), .C0(n3679), .Y(n1790)
);
OAI21XLTS U2365 ( .A0(n4139), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
n4142), .Y(n4140) );
OAI211XLTS U2366 ( .A0(n3765), .A1(n3794), .B0(n3761), .C0(n3760), .Y(n1803)
);
OAI211XLTS U2367 ( .A0(n3715), .A1(n3794), .B0(n3709), .C0(n3708), .Y(n1793)
);
OAI211XLTS U2368 ( .A0(n3753), .A1(n3794), .B0(n3740), .C0(n3739), .Y(n1809)
);
OAI211XLTS U2369 ( .A0(n3765), .A1(n3796), .B0(n3764), .C0(n3763), .Y(n1804)
);
INVX3TS U2370 ( .A(n2221), .Y(n2282) );
INVX3TS U2371 ( .A(n2222), .Y(n2284) );
OAI21X1TS U2372 ( .A0(n2798), .A1(n2797), .B0(n2357), .Y(n2796) );
OAI21X1TS U2373 ( .A0(n2851), .A1(n2850), .B0(n3027), .Y(n2849) );
CLKBUFX2TS U2374 ( .A(n3541), .Y(n2287) );
OAI211XLTS U2375 ( .A0(n3751), .A1(n4792), .B0(n3594), .C0(n3593), .Y(n1918)
);
OAI211XLTS U2376 ( .A0(n3748), .A1(n4836), .B0(n3609), .C0(n3608), .Y(n1926)
);
OAI211XLTS U2377 ( .A0(n3748), .A1(n4841), .B0(n3611), .C0(n3610), .Y(n1921)
);
OAI211XLTS U2378 ( .A0(n3751), .A1(n4848), .B0(n3688), .C0(n3687), .Y(n1843)
);
OAI211XLTS U2379 ( .A0(n3748), .A1(n4833), .B0(n3613), .C0(n3612), .Y(n1929)
);
OAI211XLTS U2380 ( .A0(n3748), .A1(n4838), .B0(n3603), .C0(n3602), .Y(n1924)
);
OAI211XLTS U2381 ( .A0(n3748), .A1(n4842), .B0(n3744), .C0(n3743), .Y(n1822)
);
OAI211XLTS U2382 ( .A0(n3670), .A1(n4823), .B0(n3664), .C0(n3663), .Y(n1939)
);
OAI211XLTS U2383 ( .A0(n3751), .A1(n4786), .B0(n3581), .C0(n3580), .Y(n1913)
);
OAI211XLTS U2384 ( .A0(n3670), .A1(n4822), .B0(n3646), .C0(n3645), .Y(n1940)
);
OAI211XLTS U2385 ( .A0(n3751), .A1(n4791), .B0(n3591), .C0(n3590), .Y(n1919)
);
OAI211XLTS U2386 ( .A0(n3748), .A1(n4857), .B0(n3731), .C0(n3730), .Y(n1820)
);
OAI211XLTS U2387 ( .A0(n3748), .A1(n4839), .B0(n3596), .C0(n3595), .Y(n1923)
);
OAI211XLTS U2388 ( .A0(n3670), .A1(n4821), .B0(n3650), .C0(n3649), .Y(n1941)
);
OAI211XLTS U2389 ( .A0(n3670), .A1(n4825), .B0(n3660), .C0(n3659), .Y(n1937)
);
OAI211XLTS U2390 ( .A0(n3751), .A1(n4793), .B0(n3583), .C0(n3582), .Y(n1917)
);
OAI211XLTS U2391 ( .A0(n3748), .A1(n4854), .B0(n3727), .C0(n3726), .Y(n1833)
);
OAI211XLTS U2392 ( .A0(n3748), .A1(n4855), .B0(n3729), .C0(n3728), .Y(n1824)
);
OAI211XLTS U2393 ( .A0(n3748), .A1(n4832), .B0(n3601), .C0(n3600), .Y(n1930)
);
OAI211XLTS U2394 ( .A0(n3670), .A1(n4829), .B0(n3658), .C0(n3657), .Y(n1933)
);
OAI211XLTS U2395 ( .A0(n3748), .A1(n4835), .B0(n3615), .C0(n3614), .Y(n1927)
);
OAI211XLTS U2396 ( .A0(n3751), .A1(n4784), .B0(n3589), .C0(n3588), .Y(n1916)
);
OAI211XLTS U2397 ( .A0(n3748), .A1(n4856), .B0(n3747), .C0(n3746), .Y(n1821)
);
OAI211XLTS U2398 ( .A0(n3748), .A1(n4837), .B0(n3605), .C0(n3604), .Y(n1925)
);
OAI211XLTS U2399 ( .A0(n3670), .A1(n4819), .B0(n3654), .C0(n3653), .Y(n1943)
);
OAI211XLTS U2400 ( .A0(n3670), .A1(n4852), .B0(n3669), .C0(n3668), .Y(n1836)
);
OAI211XLTS U2401 ( .A0(n3748), .A1(n4853), .B0(n3682), .C0(n3681), .Y(n1835)
);
OAI211XLTS U2402 ( .A0(n3748), .A1(n4645), .B0(n3617), .C0(n3616), .Y(n1920)
);
OAI211XLTS U2403 ( .A0(n3748), .A1(n4851), .B0(n3742), .C0(n3741), .Y(n1837)
);
OAI211XLTS U2404 ( .A0(n3751), .A1(n4849), .B0(n3684), .C0(n3683), .Y(n1841)
);
OAI211XLTS U2405 ( .A0(n3751), .A1(n4850), .B0(n3686), .C0(n3685), .Y(n1839)
);
OAI211XLTS U2406 ( .A0(n3670), .A1(n4830), .B0(n3642), .C0(n3641), .Y(n1932)
);
OAI211XLTS U2407 ( .A0(n3751), .A1(n4783), .B0(n3587), .C0(n3586), .Y(n1914)
);
OAI211XLTS U2408 ( .A0(n3751), .A1(n4846), .B0(n3577), .C0(n3576), .Y(n1845)
);
OAI211XLTS U2409 ( .A0(n3751), .A1(n4847), .B0(n3750), .C0(n3749), .Y(n1844)
);
OAI211XLTS U2410 ( .A0(n3670), .A1(n4827), .B0(n3652), .C0(n3651), .Y(n1935)
);
OAI211XLTS U2411 ( .A0(n3670), .A1(n4826), .B0(n3667), .C0(n3666), .Y(n1936)
);
OAI211XLTS U2412 ( .A0(n3670), .A1(n4820), .B0(n3644), .C0(n3643), .Y(n1942)
);
OAI211XLTS U2413 ( .A0(n3670), .A1(n4824), .B0(n3662), .C0(n3661), .Y(n1938)
);
OAI211XLTS U2414 ( .A0(n3748), .A1(n4840), .B0(n3607), .C0(n3606), .Y(n1922)
);
OAI211XLTS U2415 ( .A0(n3748), .A1(n4858), .B0(n3733), .C0(n3732), .Y(n1819)
);
OAI211XLTS U2416 ( .A0(n3751), .A1(n2239), .B0(n3585), .C0(n3584), .Y(n1915)
);
OAI211XLTS U2417 ( .A0(n3748), .A1(n4834), .B0(n3598), .C0(n3597), .Y(n1928)
);
OAI211XLTS U2418 ( .A0(n3748), .A1(n4831), .B0(n3656), .C0(n3655), .Y(n1931)
);
OAI211XLTS U2419 ( .A0(n3670), .A1(n4828), .B0(n3648), .C0(n3647), .Y(n1934)
);
OAI21X1TS U2420 ( .A0(n2977), .A1(n2976), .B0(n3085), .Y(n2975) );
AO21XLTS U2421 ( .A0(n4606), .A1(n4638), .B0(n3554), .Y(n3555) );
NAND2BXLTS U2422 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(n3297), .Y(n3298)
);
OAI21X1TS U2423 ( .A0(n2937), .A1(n2936), .B0(n3085), .Y(n2935) );
BUFX4TS U2424 ( .A(n3458), .Y(n3502) );
NAND3XLTS U2425 ( .A(n3624), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n4624),
.Y(n3625) );
OAI21X1TS U2426 ( .A0(n2327), .A1(n2204), .B0(n2558), .Y(n2559) );
OAI21X1TS U2427 ( .A0(n2327), .A1(n2203), .B0(n2561), .Y(n2562) );
OAI21X1TS U2428 ( .A0(n2327), .A1(n3118), .B0(n2555), .Y(n2556) );
NOR2X1TS U2429 ( .A(n3802), .B(n3568), .Y(n3573) );
NOR2X6TS U2430 ( .A(FPMULT_Op_MX[22]), .B(n2553), .Y(n2531) );
INVX4TS U2431 ( .A(FPMULT_Op_MY[14]), .Y(n3047) );
INVX4TS U2432 ( .A(FPMULT_Op_MY[13]), .Y(mult_x_69_n220) );
INVX4TS U2433 ( .A(FPMULT_Op_MY[2]), .Y(n3118) );
INVX3TS U2434 ( .A(FPMULT_Op_MY[11]), .Y(n3074) );
INVX4TS U2435 ( .A(FPMULT_Op_MY[10]), .Y(n3071) );
INVX4TS U2436 ( .A(FPMULT_Op_MY[5]), .Y(n2945) );
CLKBUFX2TS U2437 ( .A(FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n2240) );
INVX3TS U2438 ( .A(FPMULT_Op_MY[8]), .Y(n3053) );
INVX4TS U2439 ( .A(FPMULT_Op_MY[7]), .Y(mult_x_69_n272) );
NOR2X8TS U2440 ( .A(operation[1]), .B(n3901), .Y(n3166) );
XOR2X2TS U2441 ( .A(n2522), .B(n2521), .Y(n2523) );
ADDFHX2TS U2442 ( .A(n3134), .B(n3133), .CI(n3132), .CO(n2522), .S(n3135) );
AO22X1TS U2443 ( .A0(n4170), .A1(FPMULT_P_Sgf[42]), .B0(n4219), .B1(n4145),
.Y(n1595) );
AO22X1TS U2444 ( .A0(n4170), .A1(FPMULT_P_Sgf[41]), .B0(n4219), .B1(n4148),
.Y(n1594) );
AO22X1TS U2445 ( .A0(n4170), .A1(FPMULT_P_Sgf[40]), .B0(n4219), .B1(n4150),
.Y(n1593) );
AO22X1TS U2446 ( .A0(n4170), .A1(FPMULT_P_Sgf[39]), .B0(n4219), .B1(n4152),
.Y(n1592) );
AO22X1TS U2447 ( .A0(n4170), .A1(FPMULT_P_Sgf[38]), .B0(n4219), .B1(n4155),
.Y(n1591) );
AO22X1TS U2448 ( .A0(n4170), .A1(FPMULT_P_Sgf[37]), .B0(n4187), .B1(n4157),
.Y(n1590) );
AO22X1TS U2449 ( .A0(n4170), .A1(FPMULT_P_Sgf[36]), .B0(n4219), .B1(n4159),
.Y(n1589) );
AO22X1TS U2450 ( .A0(n4170), .A1(FPMULT_P_Sgf[35]), .B0(n4187), .B1(n4162),
.Y(n1588) );
AO22X1TS U2451 ( .A0(n4170), .A1(FPMULT_P_Sgf[34]), .B0(n4187), .B1(n4164),
.Y(n1587) );
AO22X1TS U2452 ( .A0(n4170), .A1(FPMULT_P_Sgf[33]), .B0(n4219), .B1(n4166),
.Y(n1586) );
AO22X1TS U2453 ( .A0(n4170), .A1(FPMULT_P_Sgf[32]), .B0(n4200), .B1(n4169),
.Y(n1585) );
AO22X1TS U2454 ( .A0(n4220), .A1(FPMULT_P_Sgf[31]), .B0(n4187), .B1(n4172),
.Y(n1584) );
AO22X1TS U2455 ( .A0(n4220), .A1(FPMULT_P_Sgf[30]), .B0(n4187), .B1(n4174),
.Y(n1583) );
ADDFHX2TS U2456 ( .A(mult_x_69_n284), .B(mult_x_69_n275), .CI(n4173), .CO(
n4171), .S(n4174) );
AO22X1TS U2457 ( .A0(n4220), .A1(FPMULT_P_Sgf[29]), .B0(n4200), .B1(n4177),
.Y(n1582) );
AO22X1TS U2458 ( .A0(n4220), .A1(FPMULT_P_Sgf[28]), .B0(n4200), .B1(n4179),
.Y(n1581) );
ADDFHX2TS U2459 ( .A(mult_x_69_n306), .B(mult_x_69_n296), .CI(n4178), .CO(
n4175), .S(n4179) );
AO22X1TS U2460 ( .A0(n4220), .A1(FPMULT_P_Sgf[27]), .B0(n4200), .B1(n4181),
.Y(n1580) );
AO22X1TS U2461 ( .A0(n4220), .A1(FPMULT_P_Sgf[26]), .B0(n4200), .B1(n4184),
.Y(n1579) );
ADDFHX2TS U2462 ( .A(mult_x_69_n317), .B(mult_x_69_n307), .CI(n4180), .CO(
n4178), .S(n4181) );
AO22X1TS U2463 ( .A0(n4220), .A1(FPMULT_P_Sgf[25]), .B0(n4187), .B1(n4186),
.Y(n1578) );
AO22X1TS U2464 ( .A0(n4220), .A1(FPMULT_P_Sgf[24]), .B0(n4200), .B1(n4190),
.Y(n1577) );
ADDFHX2TS U2465 ( .A(mult_x_69_n329), .B(mult_x_69_n339), .CI(n4185), .CO(
n4182), .S(n4186) );
ADDFHX2TS U2466 ( .A(n4189), .B(mult_x_69_n340), .CI(n4188), .CO(n4185), .S(
n4190) );
ADDFHX2TS U2467 ( .A(n4202), .B(mult_x_69_n384), .CI(n4201), .CO(n4197), .S(
n4203) );
ADDFHX2TS U2468 ( .A(n4205), .B(mult_x_69_n394), .CI(n4204), .CO(n4201), .S(
n4206) );
ADDFHX2TS U2469 ( .A(n4208), .B(mult_x_69_n404), .CI(n4207), .CO(n4204), .S(
n4209) );
OAI21X1TS U2470 ( .A0(n3023), .A1(n3022), .B0(n3088), .Y(n3021) );
OAI21X1TS U2471 ( .A0(n2844), .A1(n2843), .B0(n2365), .Y(n2842) );
OAI21X1TS U2472 ( .A0(n2980), .A1(n2979), .B0(n3041), .Y(n2978) );
OAI21X1TS U2473 ( .A0(n2926), .A1(n2925), .B0(n3027), .Y(n2924) );
OAI21X1TS U2474 ( .A0(n2755), .A1(n2754), .B0(n2373), .Y(n2753) );
ADDFHX2TS U2475 ( .A(n4211), .B(mult_x_69_n414), .CI(n4210), .CO(n4207), .S(
n4212) );
OAI21X1TS U2476 ( .A0(n3003), .A1(n3002), .B0(n3069), .Y(n3001) );
OAI21X1TS U2477 ( .A0(n2762), .A1(n2761), .B0(n2707), .Y(n2760) );
OAI21X1TS U2478 ( .A0(n2396), .A1(n2395), .B0(n2507), .Y(n2394) );
OAI21X1TS U2479 ( .A0(n2838), .A1(n2837), .B0(n2365), .Y(n2836) );
OAI21X1TS U2480 ( .A0(n2303), .A1(n2325), .B0(n3116), .Y(n2699) );
OAI21X1TS U2481 ( .A0(n2304), .A1(n2325), .B0(n2752), .Y(n2703) );
OAI21X1TS U2482 ( .A0(n2277), .A1(n2325), .B0(n3036), .Y(n2692) );
OAI21X1TS U2483 ( .A0(n2301), .A1(n2325), .B0(n3065), .Y(n2688) );
ADDFHX2TS U2484 ( .A(n4214), .B(mult_x_69_n422), .CI(n4213), .CO(n4210), .S(
n4215) );
OAI21X1TS U2485 ( .A0(n2997), .A1(n2996), .B0(n3069), .Y(n2995) );
OAI21X1TS U2486 ( .A0(n2972), .A1(n2971), .B0(n3041), .Y(n2970) );
OAI21X1TS U2487 ( .A0(n3014), .A1(n3013), .B0(n3088), .Y(n3012) );
OAI21X1TS U2488 ( .A0(n2899), .A1(n2898), .B0(n2322), .Y(n2897) );
NAND3X1TS U2489 ( .A(n4047), .B(n4046), .C(n4045), .Y(n1789) );
OAI21X1TS U2490 ( .A0(n2820), .A1(n2819), .B0(n2365), .Y(n2818) );
OAI21X1TS U2491 ( .A0(n2968), .A1(n2967), .B0(n3041), .Y(n2966) );
OAI21X1TS U2492 ( .A0(n2758), .A1(n2757), .B0(n2720), .Y(n2756) );
ADDFHX2TS U2493 ( .A(n4217), .B(mult_x_69_n430), .CI(n4216), .CO(n4213), .S(
n4218) );
OAI21X1TS U2494 ( .A0(n2805), .A1(n2804), .B0(n2365), .Y(n2803) );
OAI21X1TS U2495 ( .A0(n2955), .A1(n2954), .B0(n3041), .Y(n2953) );
INVX3TS U2496 ( .A(n2222), .Y(n2283) );
OAI21X1TS U2497 ( .A0(n2889), .A1(n2888), .B0(n2322), .Y(n2887) );
OAI21X1TS U2498 ( .A0(n3089), .A1(n3087), .B0(n3085), .Y(n3086) );
INVX3TS U2499 ( .A(n3671), .Y(n3794) );
OAI21X1TS U2500 ( .A0(n3042), .A1(n3040), .B0(n3038), .Y(n3039) );
INVX3TS U2501 ( .A(n2221), .Y(n2281) );
OR2X2TS U2502 ( .A(n3673), .B(n3800), .Y(n2221) );
OAI21X1TS U2503 ( .A0(n3028), .A1(n3026), .B0(n2322), .Y(n3025) );
OAI21X1TS U2504 ( .A0(n3081), .A1(n3080), .B0(n3085), .Y(n3079) );
OAI21X1TS U2505 ( .A0(n2814), .A1(n2813), .B0(n2357), .Y(n2812) );
OAI21X1TS U2506 ( .A0(n3031), .A1(n3030), .B0(n3038), .Y(n3029) );
ADDFX1TS U2507 ( .A(mult_x_69_n452), .B(n3204), .CI(n3203), .CO(n3206), .S(
n3205) );
INVX2TS U2508 ( .A(n2526), .Y(n3083) );
OAI21X1TS U2509 ( .A0(n2929), .A1(n2928), .B0(n3038), .Y(n2927) );
OAI21X1TS U2510 ( .A0(n2808), .A1(n2807), .B0(n2357), .Y(n2806) );
AO22X1TS U2511 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[1]), .A1(n4365), .B0(
n3756), .B1(n3854), .Y(n3672) );
OAI21X1TS U2512 ( .A0(n2923), .A1(n2922), .B0(n3038), .Y(n2921) );
ADDFHX1TS U2513 ( .A(mult_x_69_n469), .B(n3195), .CI(n3194), .CO(n3197), .S(
n3196) );
OAI21X1TS U2514 ( .A0(n2902), .A1(n2901), .B0(n3038), .Y(n2900) );
OAI21X1TS U2515 ( .A0(n2991), .A1(n2990), .B0(n3085), .Y(n2989) );
CLKINVX3TS U2516 ( .A(n4264), .Y(n2286) );
OAI21X1TS U2517 ( .A0(n2896), .A1(n2895), .B0(n3038), .Y(n2894) );
OAI21X1TS U2518 ( .A0(n2987), .A1(n2986), .B0(n3085), .Y(n2985) );
OAI21X1TS U2519 ( .A0(n3077), .A1(n3076), .B0(n3085), .Y(n3075) );
CLKAND2X2TS U2520 ( .A(n4263), .B(n4262), .Y(n4264) );
OAI21X1TS U2521 ( .A0(n2880), .A1(n2879), .B0(n3038), .Y(n2878) );
NAND3X1TS U2522 ( .A(n4009), .B(n4008), .C(n4007), .Y(n1829) );
NAND3X1TS U2523 ( .A(n4030), .B(n4029), .C(n4033), .Y(n1817) );
NAND3X1TS U2524 ( .A(n4005), .B(n4004), .C(n4020), .Y(n1830) );
NAND3X1TS U2525 ( .A(n4025), .B(n4024), .C(n4023), .Y(n1823) );
NAND3X1TS U2526 ( .A(n4022), .B(n4021), .C(n4020), .Y(n1825) );
NAND3X1TS U2527 ( .A(n4028), .B(n4027), .C(n4033), .Y(n1818) );
NAND3X1TS U2528 ( .A(n3993), .B(n3992), .C(n4001), .Y(n1840) );
ADDFX1TS U2529 ( .A(n3184), .B(n3183), .CI(n3182), .CO(n3186), .S(n3185) );
NAND3X1TS U2530 ( .A(n4015), .B(n4014), .C(n4013), .Y(n1827) );
NAND3X1TS U2531 ( .A(n4000), .B(n3999), .C(n4013), .Y(n1832) );
OAI21X1TS U2532 ( .A0(n3061), .A1(n3060), .B0(n3085), .Y(n3059) );
NAND3X1TS U2533 ( .A(n3989), .B(n3988), .C(n4007), .Y(n1842) );
NAND3X1TS U2534 ( .A(n4019), .B(n4018), .C(n4023), .Y(n1826) );
NAND3X1TS U2535 ( .A(n4011), .B(n4010), .C(n4020), .Y(n1828) );
NAND3X1TS U2536 ( .A(n3998), .B(n3997), .C(n3996), .Y(n1834) );
NAND3X1TS U2537 ( .A(n4003), .B(n4002), .C(n4001), .Y(n1831) );
NAND3X1TS U2538 ( .A(n4035), .B(n4034), .C(n4033), .Y(n1816) );
NAND3X1TS U2539 ( .A(n3995), .B(n3994), .C(n3996), .Y(n1838) );
NOR2XLTS U2540 ( .A(n3834), .B(n3302), .Y(n3304) );
OAI21X1TS U2541 ( .A0(n2965), .A1(n2964), .B0(n3085), .Y(n2963) );
NOR2XLTS U2542 ( .A(n3298), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n3299) );
NAND3X1TS U2543 ( .A(n3558), .B(n4624), .C(n4605), .Y(n3554) );
NOR2XLTS U2544 ( .A(n3296), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n3297) );
AND2X4TS U2545 ( .A(n4870), .B(n4362), .Y(n3448) );
OAI21X1TS U2546 ( .A0(n2311), .A1(n2273), .B0(n2643), .Y(n2644) );
BUFX6TS U2547 ( .A(n3990), .Y(n2199) );
OR2X1TS U2548 ( .A(n3512), .B(n3457), .Y(n3491) );
OAI21X1TS U2549 ( .A0(n3020), .A1(n3024), .B0(n2362), .Y(n2363) );
OAI21X1TS U2550 ( .A0(n2224), .A1(n3024), .B0(n2268), .Y(n2696) );
OAI21X1TS U2551 ( .A0(n2224), .A1(n3065), .B0(n2264), .Y(n2689) );
OAI21X1TS U2552 ( .A0(n2311), .A1(n3082), .B0(n2338), .Y(n2339) );
OAI21X1TS U2553 ( .A0(n3020), .A1(n3116), .B0(n2370), .Y(n2371) );
BUFX3TS U2554 ( .A(n3291), .Y(n2296) );
OAI21X1TS U2555 ( .A0(n2224), .A1(n3036), .B0(n2266), .Y(n2693) );
CLKBUFX2TS U2556 ( .A(n2680), .Y(n2280) );
OAI21X1TS U2557 ( .A0(n2224), .A1(n3116), .B0(n2256), .Y(n2700) );
CLKINVX3TS U2558 ( .A(n3564), .Y(n3756) );
NAND3X1TS U2559 ( .A(n2361), .B(n2636), .C(n2359), .Y(n2627) );
NAND3X1TS U2560 ( .A(n2337), .B(n2576), .C(n2335), .Y(n2568) );
NAND3X1TS U2561 ( .A(n2344), .B(n2597), .C(n2342), .Y(n2589) );
OAI21XLTS U2562 ( .A0(n2225), .A1(n3530), .B0(FPMULT_FS_Module_state_reg[3]),
.Y(n3531) );
NAND3X1TS U2563 ( .A(n2352), .B(n2613), .C(n2350), .Y(n2605) );
ADDFX1TS U2564 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[5]), .CI(n2455), .CO(
n2492), .S(n2549) );
NOR2BX4TS U2565 ( .AN(n2553), .B(n2328), .Y(n2540) );
NOR2X1TS U2566 ( .A(n2224), .B(n2273), .Y(n2329) );
BUFX4TS U2567 ( .A(n2745), .Y(n2752) );
NOR2X8TS U2568 ( .A(rst), .B(n3921), .Y(n3213) );
OR4X4TS U2569 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .C(underflow_flag_mult), .D(n4224), .Y(
n2314) );
NOR2XLTS U2570 ( .A(FPMULT_FSM_selector_C), .B(n3241), .Y(n3240) );
OAI211XLTS U2571 ( .A0(n3322), .A1(n3378), .B0(n3321), .C0(n3320), .Y(n3327)
);
NAND2X4TS U2572 ( .A(n2361), .B(n2360), .Y(n2358) );
AOI32X2TS U2573 ( .A0(n3910), .A1(n3167), .A2(begin_operation), .B0(n4939),
.B1(n3167), .Y(n3530) );
NAND3XLTS U2574 ( .A(FPSENCOS_cont_iter_out[1]), .B(n4871), .C(n3226), .Y(
n3896) );
NAND2X4TS U2575 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(n4249), .Y(n4546) );
NAND2X4TS U2576 ( .A(n2369), .B(n2368), .Y(n2366) );
ADDFX1TS U2577 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[4]), .CI(n2461), .CO(
n2455), .S(n2554) );
BUFX4TS U2578 ( .A(n4062), .Y(n2200) );
OR2X4TS U2579 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n3759), .Y(n3564) );
NAND2X4TS U2580 ( .A(n2344), .B(n2343), .Y(n2341) );
OAI21XLTS U2581 ( .A0(n3832), .A1(n4719), .B0(n3828), .Y(op_result[16]) );
OAI21XLTS U2582 ( .A0(n3832), .A1(n4715), .B0(n3818), .Y(op_result[17]) );
OAI21XLTS U2583 ( .A0(n3832), .A1(n4711), .B0(n3815), .Y(op_result[18]) );
NAND2BX4TS U2584 ( .AN(n3236), .B(n2324), .Y(n4200) );
INVX3TS U2585 ( .A(n4323), .Y(n4255) );
BUFX4TS U2586 ( .A(n2327), .Y(n2273) );
CLKINVX6TS U2587 ( .A(n3758), .Y(n3618) );
NAND2X4TS U2588 ( .A(n2196), .B(n4557), .Y(n4260) );
BUFX4TS U2589 ( .A(n2507), .Y(n2855) );
CLKINVX3TS U2590 ( .A(n2240), .Y(n4249) );
ADDFX1TS U2591 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[3]), .CI(n2465), .CO(
n2461), .S(n2557) );
ADDFX1TS U2592 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[2]), .CI(n2445), .CO(
n2465), .S(n2560) );
BUFX4TS U2593 ( .A(n2524), .Y(n3066) );
OA21X2TS U2594 ( .A0(n3238), .A1(n3237), .B0(FPMULT_FS_Module_state_reg[1]),
.Y(n3239) );
NAND2X4TS U2595 ( .A(n4591), .B(n2196), .Y(n4288) );
BUFX4TS U2596 ( .A(n2219), .Y(n2251) );
NOR2XLTS U2597 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n3635) );
AND3X1TS U2598 ( .A(n2201), .B(n2202), .C(FPMULT_Op_MX[2]), .Y(n2381) );
OR3X4TS U2599 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n4776), .Y(n3955) );
BUFX4TS U2600 ( .A(n2217), .Y(n2253) );
ADDHX2TS U2601 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[0]), .CO(n2445), .S(
n2633) );
BUFX4TS U2602 ( .A(n2223), .Y(n2252) );
BUFX4TS U2603 ( .A(n2218), .Y(n2254) );
BUFX4TS U2604 ( .A(n2206), .Y(n2257) );
BUFX4TS U2605 ( .A(n2205), .Y(n2260) );
NAND2BXLTS U2606 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n3319) );
INVX4TS U2607 ( .A(FPMULT_Op_MX[8]), .Y(n2357) );
BUFX4TS U2608 ( .A(n2208), .Y(n2272) );
BUFX4TS U2609 ( .A(n2317), .Y(n2507) );
INVX4TS U2610 ( .A(n3911), .Y(n3801) );
INVX6TS U2611 ( .A(rst), .Y(n3149) );
ADDFHX2TS U2612 ( .A(mult_x_69_n285), .B(n4176), .CI(n4175), .CO(n4173), .S(
n4177) );
ADDFHX2TS U2613 ( .A(mult_x_69_n256), .B(n4168), .CI(n4167), .CO(n4165), .S(
n4169) );
ADDFHX2TS U2614 ( .A(mult_x_69_n318), .B(n4183), .CI(n4182), .CO(n4180), .S(
n4184) );
OAI21XLTS U2615 ( .A0(n2616), .A1(n2615), .B0(n2799), .Y(n2614) );
OAI21XLTS U2616 ( .A0(n2723), .A1(n2722), .B0(n2720), .Y(n2721) );
INVX2TS U2617 ( .A(n2664), .Y(n3043) );
OAI21XLTS U2618 ( .A0(n2777), .A1(n2776), .B0(n2357), .Y(n2775) );
OAI21XLTS U2619 ( .A0(n2424), .A1(n2423), .B0(n2507), .Y(n2422) );
OAI21XLTS U2620 ( .A0(n2608), .A1(n2607), .B0(n3041), .Y(n2606) );
OAI21XLTS U2621 ( .A0(n2579), .A1(n2578), .B0(n3066), .Y(n2577) );
OAI21XLTS U2622 ( .A0(n2621), .A1(n2620), .B0(n2799), .Y(n2619) );
OAI21XLTS U2623 ( .A0(n2865), .A1(n2864), .B0(n3038), .Y(n2863) );
OAI21XLTS U2624 ( .A0(n2871), .A1(n2870), .B0(n3038), .Y(n2869) );
CLKBUFX2TS U2625 ( .A(n2627), .Y(n2845) );
OAI21XLTS U2626 ( .A0(n2771), .A1(n2770), .B0(n2357), .Y(n2769) );
INVX2TS U2627 ( .A(n2667), .Y(n2988) );
INVX2TS U2628 ( .A(n2554), .Y(n2938) );
INVX2TS U2629 ( .A(n2541), .Y(n2946) );
OAI21XLTS U2630 ( .A0(n2444), .A1(n2443), .B0(n2507), .Y(n2442) );
OAI21XLTS U2631 ( .A0(n2420), .A1(n2419), .B0(n2507), .Y(n2418) );
OAI21XLTS U2632 ( .A0(n2829), .A1(n2828), .B0(n2322), .Y(n2827) );
OAI21XLTS U2633 ( .A0(n2848), .A1(n2847), .B0(n3027), .Y(n2846) );
OAI21XLTS U2634 ( .A0(n2920), .A1(n2919), .B0(n3066), .Y(n2918) );
INVX2TS U2635 ( .A(n2368), .Y(n2454) );
OAI21XLTS U2636 ( .A0(n2719), .A1(n2718), .B0(n2707), .Y(n2717) );
INVX2TS U2637 ( .A(n2661), .Y(n3048) );
OAI21XLTS U2638 ( .A0(n2811), .A1(n2810), .B0(n2322), .Y(n2809) );
INVX2TS U2639 ( .A(n2681), .Y(n2962) );
INVX2TS U2640 ( .A(n2671), .Y(n3058) );
OAI21XLTS U2641 ( .A0(n2768), .A1(n2767), .B0(n2365), .Y(n2766) );
OAI31X1TS U2642 ( .A0(n2630), .A1(n2322), .A2(n2629), .B0(n2628), .Y(n3091)
);
OAI21XLTS U2643 ( .A0(n2630), .A1(n2629), .B0(n3027), .Y(n2628) );
OAI21XLTS U2644 ( .A0(n2735), .A1(n2734), .B0(n2707), .Y(n2733) );
OAI21XLTS U2645 ( .A0(n2748), .A1(n2747), .B0(n2720), .Y(n2746) );
OAI21XLTS U2646 ( .A0(n2877), .A1(n2876), .B0(n3038), .Y(n2875) );
OAI21XLTS U2647 ( .A0(n2789), .A1(n2788), .B0(n2357), .Y(n2787) );
OAI21XLTS U2648 ( .A0(n2795), .A1(n2794), .B0(n2357), .Y(n2793) );
INVX2TS U2649 ( .A(n2532), .Y(n2984) );
OAI21XLTS U2650 ( .A0(n2780), .A1(n2779), .B0(n2357), .Y(n2778) );
OAI21XLTS U2651 ( .A0(n2464), .A1(n2463), .B0(n2720), .Y(n2462) );
OAI21XLTS U2652 ( .A0(n2716), .A1(n2715), .B0(n2319), .Y(n2714) );
OAI21XLTS U2653 ( .A0(n2432), .A1(n2431), .B0(n2317), .Y(n2430) );
OAI21XLTS U2654 ( .A0(n2412), .A1(n2411), .B0(n2507), .Y(n2410) );
OAI31X1TS U2655 ( .A0(n2576), .A1(FPMULT_Op_MX[20]), .A2(n2203), .B0(n2575),
.Y(n2588) );
OAI21XLTS U2656 ( .A0(n2571), .A1(n2570), .B0(n3088), .Y(n2569) );
OAI21XLTS U2657 ( .A0(n2911), .A1(n2910), .B0(n3066), .Y(n2909) );
NOR2X1TS U2658 ( .A(n2553), .B(n2203), .Y(mult_x_69_n381) );
OAI21XLTS U2659 ( .A0(n2941), .A1(n2940), .B0(n2316), .Y(n2939) );
OAI21XLTS U2660 ( .A0(n2914), .A1(n2913), .B0(n3066), .Y(n2912) );
OAI21XLTS U2661 ( .A0(n2905), .A1(n2904), .B0(n3066), .Y(n2903) );
OAI21XLTS U2662 ( .A0(n3035), .A1(n3034), .B0(n3066), .Y(n3033) );
OAI21XLTS U2663 ( .A0(n2273), .A1(n2257), .B0(n2550), .Y(n2551) );
OAI21XLTS U2664 ( .A0(n2273), .A1(n2945), .B0(n2542), .Y(n2543) );
OAI31X1TS U2665 ( .A0(n2613), .A1(FPMULT_Op_MX[14]), .A2(n2203), .B0(n2612),
.Y(n2625) );
OAI21XLTS U2666 ( .A0(n2859), .A1(n2858), .B0(n3038), .Y(n2857) );
OAI21XLTS U2667 ( .A0(n2832), .A1(n2831), .B0(n2356), .Y(n2830) );
NAND2BXLTS U2668 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n3346) );
OAI21XLTS U2669 ( .A0(n2592), .A1(n2591), .B0(n3069), .Y(n2590) );
OAI21XLTS U2670 ( .A0(n2826), .A1(n2825), .B0(n2356), .Y(n2824) );
OAI21XLTS U2671 ( .A0(n2584), .A1(n2583), .B0(n3066), .Y(n2582) );
OAI21XLTS U2672 ( .A0(n2835), .A1(n2834), .B0(n2356), .Y(n2833) );
OAI21XLTS U2673 ( .A0(n2917), .A1(n2916), .B0(n3066), .Y(n2915) );
OAI21XLTS U2674 ( .A0(n2273), .A1(n2272), .B0(n2682), .Y(n2683) );
OAI21XLTS U2675 ( .A0(n2273), .A1(mult_x_69_n272), .B0(n2678), .Y(n2679) );
OAI21XLTS U2676 ( .A0(n3064), .A1(n3063), .B0(n3066), .Y(n3062) );
OAI21XLTS U2677 ( .A0(n3070), .A1(n3068), .B0(n3066), .Y(n3067) );
OAI21XLTS U2678 ( .A0(n2273), .A1(n2313), .B0(n2672), .Y(n2673) );
OAI21XLTS U2679 ( .A0(n2273), .A1(n3071), .B0(n2537), .Y(n2538) );
OAI21XLTS U2680 ( .A0(n2273), .A1(n3074), .B0(n2533), .Y(n2534) );
AOI2BB2X2TS U2681 ( .B0(FPMULT_Op_MX[21]), .B1(n3088), .A0N(n2316), .A1N(
FPMULT_Op_MX[21]), .Y(n2553) );
OAI21XLTS U2682 ( .A0(n3121), .A1(n3120), .B0(n4596), .Y(n3119) );
OAI31X1TS U2683 ( .A0(n2636), .A1(FPMULT_Op_MX[11]), .A2(n2203), .B0(n2635),
.Y(n3102) );
OAI21XLTS U2684 ( .A0(n2713), .A1(n2712), .B0(n2373), .Y(n2711) );
OAI21XLTS U2685 ( .A0(n2802), .A1(n2801), .B0(n2799), .Y(n2800) );
OAI21XLTS U2686 ( .A0(n2732), .A1(n2731), .B0(n2707), .Y(n2730) );
OAI21XLTS U2687 ( .A0(n2738), .A1(n2737), .B0(n2707), .Y(n2736) );
OAI21XLTS U2688 ( .A0(n2868), .A1(n2867), .B0(n3038), .Y(n2866) );
OAI21XLTS U2689 ( .A0(n2744), .A1(n2743), .B0(n2707), .Y(n2742) );
OAI21XLTS U2690 ( .A0(n2729), .A1(n2728), .B0(n2707), .Y(n2727) );
INVX2TS U2691 ( .A(n2545), .Y(n2930) );
OAI31X1TS U2692 ( .A0(n2454), .A1(FPMULT_Op_MX[8]), .A2(n2293), .B0(n2453),
.Y(n2469) );
OAI21XLTS U2693 ( .A0(n2765), .A1(n2764), .B0(n4596), .Y(n2763) );
OAI21XLTS U2694 ( .A0(n2741), .A1(n2740), .B0(n2707), .Y(n2739) );
OAI21XLTS U2695 ( .A0(n2886), .A1(n2885), .B0(n3038), .Y(n2884) );
AOI21X1TS U2696 ( .A0(n2325), .A1(n2705), .B0(n2704), .Y(n2706) );
OAI21XLTS U2697 ( .A0(n2224), .A1(n2752), .B0(n2259), .Y(n2704) );
OAI21XLTS U2698 ( .A0(n2952), .A1(n2951), .B0(n3066), .Y(n2950) );
OAI21XLTS U2699 ( .A0(n2961), .A1(n2960), .B0(n3066), .Y(n2959) );
OAI21XLTS U2700 ( .A0(n3046), .A1(n3045), .B0(n3066), .Y(n3044) );
OAI21XLTS U2701 ( .A0(n2983), .A1(n2982), .B0(n3066), .Y(n2981) );
OAI21XLTS U2702 ( .A0(n2273), .A1(n2271), .B0(n2669), .Y(n2670) );
OAI21XLTS U2703 ( .A0(n2273), .A1(mult_x_69_n220), .B0(n2665), .Y(n2666) );
OAI21XLTS U2704 ( .A0(n2273), .A1(n2315), .B0(n2659), .Y(n2660) );
OAI21XLTS U2705 ( .A0(n2273), .A1(n2253), .B0(n2527), .Y(n2528) );
OAI21XLTS U2706 ( .A0(n2273), .A1(n2251), .B0(n2656), .Y(n2657) );
CLKBUFX2TS U2707 ( .A(n2568), .Y(n3072) );
OAI21XLTS U2708 ( .A0(n2273), .A1(n2252), .B0(n2647), .Y(n2648) );
INVX2TS U2709 ( .A(n2677), .Y(n2973) );
INVX2TS U2710 ( .A(n2536), .Y(n3073) );
OAI21XLTS U2711 ( .A0(n2774), .A1(n2773), .B0(n2357), .Y(n2772) );
AO21XLTS U2712 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n4315), .B0(n4268),
.Y(n2236) );
NAND2BXLTS U2713 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n3320) );
INVX2TS U2714 ( .A(n2560), .Y(n2626) );
INVX2TS U2715 ( .A(n2557), .Y(n3117) );
OAI21XLTS U2716 ( .A0(n2472), .A1(n2471), .B0(n2707), .Y(n2470) );
INVX2TS U2717 ( .A(n2549), .Y(n2934) );
OAI21XLTS U2718 ( .A0(n2710), .A1(n2709), .B0(n2319), .Y(n2708) );
OAI21XLTS U2719 ( .A0(n2786), .A1(n2785), .B0(n2357), .Y(n2784) );
OAI21XLTS U2720 ( .A0(n2994), .A1(n2993), .B0(n3066), .Y(n2992) );
OAI21XLTS U2721 ( .A0(n2273), .A1(n2312), .B0(n2653), .Y(n2654) );
OAI21XLTS U2722 ( .A0(n2273), .A1(n2254), .B0(n2650), .Y(n2651) );
NAND2X1TS U2723 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3758) );
OAI21XLTS U2724 ( .A0(n2428), .A1(n2427), .B0(n2855), .Y(n2426) );
BUFX6TS U2725 ( .A(n3568), .Y(n4031) );
OAI31X1TS U2726 ( .A0(n2202), .A1(FPMULT_Op_MX[2]), .A2(n2203), .B0(n2518),
.Y(n3136) );
OAI21XLTS U2727 ( .A0(n2505), .A1(n2504), .B0(n2507), .Y(n2503) );
OAI21XLTS U2728 ( .A0(n2488), .A1(n2487), .B0(n2317), .Y(n2486) );
OAI21XLTS U2729 ( .A0(n2440), .A1(n2439), .B0(n2317), .Y(n2438) );
OAI21XLTS U2730 ( .A0(n3020), .A1(n2752), .B0(n2377), .Y(n2378) );
BUFX4TS U2731 ( .A(n4942), .Y(n4509) );
AO22XLTS U2732 ( .A0(n4064), .A1(Data_1[11]), .B0(n2269), .B1(
FPMULT_Op_MX[11]), .Y(n1670) );
AOI222X1TS U2733 ( .A0(n3512), .A1(cordic_result[25]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[25]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[25]), .Y(n3488) );
AOI222X1TS U2734 ( .A0(n3512), .A1(cordic_result[24]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[24]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[24]), .Y(n3490) );
AOI222X1TS U2735 ( .A0(n3512), .A1(cordic_result[23]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[23]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[23]), .Y(n3484) );
AO22XLTS U2736 ( .A0(n4220), .A1(FPMULT_P_Sgf[16]), .B0(n4219), .B1(n4215),
.Y(n1569) );
AO22XLTS U2737 ( .A0(n4220), .A1(FPMULT_P_Sgf[18]), .B0(n4219), .B1(n4209),
.Y(n1571) );
AO22XLTS U2738 ( .A0(n4220), .A1(FPMULT_P_Sgf[20]), .B0(n4219), .B1(n4203),
.Y(n1573) );
AOI222X1TS U2739 ( .A0(n3512), .A1(cordic_result[22]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[22]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[22]), .Y(n3486) );
AOI222X1TS U2740 ( .A0(n3510), .A1(cordic_result[15]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[15]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[15]), .Y(n3506) );
AOI222X1TS U2741 ( .A0(n3510), .A1(cordic_result[18]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[18]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[18]), .Y(n3511) );
AOI222X1TS U2742 ( .A0(n3512), .A1(cordic_result[21]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[21]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[21]), .Y(n3489) );
AOI222X1TS U2743 ( .A0(n3512), .A1(cordic_result[19]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[19]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[19]), .Y(n3485) );
AOI222X1TS U2744 ( .A0(n3512), .A1(cordic_result[20]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[20]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[20]), .Y(n3487) );
AOI222X1TS U2745 ( .A0(n3510), .A1(cordic_result[17]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[17]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[17]), .Y(n3505) );
AO22XLTS U2746 ( .A0(n4061), .A1(result_add_subt[30]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(n1731) );
AO22XLTS U2747 ( .A0(n4061), .A1(result_add_subt[23]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(n1786) );
AO22XLTS U2748 ( .A0(n4055), .A1(result_add_subt[30]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[30]), .Y(n1732) );
AO22XLTS U2749 ( .A0(n4049), .A1(result_add_subt[29]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[29]), .Y(n1769) );
AO22XLTS U2750 ( .A0(n4049), .A1(result_add_subt[25]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[25]), .Y(n1781) );
AO22XLTS U2751 ( .A0(n4049), .A1(result_add_subt[23]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[23]), .Y(n1787) );
AO22XLTS U2752 ( .A0(n4061), .A1(result_add_subt[29]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(n1768) );
AO22XLTS U2753 ( .A0(n4061), .A1(result_add_subt[27]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(n1774) );
AO22XLTS U2754 ( .A0(n4061), .A1(result_add_subt[26]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(n1777) );
AO22XLTS U2755 ( .A0(n4061), .A1(result_add_subt[25]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(n1780) );
AO22XLTS U2756 ( .A0(n4061), .A1(result_add_subt[24]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(n1783) );
AO22XLTS U2757 ( .A0(n3919), .A1(busy), .B0(n3917), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2147) );
MX2X1TS U2758 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n4062), .Y(n2226)
);
AO22XLTS U2759 ( .A0(n4143), .A1(n4100), .B0(n4141), .B1(
FPMULT_Add_result[4]), .Y(n1620) );
AO22XLTS U2760 ( .A0(n4143), .A1(n4104), .B0(n4141), .B1(
FPMULT_Add_result[6]), .Y(n1618) );
AO22XLTS U2761 ( .A0(n4143), .A1(n4108), .B0(n4138), .B1(
FPMULT_Add_result[8]), .Y(n1616) );
AO22XLTS U2762 ( .A0(n4143), .A1(n4112), .B0(n4138), .B1(
FPMULT_Add_result[10]), .Y(n1614) );
AO22XLTS U2763 ( .A0(n4143), .A1(n4116), .B0(n4120), .B1(
FPMULT_Add_result[12]), .Y(n1612) );
AO22XLTS U2764 ( .A0(n4143), .A1(n4121), .B0(n4120), .B1(
FPMULT_Add_result[14]), .Y(n1610) );
AO22XLTS U2765 ( .A0(n4143), .A1(n4125), .B0(n4138), .B1(
FPMULT_Add_result[16]), .Y(n1608) );
AO22XLTS U2766 ( .A0(n4143), .A1(n4129), .B0(n4138), .B1(
FPMULT_Add_result[18]), .Y(n1606) );
AO22XLTS U2767 ( .A0(n4143), .A1(n4133), .B0(n4138), .B1(
FPMULT_Add_result[20]), .Y(n1604) );
MX2X1TS U2768 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n4062), .Y(n2227)
);
MX2X1TS U2769 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n2200), .Y(n2228)
);
MX2X1TS U2770 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n2200), .Y(n2229)
);
MX2X1TS U2771 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n2200), .Y(n2230)
);
AO22XLTS U2772 ( .A0(n4064), .A1(Data_2[18]), .B0(n2270), .B1(
FPMULT_Op_MY[18]), .Y(n1645) );
AO22XLTS U2773 ( .A0(n4065), .A1(Data_1[12]), .B0(n2269), .B1(
FPMULT_Op_MX[12]), .Y(n1671) );
AO22XLTS U2774 ( .A0(n4066), .A1(Data_1[1]), .B0(n2270), .B1(FPMULT_Op_MX[1]), .Y(n1660) );
AO22XLTS U2775 ( .A0(n4065), .A1(Data_1[16]), .B0(n4062), .B1(
FPMULT_Op_MX[16]), .Y(n1675) );
AO22XLTS U2776 ( .A0(n4064), .A1(Data_1[9]), .B0(n2269), .B1(FPMULT_Op_MX[9]), .Y(n1668) );
AO22XLTS U2777 ( .A0(n4065), .A1(Data_1[13]), .B0(n2269), .B1(
FPMULT_Op_MX[13]), .Y(n1672) );
AO22XLTS U2778 ( .A0(n4066), .A1(Data_1[10]), .B0(n2269), .B1(
FPMULT_Op_MX[10]), .Y(n1669) );
AO22XLTS U2779 ( .A0(n4064), .A1(Data_1[5]), .B0(n2269), .B1(FPMULT_Op_MX[5]), .Y(n1664) );
AO22XLTS U2780 ( .A0(n4063), .A1(Data_2[9]), .B0(n2200), .B1(FPMULT_Op_MY[9]), .Y(n1636) );
AO22XLTS U2781 ( .A0(n4064), .A1(Data_2[15]), .B0(n2270), .B1(
FPMULT_Op_MY[15]), .Y(n1642) );
AO22XLTS U2782 ( .A0(n4064), .A1(Data_2[17]), .B0(n2270), .B1(
FPMULT_Op_MY[17]), .Y(n1644) );
AO22XLTS U2783 ( .A0(n4064), .A1(Data_2[20]), .B0(n2270), .B1(
FPMULT_Op_MY[20]), .Y(n1647) );
AO22XLTS U2784 ( .A0(n4063), .A1(Data_2[4]), .B0(n2200), .B1(FPMULT_Op_MY[4]), .Y(n1631) );
AO22XLTS U2785 ( .A0(n4063), .A1(Data_2[3]), .B0(n2200), .B1(FPMULT_Op_MY[3]), .Y(n1630) );
AO22XLTS U2786 ( .A0(n4064), .A1(Data_2[2]), .B0(n2200), .B1(FPMULT_Op_MY[2]), .Y(n1629) );
AO22XLTS U2787 ( .A0(n4063), .A1(Data_2[11]), .B0(n2200), .B1(
FPMULT_Op_MY[11]), .Y(n1638) );
AO22XLTS U2788 ( .A0(n4063), .A1(Data_2[7]), .B0(n2200), .B1(FPMULT_Op_MY[7]), .Y(n1634) );
AO22XLTS U2789 ( .A0(n4063), .A1(Data_2[10]), .B0(n2200), .B1(
FPMULT_Op_MY[10]), .Y(n1637) );
AO22XLTS U2790 ( .A0(n4063), .A1(Data_2[6]), .B0(n2200), .B1(FPMULT_Op_MY[6]), .Y(n1633) );
AO22XLTS U2791 ( .A0(n4063), .A1(Data_2[12]), .B0(n2270), .B1(
FPMULT_Op_MY[12]), .Y(n1639) );
AO22XLTS U2792 ( .A0(n4064), .A1(Data_2[14]), .B0(n2270), .B1(
FPMULT_Op_MY[14]), .Y(n1641) );
AO22XLTS U2793 ( .A0(n4066), .A1(Data_1[6]), .B0(n2269), .B1(FPMULT_Op_MX[6]), .Y(n1665) );
AO22XLTS U2794 ( .A0(n4064), .A1(Data_1[7]), .B0(n2269), .B1(FPMULT_Op_MX[7]), .Y(n1666) );
AO22XLTS U2795 ( .A0(n4066), .A1(Data_1[3]), .B0(n2270), .B1(FPMULT_Op_MX[3]), .Y(n1662) );
AO22XLTS U2796 ( .A0(n4066), .A1(Data_1[4]), .B0(n2269), .B1(FPMULT_Op_MX[4]), .Y(n1663) );
AO22XLTS U2797 ( .A0(n4049), .A1(result_add_subt[24]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[24]), .Y(n1784) );
AO22XLTS U2798 ( .A0(n4049), .A1(result_add_subt[26]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[26]), .Y(n1778) );
AO22XLTS U2799 ( .A0(n4049), .A1(result_add_subt[27]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[27]), .Y(n1775) );
AO22XLTS U2800 ( .A0(n4049), .A1(result_add_subt[28]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[28]), .Y(n1772) );
AO22XLTS U2801 ( .A0(n4049), .A1(result_add_subt[22]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[22]), .Y(n2009) );
AO22XLTS U2802 ( .A0(n4055), .A1(result_add_subt[15]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[15]), .Y(n2030) );
AO22XLTS U2803 ( .A0(n4049), .A1(result_add_subt[18]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[18]), .Y(n2021) );
AO22XLTS U2804 ( .A0(n4049), .A1(result_add_subt[21]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[21]), .Y(n2012) );
AO22XLTS U2805 ( .A0(n4049), .A1(result_add_subt[19]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[19]), .Y(n2018) );
AO22XLTS U2806 ( .A0(n4049), .A1(result_add_subt[20]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[20]), .Y(n2015) );
AO22XLTS U2807 ( .A0(n4055), .A1(result_add_subt[17]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[17]), .Y(n2024) );
AO22XLTS U2808 ( .A0(n4055), .A1(result_add_subt[4]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[4]), .Y(n2063) );
AO22XLTS U2809 ( .A0(n4055), .A1(result_add_subt[6]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[6]), .Y(n2057) );
AO22XLTS U2810 ( .A0(n4055), .A1(result_add_subt[13]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[13]), .Y(n2036) );
AO22XLTS U2811 ( .A0(n4055), .A1(result_add_subt[16]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[16]), .Y(n2027) );
AO22XLTS U2812 ( .A0(n4055), .A1(result_add_subt[8]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[8]), .Y(n2051) );
AO22XLTS U2813 ( .A0(n4055), .A1(result_add_subt[11]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[11]), .Y(n2042) );
AO22XLTS U2814 ( .A0(n4055), .A1(result_add_subt[14]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[14]), .Y(n2033) );
AO22XLTS U2815 ( .A0(n4055), .A1(result_add_subt[10]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[10]), .Y(n2045) );
AO22XLTS U2816 ( .A0(n4055), .A1(result_add_subt[12]), .B0(n4054), .B1(
FPSENCOS_d_ff_Yn[12]), .Y(n2039) );
AO22XLTS U2817 ( .A0(n4049), .A1(result_add_subt[3]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[3]), .Y(n2066) );
AO22XLTS U2818 ( .A0(n4055), .A1(result_add_subt[2]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[2]), .Y(n2069) );
AO22XLTS U2819 ( .A0(n4055), .A1(result_add_subt[7]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[7]), .Y(n2054) );
AO22XLTS U2820 ( .A0(n4049), .A1(result_add_subt[0]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[0]), .Y(n2075) );
AO22XLTS U2821 ( .A0(n4055), .A1(result_add_subt[1]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[1]), .Y(n2072) );
AO22XLTS U2822 ( .A0(n4055), .A1(result_add_subt[9]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[9]), .Y(n2048) );
AO22XLTS U2823 ( .A0(n4055), .A1(result_add_subt[5]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[5]), .Y(n2060) );
AO22XLTS U2824 ( .A0(n4061), .A1(result_add_subt[22]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(n2008) );
AO22XLTS U2825 ( .A0(n3953), .A1(result_add_subt[15]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(n2029) );
AO22XLTS U2826 ( .A0(n4061), .A1(result_add_subt[18]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(n2020) );
AO22XLTS U2827 ( .A0(n4061), .A1(result_add_subt[21]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(n2011) );
AO22XLTS U2828 ( .A0(n3953), .A1(result_add_subt[4]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(n2062) );
AO22XLTS U2829 ( .A0(n3953), .A1(result_add_subt[8]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(n2050) );
AO22XLTS U2830 ( .A0(n3953), .A1(result_add_subt[11]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(n2041) );
AO22XLTS U2831 ( .A0(n3953), .A1(result_add_subt[0]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(n2074) );
AO22XLTS U2832 ( .A0(n3953), .A1(result_add_subt[9]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(n2047) );
AO22XLTS U2833 ( .A0(n4061), .A1(result_add_subt[28]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(n1771) );
AO22XLTS U2834 ( .A0(n4061), .A1(result_add_subt[19]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(n2017) );
AO22XLTS U2835 ( .A0(n4061), .A1(result_add_subt[20]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(n2014) );
AO22XLTS U2836 ( .A0(n3953), .A1(result_add_subt[17]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(n2023) );
AO22XLTS U2837 ( .A0(n3953), .A1(result_add_subt[6]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(n2056) );
AO22XLTS U2838 ( .A0(n3953), .A1(result_add_subt[13]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(n2035) );
AO22XLTS U2839 ( .A0(n3953), .A1(result_add_subt[16]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(n2026) );
AO22XLTS U2840 ( .A0(n3953), .A1(result_add_subt[14]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(n2032) );
AO22XLTS U2841 ( .A0(n3953), .A1(result_add_subt[10]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(n2044) );
AO22XLTS U2842 ( .A0(n3953), .A1(result_add_subt[12]), .B0(n4060), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(n2038) );
AO22XLTS U2843 ( .A0(n4061), .A1(result_add_subt[3]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(n2065) );
AO22XLTS U2844 ( .A0(n3953), .A1(result_add_subt[2]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(n2068) );
AO22XLTS U2845 ( .A0(n3953), .A1(result_add_subt[7]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(n2053) );
AO22XLTS U2846 ( .A0(n3953), .A1(result_add_subt[1]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(n2071) );
AO22XLTS U2847 ( .A0(n3953), .A1(result_add_subt[5]), .B0(n3955), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(n2059) );
MX2X1TS U2848 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n2200), .Y(n2231)
);
MX2X1TS U2849 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n2200), .Y(n2232)
);
MX2X1TS U2850 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n2200), .Y(n2233)
);
XNOR2X1TS U2851 ( .A(n2520), .B(FPMULT_Op_MY[21]), .Y(n2521) );
AO22XLTS U2852 ( .A0(n4065), .A1(Data_1[17]), .B0(n4062), .B1(
FPMULT_Op_MX[17]), .Y(n1676) );
AO22XLTS U2853 ( .A0(n4065), .A1(Data_1[18]), .B0(n4062), .B1(
FPMULT_Op_MX[18]), .Y(n1677) );
AO22XLTS U2854 ( .A0(n4065), .A1(Data_1[21]), .B0(n4062), .B1(
FPMULT_Op_MX[21]), .Y(n1680) );
AO22XLTS U2855 ( .A0(n4065), .A1(Data_1[15]), .B0(n4062), .B1(
FPMULT_Op_MX[15]), .Y(n1674) );
AO22XLTS U2856 ( .A0(n4065), .A1(Data_1[19]), .B0(n4062), .B1(
FPMULT_Op_MX[19]), .Y(n1678) );
AO22XLTS U2857 ( .A0(n4520), .A1(n4371), .B0(n4509), .B1(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n1353) );
AO22XLTS U2858 ( .A0(n3917), .A1(n4520), .B0(n3919), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2146) );
AO22XLTS U2859 ( .A0(n4065), .A1(Data_2[1]), .B0(n2200), .B1(FPMULT_Op_MY[1]), .Y(n1628) );
AO22XLTS U2860 ( .A0(n4065), .A1(Data_1[22]), .B0(n4062), .B1(
FPMULT_Op_MX[22]), .Y(n1681) );
AO22XLTS U2861 ( .A0(n4066), .A1(Data_1[0]), .B0(n2270), .B1(FPMULT_Op_MX[0]), .Y(n1659) );
AOI32X1TS U2862 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n4038), .A2(
n3918), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n3788), .Y(n3551)
);
AO22XLTS U2863 ( .A0(n4064), .A1(Data_1[8]), .B0(n2269), .B1(FPMULT_Op_MX[8]), .Y(n1667) );
AO22XLTS U2864 ( .A0(n4065), .A1(Data_1[14]), .B0(n4062), .B1(
FPMULT_Op_MX[14]), .Y(n1673) );
OAI31X1TS U2865 ( .A0(n3924), .A1(FPSENCOS_cont_var_out[1]), .A2(n4611),
.B0(n3833), .Y(n2138) );
AO22XLTS U2866 ( .A0(n4065), .A1(Data_1[20]), .B0(n4062), .B1(
FPMULT_Op_MX[20]), .Y(n1679) );
AO22XLTS U2867 ( .A0(n4064), .A1(Data_2[16]), .B0(n2270), .B1(
FPMULT_Op_MY[16]), .Y(n1643) );
AO22XLTS U2868 ( .A0(n4064), .A1(Data_2[19]), .B0(n2270), .B1(
FPMULT_Op_MY[19]), .Y(n1646) );
AO22XLTS U2869 ( .A0(n4063), .A1(Data_2[5]), .B0(n2200), .B1(FPMULT_Op_MY[5]), .Y(n1632) );
AO22XLTS U2870 ( .A0(n4063), .A1(Data_2[8]), .B0(n2200), .B1(FPMULT_Op_MY[8]), .Y(n1635) );
AO22XLTS U2871 ( .A0(n4063), .A1(Data_2[13]), .B0(n2270), .B1(
FPMULT_Op_MY[13]), .Y(n1640) );
AO22XLTS U2872 ( .A0(n4065), .A1(Data_2[22]), .B0(n2269), .B1(
FPMULT_Op_MY[22]), .Y(n1649) );
AOI32X1TS U2873 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n4038), .A2(
n3918), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n3788), .Y(n3539)
);
AO22XLTS U2874 ( .A0(n4220), .A1(FPMULT_P_Sgf[17]), .B0(n4219), .B1(n4212),
.Y(n1570) );
AO22XLTS U2875 ( .A0(n4220), .A1(FPMULT_P_Sgf[19]), .B0(n4219), .B1(n4206),
.Y(n1572) );
AO22XLTS U2876 ( .A0(n4220), .A1(FPMULT_P_Sgf[21]), .B0(n4200), .B1(n4199),
.Y(n1574) );
AO22XLTS U2877 ( .A0(n4220), .A1(FPMULT_P_Sgf[22]), .B0(n4200), .B1(n4196),
.Y(n1575) );
NAND4XLTS U2878 ( .A(n4070), .B(n4069), .C(n4068), .D(n4067), .Y(n4086) );
AO22XLTS U2879 ( .A0(n3983), .A1(FPSENCOS_d_ff3_sh_x_out[9]), .B0(n3980),
.B1(FPSENCOS_d_ff2_X[9]), .Y(n1988) );
AO22XLTS U2880 ( .A0(n3957), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n3980),
.B1(FPSENCOS_d_ff2_X[1]), .Y(n2004) );
AO22XLTS U2881 ( .A0(n3957), .A1(FPSENCOS_d_ff3_sh_x_out[0]), .B0(n3978),
.B1(FPSENCOS_d_ff2_X[0]), .Y(n2006) );
AO22XLTS U2882 ( .A0(n3957), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n3978),
.B1(FPSENCOS_d_ff2_X[2]), .Y(n2002) );
AO22XLTS U2883 ( .A0(n3983), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n3969),
.B1(FPSENCOS_d_ff2_X[12]), .Y(n1982) );
AO22XLTS U2884 ( .A0(n3983), .A1(FPSENCOS_d_ff3_sh_x_out[10]), .B0(n3975),
.B1(FPSENCOS_d_ff2_X[10]), .Y(n1986) );
AO22XLTS U2885 ( .A0(n3983), .A1(FPSENCOS_d_ff3_sh_x_out[8]), .B0(n3980),
.B1(FPSENCOS_d_ff2_X[8]), .Y(n1990) );
AO22XLTS U2886 ( .A0(n3983), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n3978),
.B1(FPSENCOS_d_ff2_X[6]), .Y(n1994) );
AO22XLTS U2887 ( .A0(n3957), .A1(FPSENCOS_d_ff3_sh_x_out[4]), .B0(n3978),
.B1(FPSENCOS_d_ff2_X[4]), .Y(n1998) );
AO22XLTS U2888 ( .A0(n3983), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n3980),
.B1(FPSENCOS_d_ff2_X[21]), .Y(n1964) );
BUFX6TS U2889 ( .A(n2525), .Y(n2680) );
OA21XLTS U2890 ( .A0(n4607), .A1(n3564), .B0(n3737), .Y(n2234) );
OR2X1TS U2891 ( .A(n4093), .B(n4769), .Y(n2235) );
INVX2TS U2892 ( .A(n2516), .Y(n2241) );
CLKINVX6TS U2893 ( .A(n2516), .Y(n2242) );
INVX2TS U2894 ( .A(n2451), .Y(n2243) );
INVX4TS U2895 ( .A(n2451), .Y(n2244) );
INVX2TS U2896 ( .A(n2474), .Y(n2245) );
INVX4TS U2897 ( .A(n2474), .Y(n2246) );
INVX2TS U2898 ( .A(n2594), .Y(n2247) );
INVX4TS U2899 ( .A(n2594), .Y(n2248) );
INVX2TS U2900 ( .A(n2632), .Y(n2249) );
INVX4TS U2901 ( .A(n2632), .Y(n2250) );
CLKINVX6TS U2902 ( .A(n4509), .Y(n4520) );
CLKINVX6TS U2903 ( .A(n4509), .Y(n4511) );
INVX2TS U2904 ( .A(n2450), .Y(n2255) );
CLKINVX6TS U2905 ( .A(n2450), .Y(n2256) );
INVX2TS U2906 ( .A(n2473), .Y(n2258) );
CLKINVX6TS U2907 ( .A(n2473), .Y(n2259) );
INVX2TS U2908 ( .A(n2572), .Y(n2261) );
CLKINVX6TS U2909 ( .A(n2572), .Y(n2262) );
INVX2TS U2910 ( .A(n2593), .Y(n2263) );
CLKINVX6TS U2911 ( .A(n2593), .Y(n2264) );
INVX2TS U2912 ( .A(n2609), .Y(n2265) );
CLKINVX6TS U2913 ( .A(n2609), .Y(n2266) );
INVX2TS U2914 ( .A(n2631), .Y(n2267) );
CLKINVX6TS U2915 ( .A(n2631), .Y(n2268) );
CLKINVX3TS U2916 ( .A(n4063), .Y(n2269) );
CLKINVX3TS U2917 ( .A(n4066), .Y(n2270) );
CLKINVX6TS U2918 ( .A(FPMULT_Op_MY[12]), .Y(n2271) );
INVX2TS U2919 ( .A(n2333), .Y(n2274) );
CLKINVX6TS U2920 ( .A(n2274), .Y(n2275) );
INVX2TS U2921 ( .A(n2349), .Y(n2276) );
CLKINVX6TS U2922 ( .A(n2276), .Y(n2277) );
INVX2TS U2923 ( .A(n2381), .Y(n2278) );
CLKINVX6TS U2924 ( .A(n2381), .Y(n2279) );
INVX3TS U2925 ( .A(n4264), .Y(n2285) );
OAI221X1TS U2926 ( .A0(n4754), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n4760),
.B1(FPADDSUB_intDY_EWSW[9]), .C0(n4335), .Y(n4342) );
OAI21X1TS U2927 ( .A0(n4770), .A1(n4312), .B0(n4280), .Y(n4273) );
OAI21X1TS U2928 ( .A0(n4771), .A1(n4312), .B0(n4280), .Y(n4281) );
ADDHX1TS U2929 ( .A(n3115), .B(n3114), .CO(n3090), .S(mult_x_69_n466) );
ADDHX1TS U2930 ( .A(n3098), .B(n3097), .CO(n3122), .S(mult_x_69_n427) );
ADDHX1TS U2931 ( .A(n3091), .B(n3090), .CO(n3092), .S(mult_x_69_n461) );
OAI21XLTS U2932 ( .A0(n3575), .A1(n3571), .B0(n3570), .Y(n1733) );
NOR4X2TS U2933 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .C(n4621), .D(n2225), .Y(n3909) );
NAND3X2TS U2934 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n3237), .C(n4599),
.Y(n3528) );
BUFX4TS U2935 ( .A(n4911), .Y(n4914) );
NOR2X2TS U2936 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n3979), .Y(n3982) );
NAND3X2TS U2937 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n3438),
.C(n4734), .Y(n3899) );
NOR4X1TS U2938 ( .A(FPMULT_P_Sgf[6]), .B(FPMULT_P_Sgf[7]), .C(
FPMULT_P_Sgf[8]), .D(FPMULT_P_Sgf[9]), .Y(n3139) );
AOI21X2TS U2939 ( .A0(n4315), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n4308),
.Y(n4589) );
AOI211X2TS U2940 ( .A0(n4315), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n4314),
.C0(n4254), .Y(n4292) );
AOI211X2TS U2941 ( .A0(n4315), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n4314),
.C0(n4313), .Y(n4553) );
NOR2X2TS U2942 ( .A(n4748), .B(n4280), .Y(n4314) );
BUFX4TS U2943 ( .A(n4911), .Y(n4917) );
BUFX4TS U2944 ( .A(n4924), .Y(n4925) );
BUFX4TS U2945 ( .A(n3149), .Y(n3151) );
AOI21X2TS U2946 ( .A0(n4315), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n4308),
.Y(n4555) );
NOR4X1TS U2947 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[7]), .C(
FPMULT_Op_MY[8]), .D(FPMULT_Op_MY[9]), .Y(n4071) );
BUFX4TS U2948 ( .A(n4919), .Y(n4918) );
BUFX3TS U2949 ( .A(n3213), .Y(n3152) );
AOI21X2TS U2950 ( .A0(n4315), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n4308),
.Y(n4529) );
BUFX4TS U2951 ( .A(n4253), .Y(n4315) );
AOI21X2TS U2952 ( .A0(n4315), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n4308),
.Y(n4525) );
INVX2TS U2953 ( .A(n2236), .Y(n2288) );
BUFX4TS U2954 ( .A(n4905), .Y(n4907) );
BUFX4TS U2955 ( .A(n4905), .Y(n4912) );
BUFX4TS U2956 ( .A(n4929), .Y(n4909) );
BUFX4TS U2957 ( .A(n4929), .Y(n4911) );
BUFX4TS U2958 ( .A(n4910), .Y(n4904) );
NOR4X1TS U2959 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[19]), .C(
FPMULT_Op_MX[20]), .D(FPMULT_Op_MX[21]), .Y(n4078) );
NOR4X1TS U2960 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[3]), .C(
FPMULT_Op_MY[4]), .D(FPMULT_Op_MY[5]), .Y(n4074) );
BUFX4TS U2961 ( .A(n4928), .Y(n4915) );
BUFX4TS U2962 ( .A(n3151), .Y(n4908) );
BUFX4TS U2963 ( .A(n3151), .Y(n4929) );
BUFX4TS U2964 ( .A(n3151), .Y(n4910) );
BUFX4TS U2965 ( .A(n3151), .Y(n4905) );
BUFX4TS U2966 ( .A(n4927), .Y(n4902) );
BUFX4TS U2967 ( .A(n4901), .Y(n4903) );
BUFX4TS U2968 ( .A(n4917), .Y(n4916) );
BUFX4TS U2969 ( .A(n4925), .Y(n4901) );
BUFX4TS U2970 ( .A(n4912), .Y(n4927) );
BUFX4TS U2971 ( .A(n4901), .Y(n4923) );
NOR4X1TS U2972 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[19]), .C(
FPMULT_Op_MY[20]), .D(FPMULT_Op_MY[21]), .Y(n4070) );
BUFX6TS U2973 ( .A(n3991), .Y(n4012) );
BUFX4TS U2974 ( .A(n3151), .Y(n4919) );
BUFX4TS U2975 ( .A(n3152), .Y(n4890) );
BUFX4TS U2976 ( .A(n4884), .Y(n4874) );
BUFX4TS U2977 ( .A(n4879), .Y(n4888) );
BUFX4TS U2978 ( .A(n4896), .Y(n4886) );
BUFX4TS U2979 ( .A(n4886), .Y(n4875) );
BUFX4TS U2980 ( .A(n3213), .Y(n4885) );
BUFX4TS U2981 ( .A(n3152), .Y(n4881) );
BUFX4TS U2982 ( .A(n3213), .Y(n4882) );
OAI21X2TS U2983 ( .A0(n4618), .A1(n3564), .B0(n3676), .Y(n4043) );
BUFX4TS U2984 ( .A(n4882), .Y(n4899) );
BUFX4TS U2985 ( .A(n4883), .Y(n4873) );
BUFX4TS U2986 ( .A(n4874), .Y(n4876) );
BUFX4TS U2987 ( .A(n4891), .Y(n4879) );
INVX2TS U2988 ( .A(n4941), .Y(n2289) );
INVX2TS U2989 ( .A(n2289), .Y(n2290) );
CLKINVX6TS U2990 ( .A(n3978), .Y(n3961) );
BUFX4TS U2991 ( .A(n3155), .Y(n3978) );
OAI221X2TS U2992 ( .A0(n4042), .A1(n2220), .B0(n3564), .B1(n4775), .C0(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3792) );
NOR2X2TS U2993 ( .A(n4623), .B(intadd_491_B_1_), .Y(n3226) );
NAND2X2TS U2994 ( .A(n3759), .B(n4861), .Y(n4038) );
BUFX6TS U2995 ( .A(n4365), .Y(n3759) );
BUFX4TS U2996 ( .A(n3289), .Y(n3281) );
OAI32X1TS U2997 ( .A0(n3922), .A1(n3920), .A2(n4951), .B0(n4704), .B1(n3922),
.Y(n2142) );
NOR3X4TS U2998 ( .A(n3920), .B(n4704), .C(n4951), .Y(n3922) );
BUFX4TS U2999 ( .A(n4065), .Y(n4063) );
BUFX6TS U3000 ( .A(n4041), .Y(n3788) );
BUFX4TS U3001 ( .A(n4877), .Y(n4893) );
BUFX4TS U3002 ( .A(n4873), .Y(n4891) );
BUFX4TS U3003 ( .A(n4899), .Y(n4892) );
BUFX4TS U3004 ( .A(n3213), .Y(n4896) );
BUFX4TS U3005 ( .A(n4888), .Y(n4895) );
BUFX4TS U3006 ( .A(n3152), .Y(n4878) );
NOR4X1TS U3007 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[29]), .C(
FPMULT_Op_MY[28]), .D(FPMULT_Op_MY[27]), .Y(n4067) );
BUFX4TS U3008 ( .A(n3958), .Y(n3970) );
NOR3XLTS U3009 ( .A(FPMULT_Op_MY[23]), .B(FPMULT_Op_MY[0]), .C(
FPMULT_Op_MY[1]), .Y(n4073) );
NOR3XLTS U3010 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_Op_MX[0]), .C(
FPMULT_Op_MX[1]), .Y(n4081) );
BUFX6TS U3011 ( .A(n2315), .Y(n3049) );
BUFX3TS U3012 ( .A(n3986), .Y(n4940) );
BUFX4TS U3013 ( .A(n3952), .Y(n4054) );
BUFX4TS U3014 ( .A(n3955), .Y(n4060) );
OAI21XLTS U3015 ( .A0(n3020), .A1(n2279), .B0(n2386), .Y(n2387) );
BUFX6TS U3016 ( .A(n2311), .Y(n3020) );
BUFX6TS U3017 ( .A(n2312), .Y(n4595) );
AOI221X1TS U3018 ( .A0(n4591), .A1(n4318), .B0(n4557), .B1(n4319), .C0(n4320), .Y(n4575) );
NOR2X4TS U3019 ( .A(n2196), .B(n4742), .Y(n4320) );
OAI21X2TS U3020 ( .A0(n4600), .A1(n3564), .B0(n3734), .Y(n3787) );
INVX2TS U3021 ( .A(n2234), .Y(n2292) );
NOR3X1TS U3022 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[21]), .C(
FPMULT_Op_MX[22]), .Y(n2330) );
INVX2TS U3023 ( .A(FPMULT_Op_MY[0]), .Y(n2293) );
CLKINVX3TS U3024 ( .A(n2235), .Y(n2294) );
CLKINVX3TS U3025 ( .A(n2235), .Y(n2295) );
INVX2TS U3026 ( .A(n2380), .Y(n2297) );
CLKINVX6TS U3027 ( .A(n2297), .Y(n2298) );
OAI2BB2X2TS U3028 ( .B0(n2799), .B1(FPMULT_Op_MX[12]), .A0N(FPMULT_Op_MX[12]), .A1N(n2799), .Y(n2351) );
NOR4X1TS U3029 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[11]), .C(
FPMULT_Op_MX[12]), .D(FPMULT_Op_MX[13]), .Y(n4080) );
NOR4X1TS U3030 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[15]), .C(
FPMULT_Op_MX[16]), .D(FPMULT_Op_MX[17]), .Y(n4077) );
NOR4X1TS U3031 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[7]), .C(
FPMULT_Op_MX[8]), .D(FPMULT_Op_MX[9]), .Y(n4079) );
INVX2TS U3032 ( .A(n2238), .Y(n2299) );
INVX2TS U3033 ( .A(n2237), .Y(n2300) );
OAI221X1TS U3034 ( .A0(n4774), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n4758),
.B1(FPADDSUB_intDY_EWSW[27]), .C0(n4337), .Y(n4340) );
AOI222X1TS U3035 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4752), .B0(n3335), .B1(
n3334), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n4646), .Y(n3337) );
AOI221X1TS U3036 ( .A0(n4752), .A1(FPADDSUB_intDY_EWSW[4]), .B0(
FPADDSUB_intDY_EWSW[5]), .B1(n4646), .C0(n4349), .Y(n4352) );
CLKINVX6TS U3037 ( .A(FPMULT_Op_MX[5]), .Y(n2373) );
OAI31X1TS U3038 ( .A0(n2477), .A1(FPMULT_Op_MX[5]), .A2(n2293), .B0(n2476),
.Y(n2506) );
NOR4X1TS U3039 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[3]), .C(
FPMULT_Op_MX[4]), .D(FPMULT_Op_MX[5]), .Y(n4082) );
INVX2TS U3040 ( .A(n2690), .Y(n2301) );
INVX2TS U3041 ( .A(n2697), .Y(n2302) );
INVX2TS U3042 ( .A(n2701), .Y(n2303) );
INVX2TS U3043 ( .A(n2705), .Y(n2304) );
NAND2X4TS U3044 ( .A(n2376), .B(n2375), .Y(n2759) );
OAI221X1TS U3045 ( .A0(n4602), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n4747),
.B1(FPADDSUB_intDY_EWSW[23]), .C0(n4343), .Y(n4358) );
OAI221X1TS U3046 ( .A0(n4650), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n4762),
.B1(FPADDSUB_intDY_EWSW[17]), .C0(n4327), .Y(n4334) );
AOI32X2TS U3047 ( .A0(n3381), .A1(n3382), .A2(n3380), .B0(n3379), .B1(n3382),
.Y(n4362) );
INVX2TS U3048 ( .A(n2305), .Y(n2306) );
AOI222X1TS U3049 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n3972), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n3314), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n3315)
);
XOR2XLTS U3050 ( .A(FPSENCOS_d_ff_Yn[31]), .B(n3459), .Y(n3460) );
OAI33X4TS U3051 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .A2(n4778), .B0(n4613), .B1(
n4654), .B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n3459) );
AOI222X1TS U3052 ( .A0(n3512), .A1(cordic_result[29]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[29]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[29]), .Y(n3501) );
AOI222X1TS U3053 ( .A0(n3512), .A1(cordic_result[30]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[30]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[30]), .Y(n3497) );
XNOR2X2TS U3054 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[6]), .Y(n2367) );
NOR2X1TS U3055 ( .A(n3941), .B(n3931), .Y(n2307) );
NOR2X2TS U3056 ( .A(FPSENCOS_cont_iter_out[3]), .B(intadd_491_B_1_), .Y(
n3941) );
NOR2XLTS U3057 ( .A(n3941), .B(n3931), .Y(n3939) );
INVX1TS U3058 ( .A(n4262), .Y(n3305) );
NOR4X1TS U3059 ( .A(FPMULT_P_Sgf[10]), .B(FPMULT_P_Sgf[11]), .C(
FPMULT_P_Sgf[12]), .D(FPMULT_P_Sgf[13]), .Y(n3140) );
NOR2X2TS U3060 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_491_n1), .Y(n3976) );
AOI21X2TS U3061 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n4315), .B0(n4271),
.Y(n4475) );
OAI21X1TS U3062 ( .A0(n4656), .A1(n4312), .B0(n4280), .Y(n4271) );
XNOR2X2TS U3063 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[3]), .Y(n2374) );
BUFX4TS U3064 ( .A(n4928), .Y(n4920) );
BUFX3TS U3065 ( .A(n3151), .Y(n4928) );
NOR2X2TS U3066 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4689),
.Y(n3887) );
AOI222X1TS U3067 ( .A0(n3482), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n3958), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n3481), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n3479) );
OAI211X2TS U3068 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n4690), .B0(n3354),
.C0(n3340), .Y(n3356) );
AOI211XLTS U3069 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4756), .B0(n3368),
.C0(n3369), .Y(n3360) );
OAI211X2TS U3070 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n4696), .B0(n3374),
.C0(n3359), .Y(n3368) );
BUFX6TS U3071 ( .A(n4365), .Y(n3918) );
BUFX6TS U3072 ( .A(n4426), .Y(n4502) );
OAI211X2TS U3073 ( .A0(n4871), .A1(n3943), .B0(n3234), .C0(n3936), .Y(n3929)
);
OAI21X2TS U3074 ( .A0(n3226), .A1(n4951), .B0(n3936), .Y(n3931) );
AOI211X1TS U3075 ( .A0(n4704), .A1(n4951), .B0(n3957), .C0(n3936), .Y(n3224)
);
NAND2X2TS U3076 ( .A(FPSENCOS_cont_iter_out[3]), .B(intadd_491_B_1_), .Y(
n3936) );
AOI222X1TS U3077 ( .A0(n3512), .A1(cordic_result[26]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[26]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[26]), .Y(n3492) );
AOI222X1TS U3078 ( .A0(n3512), .A1(cordic_result[27]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[27]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[27]), .Y(n3499) );
AOI222X1TS U3079 ( .A0(n3510), .A1(cordic_result[4]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[4]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[4]), .Y(n3493)
);
AOI222X1TS U3080 ( .A0(n3510), .A1(cordic_result[0]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[0]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[0]), .Y(n3522)
);
AOI222X4TS U3081 ( .A0(n3510), .A1(cordic_result[9]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[9]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[9]), .Y(n3518)
);
AOI222X1TS U3082 ( .A0(n3512), .A1(cordic_result[28]), .B0(n3500), .B1(
FPSENCOS_d_ff_Yn[28]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[28]), .Y(n3494) );
AOI222X1TS U3083 ( .A0(n3510), .A1(cordic_result[6]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[6]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[6]), .Y(n3515)
);
AOI222X4TS U3084 ( .A0(n3510), .A1(cordic_result[16]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[16]), .C0(n3509), .C1(FPSENCOS_d_ff_Xn[16]), .Y(n3508) );
AOI222X1TS U3085 ( .A0(n3516), .A1(cordic_result[3]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[3]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[3]), .Y(n3496)
);
AOI222X4TS U3086 ( .A0(n3510), .A1(cordic_result[2]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[2]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[2]), .Y(n3519)
);
AOI222X4TS U3087 ( .A0(n3510), .A1(cordic_result[7]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[7]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[7]), .Y(n3520)
);
AOI222X1TS U3088 ( .A0(n3510), .A1(cordic_result[5]), .B0(n3502), .B1(
FPSENCOS_d_ff_Yn[5]), .C0(n3521), .C1(FPSENCOS_d_ff_Xn[5]), .Y(n3495)
);
AOI222X1TS U3089 ( .A0(n3973), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n3966), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n3386), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n3391) );
AOI222X1TS U3090 ( .A0(n3448), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DmP_EXP_EWSW[23]), .B1(n4368), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3383), .Y(n3449) );
NOR4X1TS U3091 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[28]), .Y(n4075) );
CLKINVX3TS U3092 ( .A(n4249), .Y(n4303) );
CLKINVX6TS U3093 ( .A(n3155), .Y(n3983) );
CLKINVX6TS U3094 ( .A(n4591), .Y(n4557) );
BUFX6TS U3095 ( .A(FPADDSUB_left_right_SHT2), .Y(n4591) );
BUFX4TS U3096 ( .A(n4869), .Y(n4933) );
BUFX4TS U3097 ( .A(n4869), .Y(n4932) );
BUFX4TS U3098 ( .A(n4869), .Y(n4930) );
BUFX4TS U3099 ( .A(n4869), .Y(n4934) );
BUFX4TS U3100 ( .A(n4869), .Y(n4936) );
BUFX4TS U3101 ( .A(n4869), .Y(n4935) );
BUFX4TS U3102 ( .A(n4869), .Y(n4938) );
BUFX4TS U3103 ( .A(n4869), .Y(n4937) );
BUFX4TS U3104 ( .A(n4869), .Y(n4931) );
BUFX4TS U3105 ( .A(n4944), .Y(n4869) );
NAND2X2TS U3106 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n2308) );
OAI21X2TS U3107 ( .A0(n4635), .A1(n2308), .B0(n3698), .Y(n3770) );
OAI21X2TS U3108 ( .A0(n4605), .A1(n2308), .B0(n3695), .Y(n3711) );
OAI21X2TS U3109 ( .A0(n4606), .A1(n2308), .B0(n3690), .Y(n3712) );
OAI21X2TS U3110 ( .A0(n4629), .A1(n2308), .B0(n3674), .Y(n3707) );
OAI21X2TS U3111 ( .A0(n4657), .A1(n2308), .B0(n3694), .Y(n3717) );
OAI21X2TS U3112 ( .A0(n4598), .A1(n2308), .B0(n3757), .Y(n3783) );
OAI21X2TS U3113 ( .A0(n4707), .A1(n3758), .B0(n3722), .Y(n3768) );
OAI21X2TS U3114 ( .A0(n4706), .A1(n3758), .B0(n3752), .Y(n3781) );
BUFX6TS U3115 ( .A(n2567), .Y(n3084) );
BUFX6TS U3116 ( .A(n2604), .Y(n3037) );
OAI211XLTS U3117 ( .A0(n3751), .A1(n2310), .B0(n3579), .C0(n3578), .Y(n1912)
);
OAI32X1TS U3118 ( .A0(n3901), .A1(FPMULT_exp_oper_result[8]), .A2(
FPMULT_Exp_module_Overflow_flag_A), .B0(overflow_flag_addsubt), .B1(
operation[2]), .Y(n3572) );
NOR3XLTS U3119 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n4224), .Y(n4225) );
NAND4X2TS U3120 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n3215),
.C(n4634), .D(n4734), .Y(n3900) );
AOI32X1TS U3121 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n4038), .A2(
n3918), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n3788), .Y(n3565)
);
BUFX3TS U3122 ( .A(n3242), .Y(n2309) );
BUFX3TS U3123 ( .A(n3242), .Y(n3290) );
NOR2X1TS U3124 ( .A(n4769), .B(n3241), .Y(n3242) );
AOI222X4TS U3125 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n4666), .B0(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(n4374), .C0(n4666), .C1(n4374), .Y(
n4380) );
AOI21X2TS U3126 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4315), .B0(n4281),
.Y(n4289) );
AOI21X2TS U3127 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n4315), .B0(n4273),
.Y(n4535) );
AOI222X4TS U3128 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(
FPADDSUB_DMP_SFG[12]), .B0(FPADDSUB_DmP_mant_SFG_SWR[14]), .B1(n4446),
.C0(FPADDSUB_DMP_SFG[12]), .C1(n4446), .Y(n4451) );
AOI222X4TS U3129 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(
FPADDSUB_DMP_SFG[10]), .B0(FPADDSUB_DmP_mant_SFG_SWR[12]), .B1(n4434),
.C0(FPADDSUB_DMP_SFG[10]), .C1(n4434), .Y(n4439) );
AOI222X4TS U3130 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1(
FPADDSUB_DMP_SFG[14]), .B0(FPADDSUB_DmP_mant_SFG_SWR[16]), .B1(n4458),
.C0(FPADDSUB_DMP_SFG[14]), .C1(n4458), .Y(n4463) );
AOI222X4TS U3131 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(
FPADDSUB_DMP_SFG[8]), .B0(FPADDSUB_DmP_mant_SFG_SWR[10]), .B1(n4421),
.C0(FPADDSUB_DMP_SFG[8]), .C1(n4421), .Y(n4427) );
AOI222X4TS U3132 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(
FPADDSUB_DMP_SFG[4]), .B0(FPADDSUB_DmP_mant_SFG_SWR[6]), .B1(n4397),
.C0(FPADDSUB_DMP_SFG[4]), .C1(n4397), .Y(n4402) );
AOI222X4TS U3133 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(
FPADDSUB_DMP_SFG[20]), .B0(FPADDSUB_DmP_mant_SFG_SWR[22]), .B1(n4497),
.C0(FPADDSUB_DMP_SFG[20]), .C1(n4497), .Y(n4503) );
AOI222X4TS U3134 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(
FPADDSUB_DMP_SFG[18]), .B0(FPADDSUB_DmP_mant_SFG_SWR[20]), .B1(n4485),
.C0(FPADDSUB_DMP_SFG[18]), .C1(n4485), .Y(n4490) );
NOR2X2TS U3135 ( .A(n2201), .B(FPMULT_Op_MX[0]), .Y(n2515) );
AOI221X1TS U3136 ( .A0(n4750), .A1(FPADDSUB_intDY_EWSW[0]), .B0(
FPADDSUB_intDY_EWSW[26]), .B1(n4608), .C0(n4347), .Y(n4354) );
AOI222X4TS U3137 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(
FPADDSUB_DMP_SFG[22]), .B0(FPADDSUB_DmP_mant_SFG_SWR[24]), .B1(n4513),
.C0(FPADDSUB_DMP_SFG[22]), .C1(n4513), .Y(n4370) );
NOR3X4TS U3138 ( .A(n3168), .B(FPMULT_FS_Module_state_reg[3]), .C(
FPMULT_FS_Module_state_reg[2]), .Y(n4090) );
NOR4X1TS U3139 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n4621), .C(n4685),
.D(n4599), .Y(n3157) );
NOR3X4TS U3140 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[2]), .C(n4621), .Y(n3238) );
NOR4X1TS U3141 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .C(FPMULT_FS_Module_state_reg[1]), .D(
n4685), .Y(n3385) );
NOR2X6TS U3142 ( .A(n3673), .B(n4039), .Y(n3675) );
OAI221X1TS U3143 ( .A0(n4756), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n4744),
.B1(FPADDSUB_intDY_EWSW[15]), .C0(n4328), .Y(n4333) );
AND3X1TS U3144 ( .A(FPSENCOS_cont_var_out[1]), .B(n3573), .C(n4611), .Y(
n3990) );
NOR2X8TS U3145 ( .A(FPMULT_Op_MY[22]), .B(n2334), .Y(n2325) );
BUFX6TS U3146 ( .A(n3640), .Y(n4026) );
BUFX6TS U3147 ( .A(n3085), .Y(n3088) );
BUFX6TS U3148 ( .A(n2365), .Y(n4596) );
OAI21XLTS U3149 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n4691), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n3330) );
OAI21XLTS U3150 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n4628), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n3350) );
NOR2XLTS U3151 ( .A(n3363), .B(FPADDSUB_intDY_EWSW[16]), .Y(n3364) );
OAI21XLTS U3152 ( .A0(n2587), .A1(n2586), .B0(n3066), .Y(n2585) );
OAI21XLTS U3153 ( .A0(n2944), .A1(n2943), .B0(n3085), .Y(n2942) );
OAI21XLTS U3154 ( .A0(n2273), .A1(n3053), .B0(n2675), .Y(n2676) );
CLKBUFX2TS U3155 ( .A(n2589), .Y(n3032) );
OAI21XLTS U3156 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n4698), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n3362) );
BUFX3TS U3157 ( .A(n2373), .Y(n2720) );
OAI21XLTS U3158 ( .A0(n2624), .A1(n2623), .B0(n2799), .Y(n2622) );
OAI21XLTS U3159 ( .A0(n2862), .A1(n2861), .B0(n3038), .Y(n2860) );
OAI21XLTS U3160 ( .A0(n2817), .A1(n2816), .B0(n2322), .Y(n2815) );
OAI21XLTS U3161 ( .A0(n2874), .A1(n2873), .B0(n3038), .Y(n2872) );
OAI21XLTS U3162 ( .A0(n2854), .A1(n2853), .B0(n3027), .Y(n2852) );
OAI21XLTS U3163 ( .A0(n2958), .A1(n2957), .B0(n3066), .Y(n2956) );
OAI21XLTS U3164 ( .A0(n3052), .A1(n3051), .B0(n3066), .Y(n3050) );
OAI21XLTS U3165 ( .A0(n2273), .A1(n3047), .B0(n2662), .Y(n2663) );
CLKBUFX2TS U3166 ( .A(n2318), .Y(n2524) );
OAI21XLTS U3167 ( .A0(n4772), .A1(n4312), .B0(n4280), .Y(n4268) );
NAND4X1TS U3168 ( .A(n4619), .B(n4598), .C(n4677), .D(n3545), .Y(n3542) );
OAI21XLTS U3169 ( .A0(n2458), .A1(n2457), .B0(n2720), .Y(n2456) );
INVX2TS U3170 ( .A(n2674), .Y(n3054) );
ADDHXLTS U3171 ( .A(n2618), .B(n2617), .CO(n3095), .S(n2642) );
OAI21XLTS U3172 ( .A0(n2726), .A1(n2725), .B0(n2707), .Y(n2724) );
OAI21XLTS U3173 ( .A0(n2783), .A1(n2782), .B0(n2321), .Y(n2781) );
INVX2TS U3174 ( .A(n2658), .Y(n3078) );
OAI21XLTS U3175 ( .A0(n2792), .A1(n2791), .B0(n2357), .Y(n2790) );
INVX2TS U3176 ( .A(n2649), .Y(n3015) );
OAI22X1TS U3177 ( .A0(n2224), .A1(n2246), .B0(n2304), .B1(n3019), .Y(n2755)
);
OR2X1TS U3178 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n3849) );
OAI21XLTS U3179 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n3843), .B0(n3842), .Y(
n3844) );
OAI21XLTS U3180 ( .A0(n2481), .A1(n2480), .B0(n2507), .Y(n2479) );
OAI21XLTS U3181 ( .A0(n2436), .A1(n2435), .B0(n2317), .Y(n2434) );
OAI21XLTS U3182 ( .A0(n2416), .A1(n2415), .B0(n2507), .Y(n2414) );
OAI21XLTS U3183 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n4665), .B0(n4392),
.Y(n4393) );
OAI21XLTS U3184 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n4664), .B0(n4378),
.Y(n4382) );
NOR2X1TS U3185 ( .A(n3575), .B(n3898), .Y(n3599) );
OAI21XLTS U3186 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n4745), .B0(n4492),
.Y(n4493) );
NAND2X1TS U3187 ( .A(FPMULT_Sgf_normalized_result[5]), .B(n4101), .Y(n4103)
);
INVX2TS U3188 ( .A(operation[1]), .Y(n3802) );
NOR2XLTS U3189 ( .A(n4262), .B(n4249), .Y(n4248) );
OAI21XLTS U3190 ( .A0(n4099), .A1(n4671), .B0(n4101), .Y(n4100) );
OAI211XLTS U3191 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4130), .B0(
n4135), .C0(n4132), .Y(n4131) );
OAI211XLTS U3192 ( .A0(n3281), .A1(n4813), .B0(n3274), .C0(n3273), .Y(n1527)
);
OAI211XLTS U3193 ( .A0(n3228), .A1(n4703), .B0(n4138), .C0(n4087), .Y(n1551)
);
OAI211XLTS U3194 ( .A0(n3525), .A1(n3524), .B0(n3523), .C0(n3528), .Y(n1693)
);
OAI21XLTS U3195 ( .A0(n4650), .A1(n4247), .B0(n3420), .Y(n1219) );
OAI21XLTS U3196 ( .A0(n4756), .A1(n3453), .B0(n3452), .Y(n1251) );
OAI21XLTS U3197 ( .A0(n3918), .A1(n2287), .B0(n3540), .Y(n1320) );
OAI21XLTS U3198 ( .A0(n4761), .A1(n3426), .B0(n3398), .Y(n1373) );
OAI211XLTS U3199 ( .A0(n3289), .A1(n4814), .B0(n3264), .C0(n3263), .Y(n1526)
);
OAI21XLTS U3200 ( .A0(n4951), .A1(n3938), .B0(n3231), .Y(n2118) );
OAI211XLTS U3201 ( .A0(n3155), .A1(n4844), .B0(n3235), .C0(n3925), .Y(n2132)
);
OAI21XLTS U3202 ( .A0(n3801), .A1(n4731), .B0(n3823), .Y(op_result[5]) );
OAI21XLTS U3203 ( .A0(n3832), .A1(n4714), .B0(n3826), .Y(op_result[20]) );
BUFX3TS U3204 ( .A(n2357), .Y(n2365) );
NOR3X2TS U3205 ( .A(n2225), .B(FPMULT_FS_Module_state_reg[3]), .C(
FPMULT_FS_Module_state_reg[0]), .Y(n3236) );
NAND3XLTS U3206 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FSM_add_overflow_flag), .C(n3238), .Y(n2324) );
INVX4TS U3207 ( .A(n4200), .Y(n3852) );
BUFX4TS U3208 ( .A(n4200), .Y(n4219) );
BUFX6TS U3209 ( .A(n2316), .Y(n3085) );
BUFX3TS U3210 ( .A(n2531), .Y(n2668) );
INVX2TS U3211 ( .A(n2330), .Y(n2327) );
XNOR2X1TS U3212 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MX[22]), .Y(n2328) );
BUFX4TS U3213 ( .A(n2540), .Y(n2684) );
AOI211X1TS U3214 ( .A0(n2325), .A1(n2668), .B0(n2329), .C0(n2684), .Y(n2332)
);
INVX2TS U3215 ( .A(n2325), .Y(n2331) );
AOI21X1TS U3216 ( .A0(n2668), .A1(n2331), .B0(n2330), .Y(n2519) );
CMPR32X2TS U3217 ( .A(mult_x_69_n180), .B(n3020), .C(n2332), .CO(n3134), .S(
n3130) );
OAI2BB2X2TS U3218 ( .B0(n2316), .B1(FPMULT_Op_MX[19]), .A0N(FPMULT_Op_MX[19]), .A1N(n2316), .Y(n2337) );
OAI2BB2X2TS U3219 ( .B0(n2318), .B1(FPMULT_Op_MX[18]), .A0N(FPMULT_Op_MX[18]), .A1N(n3066), .Y(n2336) );
NAND2X1TS U3220 ( .A(n2337), .B(n2336), .Y(n2333) );
AOI2BB2X4TS U3221 ( .B0(n2334), .B1(n2224), .A0N(n2224), .A1N(n2334), .Y(
n2645) );
INVX2TS U3222 ( .A(n2336), .Y(n2576) );
XNOR2X1TS U3223 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[18]), .Y(n2335) );
BUFX4TS U3224 ( .A(n3072), .Y(n3082) );
NOR2X2TS U3225 ( .A(n2336), .B(n2335), .Y(n2572) );
NOR2X2TS U3226 ( .A(n2337), .B(n2576), .Y(n2573) );
AOI21X1TS U3227 ( .A0(FPMULT_Op_MY[22]), .A1(n2572), .B0(n2573), .Y(n2338)
);
AOI21X1TS U3228 ( .A0(n2274), .A1(n2645), .B0(n2339), .Y(n2340) );
XOR2X1TS U3229 ( .A(n3088), .B(n2340), .Y(n4147) );
BUFX4TS U3230 ( .A(n3066), .Y(n3069) );
OAI2BB2X2TS U3231 ( .B0(n2524), .B1(FPMULT_Op_MX[16]), .A0N(FPMULT_Op_MX[16]), .A1N(n2524), .Y(n2344) );
INVX2TS U3232 ( .A(FPMULT_Op_MX[14]), .Y(n2348) );
BUFX6TS U3233 ( .A(n2348), .Y(n3038) );
OAI2BB2X2TS U3234 ( .B0(n2348), .B1(FPMULT_Op_MX[15]), .A0N(FPMULT_Op_MX[15]), .A1N(n3038), .Y(n2343) );
INVX2TS U3235 ( .A(n2341), .Y(n2690) );
INVX2TS U3236 ( .A(n2343), .Y(n2597) );
XNOR2X1TS U3237 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[15]), .Y(n2342) );
BUFX4TS U3238 ( .A(n3032), .Y(n3065) );
NOR2X2TS U3239 ( .A(n2343), .B(n2342), .Y(n2593) );
NOR2X2TS U3240 ( .A(n2344), .B(n2597), .Y(n2594) );
AOI21X1TS U3241 ( .A0(FPMULT_Op_MY[22]), .A1(n2593), .B0(n2594), .Y(n2345)
);
AOI21X1TS U3242 ( .A0(n2690), .A1(n2645), .B0(n2346), .Y(n2347) );
XOR2X1TS U3243 ( .A(n3069), .B(n2347), .Y(n4154) );
BUFX4TS U3244 ( .A(n2320), .Y(n3041) );
OAI2BB2X2TS U3245 ( .B0(n2348), .B1(FPMULT_Op_MX[13]), .A0N(FPMULT_Op_MX[13]), .A1N(n2320), .Y(n2352) );
INVX2TS U3246 ( .A(FPMULT_Op_MX[11]), .Y(n2356) );
BUFX4TS U3247 ( .A(n2356), .Y(n2799) );
NAND2X1TS U3248 ( .A(n2352), .B(n2351), .Y(n2349) );
INVX2TS U3249 ( .A(n2351), .Y(n2613) );
XNOR2X1TS U3250 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[12]), .Y(n2350) );
BUFX3TS U3251 ( .A(n2605), .Y(n3036) );
NOR2X2TS U3252 ( .A(n2351), .B(n2350), .Y(n2609) );
NOR2X2TS U3253 ( .A(n2352), .B(n2613), .Y(n2610) );
AOI21X1TS U3254 ( .A0(FPMULT_Op_MY[22]), .A1(n2609), .B0(n2610), .Y(n2353)
);
AOI21X1TS U3255 ( .A0(n2276), .A1(n2645), .B0(n2354), .Y(n2355) );
XOR2X1TS U3256 ( .A(n3041), .B(n2355), .Y(n4161) );
BUFX4TS U3257 ( .A(n2322), .Y(n3027) );
OAI2BB2X2TS U3258 ( .B0(n2799), .B1(FPMULT_Op_MX[10]), .A0N(FPMULT_Op_MX[10]), .A1N(n2799), .Y(n2361) );
OAI2BB2X2TS U3259 ( .B0(n2357), .B1(FPMULT_Op_MX[9]), .A0N(FPMULT_Op_MX[9]),
.A1N(n2357), .Y(n2360) );
INVX2TS U3260 ( .A(n2358), .Y(n2697) );
INVX2TS U3261 ( .A(n2360), .Y(n2636) );
XNOR2X1TS U3262 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[9]), .Y(n2359) );
BUFX4TS U3263 ( .A(n2845), .Y(n3024) );
NOR2X2TS U3264 ( .A(n2360), .B(n2359), .Y(n2631) );
NOR2X2TS U3265 ( .A(n2361), .B(n2636), .Y(n2632) );
AOI21X1TS U3266 ( .A0(FPMULT_Op_MY[22]), .A1(n2631), .B0(n2632), .Y(n2362)
);
AOI21X1TS U3267 ( .A0(n2697), .A1(n2645), .B0(n2363), .Y(n2364) );
XOR2X1TS U3268 ( .A(n3027), .B(n2364), .Y(n4168) );
OAI2BB2X2TS U3269 ( .B0(n2357), .B1(FPMULT_Op_MX[7]), .A0N(FPMULT_Op_MX[7]),
.A1N(n2357), .Y(n2369) );
OAI2BB2X2TS U3270 ( .B0(n2720), .B1(FPMULT_Op_MX[6]), .A0N(FPMULT_Op_MX[6]),
.A1N(n2720), .Y(n2368) );
INVX2TS U3271 ( .A(n2366), .Y(n2701) );
NAND3X2TS U3272 ( .A(n2369), .B(n2454), .C(n2367), .Y(n2446) );
BUFX4TS U3273 ( .A(n2446), .Y(n3116) );
NOR2X2TS U3274 ( .A(n2368), .B(n2367), .Y(n2450) );
NOR2X2TS U3275 ( .A(n2369), .B(n2454), .Y(n2451) );
AOI21X1TS U3276 ( .A0(FPMULT_Op_MY[22]), .A1(n2450), .B0(n2451), .Y(n2370)
);
AOI21X1TS U3277 ( .A0(n2701), .A1(n2645), .B0(n2371), .Y(n2372) );
XOR2X1TS U3278 ( .A(n2365), .B(n2372), .Y(n4176) );
BUFX4TS U3279 ( .A(n2373), .Y(n2707) );
OAI2BB2X2TS U3280 ( .B0(n2720), .B1(FPMULT_Op_MX[4]), .A0N(FPMULT_Op_MX[4]),
.A1N(n2720), .Y(n2376) );
OAI2BB2X2TS U3281 ( .B0(n2507), .B1(FPMULT_Op_MX[3]), .A0N(FPMULT_Op_MX[3]),
.A1N(n2507), .Y(n2375) );
INVX2TS U3282 ( .A(n2759), .Y(n2705) );
INVX2TS U3283 ( .A(n2375), .Y(n2477) );
NAND3X4TS U3284 ( .A(n2376), .B(n2477), .C(n2374), .Y(n2745) );
NOR2X2TS U3285 ( .A(n2375), .B(n2374), .Y(n2473) );
NOR2X2TS U3286 ( .A(n2376), .B(n2477), .Y(n2474) );
AOI21X1TS U3287 ( .A0(FPMULT_Op_MY[22]), .A1(n2473), .B0(n2474), .Y(n2377)
);
AOI21X1TS U3288 ( .A0(n2705), .A1(n2645), .B0(n2378), .Y(n2379) );
XOR2X1TS U3289 ( .A(n2707), .B(n2379), .Y(n4183) );
OAI22X1TS U3290 ( .A0(n2855), .A1(FPMULT_Op_MX[1]), .B0(n2201), .B1(
FPMULT_Op_MX[2]), .Y(n2385) );
NAND2X1TS U3291 ( .A(n2385), .B(FPMULT_Op_MX[0]), .Y(n2380) );
INVX2TS U3292 ( .A(n2515), .Y(n2382) );
BUFX4TS U3293 ( .A(n2382), .Y(n2511) );
OAI21XLTS U3294 ( .A0(n2224), .A1(n2279), .B0(n2382), .Y(n2383) );
AOI21X1TS U3295 ( .A0(n2325), .A1(n2297), .B0(n2383), .Y(n2384) );
XOR2X1TS U3296 ( .A(n2855), .B(n2384), .Y(n4189) );
NOR2X2TS U3297 ( .A(n2385), .B(n2202), .Y(n2516) );
AOI21X1TS U3298 ( .A0(FPMULT_Op_MY[22]), .A1(n2515), .B0(n2516), .Y(n2386)
);
AOI21X1TS U3299 ( .A0(n2297), .A1(n2645), .B0(n2387), .Y(n2388) );
XOR2X1TS U3300 ( .A(n2855), .B(n2388), .Y(n4192) );
OAI22X1TS U3301 ( .A0(n2224), .A1(n2242), .B0(n2298), .B1(n3019), .Y(n2392)
);
OAI22X1TS U3302 ( .A0(n3020), .A1(n2382), .B0(n2279), .B1(n2252), .Y(n2391)
);
OAI31X1TS U3303 ( .A0(n2392), .A1(n2317), .A2(n2391), .B0(n2390), .Y(n4195)
);
OAI22X1TS U3304 ( .A0(n2298), .A1(n3015), .B0(n2279), .B1(n2218), .Y(n2396)
);
OAI22X1TS U3305 ( .A0(n3020), .A1(n2242), .B0(n2382), .B1(n2223), .Y(n2395)
);
OAI31X1TS U3306 ( .A0(n2396), .A1(n2317), .A2(n2395), .B0(n2394), .Y(n4198)
);
OAI22X1TS U3307 ( .A0(n2298), .A1(n3011), .B0(n2382), .B1(n2218), .Y(n2400)
);
OAI22X1TS U3308 ( .A0(n2242), .A1(n2223), .B0(n2279), .B1(n4595), .Y(n2399)
);
OAI31X1TS U3309 ( .A0(n2400), .A1(n2317), .A2(n2399), .B0(n2398), .Y(n4202)
);
OAI22X1TS U3310 ( .A0(n2298), .A1(n3007), .B0(n2279), .B1(n2219), .Y(n2404)
);
OAI22X1TS U3311 ( .A0(n2242), .A1(n2218), .B0(n2511), .B1(n4595), .Y(n2403)
);
OAI31X1TS U3312 ( .A0(n2404), .A1(n2317), .A2(n2403), .B0(n2402), .Y(n4205)
);
OAI22X1TS U3313 ( .A0(n2298), .A1(n3083), .B0(n2279), .B1(n2217), .Y(n2408)
);
OAI22X1TS U3314 ( .A0(n2242), .A1(n4595), .B0(n2511), .B1(n2219), .Y(n2407)
);
OAI31X1TS U3315 ( .A0(n2408), .A1(n2317), .A2(n2407), .B0(n2406), .Y(n4208)
);
OAI22X1TS U3316 ( .A0(n2298), .A1(n3078), .B0(n2511), .B1(n2217), .Y(n2412)
);
OAI22X1TS U3317 ( .A0(n2242), .A1(n2219), .B0(n2279), .B1(n3049), .Y(n2411)
);
OAI31X1TS U3318 ( .A0(n2412), .A1(n2855), .A2(n2411), .B0(n2410), .Y(n4211)
);
OAI22X1TS U3319 ( .A0(n2298), .A1(n3048), .B0(n2279), .B1(n3047), .Y(n2416)
);
OAI22X1TS U3320 ( .A0(n2242), .A1(n2217), .B0(n2511), .B1(n3049), .Y(n2415)
);
OAI31X1TS U3321 ( .A0(n2416), .A1(n2855), .A2(n2415), .B0(n2414), .Y(n4214)
);
OAI22X1TS U3322 ( .A0(n2298), .A1(n3043), .B0(n2511), .B1(n2216), .Y(n2420)
);
OAI22X1TS U3323 ( .A0(n2242), .A1(n3049), .B0(n2279), .B1(n2215), .Y(n2419)
);
OAI31X1TS U3324 ( .A0(n2420), .A1(n2855), .A2(n2419), .B0(n2418), .Y(n4217)
);
OAI22X1TS U3325 ( .A0(n2298), .A1(n2988), .B0(n2242), .B1(n3047), .Y(n2424)
);
OAI22X1TS U3326 ( .A0(n2511), .A1(mult_x_69_n220), .B0(n2279), .B1(n2271),
.Y(n2423) );
OAI31X1TS U3327 ( .A0(n2424), .A1(n2855), .A2(n2423), .B0(n2422), .Y(n3210)
);
OAI22X1TS U3328 ( .A0(n2298), .A1(n2984), .B0(n2279), .B1(n2214), .Y(n2428)
);
OAI22X1TS U3329 ( .A0(n2242), .A1(mult_x_69_n220), .B0(n2511), .B1(n2271),
.Y(n2427) );
OAI31X1TS U3330 ( .A0(n2428), .A1(n2855), .A2(n2427), .B0(n2426), .Y(n3207)
);
OAI22X1TS U3331 ( .A0(n2298), .A1(n3073), .B0(n2279), .B1(n3071), .Y(n2432)
);
OAI22X1TS U3332 ( .A0(n2242), .A1(n2271), .B0(n2511), .B1(n3074), .Y(n2431)
);
OAI31X1TS U3333 ( .A0(n2432), .A1(n2855), .A2(n2431), .B0(n2430), .Y(n3204)
);
OAI22X1TS U3334 ( .A0(n2298), .A1(n3058), .B0(n2511), .B1(n3071), .Y(n2436)
);
BUFX4TS U3335 ( .A(n2313), .Y(n2974) );
OAI22X1TS U3336 ( .A0(n2242), .A1(n3074), .B0(n2279), .B1(n2974), .Y(n2435)
);
OAI31X1TS U3337 ( .A0(n2436), .A1(n2855), .A2(n2435), .B0(n2434), .Y(n3201)
);
OAI22X1TS U3338 ( .A0(n2298), .A1(n3054), .B0(n2279), .B1(n2210), .Y(n2440)
);
OAI22X1TS U3339 ( .A0(n2242), .A1(n3071), .B0(n2511), .B1(n2974), .Y(n2439)
);
OAI31X1TS U3340 ( .A0(n2440), .A1(n2855), .A2(n2439), .B0(n2438), .Y(n3198)
);
OAI22X1TS U3341 ( .A0(n2298), .A1(n2973), .B0(n2511), .B1(n3053), .Y(n2444)
);
OAI22X1TS U3342 ( .A0(n2242), .A1(n2974), .B0(n2279), .B1(mult_x_69_n272),
.Y(n2443) );
OAI31X1TS U3343 ( .A0(n2444), .A1(n2317), .A2(n2443), .B0(n2442), .Y(n3195)
);
OAI22X1TS U3344 ( .A0(n2366), .A1(n2626), .B0(n2255), .B1(n2204), .Y(n2449)
);
OAI22X1TS U3345 ( .A0(n2243), .A1(n3118), .B0(n2446), .B1(n2203), .Y(n2448)
);
OAI21X1TS U3346 ( .A0(n2449), .A1(n2448), .B0(n4596), .Y(n2447) );
OAI31X1TS U3347 ( .A0(n2449), .A1(n4596), .A2(n2448), .B0(n2447), .Y(n3110)
);
AOI222X1TS U3348 ( .A0(n2701), .A1(n2633), .B0(n2451), .B1(FPMULT_Op_MY[1]),
.C0(n2450), .C1(FPMULT_Op_MY[0]), .Y(n2452) );
XOR2X1TS U3349 ( .A(n2321), .B(n2452), .Y(n2460) );
OAI21XLTS U3350 ( .A0(n2454), .A1(n2293), .B0(FPMULT_Op_MX[8]), .Y(n2453) );
OAI22X1TS U3351 ( .A0(n2759), .A1(n2934), .B0(n2752), .B1(n2257), .Y(n2458)
);
OAI22X1TS U3352 ( .A0(n2245), .A1(n2945), .B0(n2258), .B1(n2205), .Y(n2457)
);
OAI31X1TS U3353 ( .A0(n2458), .A1(n2373), .A2(n2457), .B0(n2456), .Y(n3112)
);
OAI22X1TS U3354 ( .A0(n2759), .A1(n2938), .B0(n2752), .B1(n3118), .Y(n2464)
);
OAI22X1TS U3355 ( .A0(n2245), .A1(n2205), .B0(n2258), .B1(n2206), .Y(n2463)
);
OAI31X1TS U3356 ( .A0(n2464), .A1(n2373), .A2(n2463), .B0(n2462), .Y(n2483)
);
OAI22X1TS U3357 ( .A0(n2759), .A1(n3117), .B0(n2752), .B1(n2204), .Y(n2468)
);
OAI22X1TS U3358 ( .A0(n2245), .A1(n2206), .B0(n2258), .B1(n3118), .Y(n2467)
);
OAI21X1TS U3359 ( .A0(n2468), .A1(n2467), .B0(n2720), .Y(n2466) );
OAI31X1TS U3360 ( .A0(n2468), .A1(n2373), .A2(n2467), .B0(n2466), .Y(n2491)
);
ADDHXLTS U3361 ( .A(FPMULT_Op_MX[8]), .B(n2469), .CO(n2459), .S(n2490) );
OAI22X1TS U3362 ( .A0(n2759), .A1(n2626), .B0(n2258), .B1(n2204), .Y(n2472)
);
OAI22X1TS U3363 ( .A0(n2245), .A1(n3118), .B0(n2752), .B1(n2293), .Y(n2471)
);
OAI31X1TS U3364 ( .A0(n2472), .A1(n2720), .A2(n2471), .B0(n2470), .Y(n2497)
);
AOI222X1TS U3365 ( .A0(n2705), .A1(n2633), .B0(n2474), .B1(FPMULT_Op_MY[1]),
.C0(n2473), .C1(FPMULT_Op_MY[0]), .Y(n2475) );
XOR2X1TS U3366 ( .A(n2707), .B(n2475), .Y(n2502) );
OAI21XLTS U3367 ( .A0(n2477), .A1(n2293), .B0(FPMULT_Op_MX[5]), .Y(n2476) );
OAI22X1TS U3368 ( .A0(n2298), .A1(n2962), .B0(n2242), .B1(n3053), .Y(n2481)
);
OAI22X1TS U3369 ( .A0(n2511), .A1(mult_x_69_n272), .B0(n2279), .B1(n2208),
.Y(n2480) );
OAI31X1TS U3370 ( .A0(n2481), .A1(n2317), .A2(n2480), .B0(n2479), .Y(n3191)
);
CMPR32X2TS U3371 ( .A(n2484), .B(n2483), .C(n2482), .CO(n3111), .S(n3188) );
OAI22X1TS U3372 ( .A0(n2298), .A1(n2946), .B0(n2279), .B1(n2945), .Y(n2488)
);
OAI22X1TS U3373 ( .A0(n2242), .A1(mult_x_69_n272), .B0(n2511), .B1(n2208),
.Y(n2487) );
OAI31X1TS U3374 ( .A0(n2488), .A1(n2317), .A2(n2487), .B0(n2486), .Y(n3187)
);
CMPR32X2TS U3375 ( .A(n2491), .B(n2490), .C(n2489), .CO(n2482), .S(n3184) );
OAI22X1TS U3376 ( .A0(n2298), .A1(n2930), .B0(n2278), .B1(n2205), .Y(n2495)
);
OAI22X1TS U3377 ( .A0(n2242), .A1(n2208), .B0(n2511), .B1(n2945), .Y(n2494)
);
OAI21XLTS U3378 ( .A0(n2495), .A1(n2494), .B0(n2507), .Y(n2493) );
OAI31X1TS U3379 ( .A0(n2495), .A1(n2317), .A2(n2494), .B0(n2493), .Y(n3183)
);
ADDHXLTS U3380 ( .A(n2497), .B(n2496), .CO(n2489), .S(n3180) );
OAI22X1TS U3381 ( .A0(n2298), .A1(n2934), .B0(n2278), .B1(n2206), .Y(n2500)
);
OAI22X1TS U3382 ( .A0(n2241), .A1(n2945), .B0(n2511), .B1(n2205), .Y(n2499)
);
OAI21X1TS U3383 ( .A0(n2500), .A1(n2499), .B0(n2507), .Y(n2498) );
OAI31X1TS U3384 ( .A0(n2500), .A1(n2317), .A2(n2499), .B0(n2498), .Y(n3179)
);
ADDHXLTS U3385 ( .A(n2502), .B(n2501), .CO(n2496), .S(n3176) );
OAI22X1TS U3386 ( .A0(n2298), .A1(n2938), .B0(n2278), .B1(n3118), .Y(n2505)
);
OAI22X1TS U3387 ( .A0(n2241), .A1(n2205), .B0(n2511), .B1(n2206), .Y(n2504)
);
OAI31X1TS U3388 ( .A0(n2505), .A1(n2317), .A2(n2504), .B0(n2503), .Y(n3175)
);
ADDHXLTS U3389 ( .A(FPMULT_Op_MX[5]), .B(n2506), .CO(n2501), .S(n3172) );
OAI22X1TS U3390 ( .A0(n2380), .A1(n3117), .B0(n2278), .B1(n2204), .Y(n2510)
);
OAI22X1TS U3391 ( .A0(n2241), .A1(n2206), .B0(n2511), .B1(n3118), .Y(n2509)
);
OAI31X1TS U3392 ( .A0(n2510), .A1(n2507), .A2(n2509), .B0(n2508), .Y(n3171)
);
OAI22X1TS U3393 ( .A0(n2380), .A1(n2626), .B0(n2511), .B1(n2204), .Y(n2514)
);
OAI22X1TS U3394 ( .A0(n2241), .A1(n3118), .B0(n2278), .B1(n2203), .Y(n2513)
);
OAI21X1TS U3395 ( .A0(n2514), .A1(n2513), .B0(n2855), .Y(n2512) );
OAI31X1TS U3396 ( .A0(n2514), .A1(n2855), .A2(n2513), .B0(n2512), .Y(n3164)
);
AOI222X1TS U3397 ( .A0(n2297), .A1(n2633), .B0(n2516), .B1(FPMULT_Op_MY[1]),
.C0(n2515), .C1(FPMULT_Op_MY[0]), .Y(n2517) );
XOR2X1TS U3398 ( .A(n2855), .B(n2517), .Y(n3161) );
OAI21XLTS U3399 ( .A0(n2202), .A1(n2293), .B0(FPMULT_Op_MX[2]), .Y(n2518) );
CMPR32X2TS U3400 ( .A(n3020), .B(FPMULT_Op_MY[22]), .C(n2519), .CO(n2520),
.S(n3133) );
NOR2BX1TS U3401 ( .AN(FPMULT_Op_MX[22]), .B(n2553), .Y(n2525) );
AOI22X1TS U3402 ( .A0(n2668), .A1(n2526), .B0(n2684), .B1(FPMULT_Op_MY[17]),
.Y(n2527) );
AOI21X1TS U3403 ( .A0(n2680), .A1(FPMULT_Op_MY[18]), .B0(n2528), .Y(n2530)
);
CMPR32X2TS U3404 ( .A(mult_x_69_n211), .B(n3049), .C(n2530), .CO(n2529), .S(
mult_x_69_n206) );
AOI22X1TS U3405 ( .A0(n2531), .A1(n2532), .B0(n2540), .B1(FPMULT_Op_MY[12]),
.Y(n2533) );
AOI21X1TS U3406 ( .A0(n2680), .A1(FPMULT_Op_MY[13]), .B0(n2534), .Y(n2535)
);
AOI22X1TS U3407 ( .A0(n2531), .A1(n2536), .B0(n2540), .B1(FPMULT_Op_MY[11]),
.Y(n2537) );
AOI21X1TS U3408 ( .A0(n2680), .A1(FPMULT_Op_MY[12]), .B0(n2538), .Y(n2539)
);
CMPR32X2TS U3409 ( .A(mult_x_69_n260), .B(n2974), .C(n2539), .CO(
mult_x_69_n251), .S(mult_x_69_n252) );
AOI22X1TS U3410 ( .A0(n2531), .A1(n2541), .B0(n2540), .B1(FPMULT_Op_MY[6]),
.Y(n2542) );
AOI21X1TS U3411 ( .A0(n2680), .A1(FPMULT_Op_MY[7]), .B0(n2543), .Y(n2544) );
AOI22X1TS U3412 ( .A0(n2531), .A1(n2545), .B0(n2540), .B1(FPMULT_Op_MY[5]),
.Y(n2546) );
AOI21X1TS U3413 ( .A0(n2680), .A1(FPMULT_Op_MY[6]), .B0(n2547), .Y(n2548) );
AOI22X1TS U3414 ( .A0(n2531), .A1(n2549), .B0(n2684), .B1(FPMULT_Op_MY[4]),
.Y(n2550) );
AOI21X1TS U3415 ( .A0(n2680), .A1(FPMULT_Op_MY[5]), .B0(n2551), .Y(n2552) );
AOI22X1TS U3416 ( .A0(n2531), .A1(n2554), .B0(n2684), .B1(FPMULT_Op_MY[3]),
.Y(n2555) );
AOI21X1TS U3417 ( .A0(n2280), .A1(FPMULT_Op_MY[4]), .B0(n2556), .Y(n2564) );
AOI22X1TS U3418 ( .A0(n2531), .A1(n2557), .B0(n2684), .B1(FPMULT_Op_MY[2]),
.Y(n2558) );
AOI21X1TS U3419 ( .A0(n2280), .A1(FPMULT_Op_MY[3]), .B0(n2559), .Y(n2566) );
AOI22X1TS U3420 ( .A0(n2531), .A1(n2560), .B0(n2684), .B1(FPMULT_Op_MY[1]),
.Y(n2561) );
AOI21X1TS U3421 ( .A0(n2280), .A1(FPMULT_Op_MY[2]), .B0(n2562), .Y(n3108) );
INVX2TS U3422 ( .A(mult_x_69_n381), .Y(n3106) );
AOI222X1TS U3423 ( .A0(n2668), .A1(n2633), .B0(n2280), .B1(FPMULT_Op_MY[1]),
.C0(n2684), .C1(FPMULT_Op_MY[0]), .Y(n3105) );
CMPR32X2TS U3424 ( .A(n2564), .B(FPMULT_Op_MY[1]), .C(n2563), .CO(
mult_x_69_n336), .S(mult_x_69_n337) );
CMPR32X2TS U3425 ( .A(n2566), .B(FPMULT_Op_MY[0]), .C(n2565), .CO(n2563),
.S(mult_x_69_n348) );
OAI22X1TS U3426 ( .A0(n2333), .A1(n2626), .B0(n2261), .B1(n2204), .Y(n2571)
);
INVX2TS U3427 ( .A(n2573), .Y(n2567) );
OAI22X1TS U3428 ( .A0(n2567), .A1(n3118), .B0(n2568), .B1(n2203), .Y(n2570)
);
OAI31X1TS U3429 ( .A0(n2571), .A1(n2316), .A2(n2570), .B0(n2569), .Y(n3104)
);
AOI222X1TS U3430 ( .A0(n2274), .A1(n2633), .B0(n2573), .B1(FPMULT_Op_MY[1]),
.C0(n2572), .C1(FPMULT_Op_MY[0]), .Y(n2574) );
XOR2X1TS U3431 ( .A(n3088), .B(n2574), .Y(n2581) );
OAI21XLTS U3432 ( .A0(n2576), .A1(n2203), .B0(FPMULT_Op_MX[20]), .Y(n2575)
);
OAI22X1TS U3433 ( .A0(n2341), .A1(n2934), .B0(n3065), .B1(n2257), .Y(n2579)
);
OAI22X1TS U3434 ( .A0(n2247), .A1(n2209), .B0(n2263), .B1(n2260), .Y(n2578)
);
OAI31X1TS U3435 ( .A0(n2579), .A1(n3069), .A2(n2578), .B0(n2577), .Y(n2599)
);
ADDHXLTS U3436 ( .A(n2581), .B(n2580), .CO(n3103), .S(n2603) );
OAI22X1TS U3437 ( .A0(n2341), .A1(n2938), .B0(n3032), .B1(n3118), .Y(n2584)
);
OAI22X1TS U3438 ( .A0(n2247), .A1(n2260), .B0(n2263), .B1(n2257), .Y(n2583)
);
OAI31X1TS U3439 ( .A0(n2584), .A1(n3069), .A2(n2583), .B0(n2582), .Y(n2602)
);
OAI22X1TS U3440 ( .A0(n2341), .A1(n3117), .B0(n3032), .B1(n2204), .Y(n2587)
);
OAI22X1TS U3441 ( .A0(n2247), .A1(n2257), .B0(n2263), .B1(n2207), .Y(n2586)
);
OAI31X1TS U3442 ( .A0(n2587), .A1(n3069), .A2(n2586), .B0(n2585), .Y(n3101)
);
ADDHXLTS U3443 ( .A(FPMULT_Op_MX[20]), .B(n2588), .CO(n2580), .S(n3100) );
OAI22X1TS U3444 ( .A0(n2341), .A1(n2626), .B0(n2263), .B1(n2204), .Y(n2592)
);
OAI22X1TS U3445 ( .A0(n2247), .A1(n2207), .B0(n2589), .B1(n2203), .Y(n2591)
);
OAI31X1TS U3446 ( .A0(n2592), .A1(n3069), .A2(n2591), .B0(n2590), .Y(n3123)
);
AOI222X1TS U3447 ( .A0(n2690), .A1(n2633), .B0(n2594), .B1(FPMULT_Op_MY[1]),
.C0(n2593), .C1(FPMULT_Op_MY[0]), .Y(n2595) );
XOR2X1TS U3448 ( .A(n3069), .B(n2595), .Y(n3098) );
OAI21XLTS U3449 ( .A0(n2597), .A1(n2203), .B0(FPMULT_Op_MX[17]), .Y(n2596)
);
OAI31X1TS U3450 ( .A0(n2597), .A1(FPMULT_Op_MX[17]), .A2(n2203), .B0(n2596),
.Y(n2969) );
CMPR32X2TS U3451 ( .A(n2600), .B(n2599), .C(n2598), .CO(mult_x_69_n388), .S(
mult_x_69_n389) );
CMPR32X2TS U3452 ( .A(n2603), .B(n2602), .C(n2601), .CO(n2598), .S(
mult_x_69_n399) );
OAI22X1TS U3453 ( .A0(n2349), .A1(n2626), .B0(n2265), .B1(n2204), .Y(n2608)
);
INVX2TS U3454 ( .A(n2610), .Y(n2604) );
BUFX3TS U3455 ( .A(n2605), .Y(n2893) );
OAI22X1TS U3456 ( .A0(n2604), .A1(n2207), .B0(n2893), .B1(n2203), .Y(n2607)
);
OAI31X1TS U3457 ( .A0(n2608), .A1(n3041), .A2(n2607), .B0(n2606), .Y(n3096)
);
AOI222X1TS U3458 ( .A0(n2276), .A1(n2633), .B0(n2610), .B1(FPMULT_Op_MY[1]),
.C0(n2609), .C1(FPMULT_Op_MY[0]), .Y(n2611) );
XOR2X1TS U3459 ( .A(n3041), .B(n2611), .Y(n2618) );
OAI21XLTS U3460 ( .A0(n2613), .A1(n2203), .B0(FPMULT_Op_MX[14]), .Y(n2612)
);
OAI22X1TS U3461 ( .A0(n2358), .A1(n2934), .B0(n3024), .B1(n2257), .Y(n2616)
);
OAI22X1TS U3462 ( .A0(n2249), .A1(n2209), .B0(n2267), .B1(n2260), .Y(n2615)
);
OAI31X1TS U3463 ( .A0(n2616), .A1(n2799), .A2(n2615), .B0(n2614), .Y(n2638)
);
OAI22X1TS U3464 ( .A0(n2358), .A1(n2938), .B0(n2845), .B1(n2207), .Y(n2621)
);
OAI22X1TS U3465 ( .A0(n2249), .A1(n2260), .B0(n2267), .B1(n2257), .Y(n2620)
);
OAI31X1TS U3466 ( .A0(n2621), .A1(n2799), .A2(n2620), .B0(n2619), .Y(n2641)
);
OAI22X1TS U3467 ( .A0(n2358), .A1(n3117), .B0(n2845), .B1(n2204), .Y(n2624)
);
OAI22X1TS U3468 ( .A0(n2249), .A1(n2206), .B0(n2267), .B1(n2207), .Y(n2623)
);
OAI31X1TS U3469 ( .A0(n2624), .A1(n2799), .A2(n2623), .B0(n2622), .Y(n3094)
);
ADDHXLTS U3470 ( .A(FPMULT_Op_MX[14]), .B(n2625), .CO(n2617), .S(n3093) );
OAI22X1TS U3471 ( .A0(n2358), .A1(n2626), .B0(n2267), .B1(n2204), .Y(n2630)
);
OAI22X1TS U3472 ( .A0(n2249), .A1(n2207), .B0(n2627), .B1(n2203), .Y(n2629)
);
AOI222X1TS U3473 ( .A0(n2697), .A1(n2633), .B0(n2632), .B1(FPMULT_Op_MY[1]),
.C0(n2631), .C1(FPMULT_Op_MY[0]), .Y(n2634) );
XOR2X1TS U3474 ( .A(n3027), .B(n2634), .Y(n3115) );
OAI21XLTS U3475 ( .A0(n2636), .A1(n2293), .B0(FPMULT_Op_MX[11]), .Y(n2635)
);
CMPR32X2TS U3476 ( .A(n2639), .B(n2638), .C(n2637), .CO(mult_x_69_n439), .S(
mult_x_69_n440) );
CMPR32X2TS U3477 ( .A(n2642), .B(n2641), .C(n2640), .CO(n2637), .S(
mult_x_69_n447) );
AOI21X1TS U3478 ( .A0(FPMULT_Op_MY[22]), .A1(n2684), .B0(n2680), .Y(n2643)
);
AOI21X1TS U3479 ( .A0(n2668), .A1(n2645), .B0(n2644), .Y(mult_x_69_n593) );
AOI22X1TS U3480 ( .A0(FPMULT_Op_MY[22]), .A1(n2680), .B0(n2668), .B1(n2646),
.Y(n2647) );
AOI21X1TS U3481 ( .A0(FPMULT_Op_MY[21]), .A1(n2684), .B0(n2648), .Y(
mult_x_69_n594) );
AOI22X1TS U3482 ( .A0(n2668), .A1(n2649), .B0(n2684), .B1(FPMULT_Op_MY[20]),
.Y(n2650) );
AOI21X1TS U3483 ( .A0(FPMULT_Op_MY[21]), .A1(n2680), .B0(n2651), .Y(
mult_x_69_n595) );
AOI22X1TS U3484 ( .A0(n2668), .A1(n2652), .B0(n2684), .B1(FPMULT_Op_MY[19]),
.Y(n2653) );
AOI21X1TS U3485 ( .A0(n2680), .A1(FPMULT_Op_MY[20]), .B0(n2654), .Y(
mult_x_69_n596) );
AOI22X1TS U3486 ( .A0(n2668), .A1(n2655), .B0(n2680), .B1(FPMULT_Op_MY[19]),
.Y(n2656) );
AOI21X1TS U3487 ( .A0(n2684), .A1(FPMULT_Op_MY[18]), .B0(n2657), .Y(
mult_x_69_n597) );
AOI22X1TS U3488 ( .A0(n2668), .A1(n2658), .B0(n2684), .B1(FPMULT_Op_MY[16]),
.Y(n2659) );
AOI21X1TS U3489 ( .A0(n2680), .A1(FPMULT_Op_MY[17]), .B0(n2660), .Y(
mult_x_69_n599) );
AOI22X1TS U3490 ( .A0(n2668), .A1(n2661), .B0(n2680), .B1(FPMULT_Op_MY[16]),
.Y(n2662) );
AOI21X1TS U3491 ( .A0(n2684), .A1(FPMULT_Op_MY[15]), .B0(n2663), .Y(
mult_x_69_n600) );
AOI22X1TS U3492 ( .A0(n2531), .A1(n2664), .B0(n2684), .B1(FPMULT_Op_MY[14]),
.Y(n2665) );
AOI21X1TS U3493 ( .A0(n2680), .A1(FPMULT_Op_MY[15]), .B0(n2666), .Y(
mult_x_69_n601) );
AOI22X1TS U3494 ( .A0(n2668), .A1(n2667), .B0(n2680), .B1(FPMULT_Op_MY[14]),
.Y(n2669) );
AOI21X1TS U3495 ( .A0(n2684), .A1(FPMULT_Op_MY[13]), .B0(n2670), .Y(
mult_x_69_n602) );
AOI22X1TS U3496 ( .A0(n2531), .A1(n2671), .B0(n2540), .B1(FPMULT_Op_MY[10]),
.Y(n2672) );
AOI21X1TS U3497 ( .A0(n2680), .A1(FPMULT_Op_MY[11]), .B0(n2673), .Y(
mult_x_69_n605) );
AOI22X1TS U3498 ( .A0(n2531), .A1(n2674), .B0(n2680), .B1(FPMULT_Op_MY[10]),
.Y(n2675) );
AOI21X1TS U3499 ( .A0(n2684), .A1(FPMULT_Op_MY[9]), .B0(n2676), .Y(
mult_x_69_n606) );
AOI22X1TS U3500 ( .A0(n2531), .A1(n2677), .B0(n2540), .B1(FPMULT_Op_MY[8]),
.Y(n2678) );
AOI21X1TS U3501 ( .A0(n2680), .A1(FPMULT_Op_MY[9]), .B0(n2679), .Y(
mult_x_69_n607) );
AOI22X1TS U3502 ( .A0(n2531), .A1(n2681), .B0(n2680), .B1(FPMULT_Op_MY[8]),
.Y(n2682) );
AOI21X1TS U3503 ( .A0(n2684), .A1(FPMULT_Op_MY[7]), .B0(n2683), .Y(
mult_x_69_n608) );
XOR2X1TS U3504 ( .A(FPMULT_Op_MX[20]), .B(n2685), .Y(mult_x_69_n617) );
AOI21X1TS U3505 ( .A0(n2325), .A1(n2274), .B0(n2686), .Y(n2687) );
XOR2X1TS U3506 ( .A(n3088), .B(n2687), .Y(mult_x_69_n618) );
XOR2X1TS U3507 ( .A(FPMULT_Op_MX[17]), .B(n2688), .Y(mult_x_69_n644) );
AOI21X1TS U3508 ( .A0(n2325), .A1(n2690), .B0(n2689), .Y(n2691) );
XOR2X1TS U3509 ( .A(n3069), .B(n2691), .Y(mult_x_69_n645) );
XOR2X1TS U3510 ( .A(FPMULT_Op_MX[14]), .B(n2692), .Y(mult_x_69_n671) );
AOI21X1TS U3511 ( .A0(n2325), .A1(n2276), .B0(n2693), .Y(n2694) );
XOR2X1TS U3512 ( .A(n3041), .B(n2694), .Y(mult_x_69_n672) );
XOR2X1TS U3513 ( .A(FPMULT_Op_MX[11]), .B(n2695), .Y(mult_x_69_n698) );
AOI21X1TS U3514 ( .A0(n2325), .A1(n2697), .B0(n2696), .Y(n2698) );
XOR2X1TS U3515 ( .A(n3027), .B(n2698), .Y(mult_x_69_n699) );
XOR2X1TS U3516 ( .A(FPMULT_Op_MX[8]), .B(n2699), .Y(mult_x_69_n725) );
AOI21X1TS U3517 ( .A0(n2325), .A1(n2701), .B0(n2700), .Y(n2702) );
XOR2X1TS U3518 ( .A(n2365), .B(n2702), .Y(mult_x_69_n726) );
XOR2X1TS U3519 ( .A(FPMULT_Op_MX[5]), .B(n2703), .Y(mult_x_69_n752) );
XOR2X1TS U3520 ( .A(n2707), .B(n2706), .Y(mult_x_69_n753) );
OAI22X1TS U3521 ( .A0(n2759), .A1(n2962), .B0(n2246), .B1(n3053), .Y(n2710)
);
OAI22X1TS U3522 ( .A0(n2259), .A1(mult_x_69_n272), .B0(n2752), .B1(n2208),
.Y(n2709) );
OAI31X1TS U3523 ( .A0(n2710), .A1(n2373), .A2(n2709), .B0(n2708), .Y(
mult_x_69_n769) );
OAI22X1TS U3524 ( .A0(n2759), .A1(n2973), .B0(n2259), .B1(n3053), .Y(n2713)
);
OAI22X1TS U3525 ( .A0(n2246), .A1(n2974), .B0(n2752), .B1(mult_x_69_n272),
.Y(n2712) );
OAI31X1TS U3526 ( .A0(n2713), .A1(n2373), .A2(n2712), .B0(n2711), .Y(
mult_x_69_n768) );
OAI22X1TS U3527 ( .A0(n2759), .A1(n2946), .B0(n2752), .B1(n2945), .Y(n2716)
);
OAI22X1TS U3528 ( .A0(n2246), .A1(mult_x_69_n272), .B0(n2259), .B1(n2208),
.Y(n2715) );
OAI31X1TS U3529 ( .A0(n2716), .A1(n2373), .A2(n2715), .B0(n2714), .Y(
mult_x_69_n770) );
OAI22X1TS U3530 ( .A0(n2759), .A1(n3058), .B0(n2259), .B1(n3071), .Y(n2719)
);
OAI22X1TS U3531 ( .A0(n2246), .A1(n3074), .B0(n2752), .B1(n2313), .Y(n2718)
);
OAI31X1TS U3532 ( .A0(n2719), .A1(n2373), .A2(n2718), .B0(n2717), .Y(
mult_x_69_n766) );
OAI22X1TS U3533 ( .A0(n2759), .A1(n2930), .B0(n2752), .B1(n2205), .Y(n2723)
);
OAI22X1TS U3534 ( .A0(n2245), .A1(n2208), .B0(n2258), .B1(n2945), .Y(n2722)
);
OAI31X1TS U3535 ( .A0(n2723), .A1(n2373), .A2(n2722), .B0(n2721), .Y(
mult_x_69_n771) );
OAI22X1TS U3536 ( .A0(n2759), .A1(n3073), .B0(n2752), .B1(n3071), .Y(n2726)
);
OAI22X1TS U3537 ( .A0(n2246), .A1(n2213), .B0(n2259), .B1(n3074), .Y(n2725)
);
OAI31X1TS U3538 ( .A0(n2726), .A1(n2707), .A2(n2725), .B0(n2724), .Y(
mult_x_69_n765) );
OAI22X1TS U3539 ( .A0(n2759), .A1(n3054), .B0(n2752), .B1(n2210), .Y(n2729)
);
OAI22X1TS U3540 ( .A0(n2246), .A1(n3071), .B0(n2259), .B1(n2974), .Y(n2728)
);
OAI31X1TS U3541 ( .A0(n2729), .A1(n2373), .A2(n2728), .B0(n2727), .Y(
mult_x_69_n767) );
OAI22X1TS U3542 ( .A0(n2759), .A1(n2984), .B0(n2752), .B1(n3074), .Y(n2732)
);
OAI22X1TS U3543 ( .A0(n2246), .A1(mult_x_69_n220), .B0(n2259), .B1(n2271),
.Y(n2731) );
OAI31X1TS U3544 ( .A0(n2732), .A1(n2707), .A2(n2731), .B0(n2730), .Y(
mult_x_69_n764) );
OAI22X1TS U3545 ( .A0(n2759), .A1(n2988), .B0(n2246), .B1(n3047), .Y(n2735)
);
OAI22X1TS U3546 ( .A0(n2259), .A1(mult_x_69_n220), .B0(n2752), .B1(n2213),
.Y(n2734) );
OAI31X1TS U3547 ( .A0(n2735), .A1(n2707), .A2(n2734), .B0(n2733), .Y(
mult_x_69_n763) );
OAI22X1TS U3548 ( .A0(n2759), .A1(n3043), .B0(n2259), .B1(n3047), .Y(n2738)
);
OAI22X1TS U3549 ( .A0(n2246), .A1(n3049), .B0(n2745), .B1(mult_x_69_n220),
.Y(n2737) );
OAI31X1TS U3550 ( .A0(n2738), .A1(n2707), .A2(n2737), .B0(n2736), .Y(
mult_x_69_n762) );
OAI22X1TS U3551 ( .A0(n2759), .A1(n3048), .B0(n2745), .B1(n3047), .Y(n2741)
);
OAI22X1TS U3552 ( .A0(n2246), .A1(n2217), .B0(n2259), .B1(n3049), .Y(n2740)
);
OAI31X1TS U3553 ( .A0(n2741), .A1(n2707), .A2(n2740), .B0(n2739), .Y(
mult_x_69_n761) );
OAI22X1TS U3554 ( .A0(n2759), .A1(n3078), .B0(n2259), .B1(n2217), .Y(n2744)
);
OAI22X1TS U3555 ( .A0(n2246), .A1(n2219), .B0(n2745), .B1(n3049), .Y(n2743)
);
OAI31X1TS U3556 ( .A0(n2744), .A1(n2707), .A2(n2743), .B0(n2742), .Y(
mult_x_69_n760) );
OAI22X1TS U3557 ( .A0(n2304), .A1(n3083), .B0(n2745), .B1(n2217), .Y(n2748)
);
OAI22X1TS U3558 ( .A0(n2246), .A1(n4595), .B0(n2259), .B1(n2219), .Y(n2747)
);
OAI31X1TS U3559 ( .A0(n2748), .A1(n2373), .A2(n2747), .B0(n2746), .Y(
mult_x_69_n759) );
OAI22X1TS U3560 ( .A0(n2304), .A1(n3007), .B0(n2745), .B1(n2251), .Y(n2751)
);
OAI22X1TS U3561 ( .A0(n2246), .A1(n2218), .B0(n2259), .B1(n4595), .Y(n2750)
);
OAI31X1TS U3562 ( .A0(n2751), .A1(n2373), .A2(n2750), .B0(n2749), .Y(
mult_x_69_n758) );
OAI22X1TS U3563 ( .A0(n3020), .A1(n2259), .B0(n2752), .B1(n2223), .Y(n2754)
);
OAI31X1TS U3564 ( .A0(n2755), .A1(n2373), .A2(n2754), .B0(n2753), .Y(
mult_x_69_n755) );
OAI22X1TS U3565 ( .A0(n2304), .A1(n3011), .B0(n2259), .B1(n2218), .Y(n2758)
);
OAI22X1TS U3566 ( .A0(n2246), .A1(n2223), .B0(n2745), .B1(n4595), .Y(n2757)
);
OAI31X1TS U3567 ( .A0(n2758), .A1(n2373), .A2(n2757), .B0(n2756), .Y(
mult_x_69_n757) );
OAI22X1TS U3568 ( .A0(n2304), .A1(n3015), .B0(n2745), .B1(n2218), .Y(n2762)
);
OAI22X1TS U3569 ( .A0(n3020), .A1(n2246), .B0(n2259), .B1(n2223), .Y(n2761)
);
OAI31X1TS U3570 ( .A0(n2762), .A1(n2373), .A2(n2761), .B0(n2760), .Y(
mult_x_69_n756) );
OAI22X1TS U3571 ( .A0(n2366), .A1(n2938), .B0(n3116), .B1(n2207), .Y(n2765)
);
OAI22X1TS U3572 ( .A0(n2243), .A1(n2260), .B0(n2255), .B1(n2257), .Y(n2764)
);
OAI31X1TS U3573 ( .A0(n2765), .A1(n4596), .A2(n2764), .B0(n2763), .Y(
mult_x_69_n746) );
OAI22X1TS U3574 ( .A0(n2366), .A1(n2934), .B0(n3116), .B1(n2257), .Y(n2768)
);
OAI22X1TS U3575 ( .A0(n2243), .A1(n2945), .B0(n2255), .B1(n2260), .Y(n2767)
);
OAI31X1TS U3576 ( .A0(n2768), .A1(n4596), .A2(n2767), .B0(n2766), .Y(
mult_x_69_n745) );
OAI22X1TS U3577 ( .A0(n2366), .A1(n2930), .B0(n3116), .B1(n2260), .Y(n2771)
);
OAI22X1TS U3578 ( .A0(n2243), .A1(n2208), .B0(n2255), .B1(n2209), .Y(n2770)
);
OAI31X1TS U3579 ( .A0(n2771), .A1(n4596), .A2(n2770), .B0(n2769), .Y(
mult_x_69_n744) );
OAI22X1TS U3580 ( .A0(n2366), .A1(n2962), .B0(n2244), .B1(n3053), .Y(n2774)
);
OAI22X1TS U3581 ( .A0(n2256), .A1(n2211), .B0(n3116), .B1(n2272), .Y(n2773)
);
OAI31X1TS U3582 ( .A0(n2774), .A1(n4596), .A2(n2773), .B0(n2772), .Y(
mult_x_69_n742) );
OAI22X1TS U3583 ( .A0(n2366), .A1(n2973), .B0(n2256), .B1(n2210), .Y(n2777)
);
OAI22X1TS U3584 ( .A0(n2244), .A1(n2974), .B0(n3116), .B1(n2211), .Y(n2776)
);
OAI31X1TS U3585 ( .A0(n2777), .A1(n4596), .A2(n2776), .B0(n2775), .Y(
mult_x_69_n741) );
OAI22X1TS U3586 ( .A0(n2366), .A1(n2946), .B0(n3116), .B1(n2209), .Y(n2780)
);
OAI22X1TS U3587 ( .A0(n2244), .A1(mult_x_69_n272), .B0(n2256), .B1(n2272),
.Y(n2779) );
OAI31X1TS U3588 ( .A0(n2780), .A1(n4596), .A2(n2779), .B0(n2778), .Y(
mult_x_69_n743) );
OAI22X1TS U3589 ( .A0(n2366), .A1(n3054), .B0(n3116), .B1(n2210), .Y(n2783)
);
OAI22X1TS U3590 ( .A0(n2244), .A1(n3071), .B0(n2256), .B1(n2974), .Y(n2782)
);
OAI31X1TS U3591 ( .A0(n2783), .A1(n4596), .A2(n2782), .B0(n2781), .Y(
mult_x_69_n740) );
OAI22X1TS U3592 ( .A0(n2366), .A1(n3058), .B0(n2256), .B1(n2212), .Y(n2786)
);
OAI22X1TS U3593 ( .A0(n2244), .A1(n3074), .B0(n3116), .B1(n2974), .Y(n2785)
);
OAI31X1TS U3594 ( .A0(n2786), .A1(n4596), .A2(n2785), .B0(n2784), .Y(
mult_x_69_n739) );
OAI22X1TS U3595 ( .A0(n2366), .A1(n3073), .B0(n3116), .B1(n2212), .Y(n2789)
);
OAI22X1TS U3596 ( .A0(n2244), .A1(n2213), .B0(n2256), .B1(n2214), .Y(n2788)
);
OAI31X1TS U3597 ( .A0(n2789), .A1(n4596), .A2(n2788), .B0(n2787), .Y(
mult_x_69_n738) );
OAI22X1TS U3598 ( .A0(n2366), .A1(n2984), .B0(n3116), .B1(n2214), .Y(n2792)
);
OAI22X1TS U3599 ( .A0(n2244), .A1(mult_x_69_n220), .B0(n2256), .B1(n2271),
.Y(n2791) );
OAI31X1TS U3600 ( .A0(n2792), .A1(n4596), .A2(n2791), .B0(n2790), .Y(
mult_x_69_n737) );
OAI22X1TS U3601 ( .A0(n2366), .A1(n2988), .B0(n2244), .B1(n3047), .Y(n2795)
);
OAI22X1TS U3602 ( .A0(n2256), .A1(n2215), .B0(n3116), .B1(n2271), .Y(n2794)
);
OAI31X1TS U3603 ( .A0(n2795), .A1(n4596), .A2(n2794), .B0(n2793), .Y(
mult_x_69_n736) );
OAI22X1TS U3604 ( .A0(n2366), .A1(n3043), .B0(n2256), .B1(n2216), .Y(n2798)
);
OAI22X1TS U3605 ( .A0(n2244), .A1(n3049), .B0(n2446), .B1(n2215), .Y(n2797)
);
OAI31X1TS U3606 ( .A0(n2798), .A1(n2365), .A2(n2797), .B0(n2796), .Y(
mult_x_69_n735) );
OAI22X1TS U3607 ( .A0(n2358), .A1(n2930), .B0(n3024), .B1(n2260), .Y(n2802)
);
OAI22X1TS U3608 ( .A0(n2249), .A1(n2272), .B0(n2267), .B1(n2209), .Y(n2801)
);
OAI31X1TS U3609 ( .A0(n2802), .A1(n2799), .A2(n2801), .B0(n2800), .Y(
mult_x_69_n717) );
OAI22X1TS U3610 ( .A0(n2303), .A1(n3007), .B0(n2446), .B1(n2251), .Y(n2805)
);
OAI22X1TS U3611 ( .A0(n2244), .A1(n2254), .B0(n2256), .B1(n4595), .Y(n2804)
);
OAI31X1TS U3612 ( .A0(n2805), .A1(n2365), .A2(n2804), .B0(n2803), .Y(
mult_x_69_n731) );
OAI22X1TS U3613 ( .A0(n2366), .A1(n3048), .B0(n2446), .B1(n2216), .Y(n2808)
);
OAI22X1TS U3614 ( .A0(n2244), .A1(n2217), .B0(n2256), .B1(n3049), .Y(n2807)
);
OAI31X1TS U3615 ( .A0(n2808), .A1(n2365), .A2(n2807), .B0(n2806), .Y(
mult_x_69_n734) );
OAI22X1TS U3616 ( .A0(n2358), .A1(n2946), .B0(n3024), .B1(n2209), .Y(n2811)
);
OAI22X1TS U3617 ( .A0(n2250), .A1(mult_x_69_n272), .B0(n2268), .B1(n2272),
.Y(n2810) );
OAI31X1TS U3618 ( .A0(n2811), .A1(n2799), .A2(n2810), .B0(n2809), .Y(
mult_x_69_n716) );
OAI22X1TS U3619 ( .A0(n2366), .A1(n3078), .B0(n2256), .B1(n2253), .Y(n2814)
);
OAI22X1TS U3620 ( .A0(n2244), .A1(n2219), .B0(n2446), .B1(n3049), .Y(n2813)
);
OAI31X1TS U3621 ( .A0(n2814), .A1(n2365), .A2(n2813), .B0(n2812), .Y(
mult_x_69_n733) );
OAI22X1TS U3622 ( .A0(n2358), .A1(n2962), .B0(n2250), .B1(n3053), .Y(n2817)
);
OAI22X1TS U3623 ( .A0(n2268), .A1(n2211), .B0(n3024), .B1(n2272), .Y(n2816)
);
OAI31X1TS U3624 ( .A0(n2817), .A1(n2799), .A2(n2816), .B0(n2815), .Y(
mult_x_69_n715) );
OAI22X1TS U3625 ( .A0(n2303), .A1(n3011), .B0(n2256), .B1(n2254), .Y(n2820)
);
OAI22X1TS U3626 ( .A0(n2244), .A1(n2223), .B0(n3116), .B1(n4595), .Y(n2819)
);
OAI31X1TS U3627 ( .A0(n2820), .A1(n4596), .A2(n2819), .B0(n2818), .Y(
mult_x_69_n730) );
OAI22X1TS U3628 ( .A0(n2303), .A1(n3083), .B0(n2446), .B1(n2253), .Y(n2823)
);
OAI22X1TS U3629 ( .A0(n2244), .A1(n4595), .B0(n2256), .B1(n2251), .Y(n2822)
);
OAI31X1TS U3630 ( .A0(n2823), .A1(n2365), .A2(n2822), .B0(n2821), .Y(
mult_x_69_n732) );
OAI22X1TS U3631 ( .A0(n2358), .A1(n3054), .B0(n3024), .B1(n2210), .Y(n2826)
);
OAI22X1TS U3632 ( .A0(n2250), .A1(n2212), .B0(n2268), .B1(n2313), .Y(n2825)
);
OAI31X1TS U3633 ( .A0(n2826), .A1(n2356), .A2(n2825), .B0(n2824), .Y(
mult_x_69_n713) );
OAI22X1TS U3634 ( .A0(n2358), .A1(n2973), .B0(n2268), .B1(n2210), .Y(n2829)
);
OAI22X1TS U3635 ( .A0(n2250), .A1(n2974), .B0(n3024), .B1(n2211), .Y(n2828)
);
OAI31X1TS U3636 ( .A0(n2829), .A1(n2799), .A2(n2828), .B0(n2827), .Y(
mult_x_69_n714) );
OAI22X1TS U3637 ( .A0(n2358), .A1(n3058), .B0(n2268), .B1(n2212), .Y(n2832)
);
OAI22X1TS U3638 ( .A0(n2250), .A1(n2214), .B0(n2845), .B1(n2974), .Y(n2831)
);
OAI31X1TS U3639 ( .A0(n2832), .A1(n2356), .A2(n2831), .B0(n2830), .Y(
mult_x_69_n712) );
OAI22X1TS U3640 ( .A0(n2358), .A1(n3073), .B0(n2845), .B1(n2212), .Y(n2835)
);
OAI22X1TS U3641 ( .A0(n2250), .A1(n2271), .B0(n2268), .B1(n2214), .Y(n2834)
);
OAI31X1TS U3642 ( .A0(n2835), .A1(n3027), .A2(n2834), .B0(n2833), .Y(
mult_x_69_n711) );
OAI22X1TS U3643 ( .A0(n2303), .A1(n3015), .B0(n3116), .B1(n2254), .Y(n2838)
);
OAI22X1TS U3644 ( .A0(n3020), .A1(n2244), .B0(n2256), .B1(n2252), .Y(n2837)
);
OAI31X1TS U3645 ( .A0(n2838), .A1(n4596), .A2(n2837), .B0(n2836), .Y(
mult_x_69_n729) );
OAI22X1TS U3646 ( .A0(n2358), .A1(n3048), .B0(n3024), .B1(n2216), .Y(n2841)
);
OAI22X1TS U3647 ( .A0(n2250), .A1(n2253), .B0(n2268), .B1(n3049), .Y(n2840)
);
OAI31X1TS U3648 ( .A0(n2841), .A1(n3027), .A2(n2840), .B0(n2839), .Y(
mult_x_69_n707) );
OAI22X1TS U3649 ( .A0(n2224), .A1(n2244), .B0(n2303), .B1(n3019), .Y(n2844)
);
OAI22X1TS U3650 ( .A0(n3020), .A1(n2256), .B0(n3116), .B1(n2252), .Y(n2843)
);
OAI31X1TS U3651 ( .A0(n2844), .A1(n4596), .A2(n2843), .B0(n2842), .Y(
mult_x_69_n728) );
OAI22X1TS U3652 ( .A0(n2358), .A1(n2984), .B0(n2845), .B1(n2214), .Y(n2848)
);
OAI22X1TS U3653 ( .A0(n2250), .A1(mult_x_69_n220), .B0(n2268), .B1(n2271),
.Y(n2847) );
OAI31X1TS U3654 ( .A0(n2848), .A1(n3027), .A2(n2847), .B0(n2846), .Y(
mult_x_69_n710) );
OAI22X1TS U3655 ( .A0(n2358), .A1(n3043), .B0(n2268), .B1(n2216), .Y(n2851)
);
OAI22X1TS U3656 ( .A0(n2250), .A1(n3049), .B0(n3024), .B1(n2215), .Y(n2850)
);
OAI31X1TS U3657 ( .A0(n2851), .A1(n3027), .A2(n2850), .B0(n2849), .Y(
mult_x_69_n708) );
OAI22X1TS U3658 ( .A0(n2358), .A1(n2988), .B0(n2250), .B1(n3047), .Y(n2854)
);
OAI22X1TS U3659 ( .A0(n2268), .A1(n2215), .B0(n3024), .B1(n2271), .Y(n2853)
);
OAI31X1TS U3660 ( .A0(n2854), .A1(n3027), .A2(n2853), .B0(n2852), .Y(
mult_x_69_n709) );
AOI21X1TS U3661 ( .A0(FPMULT_Op_MX[0]), .A1(n2325), .B0(FPMULT_Op_MX[1]),
.Y(n2856) );
OAI32X1TS U3662 ( .A0(n2202), .A1(n2201), .A2(n2325), .B0(n2856), .B1(n2855),
.Y(mult_x_69_n779) );
OAI22X1TS U3663 ( .A0(n2277), .A1(n2938), .B0(n2893), .B1(n3118), .Y(n2859)
);
OAI22X1TS U3664 ( .A0(n3037), .A1(n2260), .B0(n2265), .B1(n2257), .Y(n2858)
);
OAI31X1TS U3665 ( .A0(n2859), .A1(n3041), .A2(n2858), .B0(n2857), .Y(
mult_x_69_n692) );
OAI22X1TS U3666 ( .A0(n2349), .A1(n3117), .B0(n2893), .B1(n2204), .Y(n2862)
);
OAI22X1TS U3667 ( .A0(n3037), .A1(n2257), .B0(n2265), .B1(n2207), .Y(n2861)
);
OAI31X1TS U3668 ( .A0(n2862), .A1(n3041), .A2(n2861), .B0(n2860), .Y(
mult_x_69_n693) );
OAI22X1TS U3669 ( .A0(n2277), .A1(n2934), .B0(n2893), .B1(n2257), .Y(n2865)
);
OAI22X1TS U3670 ( .A0(n3037), .A1(n2209), .B0(n2265), .B1(n2260), .Y(n2864)
);
OAI31X1TS U3671 ( .A0(n2865), .A1(n2320), .A2(n2864), .B0(n2863), .Y(
mult_x_69_n691) );
OAI22X1TS U3672 ( .A0(n2277), .A1(n2930), .B0(n2893), .B1(n2260), .Y(n2868)
);
OAI22X1TS U3673 ( .A0(n3037), .A1(n2272), .B0(n2266), .B1(n2209), .Y(n2867)
);
OAI31X1TS U3674 ( .A0(n2868), .A1(n2320), .A2(n2867), .B0(n2866), .Y(
mult_x_69_n690) );
OAI22X1TS U3675 ( .A0(n2277), .A1(n2946), .B0(n2893), .B1(n2945), .Y(n2871)
);
OAI22X1TS U3676 ( .A0(n3037), .A1(n2211), .B0(n2266), .B1(n2272), .Y(n2870)
);
OAI31X1TS U3677 ( .A0(n2871), .A1(n2320), .A2(n2870), .B0(n2869), .Y(
mult_x_69_n689) );
OAI22X1TS U3678 ( .A0(n2277), .A1(n2962), .B0(n3037), .B1(n2210), .Y(n2874)
);
OAI22X1TS U3679 ( .A0(n2266), .A1(n2211), .B0(n2893), .B1(n2272), .Y(n2873)
);
OAI31X1TS U3680 ( .A0(n2874), .A1(n2320), .A2(n2873), .B0(n2872), .Y(
mult_x_69_n688) );
OAI22X1TS U3681 ( .A0(n2277), .A1(n2973), .B0(n2266), .B1(n2210), .Y(n2877)
);
OAI22X1TS U3682 ( .A0(n3037), .A1(n2974), .B0(n2893), .B1(n2211), .Y(n2876)
);
OAI31X1TS U3683 ( .A0(n2877), .A1(n2320), .A2(n2876), .B0(n2875), .Y(
mult_x_69_n687) );
OAI22X1TS U3684 ( .A0(n2277), .A1(n3073), .B0(n2893), .B1(n2212), .Y(n2880)
);
OAI22X1TS U3685 ( .A0(n3037), .A1(n2271), .B0(n2266), .B1(n2214), .Y(n2879)
);
OAI31X1TS U3686 ( .A0(n2880), .A1(n3038), .A2(n2879), .B0(n2878), .Y(
mult_x_69_n684) );
OAI22X1TS U3687 ( .A0(n2277), .A1(n3058), .B0(n2266), .B1(n2212), .Y(n2883)
);
OAI22X1TS U3688 ( .A0(n3037), .A1(n2214), .B0(n2893), .B1(n2974), .Y(n2882)
);
OAI31X1TS U3689 ( .A0(n2883), .A1(n3038), .A2(n2882), .B0(n2881), .Y(
mult_x_69_n685) );
OAI22X1TS U3690 ( .A0(n2277), .A1(n3054), .B0(n2893), .B1(n3053), .Y(n2886)
);
OAI22X1TS U3691 ( .A0(n3037), .A1(n2212), .B0(n2266), .B1(n2974), .Y(n2885)
);
OAI31X1TS U3692 ( .A0(n2886), .A1(n3038), .A2(n2885), .B0(n2884), .Y(
mult_x_69_n686) );
OAI22X1TS U3693 ( .A0(n2302), .A1(n3083), .B0(n3024), .B1(n2253), .Y(n2889)
);
OAI22X1TS U3694 ( .A0(n2250), .A1(n4595), .B0(n2268), .B1(n2251), .Y(n2888)
);
OAI31X1TS U3695 ( .A0(n2889), .A1(n3027), .A2(n2888), .B0(n2887), .Y(
mult_x_69_n705) );
OAI22X1TS U3696 ( .A0(n2302), .A1(n3007), .B0(n3024), .B1(n2251), .Y(n2892)
);
OAI22X1TS U3697 ( .A0(n2250), .A1(n2254), .B0(n2268), .B1(n4595), .Y(n2891)
);
OAI31X1TS U3698 ( .A0(n2892), .A1(n3027), .A2(n2891), .B0(n2890), .Y(
mult_x_69_n704) );
OAI22X1TS U3699 ( .A0(n2277), .A1(n2984), .B0(n2893), .B1(n3074), .Y(n2896)
);
OAI22X1TS U3700 ( .A0(n3037), .A1(n2215), .B0(n2266), .B1(n2271), .Y(n2895)
);
OAI31X1TS U3701 ( .A0(n2896), .A1(n3041), .A2(n2895), .B0(n2894), .Y(
mult_x_69_n683) );
OAI22X1TS U3702 ( .A0(n2302), .A1(n3011), .B0(n2268), .B1(n2254), .Y(n2899)
);
OAI22X1TS U3703 ( .A0(n2250), .A1(n2252), .B0(n3024), .B1(n4595), .Y(n2898)
);
OAI31X1TS U3704 ( .A0(n2899), .A1(n2356), .A2(n2898), .B0(n2897), .Y(
mult_x_69_n703) );
OAI22X1TS U3705 ( .A0(n2277), .A1(n2988), .B0(n3037), .B1(n2216), .Y(n2902)
);
OAI22X1TS U3706 ( .A0(n2266), .A1(n2215), .B0(n3036), .B1(n2271), .Y(n2901)
);
OAI31X1TS U3707 ( .A0(n2902), .A1(n3041), .A2(n2901), .B0(n2900), .Y(
mult_x_69_n682) );
OAI22X1TS U3708 ( .A0(n2341), .A1(n3054), .B0(n3065), .B1(n3053), .Y(n2905)
);
OAI22X1TS U3709 ( .A0(n2248), .A1(n2212), .B0(n2264), .B1(n2974), .Y(n2904)
);
OAI31X1TS U3710 ( .A0(n2905), .A1(n2318), .A2(n2904), .B0(n2903), .Y(
mult_x_69_n659) );
OAI22X1TS U3711 ( .A0(n2302), .A1(n3015), .B0(n3024), .B1(n2254), .Y(n2908)
);
OAI22X1TS U3712 ( .A0(n3020), .A1(n2250), .B0(n2268), .B1(n2252), .Y(n2907)
);
OAI31X1TS U3713 ( .A0(n2908), .A1(n2799), .A2(n2907), .B0(n2906), .Y(
mult_x_69_n702) );
OAI22X1TS U3714 ( .A0(n2341), .A1(n2930), .B0(n3065), .B1(n2260), .Y(n2911)
);
OAI22X1TS U3715 ( .A0(n2247), .A1(n2272), .B0(n2263), .B1(n2209), .Y(n2910)
);
OAI31X1TS U3716 ( .A0(n2911), .A1(n2318), .A2(n2910), .B0(n2909), .Y(
mult_x_69_n663) );
OAI22X1TS U3717 ( .A0(n2341), .A1(n2973), .B0(n2264), .B1(n3053), .Y(n2914)
);
OAI22X1TS U3718 ( .A0(n2248), .A1(n2974), .B0(n3065), .B1(mult_x_69_n272),
.Y(n2913) );
OAI31X1TS U3719 ( .A0(n2914), .A1(n2318), .A2(n2913), .B0(n2912), .Y(
mult_x_69_n660) );
OAI22X1TS U3720 ( .A0(n2341), .A1(n2962), .B0(n2248), .B1(n2210), .Y(n2917)
);
OAI22X1TS U3721 ( .A0(n2264), .A1(n2211), .B0(n3065), .B1(n2272), .Y(n2916)
);
OAI31X1TS U3722 ( .A0(n2917), .A1(n2318), .A2(n2916), .B0(n2915), .Y(
mult_x_69_n661) );
OAI22X1TS U3723 ( .A0(n2341), .A1(n2946), .B0(n3065), .B1(n2945), .Y(n2920)
);
OAI22X1TS U3724 ( .A0(n2248), .A1(n2211), .B0(n2264), .B1(n2272), .Y(n2919)
);
OAI31X1TS U3725 ( .A0(n2920), .A1(n2318), .A2(n2919), .B0(n2918), .Y(
mult_x_69_n662) );
OAI22X1TS U3726 ( .A0(n2277), .A1(n3043), .B0(n2266), .B1(n2216), .Y(n2923)
);
OAI22X1TS U3727 ( .A0(n3037), .A1(n3049), .B0(n3036), .B1(n2215), .Y(n2922)
);
OAI31X1TS U3728 ( .A0(n2923), .A1(n3041), .A2(n2922), .B0(n2921), .Y(
mult_x_69_n681) );
OAI22X1TS U3729 ( .A0(n2224), .A1(n2250), .B0(n2302), .B1(n3019), .Y(n2926)
);
OAI22X1TS U3730 ( .A0(n3020), .A1(n2268), .B0(n3024), .B1(n2252), .Y(n2925)
);
OAI31X1TS U3731 ( .A0(n2926), .A1(n2799), .A2(n2925), .B0(n2924), .Y(
mult_x_69_n701) );
OAI22X1TS U3732 ( .A0(n2277), .A1(n3048), .B0(n3036), .B1(n2216), .Y(n2929)
);
OAI22X1TS U3733 ( .A0(n3037), .A1(n2253), .B0(n2266), .B1(n3049), .Y(n2928)
);
OAI31X1TS U3734 ( .A0(n2929), .A1(n3041), .A2(n2928), .B0(n2927), .Y(
mult_x_69_n680) );
OAI22X1TS U3735 ( .A0(n2275), .A1(n2930), .B0(n3082), .B1(n2260), .Y(n2933)
);
OAI22X1TS U3736 ( .A0(n3084), .A1(n2272), .B0(n2262), .B1(n2945), .Y(n2932)
);
OAI31X1TS U3737 ( .A0(n2933), .A1(n3085), .A2(n2932), .B0(n2931), .Y(
mult_x_69_n636) );
OAI22X1TS U3738 ( .A0(n2275), .A1(n2934), .B0(n3082), .B1(n2257), .Y(n2937)
);
OAI22X1TS U3739 ( .A0(n3084), .A1(n2945), .B0(n2261), .B1(n2260), .Y(n2936)
);
OAI31X1TS U3740 ( .A0(n2937), .A1(n3085), .A2(n2936), .B0(n2935), .Y(
mult_x_69_n637) );
OAI22X1TS U3741 ( .A0(n2275), .A1(n2938), .B0(n3072), .B1(n3118), .Y(n2941)
);
OAI22X1TS U3742 ( .A0(n3084), .A1(n2260), .B0(n2261), .B1(n2257), .Y(n2940)
);
OAI31X1TS U3743 ( .A0(n2941), .A1(n3085), .A2(n2940), .B0(n2939), .Y(
mult_x_69_n638) );
OAI22X1TS U3744 ( .A0(n2333), .A1(n3117), .B0(n3072), .B1(n2204), .Y(n2944)
);
OAI22X1TS U3745 ( .A0(n3084), .A1(n2257), .B0(n2261), .B1(n3118), .Y(n2943)
);
OAI31X1TS U3746 ( .A0(n2944), .A1(n3088), .A2(n2943), .B0(n2942), .Y(
mult_x_69_n639) );
OAI22X1TS U3747 ( .A0(n2275), .A1(n2946), .B0(n3082), .B1(n2945), .Y(n2949)
);
OAI22X1TS U3748 ( .A0(n3084), .A1(mult_x_69_n272), .B0(n2262), .B1(n2272),
.Y(n2948) );
OAI31X1TS U3749 ( .A0(n2949), .A1(n3088), .A2(n2948), .B0(n2947), .Y(
mult_x_69_n635) );
OAI22X1TS U3750 ( .A0(n2341), .A1(n3073), .B0(n3032), .B1(n3071), .Y(n2952)
);
OAI22X1TS U3751 ( .A0(n2248), .A1(n2271), .B0(n2264), .B1(n3074), .Y(n2951)
);
OAI31X1TS U3752 ( .A0(n2952), .A1(n3069), .A2(n2951), .B0(n2950), .Y(
mult_x_69_n657) );
OAI22X1TS U3753 ( .A0(n2277), .A1(n3007), .B0(n3036), .B1(n2251), .Y(n2955)
);
OAI22X1TS U3754 ( .A0(n3037), .A1(n2254), .B0(n2266), .B1(n4595), .Y(n2954)
);
OAI31X1TS U3755 ( .A0(n2955), .A1(n3041), .A2(n2954), .B0(n2953), .Y(
mult_x_69_n677) );
OAI22X1TS U3756 ( .A0(n2341), .A1(n2984), .B0(n3032), .B1(n3074), .Y(n2958)
);
OAI22X1TS U3757 ( .A0(n2248), .A1(n2215), .B0(n2264), .B1(n2271), .Y(n2957)
);
OAI31X1TS U3758 ( .A0(n2958), .A1(n3069), .A2(n2957), .B0(n2956), .Y(
mult_x_69_n656) );
OAI22X1TS U3759 ( .A0(n2341), .A1(n2988), .B0(n2248), .B1(n2216), .Y(n2961)
);
OAI22X1TS U3760 ( .A0(n2264), .A1(mult_x_69_n220), .B0(n3065), .B1(n2271),
.Y(n2960) );
OAI31X1TS U3761 ( .A0(n2961), .A1(n3069), .A2(n2960), .B0(n2959), .Y(
mult_x_69_n655) );
OAI22X1TS U3762 ( .A0(n2275), .A1(n2962), .B0(n3084), .B1(n3053), .Y(n2965)
);
OAI22X1TS U3763 ( .A0(n2262), .A1(mult_x_69_n272), .B0(n3082), .B1(n2272),
.Y(n2964) );
OAI31X1TS U3764 ( .A0(n2965), .A1(n3088), .A2(n2964), .B0(n2963), .Y(
mult_x_69_n634) );
OAI22X1TS U3765 ( .A0(n2277), .A1(n3011), .B0(n2266), .B1(n2254), .Y(n2968)
);
OAI22X1TS U3766 ( .A0(n3037), .A1(n2252), .B0(n3036), .B1(n4595), .Y(n2967)
);
OAI31X1TS U3767 ( .A0(n2968), .A1(n2348), .A2(n2967), .B0(n2966), .Y(
mult_x_69_n676) );
ADDHXLTS U3768 ( .A(FPMULT_Op_MX[17]), .B(n2969), .CO(n3097), .S(
mult_x_69_n435) );
OAI22X1TS U3769 ( .A0(n2277), .A1(n3015), .B0(n3036), .B1(n2254), .Y(n2972)
);
OAI22X1TS U3770 ( .A0(n3020), .A1(n3037), .B0(n2266), .B1(n2252), .Y(n2971)
);
OAI31X1TS U3771 ( .A0(n2972), .A1(n2348), .A2(n2971), .B0(n2970), .Y(
mult_x_69_n675) );
OAI22X1TS U3772 ( .A0(n2275), .A1(n2973), .B0(n2262), .B1(n3053), .Y(n2977)
);
OAI22X1TS U3773 ( .A0(n3084), .A1(n2974), .B0(n3082), .B1(mult_x_69_n272),
.Y(n2976) );
OAI31X1TS U3774 ( .A0(n2977), .A1(n3088), .A2(n2976), .B0(n2975), .Y(
mult_x_69_n633) );
OAI22X1TS U3775 ( .A0(n2277), .A1(n3019), .B0(n3036), .B1(n2252), .Y(n2980)
);
OAI22X1TS U3776 ( .A0(n2224), .A1(n3037), .B0(n3020), .B1(n2266), .Y(n2979)
);
OAI31X1TS U3777 ( .A0(n2980), .A1(n2348), .A2(n2979), .B0(n2978), .Y(
mult_x_69_n674) );
OAI22X1TS U3778 ( .A0(n2301), .A1(n3007), .B0(n3065), .B1(n2251), .Y(n2983)
);
OAI22X1TS U3779 ( .A0(n2248), .A1(n2254), .B0(n2264), .B1(n4595), .Y(n2982)
);
OAI31X1TS U3780 ( .A0(n2983), .A1(n3069), .A2(n2982), .B0(n2981), .Y(
mult_x_69_n650) );
OAI22X1TS U3781 ( .A0(n2275), .A1(n2984), .B0(n3072), .B1(n3074), .Y(n2987)
);
OAI22X1TS U3782 ( .A0(n3084), .A1(mult_x_69_n220), .B0(n2262), .B1(n2271),
.Y(n2986) );
OAI31X1TS U3783 ( .A0(n2987), .A1(n3088), .A2(n2986), .B0(n2985), .Y(
mult_x_69_n629) );
OAI22X1TS U3784 ( .A0(n2275), .A1(n2988), .B0(n3084), .B1(n3047), .Y(n2991)
);
OAI22X1TS U3785 ( .A0(n2262), .A1(mult_x_69_n220), .B0(n3082), .B1(n2271),
.Y(n2990) );
OAI31X1TS U3786 ( .A0(n2991), .A1(n3088), .A2(n2990), .B0(n2989), .Y(
mult_x_69_n628) );
OAI22X1TS U3787 ( .A0(n2301), .A1(n3011), .B0(n2264), .B1(n2254), .Y(n2994)
);
OAI22X1TS U3788 ( .A0(n2248), .A1(n2252), .B0(n3065), .B1(n2312), .Y(n2993)
);
OAI31X1TS U3789 ( .A0(n2994), .A1(n2318), .A2(n2993), .B0(n2992), .Y(
mult_x_69_n649) );
OAI22X1TS U3790 ( .A0(n2301), .A1(n3015), .B0(n3065), .B1(n2254), .Y(n2997)
);
OAI22X1TS U3791 ( .A0(n3020), .A1(n2248), .B0(n2264), .B1(n2252), .Y(n2996)
);
OAI31X1TS U3792 ( .A0(n2997), .A1(n2524), .A2(n2996), .B0(n2995), .Y(
mult_x_69_n648) );
OAI22X1TS U3793 ( .A0(n2275), .A1(n3043), .B0(n2262), .B1(n3047), .Y(n3000)
);
OAI22X1TS U3794 ( .A0(n3084), .A1(n3049), .B0(n3082), .B1(mult_x_69_n220),
.Y(n2999) );
OAI31X1TS U3795 ( .A0(n3000), .A1(n3088), .A2(n2999), .B0(n2998), .Y(
mult_x_69_n627) );
OAI22X1TS U3796 ( .A0(n2301), .A1(n3019), .B0(n3065), .B1(n2252), .Y(n3003)
);
OAI22X1TS U3797 ( .A0(n2224), .A1(n2248), .B0(n3020), .B1(n2264), .Y(n3002)
);
OAI31X1TS U3798 ( .A0(n3003), .A1(n2524), .A2(n3002), .B0(n3001), .Y(
mult_x_69_n647) );
OAI22X1TS U3799 ( .A0(n2275), .A1(n3048), .B0(n3082), .B1(n3047), .Y(n3006)
);
OAI22X1TS U3800 ( .A0(n3084), .A1(n2253), .B0(n2262), .B1(n2315), .Y(n3005)
);
OAI31X1TS U3801 ( .A0(n3006), .A1(n3088), .A2(n3005), .B0(n3004), .Y(
mult_x_69_n626) );
OAI22X1TS U3802 ( .A0(n2275), .A1(n3007), .B0(n3082), .B1(n2251), .Y(n3010)
);
OAI22X1TS U3803 ( .A0(n3084), .A1(n2254), .B0(n2262), .B1(n2312), .Y(n3009)
);
OAI31X1TS U3804 ( .A0(n3010), .A1(n3088), .A2(n3009), .B0(n3008), .Y(
mult_x_69_n623) );
OAI22X1TS U3805 ( .A0(n2275), .A1(n3011), .B0(n2262), .B1(n2254), .Y(n3014)
);
OAI22X1TS U3806 ( .A0(n3084), .A1(n2252), .B0(n3082), .B1(n2312), .Y(n3013)
);
OAI31X1TS U3807 ( .A0(n3014), .A1(n2316), .A2(n3013), .B0(n3012), .Y(
mult_x_69_n622) );
OAI22X1TS U3808 ( .A0(n2275), .A1(n3015), .B0(n3082), .B1(n2254), .Y(n3018)
);
OAI22X1TS U3809 ( .A0(n3020), .A1(n3084), .B0(n2262), .B1(n2252), .Y(n3017)
);
OAI31X1TS U3810 ( .A0(n3018), .A1(n2316), .A2(n3017), .B0(n3016), .Y(
mult_x_69_n621) );
OAI22X1TS U3811 ( .A0(n2275), .A1(n3019), .B0(n3082), .B1(n2252), .Y(n3023)
);
OAI22X1TS U3812 ( .A0(n2224), .A1(n3084), .B0(n3020), .B1(n2262), .Y(n3022)
);
OAI31X1TS U3813 ( .A0(n3023), .A1(n2316), .A2(n3022), .B0(n3021), .Y(
mult_x_69_n620) );
OAI22X1TS U3814 ( .A0(n2358), .A1(n3078), .B0(n2268), .B1(n2253), .Y(n3028)
);
OAI22X1TS U3815 ( .A0(n2250), .A1(n2251), .B0(n3024), .B1(n3049), .Y(n3026)
);
OAI31X1TS U3816 ( .A0(n3028), .A1(n3027), .A2(n3026), .B0(n3025), .Y(
mult_x_69_n706) );
OAI22X1TS U3817 ( .A0(n2277), .A1(n3078), .B0(n2266), .B1(n2253), .Y(n3031)
);
OAI22X1TS U3818 ( .A0(n3037), .A1(n2251), .B0(n3036), .B1(n3049), .Y(n3030)
);
OAI31X1TS U3819 ( .A0(n3031), .A1(n3041), .A2(n3030), .B0(n3029), .Y(
mult_x_69_n679) );
OAI22X1TS U3820 ( .A0(n2341), .A1(n3058), .B0(n2264), .B1(n3071), .Y(n3035)
);
OAI22X1TS U3821 ( .A0(n2248), .A1(n2214), .B0(n3032), .B1(n2313), .Y(n3034)
);
OAI31X1TS U3822 ( .A0(n3035), .A1(n2318), .A2(n3034), .B0(n3033), .Y(
mult_x_69_n658) );
OAI22X1TS U3823 ( .A0(n2277), .A1(n3083), .B0(n3036), .B1(n2253), .Y(n3042)
);
OAI22X1TS U3824 ( .A0(n3037), .A1(n4595), .B0(n2266), .B1(n2251), .Y(n3040)
);
OAI31X1TS U3825 ( .A0(n3042), .A1(n3041), .A2(n3040), .B0(n3039), .Y(
mult_x_69_n678) );
OAI22X1TS U3826 ( .A0(n2341), .A1(n3043), .B0(n2264), .B1(n3047), .Y(n3046)
);
OAI22X1TS U3827 ( .A0(n2248), .A1(n3049), .B0(n3065), .B1(mult_x_69_n220),
.Y(n3045) );
OAI31X1TS U3828 ( .A0(n3046), .A1(n3069), .A2(n3045), .B0(n3044), .Y(
mult_x_69_n654) );
OAI22X1TS U3829 ( .A0(n2341), .A1(n3048), .B0(n3065), .B1(n3047), .Y(n3052)
);
OAI22X1TS U3830 ( .A0(n2248), .A1(n2253), .B0(n2264), .B1(n3049), .Y(n3051)
);
OAI31X1TS U3831 ( .A0(n3052), .A1(n3069), .A2(n3051), .B0(n3050), .Y(
mult_x_69_n653) );
OAI22X1TS U3832 ( .A0(n2275), .A1(n3054), .B0(n3082), .B1(n3053), .Y(n3057)
);
OAI22X1TS U3833 ( .A0(n3084), .A1(n3071), .B0(n2262), .B1(n2313), .Y(n3056)
);
OAI31X1TS U3834 ( .A0(n3057), .A1(n3088), .A2(n3056), .B0(n3055), .Y(
mult_x_69_n632) );
OAI22X1TS U3835 ( .A0(n2275), .A1(n3058), .B0(n2262), .B1(n3071), .Y(n3061)
);
OAI22X1TS U3836 ( .A0(n3084), .A1(n3074), .B0(n3072), .B1(n2313), .Y(n3060)
);
OAI31X1TS U3837 ( .A0(n3061), .A1(n2316), .A2(n3060), .B0(n3059), .Y(
mult_x_69_n631) );
OAI22X1TS U3838 ( .A0(n2341), .A1(n3078), .B0(n2264), .B1(n2253), .Y(n3064)
);
OAI22X1TS U3839 ( .A0(n2248), .A1(n2251), .B0(n3065), .B1(n2315), .Y(n3063)
);
OAI31X1TS U3840 ( .A0(n3064), .A1(n3069), .A2(n3063), .B0(n3062), .Y(
mult_x_69_n652) );
OAI22X1TS U3841 ( .A0(n2301), .A1(n3083), .B0(n3065), .B1(n2253), .Y(n3070)
);
OAI22X1TS U3842 ( .A0(n2248), .A1(n4595), .B0(n2264), .B1(n2251), .Y(n3068)
);
OAI31X1TS U3843 ( .A0(n3070), .A1(n3069), .A2(n3068), .B0(n3067), .Y(
mult_x_69_n651) );
OAI22X1TS U3844 ( .A0(n2275), .A1(n3073), .B0(n3072), .B1(n3071), .Y(n3077)
);
OAI22X1TS U3845 ( .A0(n3084), .A1(n2271), .B0(n2262), .B1(n3074), .Y(n3076)
);
OAI31X1TS U3846 ( .A0(n3077), .A1(n2316), .A2(n3076), .B0(n3075), .Y(
mult_x_69_n630) );
OAI22X1TS U3847 ( .A0(n2275), .A1(n3078), .B0(n2262), .B1(n2253), .Y(n3081)
);
OAI22X1TS U3848 ( .A0(n3084), .A1(n2251), .B0(n3082), .B1(n2315), .Y(n3080)
);
OAI31X1TS U3849 ( .A0(n3081), .A1(n3088), .A2(n3080), .B0(n3079), .Y(
mult_x_69_n625) );
OAI22X1TS U3850 ( .A0(n2275), .A1(n3083), .B0(n3082), .B1(n2253), .Y(n3089)
);
OAI22X1TS U3851 ( .A0(n3084), .A1(n4595), .B0(n2262), .B1(n2251), .Y(n3087)
);
OAI31X1TS U3852 ( .A0(n3089), .A1(n3088), .A2(n3087), .B0(n3086), .Y(
mult_x_69_n624) );
CMPR32X2TS U3853 ( .A(n3094), .B(n3093), .C(n3092), .CO(n2640), .S(
mult_x_69_n454) );
ADDHXLTS U3854 ( .A(n3096), .B(n3095), .CO(mult_x_69_n441), .S(n2639) );
CMPR32X2TS U3855 ( .A(n3101), .B(n3100), .C(n3099), .CO(n2601), .S(
mult_x_69_n409) );
ADDHXLTS U3856 ( .A(FPMULT_Op_MX[11]), .B(n3102), .CO(n3114), .S(
mult_x_69_n471) );
ADDHXLTS U3857 ( .A(n3104), .B(n3103), .CO(mult_x_69_n390), .S(n2600) );
ADDHXLTS U3858 ( .A(n3106), .B(n3105), .CO(n3107), .S(mult_x_69_n370) );
ADDHXLTS U3859 ( .A(n3108), .B(n3107), .CO(n2565), .S(mult_x_69_n359) );
OAI22X1TS U3860 ( .A0(n2366), .A1(n3117), .B0(n3116), .B1(n2204), .Y(n3121)
);
OAI22X1TS U3861 ( .A0(n2243), .A1(n2257), .B0(n2255), .B1(n2207), .Y(n3120)
);
OAI31X1TS U3862 ( .A0(n3121), .A1(n4596), .A2(n3120), .B0(n3119), .Y(
mult_x_69_n747) );
ADDHX1TS U3863 ( .A(n3123), .B(n3122), .CO(n3099), .S(mult_x_69_n419) );
NOR4X1TS U3864 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n4866) );
NOR4X1TS U3865 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n4865) );
NOR4X1TS U3866 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n4867) );
NOR4X1TS U3867 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n4864) );
OR4X2TS U3868 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n3124) );
NOR4X1TS U3869 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n3124),
.Y(n4863) );
CLKAND2X4TS U3870 ( .A(n3236), .B(n4599), .Y(FPMULT_FSM_exp_operation_A_S)
);
NAND4X1TS U3871 ( .A(n2225), .B(n4599), .C(n4685), .D(n4621), .Y(n4944) );
BUFX3TS U3872 ( .A(n4869), .Y(n4939) );
INVX4TS U3873 ( .A(n4200), .Y(n4170) );
BUFX4TS U3874 ( .A(n4200), .Y(n4187) );
INVX2TS U3875 ( .A(n2323), .Y(n3943) );
INVX2TS U3876 ( .A(n3943), .Y(intadd_491_B_1_) );
ADDHXLTS U3877 ( .A(FPMULT_Op_MX[2]), .B(n3136), .CO(n3160), .S(n3137) );
AO22XLTS U3878 ( .A0(n3852), .A1(FPMULT_P_Sgf[0]), .B0(n4187), .B1(n3137),
.Y(n1553) );
NOR4X1TS U3879 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n3158) );
NOR2BX1TS U3880 ( .AN(n3158), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.Y(n3150) );
NAND2BX1TS U3881 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n3150),
.Y(n3894) );
NOR3X1TS U3882 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n4699),
.C(n3894), .Y(n3307) );
BUFX4TS U3883 ( .A(n3307), .Y(n3986) );
INVX2TS U3884 ( .A(n3238), .Y(n3524) );
NOR4X1TS U3885 ( .A(FPMULT_P_Sgf[14]), .B(FPMULT_P_Sgf[15]), .C(
FPMULT_P_Sgf[16]), .D(FPMULT_P_Sgf[17]), .Y(n3147) );
NOR4X1TS U3886 ( .A(FPMULT_P_Sgf[18]), .B(FPMULT_P_Sgf[19]), .C(
FPMULT_P_Sgf[20]), .D(FPMULT_P_Sgf[21]), .Y(n3146) );
NOR4X1TS U3887 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_P_Sgf[3]), .C(
FPMULT_P_Sgf[4]), .D(FPMULT_P_Sgf[5]), .Y(n3142) );
NOR3XLTS U3888 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[0]), .C(
FPMULT_P_Sgf[1]), .Y(n3141) );
AND4X1TS U3889 ( .A(n3142), .B(n3141), .C(n3140), .D(n3139), .Y(n3145) );
XOR2X1TS U3890 ( .A(FPMULT_Op_MX[31]), .B(FPMULT_Op_MY[31]), .Y(n4226) );
MXI2X1TS U3891 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n4226), .Y(n3143) );
OAI21XLTS U3892 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n3143), .Y(n3144) );
AOI31X1TS U3893 ( .A0(n3147), .A1(n3146), .A2(n3145), .B0(n3144), .Y(n3525)
);
INVX2TS U3894 ( .A(n3525), .Y(n3148) );
OAI31X1TS U3895 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(n3524), .A2(n3148),
.B0(n4769), .Y(n1690) );
BUFX3TS U3896 ( .A(n3151), .Y(n4906) );
CLKBUFX2TS U3897 ( .A(n3149), .Y(n4868) );
NAND4X2TS U3898 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n3150),
.C(n4631), .D(n4699), .Y(n3920) );
INVX2TS U3899 ( .A(n3920), .Y(n3921) );
BUFX3TS U3900 ( .A(n4896), .Y(n4883) );
BUFX3TS U3901 ( .A(n3213), .Y(n4884) );
BUFX3TS U3902 ( .A(n4926), .Y(n4913) );
BUFX3TS U3903 ( .A(n3152), .Y(n4887) );
BUFX3TS U3904 ( .A(n4880), .Y(n4900) );
BUFX3TS U3905 ( .A(n3151), .Y(n4924) );
BUFX3TS U3906 ( .A(n4892), .Y(n4889) );
BUFX3TS U3907 ( .A(n4892), .Y(n4898) );
BUFX3TS U3908 ( .A(n3151), .Y(n4926) );
BUFX3TS U3909 ( .A(n3152), .Y(n4897) );
BUFX3TS U3910 ( .A(n4896), .Y(n4880) );
BUFX3TS U3911 ( .A(n3152), .Y(n4894) );
BUFX3TS U3912 ( .A(n4874), .Y(n4872) );
BUFX3TS U3913 ( .A(n4923), .Y(n4921) );
CLKBUFX2TS U3914 ( .A(n3151), .Y(n4922) );
BUFX3TS U3915 ( .A(n4874), .Y(n4877) );
INVX4TS U3916 ( .A(n4941), .Y(n4532) );
BUFX4TS U3917 ( .A(n2290), .Y(n4543) );
BUFX4TS U3918 ( .A(n4543), .Y(n4540) );
AO22XLTS U3919 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[12]), .B0(n4540),
.B1(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1272) );
INVX4TS U3920 ( .A(n2290), .Y(n4528) );
AO22XLTS U3921 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[9]), .B0(n4540), .B1(
FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1285) );
AO22XLTS U3922 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[12]), .B0(n4540), .B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1270) );
AO22XLTS U3923 ( .A0(n2289), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n4540),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1266) );
INVX4TS U3924 ( .A(n4941), .Y(n4542) );
AO22XLTS U3925 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n4540), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1238) );
AO22XLTS U3926 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n4540),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1226) );
AO22XLTS U3927 ( .A0(n4532), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n4540), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1283) );
AO22XLTS U3928 ( .A0(n4532), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n4540),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1234) );
AO22XLTS U3929 ( .A0(n4532), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n4540),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1222) );
AO22XLTS U3930 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n4540), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1278) );
AO22XLTS U3931 ( .A0(n4528), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n4540),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1218) );
AO22XLTS U3932 ( .A0(n4528), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n4540), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1276) );
AO22XLTS U3933 ( .A0(n4528), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n4540),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1230) );
AO22XLTS U3934 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n4540),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1372) );
AO22XLTS U3935 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n4540), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1290) );
OR4X2TS U3936 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3214) );
NOR3XLTS U3937 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n3153) );
NAND3BXLTS U3938 ( .AN(n3214), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]),
.C(n3153), .Y(n3154) );
INVX2TS U3939 ( .A(n3154), .Y(n3155) );
BUFX4TS U3940 ( .A(n3978), .Y(n4053) );
INVX4TS U3941 ( .A(n3155), .Y(n3987) );
AO22XLTS U3942 ( .A0(n4053), .A1(intadd_491_SUM_2_), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1852) );
AO22XLTS U3943 ( .A0(n4053), .A1(intadd_491_SUM_0_), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1854) );
AO22XLTS U3944 ( .A0(n4053), .A1(intadd_491_SUM_1_), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1853) );
OR3X1TS U3945 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_492_n1), .Y(n3964) );
NOR2X1TS U3946 ( .A(FPSENCOS_d_ff2_X[29]), .B(n3964), .Y(n3963) );
XOR2XLTS U3947 ( .A(FPSENCOS_d_ff2_X[30]), .B(n3963), .Y(n3156) );
INVX4TS U3948 ( .A(n3155), .Y(n4052) );
AO22XLTS U3949 ( .A0(n4053), .A1(n3156), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1946) );
CLKBUFX3TS U3950 ( .A(n3157), .Y(n4223) );
INVX2TS U3951 ( .A(n4223), .Y(n4228) );
BUFX4TS U3952 ( .A(n4228), .Y(n4224) );
OA22X1TS U3953 ( .A0(FPMULT_exp_oper_result[5]), .A1(n2314), .B0(n4223),
.B1(mult_result[28]), .Y(n1487) );
OA22X1TS U3954 ( .A0(FPMULT_exp_oper_result[1]), .A1(n2314), .B0(n4223),
.B1(mult_result[24]), .Y(n1491) );
OA22X1TS U3955 ( .A0(FPMULT_exp_oper_result[7]), .A1(n2314), .B0(n4223),
.B1(mult_result[30]), .Y(n1485) );
OA22X1TS U3956 ( .A0(FPMULT_exp_oper_result[0]), .A1(n2314), .B0(n4223),
.B1(mult_result[23]), .Y(n1492) );
OA22X1TS U3957 ( .A0(FPMULT_exp_oper_result[6]), .A1(n2314), .B0(n4223),
.B1(mult_result[29]), .Y(n1486) );
OA22X1TS U3958 ( .A0(FPMULT_exp_oper_result[3]), .A1(n2314), .B0(n4223),
.B1(mult_result[26]), .Y(n1489) );
OA22X1TS U3959 ( .A0(FPMULT_exp_oper_result[2]), .A1(n2314), .B0(n4223),
.B1(mult_result[25]), .Y(n1490) );
NOR3XLTS U3960 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3159) );
NAND3XLTS U3961 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(n3159),
.C(n3158), .Y(n3454) );
AOI21X1TS U3962 ( .A0(operation[1]), .A1(ack_operation), .B0(n3454), .Y(
n3891) );
NOR2X1TS U3963 ( .A(n3920), .B(n3896), .Y(n3455) );
OR2X1TS U3964 ( .A(n3891), .B(n3455), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
ADDHXLTS U3965 ( .A(n3161), .B(n3160), .CO(n3163), .S(n3162) );
AO22XLTS U3966 ( .A0(n3852), .A1(FPMULT_P_Sgf[1]), .B0(n4187), .B1(n3162),
.Y(n1554) );
ADDHXLTS U3967 ( .A(n3164), .B(n3163), .CO(n3170), .S(n3165) );
AO22XLTS U3968 ( .A0(n3852), .A1(FPMULT_P_Sgf[2]), .B0(n4187), .B1(n3165),
.Y(n1555) );
INVX2TS U3969 ( .A(operation[2]), .Y(n3901) );
BUFX4TS U3970 ( .A(n3166), .Y(n3910) );
OAI2BB1X1TS U3971 ( .A0N(ack_operation), .A1N(n3166), .B0(n3909), .Y(n3167)
);
NAND2X1TS U3972 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[0]), .Y(n3168) );
AOI211XLTS U3973 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(n3530), .B0(n4090), .C0(n4223), .Y(n3169) );
INVX2TS U3974 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n3851) );
NOR2X1TS U3975 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n2225), .Y(n3237) );
NAND3XLTS U3976 ( .A(n3169), .B(n3851), .C(n3528), .Y(n1692) );
CMPR32X2TS U3977 ( .A(n3172), .B(n3171), .C(n3170), .CO(n3174), .S(n3173) );
AO22XLTS U3978 ( .A0(n3852), .A1(FPMULT_P_Sgf[3]), .B0(n4187), .B1(n3173),
.Y(n1556) );
CMPR32X2TS U3979 ( .A(n3176), .B(n3175), .C(n3174), .CO(n3178), .S(n3177) );
AO22XLTS U3980 ( .A0(n3852), .A1(FPMULT_P_Sgf[4]), .B0(n4187), .B1(n3177),
.Y(n1557) );
AO22XLTS U3981 ( .A0(n3852), .A1(FPMULT_P_Sgf[5]), .B0(n4187), .B1(n3181),
.Y(n1558) );
AO22XLTS U3982 ( .A0(n3852), .A1(FPMULT_P_Sgf[6]), .B0(n4187), .B1(n3185),
.Y(n1559) );
AO22XLTS U3983 ( .A0(n3852), .A1(FPMULT_P_Sgf[7]), .B0(n4187), .B1(n3189),
.Y(n1560) );
AO22XLTS U3984 ( .A0(n3852), .A1(FPMULT_P_Sgf[8]), .B0(n4187), .B1(n3193),
.Y(n1561) );
AO22XLTS U3985 ( .A0(n3852), .A1(FPMULT_P_Sgf[9]), .B0(n4187), .B1(n3196),
.Y(n1562) );
AO22XLTS U3986 ( .A0(n3852), .A1(FPMULT_P_Sgf[10]), .B0(n4187), .B1(n3199),
.Y(n1563) );
AO22XLTS U3987 ( .A0(n3852), .A1(FPMULT_P_Sgf[11]), .B0(n4219), .B1(n3202),
.Y(n1564) );
AO22XLTS U3988 ( .A0(n3852), .A1(FPMULT_P_Sgf[12]), .B0(n4219), .B1(n3205),
.Y(n1565) );
CMPR32X2TS U3989 ( .A(n3207), .B(mult_x_69_n445), .C(n3206), .CO(n3209), .S(
n3208) );
AO22XLTS U3990 ( .A0(n3852), .A1(FPMULT_P_Sgf[13]), .B0(n4219), .B1(n3208),
.Y(n1566) );
CMPR32X2TS U3991 ( .A(n3210), .B(mult_x_69_n438), .C(n3209), .CO(n4216), .S(
n3211) );
AO22XLTS U3992 ( .A0(n3852), .A1(FPMULT_P_Sgf[14]), .B0(n4219), .B1(n3211),
.Y(n1567) );
NAND4X1TS U3993 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[0]), .C(n2225), .D(n4599), .Y(n4120) );
BUFX3TS U3994 ( .A(n4120), .Y(n4138) );
BUFX3TS U3995 ( .A(n4138), .Y(n4141) );
OR3X1TS U3996 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n4097) );
NAND2X1TS U3997 ( .A(FPMULT_Sgf_normalized_result[3]), .B(n4097), .Y(n4099)
);
NAND2X1TS U3998 ( .A(n4671), .B(n4099), .Y(n4101) );
NOR2X2TS U3999 ( .A(n4674), .B(n4103), .Y(n4105) );
NAND2X1TS U4000 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n4105), .Y(n4107)
);
NOR2X2TS U4001 ( .A(n4678), .B(n4107), .Y(n4109) );
NAND2X1TS U4002 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n4109), .Y(n4111)
);
NOR2X2TS U4003 ( .A(n4679), .B(n4111), .Y(n4113) );
NAND2X1TS U4004 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n4113), .Y(n4115)
);
NOR2X2TS U4005 ( .A(n4681), .B(n4115), .Y(n4117) );
NAND2X1TS U4006 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n4117), .Y(n4119)
);
NOR2X2TS U4007 ( .A(n4692), .B(n4119), .Y(n4122) );
NAND2X1TS U4008 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n4122), .Y(n4124)
);
NOR2X2TS U4009 ( .A(n4732), .B(n4124), .Y(n4126) );
NAND2X1TS U4010 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n4126), .Y(n4128)
);
NOR2X2TS U4011 ( .A(n4743), .B(n4128), .Y(n4130) );
NAND2X1TS U4012 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n4130), .Y(n4132)
);
NOR2X2TS U4013 ( .A(n4767), .B(n4132), .Y(n4136) );
NAND2X1TS U4014 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4136), .Y(n4134)
);
NOR2X2TS U4015 ( .A(n4779), .B(n4134), .Y(n4139) );
AOI211XLTS U4016 ( .A0(n4779), .A1(n4134), .B0(n4139), .C0(n4138), .Y(n3212)
);
AO21XLTS U4017 ( .A0(FPMULT_Add_result[22]), .A1(n4141), .B0(n3212), .Y(
n1602) );
OAI21XLTS U4018 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n2197), .B0(n2308),
.Y(n1352) );
INVX2TS U4019 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4365) );
OAI21XLTS U4020 ( .A0(n4038), .A1(n4742), .B0(n2308), .Y(n2081) );
OAI21XLTS U4021 ( .A0(n4038), .A1(n4557), .B0(n3564), .Y(n2080) );
NOR2X1TS U4022 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(n3214),
.Y(n3215) );
BUFX4TS U4023 ( .A(n3897), .Y(n4050) );
NOR2XLTS U4024 ( .A(n3900), .B(n4050), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
NAND2X1TS U4025 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n3898) );
INVX2TS U4026 ( .A(n3898), .Y(n3216) );
NOR2BX1TS U4027 ( .AN(n3215), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n3438) );
INVX3TS U4028 ( .A(n3155), .Y(n3957) );
OAI21XLTS U4029 ( .A0(n3216), .A1(n3899), .B0(n3957), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
BUFX3TS U4030 ( .A(n3978), .Y(n3975) );
NAND2X2TS U4031 ( .A(n3975), .B(n4704), .Y(n3946) );
AOI21X1TS U4032 ( .A0(n4871), .A1(n3943), .B0(FPSENCOS_cont_iter_out[3]),
.Y(n3232) );
AOI22X1TS U4033 ( .A0(n3978), .A1(n3232), .B0(FPSENCOS_d_ff3_LUT_out[26]),
.B1(n3957), .Y(n3217) );
OAI21XLTS U4034 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3946), .B0(n3217),
.Y(n2116) );
NAND2X1TS U4035 ( .A(n4871), .B(n4645), .Y(intadd_491_CI) );
NAND2X1TS U4036 ( .A(n3975), .B(n4951), .Y(n3944) );
INVX2TS U4037 ( .A(n3944), .Y(n3219) );
AOI22X1TS U4038 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n3219), .B0(
FPSENCOS_d_ff3_sh_y_out[23]), .B1(n3957), .Y(n3218) );
OAI21XLTS U4039 ( .A0(n3961), .A1(intadd_491_CI), .B0(n3218), .Y(n1855) );
OR2X1TS U4040 ( .A(FPSENCOS_d_ff2_X[23]), .B(n4951), .Y(intadd_492_CI) );
AOI22X1TS U4041 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n3219), .B0(
FPSENCOS_d_ff3_sh_x_out[23]), .B1(n3957), .Y(n3220) );
OAI21XLTS U4042 ( .A0(n3961), .A1(intadd_492_CI), .B0(n3220), .Y(n1953) );
INVX2TS U4043 ( .A(n3941), .Y(n3234) );
NAND2X2TS U4044 ( .A(n3975), .B(FPSENCOS_cont_iter_out[1]), .Y(n3940) );
NOR3X1TS U4045 ( .A(n3943), .B(n4951), .C(n3940), .Y(n3223) );
AOI21X1TS U4046 ( .A0(n2306), .A1(n3957), .B0(n3223), .Y(n3221) );
OAI21XLTS U4047 ( .A0(n3946), .A1(n3234), .B0(n3221), .Y(n2133) );
INVX2TS U4048 ( .A(n3226), .Y(n3937) );
OAI21XLTS U4049 ( .A0(n3937), .A1(n3944), .B0(n3222), .Y(n2119) );
OAI31X1TS U4050 ( .A0(n4871), .A1(FPSENCOS_cont_iter_out[3]), .A2(n3946),
.B0(n3225), .Y(n2129) );
AOI211X1TS U4051 ( .A0(n4871), .A1(n4623), .B0(n3943), .C0(n3946), .Y(n3934)
);
AOI21X1TS U4052 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n3957), .B0(n3934),
.Y(n3227) );
OAI21XLTS U4053 ( .A0(n2307), .A1(n3940), .B0(n3227), .Y(n2135) );
NOR2BX1TS U4054 ( .AN(FPMULT_P_Sgf[47]), .B(n3528), .Y(n3228) );
INVX2TS U4055 ( .A(n4090), .Y(n4087) );
INVX3TS U4056 ( .A(n4138), .Y(n4143) );
INVX2TS U4057 ( .A(n3228), .Y(n3229) );
OAI31X1TS U4058 ( .A0(n4090), .A1(n4143), .A2(n4708), .B0(n3229), .Y(n1550)
);
INVX2TS U4059 ( .A(n3940), .Y(n3932) );
NAND2X1TS U4060 ( .A(n3932), .B(n3937), .Y(n3938) );
OAI2BB1X1TS U4061 ( .A0N(n3936), .A1N(n3234), .B0(n3975), .Y(n3925) );
OAI211XLTS U4062 ( .A0(n3978), .A1(n4845), .B0(n3938), .C0(n3925), .Y(n2122)
);
INVX2TS U4063 ( .A(n3946), .Y(n3927) );
NAND2X1TS U4064 ( .A(n4871), .B(n3937), .Y(n3230) );
AOI22X1TS U4065 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n3961), .B0(n3927),
.B1(n3230), .Y(n3231) );
AOI22X1TS U4066 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n3983), .B0(n3927),
.B1(n3232), .Y(n3233) );
OAI21XLTS U4067 ( .A0(n3943), .A1(n3940), .B0(n3233), .Y(n2131) );
NAND2X1TS U4068 ( .A(n3927), .B(n3937), .Y(n3235) );
NAND2X1TS U4069 ( .A(n3932), .B(n3929), .Y(n3935) );
OAI211XLTS U4070 ( .A0(n3975), .A1(n4843), .B0(n3935), .C0(n3235), .Y(n2126)
);
AOI32X2TS U4071 ( .A0(FPMULT_FSM_add_overflow_flag), .A1(
FPMULT_FS_Module_state_reg[1]), .A2(n3238), .B0(n3236), .B1(
FPMULT_FS_Module_state_reg[1]), .Y(n4093) );
OR2X2TS U4072 ( .A(n4093), .B(FPMULT_FSM_selector_C), .Y(n3289) );
INVX3TS U4073 ( .A(n3239), .Y(n4091) );
AOI22X1TS U4074 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n4091), .B0(
n2295), .B1(FPMULT_Add_result[3]), .Y(n3244) );
NAND2X1TS U4075 ( .A(n3239), .B(n4093), .Y(n3241) );
BUFX3TS U4076 ( .A(n3240), .Y(n3291) );
AOI22X1TS U4077 ( .A0(n2296), .A1(FPMULT_P_Sgf[25]), .B0(n3290), .B1(
FPMULT_Add_result[2]), .Y(n3243) );
OAI211XLTS U4078 ( .A0(n3281), .A1(n4799), .B0(n3244), .C0(n3243), .Y(n1519)
);
INVX3TS U4079 ( .A(n3239), .Y(n3286) );
AOI22X1TS U4080 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n3286), .B0(
n2295), .B1(FPMULT_Add_result[1]), .Y(n3246) );
AOI22X1TS U4081 ( .A0(n2296), .A1(FPMULT_P_Sgf[23]), .B0(n3290), .B1(
FPMULT_Add_result[0]), .Y(n3245) );
OAI211XLTS U4082 ( .A0(n3281), .A1(n4801), .B0(n3246), .C0(n3245), .Y(n1517)
);
AOI22X1TS U4083 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4091), .B0(
FPMULT_Add_result[6]), .B1(n2294), .Y(n3248) );
AOI22X1TS U4084 ( .A0(n2296), .A1(FPMULT_P_Sgf[28]), .B0(n3290), .B1(
FPMULT_Add_result[5]), .Y(n3247) );
OAI211XLTS U4085 ( .A0(n3281), .A1(n4818), .B0(n3248), .C0(n3247), .Y(n1522)
);
AOI22X1TS U4086 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4091), .B0(
n2295), .B1(FPMULT_Add_result[4]), .Y(n3250) );
AOI22X1TS U4087 ( .A0(n2296), .A1(FPMULT_P_Sgf[26]), .B0(n3290), .B1(
FPMULT_Add_result[3]), .Y(n3249) );
OAI211XLTS U4088 ( .A0(n3281), .A1(n4798), .B0(n3250), .C0(n3249), .Y(n1520)
);
AOI22X1TS U4089 ( .A0(FPMULT_Sgf_normalized_result[1]), .A1(n4091), .B0(
n2295), .B1(FPMULT_Add_result[2]), .Y(n3252) );
AOI22X1TS U4090 ( .A0(n2296), .A1(FPMULT_P_Sgf[24]), .B0(n3290), .B1(
FPMULT_Add_result[1]), .Y(n3251) );
OAI211XLTS U4091 ( .A0(n3281), .A1(n4800), .B0(n3252), .C0(n3251), .Y(n1518)
);
AOI22X1TS U4092 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n4091), .B0(
n2295), .B1(FPMULT_Add_result[5]), .Y(n3254) );
AOI22X1TS U4093 ( .A0(n2296), .A1(FPMULT_P_Sgf[27]), .B0(n3290), .B1(
FPMULT_Add_result[4]), .Y(n3253) );
OAI211XLTS U4094 ( .A0(n3281), .A1(n4797), .B0(n3254), .C0(n3253), .Y(n1521)
);
AOI22X1TS U4095 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4091), .B0(
FPMULT_Add_result[8]), .B1(n2294), .Y(n3256) );
AOI22X1TS U4096 ( .A0(FPMULT_Add_result[7]), .A1(n2309), .B0(n3291), .B1(
FPMULT_P_Sgf[30]), .Y(n3255) );
OAI211XLTS U4097 ( .A0(n3281), .A1(n4816), .B0(n3256), .C0(n3255), .Y(n1524)
);
AOI22X1TS U4098 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n3286), .B0(
FPMULT_Add_result[20]), .B1(n2294), .Y(n3258) );
AOI22X1TS U4099 ( .A0(FPMULT_Add_result[19]), .A1(n2309), .B0(n3291), .B1(
FPMULT_P_Sgf[42]), .Y(n3257) );
OAI211XLTS U4100 ( .A0(n3281), .A1(n4804), .B0(n3258), .C0(n3257), .Y(n1536)
);
AOI22X1TS U4101 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n3286), .B0(
FPMULT_Add_result[22]), .B1(n2294), .Y(n3260) );
AOI22X1TS U4102 ( .A0(FPMULT_Add_result[21]), .A1(n2309), .B0(n3291), .B1(
FPMULT_P_Sgf[44]), .Y(n3259) );
OAI211XLTS U4103 ( .A0(n4802), .A1(n3281), .B0(n3260), .C0(n3259), .Y(n1538)
);
AOI22X1TS U4104 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n3286), .B0(
FPMULT_Add_result[18]), .B1(n2294), .Y(n3262) );
AOI22X1TS U4105 ( .A0(FPMULT_Add_result[17]), .A1(n2309), .B0(n3291), .B1(
FPMULT_P_Sgf[40]), .Y(n3261) );
OAI211XLTS U4106 ( .A0(n3281), .A1(n4806), .B0(n3262), .C0(n3261), .Y(n1534)
);
AOI22X1TS U4107 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4091), .B0(
FPMULT_Add_result[10]), .B1(n2294), .Y(n3264) );
AOI22X1TS U4108 ( .A0(FPMULT_Add_result[9]), .A1(n2309), .B0(n2296), .B1(
FPMULT_P_Sgf[32]), .Y(n3263) );
AOI22X1TS U4109 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n3286), .B0(
FPMULT_Add_result[14]), .B1(n2294), .Y(n3266) );
AOI22X1TS U4110 ( .A0(FPMULT_Add_result[13]), .A1(n2309), .B0(n2296), .B1(
FPMULT_P_Sgf[36]), .Y(n3265) );
OAI211XLTS U4111 ( .A0(n3289), .A1(n4810), .B0(n3266), .C0(n3265), .Y(n1530)
);
AOI22X1TS U4112 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n3286), .B0(
FPMULT_Add_result[16]), .B1(n2294), .Y(n3268) );
AOI22X1TS U4113 ( .A0(FPMULT_Add_result[15]), .A1(n2309), .B0(n2296), .B1(
FPMULT_P_Sgf[38]), .Y(n3267) );
OAI211XLTS U4114 ( .A0(n3289), .A1(n4808), .B0(n3268), .C0(n3267), .Y(n1532)
);
AOI22X1TS U4115 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n3286), .B0(
FPMULT_Add_result[12]), .B1(n2294), .Y(n3270) );
AOI22X1TS U4116 ( .A0(FPMULT_Add_result[11]), .A1(n2309), .B0(n2296), .B1(
FPMULT_P_Sgf[34]), .Y(n3269) );
OAI211XLTS U4117 ( .A0(n3289), .A1(n4812), .B0(n3270), .C0(n3269), .Y(n1528)
);
AOI22X1TS U4118 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n3286), .B0(
FPMULT_Add_result[21]), .B1(n2294), .Y(n3272) );
AOI22X1TS U4119 ( .A0(FPMULT_Add_result[20]), .A1(n3290), .B0(n3291), .B1(
FPMULT_P_Sgf[43]), .Y(n3271) );
OAI211XLTS U4120 ( .A0(n4796), .A1(n3281), .B0(n3272), .C0(n3271), .Y(n1537)
);
AOI22X1TS U4121 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n4091), .B0(
FPMULT_Add_result[11]), .B1(n2294), .Y(n3274) );
AOI22X1TS U4122 ( .A0(FPMULT_Add_result[10]), .A1(n3290), .B0(n3291), .B1(
FPMULT_P_Sgf[33]), .Y(n3273) );
AOI22X1TS U4123 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n3286), .B0(
FPMULT_Add_result[13]), .B1(n2295), .Y(n3276) );
AOI22X1TS U4124 ( .A0(FPMULT_Add_result[12]), .A1(n3290), .B0(n3291), .B1(
FPMULT_P_Sgf[35]), .Y(n3275) );
OAI211XLTS U4125 ( .A0(n3281), .A1(n4811), .B0(n3276), .C0(n3275), .Y(n1529)
);
AOI22X1TS U4126 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n4091), .B0(
FPMULT_Add_result[9]), .B1(n2295), .Y(n3278) );
AOI22X1TS U4127 ( .A0(FPMULT_Add_result[8]), .A1(n3290), .B0(n3291), .B1(
FPMULT_P_Sgf[31]), .Y(n3277) );
OAI211XLTS U4128 ( .A0(n3281), .A1(n4815), .B0(n3278), .C0(n3277), .Y(n1525)
);
AOI22X1TS U4129 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n4091), .B0(
FPMULT_Add_result[7]), .B1(n2295), .Y(n3280) );
AOI22X1TS U4130 ( .A0(FPMULT_Add_result[6]), .A1(n2309), .B0(n3291), .B1(
FPMULT_P_Sgf[29]), .Y(n3279) );
OAI211XLTS U4131 ( .A0(n3281), .A1(n4817), .B0(n3280), .C0(n3279), .Y(n1523)
);
AOI22X1TS U4132 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n3286), .B0(
FPMULT_Add_result[17]), .B1(n2295), .Y(n3283) );
AOI22X1TS U4133 ( .A0(FPMULT_Add_result[16]), .A1(n2309), .B0(n3291), .B1(
FPMULT_P_Sgf[39]), .Y(n3282) );
OAI211XLTS U4134 ( .A0(n3289), .A1(n4807), .B0(n3283), .C0(n3282), .Y(n1533)
);
AOI22X1TS U4135 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n3286), .B0(
FPMULT_Add_result[15]), .B1(n2295), .Y(n3285) );
AOI22X1TS U4136 ( .A0(FPMULT_Add_result[14]), .A1(n2309), .B0(n3291), .B1(
FPMULT_P_Sgf[37]), .Y(n3284) );
OAI211XLTS U4137 ( .A0(n3289), .A1(n4809), .B0(n3285), .C0(n3284), .Y(n1531)
);
AOI22X1TS U4138 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n3286), .B0(
FPMULT_Add_result[19]), .B1(n2295), .Y(n3288) );
AOI22X1TS U4139 ( .A0(FPMULT_Add_result[18]), .A1(n2309), .B0(n3291), .B1(
FPMULT_P_Sgf[41]), .Y(n3287) );
OAI211XLTS U4140 ( .A0(n3289), .A1(n4805), .B0(n3288), .C0(n3287), .Y(n1535)
);
AOI22X1TS U4141 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n4769), .Y(n4092) );
AOI22X1TS U4142 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4091), .B0(
FPMULT_Add_result[22]), .B1(n3290), .Y(n3293) );
NAND2X1TS U4143 ( .A(n2296), .B(FPMULT_P_Sgf[45]), .Y(n3292) );
OAI211XLTS U4144 ( .A0(n4093), .A1(n4092), .B0(n3293), .C0(n3292), .Y(n1539)
);
XNOR2X1TS U4145 ( .A(DP_OP_26J217_122_5882_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n3303) );
NOR2XLTS U4146 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n3295) );
INVX2TS U4147 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n3860) );
INVX2TS U4148 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n3294) );
NAND4BXLTS U4149 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n3295), .C(n3860),
.D(n3294), .Y(n3296) );
NAND2BX1TS U4150 ( .AN(n3303), .B(n3299), .Y(n4262) );
INVX2TS U4151 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n3834) );
AND4X1TS U4152 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n3300) );
NAND3XLTS U4153 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[4]), .C(n3300), .Y(n3301) );
NAND2BXLTS U4154 ( .AN(n3301), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n3302)
);
OAI2BB1X1TS U4155 ( .A0N(n3304), .A1N(n3303), .B0(n2240), .Y(n3856) );
INVX2TS U4156 ( .A(n3856), .Y(n4263) );
OAI21XLTS U4157 ( .A0(n3305), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n4263),
.Y(n3306) );
OAI21XLTS U4158 ( .A0(n4303), .A1(n4640), .B0(n3306), .Y(n1358) );
CLKINVX6TS U4159 ( .A(n3986), .Y(n3482) );
NAND4X1TS U4160 ( .A(n4704), .B(n4951), .C(n4623), .D(intadd_491_B_1_), .Y(
n3309) );
NAND2X1TS U4161 ( .A(n3309), .B(n3986), .Y(n3308) );
BUFX4TS U4162 ( .A(n3308), .Y(n3985) );
INVX2TS U4163 ( .A(n3308), .Y(n3968) );
BUFX4TS U4164 ( .A(n3968), .Y(n3972) );
CLKINVX6TS U4165 ( .A(n3986), .Y(n3973) );
NOR2X2TS U4166 ( .A(n3967), .B(n3309), .Y(n3314) );
BUFX3TS U4167 ( .A(n3314), .Y(n3386) );
INVX2TS U4168 ( .A(n3310), .Y(n1765) );
INVX2TS U4169 ( .A(n3311), .Y(n1760) );
INVX2TS U4170 ( .A(n3312), .Y(n1762) );
INVX2TS U4171 ( .A(n3313), .Y(n1764) );
INVX2TS U4172 ( .A(n3315), .Y(n1763) );
BUFX4TS U4173 ( .A(n3968), .Y(n3958) );
INVX2TS U4174 ( .A(n3316), .Y(n1761) );
INVX2TS U4175 ( .A(n3317), .Y(n1766) );
BUFX4TS U4176 ( .A(n4952), .Y(n3916) );
NOR2X1TS U4177 ( .A(n4782), .B(FPADDSUB_intDX_EWSW[25]), .Y(n3377) );
NOR2XLTS U4178 ( .A(n3377), .B(FPADDSUB_intDY_EWSW[24]), .Y(n3318) );
AOI22X1TS U4179 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n4782), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n3318), .Y(n3322) );
OAI21X1TS U4180 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n4781), .B0(n3319), .Y(
n3378) );
NAND3XLTS U4181 ( .A(n4781), .B(n3319), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n3321) );
NOR2X1TS U4182 ( .A(n4735), .B(FPADDSUB_intDX_EWSW[30]), .Y(n3325) );
NOR2X1TS U4183 ( .A(n4639), .B(FPADDSUB_intDX_EWSW[29]), .Y(n3323) );
AOI211X1TS U4184 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n4774), .B0(n3325),
.C0(n3323), .Y(n3376) );
NOR3X1TS U4185 ( .A(n4774), .B(n3323), .C(FPADDSUB_intDY_EWSW[28]), .Y(n3324) );
AOI221X1TS U4186 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n4735), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n4639), .C0(n3324), .Y(n3326) );
AOI2BB2X1TS U4187 ( .B0(n3327), .B1(n3376), .A0N(n3326), .A1N(n3325), .Y(
n3382) );
NOR2X1TS U4188 ( .A(n4702), .B(FPADDSUB_intDX_EWSW[17]), .Y(n3363) );
NAND2BXLTS U4189 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n3344) );
NOR2X1TS U4190 ( .A(n4693), .B(FPADDSUB_intDX_EWSW[11]), .Y(n3342) );
AOI21X1TS U4191 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4754), .B0(n3342), .Y(
n3347) );
OAI211XLTS U4192 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n4701), .B0(n3344), .C0(
n3347), .Y(n3358) );
OAI2BB1X1TS U4193 ( .A0N(n4646), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n3328) );
OAI22X1TS U4194 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3328), .B0(n4646), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n3339) );
OAI2BB1X1TS U4195 ( .A0N(n4766), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n3329) );
OAI22X1TS U4196 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3329), .B0(n4766), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n3338) );
OAI2BB2XLTS U4197 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n3330), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n4691), .Y(n3332) );
NAND2BXLTS U4198 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n3331) );
OAI211XLTS U4199 ( .A0(n4688), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n3332), .C0(
n3331), .Y(n3335) );
OAI21XLTS U4200 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n4688), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n3333) );
AOI2BB2XLTS U4201 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n4688), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n3333), .Y(n3334) );
AOI22X1TS U4202 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n4766), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n4648), .Y(n3336) );
OAI32X1TS U4203 ( .A0(n3339), .A1(n3338), .A2(n3337), .B0(n3336), .B1(n3338),
.Y(n3357) );
OA22X1TS U4204 ( .A0(n4684), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n4628), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n3354) );
NAND2BXLTS U4205 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n3340) );
OAI21XLTS U4206 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n4697), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n3341) );
OAI2BB2XLTS U4207 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n3341), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n4697), .Y(n3353) );
NOR2XLTS U4208 ( .A(n3342), .B(FPADDSUB_intDY_EWSW[10]), .Y(n3343) );
AOI22X1TS U4209 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n4693), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n3343), .Y(n3349) );
NAND3XLTS U4210 ( .A(n4701), .B(n3344), .C(FPADDSUB_intDX_EWSW[8]), .Y(n3345) );
AOI21X1TS U4211 ( .A0(n3346), .A1(n3345), .B0(n3356), .Y(n3348) );
OAI2BB2XLTS U4212 ( .B0(n3349), .B1(n3356), .A0N(n3348), .A1N(n3347), .Y(
n3352) );
OAI2BB2XLTS U4213 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n3350), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n4628), .Y(n3351) );
AOI211X1TS U4214 ( .A0(n3354), .A1(n3353), .B0(n3352), .C0(n3351), .Y(n3355)
);
OAI31X1TS U4215 ( .A0(n3358), .A1(n3357), .A2(n3356), .B0(n3355), .Y(n3361)
);
OA22X1TS U4216 ( .A0(n4633), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n4695), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n3374) );
NAND2BXLTS U4217 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n3359) );
NAND2BXLTS U4218 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n3365) );
OAI21X1TS U4219 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n4733), .B0(n3365), .Y(
n3369) );
NAND3BXLTS U4220 ( .AN(n3363), .B(n3361), .C(n3360), .Y(n3381) );
OAI2BB2XLTS U4221 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n3362), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n4698), .Y(n3373) );
AOI22X1TS U4222 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n4702), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n3364), .Y(n3367) );
AOI32X1TS U4223 ( .A0(n4733), .A1(n3365), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n4637), .Y(n3366) );
OAI32X1TS U4224 ( .A0(n3369), .A1(n3368), .A2(n3367), .B0(n3366), .B1(n3368),
.Y(n3372) );
OAI21XLTS U4225 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n4695), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n3370) );
OAI2BB2XLTS U4226 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n3370), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n4695), .Y(n3371) );
AOI211X1TS U4227 ( .A0(n3374), .A1(n3373), .B0(n3372), .C0(n3371), .Y(n3380)
);
NAND2BXLTS U4228 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n3375) );
NAND4BBX1TS U4229 ( .AN(n3378), .BN(n3377), .C(n3376), .D(n3375), .Y(n3379)
);
NOR2X1TS U4230 ( .A(n3916), .B(n4362), .Y(n3383) );
BUFX3TS U4231 ( .A(n3383), .Y(n3427) );
BUFX4TS U4232 ( .A(n3916), .Y(n3450) );
AOI22X1TS U4233 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n4952), .Y(n3384) );
OAI21XLTS U4234 ( .A0(n4649), .A1(n4246), .B0(n3384), .Y(n1273) );
BUFX3TS U4235 ( .A(n3385), .Y(n4064) );
BUFX3TS U4236 ( .A(n4064), .Y(n4066) );
INVX4TS U4237 ( .A(n4066), .Y(n4062) );
INVX2TS U4238 ( .A(n3387), .Y(n1754) );
BUFX4TS U4239 ( .A(n3968), .Y(n3966) );
INVX2TS U4240 ( .A(n3388), .Y(n1736) );
INVX2TS U4241 ( .A(n3389), .Y(n1759) );
INVX2TS U4242 ( .A(n3390), .Y(n1756) );
INVX2TS U4243 ( .A(n3391), .Y(n1735) );
INVX2TS U4244 ( .A(n3392), .Y(n1755) );
INVX3TS U4245 ( .A(n3427), .Y(n3426) );
AOI22X1TS U4246 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n3916), .Y(n3393) );
OAI21XLTS U4247 ( .A0(n4756), .A1(n3426), .B0(n3393), .Y(n1379) );
AOI22X1TS U4248 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n3450), .Y(n3394) );
OAI21XLTS U4249 ( .A0(n4648), .A1(n3426), .B0(n3394), .Y(n1385) );
AOI22X1TS U4250 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n3450), .Y(n3395) );
OAI21XLTS U4251 ( .A0(n4752), .A1(n3426), .B0(n3395), .Y(n1388) );
AOI22X1TS U4252 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n3450), .Y(n3396) );
OAI21XLTS U4253 ( .A0(n4762), .A1(n3426), .B0(n3396), .Y(n1391) );
AOI22X1TS U4254 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n4952), .Y(n3397) );
OAI21XLTS U4255 ( .A0(n4642), .A1(n3426), .B0(n3397), .Y(n1382) );
AOI22X1TS U4256 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n4368), .Y(n3398) );
AOI22X1TS U4257 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n4952), .Y(n3399) );
OAI21XLTS U4258 ( .A0(n4749), .A1(n3426), .B0(n3399), .Y(n1376) );
INVX4TS U4259 ( .A(n3427), .Y(n4246) );
AOI22X1TS U4260 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n3450), .Y(n3400) );
OAI21XLTS U4261 ( .A0(n4647), .A1(n4246), .B0(n3400), .Y(n1394) );
AOI22X1TS U4262 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n3448), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n3450), .Y(n3401) );
OAI21XLTS U4263 ( .A0(n4753), .A1(n4246), .B0(n3401), .Y(n1397) );
BUFX4TS U4264 ( .A(n3448), .Y(n3434) );
AOI22X1TS U4265 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n3916), .Y(n3402) );
OAI21XLTS U4266 ( .A0(n4766), .A1(n3426), .B0(n3402), .Y(n1307) );
AOI22X1TS U4267 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n3434), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n3916), .Y(n3403) );
OAI21XLTS U4268 ( .A0(n4746), .A1(n3426), .B0(n3403), .Y(n1305) );
AOI22X1TS U4269 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n3450), .Y(n3404) );
OAI21XLTS U4270 ( .A0(n4643), .A1(n4246), .B0(n3404), .Y(n1400) );
AOI22X1TS U4271 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n3450), .Y(n3405) );
OAI21XLTS U4272 ( .A0(n4744), .A1(n4246), .B0(n3405), .Y(n1406) );
AOI22X1TS U4273 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n3450), .Y(n3406) );
OAI21XLTS U4274 ( .A0(n4757), .A1(n4246), .B0(n3406), .Y(n1409) );
AOI22X1TS U4275 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n4952), .Y(n3407) );
OAI21XLTS U4276 ( .A0(n4759), .A1(n4246), .B0(n3407), .Y(n1293) );
AOI22X1TS U4277 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n4952), .Y(n3408) );
OAI21XLTS U4278 ( .A0(n4755), .A1(n3426), .B0(n3408), .Y(n1370) );
AOI22X1TS U4279 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n3450), .Y(n3409) );
OAI21XLTS U4280 ( .A0(n4650), .A1(n4246), .B0(n3409), .Y(n1403) );
AOI22X1TS U4281 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n3450), .Y(n3410) );
OAI21XLTS U4282 ( .A0(n4641), .A1(n3426), .B0(n3410), .Y(n1330) );
AOI22X1TS U4283 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n4952), .Y(n3411) );
OAI21XLTS U4284 ( .A0(n4750), .A1(n4246), .B0(n3411), .Y(n1300) );
INVX4TS U4285 ( .A(n3448), .Y(n4247) );
BUFX4TS U4286 ( .A(n3427), .Y(n3445) );
AOI22X1TS U4287 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n3916), .Y(n3412) );
OAI21XLTS U4288 ( .A0(n4647), .A1(n4247), .B0(n3412), .Y(n1231) );
INVX4TS U4289 ( .A(n3448), .Y(n3453) );
AOI22X1TS U4290 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n4952), .Y(n3413) );
OAI21XLTS U4291 ( .A0(n4759), .A1(n3453), .B0(n3413), .Y(n1291) );
AOI22X1TS U4292 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n4952), .Y(n3414) );
OAI21XLTS U4293 ( .A0(n4755), .A1(n3453), .B0(n3414), .Y(n1263) );
AOI22X1TS U4294 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n3916), .Y(n3415) );
OAI21XLTS U4295 ( .A0(n4762), .A1(n4247), .B0(n3415), .Y(n1235) );
AOI22X1TS U4296 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n4952), .Y(n3416) );
OAI21XLTS U4297 ( .A0(n4761), .A1(n3453), .B0(n3416), .Y(n1259) );
AOI22X1TS U4298 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n4952), .Y(n3417) );
OAI21XLTS U4299 ( .A0(n4757), .A1(n3453), .B0(n3417), .Y(n1211) );
AOI22X1TS U4300 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n4952), .Y(n3418) );
OAI21XLTS U4301 ( .A0(n4649), .A1(n3453), .B0(n3418), .Y(n1271) );
AOI22X1TS U4302 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n3916), .Y(n3419) );
OAI21XLTS U4303 ( .A0(n4643), .A1(n4247), .B0(n3419), .Y(n1223) );
AOI22X1TS U4304 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n3916), .Y(n3420) );
AOI22X1TS U4305 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n3916), .Y(n3421) );
OAI21XLTS U4306 ( .A0(n4749), .A1(n3453), .B0(n3421), .Y(n1255) );
AOI22X1TS U4307 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n3450), .Y(n3422) );
OAI21XLTS U4308 ( .A0(n4760), .A1(n4246), .B0(n3422), .Y(n1286) );
AOI22X1TS U4309 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n3450), .Y(n3423) );
OAI21XLTS U4310 ( .A0(n4758), .A1(n4246), .B0(n3423), .Y(n1415) );
AOI22X1TS U4311 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n3450), .Y(n3424) );
OAI21XLTS U4312 ( .A0(n4754), .A1(n3426), .B0(n3424), .Y(n1367) );
AOI22X1TS U4313 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n3450), .Y(n3425) );
OAI21XLTS U4314 ( .A0(n4751), .A1(n3426), .B0(n3425), .Y(n1314) );
AOI22X1TS U4315 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n3427), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n3450), .Y(n3428) );
OAI21XLTS U4316 ( .A0(n4652), .A1(n3453), .B0(n3428), .Y(n1460) );
AOI22X1TS U4317 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n3450), .Y(n3429) );
OAI21XLTS U4318 ( .A0(n4765), .A1(n4247), .B0(n3429), .Y(n1461) );
AOI22X1TS U4319 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n3427), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n3916), .Y(n3430) );
OAI21XLTS U4320 ( .A0(n4642), .A1(n3453), .B0(n3430), .Y(n1247) );
AOI22X1TS U4321 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n3427), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n4952), .Y(n3431) );
OAI21XLTS U4322 ( .A0(n4641), .A1(n3453), .B0(n3431), .Y(n1328) );
AOI22X1TS U4323 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n3427), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n3916), .Y(n3432) );
OAI21XLTS U4324 ( .A0(n4753), .A1(n4247), .B0(n3432), .Y(n1227) );
AOI22X1TS U4325 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n3427), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n3916), .Y(n3433) );
OAI21XLTS U4326 ( .A0(n4744), .A1(n4247), .B0(n3433), .Y(n1215) );
AOI22X1TS U4327 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3434), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n4368), .Y(n3435) );
OAI21XLTS U4328 ( .A0(n4646), .A1(n3426), .B0(n3435), .Y(n1279) );
CLKBUFX2TS U4329 ( .A(n3916), .Y(n4368) );
AOI222X1TS U4330 ( .A0(n3445), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DMP_EXP_EWSW[23]), .B1(n4368), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3448), .Y(n3436) );
INVX2TS U4331 ( .A(n3436), .Y(n1467) );
AOI22X1TS U4332 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n4952), .Y(n3437) );
OAI21XLTS U4333 ( .A0(n4750), .A1(n3453), .B0(n3437), .Y(n1298) );
NAND3X1TS U4334 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n3438),
.C(n4634), .Y(n3892) );
INVX4TS U4335 ( .A(n3950), .Y(n3948) );
INVX2TS U4336 ( .A(operation[0]), .Y(n3439) );
BUFX4TS U4337 ( .A(n3950), .Y(n3949) );
OAI32X1TS U4338 ( .A0(n3948), .A1(n3439), .A2(n3802), .B0(n4613), .B1(n3949),
.Y(n2082) );
AOI22X1TS U4339 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n3916), .Y(n3440) );
OAI21XLTS U4340 ( .A0(n4760), .A1(n3453), .B0(n3440), .Y(n1284) );
AOI22X1TS U4341 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n3450), .Y(n3441) );
OAI21XLTS U4342 ( .A0(n4754), .A1(n3453), .B0(n3441), .Y(n1267) );
AOI22X1TS U4343 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n3916), .Y(n3442) );
OAI21XLTS U4344 ( .A0(n4752), .A1(n3453), .B0(n3442), .Y(n1239) );
AOI22X1TS U4345 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n3916), .Y(n3443) );
OAI21XLTS U4346 ( .A0(n4648), .A1(n3453), .B0(n3443), .Y(n1243) );
AOI22X1TS U4347 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n3427), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n3450), .Y(n3444) );
OAI21XLTS U4348 ( .A0(n4774), .A1(n4247), .B0(n3444), .Y(n1462) );
AOI22X1TS U4349 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3445), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n4368), .Y(n3446) );
OAI21XLTS U4350 ( .A0(n4646), .A1(n3453), .B0(n3446), .Y(n1277) );
AOI22X1TS U4351 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n3427), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n4368), .Y(n3447) );
OAI21XLTS U4352 ( .A0(n4758), .A1(n4247), .B0(n3447), .Y(n1463) );
INVX2TS U4353 ( .A(n3449), .Y(n1419) );
AOI22X1TS U4354 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3427), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n3450), .Y(n3451) );
OAI21XLTS U4355 ( .A0(n4751), .A1(n3453), .B0(n3451), .Y(n1312) );
AOI22X1TS U4356 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3427), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n3916), .Y(n3452) );
XNOR2X1TS U4357 ( .A(n3459), .B(FPSENCOS_d_ff_Xn[31]), .Y(n3462) );
INVX2TS U4358 ( .A(n3454), .Y(n3914) );
NOR2X2TS U4359 ( .A(n3914), .B(n3455), .Y(n3516) );
BUFX3TS U4360 ( .A(n3516), .Y(n3510) );
BUFX4TS U4361 ( .A(n3510), .Y(n3512) );
XNOR2X1TS U4362 ( .A(FPSENCOS_d_ff1_operation_out), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n3456) );
XNOR2X1TS U4363 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n3456),
.Y(n3457) );
NOR2BX1TS U4364 ( .AN(n3457), .B(n3510), .Y(n3458) );
BUFX4TS U4365 ( .A(n3502), .Y(n3500) );
AOI22X1TS U4366 ( .A0(n3512), .A1(cordic_result[31]), .B0(n3500), .B1(n3460),
.Y(n3461) );
OAI21XLTS U4367 ( .A0(n3462), .A1(n3491), .B0(n3461), .Y(n1697) );
BUFX4TS U4368 ( .A(n3314), .Y(n3481) );
INVX2TS U4369 ( .A(n3463), .Y(n1744) );
INVX2TS U4370 ( .A(n3464), .Y(n1749) );
INVX2TS U4371 ( .A(n3465), .Y(n1747) );
INVX2TS U4372 ( .A(n3466), .Y(n1739) );
INVX2TS U4373 ( .A(n3467), .Y(n1738) );
INVX2TS U4374 ( .A(n3468), .Y(n1737) );
INVX2TS U4375 ( .A(n3469), .Y(n1742) );
INVX2TS U4376 ( .A(n3470), .Y(n1746) );
INVX2TS U4377 ( .A(n3471), .Y(n1741) );
INVX2TS U4378 ( .A(n3472), .Y(n1748) );
INVX2TS U4379 ( .A(n3473), .Y(n1745) );
INVX2TS U4380 ( .A(n3474), .Y(n1740) );
INVX2TS U4381 ( .A(n3475), .Y(n1751) );
INVX2TS U4382 ( .A(n3476), .Y(n1743) );
INVX2TS U4383 ( .A(n3477), .Y(n1758) );
INVX2TS U4384 ( .A(n3478), .Y(n1757) );
INVX2TS U4385 ( .A(n3479), .Y(n1752) );
INVX2TS U4386 ( .A(n3480), .Y(n1750) );
INVX2TS U4387 ( .A(n3483), .Y(n1753) );
INVX4TS U4388 ( .A(n3491), .Y(n3509) );
INVX2TS U4389 ( .A(n3484), .Y(n1705) );
INVX2TS U4390 ( .A(n3485), .Y(n1709) );
INVX2TS U4391 ( .A(n3486), .Y(n1706) );
INVX2TS U4392 ( .A(n3487), .Y(n1708) );
INVX2TS U4393 ( .A(n3488), .Y(n1703) );
INVX2TS U4394 ( .A(n3489), .Y(n1707) );
INVX2TS U4395 ( .A(n3490), .Y(n1704) );
INVX4TS U4396 ( .A(n3491), .Y(n3521) );
INVX2TS U4397 ( .A(n3492), .Y(n1702) );
INVX2TS U4398 ( .A(n3493), .Y(n1724) );
INVX2TS U4399 ( .A(n3494), .Y(n1700) );
INVX2TS U4400 ( .A(n3495), .Y(n1723) );
INVX2TS U4401 ( .A(n3496), .Y(n1725) );
INVX2TS U4402 ( .A(n3497), .Y(n1698) );
INVX2TS U4403 ( .A(n3498), .Y(n1727) );
INVX2TS U4404 ( .A(n3499), .Y(n1701) );
INVX2TS U4405 ( .A(n3501), .Y(n1699) );
INVX2TS U4406 ( .A(n3503), .Y(n1715) );
INVX2TS U4407 ( .A(n3504), .Y(n1716) );
INVX2TS U4408 ( .A(n3505), .Y(n1711) );
INVX2TS U4409 ( .A(n3506), .Y(n1713) );
INVX2TS U4410 ( .A(n3507), .Y(n1714) );
INVX2TS U4411 ( .A(n3508), .Y(n1712) );
INVX2TS U4412 ( .A(n3511), .Y(n1710) );
INVX2TS U4413 ( .A(n3513), .Y(n1717) );
INVX2TS U4414 ( .A(n3514), .Y(n1720) );
INVX2TS U4415 ( .A(n3515), .Y(n1722) );
INVX2TS U4416 ( .A(n3517), .Y(n1718) );
INVX2TS U4417 ( .A(n3518), .Y(n1719) );
INVX2TS U4418 ( .A(n3519), .Y(n1726) );
INVX2TS U4419 ( .A(n3520), .Y(n1721) );
INVX2TS U4420 ( .A(n3522), .Y(n1728) );
OAI221XLTS U4421 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(
FPMULT_FS_Module_state_reg[1]), .B0(n4685), .B1(n4599), .C0(n2225),
.Y(n3523) );
NOR2XLTS U4422 ( .A(n4659), .B(n4780), .Y(FPMULT_S_Oper_A_exp[8]) );
NAND2X1TS U4423 ( .A(n3900), .B(n3899), .Y(n3526) );
NOR2X4TS U4424 ( .A(operation[1]), .B(operation[2]), .Y(n3911) );
AOI22X1TS U4425 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n4625), .B0(n3567), .B1(n4604), .Y(n3527) );
NAND3XLTS U4426 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4604),
.C(n4689), .Y(n3902) );
OAI21XLTS U4427 ( .A0(n3887), .A1(n3527), .B0(n3902), .Y(n2151) );
INVX2TS U4428 ( .A(FPMULT_zero_flag), .Y(n4088) );
AOI22X1TS U4429 ( .A0(FPMULT_FSM_exp_operation_A_S), .A1(n4088), .B0(n4685),
.B1(n2225), .Y(n3529) );
OAI22X1TS U4430 ( .A0(n3529), .A1(n3530), .B0(FPMULT_P_Sgf[47]), .B1(n3528),
.Y(n1694) );
OAI211XLTS U4431 ( .A0(n4088), .A1(n3851), .B0(n4091), .C0(n3531), .Y(n1695)
);
NAND4XLTS U4432 ( .A(n2220), .B(n4673), .C(n4618), .D(n4597), .Y(n3535) );
OR4X2TS U4433 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .D(
n3535), .Y(n3621) );
NOR2X1TS U4434 ( .A(n3621), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n3545) );
NOR2X2TS U4435 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n3534), .Y(n3628) );
INVX2TS U4436 ( .A(n3628), .Y(n3548) );
NOR2X2TS U4437 ( .A(n3548), .B(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n3624) );
NAND2X1TS U4438 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n3624), .Y(n3546) );
OAI22X1TS U4439 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n3546), .B0(n4706),
.B1(n3621), .Y(n3629) );
AOI32X1TS U4440 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n4600), .A2(n4627),
.B0(FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n4600), .Y(n3532) );
NOR3BX1TS U4441 ( .AN(n3624), .B(FPADDSUB_Raw_mant_NRM_SWR[12]), .C(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n3558) );
NOR2X2TS U4442 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n3554), .Y(n3623) );
NAND2X1TS U4443 ( .A(n3623), .B(n4606), .Y(n3536) );
AOI211X1TS U4444 ( .A0(n4629), .A1(n3532), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C0(n3536), .Y(n3533) );
AOI211X1TS U4445 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n3628), .B0(n3629), .C0(n3533), .Y(n3626) );
AOI21X1TS U4446 ( .A0(n4658), .A1(n4601), .B0(n3534), .Y(n3543) );
NAND2X1TS U4447 ( .A(n4700), .B(n4632), .Y(n3630) );
AOI2BB1XLTS U4448 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1N(n3630), .B0(
n3535), .Y(n3538) );
INVX2TS U4449 ( .A(n3536), .Y(n3562) );
NAND3X2TS U4450 ( .A(n3562), .B(n4607), .C(n4629), .Y(n3559) );
OAI22X1TS U4451 ( .A0(n4607), .A1(n3536), .B0(n3559), .B1(n4600), .Y(n3537)
);
NOR4BX1TS U4452 ( .AN(n3626), .B(n3543), .C(n3538), .D(n3537), .Y(n3541) );
INVX2TS U4453 ( .A(n4038), .Y(n4041) );
OAI21XLTS U4454 ( .A0(n2287), .A1(n3564), .B0(n3539), .Y(n2079) );
NAND2X1TS U4455 ( .A(n3918), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n3540)
);
INVX2TS U4456 ( .A(n3559), .Y(n3550) );
NOR2X1TS U4457 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n3556) );
NAND3XLTS U4458 ( .A(n4619), .B(n4598), .C(n4677), .Y(n3544) );
NOR2X2TS U4459 ( .A(n4707), .B(n3542), .Y(n3633) );
AOI211X1TS U4460 ( .A0(n3545), .A1(n3544), .B0(n3633), .C0(n3543), .Y(n3547)
);
OAI211XLTS U4461 ( .A0(n3548), .A1(n4635), .B0(n3547), .C0(n3546), .Y(n3549)
);
AOI31X1TS U4462 ( .A0(n3550), .A1(n3556), .A2(FPADDSUB_Raw_mant_NRM_SWR[1]),
.B0(n3549), .Y(n3553) );
OAI21XLTS U4463 ( .A0(n3553), .A1(n3564), .B0(n3551), .Y(n2078) );
NAND2X1TS U4464 ( .A(n3918), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n3552)
);
OAI21XLTS U4465 ( .A0(n3553), .A1(n3918), .B0(n3552), .Y(n1324) );
OAI21X1TS U4466 ( .A0(n3556), .A1(n3559), .B0(n3555), .Y(n3632) );
NAND2X1TS U4467 ( .A(n4624), .B(n4605), .Y(n3557) );
AOI22X1TS U4468 ( .A0(n3623), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n3558),
.B1(n3557), .Y(n3560) );
AOI32X1TS U4469 ( .A0(n4627), .A1(n3560), .A2(n4775), .B0(n3559), .B1(n3560),
.Y(n3561) );
AOI211X1TS U4470 ( .A0(n3562), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n3632),
.C0(n3561), .Y(n3566) );
NAND2X1TS U4471 ( .A(n3918), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n3563)
);
OAI21XLTS U4472 ( .A0(n3566), .A1(n3918), .B0(n3563), .Y(n1332) );
OAI21XLTS U4473 ( .A0(n3566), .A1(n3564), .B0(n3565), .Y(n2077) );
AOI22X1TS U4474 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n3887), .B0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n4604),
.Y(n3915) );
NAND2X4TS U4475 ( .A(n3915), .B(n3567), .Y(n3568) );
INVX2TS U4476 ( .A(n3573), .Y(n3575) );
AOI2BB2XLTS U4477 ( .B0(FPSENCOS_d_ff3_sign_out), .B1(n4611), .A0N(n4611),
.A1N(FPSENCOS_d_ff3_sign_out), .Y(n3571) );
BUFX4TS U4478 ( .A(n4031), .Y(n4056) );
NOR2X2TS U4479 ( .A(operation[1]), .B(n4056), .Y(n3569) );
BUFX3TS U4480 ( .A(n3569), .Y(n3592) );
BUFX4TS U4481 ( .A(n3592), .Y(n4032) );
BUFX4TS U4482 ( .A(n4031), .Y(n3745) );
AOI22X1TS U4483 ( .A0(operation[0]), .A1(n4032), .B0(FPADDSUB_intAS), .B1(
n3745), .Y(n3570) );
INVX2TS U4484 ( .A(n3572), .Y(overflow_flag) );
INVX3TS U4485 ( .A(n2199), .Y(n3751) );
BUFX4TS U4486 ( .A(n3592), .Y(n4006) );
AOI22X1TS U4487 ( .A0(Data_2[0]), .A1(n4006), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n4056), .Y(n3577) );
NOR3X1TS U4488 ( .A(FPSENCOS_cont_var_out[1]), .B(n4611), .C(n3575), .Y(
n3574) );
BUFX4TS U4489 ( .A(n3574), .Y(n3991) );
BUFX4TS U4490 ( .A(n3599), .Y(n3640) );
BUFX4TS U4491 ( .A(n3640), .Y(n3665) );
AOI22X1TS U4492 ( .A0(n3991), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n3665),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n3576) );
AOI22X1TS U4493 ( .A0(Data_1[31]), .A1(n4006), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n4056), .Y(n3579) );
AOI22X1TS U4494 ( .A0(n3991), .A1(FPSENCOS_d_ff2_X[31]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n3578) );
AOI22X1TS U4495 ( .A0(Data_1[30]), .A1(n4006), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n4056), .Y(n3581) );
AOI22X1TS U4496 ( .A0(n3991), .A1(FPSENCOS_d_ff2_X[30]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n3580) );
AOI22X1TS U4497 ( .A0(Data_1[26]), .A1(n4006), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n3745), .Y(n3583) );
AOI22X1TS U4498 ( .A0(n3991), .A1(FPSENCOS_d_ff2_X[26]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n3582) );
AOI22X1TS U4499 ( .A0(Data_1[28]), .A1(n4006), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n3745), .Y(n3585) );
AOI22X1TS U4500 ( .A0(n3991), .A1(FPSENCOS_d_ff2_X[28]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n3584) );
AOI22X1TS U4501 ( .A0(Data_1[29]), .A1(n4006), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n4056), .Y(n3587) );
AOI22X1TS U4502 ( .A0(n3991), .A1(FPSENCOS_d_ff2_X[29]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n3586) );
AOI22X1TS U4503 ( .A0(Data_1[27]), .A1(n4006), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n3745), .Y(n3589) );
AOI22X1TS U4504 ( .A0(n3991), .A1(FPSENCOS_d_ff2_X[27]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n3588) );
BUFX4TS U4505 ( .A(n3592), .Y(n4016) );
AOI22X1TS U4506 ( .A0(Data_1[24]), .A1(n4016), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n3745), .Y(n3591) );
AOI22X1TS U4507 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[24]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n3590) );
AOI22X1TS U4508 ( .A0(Data_1[25]), .A1(n3592), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n3745), .Y(n3594) );
AOI22X1TS U4509 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[25]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n3593) );
CLKINVX6TS U4510 ( .A(n3990), .Y(n3748) );
AOI22X1TS U4511 ( .A0(Data_1[20]), .A1(n3569), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n3745), .Y(n3596) );
AOI22X1TS U4512 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[20]), .B0(n3640), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n3595) );
AOI22X1TS U4513 ( .A0(Data_1[15]), .A1(n4006), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n4031), .Y(n3598) );
AOI22X1TS U4514 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[15]), .B0(n3640), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n3597) );
AOI22X1TS U4515 ( .A0(Data_1[13]), .A1(n4032), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n4031), .Y(n3601) );
AOI22X1TS U4516 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[13]), .B0(n3599), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n3600) );
AOI22X1TS U4517 ( .A0(Data_1[19]), .A1(n3569), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n3745), .Y(n3603) );
AOI22X1TS U4518 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[19]), .B0(n4026), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n3602) );
AOI22X1TS U4519 ( .A0(Data_1[18]), .A1(n4032), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n3745), .Y(n3605) );
AOI22X1TS U4520 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[18]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n3604) );
AOI22X1TS U4521 ( .A0(Data_1[21]), .A1(n4032), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n3745), .Y(n3607) );
AOI22X1TS U4522 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[21]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n3606) );
AOI22X1TS U4523 ( .A0(Data_1[17]), .A1(n4016), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n3745), .Y(n3609) );
AOI22X1TS U4524 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[17]), .B0(n4026), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n3608) );
AOI22X1TS U4525 ( .A0(Data_1[22]), .A1(n4032), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n3745), .Y(n3611) );
AOI22X1TS U4526 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[22]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n3610) );
AOI22X1TS U4527 ( .A0(Data_1[14]), .A1(n4006), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n4031), .Y(n3613) );
AOI22X1TS U4528 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4026), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n3612) );
AOI22X1TS U4529 ( .A0(Data_1[16]), .A1(n4032), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n4031), .Y(n3615) );
AOI22X1TS U4530 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[16]), .B0(n3640), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n3614) );
AOI22X1TS U4531 ( .A0(Data_1[23]), .A1(n4016), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n3745), .Y(n3617) );
AOI22X1TS U4532 ( .A0(n4012), .A1(FPSENCOS_d_ff2_X[23]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n3616) );
INVX3TS U4533 ( .A(n3564), .Y(n4042) );
AOI222X4TS U4534 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(n4042), .B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .C0(FPADDSUB_Raw_mant_NRM_SWR[24]), .C1(
n3618), .Y(n3795) );
OAI32X1TS U4535 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n4632), .B0(n4597), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3619) );
OAI21XLTS U4536 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n3619), .B0(n2220),
.Y(n3620) );
OAI31X1TS U4537 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n4598), .A2(n3621),
.B0(n3620), .Y(n3622) );
AOI211X1TS U4538 ( .A0(n3623), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n3633),
.C0(n3622), .Y(n3627) );
AOI31X1TS U4539 ( .A0(n3627), .A1(n3626), .A2(n3625), .B0(n3918), .Y(n3855)
);
INVX2TS U4540 ( .A(n3793), .Y(n3673) );
NAND2X1TS U4541 ( .A(n3628), .B(n4635), .Y(n3638) );
INVX2TS U4542 ( .A(n3629), .Y(n3637) );
AOI31XLTS U4543 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n4619), .A2(n4598),
.B0(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n3631) );
OAI211XLTS U4544 ( .A0(n3631), .A1(n3630), .B0(n4618), .C0(n4597), .Y(n3634)
);
AOI211X1TS U4545 ( .A0(n3635), .A1(n3634), .B0(n3633), .C0(n3632), .Y(n3636)
);
OAI211X1TS U4546 ( .A0(n4601), .A1(n3638), .B0(n3637), .C0(n3636), .Y(n3854)
);
NAND2BX1TS U4547 ( .AN(n3672), .B(n4038), .Y(n4039) );
INVX3TS U4548 ( .A(n3675), .Y(n3796) );
NOR2X1TS U4549 ( .A(n4039), .B(n3793), .Y(n3671) );
BUFX3TS U4550 ( .A(n3671), .Y(n3778) );
AOI22X1TS U4551 ( .A0(n4041), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n3778),
.B1(n3792), .Y(n3639) );
OAI21XLTS U4552 ( .A0(n3795), .A1(n3796), .B0(n3639), .Y(n1813) );
INVX3TS U4553 ( .A(n2199), .Y(n3670) );
AOI22X1TS U4554 ( .A0(Data_1[11]), .A1(n3569), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n4031), .Y(n3642) );
BUFX6TS U4555 ( .A(n3991), .Y(n4017) );
AOI22X1TS U4556 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[11]), .B0(n3640), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n3641) );
AOI22X1TS U4557 ( .A0(Data_1[1]), .A1(n4032), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n3568), .Y(n3644) );
AOI22X1TS U4558 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[1]), .B0(n4026), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n3643) );
AOI22X1TS U4559 ( .A0(Data_1[3]), .A1(n4006), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n3745), .Y(n3646) );
AOI22X1TS U4560 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4026), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n3645) );
AOI22X1TS U4561 ( .A0(Data_1[9]), .A1(n3592), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n4031), .Y(n3648) );
AOI22X1TS U4562 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[9]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n3647) );
AOI22X1TS U4563 ( .A0(Data_1[2]), .A1(n4016), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n3745), .Y(n3650) );
AOI22X1TS U4564 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[2]), .B0(n4026), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n3649) );
AOI22X1TS U4565 ( .A0(Data_1[8]), .A1(n3569), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n4031), .Y(n3652) );
AOI22X1TS U4566 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[8]), .B0(n4026), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n3651) );
AOI22X1TS U4567 ( .A0(n4032), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n4056), .Y(n3654) );
AOI22X1TS U4568 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[0]), .B0(
FPSENCOS_d_ff2_Z[0]), .B1(n4026), .Y(n3653) );
AOI22X1TS U4569 ( .A0(Data_1[12]), .A1(n3592), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n4031), .Y(n3656) );
AOI22X1TS U4570 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[12]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n3655) );
AOI22X1TS U4571 ( .A0(Data_1[10]), .A1(n3592), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n4031), .Y(n3658) );
AOI22X1TS U4572 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[10]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n3657) );
AOI22X1TS U4573 ( .A0(Data_1[6]), .A1(n3592), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n4031), .Y(n3660) );
AOI22X1TS U4574 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[6]), .B0(n4026), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n3659) );
AOI22X1TS U4575 ( .A0(Data_1[5]), .A1(n3592), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n4031), .Y(n3662) );
AOI22X1TS U4576 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[5]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n3661) );
AOI22X1TS U4577 ( .A0(Data_1[4]), .A1(n3592), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n3745), .Y(n3664) );
AOI22X1TS U4578 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[4]), .B0(n4026), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n3663) );
AOI22X1TS U4579 ( .A0(Data_1[7]), .A1(n3592), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n4031), .Y(n3667) );
AOI22X1TS U4580 ( .A0(n4017), .A1(FPSENCOS_d_ff2_X[7]), .B0(n3665), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n3666) );
AOI22X1TS U4581 ( .A0(Data_2[9]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n4031), .Y(n3669) );
AOI22X1TS U4582 ( .A0(n4012), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n3668) );
AOI222X4TS U4583 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n3618), .C0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .C1(n3756), .Y(n3693) );
NAND2X1TS U4584 ( .A(n3672), .B(n4038), .Y(n3800) );
AOI22X1TS U4585 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[21]), .A1(n4042), .B0(
FPADDSUB_DmP_mant_SHT1_SW[2]), .B1(n3918), .Y(n3674) );
AOI22X1TS U4586 ( .A0(n4041), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2281),
.B1(n3707), .Y(n3678) );
AOI22X1TS U4587 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[2]), .A1(n3618), .B0(
FPADDSUB_DmP_mant_SHT1_SW[0]), .B1(n3759), .Y(n3676) );
AOI222X4TS U4588 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n3618), .C0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C1(n3756), .Y(n3715) );
INVX2TS U4589 ( .A(n3715), .Y(n3689) );
AOI22X1TS U4590 ( .A0(n3675), .A1(n4043), .B0(n2283), .B1(n3689), .Y(n3677)
);
AOI22X1TS U4591 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n4042), .B0(n3618),
.B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n4047) );
INVX2TS U4592 ( .A(n3693), .Y(n4044) );
AOI22X1TS U4593 ( .A0(n4041), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n2281),
.B1(n4044), .Y(n3680) );
AOI22X1TS U4594 ( .A0(n3778), .A1(n4043), .B0(n2283), .B1(n3707), .Y(n3679)
);
AOI22X1TS U4595 ( .A0(Data_2[10]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n3745), .Y(n3682) );
AOI22X1TS U4596 ( .A0(n4017), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n3681) );
AOI22X1TS U4597 ( .A0(Data_2[4]), .A1(n4006), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n4056), .Y(n3684) );
AOI22X1TS U4598 ( .A0(n3991), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n3683) );
AOI22X1TS U4599 ( .A0(Data_2[6]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n4056), .Y(n3686) );
AOI22X1TS U4600 ( .A0(n3991), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n3685) );
AOI22X1TS U4601 ( .A0(Data_2[2]), .A1(n4006), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n4056), .Y(n3688) );
AOI22X1TS U4602 ( .A0(n3991), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n3687) );
AOI22X1TS U4603 ( .A0(n4041), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2281),
.B1(n3689), .Y(n3692) );
AOI22X1TS U4604 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n4042), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n3759), .Y(n3690) );
AOI22X1TS U4605 ( .A0(n3778), .A1(n3707), .B0(n2283), .B1(n3712), .Y(n3691)
);
AOI222X4TS U4606 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n3618), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n3756), .Y(n3720) );
AOI22X1TS U4607 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n4042), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n3918), .Y(n3694) );
AOI22X1TS U4608 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n2281),
.B1(n3717), .Y(n3697) );
AOI22X1TS U4609 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n4042), .B0(
FPADDSUB_DmP_mant_SHT1_SW[6]), .B1(n3918), .Y(n3695) );
AOI222X4TS U4610 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n3618), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n3756), .Y(n3725) );
INVX2TS U4611 ( .A(n3725), .Y(n3716) );
AOI22X1TS U4612 ( .A0(n3675), .A1(n3711), .B0(n2283), .B1(n3716), .Y(n3696)
);
AOI22X1TS U4613 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n4042), .B0(
FPADDSUB_DmP_mant_SHT1_SW[10]), .B1(n3918), .Y(n3698) );
AOI22X1TS U4614 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2281),
.B1(n3770), .Y(n3700) );
AOI222X4TS U4615 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n3756), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n3618), .Y(n3773) );
INVX2TS U4616 ( .A(n3773), .Y(n3721) );
AOI22X1TS U4617 ( .A0(n3675), .A1(n3717), .B0(n2283), .B1(n3721), .Y(n3699)
);
AOI222X4TS U4618 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n3618), .C0(
FPADDSUB_Raw_mant_NRM_SWR[18]), .C1(n3756), .Y(n3706) );
INVX2TS U4619 ( .A(n3720), .Y(n3703) );
AOI22X1TS U4620 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2281),
.B1(n3703), .Y(n3702) );
AOI22X1TS U4621 ( .A0(n3778), .A1(n3711), .B0(n2283), .B1(n3717), .Y(n3701)
);
AOI22X1TS U4622 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2281),
.B1(n3711), .Y(n3705) );
AOI22X1TS U4623 ( .A0(n3675), .A1(n3712), .B0(n2283), .B1(n3703), .Y(n3704)
);
AOI22X1TS U4624 ( .A0(n4041), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2281),
.B1(n3712), .Y(n3709) );
INVX2TS U4625 ( .A(n3706), .Y(n3710) );
AOI22X1TS U4626 ( .A0(n3675), .A1(n3707), .B0(n2284), .B1(n3710), .Y(n3708)
);
AOI22X1TS U4627 ( .A0(n4041), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n2281),
.B1(n3710), .Y(n3714) );
AOI22X1TS U4628 ( .A0(n3778), .A1(n3712), .B0(n2283), .B1(n3711), .Y(n3713)
);
AOI22X1TS U4629 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2281),
.B1(n3716), .Y(n3719) );
AOI22X1TS U4630 ( .A0(n3778), .A1(n3717), .B0(n2283), .B1(n3770), .Y(n3718)
);
AOI22X1TS U4631 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2281),
.B1(n3721), .Y(n3724) );
AOI22X1TS U4632 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n4042), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n3918), .Y(n3722) );
AOI22X1TS U4633 ( .A0(n3778), .A1(n3770), .B0(n2283), .B1(n3768), .Y(n3723)
);
AOI22X1TS U4634 ( .A0(Data_2[12]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n4056), .Y(n3727) );
AOI22X1TS U4635 ( .A0(n4012), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n4026),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n3726) );
AOI22X1TS U4636 ( .A0(Data_2[21]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n4031), .Y(n3729) );
BUFX3TS U4637 ( .A(n3991), .Y(n4057) );
AOI22X1TS U4638 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n4026),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n3728) );
AOI22X1TS U4639 ( .A0(Data_2[25]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n3568), .Y(n3731) );
AOI22X1TS U4640 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n3730) );
AOI22X1TS U4641 ( .A0(Data_2[26]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n3745), .Y(n3733) );
AOI22X1TS U4642 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n3732) );
AOI222X4TS U4643 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[4]), .B1(n3756), .C0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .C1(n3618), .Y(n3753) );
AOI222X4TS U4644 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n3756), .C0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .C1(n3618), .Y(n3797) );
INVX2TS U4645 ( .A(n3797), .Y(n3738) );
AOI22X1TS U4646 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n2282),
.B1(n3738), .Y(n3736) );
AOI22X1TS U4647 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[22]), .A1(n3618), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n3759), .Y(n3734) );
INVX2TS U4648 ( .A(n3795), .Y(n3789) );
AOI22X1TS U4649 ( .A0(n3778), .A1(n3787), .B0(n2283), .B1(n3789), .Y(n3735)
);
AOI22X1TS U4650 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2282),
.B1(n3787), .Y(n3740) );
AOI22X1TS U4651 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[20]), .A1(n3618), .B0(
FPADDSUB_DmP_mant_SHT1_SW[18]), .B1(n3759), .Y(n3737) );
AOI22X1TS U4652 ( .A0(n3675), .A1(n2292), .B0(n2284), .B1(n3738), .Y(n3739)
);
AOI22X1TS U4653 ( .A0(Data_2[8]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n4056), .Y(n3742) );
AOI22X1TS U4654 ( .A0(n4017), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n4026),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n3741) );
AOI22X1TS U4655 ( .A0(Data_2[23]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n4056), .Y(n3744) );
AOI22X1TS U4656 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n3743) );
AOI22X1TS U4657 ( .A0(Data_2[24]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n3745), .Y(n3747) );
AOI22X1TS U4658 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n3746) );
AOI22X1TS U4659 ( .A0(Data_2[1]), .A1(n4006), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n4056), .Y(n3750) );
AOI22X1TS U4660 ( .A0(n3991), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n3640),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n3749) );
AOI222X4TS U4661 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n3756), .C0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .C1(n3618), .Y(n3777) );
AOI22X1TS U4662 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2282),
.B1(n2292), .Y(n3755) );
AOI22X1TS U4663 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n4042), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n3759), .Y(n3752) );
INVX2TS U4664 ( .A(n3753), .Y(n3774) );
AOI22X1TS U4665 ( .A0(n3675), .A1(n3781), .B0(n2284), .B1(n3774), .Y(n3754)
);
AOI222X4TS U4666 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n3756), .C0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n3618), .Y(n3765) );
AOI22X1TS U4667 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n4042), .B0(
FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(n3759), .Y(n3757) );
AOI22X1TS U4668 ( .A0(n3788), .A1(n2300), .B0(n2282), .B1(n3783), .Y(n3761)
);
AOI222X4TS U4669 ( .A0(n3759), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n4042), .C0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n3618), .Y(n3786) );
INVX2TS U4670 ( .A(n3786), .Y(n3762) );
AOI22X1TS U4671 ( .A0(n3675), .A1(n3768), .B0(n2284), .B1(n3762), .Y(n3760)
);
AOI22X1TS U4672 ( .A0(n3788), .A1(n2299), .B0(n2282), .B1(n3762), .Y(n3764)
);
AOI22X1TS U4673 ( .A0(n3778), .A1(n3783), .B0(n2284), .B1(n3781), .Y(n3763)
);
INVX2TS U4674 ( .A(n3765), .Y(n3769) );
AOI22X1TS U4675 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n2282),
.B1(n3769), .Y(n3767) );
AOI22X1TS U4676 ( .A0(n3778), .A1(n3768), .B0(n2284), .B1(n3783), .Y(n3766)
);
AOI22X1TS U4677 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2282),
.B1(n3768), .Y(n3772) );
AOI22X1TS U4678 ( .A0(n3675), .A1(n3770), .B0(n2284), .B1(n3769), .Y(n3771)
);
AOI22X1TS U4679 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2282),
.B1(n3774), .Y(n3776) );
AOI22X1TS U4680 ( .A0(n3778), .A1(n2292), .B0(n2284), .B1(n3787), .Y(n3775)
);
INVX2TS U4681 ( .A(n3777), .Y(n3782) );
AOI22X1TS U4682 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2282),
.B1(n3782), .Y(n3780) );
AOI22X1TS U4683 ( .A0(n3778), .A1(n3781), .B0(n2284), .B1(n2292), .Y(n3779)
);
AOI22X1TS U4684 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2282),
.B1(n3781), .Y(n3785) );
AOI22X1TS U4685 ( .A0(n3675), .A1(n3783), .B0(n2284), .B1(n3782), .Y(n3784)
);
AOI22X1TS U4686 ( .A0(n3788), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n3675),
.B1(n3787), .Y(n3791) );
AOI22X1TS U4687 ( .A0(n2282), .A1(n3789), .B0(n2284), .B1(n3792), .Y(n3790)
);
AOI21X1TS U4688 ( .A0(n3793), .A1(n3792), .B0(n3618), .Y(n4040) );
OAI22X1TS U4689 ( .A0(n3797), .A1(n3796), .B0(n3795), .B1(n3794), .Y(n3798)
);
AOI21X1TS U4690 ( .A0(n4041), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n3798),
.Y(n3799) );
OAI21XLTS U4691 ( .A0(n4040), .A1(n3800), .B0(n3799), .Y(n1812) );
BUFX3TS U4692 ( .A(n3801), .Y(n3832) );
AOI22X1TS U4693 ( .A0(cordic_result[0]), .A1(n3804), .B0(n3910), .B1(
mult_result[0]), .Y(n3803) );
OAI21XLTS U4694 ( .A0(n3832), .A1(n4728), .B0(n3803), .Y(op_result[0]) );
BUFX6TS U4695 ( .A(n3804), .Y(n3913) );
AOI22X1TS U4696 ( .A0(n3913), .A1(cordic_result[9]), .B0(n3910), .B1(
mult_result[9]), .Y(n3805) );
OAI21XLTS U4697 ( .A0(n3801), .A1(n4730), .B0(n3805), .Y(op_result[9]) );
AOI22X1TS U4698 ( .A0(n3913), .A1(cordic_result[7]), .B0(n3910), .B1(
mult_result[7]), .Y(n3806) );
OAI21XLTS U4699 ( .A0(n3801), .A1(n4727), .B0(n3806), .Y(op_result[7]) );
AOI22X1TS U4700 ( .A0(n3913), .A1(cordic_result[11]), .B0(n3910), .B1(
mult_result[11]), .Y(n3807) );
OAI21XLTS U4701 ( .A0(n3801), .A1(n4721), .B0(n3807), .Y(op_result[11]) );
AOI22X1TS U4702 ( .A0(n3913), .A1(cordic_result[8]), .B0(n3910), .B1(
mult_result[8]), .Y(n3808) );
OAI21XLTS U4703 ( .A0(n3801), .A1(n4720), .B0(n3808), .Y(op_result[8]) );
AOI22X1TS U4704 ( .A0(n3913), .A1(cordic_result[2]), .B0(n3910), .B1(
mult_result[2]), .Y(n3809) );
OAI21XLTS U4705 ( .A0(n3832), .A1(n4726), .B0(n3809), .Y(op_result[2]) );
AOI22X1TS U4706 ( .A0(n3913), .A1(cordic_result[10]), .B0(n3910), .B1(
mult_result[10]), .Y(n3810) );
OAI21XLTS U4707 ( .A0(n3801), .A1(n4723), .B0(n3810), .Y(op_result[10]) );
AOI22X1TS U4708 ( .A0(cordic_result[4]), .A1(n3913), .B0(n3910), .B1(
mult_result[4]), .Y(n3811) );
OAI21XLTS U4709 ( .A0(n3801), .A1(n4716), .B0(n3811), .Y(op_result[4]) );
AOI22X1TS U4710 ( .A0(cordic_result[6]), .A1(n3913), .B0(n3910), .B1(
mult_result[6]), .Y(n3812) );
OAI21XLTS U4711 ( .A0(n3801), .A1(n4717), .B0(n3812), .Y(op_result[6]) );
BUFX3TS U4712 ( .A(n3913), .Y(n3907) );
AOI22X1TS U4713 ( .A0(cordic_result[27]), .A1(n3907), .B0(n3166), .B1(
mult_result[27]), .Y(n3813) );
OAI21XLTS U4714 ( .A0(n3832), .A1(n4737), .B0(n3813), .Y(op_result[27]) );
AOI22X1TS U4715 ( .A0(cordic_result[22]), .A1(n3907), .B0(n3910), .B1(
mult_result[22]), .Y(n3814) );
OAI21XLTS U4716 ( .A0(n3832), .A1(n4709), .B0(n3814), .Y(op_result[22]) );
AOI22X1TS U4717 ( .A0(cordic_result[18]), .A1(n3913), .B0(n3166), .B1(
mult_result[18]), .Y(n3815) );
AOI22X1TS U4718 ( .A0(cordic_result[3]), .A1(n3913), .B0(n3910), .B1(
mult_result[3]), .Y(n3816) );
OAI21XLTS U4719 ( .A0(n3801), .A1(n4725), .B0(n3816), .Y(op_result[3]) );
AOI22X1TS U4720 ( .A0(n3913), .A1(cordic_result[1]), .B0(n3910), .B1(
mult_result[1]), .Y(n3817) );
OAI21XLTS U4721 ( .A0(n3801), .A1(n4729), .B0(n3817), .Y(op_result[1]) );
AOI22X1TS U4722 ( .A0(cordic_result[17]), .A1(n3913), .B0(n3166), .B1(
mult_result[17]), .Y(n3818) );
AOI22X1TS U4723 ( .A0(cordic_result[26]), .A1(n3907), .B0(n3166), .B1(
mult_result[26]), .Y(n3819) );
OAI21XLTS U4724 ( .A0(n3832), .A1(n4739), .B0(n3819), .Y(op_result[26]) );
AOI22X1TS U4725 ( .A0(cordic_result[19]), .A1(n3907), .B0(n3166), .B1(
mult_result[19]), .Y(n3820) );
OAI21XLTS U4726 ( .A0(n3832), .A1(n4713), .B0(n3820), .Y(op_result[19]) );
AOI22X1TS U4727 ( .A0(n3913), .A1(cordic_result[14]), .B0(n3166), .B1(
mult_result[14]), .Y(n3821) );
OAI21XLTS U4728 ( .A0(n3801), .A1(n4722), .B0(n3821), .Y(op_result[14]) );
AOI22X1TS U4729 ( .A0(n3913), .A1(cordic_result[12]), .B0(n3910), .B1(
mult_result[12]), .Y(n3822) );
OAI21XLTS U4730 ( .A0(n3801), .A1(n4724), .B0(n3822), .Y(op_result[12]) );
AOI22X1TS U4731 ( .A0(cordic_result[5]), .A1(n3913), .B0(n3166), .B1(
mult_result[5]), .Y(n3823) );
AOI22X1TS U4732 ( .A0(n3913), .A1(cordic_result[13]), .B0(n3166), .B1(
mult_result[13]), .Y(n3824) );
OAI21XLTS U4733 ( .A0(n3801), .A1(n4718), .B0(n3824), .Y(op_result[13]) );
AOI22X1TS U4734 ( .A0(cordic_result[28]), .A1(n3907), .B0(n3166), .B1(
mult_result[28]), .Y(n3825) );
OAI21XLTS U4735 ( .A0(n3832), .A1(n4736), .B0(n3825), .Y(op_result[28]) );
AOI22X1TS U4736 ( .A0(cordic_result[20]), .A1(n3907), .B0(n3166), .B1(
mult_result[20]), .Y(n3826) );
AOI22X1TS U4737 ( .A0(cordic_result[15]), .A1(n3913), .B0(n3166), .B1(
mult_result[15]), .Y(n3827) );
OAI21XLTS U4738 ( .A0(n3801), .A1(n4710), .B0(n3827), .Y(op_result[15]) );
AOI22X1TS U4739 ( .A0(n3913), .A1(cordic_result[16]), .B0(n3166), .B1(
mult_result[16]), .Y(n3828) );
AOI22X1TS U4740 ( .A0(cordic_result[31]), .A1(n3907), .B0(n3910), .B1(
mult_result[31]), .Y(n3829) );
OAI21XLTS U4741 ( .A0(n3832), .A1(n4640), .B0(n3829), .Y(op_result[31]) );
AOI22X1TS U4742 ( .A0(cordic_result[24]), .A1(n3907), .B0(n3166), .B1(
mult_result[24]), .Y(n3830) );
OAI21XLTS U4743 ( .A0(n3832), .A1(n4738), .B0(n3830), .Y(op_result[24]) );
AOI22X1TS U4744 ( .A0(cordic_result[21]), .A1(n3907), .B0(n3166), .B1(
mult_result[21]), .Y(n3831) );
OAI21XLTS U4745 ( .A0(n3832), .A1(n4712), .B0(n3831), .Y(op_result[21]) );
NAND2X1TS U4746 ( .A(n3899), .B(n3920), .Y(n3888) );
NOR2X2TS U4747 ( .A(ready_add_subt), .B(n3888), .Y(n3924) );
OAI21XLTS U4748 ( .A0(n3924), .A1(n4611), .B0(FPSENCOS_cont_var_out[1]), .Y(
n3833) );
OAI2BB2XLTS U4749 ( .B0(n3856), .B1(n3834), .A0N(n4249), .A1N(
result_add_subt[30]), .Y(n1468) );
NOR3BX1TS U4750 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n3835) );
XOR2X1TS U4751 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3835), .Y(
DP_OP_230J217_125_7006_n15) );
OR2X2TS U4752 ( .A(FPMULT_FSM_selector_B[1]), .B(n4703), .Y(n3842) );
OAI2BB1X1TS U4753 ( .A0N(FPMULT_Op_MY[29]), .A1N(n4708), .B0(n3842), .Y(
n3836) );
XOR2X1TS U4754 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3836), .Y(
DP_OP_230J217_125_7006_n16) );
OAI2BB1X1TS U4755 ( .A0N(FPMULT_Op_MY[28]), .A1N(n4708), .B0(n3842), .Y(
n3837) );
XOR2X1TS U4756 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3837), .Y(
DP_OP_230J217_125_7006_n17) );
OAI2BB1X1TS U4757 ( .A0N(FPMULT_Op_MY[27]), .A1N(n4708), .B0(n3842), .Y(
n3838) );
XOR2X1TS U4758 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3838), .Y(
DP_OP_230J217_125_7006_n18) );
OAI2BB1X1TS U4759 ( .A0N(FPMULT_Op_MY[26]), .A1N(n4708), .B0(n3842), .Y(
n3839) );
XOR2X1TS U4760 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3839), .Y(
DP_OP_230J217_125_7006_n19) );
OAI2BB1X1TS U4761 ( .A0N(FPMULT_Op_MY[25]), .A1N(n4708), .B0(n3842), .Y(
n3840) );
XOR2X1TS U4762 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3840), .Y(
DP_OP_230J217_125_7006_n20) );
OAI2BB1X1TS U4763 ( .A0N(FPMULT_Op_MY[24]), .A1N(n4708), .B0(n3842), .Y(
n3841) );
XOR2X1TS U4764 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3841), .Y(
DP_OP_230J217_125_7006_n21) );
NOR2XLTS U4765 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n3843) );
XOR2X1TS U4766 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n3844), .Y(
DP_OP_230J217_125_7006_n22) );
NOR2BX1TS U4767 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3845) );
XOR2X1TS U4768 ( .A(n2197), .B(n3845), .Y(DP_OP_26J217_122_5882_n14) );
NOR2BX1TS U4769 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3846) );
XOR2X1TS U4770 ( .A(n2197), .B(n3846), .Y(DP_OP_26J217_122_5882_n15) );
NOR2BX1TS U4771 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3847) );
XOR2X1TS U4772 ( .A(n2197), .B(n3847), .Y(DP_OP_26J217_122_5882_n16) );
NOR2BX1TS U4773 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3848) );
XOR2X1TS U4774 ( .A(n2197), .B(n3848), .Y(DP_OP_26J217_122_5882_n17) );
XOR2X1TS U4775 ( .A(n2197), .B(n3849), .Y(DP_OP_26J217_122_5882_n18) );
NAND2X1TS U4776 ( .A(n4087), .B(n4780), .Y(n1691) );
NOR2X4TS U4777 ( .A(n4090), .B(n4187), .Y(n3850) );
MX2X1TS U4778 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n3850), .Y(n1542) );
MX2X1TS U4779 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
MX2X1TS U4780 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n3850), .Y(n1543) );
MX2X1TS U4781 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U4782 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n3850), .Y(n1544) );
MX2X1TS U4783 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U4784 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n3850), .Y(n1545) );
MX2X1TS U4785 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U4786 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n3850), .Y(n1546) );
MX2X1TS U4787 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U4788 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n3850), .Y(n1547) );
MX2X1TS U4789 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U4790 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n3850), .Y(n1548) );
MX2X1TS U4791 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U4792 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n3850), .Y(n1549) );
MX2X1TS U4793 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
BUFX4TS U4794 ( .A(n4066), .Y(n4065) );
MX2X1TS U4795 ( .A(FPMULT_Op_MY[30]), .B(Data_2[30]), .S0(n4065), .Y(n1657)
);
MX2X1TS U4796 ( .A(FPMULT_Op_MY[29]), .B(Data_2[29]), .S0(n4063), .Y(n1656)
);
MX2X1TS U4797 ( .A(FPMULT_Op_MY[28]), .B(Data_2[28]), .S0(n4065), .Y(n1655)
);
MX2X1TS U4798 ( .A(FPMULT_Op_MY[27]), .B(Data_2[27]), .S0(n4063), .Y(n1654)
);
MX2X1TS U4799 ( .A(FPMULT_Op_MY[26]), .B(Data_2[26]), .S0(n4063), .Y(n1653)
);
MX2X1TS U4800 ( .A(FPMULT_Op_MY[25]), .B(Data_2[25]), .S0(n4065), .Y(n1652)
);
MX2X1TS U4801 ( .A(FPMULT_Op_MY[24]), .B(Data_2[24]), .S0(n4065), .Y(n1651)
);
MX2X1TS U4802 ( .A(FPMULT_Op_MY[23]), .B(Data_2[23]), .S0(n4063), .Y(n1650)
);
MX2X1TS U4803 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n3850), .Y(n1541) );
XNOR2X1TS U4804 ( .A(DP_OP_230J217_125_7006_n1), .B(n3851), .Y(n3853) );
MX2X1TS U4805 ( .A(n3853), .B(FPMULT_Exp_module_Overflow_flag_A), .S0(n3852),
.Y(n1540) );
MX2X1TS U4806 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1420) );
MX2X1TS U4807 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1425) );
MX2X1TS U4808 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1430) );
MX2X1TS U4809 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1435) );
MX2X1TS U4810 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1440) );
MX2X1TS U4811 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1445) );
MX2X1TS U4812 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1450) );
MX2X1TS U4813 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1455) );
MX2X1TS U4814 ( .A(n3854), .B(FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n3918),
.Y(n1411) );
AO21XLTS U4815 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n3918), .B0(n3855),
.Y(n1316) );
OA21XLTS U4816 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(
overflow_flag_addsubt), .B0(n3856), .Y(n1413) );
NAND4XLTS U4817 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n3857) );
NAND4BXLTS U4818 ( .AN(n3857), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n3858) );
NAND3BXLTS U4819 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n4090), .C(n3858),
.Y(n3859) );
OAI22X1TS U4820 ( .A0(FPMULT_Exp_module_Data_S[8]), .A1(n3859), .B0(n4090),
.B1(n4787), .Y(n1516) );
NAND2X2TS U4821 ( .A(n4262), .B(n2240), .Y(n3862) );
OA22X1TS U4822 ( .A0(n3862), .A1(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(result_add_subt[29]), .Y(n1469) );
AOI2BB2XLTS U4823 ( .B0(n4249), .B1(n4736), .A0N(n3862), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n1470) );
AOI2BB2XLTS U4824 ( .B0(n4249), .B1(n4737), .A0N(n3862), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(n1471) );
INVX2TS U4825 ( .A(n3862), .Y(n3861) );
AOI22X1TS U4826 ( .A0(n3861), .A1(n3860), .B0(n4249), .B1(n4739), .Y(n1472)
);
OA22X1TS U4827 ( .A0(n3862), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(result_add_subt[25]), .Y(n1473) );
AOI2BB2XLTS U4828 ( .B0(n4249), .B1(n4738), .A0N(n3862), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n1474) );
OA22X1TS U4829 ( .A0(n3862), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(result_add_subt[23]), .Y(n1475) );
NOR4X1TS U4830 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n3869) );
NOR4X1TS U4831 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n3868) );
NOR4X1TS U4832 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n3866) );
NOR3XLTS U4833 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n3865) );
NOR4X1TS U4834 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n3864) );
NOR4X1TS U4835 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n3863) );
AND4X1TS U4836 ( .A(n3866), .B(n3865), .C(n3864), .D(n3863), .Y(n3867) );
NAND3XLTS U4837 ( .A(n3869), .B(n3868), .C(n3867), .Y(n4862) );
NAND4XLTS U4838 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n3871) );
NAND4XLTS U4839 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n3870) );
NOR3X1TS U4840 ( .A(n4947), .B(n3871), .C(n3870), .Y(n3876) );
NOR4X1TS U4841 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[28]), .D(dataB[23]),
.Y(n3873) );
NOR3XLTS U4842 ( .A(dataB[26]), .B(dataB[29]), .C(dataB[25]), .Y(n3872) );
NAND4XLTS U4843 ( .A(n3876), .B(operation_reg[1]), .C(n3873), .D(n3872), .Y(
n3874) );
NOR3XLTS U4844 ( .A(operation_reg[0]), .B(dataB[31]), .C(n3874), .Y(n3875)
);
OAI211XLTS U4845 ( .A0(dataB[27]), .A1(n3875), .B0(n4946), .C0(n4945), .Y(
n3886) );
NOR4X1TS U4846 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[28]), .D(dataA[26]),
.Y(n3879) );
NOR4BX1TS U4847 ( .AN(operation_reg[1]), .B(dataA[31]), .C(dataA[24]), .D(
dataA[25]), .Y(n3878) );
NOR4X1TS U4848 ( .A(n4947), .B(dataA[30]), .C(operation_reg[0]), .D(
dataA[27]), .Y(n3877) );
NOR2BX1TS U4849 ( .AN(n3876), .B(operation_reg[1]), .Y(n3884) );
AOI31XLTS U4850 ( .A0(n3879), .A1(n3878), .A2(n3877), .B0(n3884), .Y(n3882)
);
NAND3XLTS U4851 ( .A(dataB[23]), .B(dataB[28]), .C(dataB[25]), .Y(n3881) );
NAND4XLTS U4852 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n3880) );
OAI31X1TS U4853 ( .A0(n3882), .A1(n3881), .A2(n3880), .B0(dataB[27]), .Y(
n3883) );
NAND4XLTS U4854 ( .A(n4950), .B(n4949), .C(n4948), .D(n3883), .Y(n3885) );
OAI2BB2XLTS U4855 ( .B0(n3886), .B1(n3885), .A0N(n3884), .A1N(
operation_reg[0]), .Y(NaN_reg) );
INVX2TS U4856 ( .A(n3887), .Y(n3903) );
AOI22X1TS U4857 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n3903), .B1(n4604),
.Y(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR3XLTS U4858 ( .A(n3986), .B(n3949), .C(n3888), .Y(n3889) );
NAND3XLTS U4859 ( .A(n3889), .B(n3983), .C(n3900), .Y(n3890) );
CLKAND2X2TS U4860 ( .A(begin_operation), .B(operation[1]), .Y(n3893) );
OAI22X1TS U4861 ( .A0(n3891), .A1(n3890), .B0(n3893), .B1(n3892), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U4862 ( .AN(n3893), .B(n3892), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
NOR3XLTS U4863 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n4631),
.C(n3894), .Y(n3895) );
AO21XLTS U4864 ( .A0(n3921), .A1(n3896), .B0(n3895), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
INVX4TS U4865 ( .A(n3897), .Y(n4051) );
OAI22X1TS U4866 ( .A0(n4051), .A1(n3900), .B0(n3899), .B1(n3898), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
AO22XLTS U4867 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n3901),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
NAND2X1TS U4868 ( .A(n3903), .B(n3902), .Y(n2193) );
AOI22X1TS U4869 ( .A0(cordic_result[30]), .A1(n3907), .B0(n3166), .B1(
mult_result[30]), .Y(n3904) );
OAI2BB1X1TS U4870 ( .A0N(n3911), .A1N(result_add_subt[30]), .B0(n3904), .Y(
op_result[30]) );
AOI22X1TS U4871 ( .A0(cordic_result[29]), .A1(n3907), .B0(n3166), .B1(
mult_result[29]), .Y(n3905) );
OAI2BB1X1TS U4872 ( .A0N(n3911), .A1N(result_add_subt[29]), .B0(n3905), .Y(
op_result[29]) );
AOI22X1TS U4873 ( .A0(cordic_result[25]), .A1(n3907), .B0(n3166), .B1(
mult_result[25]), .Y(n3906) );
OAI2BB1X1TS U4874 ( .A0N(n3911), .A1N(result_add_subt[25]), .B0(n3906), .Y(
op_result[25]) );
AOI22X1TS U4875 ( .A0(cordic_result[23]), .A1(n3907), .B0(n3166), .B1(
mult_result[23]), .Y(n3908) );
OAI2BB1X1TS U4876 ( .A0N(n3911), .A1N(result_add_subt[23]), .B0(n3908), .Y(
op_result[23]) );
AOI22X1TS U4877 ( .A0(n3911), .A1(ready_add_subt), .B0(n3910), .B1(n3909),
.Y(n3912) );
OAI2BB1X1TS U4878 ( .A0N(n3914), .A1N(n3913), .B0(n3912), .Y(operation_ready) );
OAI33X4TS U4879 ( .A0(n4625), .A1(n4604), .A2(n4689), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n3917) );
INVX2TS U4880 ( .A(n3917), .Y(n3919) );
AO22XLTS U4881 ( .A0(n3917), .A1(n4870), .B0(n3919), .B1(n3915), .Y(n2150)
);
AOI22X1TS U4882 ( .A0(n3919), .A1(n3916), .B0(n4540), .B1(n3917), .Y(n2149)
);
AOI22X1TS U4883 ( .A0(n3919), .A1(n4540), .B0(n4861), .B1(n3917), .Y(n2148)
);
AOI22X1TS U4884 ( .A0(n3919), .A1(n4509), .B0(n3918), .B1(n3917), .Y(n2145)
);
AOI22X1TS U4885 ( .A0(n3919), .A1(n3918), .B0(n4249), .B1(n3917), .Y(n2144)
);
AOI22X1TS U4886 ( .A0(n3921), .A1(n4871), .B0(n4951), .B1(n3920), .Y(n2143)
);
AOI2BB2XLTS U4887 ( .B0(n3943), .B1(n3922), .A0N(n3922), .A1N(
FPSENCOS_cont_iter_out[2]), .Y(n2141) );
NAND2X1TS U4888 ( .A(n3943), .B(n3922), .Y(n3923) );
XNOR2X1TS U4889 ( .A(FPSENCOS_cont_iter_out[3]), .B(n3923), .Y(n2140) );
AOI2BB2XLTS U4890 ( .B0(n3924), .B1(n4611), .A0N(n4611), .A1N(n3924), .Y(
n2139) );
AO22XLTS U4891 ( .A0(n3948), .A1(FPSENCOS_d_ff1_shift_region_flag_out[0]),
.B0(n3949), .B1(region_flag[0]), .Y(n2137) );
AO22XLTS U4892 ( .A0(n3948), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B0(n3950), .B1(region_flag[1]), .Y(n2136) );
AOI22X1TS U4893 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n3983), .B0(n3927),
.B1(n3929), .Y(n3926) );
NAND2X1TS U4894 ( .A(n3926), .B(n3925), .Y(n2134) );
AOI22X1TS U4895 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n3961), .B0(n3927),
.B1(n3931), .Y(n3928) );
NAND2X1TS U4896 ( .A(n3928), .B(n3935), .Y(n2130) );
AOI22X1TS U4897 ( .A0(n3978), .A1(n3929), .B0(FPSENCOS_d_ff3_LUT_out[7]),
.B1(n3983), .Y(n3930) );
NAND2X1TS U4898 ( .A(n3930), .B(n3938), .Y(n2128) );
AO22XLTS U4899 ( .A0(n3978), .A1(intadd_491_B_1_), .B0(n3983), .B1(
FPSENCOS_d_ff3_LUT_out[8]), .Y(n2127) );
AOI22X1TS U4900 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n3961), .B0(n3932),
.B1(n3931), .Y(n3933) );
NAND2BXLTS U4901 ( .AN(n3934), .B(n3933), .Y(n2125) );
OAI221XLTS U4902 ( .A0(n3975), .A1(n4859), .B0(n3957), .B1(n3936), .C0(n3935), .Y(n2124) );
BUFX3TS U4903 ( .A(n3978), .Y(n3980) );
AOI2BB2XLTS U4904 ( .B0(n3975), .B1(n2307), .A0N(FPSENCOS_d_ff3_LUT_out[13]),
.A1N(n3980), .Y(n2123) );
BUFX4TS U4905 ( .A(n3978), .Y(n3969) );
AO22XLTS U4906 ( .A0(n3969), .A1(n3937), .B0(n4052), .B1(
FPSENCOS_d_ff3_LUT_out[19]), .Y(n2121) );
OAI221XLTS U4907 ( .A0(n3975), .A1(n4860), .B0(n3957), .B1(n3939), .C0(n3938), .Y(n2120) );
NOR2XLTS U4908 ( .A(n4951), .B(n3940), .Y(n3942) );
AOI22X1TS U4909 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n3987), .B0(n3942),
.B1(n3941), .Y(n3945) );
AOI32X1TS U4910 ( .A0(n3946), .A1(n3945), .A2(n3944), .B0(n3943), .B1(n3945),
.Y(n2117) );
NAND2BXLTS U4911 ( .AN(FPSENCOS_d_ff3_LUT_out[27]), .B(n3957), .Y(n2115) );
AO22XLTS U4912 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n3950), .B1(
Data_1[0]), .Y(n2114) );
AO22XLTS U4913 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n3950), .B1(
Data_1[1]), .Y(n2113) );
AO22XLTS U4914 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n3949), .B1(
Data_1[2]), .Y(n2112) );
AO22XLTS U4915 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n3949), .B1(
Data_1[3]), .Y(n2111) );
INVX4TS U4916 ( .A(n3950), .Y(n3951) );
AO22XLTS U4917 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n3949), .B1(
Data_1[4]), .Y(n2110) );
AO22XLTS U4918 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n3949), .B1(
Data_1[5]), .Y(n2109) );
AO22XLTS U4919 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n3949), .B1(
Data_1[6]), .Y(n2108) );
AO22XLTS U4920 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n3949), .B1(
Data_1[7]), .Y(n2107) );
AO22XLTS U4921 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n3949), .B1(
Data_1[8]), .Y(n2106) );
AO22XLTS U4922 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n3949), .B1(
Data_1[9]), .Y(n2105) );
AO22XLTS U4923 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n3949), .B1(
Data_1[10]), .Y(n2104) );
AO22XLTS U4924 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n3949), .B1(
Data_1[11]), .Y(n2103) );
AO22XLTS U4925 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n3950), .B1(
Data_1[12]), .Y(n2102) );
AO22XLTS U4926 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n3950), .B1(
Data_1[13]), .Y(n2101) );
AO22XLTS U4927 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n3950), .B1(
Data_1[14]), .Y(n2100) );
AO22XLTS U4928 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n3950), .B1(
Data_1[15]), .Y(n2099) );
AO22XLTS U4929 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n3950), .B1(
Data_1[16]), .Y(n2098) );
AO22XLTS U4930 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n3950), .B1(
Data_1[17]), .Y(n2097) );
AO22XLTS U4931 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n3950), .B1(
Data_1[18]), .Y(n2096) );
AO22XLTS U4932 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n3950), .B1(
Data_1[19]), .Y(n2095) );
AO22XLTS U4933 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n3950), .B1(
Data_1[20]), .Y(n2094) );
AO22XLTS U4934 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n3950), .B1(
Data_1[21]), .Y(n2093) );
AO22XLTS U4935 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n3950), .B1(
Data_1[22]), .Y(n2092) );
AO22XLTS U4936 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n3949), .B1(
Data_1[23]), .Y(n2091) );
AO22XLTS U4937 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n3950), .B1(
Data_1[24]), .Y(n2090) );
AO22XLTS U4938 ( .A0(n3948), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n3949), .B1(
Data_1[25]), .Y(n2089) );
AO22XLTS U4939 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n3949), .B1(
Data_1[26]), .Y(n2088) );
AO22XLTS U4940 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n3949), .B1(
Data_1[27]), .Y(n2087) );
AO22XLTS U4941 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n3949), .B1(
Data_1[28]), .Y(n2086) );
AO22XLTS U4942 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n3949), .B1(
Data_1[29]), .Y(n2085) );
AO22XLTS U4943 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n3949), .B1(
Data_1[30]), .Y(n2084) );
AO22XLTS U4944 ( .A0(n3951), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n3950), .B1(
Data_1[31]), .Y(n2083) );
INVX4TS U4945 ( .A(n3897), .Y(n4048) );
AO22XLTS U4946 ( .A0(n4048), .A1(result_add_subt[0]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(n2076) );
INVX4TS U4947 ( .A(n3952), .Y(n4049) );
INVX4TS U4948 ( .A(n3955), .Y(n3953) );
AO22XLTS U4949 ( .A0(n4048), .A1(result_add_subt[1]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(n2073) );
INVX4TS U4950 ( .A(n3952), .Y(n4055) );
AO22XLTS U4951 ( .A0(n4048), .A1(result_add_subt[2]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(n2070) );
AO22XLTS U4952 ( .A0(n4048), .A1(result_add_subt[3]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(n2067) );
INVX4TS U4953 ( .A(n3955), .Y(n4061) );
AO22XLTS U4954 ( .A0(n4048), .A1(result_add_subt[4]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(n2064) );
AO22XLTS U4955 ( .A0(n4048), .A1(result_add_subt[5]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(n2061) );
AO22XLTS U4956 ( .A0(n4048), .A1(result_add_subt[6]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(n2058) );
AO22XLTS U4957 ( .A0(n4048), .A1(result_add_subt[7]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(n2055) );
AO22XLTS U4958 ( .A0(n4051), .A1(result_add_subt[8]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(n2052) );
AO22XLTS U4959 ( .A0(n4048), .A1(result_add_subt[9]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(n2049) );
AO22XLTS U4960 ( .A0(n4051), .A1(result_add_subt[10]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(n2046) );
AO22XLTS U4961 ( .A0(n4048), .A1(result_add_subt[11]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(n2043) );
AO22XLTS U4962 ( .A0(n4051), .A1(result_add_subt[12]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(n2040) );
AO22XLTS U4963 ( .A0(n4051), .A1(result_add_subt[13]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(n2037) );
AO22XLTS U4964 ( .A0(n4051), .A1(result_add_subt[14]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(n2034) );
AO22XLTS U4965 ( .A0(n4051), .A1(result_add_subt[15]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(n2031) );
AO22XLTS U4966 ( .A0(n4051), .A1(result_add_subt[16]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(n2028) );
AO22XLTS U4967 ( .A0(n4051), .A1(result_add_subt[17]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(n2025) );
AO22XLTS U4968 ( .A0(n4051), .A1(result_add_subt[18]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(n2022) );
AO22XLTS U4969 ( .A0(n4051), .A1(result_add_subt[19]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(n2019) );
AO22XLTS U4970 ( .A0(n4051), .A1(result_add_subt[20]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(n2016) );
AO22XLTS U4971 ( .A0(n4048), .A1(result_add_subt[21]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(n2013) );
AO22XLTS U4972 ( .A0(n4048), .A1(result_add_subt[22]), .B0(n3897), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(n2010) );
AO22XLTS U4973 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n3482), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n3972), .Y(n2007) );
OA22X1TS U4974 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[1]), .B1(n3986), .Y(n2005) );
OA22X1TS U4975 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[2]), .B1(n4940), .Y(n2003) );
OA22X1TS U4976 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[3]), .B1(n4940), .Y(n2001) );
AO22XLTS U4977 ( .A0(n3969), .A1(FPSENCOS_d_ff2_X[3]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n2000) );
AO22XLTS U4978 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n3973), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n3972), .Y(n1999) );
OA22X1TS U4979 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[5]), .B1(n4940), .Y(n1997) );
AO22XLTS U4980 ( .A0(n3978), .A1(FPSENCOS_d_ff2_X[5]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1996) );
OA22X1TS U4981 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[6]), .B1(n4940), .Y(n1995) );
OA22X1TS U4982 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[7]), .B1(n4940), .Y(n1993) );
AO22XLTS U4983 ( .A0(n3978), .A1(FPSENCOS_d_ff2_X[7]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1992) );
INVX4TS U4984 ( .A(n4940), .Y(n3971) );
AO22XLTS U4985 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n3971), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n3970), .Y(n1991) );
INVX4TS U4986 ( .A(n3986), .Y(n3967) );
AO22XLTS U4987 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n3967), .B0(
FPSENCOS_d_ff_Xn[9]), .B1(n3972), .Y(n1989) );
OA22X1TS U4988 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[10]), .B1(n4940), .Y(n1987) );
AO22XLTS U4989 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n3971), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n3958), .Y(n1985) );
AO22XLTS U4990 ( .A0(n4053), .A1(FPSENCOS_d_ff2_X[11]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1984) );
OA22X1TS U4991 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[12]), .B1(n4940), .Y(n1983) );
OA22X1TS U4992 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[13]), .B1(n4940), .Y(n1981) );
AO22XLTS U4993 ( .A0(n3969), .A1(FPSENCOS_d_ff2_X[13]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1980) );
OA22X1TS U4994 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[14]), .B1(n4940), .Y(n1979) );
AO22XLTS U4995 ( .A0(n3969), .A1(FPSENCOS_d_ff2_X[14]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1978) );
AO22XLTS U4996 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n3971), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n3958), .Y(n1977) );
AO22XLTS U4997 ( .A0(n3969), .A1(FPSENCOS_d_ff2_X[15]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1976) );
OA22X1TS U4998 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[16]), .B1(n4940), .Y(n1975) );
AO22XLTS U4999 ( .A0(n3980), .A1(FPSENCOS_d_ff2_X[16]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1974) );
OA22X1TS U5000 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[17]), .B1(n3986), .Y(n1973) );
AO22XLTS U5001 ( .A0(n3969), .A1(FPSENCOS_d_ff2_X[17]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1972) );
AO22XLTS U5002 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n3967), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n3958), .Y(n1971) );
AO22XLTS U5003 ( .A0(n4053), .A1(FPSENCOS_d_ff2_X[18]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1970) );
OA22X1TS U5004 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[19]), .B1(n3986), .Y(n1969) );
AO22XLTS U5005 ( .A0(n3969), .A1(FPSENCOS_d_ff2_X[19]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1968) );
OA22X1TS U5006 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[20]), .B1(n3986), .Y(n1967) );
AO22XLTS U5007 ( .A0(n4053), .A1(FPSENCOS_d_ff2_X[20]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1966) );
AO22XLTS U5008 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n3967), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n3970), .Y(n1965) );
AO22XLTS U5009 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n3967), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n3970), .Y(n1963) );
AO22XLTS U5010 ( .A0(n4053), .A1(FPSENCOS_d_ff2_X[22]), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1962) );
AO22XLTS U5011 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n3967), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n3958), .Y(n1961) );
OA22X1TS U5012 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[24]), .B1(n3986), .Y(n1960) );
OA22X1TS U5013 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[25]), .B1(n4940), .Y(n1959) );
OA22X1TS U5014 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[26]), .B1(n3986), .Y(n1958) );
OA22X1TS U5015 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n3308), .B0(
FPSENCOS_d_ff2_X[27]), .B1(n3986), .Y(n1957) );
OA22X1TS U5016 ( .A0(FPSENCOS_d_ff2_X[28]), .A1(n3986), .B0(
FPSENCOS_d_ff_Xn[28]), .B1(n3985), .Y(n1956) );
OA22X1TS U5017 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n3985), .B0(
FPSENCOS_d_ff2_X[29]), .B1(n4940), .Y(n1955) );
AO22XLTS U5018 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n3967), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n3958), .Y(n1954) );
AO22XLTS U5019 ( .A0(n3983), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n3980),
.B1(intadd_492_SUM_0_), .Y(n1952) );
AO22XLTS U5020 ( .A0(n3983), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n3980),
.B1(intadd_492_SUM_1_), .Y(n1951) );
AO22XLTS U5021 ( .A0(n3983), .A1(FPSENCOS_d_ff3_sh_x_out[26]), .B0(n3980),
.B1(intadd_492_SUM_2_), .Y(n1950) );
NOR2X1TS U5022 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_492_n1), .Y(n3960) );
AOI21X1TS U5023 ( .A0(intadd_492_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n3960),
.Y(n3959) );
AOI2BB2XLTS U5024 ( .B0(n3975), .B1(n3959), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n3980), .Y(n1949) );
OAI21XLTS U5025 ( .A0(n3960), .A1(n4785), .B0(n3964), .Y(n3962) );
AO22XLTS U5026 ( .A0(n4053), .A1(n3962), .B0(n3961), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1948) );
AOI21X1TS U5027 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n3964), .B0(n3963), .Y(
n3965) );
AOI2BB2XLTS U5028 ( .B0(n3975), .B1(n3965), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n3980), .Y(n1947) );
AO22XLTS U5029 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n3972), .B0(
FPSENCOS_d_ff2_X[31]), .B1(n3971), .Y(n1945) );
AO22XLTS U5030 ( .A0(n4053), .A1(FPSENCOS_d_ff2_X[31]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1944) );
AO22XLTS U5031 ( .A0(n4048), .A1(result_add_subt[31]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(n1911) );
AOI22X1TS U5032 ( .A0(n4049), .A1(n4640), .B0(n4789), .B1(n4054), .Y(n1910)
);
AO22XLTS U5033 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n3972), .Y(n1909) );
AO22XLTS U5034 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1908) );
AO22XLTS U5035 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n3966), .Y(n1907) );
AO22XLTS U5036 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1906) );
AO22XLTS U5037 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n3966), .Y(n1905) );
AO22XLTS U5038 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1904) );
AO22XLTS U5039 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n3966), .Y(n1903) );
AO22XLTS U5040 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1902) );
AO22XLTS U5041 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n3966), .Y(n1901) );
AO22XLTS U5042 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1900) );
AO22XLTS U5043 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n3973), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n3966), .Y(n1899) );
AO22XLTS U5044 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1898) );
AO22XLTS U5045 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n3972), .Y(n1897) );
AO22XLTS U5046 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1896) );
AO22XLTS U5047 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n3482), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n3966), .Y(n1895) );
AO22XLTS U5048 ( .A0(n3978), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1894) );
AO22XLTS U5049 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n3972), .Y(n1893) );
AO22XLTS U5050 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[8]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1892) );
AO22XLTS U5051 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n3972), .Y(n1891) );
AO22XLTS U5052 ( .A0(n3980), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1890) );
AO22XLTS U5053 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n3972), .Y(n1889) );
AO22XLTS U5054 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[10]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1888) );
AO22XLTS U5055 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n3968), .Y(n1887) );
AO22XLTS U5056 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1886) );
AO22XLTS U5057 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n3967), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n3968), .Y(n1885) );
AO22XLTS U5058 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[12]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1884) );
AO22XLTS U5059 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n3968), .Y(n1883) );
AO22XLTS U5060 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1882) );
AO22XLTS U5061 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n3970), .Y(n1881) );
AO22XLTS U5062 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1880) );
AO22XLTS U5063 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n3970), .Y(n1879) );
AO22XLTS U5064 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1878) );
AO22XLTS U5065 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n3970), .Y(n1877) );
AO22XLTS U5066 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1876) );
AO22XLTS U5067 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n3970), .Y(n1875) );
AO22XLTS U5068 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1874) );
AO22XLTS U5069 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n3970), .Y(n1873) );
AO22XLTS U5070 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1872) );
AO22XLTS U5071 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n3970), .Y(n1871) );
AO22XLTS U5072 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1870) );
AO22XLTS U5073 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n3970), .Y(n1869) );
AO22XLTS U5074 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n3983), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1868) );
AO22XLTS U5075 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n3970), .Y(n1867) );
AO22XLTS U5076 ( .A0(n3969), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1866) );
AO22XLTS U5077 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n3970), .Y(n1865) );
AO22XLTS U5078 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n3983), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1864) );
AO22XLTS U5079 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n3970), .Y(n1863) );
AO22XLTS U5080 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n3970), .Y(n1862) );
AO22XLTS U5081 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n3970), .Y(n1861) );
AO22XLTS U5082 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n3971), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n3970), .Y(n1860) );
AO22XLTS U5083 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n3973), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n3972), .Y(n1859) );
AO22XLTS U5084 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n3482), .B0(
FPSENCOS_d_ff_Yn[28]), .B1(n3972), .Y(n1858) );
AO22XLTS U5085 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n3482), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n3972), .Y(n1857) );
AO22XLTS U5086 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n3973), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n3972), .Y(n1856) );
AOI21X1TS U5087 ( .A0(intadd_491_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n3976),
.Y(n3974) );
AOI2BB2XLTS U5088 ( .B0(n3975), .B1(n3974), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n3980), .Y(n1851) );
NAND2X1TS U5089 ( .A(n3976), .B(n2239), .Y(n3979) );
OAI21XLTS U5090 ( .A0(n3976), .A1(n2239), .B0(n3979), .Y(n3977) );
AO22XLTS U5091 ( .A0(n3978), .A1(n3977), .B0(n3983), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1850) );
AOI21X1TS U5092 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n3979), .B0(n3982), .Y(
n3981) );
AOI2BB2XLTS U5093 ( .B0(n3975), .B1(n3981), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n3980), .Y(n1849) );
AOI2BB2XLTS U5094 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n3982), .A0N(n3982),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n3984) );
AO22XLTS U5095 ( .A0(n3155), .A1(n3984), .B0(n3983), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1848) );
OAI22X1TS U5096 ( .A0(n3986), .A1(n2310), .B0(n4789), .B1(n3985), .Y(n1847)
);
AO22XLTS U5097 ( .A0(n3155), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n3987), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1846) );
AOI22X1TS U5098 ( .A0(Data_2[3]), .A1(n4006), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n4056), .Y(n3989) );
AOI22X1TS U5099 ( .A0(n3991), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n3988) );
NAND2X1TS U5100 ( .A(n4026), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n4007) );
AOI22X1TS U5101 ( .A0(Data_2[5]), .A1(n4006), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n4056), .Y(n3993) );
AOI22X1TS U5102 ( .A0(n3991), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n3992) );
NAND2X1TS U5103 ( .A(n4026), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n4001) );
AOI22X1TS U5104 ( .A0(Data_2[7]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n4056), .Y(n3995) );
AOI22X1TS U5105 ( .A0(n4012), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n3994) );
NAND2X1TS U5106 ( .A(n4026), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n3996) );
AOI22X1TS U5107 ( .A0(Data_2[11]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n3568), .Y(n3998) );
AOI22X1TS U5108 ( .A0(n4017), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n3997) );
AOI22X1TS U5109 ( .A0(Data_2[13]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n3568), .Y(n4000) );
AOI22X1TS U5110 ( .A0(n4012), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n3999) );
NAND2X1TS U5111 ( .A(n4026), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n4013) );
AOI22X1TS U5112 ( .A0(Data_2[14]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n3568), .Y(n4003) );
AOI22X1TS U5113 ( .A0(n4017), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n4002) );
AOI22X1TS U5114 ( .A0(Data_2[15]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n3568), .Y(n4005) );
AOI22X1TS U5115 ( .A0(n4017), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n4004) );
NAND2X1TS U5116 ( .A(n4026), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n4020) );
AOI22X1TS U5117 ( .A0(Data_2[16]), .A1(n4006), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n4031), .Y(n4009) );
AOI22X1TS U5118 ( .A0(n4012), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n4008) );
AOI22X1TS U5119 ( .A0(Data_2[17]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n3568), .Y(n4011) );
AOI22X1TS U5120 ( .A0(n4017), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n4010) );
AOI22X1TS U5121 ( .A0(Data_2[18]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n3568), .Y(n4015) );
AOI22X1TS U5122 ( .A0(n4012), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n4014) );
AOI22X1TS U5123 ( .A0(Data_2[19]), .A1(n4016), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n3568), .Y(n4019) );
AOI22X1TS U5124 ( .A0(n4017), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n4018) );
NAND2X1TS U5125 ( .A(n4026), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n4023) );
AOI22X1TS U5126 ( .A0(Data_2[20]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n3568), .Y(n4022) );
AOI22X1TS U5127 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n4021) );
AOI22X1TS U5128 ( .A0(Data_2[22]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n4056), .Y(n4025) );
AOI22X1TS U5129 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n4024) );
AOI22X1TS U5130 ( .A0(Data_2[27]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n4031), .Y(n4028) );
AOI22X1TS U5131 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n4027) );
NAND2X1TS U5132 ( .A(n4026), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n4033) );
AOI22X1TS U5133 ( .A0(Data_2[28]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n4031), .Y(n4030) );
AOI22X1TS U5134 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n4029) );
AOI22X1TS U5135 ( .A0(Data_2[29]), .A1(n4032), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n4031), .Y(n4035) );
AOI22X1TS U5136 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n2199),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n4034) );
AOI22X1TS U5137 ( .A0(FPSENCOS_d_ff3_sh_x_out[30]), .A1(n2199), .B0(
FPADDSUB_intDY_EWSW[30]), .B1(n3568), .Y(n4037) );
AOI22X1TS U5138 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n3592),
.B1(Data_2[30]), .Y(n4036) );
NAND2X1TS U5139 ( .A(n4037), .B(n4036), .Y(n1815) );
OAI22X1TS U5140 ( .A0(n4040), .A1(n4039), .B0(n4038), .B1(n4772), .Y(n1814)
);
AOI22X1TS U5141 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n4042), .B0(n4041),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n4046) );
AOI22X1TS U5142 ( .A0(n2284), .A1(n4044), .B0(n2282), .B1(n4043), .Y(n4045)
);
AO22XLTS U5143 ( .A0(n4048), .A1(result_add_subt[23]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1788) );
AO22XLTS U5144 ( .A0(n4048), .A1(result_add_subt[24]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(n1785) );
AO22XLTS U5145 ( .A0(n4048), .A1(result_add_subt[25]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1782) );
AO22XLTS U5146 ( .A0(n4048), .A1(result_add_subt[26]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(n1779) );
AO22XLTS U5147 ( .A0(n4051), .A1(result_add_subt[27]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(n1776) );
AO22XLTS U5148 ( .A0(n4051), .A1(result_add_subt[28]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(n1773) );
AO22XLTS U5149 ( .A0(n4051), .A1(result_add_subt[29]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1770) );
AO22XLTS U5150 ( .A0(n4051), .A1(result_add_subt[30]), .B0(n4050), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1767) );
AO22XLTS U5151 ( .A0(n4053), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4052), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1734) );
AOI22X1TS U5152 ( .A0(FPSENCOS_d_ff3_sh_x_out[31]), .A1(n2199), .B0(
FPADDSUB_intDY_EWSW[31]), .B1(n4056), .Y(n4059) );
AOI22X1TS U5153 ( .A0(n4057), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n3592),
.B1(Data_2[31]), .Y(n4058) );
NAND2X1TS U5154 ( .A(n4059), .B(n4058), .Y(n1730) );
AOI22X1TS U5155 ( .A0(n4061), .A1(n4640), .B0(n4803), .B1(n4060), .Y(n1729)
);
AO22XLTS U5156 ( .A0(n4066), .A1(Data_2[31]), .B0(n4062), .B1(
FPMULT_Op_MY[31]), .Y(n1696) );
AO22XLTS U5157 ( .A0(n4065), .A1(Data_1[2]), .B0(n4062), .B1(FPMULT_Op_MX[2]), .Y(n1661) );
AO22XLTS U5158 ( .A0(n4066), .A1(Data_1[31]), .B0(n4062), .B1(
FPMULT_Op_MX[31]), .Y(n1658) );
AO22XLTS U5159 ( .A0(n4066), .A1(Data_2[21]), .B0(n4062), .B1(
FPMULT_Op_MY[21]), .Y(n1648) );
AO22XLTS U5160 ( .A0(n4066), .A1(Data_2[0]), .B0(n2200), .B1(FPMULT_Op_MY[0]), .Y(n1627) );
NOR4X1TS U5161 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[15]), .C(
FPMULT_Op_MY[16]), .D(FPMULT_Op_MY[17]), .Y(n4069) );
NOR4X1TS U5162 ( .A(FPMULT_Op_MY[26]), .B(FPMULT_Op_MY[25]), .C(
FPMULT_Op_MY[30]), .D(FPMULT_Op_MY[24]), .Y(n4068) );
NOR4X1TS U5163 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[11]), .C(
FPMULT_Op_MY[12]), .D(FPMULT_Op_MY[13]), .Y(n4072) );
NAND4XLTS U5164 ( .A(n4074), .B(n4073), .C(n4072), .D(n4071), .Y(n4085) );
NOR4X1TS U5165 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[23]), .D(FPMULT_Op_MX[25]), .Y(n4076) );
NAND4XLTS U5166 ( .A(n4078), .B(n4077), .C(n4076), .D(n4075), .Y(n4084) );
NAND4XLTS U5167 ( .A(n4082), .B(n4081), .C(n4080), .D(n4079), .Y(n4083) );
OA22X1TS U5168 ( .A0(n4086), .A1(n4085), .B0(n4084), .B1(n4083), .Y(n4089)
);
AOI22X1TS U5169 ( .A0(n4090), .A1(n4089), .B0(n4088), .B1(n4087), .Y(n1626)
);
AOI32X1TS U5170 ( .A0(n4093), .A1(n3239), .A2(n4092), .B0(n4795), .B1(n4091),
.Y(n1625) );
INVX3TS U5171 ( .A(n4138), .Y(n4135) );
AOI2BB2XLTS U5172 ( .B0(n4135), .B1(FPMULT_Sgf_normalized_result[0]), .A0N(
FPMULT_Add_result[0]), .A1N(n4143), .Y(n1624) );
NOR2XLTS U5173 ( .A(FPMULT_Sgf_normalized_result[1]), .B(
FPMULT_Sgf_normalized_result[0]), .Y(n4094) );
AOI21X1TS U5174 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(
FPMULT_Sgf_normalized_result[1]), .B0(n4094), .Y(n4095) );
AOI2BB2XLTS U5175 ( .B0(n4135), .B1(n4095), .A0N(FPMULT_Add_result[1]),
.A1N(n4143), .Y(n1623) );
OAI21XLTS U5176 ( .A0(FPMULT_Sgf_normalized_result[1]), .A1(
FPMULT_Sgf_normalized_result[0]), .B0(FPMULT_Sgf_normalized_result[2]),
.Y(n4096) );
AOI32X1TS U5177 ( .A0(n4097), .A1(n4135), .A2(n4096), .B0(n4794), .B1(n4138),
.Y(n1622) );
OAI211XLTS U5178 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4097), .B0(
n4135), .C0(n4099), .Y(n4098) );
OAI2BB1X1TS U5179 ( .A0N(FPMULT_Add_result[3]), .A1N(n4141), .B0(n4098), .Y(
n1621) );
OAI211XLTS U5180 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4101), .B0(
n4135), .C0(n4103), .Y(n4102) );
OAI2BB1X1TS U5181 ( .A0N(FPMULT_Add_result[5]), .A1N(n4141), .B0(n4102), .Y(
n1619) );
AOI21X1TS U5182 ( .A0(n4674), .A1(n4103), .B0(n4105), .Y(n4104) );
OAI211XLTS U5183 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4105), .B0(
n4135), .C0(n4107), .Y(n4106) );
OAI2BB1X1TS U5184 ( .A0N(FPMULT_Add_result[7]), .A1N(n4141), .B0(n4106), .Y(
n1617) );
AOI21X1TS U5185 ( .A0(n4678), .A1(n4107), .B0(n4109), .Y(n4108) );
OAI211XLTS U5186 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4109), .B0(
n4135), .C0(n4111), .Y(n4110) );
OAI2BB1X1TS U5187 ( .A0N(FPMULT_Add_result[9]), .A1N(n4141), .B0(n4110), .Y(
n1615) );
AOI21X1TS U5188 ( .A0(n4679), .A1(n4111), .B0(n4113), .Y(n4112) );
OAI211XLTS U5189 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4113), .B0(
n4135), .C0(n4115), .Y(n4114) );
OAI2BB1X1TS U5190 ( .A0N(FPMULT_Add_result[11]), .A1N(n4141), .B0(n4114),
.Y(n1613) );
AOI21X1TS U5191 ( .A0(n4681), .A1(n4115), .B0(n4117), .Y(n4116) );
OAI211XLTS U5192 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4117), .B0(
n4135), .C0(n4119), .Y(n4118) );
OAI2BB1X1TS U5193 ( .A0N(FPMULT_Add_result[13]), .A1N(n4141), .B0(n4118),
.Y(n1611) );
AOI21X1TS U5194 ( .A0(n4692), .A1(n4119), .B0(n4122), .Y(n4121) );
OAI211XLTS U5195 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4122), .B0(
n4135), .C0(n4124), .Y(n4123) );
OAI2BB1X1TS U5196 ( .A0N(FPMULT_Add_result[15]), .A1N(n4141), .B0(n4123),
.Y(n1609) );
AOI21X1TS U5197 ( .A0(n4732), .A1(n4124), .B0(n4126), .Y(n4125) );
OAI211XLTS U5198 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4126), .B0(
n4135), .C0(n4128), .Y(n4127) );
OAI2BB1X1TS U5199 ( .A0N(FPMULT_Add_result[17]), .A1N(n4141), .B0(n4127),
.Y(n1607) );
AOI21X1TS U5200 ( .A0(n4743), .A1(n4128), .B0(n4130), .Y(n4129) );
OAI2BB1X1TS U5201 ( .A0N(FPMULT_Add_result[19]), .A1N(n4141), .B0(n4131),
.Y(n1605) );
AOI21X1TS U5202 ( .A0(n4767), .A1(n4132), .B0(n4136), .Y(n4133) );
OAI211XLTS U5203 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4136), .B0(
n4135), .C0(n4134), .Y(n4137) );
OAI2BB1X1TS U5204 ( .A0N(FPMULT_Add_result[21]), .A1N(n4141), .B0(n4137),
.Y(n1603) );
AOI21X1TS U5205 ( .A0(n4139), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
n4138), .Y(n4142) );
OAI2BB1X1TS U5206 ( .A0N(FPMULT_Add_result[23]), .A1N(n4141), .B0(n4140),
.Y(n1601) );
AOI2BB1XLTS U5207 ( .A0N(n4143), .A1N(FPMULT_FSM_add_overflow_flag), .B0(
n4142), .Y(n1600) );
ADDFHX4TS U5208 ( .A(mult_x_69_n203), .B(mult_x_69_n198), .CI(n4149), .CO(
n4146), .S(n4150) );
ADDFHX4TS U5209 ( .A(mult_x_69_n209), .B(mult_x_69_n204), .CI(n4151), .CO(
n4149), .S(n4152) );
ADDFHX4TS U5210 ( .A(mult_x_69_n222), .B(mult_x_69_n216), .CI(n4156), .CO(
n4153), .S(n4157) );
INVX4TS U5211 ( .A(n4200), .Y(n4220) );
CMPR32X2TS U5212 ( .A(n4195), .B(mult_x_69_n362), .C(n4194), .CO(n4191), .S(
n4196) );
CMPR32X2TS U5213 ( .A(n4198), .B(mult_x_69_n373), .C(n4197), .CO(n4194), .S(
n4199) );
AO22XLTS U5214 ( .A0(n4220), .A1(FPMULT_P_Sgf[15]), .B0(n4219), .B1(n4218),
.Y(n1568) );
INVX3TS U5215 ( .A(n2314), .Y(n4221) );
AO22XLTS U5216 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n4221), .B0(
mult_result[0]), .B1(n4224), .Y(n1515) );
AO22XLTS U5217 ( .A0(FPMULT_Sgf_normalized_result[1]), .A1(n4221), .B0(
mult_result[1]), .B1(n4224), .Y(n1514) );
AO22XLTS U5218 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n4221), .B0(
mult_result[2]), .B1(n4228), .Y(n1513) );
AO22XLTS U5219 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4221), .B0(
mult_result[3]), .B1(n4224), .Y(n1512) );
AO22XLTS U5220 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n4221), .B0(
mult_result[4]), .B1(n4228), .Y(n1511) );
AO22XLTS U5221 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4221), .B0(
mult_result[5]), .B1(n4224), .Y(n1510) );
AO22XLTS U5222 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n4221), .B0(
mult_result[6]), .B1(n4228), .Y(n1509) );
AO22XLTS U5223 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4221), .B0(
mult_result[7]), .B1(n4224), .Y(n1508) );
AO22XLTS U5224 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n4221), .B0(
mult_result[8]), .B1(n4228), .Y(n1507) );
AO22XLTS U5225 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4221), .B0(
mult_result[9]), .B1(n4228), .Y(n1506) );
AO22XLTS U5226 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n4221), .B0(
mult_result[10]), .B1(n4228), .Y(n1505) );
AO22XLTS U5227 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4221), .B0(
mult_result[11]), .B1(n4228), .Y(n1504) );
AO22XLTS U5228 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n4221), .B0(
mult_result[12]), .B1(n4224), .Y(n1503) );
INVX2TS U5229 ( .A(n2314), .Y(n4222) );
AO22XLTS U5230 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4222), .B0(
mult_result[13]), .B1(n4224), .Y(n1502) );
AO22XLTS U5231 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n4222), .B0(
mult_result[14]), .B1(n4224), .Y(n1501) );
AO22XLTS U5232 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4222), .B0(
mult_result[15]), .B1(n4224), .Y(n1500) );
AO22XLTS U5233 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n4222), .B0(
mult_result[16]), .B1(n4224), .Y(n1499) );
AO22XLTS U5234 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4222), .B0(
mult_result[17]), .B1(n4224), .Y(n1498) );
AO22XLTS U5235 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n4222), .B0(
mult_result[18]), .B1(n4224), .Y(n1497) );
AO22XLTS U5236 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4222), .B0(
mult_result[19]), .B1(n4224), .Y(n1496) );
AO22XLTS U5237 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n4222), .B0(
mult_result[20]), .B1(n4224), .Y(n1495) );
AO22XLTS U5238 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4222), .B0(
mult_result[21]), .B1(n4224), .Y(n1494) );
AO22XLTS U5239 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4222), .B0(
mult_result[22]), .B1(n4224), .Y(n1493) );
OA22X1TS U5240 ( .A0(FPMULT_exp_oper_result[4]), .A1(n2314), .B0(n4223),
.B1(mult_result[27]), .Y(n1488) );
OAI21XLTS U5241 ( .A0(n4226), .A1(underflow_flag_mult), .B0(n4225), .Y(n4227) );
OAI2BB1X1TS U5242 ( .A0N(mult_result[31]), .A1N(n4228), .B0(n4227), .Y(n1483) );
NAND2X1TS U5243 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n4655), .Y(n4231) );
NAND2X1TS U5244 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n4768), .Y(n4239) );
INVX2TS U5245 ( .A(n4239), .Y(n4237) );
NOR2X1TS U5246 ( .A(n4610), .B(FPADDSUB_DMP_EXP_EWSW[24]), .Y(n4235) );
OAI22X1TS U5247 ( .A0(n4237), .A1(n4235), .B0(FPADDSUB_DmP_EXP_EWSW[24]),
.B1(n4612), .Y(n4233) );
AOI22X1TS U5248 ( .A0(FPADDSUB_DMP_EXP_EWSW[25]), .A1(n4663), .B0(n4231),
.B1(n4233), .Y(n4241) );
NOR2X1TS U5249 ( .A(n4660), .B(FPADDSUB_DMP_EXP_EWSW[26]), .Y(n4242) );
AOI21X1TS U5250 ( .A0(FPADDSUB_DMP_EXP_EWSW[26]), .A1(n4660), .B0(n4242),
.Y(n4229) );
XNOR2X1TS U5251 ( .A(n4241), .B(n4229), .Y(n4230) );
AO22XLTS U5252 ( .A0(n4542), .A1(n4230), .B0(n2290), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1480) );
OAI21XLTS U5253 ( .A0(FPADDSUB_DmP_EXP_EWSW[25]), .A1(n4655), .B0(n4231),
.Y(n4232) );
XNOR2X1TS U5254 ( .A(n4233), .B(n4232), .Y(n4234) );
AO22XLTS U5255 ( .A0(n4542), .A1(n4234), .B0(n2290), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1479) );
AOI21X1TS U5256 ( .A0(FPADDSUB_DMP_EXP_EWSW[24]), .A1(n4610), .B0(n4235),
.Y(n4236) );
XNOR2X1TS U5257 ( .A(n4237), .B(n4236), .Y(n4238) );
BUFX4TS U5258 ( .A(n2290), .Y(n4539) );
AO22XLTS U5259 ( .A0(n4542), .A1(n4238), .B0(n4539), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1478) );
OAI21XLTS U5260 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n4768), .B0(n4239),
.Y(n4240) );
AO22XLTS U5261 ( .A0(n4542), .A1(n4240), .B0(n4539), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1477) );
OAI22X1TS U5262 ( .A0(n4242), .A1(n4241), .B0(FPADDSUB_DmP_EXP_EWSW[26]),
.B1(n4662), .Y(n4244) );
XNOR2X1TS U5263 ( .A(FPADDSUB_DmP_EXP_EWSW[27]), .B(
FPADDSUB_DMP_EXP_EWSW[27]), .Y(n4243) );
XOR2XLTS U5264 ( .A(n4244), .B(n4243), .Y(n4245) );
AO22XLTS U5265 ( .A0(n4542), .A1(n4245), .B0(n4539), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1476) );
OAI222X1TS U5266 ( .A0(n4246), .A1(n4661), .B0(n4612), .B1(n4870), .C0(n4602), .C1(n4247), .Y(n1466) );
OAI222X1TS U5267 ( .A0(n4246), .A1(n4782), .B0(n4655), .B1(n4870), .C0(n4609), .C1(n4247), .Y(n1465) );
OAI222X1TS U5268 ( .A0(n4246), .A1(n4781), .B0(n4662), .B1(n4870), .C0(n4608), .C1(n4247), .Y(n1464) );
AO22XLTS U5269 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[23]), .B0(n4539),
.B1(FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1459) );
AO22XLTS U5270 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1458) );
INVX4TS U5271 ( .A(n4546), .Y(n4545) );
BUFX3TS U5272 ( .A(n4546), .Y(n4585) );
BUFX4TS U5273 ( .A(n4585), .Y(n4573) );
AO22XLTS U5274 ( .A0(n4545), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n4573),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1457) );
AO22XLTS U5275 ( .A0(n4520), .A1(FPADDSUB_DMP_SFG[23]), .B0(n4518), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1456) );
AO22XLTS U5276 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n2290),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1454) );
AO22XLTS U5277 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1453) );
AO22XLTS U5278 ( .A0(n4545), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n4573),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1452) );
AO22XLTS U5279 ( .A0(n4520), .A1(FPADDSUB_DMP_SFG[24]), .B0(n4509), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1451) );
AO22XLTS U5280 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n4539),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1449) );
AO22XLTS U5281 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1448) );
AO22XLTS U5282 ( .A0(n4545), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n4573),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1447) );
AO22XLTS U5283 ( .A0(n4520), .A1(FPADDSUB_DMP_SFG[25]), .B0(n4509), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1446) );
AO22XLTS U5284 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n4539),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1444) );
AO22XLTS U5285 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1443) );
AO22XLTS U5286 ( .A0(n4545), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n4573),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1442) );
AO22XLTS U5287 ( .A0(n4520), .A1(FPADDSUB_DMP_SFG[26]), .B0(n4509), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1441) );
AO22XLTS U5288 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n4539),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1439) );
AO22XLTS U5289 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1438) );
AO22XLTS U5290 ( .A0(n4545), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n4573),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1437) );
BUFX4TS U5291 ( .A(n4942), .Y(n4518) );
AO22XLTS U5292 ( .A0(n4520), .A1(FPADDSUB_DMP_SFG[27]), .B0(n4518), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1436) );
AO22XLTS U5293 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n4539),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1434) );
AO22XLTS U5294 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1433) );
AO22XLTS U5295 ( .A0(n4545), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n4573),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1432) );
AO22XLTS U5296 ( .A0(n4520), .A1(FPADDSUB_DMP_SFG[28]), .B0(n4518), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1431) );
AO22XLTS U5297 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n4539),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1429) );
AO22XLTS U5298 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1428) );
AO22XLTS U5299 ( .A0(n4545), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n4573),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1427) );
AO22XLTS U5300 ( .A0(n4520), .A1(FPADDSUB_DMP_SFG[29]), .B0(n4518), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1426) );
AO22XLTS U5301 ( .A0(n4528), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n4539),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1424) );
AO22XLTS U5302 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1423) );
AO22XLTS U5303 ( .A0(n4545), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n4573),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1422) );
AO22XLTS U5304 ( .A0(n4520), .A1(FPADDSUB_DMP_SFG[30]), .B0(n4518), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1421) );
OAI222X1TS U5305 ( .A0(n4247), .A1(n4661), .B0(n4610), .B1(n4870), .C0(n4602), .C1(n4246), .Y(n1418) );
OAI222X1TS U5306 ( .A0(n4247), .A1(n4782), .B0(n4663), .B1(n4870), .C0(n4609), .C1(n4246), .Y(n1417) );
OAI222X1TS U5307 ( .A0(n4247), .A1(n4781), .B0(n4660), .B1(n4870), .C0(n4608), .C1(n4246), .Y(n1416) );
AO21XLTS U5308 ( .A0(underflow_flag_addsubt), .A1(n4249), .B0(n4248), .Y(
n1414) );
INVX2TS U5309 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n4426) );
NOR2X1TS U5310 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(n4773), .Y(n4512) );
NAND2X1TS U5311 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n4763), .Y(n4506) );
NOR2X1TS U5312 ( .A(FPADDSUB_DMP_SFG[20]), .B(n4764), .Y(n4496) );
NAND2X1TS U5313 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n4745), .Y(n4492) );
NOR2X1TS U5314 ( .A(FPADDSUB_DMP_SFG[18]), .B(n4741), .Y(n4484) );
NAND2X1TS U5315 ( .A(FPADDSUB_DmP_mant_SFG_SWR[19]), .B(n4636), .Y(n4480) );
NOR2X1TS U5316 ( .A(FPADDSUB_DMP_SFG[16]), .B(n4705), .Y(n4469) );
NAND2X1TS U5317 ( .A(FPADDSUB_DmP_mant_SFG_SWR[17]), .B(n4694), .Y(n4465) );
NOR2X1TS U5318 ( .A(FPADDSUB_DMP_SFG[14]), .B(n4687), .Y(n4457) );
NAND2X1TS U5319 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n4686), .Y(n4453) );
NOR2X1TS U5320 ( .A(FPADDSUB_DMP_SFG[12]), .B(n4683), .Y(n4445) );
NAND2X1TS U5321 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n4622), .Y(n4441) );
NOR2X1TS U5322 ( .A(FPADDSUB_DMP_SFG[10]), .B(n4680), .Y(n4433) );
NAND2X1TS U5323 ( .A(FPADDSUB_DmP_mant_SFG_SWR[11]), .B(n4676), .Y(n4429) );
NOR2X1TS U5324 ( .A(FPADDSUB_DMP_SFG[8]), .B(n4675), .Y(n4420) );
NAND2X1TS U5325 ( .A(FPADDSUB_DmP_mant_SFG_SWR[9]), .B(n4670), .Y(n4416) );
NOR2X1TS U5326 ( .A(FPADDSUB_DMP_SFG[6]), .B(n4672), .Y(n4408) );
NAND2X1TS U5327 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n4667), .Y(n4404) );
NOR2X1TS U5328 ( .A(FPADDSUB_DMP_SFG[4]), .B(n4669), .Y(n4396) );
NAND2X1TS U5329 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n4665), .Y(n4392) );
NOR2X1TS U5330 ( .A(FPADDSUB_DMP_SFG[2]), .B(n4668), .Y(n4384) );
CLKINVX1TS U5331 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .Y(n4558) );
NAND2X1TS U5332 ( .A(n4558), .B(n4603), .Y(n4374) );
NAND2X1TS U5333 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(n4664), .Y(n4378) );
AOI22X1TS U5334 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n4614), .B0(n4380), .B1(
n4378), .Y(n4386) );
OAI2BB2X1TS U5335 ( .B0(n4384), .B1(n4386), .A0N(n4668), .A1N(
FPADDSUB_DMP_SFG[2]), .Y(n4391) );
AOI22X1TS U5336 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n4615), .B0(n4392), .B1(
n4391), .Y(n4398) );
OAI2BB2X1TS U5337 ( .B0(n4396), .B1(n4398), .A0N(n4669), .A1N(
FPADDSUB_DMP_SFG[4]), .Y(n4403) );
AOI22X1TS U5338 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n4616), .B0(n4404), .B1(
n4403), .Y(n4410) );
OAI2BB2X1TS U5339 ( .B0(n4408), .B1(n4410), .A0N(n4672), .A1N(
FPADDSUB_DMP_SFG[6]), .Y(n4415) );
AOI22X1TS U5340 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n4617), .B0(n4416), .B1(
n4415), .Y(n4422) );
OAI2BB2X1TS U5341 ( .B0(n4420), .B1(n4422), .A0N(n4675), .A1N(
FPADDSUB_DMP_SFG[8]), .Y(n4428) );
AOI22X1TS U5342 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n4620), .B0(n4429), .B1(
n4428), .Y(n4435) );
OAI2BB2X1TS U5343 ( .B0(n4433), .B1(n4435), .A0N(n4680), .A1N(
FPADDSUB_DMP_SFG[10]), .Y(n4440) );
AOI22X1TS U5344 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n4682), .B0(n4441), .B1(
n4440), .Y(n4447) );
OAI2BB2X1TS U5345 ( .B0(n4445), .B1(n4447), .A0N(n4683), .A1N(
FPADDSUB_DMP_SFG[12]), .Y(n4452) );
AOI22X1TS U5346 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n4626), .B0(n4453), .B1(
n4452), .Y(n4459) );
OAI2BB2X1TS U5347 ( .B0(n4457), .B1(n4459), .A0N(n4687), .A1N(
FPADDSUB_DMP_SFG[14]), .Y(n4464) );
AOI22X1TS U5348 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n4630), .B0(n4465), .B1(
n4464), .Y(n4471) );
OAI2BB2X1TS U5349 ( .B0(n4469), .B1(n4471), .A0N(n4705), .A1N(
FPADDSUB_DMP_SFG[16]), .Y(n4479) );
AOI22X1TS U5350 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n4740), .B0(n4480), .B1(
n4479), .Y(n4486) );
OAI2BB2X1TS U5351 ( .B0(n4484), .B1(n4486), .A0N(n4741), .A1N(
FPADDSUB_DMP_SFG[18]), .Y(n4491) );
AOI22X1TS U5352 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n4644), .B0(n4492), .B1(
n4491), .Y(n4498) );
OAI2BB2X1TS U5353 ( .B0(n4496), .B1(n4498), .A0N(n4764), .A1N(
FPADDSUB_DMP_SFG[20]), .Y(n4504) );
AOI22X1TS U5354 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n4651), .B0(n4506), .B1(
n4504), .Y(n4514) );
AOI21X1TS U5355 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n4773), .B0(n4514),
.Y(n4250) );
NAND2X1TS U5356 ( .A(FPADDSUB_DmP_mant_SFG_SWR[2]), .B(FPADDSUB_DMP_SFG[0]),
.Y(n4379) );
AOI222X4TS U5357 ( .A0(n4614), .A1(n4664), .B0(n4614), .B1(n4379), .C0(n4664), .C1(n4379), .Y(n4385) );
AOI222X4TS U5358 ( .A0(n4390), .A1(n4615), .B0(n4390), .B1(n4665), .C0(n4615), .C1(n4665), .Y(n4397) );
AOI222X4TS U5359 ( .A0(n4402), .A1(n4616), .B0(n4402), .B1(n4667), .C0(n4616), .C1(n4667), .Y(n4409) );
AOI222X4TS U5360 ( .A0(n4414), .A1(n4617), .B0(n4414), .B1(n4670), .C0(n4617), .C1(n4670), .Y(n4421) );
AOI222X4TS U5361 ( .A0(n4427), .A1(n4620), .B0(n4427), .B1(n4676), .C0(n4620), .C1(n4676), .Y(n4434) );
AOI222X4TS U5362 ( .A0(n4439), .A1(n4682), .B0(n4439), .B1(n4622), .C0(n4682), .C1(n4622), .Y(n4446) );
AOI222X4TS U5363 ( .A0(n4451), .A1(n4626), .B0(n4451), .B1(n4686), .C0(n4626), .C1(n4686), .Y(n4458) );
AOI222X4TS U5364 ( .A0(n4463), .A1(n4630), .B0(n4463), .B1(n4694), .C0(n4630), .C1(n4694), .Y(n4470) );
AOI222X4TS U5365 ( .A0(n4478), .A1(n4740), .B0(n4478), .B1(n4636), .C0(n4740), .C1(n4636), .Y(n4485) );
AOI222X4TS U5366 ( .A0(n4490), .A1(n4644), .B0(n4490), .B1(n4745), .C0(n4644), .C1(n4745), .Y(n4497) );
AOI222X4TS U5367 ( .A0(n4503), .A1(n4651), .B0(n4503), .B1(n4763), .C0(n4651), .C1(n4763), .Y(n4513) );
INVX3TS U5368 ( .A(n4502), .Y(n4515) );
OAI32X1TS U5369 ( .A0(n4502), .A1(n4512), .A2(n4250), .B0(n4370), .B1(n4515),
.Y(n4251) );
XOR2X1TS U5370 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .B(n4251), .Y(n4252) );
AOI22X1TS U5371 ( .A0(n4511), .A1(n4252), .B0(n2220), .B1(n4518), .Y(n1412)
);
NOR2XLTS U5372 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4253) );
NAND2X2TS U5373 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n4280) );
NAND2BX2TS U5374 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4312) );
NAND2X1TS U5375 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n4748), .Y(n4311)
);
OAI22X1TS U5376 ( .A0(n4653), .A1(n4312), .B0(n4772), .B1(n4311), .Y(n4254)
);
NAND3X1TS U5377 ( .A(n2196), .B(FPADDSUB_shift_value_SHT2_EWR[2]), .C(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4323) );
NOR2XLTS U5378 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4312), .Y(n4256)
);
BUFX4TS U5379 ( .A(n4256), .Y(n4549) );
AOI22X1TS U5380 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n4255), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n4549), .Y(n4259) );
NOR2XLTS U5381 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4311), .Y(n4257)
);
BUFX4TS U5382 ( .A(n4257), .Y(n4548) );
AND2X4TS U5383 ( .A(n4315), .B(n2196), .Y(n4547) );
AOI22X1TS U5384 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[1]), .B1(n4547), .Y(n4258) );
OAI211X1TS U5385 ( .A0(n4292), .A1(n2196), .B0(n4259), .C0(n4258), .Y(n4556)
);
NAND2X1TS U5386 ( .A(n4557), .B(n4320), .Y(n4592) );
INVX2TS U5387 ( .A(n4592), .Y(n4317) );
NOR2X2TS U5388 ( .A(n4315), .B(n4742), .Y(n4308) );
NOR2XLTS U5389 ( .A(n4555), .B(n4260), .Y(n4261) );
AOI211X1TS U5390 ( .A0(n4591), .A1(n4556), .B0(n4317), .C0(n4261), .Y(n4588)
);
OAI22X1TS U5391 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4709), .B0(n4588),
.B1(n2285), .Y(n1410) );
AO22XLTS U5392 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n4539),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1408) );
AOI22X1TS U5393 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n4255), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n4549), .Y(n4266) );
AOI22X1TS U5394 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n4547), .Y(n4265) );
OAI211X1TS U5395 ( .A0(n4555), .A1(n2196), .B0(n4266), .C0(n4265), .Y(n4294)
);
NOR2XLTS U5396 ( .A(n4292), .B(n4260), .Y(n4267) );
AOI211X1TS U5397 ( .A0(n4591), .A1(n4294), .B0(n4317), .C0(n4267), .Y(n4579)
);
OAI22X1TS U5398 ( .A0(n4303), .A1(n4710), .B0(n4579), .B1(n2285), .Y(n1407)
);
AO22XLTS U5399 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[15]), .B0(n4539),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1405) );
AOI22X1TS U5400 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n4547), .Y(n4270) );
AOI22X1TS U5401 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n4255), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n4549), .Y(n4269) );
OAI211X1TS U5402 ( .A0(n2288), .A1(n2196), .B0(n4270), .C0(n4269), .Y(n4477)
);
NOR2XLTS U5403 ( .A(n4475), .B(n4260), .Y(n4272) );
AOI211X1TS U5404 ( .A0(n4591), .A1(n4477), .B0(n4317), .C0(n4272), .Y(n4582)
);
OAI22X1TS U5405 ( .A0(n4303), .A1(n4711), .B0(n4582), .B1(n2285), .Y(n1404)
);
AO22XLTS U5406 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[18]), .B0(n4539),
.B1(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1402) );
AOI22X1TS U5407 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n4547), .Y(n4275) );
AOI22X1TS U5408 ( .A0(n2300), .A1(n4255), .B0(FPADDSUB_Data_array_SWR[6]),
.B1(n4549), .Y(n4274) );
OAI211X1TS U5409 ( .A0(n4535), .A1(n2196), .B0(n4275), .C0(n4274), .Y(n4527)
);
NOR2XLTS U5410 ( .A(n4525), .B(n4260), .Y(n4276) );
AOI211X1TS U5411 ( .A0(n4591), .A1(n4527), .B0(n4317), .C0(n4276), .Y(n4586)
);
OAI22X1TS U5412 ( .A0(n4303), .A1(n4712), .B0(n4586), .B1(n2285), .Y(n1401)
);
AO22XLTS U5413 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n4539),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1399) );
AOI22X1TS U5414 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n4547), .Y(n4278) );
AOI22X1TS U5415 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n4255), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n4549), .Y(n4277) );
OAI211X1TS U5416 ( .A0(n4475), .A1(n2196), .B0(n4278), .C0(n4277), .Y(n4522)
);
NOR2XLTS U5417 ( .A(n2288), .B(n4260), .Y(n4279) );
AOI211X1TS U5418 ( .A0(n4591), .A1(n4522), .B0(n4317), .C0(n4279), .Y(n4583)
);
OAI22X1TS U5419 ( .A0(n4303), .A1(n4713), .B0(n4583), .B1(n2285), .Y(n1398)
);
AO22XLTS U5420 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n4539),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1396) );
AOI22X1TS U5421 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[3]), .B1(n4547), .Y(n4283) );
AOI22X1TS U5422 ( .A0(n2299), .A1(n4255), .B0(FPADDSUB_Data_array_SWR[7]),
.B1(n4549), .Y(n4282) );
OAI211X1TS U5423 ( .A0(n4289), .A1(n2196), .B0(n4283), .C0(n4282), .Y(n4531)
);
NOR2XLTS U5424 ( .A(n4529), .B(n4260), .Y(n4284) );
AOI211X1TS U5425 ( .A0(n4591), .A1(n4531), .B0(n4317), .C0(n4284), .Y(n4584)
);
OAI22X1TS U5426 ( .A0(n4303), .A1(n4714), .B0(n4584), .B1(n2285), .Y(n1395)
);
AO22XLTS U5427 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[20]), .B0(n4543),
.B1(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1393) );
AOI22X1TS U5428 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n4255), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n4549), .Y(n4286) );
AOI22X1TS U5429 ( .A0(n2300), .A1(n4548), .B0(FPADDSUB_Data_array_SWR[6]),
.B1(n4547), .Y(n4285) );
OAI211X1TS U5430 ( .A0(n4529), .A1(n2196), .B0(n4286), .C0(n4285), .Y(n4291)
);
NOR2XLTS U5431 ( .A(n4289), .B(n4260), .Y(n4287) );
AOI211X1TS U5432 ( .A0(n4591), .A1(n4291), .B0(n4317), .C0(n4287), .Y(n4581)
);
OAI22X1TS U5433 ( .A0(n4303), .A1(n4715), .B0(n4581), .B1(n2285), .Y(n1392)
);
AO22XLTS U5434 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[17]), .B0(n4543),
.B1(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1390) );
NOR2XLTS U5435 ( .A(n4289), .B(n4288), .Y(n4290) );
NAND2X1TS U5436 ( .A(n4591), .B(n4320), .Y(n4559) );
INVX2TS U5437 ( .A(n4559), .Y(n4536) );
AOI211X1TS U5438 ( .A0(n4557), .A1(n4291), .B0(n4290), .C0(n4536), .Y(n4567)
);
OAI22X1TS U5439 ( .A0(n4303), .A1(n4716), .B0(n4567), .B1(n2285), .Y(n1389)
);
AO22XLTS U5440 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n4543), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1387) );
NOR2XLTS U5441 ( .A(n4292), .B(n4288), .Y(n4293) );
AOI211X1TS U5442 ( .A0(n4557), .A1(n4294), .B0(n4293), .C0(n4536), .Y(n4569)
);
OAI22X1TS U5443 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4717), .B0(n4569),
.B1(n2286), .Y(n1386) );
AO22XLTS U5444 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n4543), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1384) );
AOI21X1TS U5445 ( .A0(n2300), .A1(n4549), .B0(n4320), .Y(n4296) );
AOI22X1TS U5446 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n4547), .Y(n4295) );
OAI211X1TS U5447 ( .A0(n4770), .A1(n4323), .B0(n4296), .C0(n4295), .Y(n4301)
);
INVX2TS U5448 ( .A(n4548), .Y(n4326) );
NOR2X1TS U5449 ( .A(n4320), .B(n4314), .Y(n4325) );
AOI22X1TS U5450 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4549), .B0(n2299),
.B1(n4547), .Y(n4297) );
OAI211X1TS U5451 ( .A0(n4771), .A1(n4326), .B0(n4325), .C0(n4297), .Y(n4302)
);
AOI22X1TS U5452 ( .A0(n4591), .A1(n4301), .B0(n4302), .B1(n4557), .Y(n4577)
);
OAI22X1TS U5453 ( .A0(n4303), .A1(n4718), .B0(n4577), .B1(n2285), .Y(n1383)
);
AO22XLTS U5454 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n2290),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1381) );
AOI22X1TS U5455 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4255), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n4549), .Y(n4299) );
AOI22X1TS U5456 ( .A0(n2299), .A1(n4548), .B0(FPADDSUB_Data_array_SWR[7]),
.B1(n4547), .Y(n4298) );
OAI211X1TS U5457 ( .A0(n4525), .A1(n2196), .B0(n4299), .C0(n4298), .Y(n4538)
);
NOR2XLTS U5458 ( .A(n4535), .B(n4260), .Y(n4300) );
AOI211X1TS U5459 ( .A0(n4591), .A1(n4538), .B0(n4317), .C0(n4300), .Y(n4580)
);
OAI22X1TS U5460 ( .A0(n4303), .A1(n4719), .B0(n4580), .B1(n2285), .Y(n1380)
);
AO22XLTS U5461 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n4543),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1378) );
AOI22X1TS U5462 ( .A0(n4591), .A1(n4302), .B0(n4301), .B1(n4557), .Y(n4571)
);
OAI22X1TS U5463 ( .A0(n4303), .A1(n4720), .B0(n4571), .B1(n2285), .Y(n1377)
);
AO22XLTS U5464 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n4543), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1375) );
AOI22X1TS U5465 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n4547), .Y(n4305) );
AOI22X1TS U5466 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n4549), .B0(
FPADDSUB_Data_array_SWR[22]), .B1(n4255), .Y(n4304) );
NAND2X1TS U5467 ( .A(n4305), .B(n4304), .Y(n4318) );
AOI22X1TS U5468 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n4547), .Y(n4307) );
AOI22X1TS U5469 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n4549), .B0(
FPADDSUB_Data_array_SWR[23]), .B1(n4255), .Y(n4306) );
NAND2X1TS U5470 ( .A(n4307), .B(n4306), .Y(n4319) );
OAI22X1TS U5471 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4721), .B0(n4575),
.B1(n2286), .Y(n1374) );
AOI22X1TS U5472 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n4255), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n4549), .Y(n4310) );
AOI22X1TS U5473 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n4547), .Y(n4309) );
OAI211X1TS U5474 ( .A0(n4589), .A1(n2196), .B0(n4310), .C0(n4309), .Y(n4524)
);
OAI22X1TS U5475 ( .A0(n4777), .A1(n4312), .B0(n4656), .B1(n4311), .Y(n4313)
);
NOR2XLTS U5476 ( .A(n4553), .B(n4260), .Y(n4316) );
AOI211X1TS U5477 ( .A0(n4591), .A1(n4524), .B0(n4317), .C0(n4316), .Y(n4578)
);
OAI22X1TS U5478 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4722), .B0(n4578),
.B1(n2286), .Y(n1371) );
AO22XLTS U5479 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n4543),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1369) );
AOI221X1TS U5480 ( .A0(n4591), .A1(n4319), .B0(n4557), .B1(n4318), .C0(n4320), .Y(n4574) );
OAI22X1TS U5481 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4723), .B0(n4574),
.B1(n2285), .Y(n1368) );
AO22XLTS U5482 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n4543),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1366) );
AOI21X1TS U5483 ( .A0(n2299), .A1(n4549), .B0(n4320), .Y(n4322) );
AOI22X1TS U5484 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n4547), .Y(n4321) );
OAI211X1TS U5485 ( .A0(n4771), .A1(n4323), .B0(n4322), .C0(n4321), .Y(n4533)
);
AOI22X1TS U5486 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n4549), .B0(n2300),
.B1(n4547), .Y(n4324) );
OAI211X1TS U5487 ( .A0(n4770), .A1(n4326), .B0(n4325), .C0(n4324), .Y(n4534)
);
AOI22X1TS U5488 ( .A0(n4591), .A1(n4533), .B0(n4534), .B1(n4557), .Y(n4576)
);
OAI22X1TS U5489 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4724), .B0(n4576),
.B1(n2286), .Y(n1365) );
AOI22X1TS U5490 ( .A0(n4650), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n4762), .B1(
FPADDSUB_intDY_EWSW[17]), .Y(n4327) );
AOI22X1TS U5491 ( .A0(n4756), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n4744), .B1(
FPADDSUB_intDY_EWSW[15]), .Y(n4328) );
AOI22X1TS U5492 ( .A0(n4755), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n4642), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n4329) );
OAI221XLTS U5493 ( .A0(n4755), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n4642),
.B1(FPADDSUB_intDY_EWSW[13]), .C0(n4329), .Y(n4332) );
AOI22X1TS U5494 ( .A0(n4649), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n4761), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n4330) );
OAI221XLTS U5495 ( .A0(n4649), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n4761),
.B1(FPADDSUB_intDY_EWSW[11]), .C0(n4330), .Y(n4331) );
NOR4X1TS U5496 ( .A(n4334), .B(n4332), .C(n4333), .D(n4331), .Y(n4361) );
AOI22X1TS U5497 ( .A0(n4754), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n4760), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n4335) );
AOI22X1TS U5498 ( .A0(n4652), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n4765), .B1(
FPADDSUB_intDY_EWSW[29]), .Y(n4336) );
OAI221XLTS U5499 ( .A0(n4652), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n4765),
.B1(FPADDSUB_intDY_EWSW[29]), .C0(n4336), .Y(n4341) );
AOI22X1TS U5500 ( .A0(n4774), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n4758), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n4337) );
AOI22X1TS U5501 ( .A0(n4609), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n4759), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n4338) );
OAI221XLTS U5502 ( .A0(n4609), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n4759),
.B1(FPADDSUB_intDY_EWSW[1]), .C0(n4338), .Y(n4339) );
NOR4X1TS U5503 ( .A(n4340), .B(n4341), .C(n4342), .D(n4339), .Y(n4360) );
AOI22X1TS U5504 ( .A0(n4602), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n4747), .B1(
FPADDSUB_intDY_EWSW[23]), .Y(n4343) );
AOI22X1TS U5505 ( .A0(n4757), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n4643), .B1(
FPADDSUB_intDY_EWSW[21]), .Y(n4344) );
OAI221XLTS U5506 ( .A0(n4757), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n4643),
.B1(FPADDSUB_intDY_EWSW[21]), .C0(n4344), .Y(n4357) );
OAI22X1TS U5507 ( .A0(n4753), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n4647), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n4345) );
AOI221X1TS U5508 ( .A0(n4753), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[20]), .B1(n4647), .C0(n4345), .Y(n4346) );
OAI221XLTS U5509 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n4746), .B0(n4766), .B1(
FPADDSUB_intDY_EWSW[7]), .C0(n4346), .Y(n4356) );
OAI22X1TS U5510 ( .A0(n4750), .A1(FPADDSUB_intDY_EWSW[0]), .B0(n4608), .B1(
FPADDSUB_intDY_EWSW[26]), .Y(n4347) );
OAI22X1TS U5511 ( .A0(n4751), .A1(FPADDSUB_intDY_EWSW[2]), .B0(n4641), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n4348) );
AOI221X1TS U5512 ( .A0(n4751), .A1(FPADDSUB_intDY_EWSW[2]), .B0(
FPADDSUB_intDY_EWSW[3]), .B1(n4641), .C0(n4348), .Y(n4353) );
OAI22X1TS U5513 ( .A0(n4752), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n4646), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n4349) );
OAI22X1TS U5514 ( .A0(n4648), .A1(FPADDSUB_intDY_EWSW[6]), .B0(n4749), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n4350) );
AOI221X1TS U5515 ( .A0(n4648), .A1(FPADDSUB_intDY_EWSW[6]), .B0(
FPADDSUB_intDY_EWSW[8]), .B1(n4749), .C0(n4350), .Y(n4351) );
NAND4XLTS U5516 ( .A(n4354), .B(n4353), .C(n4352), .D(n4351), .Y(n4355) );
NOR4X1TS U5517 ( .A(n4358), .B(n4357), .C(n4355), .D(n4356), .Y(n4359) );
AOI31XLTS U5518 ( .A0(n4361), .A1(n4360), .A2(n4359), .B0(n4362), .Y(n4363)
);
CLKXOR2X2TS U5519 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n4367) );
OAI22X1TS U5520 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(n4363), .B0(n4362), .B1(
n4367), .Y(n4364) );
AOI2BB2XLTS U5521 ( .B0(n4870), .B1(n4364), .A0N(FPADDSUB_SIGN_FLAG_EXP),
.A1N(n4870), .Y(n1364) );
AO22XLTS U5522 ( .A0(n4532), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n4539), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1363) );
AO22XLTS U5523 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n4861), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1362) );
AO22XLTS U5524 ( .A0(n4545), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n4573), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1361) );
AO22XLTS U5525 ( .A0(n4520), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n4518), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1360) );
AO22XLTS U5526 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n4365), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n1359) );
AOI2BB2XLTS U5527 ( .B0(FPADDSUB_intDX_EWSW[31]), .B1(n4367), .A0N(n4367),
.A1N(FPADDSUB_intDX_EWSW[31]), .Y(n4369) );
AO22XLTS U5528 ( .A0(n4870), .A1(n4369), .B0(n4368), .B1(
FPADDSUB_OP_FLAG_EXP), .Y(n1357) );
AO22XLTS U5529 ( .A0(n4532), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n4543), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1356) );
AO22XLTS U5530 ( .A0(busy), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n4861), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1355) );
INVX4TS U5531 ( .A(n4546), .Y(n4561) );
AO22XLTS U5532 ( .A0(n4585), .A1(n4515), .B0(n4561), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1354) );
AOI21X1TS U5533 ( .A0(n4370), .A1(n4790), .B0(n4515), .Y(n4371) );
AOI22X1TS U5534 ( .A0(n4511), .A1(n4603), .B0(n4775), .B1(n4518), .Y(n1351)
);
NOR2XLTS U5535 ( .A(n4502), .B(n4603), .Y(n4372) );
OAI32X1TS U5536 ( .A0(n4558), .A1(n4502), .A2(n4603), .B0(
FPADDSUB_DmP_mant_SFG_SWR[1]), .B1(n4372), .Y(n4373) );
AOI22X1TS U5537 ( .A0(n4511), .A1(n4373), .B0(n4627), .B1(n4518), .Y(n1350)
);
NAND2X1TS U5538 ( .A(n4515), .B(n4374), .Y(n4376) );
OAI21XLTS U5539 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(FPADDSUB_DMP_SFG[0]), .B0(n4379), .Y(n4375) );
XNOR2X1TS U5540 ( .A(n4376), .B(n4375), .Y(n4377) );
AOI2BB2XLTS U5541 ( .B0(n4520), .B1(n4377), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[2]), .A1N(n4520), .Y(n1349) );
AOI22X1TS U5542 ( .A0(n4515), .A1(n4380), .B0(n4379), .B1(n4502), .Y(n4381)
);
XNOR2X1TS U5543 ( .A(n4382), .B(n4381), .Y(n4383) );
AOI22X1TS U5544 ( .A0(n4520), .A1(n4383), .B0(n4600), .B1(n4518), .Y(n1348)
);
AOI21X1TS U5545 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(n4668), .B0(n4384), .Y(n4388) );
AOI22X1TS U5546 ( .A0(n4515), .A1(n4386), .B0(n4385), .B1(n4788), .Y(n4387)
);
XNOR2X1TS U5547 ( .A(n4388), .B(n4387), .Y(n4389) );
AOI22X1TS U5548 ( .A0(n4520), .A1(n4389), .B0(n4629), .B1(n4942), .Y(n1347)
);
AOI22X1TS U5549 ( .A0(n4515), .A1(n4391), .B0(n4390), .B1(n4426), .Y(n4394)
);
XNOR2X1TS U5550 ( .A(n4394), .B(n4393), .Y(n4395) );
AOI22X1TS U5551 ( .A0(n4511), .A1(n4395), .B0(n4607), .B1(n4942), .Y(n1346)
);
AOI21X1TS U5552 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(n4669), .B0(n4396), .Y(n4400) );
AOI22X1TS U5553 ( .A0(n4515), .A1(n4398), .B0(n4397), .B1(n4502), .Y(n4399)
);
XNOR2X1TS U5554 ( .A(n4400), .B(n4399), .Y(n4401) );
AOI22X1TS U5555 ( .A0(n4511), .A1(n4401), .B0(n4606), .B1(n4518), .Y(n1345)
);
AOI22X1TS U5556 ( .A0(n4515), .A1(n4403), .B0(n4402), .B1(n4502), .Y(n4406)
);
OAI21XLTS U5557 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n4667), .B0(n4404),
.Y(n4405) );
XNOR2X1TS U5558 ( .A(n4406), .B(n4405), .Y(n4407) );
AOI22X1TS U5559 ( .A0(n4511), .A1(n4407), .B0(n4638), .B1(n4518), .Y(n1344)
);
AOI21X1TS U5560 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(n4672), .B0(n4408), .Y(n4412) );
AOI22X1TS U5561 ( .A0(n4515), .A1(n4410), .B0(n4409), .B1(n4502), .Y(n4411)
);
XNOR2X1TS U5562 ( .A(n4412), .B(n4411), .Y(n4413) );
AOI22X1TS U5563 ( .A0(n4511), .A1(n4413), .B0(n4605), .B1(n4518), .Y(n1343)
);
AOI22X1TS U5564 ( .A0(n4515), .A1(n4415), .B0(n4414), .B1(n4502), .Y(n4418)
);
OAI21XLTS U5565 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n4670), .B0(n4416),
.Y(n4417) );
XNOR2X1TS U5566 ( .A(n4418), .B(n4417), .Y(n4419) );
AOI22X1TS U5567 ( .A0(n4511), .A1(n4419), .B0(n4624), .B1(n4518), .Y(n1342)
);
AOI21X1TS U5568 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(n4675), .B0(n4420), .Y(n4424) );
AOI22X1TS U5569 ( .A0(n4515), .A1(n4422), .B0(n4421), .B1(n4426), .Y(n4423)
);
XNOR2X1TS U5570 ( .A(n4424), .B(n4423), .Y(n4425) );
AOI22X1TS U5571 ( .A0(n4520), .A1(n4425), .B0(n4657), .B1(n4518), .Y(n1341)
);
INVX3TS U5572 ( .A(n4426), .Y(n4505) );
AOI22X1TS U5573 ( .A0(n4505), .A1(n4428), .B0(n4427), .B1(n4426), .Y(n4431)
);
OAI21XLTS U5574 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n4676), .B0(n4429),
.Y(n4430) );
XNOR2X1TS U5575 ( .A(n4431), .B(n4430), .Y(n4432) );
AOI22X1TS U5576 ( .A0(n4511), .A1(n4432), .B0(n4601), .B1(n4518), .Y(n1340)
);
AOI21X1TS U5577 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(n4680), .B0(n4433), .Y(
n4437) );
AOI22X1TS U5578 ( .A0(n4505), .A1(n4435), .B0(n4434), .B1(n4426), .Y(n4436)
);
XNOR2X1TS U5579 ( .A(n4437), .B(n4436), .Y(n4438) );
AOI22X1TS U5580 ( .A0(n4520), .A1(n4438), .B0(n4635), .B1(n4518), .Y(n1339)
);
AOI22X1TS U5581 ( .A0(n4505), .A1(n4440), .B0(n4439), .B1(n4426), .Y(n4443)
);
OAI21XLTS U5582 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n4622), .B0(n4441),
.Y(n4442) );
XNOR2X1TS U5583 ( .A(n4443), .B(n4442), .Y(n4444) );
AOI22X1TS U5584 ( .A0(n4511), .A1(n4444), .B0(n4658), .B1(n4518), .Y(n1338)
);
AOI21X1TS U5585 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(n4683), .B0(n4445), .Y(
n4449) );
AOI22X1TS U5586 ( .A0(n4505), .A1(n4447), .B0(n4446), .B1(n4502), .Y(n4448)
);
XNOR2X1TS U5587 ( .A(n4449), .B(n4448), .Y(n4450) );
AOI22X1TS U5588 ( .A0(n4511), .A1(n4450), .B0(n4707), .B1(n4942), .Y(n1337)
);
AOI22X1TS U5589 ( .A0(n4505), .A1(n4452), .B0(n4451), .B1(n4502), .Y(n4455)
);
OAI21XLTS U5590 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n4686), .B0(n4453),
.Y(n4454) );
XNOR2X1TS U5591 ( .A(n4455), .B(n4454), .Y(n4456) );
AOI22X1TS U5592 ( .A0(n4511), .A1(n4456), .B0(n4677), .B1(n4942), .Y(n1336)
);
AOI21X1TS U5593 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(n4687), .B0(n4457), .Y(
n4461) );
AOI22X1TS U5594 ( .A0(n4505), .A1(n4459), .B0(n4458), .B1(n4502), .Y(n4460)
);
XNOR2X1TS U5595 ( .A(n4461), .B(n4460), .Y(n4462) );
AOI22X1TS U5596 ( .A0(n4520), .A1(n4462), .B0(n4598), .B1(n4509), .Y(n1335)
);
AOI22X1TS U5597 ( .A0(n4505), .A1(n4464), .B0(n4463), .B1(n4502), .Y(n4467)
);
OAI21XLTS U5598 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n4694), .B0(n4465),
.Y(n4466) );
XNOR2X1TS U5599 ( .A(n4467), .B(n4466), .Y(n4468) );
AOI22X1TS U5600 ( .A0(n4511), .A1(n4468), .B0(n4619), .B1(n4509), .Y(n1334)
);
AOI21X1TS U5601 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(n4705), .B0(n4469), .Y(
n4473) );
AOI22X1TS U5602 ( .A0(n4505), .A1(n4471), .B0(n4470), .B1(n4502), .Y(n4472)
);
XNOR2X1TS U5603 ( .A(n4473), .B(n4472), .Y(n4474) );
AOI22X1TS U5604 ( .A0(n4511), .A1(n4474), .B0(n4706), .B1(n4942), .Y(n1333)
);
NOR2XLTS U5605 ( .A(n4475), .B(n4288), .Y(n4476) );
AOI211X1TS U5606 ( .A0(n4557), .A1(n4477), .B0(n4476), .C0(n4536), .Y(n4566)
);
OAI22X1TS U5607 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4725), .B0(n4566),
.B1(n2286), .Y(n1331) );
AO22XLTS U5608 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n4543), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1329) );
AO22XLTS U5609 ( .A0(n4532), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n4543), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1327) );
BUFX4TS U5610 ( .A(n4861), .Y(n4541) );
AO22XLTS U5611 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(n4541), .B1(
FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1326) );
AO22XLTS U5612 ( .A0(n4573), .A1(FPADDSUB_DMP_SFG[3]), .B0(n4545), .B1(
FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1325) );
AOI22X1TS U5613 ( .A0(n4505), .A1(n4479), .B0(n4478), .B1(n4502), .Y(n4482)
);
OAI21XLTS U5614 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n4636), .B0(n4480),
.Y(n4481) );
XNOR2X1TS U5615 ( .A(n4482), .B(n4481), .Y(n4483) );
AOI2BB2XLTS U5616 ( .B0(n4520), .B1(n4483), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[19]), .A1N(n4520), .Y(n1323) );
AOI21X1TS U5617 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(n4741), .B0(n4484), .Y(
n4488) );
AOI22X1TS U5618 ( .A0(n4505), .A1(n4486), .B0(n4485), .B1(n4502), .Y(n4487)
);
XNOR2X1TS U5619 ( .A(n4488), .B(n4487), .Y(n4489) );
AOI22X1TS U5620 ( .A0(n4511), .A1(n4489), .B0(n4632), .B1(n4509), .Y(n1322)
);
AOI22X1TS U5621 ( .A0(n4505), .A1(n4491), .B0(n4490), .B1(n4502), .Y(n4494)
);
XNOR2X1TS U5622 ( .A(n4494), .B(n4493), .Y(n4495) );
AOI22X1TS U5623 ( .A0(n4511), .A1(n4495), .B0(n4700), .B1(n4509), .Y(n1321)
);
AOI21X1TS U5624 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(n4764), .B0(n4496), .Y(
n4500) );
AOI22X1TS U5625 ( .A0(n4505), .A1(n4498), .B0(n4497), .B1(n4502), .Y(n4499)
);
XNOR2X1TS U5626 ( .A(n4500), .B(n4499), .Y(n4501) );
AOI22X1TS U5627 ( .A0(n4511), .A1(n4501), .B0(n4597), .B1(n4509), .Y(n1319)
);
AOI22X1TS U5628 ( .A0(n4505), .A1(n4504), .B0(n4503), .B1(n4502), .Y(n4508)
);
OAI21XLTS U5629 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n4763), .B0(n4506),
.Y(n4507) );
XNOR2X1TS U5630 ( .A(n4508), .B(n4507), .Y(n4510) );
AOI22X1TS U5631 ( .A0(n4511), .A1(n4510), .B0(n4618), .B1(n4509), .Y(n1318)
);
AOI21X1TS U5632 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n4773), .B0(n4512),
.Y(n4517) );
AOI22X1TS U5633 ( .A0(n4515), .A1(n4514), .B0(n4513), .B1(n4426), .Y(n4516)
);
XNOR2X1TS U5634 ( .A(n4517), .B(n4516), .Y(n4519) );
AOI22X1TS U5635 ( .A0(n4511), .A1(n4519), .B0(n4673), .B1(n4518), .Y(n1317)
);
NOR2XLTS U5636 ( .A(n2288), .B(n4288), .Y(n4521) );
AOI211X1TS U5637 ( .A0(n4557), .A1(n4522), .B0(n4521), .C0(n4536), .Y(n4565)
);
OAI22X1TS U5638 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4726), .B0(n4565),
.B1(n2286), .Y(n1315) );
AO22XLTS U5639 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n4543), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1313) );
AO22XLTS U5640 ( .A0(n4532), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n4543), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1311) );
AO22XLTS U5641 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(n4541), .B1(
FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1310) );
BUFX4TS U5642 ( .A(n4546), .Y(n4563) );
AO22XLTS U5643 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[2]), .B0(n4545), .B1(
FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1309) );
NOR2XLTS U5644 ( .A(n4553), .B(n4288), .Y(n4523) );
AOI211X1TS U5645 ( .A0(n4557), .A1(n4524), .B0(n4523), .C0(n4536), .Y(n4570)
);
OAI22X1TS U5646 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4727), .B0(n4570),
.B1(n2286), .Y(n1308) );
AO22XLTS U5647 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n4543), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1306) );
AO22XLTS U5648 ( .A0(n4532), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n4543), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1304) );
AO22XLTS U5649 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(n4541), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1303) );
AO22XLTS U5650 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[7]), .B0(n4545), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1302) );
NOR2XLTS U5651 ( .A(n4525), .B(n4288), .Y(n4526) );
AOI211X1TS U5652 ( .A0(n4557), .A1(n4527), .B0(n4526), .C0(n4536), .Y(n4562)
);
OAI22X1TS U5653 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4728), .B0(n4562),
.B1(n2286), .Y(n1301) );
AO22XLTS U5654 ( .A0(n4528), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n4543), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1299) );
AO22XLTS U5655 ( .A0(n4528), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n4543), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1297) );
AO22XLTS U5656 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(n4541), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1296) );
AO22XLTS U5657 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[0]), .B0(n4545), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1295) );
NOR2XLTS U5658 ( .A(n4529), .B(n4288), .Y(n4530) );
AOI211X1TS U5659 ( .A0(n4557), .A1(n4531), .B0(n4530), .C0(n4536), .Y(n4564)
);
OAI22X1TS U5660 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4729), .B0(n4564),
.B1(n2286), .Y(n1294) );
AO22XLTS U5661 ( .A0(n4532), .A1(FPADDSUB_DmP_EXP_EWSW[1]), .B0(n4543), .B1(
FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1292) );
AO22XLTS U5662 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(n4541), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1289) );
AO22XLTS U5663 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[1]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1288) );
AOI22X1TS U5664 ( .A0(n4591), .A1(n4534), .B0(n4533), .B1(n4557), .Y(n4572)
);
OAI22X1TS U5665 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4730), .B0(n4572),
.B1(n2286), .Y(n1287) );
AO22XLTS U5666 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n4541), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1282) );
INVX4TS U5667 ( .A(n4546), .Y(n4587) );
AO22XLTS U5668 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[9]), .B0(n4587), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1281) );
NOR2XLTS U5669 ( .A(n4535), .B(n4288), .Y(n4537) );
AOI211X1TS U5670 ( .A0(n4557), .A1(n4538), .B0(n4537), .C0(n4536), .Y(n4568)
);
OAI22X1TS U5671 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n4731), .B0(n4568),
.B1(n2286), .Y(n1280) );
AO22XLTS U5672 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(n4541), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1275) );
AO22XLTS U5673 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[5]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1274) );
AO22XLTS U5674 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1269) );
AO22XLTS U5675 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[12]), .B0(n4545), .B1(
FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1268) );
AO22XLTS U5676 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1265) );
AO22XLTS U5677 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[10]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1264) );
AO22XLTS U5678 ( .A0(n2289), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n4539),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1262) );
AO22XLTS U5679 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1261) );
AO22XLTS U5680 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[14]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1260) );
AO22XLTS U5681 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n4539),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1258) );
AO22XLTS U5682 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1257) );
AO22XLTS U5683 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[11]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1256) );
AO22XLTS U5684 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n4539), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1254) );
AO22XLTS U5685 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n4861), .B1(
FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1253) );
AO22XLTS U5686 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[8]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1252) );
AO22XLTS U5687 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[16]), .B0(n4540), .B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1250) );
AO22XLTS U5688 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1249) );
AO22XLTS U5689 ( .A0(n4546), .A1(FPADDSUB_DMP_SFG[16]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1248) );
AO22XLTS U5690 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[13]), .B0(n4540), .B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1246) );
AO22XLTS U5691 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1245) );
AO22XLTS U5692 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[13]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1244) );
AO22XLTS U5693 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[6]), .B0(n4540), .B1(FPADDSUB_DMP_SHT1_EWSW[6]),
.Y(n1242) );
AO22XLTS U5694 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(n4541), .B1(
FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1241) );
AO22XLTS U5695 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[6]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1240) );
AO22XLTS U5696 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(n4541), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1237) );
AO22XLTS U5697 ( .A0(n4546), .A1(FPADDSUB_DMP_SFG[4]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1236) );
AO22XLTS U5698 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1233) );
AO22XLTS U5699 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[17]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1232) );
AO22XLTS U5700 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1229) );
AO22XLTS U5701 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[20]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1228) );
AO22XLTS U5702 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1225) );
AO22XLTS U5703 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[19]), .B0(n4545), .B1(
FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1224) );
AO22XLTS U5704 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1221) );
AO22XLTS U5705 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[21]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1220) );
AO22XLTS U5706 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n4541),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1217) );
AO22XLTS U5707 ( .A0(n4563), .A1(FPADDSUB_DMP_SFG[18]), .B0(n4587), .B1(
FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1216) );
AO22XLTS U5708 ( .A0(n4542), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n2290),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1214) );
AO22XLTS U5709 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1213) );
AO22XLTS U5710 ( .A0(n4546), .A1(FPADDSUB_DMP_SFG[15]), .B0(n4561), .B1(
FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1212) );
AO22XLTS U5711 ( .A0(n2289), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n4543),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1210) );
AO22XLTS U5712 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n4861),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1209) );
AO22XLTS U5713 ( .A0(n4546), .A1(FPADDSUB_DMP_SFG[22]), .B0(n4545), .B1(
FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1208) );
AOI22X1TS U5714 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n4548), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n4547), .Y(n4551) );
AOI22X1TS U5715 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n4255), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n4549), .Y(n4550) );
OAI211X1TS U5716 ( .A0(n4553), .A1(n2196), .B0(n4551), .C0(n4550), .Y(n4590)
);
AOI2BB2XLTS U5717 ( .B0(n4557), .B1(n4590), .A0N(n4589), .A1N(n4288), .Y(
n4554) );
INVX3TS U5718 ( .A(n4546), .Y(n4593) );
AOI32X1TS U5719 ( .A0(n4554), .A1(n4593), .A2(n4559), .B0(n4603), .B1(n4546),
.Y(n1207) );
AOI2BB2XLTS U5720 ( .B0(n4557), .B1(n4556), .A0N(n4555), .A1N(n4288), .Y(
n4560) );
AOI32X1TS U5721 ( .A0(n4560), .A1(n4593), .A2(n4559), .B0(n4558), .B1(n4546),
.Y(n1206) );
AOI2BB2XLTS U5722 ( .B0(n4593), .B1(n4562), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[2]), .A1N(n4561), .Y(n1205) );
AOI22X1TS U5723 ( .A0(n4593), .A1(n4564), .B0(n4614), .B1(n4563), .Y(n1204)
);
AOI22X1TS U5724 ( .A0(n4593), .A1(n4565), .B0(n4668), .B1(n4573), .Y(n1203)
);
AOI22X1TS U5725 ( .A0(n4587), .A1(n4566), .B0(n4615), .B1(n4573), .Y(n1202)
);
AOI22X1TS U5726 ( .A0(n4593), .A1(n4567), .B0(n4669), .B1(n4573), .Y(n1201)
);
AOI22X1TS U5727 ( .A0(n4593), .A1(n4568), .B0(n4616), .B1(n4573), .Y(n1200)
);
AOI22X1TS U5728 ( .A0(n4593), .A1(n4569), .B0(n4672), .B1(n4573), .Y(n1199)
);
AOI22X1TS U5729 ( .A0(n4593), .A1(n4570), .B0(n4617), .B1(n4573), .Y(n1198)
);
AOI22X1TS U5730 ( .A0(n4587), .A1(n4571), .B0(n4675), .B1(n4573), .Y(n1197)
);
AOI22X1TS U5731 ( .A0(n4593), .A1(n4572), .B0(n4620), .B1(n4573), .Y(n1196)
);
AOI22X1TS U5732 ( .A0(n4587), .A1(n4574), .B0(n4680), .B1(n4573), .Y(n1195)
);
AOI22X1TS U5733 ( .A0(n4587), .A1(n4575), .B0(n4682), .B1(n4585), .Y(n1194)
);
AOI22X1TS U5734 ( .A0(n4587), .A1(n4576), .B0(n4683), .B1(n4585), .Y(n1193)
);
AOI22X1TS U5735 ( .A0(n4587), .A1(n4577), .B0(n4626), .B1(n4585), .Y(n1192)
);
AOI22X1TS U5736 ( .A0(n4587), .A1(n4578), .B0(n4687), .B1(n4585), .Y(n1191)
);
AOI22X1TS U5737 ( .A0(n4587), .A1(n4579), .B0(n4630), .B1(n4585), .Y(n1190)
);
AOI22X1TS U5738 ( .A0(n4587), .A1(n4580), .B0(n4705), .B1(n4585), .Y(n1189)
);
AOI22X1TS U5739 ( .A0(n4587), .A1(n4581), .B0(n4740), .B1(n4585), .Y(n1188)
);
AOI22X1TS U5740 ( .A0(n4587), .A1(n4582), .B0(n4741), .B1(n4585), .Y(n1187)
);
AOI22X1TS U5741 ( .A0(n4587), .A1(n4583), .B0(n4644), .B1(n4585), .Y(n1186)
);
AOI22X1TS U5742 ( .A0(n4587), .A1(n4584), .B0(n4764), .B1(n4585), .Y(n1185)
);
AOI22X1TS U5743 ( .A0(n4593), .A1(n4586), .B0(n4651), .B1(n4585), .Y(n1184)
);
AOI2BB2XLTS U5744 ( .B0(n4593), .B1(n4588), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[24]), .A1N(n4587), .Y(n1183) );
AOI2BB2XLTS U5745 ( .B0(n4591), .B1(n4590), .A0N(n4589), .A1N(n4260), .Y(
n4594) );
AOI32X1TS U5746 ( .A0(n4594), .A1(n4593), .A2(n4592), .B0(n4790), .B1(n4546),
.Y(n1182) );
CMPR42X1TS U5747 ( .A(mult_x_69_n745), .B(mult_x_69_n461), .C(mult_x_69_n462), .D(mult_x_69_n769), .ICI(mult_x_69_n463), .S(mult_x_69_n459), .ICO(
mult_x_69_n457), .CO(mult_x_69_n458) );
CMPR42X1TS U5748 ( .A(mult_x_69_n397), .B(mult_x_69_n737), .C(mult_x_69_n402), .D(mult_x_69_n761), .ICI(mult_x_69_n403), .S(mult_x_69_n394), .ICO(
mult_x_69_n392), .CO(mult_x_69_n393) );
CMPR42X1TS U5749 ( .A(mult_x_69_n742), .B(mult_x_69_n440), .C(mult_x_69_n443), .D(mult_x_69_n766), .ICI(mult_x_69_n444), .S(mult_x_69_n438), .ICO(
mult_x_69_n436), .CO(mult_x_69_n437) );
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
// Date : Fri Jun 23 10:19:57 2017
// Host : dshwdev running 64-bit Ubuntu 16.04.2 LTS
// Command : write_verilog -force -mode synth_stub
// /home/h-ishihara/workspace/FPGAMAG18/FPGA/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/fmrv32im_artya7_stub.v
// Design : fmrv32im_artya7
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module fmrv32im_artya7(CLK100MHZ, GPIO_i, GPIO_o, GPIO_ot, UART_rx,
UART_tx)
/* synthesis syn_black_box black_box_pad_pin="CLK100MHZ,GPIO_i[31:0],GPIO_o[31:0],GPIO_ot[31:0],UART_rx,UART_tx" */;
input CLK100MHZ;
input [31:0]GPIO_i;
output [31:0]GPIO_o;
output [31:0]GPIO_ot;
input UART_rx;
output UART_tx;
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// ECC Encoder for error correction and detection memory //
// //
// //
// Description //
// Error correcting code generator //
// This module takes one word of data as input and generates //
// an error correcting code (ECC). //
// The ECC allows error detection and correction depending on //
// how it was generated and its size. //
// A write_enabled flag and an ECC are also taken as input so //
// that we can reuse this module for WRITE operations (only ECC //
// generation) and READ operations (compute difference between //
// the ECC coming from memory and the generated, aka syndrome). //
// //
// This module implements the (40,32) parity check matrix used //
// for IBM 8130. //
// Notes: this module is not parameterized because the parity //
// check matrix varies depending on input data width and //
// desired ECC width and must be 'hardcoded'. //
// Reference: Error-Correcting Codes for Semiconductor Memory //
// Applications: A State-of-the-Art Review //
// //
// Author(s): //
// - Jorge Bellon Castro, [email protected] //
// - Carlos Diaz Suarez, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2014 Jorge Bellon Castro //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module edc_generator #() (
input [31:0] i_data, // Input data bus
input [7:0] i_ecc, // Input ECC (only relevant when write_enabled_i == 0)
input i_write_enabled, // Write enabled flag
output [7:0] o_ecc_syndrome // Generated ecc (write_enabled_i == 1) or Syndrome (write_enabled_i == 0)
);
wire [31:0] parity_check_matrix[0:7];
wire [7:0] generated_ecc;
// Parity check matrix definition
generate
// Parity check matrix
assign parity_check_matrix[7] = 40'b10101010_10101010_11000000_11000000;//10000000;
assign parity_check_matrix[6] = 40'b01010101_01010101_00110000_00110000;//01000000;
assign parity_check_matrix[5] = 40'b11111111_00000000_00001100_00001100;//00100000;
assign parity_check_matrix[4] = 40'b00000000_11111111_00000011_00000011;//00010000;
assign parity_check_matrix[3] = 40'b11000000_11000000_11111111_00000000;//00001000;
assign parity_check_matrix[2] = 40'b00110000_00110000_00000000_11111111;//00000100;
assign parity_check_matrix[1] = 40'b00001100_00001100_10101010_10101010;//00000010;
assign parity_check_matrix[0] = 40'b00000011_00000011_01010101_01010101;//00000001;
endgenerate
// ECC computation
genvar r,c;
generate
for (r=0; r<8; r=r+1) begin
// Compute the ECC as the 'sum-product' of all elements of the row by the elements of the word
// Product: logic AND; Sum (mod 2): logic XOR
assign generated_ecc[r] = ( ^ ( parity_check_matrix[r] & i_data ));
// Return either difference (XOR) between generated ecc and input ecc or just the generated one
// depending if we are performing a READ operation (first case) or a WRITE (second case).
assign o_ecc_syndrome[r] = i_write_enabled ? generated_ecc[r] : generated_ecc[r] ^ i_ecc[r];
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07:04:40 06/02/2013
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Alu(Alu_in1,Alu_in2,Alu_sel,Alu_zero_flg,Alu_out
);
parameter wrd_size = 8,
sel_width= 3;
input [wrd_size-1:0] Alu_in1,Alu_in2;
input [sel_width-1:0] Alu_sel;
output reg [wrd_size-1:0] Alu_out;
output Alu_zero_flg;
localparam NOP = 3'b000,
ADD = 3'b001,
SUB = 3'b010,
AND = 3'b011,
OR = 3'b100,
SLT = 3'b101,
SRT = 3'b110,
NOT = 3'b111;
assign Alu_zero_flg = ~|Alu_out;
always @(*)
case(Alu_sel)
NOP: Alu_out = 0;
AND: Alu_out = Alu_in1&Alu_in2;
OR: Alu_out = Alu_in1|Alu_in2;
ADD: Alu_out = Alu_in1+Alu_in2;
SUB: Alu_out = Alu_in1-Alu_in2;
NOT: Alu_out = ~Alu_in1;
SLT: Alu_out = Alu_in1<<Alu_in2;
SRT: Alu_out = Alu_in1>>Alu_in2;
default: Alu_out = 0;
endcase
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Samuel A. Falvo II
//
// Create Date: 19:59:06 10/30/2011
// Design Name: UXA 1A
// Module Name: M_uxa_ps2
// Project Name: Kestrel-2
// Target Devices: Nexys2
// Tool versions:
// Description:
// This top-level module encapsulates one entire PS/2
// interface adapter. Instantiate one of these in your
// design, plus all dependent sub-modules, and you will
// have a PS/2 interface adapter with a 16-byte FIFO.
//
// Dependencies:
// M_uxa_ps2_busctl
// M_uxa_ps2_fifo
// M_uxa_ps2_wrtlgc
// M_uxa_ps2_shfreg
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module M_uxa_ps2(
// PS/2 port I/O ports
output ps2_c_oe_o,
output ps2_d_oe_o,
input ps2_d_i,
input ps2_c_i,
// Wishbone bus interface
input sys_clk_i,
input sys_reset_i,
output io_ack_o,
input io_stb_i,
input io_we_i,
input [9:8] io_dat_i,
output [15:0] io_dat_o
);
wire bc_rp_inc_o;
wire wl_we_o;
wire wl_ptr_inc_o;
wire wl_reset_o;
wire [7:0] sr_d_o;
wire sr_frame_o;
wire sr_reset_i = (sys_reset_i | wl_reset_o);
M_uxa_ps2_busctl busctl (
.sys_clk_i(sys_clk_i),
.sys_reset_i(sys_reset_i),
.wb_we_i(io_we_i),
.wb_stb_i(io_stb_i),
.wb_dat_8_i(io_dat_i[8]),
.wb_dat_9_i(io_dat_i[9]),
.wb_ack_o(io_ack_o),
.rp_inc_o(bc_rp_inc_o),
.c_oe_o(ps2_c_oe_o),
.d_oe_o(ps2_d_oe_o)
);
M_uxa_ps2_shfreg shfreg (
.ps2_d_i(ps2_d_i),
.ps2_c_i(ps2_c_i),
.d_o(sr_d_o),
.frame_o(sr_frame_o),
.reset_i(sr_reset_i),
.sys_clk_i(sys_clk_i)
);
M_uxa_ps2_wrtlgc wrtlgc (
.frame_i(sr_frame_o),
.reset_o(wl_reset_o),
.we_o(wl_we_o),
.ptr_inc_o(wl_ptr_inc_o),
.sys_clk_i(sys_clk_i),
.sys_reset_i(sys_reset_i)
);
M_uxa_ps2_fifo fifo (
.d_i(sr_d_o),
.we_i(wl_we_o),
.wp_inc_i(wl_ptr_inc_o),
.q_o(io_dat_o[7:0]),
.rp_inc_i(bc_rp_inc_o),
.full_o(io_dat_o[14]),
.data_available_o(io_dat_o[15]),
.sys_clk_i(sys_clk_i),
.sys_reset_i(sys_reset_i)
);
reg [3:0] zeros;
assign io_dat_o[13:10] = zeros;
assign io_dat_o[9] = ps2_c_i;
assign io_dat_o[8] = ps2_d_i;
initial begin
zeros <= 4'b0000;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFBBN_BEHAVIORAL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_N_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:32:54 02/22/2015
// Design Name:
// Module Name: ExecutePipeline
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ExecutePipeline(
input [31:0] X_in,
input [31:0] Y_in,
input [31:0] Z_in,
input [31:0] K_in,
input [31:0] kappa_in,
input [31:0] theta_in,
input [31:0] delta_in,
input reset,
input clock,
input operation,
input NatLogFlag_Execute,
input [1:0] mode,
input [7:0] InsTagFSMOut,
output [31:0] X_next,
output [31:0] Y_next,
output [31:0] Z_next,
output [31:0] K_next,
output [1:0] mode_out,
output operation_out,
output NatLogFlag_iter,
output ALU_done,
output [7:0] InsTag_iter
);
alu_x_pipelined alu_x (
.a_multiplicand(Y_in),
.b_multiplier(delta_in),
.c_addition(X_in),
.mode(mode),
.operation(operation),
.NatLogFlag_Execute(NatLogFlag_Execute),
.InsTagFSMOut(InsTagFSMOut),
.reset(reset),
.clock(clock),
.accumulate(X_next),
.mode_out(mode_out),
.operation_out(operation_out),
.NatLogFlag_iter(NatLogFlag_iter),
.InsTagXOut(InsTag_iter)
);
alu_y_pipelined alu_y (
.a_multiplicand(X_in),
.b_multiplier(delta_in),
.c_addition(Y_in),
.mode(mode),
.operation(operation),
.NatLogFlag_Execute(NatLogFlag_Execute),
.InsTagFSMOut(InsTagFSMOut),
.reset(reset),
.clock(clock),
.accumulate(Y_next),
.done(ALU_done)
);
mult_k mul_k (
.a_multiplicand(K_in),
.b_multiplier(kappa_in),
.reset(reset),
.clock(clock),
.FinalProduct(K_next)
);
Adder_z add_z (
.a_adder(Z_in),
.b_adder(theta_in),
.reset(reset),
.clock(clock),
.FinalSum(Z_next)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CPU SM
// File : sm_cpu_cy124.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module consists of two state machines.
// The first one is cpu_latch_data, which process the
// hostdata, latches the data into a latch. This state
// machine also generates the host ready signal to host.
// Which indicates that the VGA is ready for the
// next cycle.
//
// The second state machine generates the internal cylces
// for the external host transfers to the external memory
// memory acess. When the external host transfer is 32-bit
// mode then internal it is one cycle transfer. If it is
// 16-bit transfer then it is a two cycle transfer. If the
// host is 8-bit transfer then the internal transfer is four
// cycles.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module sm_cpu_cy124
(
input t_mem_io_n,
input t_svga_sel,
input m_cpurd_s0,
input t_data_ready_n,
input cpu_rd_gnt,
input svga_ack,
input en_cy1,
input en_cy2,
input en_cy3,
input en_cy4,
input c_misc_b1,
input h_reset_n,
input t_mem_clk,
input h_svga_sel,
input h_hrd_hwr_n,
input h_mem_io_n,
input m_cpu_ff_full,
input m_chain4,
input m_odd_even,
input m_planar,
input m_memrd_ready_n,
output cpucy_1_2,
output cpucy_2_2,
output cpucy_1_3,
output cpucy_2_3,
output cpucy_3_3,
output cpucy_1_4,
output cpucy_2_4,
output cpucy_3_4,
output cpucy_4_4,
output g_mem_ready_n,
output g_memwr,
output mem_clk,
output g_memrd,
output g_lt_hwr_cmd,
output g_cpult_state1,
output reg cy2_gnt,
output reg cy3_gnt,
output reg cy4_gnt,
output mem_write,
output memwr_inpr,
output g_cpu_data_done,
output g_cpu_cycle_done,
output mem_read,
output reg svga_sel_hit,
output reg svmem_sel_hit,
output svmem_hit_we,
output reg en_cy1_ff,
output reg en_cy2_ff,
output reg en_cy3_ff,
output reg en_cy4_ff,
output cur_cpurd_done
);
reg [1:0] lt_current_state;
reg [1:0] lt_next_state;
reg [4:0] cyl_current_state;
reg [4:0] cyl_next_state;
reg cyl_s0, cyl_s1;
reg cyl_s2, cyl_s3;
reg cyl_s4, cyl_s5;
reg cyl_s6;
reg cyl_s7, cyl_s8;
reg cyl_s9, cyl_sa;
reg cyl_sb;
reg cyl_sc, cyl_sd, cyl_se, cyl_sf, cyl_s10;
reg cltda_s0, cltda_s1, cltda_s2, cltda_s3;
reg [2:0] drdy_q;
reg mem_ready_dly;
reg mem_ready_dly1;
wire data_rdy;
wire ency1_rst_n;
wire ency2_rst_n;
wire ency3_rst_n;
wire ency4_rst_n;
wire cur_cyl_done;
wire cpuff_ack;
wire start_cpuwr;
wire cpu_wrcycle_done;
wire start_rdwr;
wire dly_reset_n;
wire cyl_gnt_rst_n;
wire dx_1;
wire dx_2;
wire dx_3;
wire dx_4;
wire drdy_cnt_inc;
wire svga_hit_we;
wire ency1_rst, ency2_rst, ency3_rst, ency4_rst;
wire mem_ready;
wire c_rd_rst;
wire c_rd_rst_dly;
wire svgahit_din;
wire svmemhit_din;
//
// Define state machine states
//
assign mem_write = ~h_hrd_hwr_n & h_mem_io_n;
assign mem_read = h_hrd_hwr_n & h_mem_io_n;
assign g_memrd = h_hrd_hwr_n & h_mem_io_n;
assign mem_clk = t_mem_clk;
assign svga_hit_we = (t_mem_io_n & t_svga_sel) | cltda_s1;
assign svgahit_din = ~cltda_s1;
always @(posedge mem_clk or negedge h_reset_n)
if (!h_reset_n) svga_sel_hit <= 1'b0;
else if (svga_hit_we) svga_sel_hit <= svgahit_din;
assign svmem_hit_we = t_mem_io_n & t_svga_sel | ~g_mem_ready_n;
assign svmemhit_din = g_mem_ready_n;
always @(posedge mem_clk or negedge h_reset_n)
if (!h_reset_n) svmem_sel_hit <= 1'b0;
else if (svmem_hit_we) svmem_sel_hit <= svmemhit_din;
parameter cpu_ltda_state0 = 2'b00,
cpu_ltda_state1 = 2'b01,
cpu_ltda_state3 = 2'b11,
cpu_ltda_state2 = 2'b10;
always @ (posedge mem_clk or negedge h_reset_n) begin
if (!h_reset_n) lt_current_state <= cpu_ltda_state0;
else lt_current_state <= lt_next_state;
end
always @* begin
cltda_s0 = 1'b0;
cltda_s1 = 1'b0;
cltda_s2 = 1'b0;
cltda_s3 = 1'b0;
case (lt_current_state) // synopsys parallel_case full_case
cpu_ltda_state0: begin
cltda_s0 = 1'b1;
if (~m_cpu_ff_full & svga_sel_hit & c_misc_b1 & mem_write)
lt_next_state = cpu_ltda_state1;
else
lt_next_state = cpu_ltda_state0;
end
cpu_ltda_state1: begin
cltda_s1 = 1'b1;
lt_next_state = cpu_ltda_state3;
end
cpu_ltda_state3: begin
cltda_s3 = 1'b1;
if (cpu_wrcycle_done)
lt_next_state = cpu_ltda_state0;
else
lt_next_state = cpu_ltda_state2;
end
cpu_ltda_state2: begin
cltda_s2 = 1'b1;
if (cpu_wrcycle_done)
lt_next_state = cpu_ltda_state0;
else
lt_next_state = cpu_ltda_state2;
end
endcase
end
assign start_cpuwr = cltda_s1 | cltda_s3;
assign start_rdwr = (start_cpuwr | (cpu_rd_gnt & svga_ack));
assign mem_ready = cpu_rd_gnt & ~t_data_ready_n;
always @(posedge mem_clk or negedge h_reset_n)
if (!h_reset_n) begin
mem_ready_dly <= 1'b0;
mem_ready_dly1 <= 1'b0;
cy2_gnt <= 1'b0;
cy3_gnt <= 1'b0;
cy4_gnt <= 1'b0;
end else begin
mem_ready_dly <= mem_ready;
mem_ready_dly1 <= data_rdy;
if (cpu_wrcycle_done) begin
cy2_gnt <= 1'b0;
cy3_gnt <= 1'b0;
cy4_gnt <= 1'b0;
end else if (start_rdwr) begin
if (en_cy2_ff) cy2_gnt <= 1'b1;
if (en_cy3_ff) cy3_gnt <= 1'b1;
if (en_cy4_ff) cy4_gnt <= 1'b1;
end
end
assign data_rdy = mem_ready_dly & g_cpu_data_done;
assign g_mem_ready_n = ~cltda_s1 & ~mem_ready_dly1;
assign g_lt_hwr_cmd = cltda_s0;
assign g_cpult_state1 = cltda_s1;
//
// The following state machine generates internal cycles for the
// external host transfers to the external memory access.
// When the external host transfer is 32-bit mode then internal
// it is one cycle transfer. If it is 16-bit transfer then it is a
// two cycle transfer. If the host is 8-bit transfer then the
// internal transfer is four cycles.
//
parameter cpucyl_state0 = 5'b00000,
cpucyl_state1 = 5'b00001,
cpucyl_state2 = 5'b00010,
cpucyl_state3 = 5'b00011,
cpucyl_state4 = 5'b00111,
cpucyl_state5 = 5'b01000,
cpucyl_state6 = 5'b01100,
cpucyl_state7 = 5'b01110,
cpucyl_state8 = 5'b01111,
cpucyl_state9 = 5'b01011,
cpucyl_statea = 5'b01001,
cpucyl_stateb = 5'b01101,
cpucyl_statec = 5'b10000,
cpucyl_stated = 5'b10001,
cpucyl_statee = 5'b10011,
cpucyl_statef = 5'b10111,
cpucyl_state10 = 5'b11111;
always @(posedge mem_clk or negedge h_reset_n ) begin
if (!h_reset_n) cyl_current_state <= cpucyl_state0;
else cyl_current_state <= cyl_next_state;
end
assign cur_cyl_done = ((g_cpu_data_done & cpu_rd_gnt) | ~cpu_rd_gnt);
assign cur_cpurd_done = (~t_data_ready_n & cpu_rd_gnt);
assign cpuff_ack = ((~cpu_rd_gnt & m_cpu_ff_full) | (~svga_ack & cpu_rd_gnt ));
always @* begin
cyl_s0 = 1'b0;
cyl_s1 = 1'b0;
cyl_s2 = 1'b0;
cyl_s3 = 1'b0;
cyl_s4 = 1'b0;
cyl_s5 = 1'b0;
cyl_s6 = 1'b0;
cyl_s7 = 1'b0;
cyl_s8 = 1'b0;
cyl_s9 = 1'b0;
cyl_sa = 1'b0;
cyl_sb = 1'b0;
cyl_sc = 1'b0;
cyl_sd = 1'b0;
cyl_se = 1'b0;
cyl_sf = 1'b0;
cyl_s10 = 1'b0;
case (cyl_current_state) // synopsys parallel_case full_case
cpucyl_state0: begin
cyl_s0 = 1'b1;
if (start_rdwr & en_cy1_ff) cyl_next_state = cpucyl_state1;
else if (start_rdwr & en_cy2_ff) cyl_next_state = cpucyl_state2;
else if (start_rdwr & en_cy3_ff) cyl_next_state = cpucyl_statec;
else if (start_rdwr & en_cy4_ff) cyl_next_state = cpucyl_state5;
else cyl_next_state = cpucyl_state0;
end
//
// Start of cycle 1
//
cpucyl_state1: begin
cyl_s1 = 1'b1;
if (cur_cyl_done) cyl_next_state = cpucyl_state0;
else cyl_next_state = cpucyl_state1;
end
//
// Start of cycle 2
//
cpucyl_state2: begin
cyl_s2 = 1'b1;
cyl_next_state = cpucyl_state3;
end
cpucyl_state3: begin
cyl_s3 = 1'b1;
if (!cpuff_ack) cyl_next_state = cpucyl_state4;
else cyl_next_state = cpucyl_state3;
end
cpucyl_state4: begin
cyl_s4 = 1'b1;
if (cur_cyl_done) cyl_next_state = cpucyl_state0;
else cyl_next_state = cpucyl_state4;
end
//
// Start of cycle 4
//
cpucyl_state5: begin
cyl_s5 = 1'b1;
cyl_next_state = cpucyl_state6;
end
cpucyl_state6: begin
cyl_s6 = 1'b1;
if (!cpuff_ack) cyl_next_state = cpucyl_state7;
else cyl_next_state = cpucyl_state6;
end
cpucyl_state7: begin
cyl_s7 = 1'b1;
cyl_next_state = cpucyl_state8;
end
cpucyl_state8: begin
cyl_s8 = 1'b1;
if (!cpuff_ack) cyl_next_state = cpucyl_state9;
else cyl_next_state = cpucyl_state8;
end
cpucyl_state9: begin
cyl_s9 = 1'b1;
cyl_next_state = cpucyl_statea;
end
cpucyl_statea: begin
cyl_sa = 1'b1;
if (!cpuff_ack) cyl_next_state = cpucyl_stateb;
else cyl_next_state = cpucyl_statea;
end
cpucyl_stateb: begin
cyl_sb = 1'b1;
if (cur_cyl_done) cyl_next_state = cpucyl_state0;
else cyl_next_state = cpucyl_stateb;
end
//
// Start of cycle 3
//
cpucyl_statec: begin
cyl_sc = 1'b1;
cyl_next_state = cpucyl_stated;
end
cpucyl_stated: begin
cyl_sd = 1'b1;
if (!cpuff_ack) cyl_next_state = cpucyl_statee;
else cyl_next_state = cpucyl_stated;
end
cpucyl_statee: begin
cyl_se = 1'b1;
cyl_next_state = cpucyl_statef;
end
cpucyl_statef: begin
cyl_sf = 1'b1;
if (!cpuff_ack) cyl_next_state = cpucyl_state10;
else cyl_next_state = cpucyl_statef;
end
cpucyl_state10: begin
cyl_s10 = 1'b1;
if (cur_cyl_done) cyl_next_state = cpucyl_state0;
else cyl_next_state = cpucyl_state10;
end
endcase
end
assign cpu_wrcycle_done = cyl_s1 | cyl_s4 | cyl_sb | cyl_s10;
assign g_cpu_cycle_done = cpu_wrcycle_done;
//
// g_cpu_write or g_memwr are the same, it goes to the cpu_fifo_write
// to increment the f_wr counter.
//
assign g_memwr = (cyl_s1 | (cyl_s2 | cyl_s4) | (cyl_s5 | cyl_s7 | cyl_s9 | cyl_sb) | (cyl_sc | cyl_se | cyl_s10));
assign memwr_inpr = ~cyl_s0; // memory write in progress
assign cpucy_1_2 = cyl_s2; // cpu_cycle one of two cycles
assign cpucy_2_2 = cyl_s4; // cpu_cycle two of two cycles
assign cpucy_1_3 = cyl_sc; // cpu_cycle one of three cycles
assign cpucy_2_3 = cyl_se; // cpu_cycle two of three cycles
assign cpucy_3_3 = cyl_s10; // cpu_cycle three of three cycles
assign cpucy_1_4 = cyl_s5; // cpu_cycle one of four cycles
assign cpucy_2_4 = cyl_s7; // cpu_cycle two of four cycles
assign cpucy_3_4 = cyl_s9; // cpu_cycle three of four cycles
assign cpucy_4_4 = cyl_sb; // cpu_cycle four of four cycles
assign drdy_cnt_inc = ~t_data_ready_n & cpu_rd_gnt;
always @ (posedge mem_clk or negedge h_reset_n) begin
if (!h_reset_n) drdy_q <= 3'b0;
else if (m_cpurd_s0) drdy_q <= 3'b0;
else if (drdy_cnt_inc) drdy_q <= drdy_q + 1;
end
assign dx_1 = (drdy_q[2:0] == 3'b001) & en_cy1_ff;
assign dx_2 = (drdy_q[2:0] == 3'b010) & en_cy2_ff;
assign dx_3 = (drdy_q[2:0] == 3'b011) & en_cy3_ff;
assign dx_4 = (drdy_q[2:0] == 3'b100) & en_cy4_ff;
assign g_cpu_data_done = dx_1 | dx_2 | dx_3 | dx_4;
assign c_rd_rst = cpu_rd_gnt & m_cpurd_s0;
always @(posedge mem_clk or negedge h_reset_n)
if (!h_reset_n) begin
en_cy1_ff <= 1'b0;
en_cy2_ff <= 1'b0;
en_cy3_ff <= 1'b0;
en_cy4_ff <= 1'b0;
end else if ((mem_write & cpu_wrcycle_done) | c_rd_rst) begin
en_cy1_ff <= 1'b0;
en_cy2_ff <= 1'b0;
en_cy3_ff <= 1'b0;
en_cy4_ff <= 1'b0;
end else begin
if (en_cy1) en_cy1_ff <= 1'b1;
if (en_cy2) en_cy2_ff <= 1'b1;
if (en_cy3) en_cy3_ff <= 1'b1;
if (en_cy4) en_cy4_ff <= 1'b1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__AND4B_FUNCTIONAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and4b (
X ,
A_N,
B ,
C ,
D
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B, C, D);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_FUNCTIONAL_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ac_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ac_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_ac_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ac_e
//
// No `defines in this module
module inst_ac_e
//
// Generated Module inst_ac
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_ac_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
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