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1.05M
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Programmed By: Ashwith Jerome Rego
// Pin Description:
// CLKIN : Input clock. Must be 100MHz
// RST : Active high module reset.
// BAUD : Baud rate select. The following are the valid values.
// Any other values for BAUD will default to the 9600 baud
// clock.
// +-----+-------------+
// |BAUD |clock rate |
// +-----+-------------+
// |4'h0 | 300 bauds |
// |4'h1 | 600 bauds |
// |4'h2 | 1200 bauds |
// |4'h3 | 2400 bauds |
// |4'h4 | 4800 bauds |
// |4'h5 | 9600 bauds |
// |4'h6 | 19200 bauds |
// |4'h7 | 38400 bauds |
// |4'h8 | 57600 bauds |
// |4'h9 |115200 bauds |
// +-----+-------------+
// CLKOUT: divided output clock.
//////////////////////////////////////////////////////////////////////////////////
module clk_div(
input CLKIN,
input RST,
input [3:0] BAUD,
output CLKOUT
);
//Counter roll over values for different baud rates.
parameter B300 = 19'b1010001011000010100;
parameter B600 = 19'b0101000101100001010;
parameter B1200 = 19'b0010100010110000100;
parameter B2400 = 19'b0001010001011000010;
parameter B4800 = 19'b0000101000101100000;
parameter B9600 = 19'b0000010100010110000;
parameter B19200 = 19'b0000001010001010111;
parameter B38400 = 19'b0000000101000101011;
parameter B57600 = 19'b0000000011011000111;
parameter B115200 = 19'b0000000001101100011;
//clock divider counter;
reg [19:0] clk_cntr;
//roll over value.
reg [19:0] baud_rate;
//output clock register
reg out_clk;
//Set roll over value if module is resetted or baud is changed.
always @ (BAUD, RST) begin
if(RST == 1'b1) begin
baud_rate <= B9600;
end
else begin
case(BAUD)
4'h0 : baud_rate <= B300;
4'h1 : baud_rate <= B600;
4'h2 : baud_rate <= B1200;
4'h3 : baud_rate <= B2400;
4'h4 : baud_rate <= B4800;
4'h5 : baud_rate <= B9600;
4'h6 : baud_rate <= B19200;
4'h7 : baud_rate <= B38400;
4'h8 : baud_rate <= B57600;
4'h9 : baud_rate <= B115200;
default : baud_rate <= B9600;
endcase
end
end
//clock divider
always @ (posedge CLKIN) begin
if(RST == 1'b1) begin
clk_cntr <= 0;
out_clk <= 0;
end
else if(clk_cntr == baud_rate) begin
clk_cntr <= 0;
out_clk <= ~out_clk;
end
else begin
clk_cntr <= clk_cntr + 1'b1;
end
end
assign CLKOUT = out_clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_TB_V
`define SKY130_FD_SC_HD__SDFRBP_TB_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfrbp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_FUNCTIONAL_V
`define SKY130_FD_SC_LP__FILL_FUNCTIONAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_SYMBOL_V
`define SKY130_FD_SC_LP__DLXBN_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_engine.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The tx_engine module takes a formatted header, number of alignment
// blanks and a payloa and concatenates all three (in that order) to form a
// packet. These packets must meet max-request, max-payload, and payload
// termination requirements (see Read Completion Boundary). The tx_engine does
// not check these requirements during operation, but may do so during simulation.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_engine
#(parameter C_DATA_WIDTH = 128,
parameter C_DEPTH_PACKETS = 10,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_FORMATTER_DELAY = 1,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: TX HDR
input TX_HDR_VALID,
input [C_MAX_HDR_WIDTH-1:0] TX_HDR,
input [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
input TX_HDR_NOPAYLOAD,
output TX_HDR_READY,
// Interface: TX_DATA
input TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] TX_DATA,
input TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_START_OFFSET,
input TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_END_OFFSET,
output TX_DATA_READY,
// Interface: TX_PKT
input TX_PKT_READY,
output [C_DATA_WIDTH-1:0] TX_PKT,
output TX_PKT_START_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
output TX_PKT_END_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
output TX_PKT_VALID
);
localparam C_PIPELINE_HDR_FIFO_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_HDR_FIFO_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_PIPELINE_HDR_INPUT = C_PIPELINE_INPUT;
localparam C_ACTUAL_HDR_FIFO_DEPTH = clog2s(C_DEPTH_PACKETS);
localparam C_USE_COMPUTE_REG = 1;
localparam C_USE_READY_REG = 1;
localparam C_USE_FWFT_HDR_FIFO = 1;
localparam C_DATA_FIFO_DEPTH = C_ACTUAL_HDR_FIFO_DEPTH + C_FORMATTER_DELAY +
C_PIPELINE_HDR_FIFO_INPUT + C_PIPELINE_HDR_FIFO_OUTPUT + C_USE_FWFT_HDR_FIFO + // Header Fifo
C_PIPELINE_HDR_INPUT + C_USE_COMPUTE_REG + C_USE_READY_REG + C_PIPELINE_OUTPUT; // Aligner
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNoPayload;
wire wTxDataReady;
wire [C_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady;
tx_data_pipeline
#(
.C_MAX_PAYLOAD (C_MAX_PAYLOAD_DWORDS*32),
.C_DEPTH_PACKETS (C_DATA_FIFO_DEPTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
tx_data_pipeline_inst
(
// Outputs
.RD_TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_START_FLAG (wTxDataStartFlag),
.RD_TX_DATA_END_FLAGS (wTxDataEndFlags[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_READY (TX_DATA_READY),
// Inputs
.RD_TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA (TX_DATA),
.WR_TX_DATA_VALID (TX_DATA_VALID),
.WR_TX_DATA_START_FLAG (TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_hdr_fifo
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_HDR_FIFO_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_HDR_FIFO_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_ACTUAL_HDR_FIFO_DEPTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_VENDOR (C_VENDOR))
txhf_inst
(
// Outputs
.WR_TX_HDR_READY (TX_HDR_READY),
.RD_TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.RD_TX_HDR_VALID (wTxHdrValid),
.RD_TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.RD_TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.RD_TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.RD_TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.WR_TX_HDR (TX_HDR[C_MAX_HDR_WIDTH-1:0]),
.WR_TX_HDR_VALID (TX_HDR_VALID),
.WR_TX_HDR_NOPAYLOAD (TX_HDR_NOPAYLOAD),
.WR_TX_HDR_PAYLOAD_LEN (TX_HDR_PAYLOAD_LEN[`SIG_LEN_W-1:0]),
.WR_TX_HDR_NONPAY_LEN (TX_HDR_NONPAY_LEN[`SIG_NONPAY_W-1:0]),
.WR_TX_HDR_PACKET_LEN (TX_HDR_PACKET_LEN[`SIG_PACKETLEN_W-1:0]),
.RD_TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_alignment_pipeline
#(
// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_DATA_INPUT (1),
.C_PIPELINE_HDR_INPUT (C_PIPELINE_HDR_INPUT),
.C_DATA_WIDTH (C_DATA_WIDTH),
// Parameters
/*AUTOINSTPARAM*/
// Parameters
.C_USE_COMPUTE_REG (C_USE_COMPUTE_REG),
.C_USE_READY_REG (C_USE_READY_REG),
.C_VENDOR (C_VENDOR))
tx_alignment_inst
(
// Outputs
.TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.TX_HDR_READY (wTxHdrReady),
.TX_PKT (TX_PKT[C_DATA_WIDTH-1:0]),
.TX_PKT_VALID (TX_PKT_VALID),
.TX_PKT_START_FLAG (TX_PKT_START_FLAG),
.TX_PKT_START_OFFSET (TX_PKT_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TX_PKT_END_FLAG),
.TX_PKT_END_OFFSET (TX_PKT_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
// Inputs
.TX_DATA_START_FLAG (wTxDataStartFlag),
.TX_DATA_END_FLAGS (wTxDataEndFlags),
.TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_PKT_READY (TX_PKT_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz LVDS
* Reset: Push button, active low
*/
input wire clk_125mhz_p,
input wire clk_125mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* I2C for board management
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: QSFP28
*/
output wire qsfp1_tx1_p,
output wire qsfp1_tx1_n,
input wire qsfp1_rx1_p,
input wire qsfp1_rx1_n,
output wire qsfp1_tx2_p,
output wire qsfp1_tx2_n,
input wire qsfp1_rx2_p,
input wire qsfp1_rx2_n,
output wire qsfp1_tx3_p,
output wire qsfp1_tx3_n,
input wire qsfp1_rx3_p,
input wire qsfp1_rx3_n,
output wire qsfp1_tx4_p,
output wire qsfp1_tx4_n,
input wire qsfp1_rx4_p,
input wire qsfp1_rx4_n,
input wire qsfp1_mgt_refclk_0_p,
input wire qsfp1_mgt_refclk_0_n,
// input wire qsfp1_mgt_refclk_1_p,
// input wire qsfp1_mgt_refclk_1_n,
// output wire qsfp1_recclk_p,
// output wire qsfp1_recclk_n,
output wire qsfp1_modsell,
output wire qsfp1_resetl,
input wire qsfp1_modprsl,
input wire qsfp1_intl,
output wire qsfp1_lpmode,
output wire qsfp2_tx1_p,
output wire qsfp2_tx1_n,
input wire qsfp2_rx1_p,
input wire qsfp2_rx1_n,
output wire qsfp2_tx2_p,
output wire qsfp2_tx2_n,
input wire qsfp2_rx2_p,
input wire qsfp2_rx2_n,
output wire qsfp2_tx3_p,
output wire qsfp2_tx3_n,
input wire qsfp2_rx3_p,
input wire qsfp2_rx3_n,
output wire qsfp2_tx4_p,
output wire qsfp2_tx4_n,
input wire qsfp2_rx4_p,
input wire qsfp2_rx4_n,
// input wire qsfp2_mgt_refclk_0_p,
// input wire qsfp2_mgt_refclk_0_n,
// input wire qsfp2_mgt_refclk_1_p,
// input wire qsfp2_mgt_refclk_1_n,
// output wire qsfp2_recclk_p,
// output wire qsfp2_recclk_n,
output wire qsfp2_modsell,
output wire qsfp2_resetl,
input wire qsfp2_modprsl,
input wire qsfp2_intl,
output wire qsfp2_lpmode,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
input wire phy_int_n,
inout wire phy_mdio,
output wire phy_mdc,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_125mhz_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS #(
.DIFF_TERM("FALSE"),
.IBUF_LOW_PWR("FALSE")
)
clk_125mhz_ibufg_inst (
.O (clk_125mhz_ibufg),
.I (clk_125mhz_p),
.IB (clk_125mhz_n)
);
// MMCM instance
// 125 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 8, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(8),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(8.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_125mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(156000)
)
debounce_switch_inst (
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_156mhz_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
// SI570 I2C
wire i2c_scl_i;
wire i2c_scl_o = 1'b1;
wire i2c_scl_t = 1'b1;
wire i2c_sda_i;
wire i2c_sda_o = 1'b1;
wire i2c_sda_t = 1'b1;
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// XGMII 10G PHY
assign qsfp1_modsell = 1'b0;
assign qsfp1_resetl = 1'b1;
assign qsfp1_lpmode = 1'b0;
wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [63:0] qsfp1_txd_1_int;
wire [7:0] qsfp1_txc_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [63:0] qsfp1_rxd_1_int;
wire [7:0] qsfp1_rxc_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [63:0] qsfp1_txd_2_int;
wire [7:0] qsfp1_txc_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [63:0] qsfp1_rxd_2_int;
wire [7:0] qsfp1_rxc_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [63:0] qsfp1_txd_3_int;
wire [7:0] qsfp1_txc_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [63:0] qsfp1_rxd_3_int;
wire [7:0] qsfp1_rxc_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [63:0] qsfp1_txd_4_int;
wire [7:0] qsfp1_txc_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [63:0] qsfp1_rxd_4_int;
wire [7:0] qsfp1_rxc_4_int;
assign qsfp2_modsell = 1'b0;
assign qsfp2_resetl = 1'b1;
assign qsfp2_lpmode = 1'b0;
wire qsfp2_tx_clk_1_int;
wire qsfp2_tx_rst_1_int;
wire [63:0] qsfp2_txd_1_int;
wire [7:0] qsfp2_txc_1_int;
wire qsfp2_rx_clk_1_int;
wire qsfp2_rx_rst_1_int;
wire [63:0] qsfp2_rxd_1_int;
wire [7:0] qsfp2_rxc_1_int;
wire qsfp2_tx_clk_2_int;
wire qsfp2_tx_rst_2_int;
wire [63:0] qsfp2_txd_2_int;
wire [7:0] qsfp2_txc_2_int;
wire qsfp2_rx_clk_2_int;
wire qsfp2_rx_rst_2_int;
wire [63:0] qsfp2_rxd_2_int;
wire [7:0] qsfp2_rxc_2_int;
wire qsfp2_tx_clk_3_int;
wire qsfp2_tx_rst_3_int;
wire [63:0] qsfp2_txd_3_int;
wire [7:0] qsfp2_txc_3_int;
wire qsfp2_rx_clk_3_int;
wire qsfp2_rx_rst_3_int;
wire [63:0] qsfp2_rxd_3_int;
wire [7:0] qsfp2_rxc_3_int;
wire qsfp2_tx_clk_4_int;
wire qsfp2_tx_rst_4_int;
wire [63:0] qsfp2_txd_4_int;
wire [7:0] qsfp2_txc_4_int;
wire qsfp2_rx_clk_4_int;
wire qsfp2_rx_rst_4_int;
wire [63:0] qsfp2_rxd_4_int;
wire [7:0] qsfp2_rxc_4_int;
wire qsfp1_rx_block_lock_1;
wire qsfp1_rx_block_lock_2;
wire qsfp1_rx_block_lock_3;
wire qsfp1_rx_block_lock_4;
wire qsfp2_rx_block_lock_1;
wire qsfp2_rx_block_lock_2;
wire qsfp2_rx_block_lock_3;
wire qsfp2_rx_block_lock_4;
wire qsfp1_mgt_refclk_0;
wire [7:0] gt_txclkout;
wire gt_txusrclk;
wire [7:0] gt_rxclkout;
wire [7:0] gt_rxusrclk;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [7:0] gt_txprgdivresetdone;
wire [7:0] gt_txpmaresetdone;
wire [7:0] gt_rxprgdivresetdone;
wire [7:0] gt_rxpmaresetdone;
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
wire gt_rx_reset = ~>_rxpmaresetdone;
reg gt_userclk_tx_active = 1'b0;
reg [7:0] gt_userclk_rx_active = 1'b0;
IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_0_inst (
.I (qsfp1_mgt_refclk_0_p),
.IB (qsfp1_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp1_mgt_refclk_0),
.ODIV2 ()
);
BUFG_GT bufg_gt_tx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_tx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_txclkout[0]),
.O (gt_txusrclk)
);
assign clk_156mhz_int = gt_txusrclk;
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
if (gt_tx_reset) begin
gt_userclk_tx_active <= 1'b0;
end else begin
gt_userclk_tx_active <= 1'b1;
end
end
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin
BUFG_GT bufg_gt_rx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_rxclkout[n]),
.O (gt_rxusrclk[n])
);
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
if (gt_rx_reset) begin
gt_userclk_rx_active[n] <= 1'b0;
end else begin
gt_userclk_rx_active[n] <= 1'b1;
end
end
end
endgenerate
sync_reset #(
.N(4)
)
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.out(rst_156mhz_int)
);
wire [5:0] qsfp1_gt_txheader_1;
wire [63:0] qsfp1_gt_txdata_1;
wire qsfp1_gt_rxgearboxslip_1;
wire [5:0] qsfp1_gt_rxheader_1;
wire [1:0] qsfp1_gt_rxheadervalid_1;
wire [63:0] qsfp1_gt_rxdata_1;
wire [1:0] qsfp1_gt_rxdatavalid_1;
wire [5:0] qsfp1_gt_txheader_2;
wire [63:0] qsfp1_gt_txdata_2;
wire qsfp1_gt_rxgearboxslip_2;
wire [5:0] qsfp1_gt_rxheader_2;
wire [1:0] qsfp1_gt_rxheadervalid_2;
wire [63:0] qsfp1_gt_rxdata_2;
wire [1:0] qsfp1_gt_rxdatavalid_2;
wire [5:0] qsfp1_gt_txheader_3;
wire [63:0] qsfp1_gt_txdata_3;
wire qsfp1_gt_rxgearboxslip_3;
wire [5:0] qsfp1_gt_rxheader_3;
wire [1:0] qsfp1_gt_rxheadervalid_3;
wire [63:0] qsfp1_gt_rxdata_3;
wire [1:0] qsfp1_gt_rxdatavalid_3;
wire [5:0] qsfp1_gt_txheader_4;
wire [63:0] qsfp1_gt_txdata_4;
wire qsfp1_gt_rxgearboxslip_4;
wire [5:0] qsfp1_gt_rxheader_4;
wire [1:0] qsfp1_gt_rxheadervalid_4;
wire [63:0] qsfp1_gt_rxdata_4;
wire [1:0] qsfp1_gt_rxdatavalid_4;
wire [5:0] qsfp2_gt_txheader_1;
wire [63:0] qsfp2_gt_txdata_1;
wire qsfp2_gt_rxgearboxslip_1;
wire [5:0] qsfp2_gt_rxheader_1;
wire [1:0] qsfp2_gt_rxheadervalid_1;
wire [63:0] qsfp2_gt_rxdata_1;
wire [1:0] qsfp2_gt_rxdatavalid_1;
wire [5:0] qsfp2_gt_txheader_2;
wire [63:0] qsfp2_gt_txdata_2;
wire qsfp2_gt_rxgearboxslip_2;
wire [5:0] qsfp2_gt_rxheader_2;
wire [1:0] qsfp2_gt_rxheadervalid_2;
wire [63:0] qsfp2_gt_rxdata_2;
wire [1:0] qsfp2_gt_rxdatavalid_2;
wire [5:0] qsfp2_gt_txheader_3;
wire [63:0] qsfp2_gt_txdata_3;
wire qsfp2_gt_rxgearboxslip_3;
wire [5:0] qsfp2_gt_rxheader_3;
wire [1:0] qsfp2_gt_rxheadervalid_3;
wire [63:0] qsfp2_gt_rxdata_3;
wire [1:0] qsfp2_gt_rxdatavalid_3;
wire [5:0] qsfp2_gt_txheader_4;
wire [63:0] qsfp2_gt_txdata_4;
wire qsfp2_gt_rxgearboxslip_4;
wire [5:0] qsfp2_gt_rxheader_4;
wire [1:0] qsfp2_gt_rxheadervalid_4;
wire [63:0] qsfp2_gt_rxdata_4;
wire [1:0] qsfp2_gt_rxdatavalid_4;
gtwizard_ultrascale_0
qsfp_gty_inst (
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
.gtwiz_reset_all_in(rst_125mhz_int),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(1'b0),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(1'b0),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.gtrefclk00_in({2{qsfp1_mgt_refclk_0}}),
.qpll0outclk_out(),
.qpll0outrefclk_out(),
.gtyrxn_in({qsfp2_rx4_n, qsfp2_rx3_n, qsfp2_rx2_n, qsfp2_rx1_n, qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}),
.gtyrxp_in({qsfp2_rx4_p, qsfp2_rx3_p, qsfp2_rx2_p, qsfp2_rx1_p, qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}),
.rxusrclk_in(gt_rxusrclk),
.rxusrclk2_in(gt_rxusrclk),
.gtwiz_userdata_tx_in({qsfp2_gt_txdata_4, qsfp2_gt_txdata_3, qsfp2_gt_txdata_2, qsfp2_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}),
.txheader_in({qsfp2_gt_txheader_4, qsfp2_gt_txheader_3, qsfp2_gt_txheader_2, qsfp2_gt_txheader_1, qsfp1_gt_txheader_4, qsfp1_gt_txheader_3, qsfp1_gt_txheader_2, qsfp1_gt_txheader_1}),
.txsequence_in({8{1'b0}}),
.txusrclk_in({8{gt_txusrclk}}),
.txusrclk2_in({8{gt_txusrclk}}),
.gtpowergood_out(),
.gtytxn_out({qsfp2_tx4_n, qsfp2_tx3_n, qsfp2_tx2_n, qsfp2_tx1_n, qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}),
.gtytxp_out({qsfp2_tx4_p, qsfp2_tx3_p, qsfp2_tx2_p, qsfp2_tx1_p, qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}),
.rxgearboxslip_in({qsfp2_gt_rxgearboxslip_4, qsfp2_gt_rxgearboxslip_3, qsfp2_gt_rxgearboxslip_2, qsfp2_gt_rxgearboxslip_1, qsfp1_gt_rxgearboxslip_4, qsfp1_gt_rxgearboxslip_3, qsfp1_gt_rxgearboxslip_2, qsfp1_gt_rxgearboxslip_1}),
.gtwiz_userdata_rx_out({qsfp2_gt_rxdata_4, qsfp2_gt_rxdata_3, qsfp2_gt_rxdata_2, qsfp2_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}),
.rxdatavalid_out({qsfp2_gt_rxdatavalid_4, qsfp2_gt_rxdatavalid_3, qsfp2_gt_rxdatavalid_2, qsfp2_gt_rxdatavalid_1, qsfp1_gt_rxdatavalid_4, qsfp1_gt_rxdatavalid_3, qsfp1_gt_rxdatavalid_2, qsfp1_gt_rxdatavalid_1}),
.rxheader_out({qsfp2_gt_rxheader_4, qsfp2_gt_rxheader_3, qsfp2_gt_rxheader_2, qsfp2_gt_rxheader_1, qsfp1_gt_rxheader_4, qsfp1_gt_rxheader_3, qsfp1_gt_rxheader_2, qsfp1_gt_rxheader_1}),
.rxheadervalid_out({qsfp2_gt_rxheadervalid_4, qsfp2_gt_rxheadervalid_3, qsfp2_gt_rxheadervalid_2, qsfp2_gt_rxheadervalid_1, qsfp1_gt_rxheadervalid_4, qsfp1_gt_rxheadervalid_3, qsfp1_gt_rxheadervalid_2, qsfp1_gt_rxheadervalid_1}),
.rxoutclk_out(gt_rxclkout),
.rxpmaresetdone_out(gt_rxpmaresetdone),
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
.rxstartofseq_out(),
.txoutclk_out(gt_txclkout),
.txpmaresetdone_out(gt_txpmaresetdone),
.txprgdivresetdone_out(gt_txprgdivresetdone)
);
assign qsfp1_tx_clk_1_int = clk_156mhz_int;
assign qsfp1_tx_rst_1_int = rst_156mhz_int;
assign qsfp1_rx_clk_1_int = gt_rxusrclk[0];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_1_reset_sync_inst (
.clk(qsfp1_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_1_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp1_phy_1_inst (
.tx_clk(qsfp1_tx_clk_1_int),
.tx_rst(qsfp1_tx_rst_1_int),
.rx_clk(qsfp1_rx_clk_1_int),
.rx_rst(qsfp1_rx_rst_1_int),
.xgmii_txd(qsfp1_txd_1_int),
.xgmii_txc(qsfp1_txc_1_int),
.xgmii_rxd(qsfp1_rxd_1_int),
.xgmii_rxc(qsfp1_rxc_1_int),
.serdes_tx_data(qsfp1_gt_txdata_1),
.serdes_tx_hdr(qsfp1_gt_txheader_1),
.serdes_rx_data(qsfp1_gt_rxdata_1),
.serdes_rx_hdr(qsfp1_gt_rxheader_1),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_1),
.rx_block_lock(qsfp1_rx_block_lock_1),
.rx_high_ber()
);
assign qsfp1_tx_clk_2_int = clk_156mhz_int;
assign qsfp1_tx_rst_2_int = rst_156mhz_int;
assign qsfp1_rx_clk_2_int = gt_rxusrclk[1];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_2_reset_sync_inst (
.clk(qsfp1_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_2_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp1_phy_2_inst (
.tx_clk(qsfp1_tx_clk_2_int),
.tx_rst(qsfp1_tx_rst_2_int),
.rx_clk(qsfp1_rx_clk_2_int),
.rx_rst(qsfp1_rx_rst_2_int),
.xgmii_txd(qsfp1_txd_2_int),
.xgmii_txc(qsfp1_txc_2_int),
.xgmii_rxd(qsfp1_rxd_2_int),
.xgmii_rxc(qsfp1_rxc_2_int),
.serdes_tx_data(qsfp1_gt_txdata_2),
.serdes_tx_hdr(qsfp1_gt_txheader_2),
.serdes_rx_data(qsfp1_gt_rxdata_2),
.serdes_rx_hdr(qsfp1_gt_rxheader_2),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_2),
.rx_block_lock(qsfp1_rx_block_lock_2),
.rx_high_ber()
);
assign qsfp1_tx_clk_3_int = clk_156mhz_int;
assign qsfp1_tx_rst_3_int = rst_156mhz_int;
assign qsfp1_rx_clk_3_int = gt_rxusrclk[2];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_3_reset_sync_inst (
.clk(qsfp1_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_3_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp1_phy_3_inst (
.tx_clk(qsfp1_tx_clk_3_int),
.tx_rst(qsfp1_tx_rst_3_int),
.rx_clk(qsfp1_rx_clk_3_int),
.rx_rst(qsfp1_rx_rst_3_int),
.xgmii_txd(qsfp1_txd_3_int),
.xgmii_txc(qsfp1_txc_3_int),
.xgmii_rxd(qsfp1_rxd_3_int),
.xgmii_rxc(qsfp1_rxc_3_int),
.serdes_tx_data(qsfp1_gt_txdata_3),
.serdes_tx_hdr(qsfp1_gt_txheader_3),
.serdes_rx_data(qsfp1_gt_rxdata_3),
.serdes_rx_hdr(qsfp1_gt_rxheader_3),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_3),
.rx_block_lock(qsfp1_rx_block_lock_3),
.rx_high_ber()
);
assign qsfp1_tx_clk_4_int = clk_156mhz_int;
assign qsfp1_tx_rst_4_int = rst_156mhz_int;
assign qsfp1_rx_clk_4_int = gt_rxusrclk[3];
sync_reset #(
.N(4)
)
qsfp1_rx_rst_4_reset_sync_inst (
.clk(qsfp1_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.out(qsfp1_rx_rst_4_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp1_phy_4_inst (
.tx_clk(qsfp1_tx_clk_4_int),
.tx_rst(qsfp1_tx_rst_4_int),
.rx_clk(qsfp1_rx_clk_4_int),
.rx_rst(qsfp1_rx_rst_4_int),
.xgmii_txd(qsfp1_txd_4_int),
.xgmii_txc(qsfp1_txc_4_int),
.xgmii_rxd(qsfp1_rxd_4_int),
.xgmii_rxc(qsfp1_rxc_4_int),
.serdes_tx_data(qsfp1_gt_txdata_4),
.serdes_tx_hdr(qsfp1_gt_txheader_4),
.serdes_rx_data(qsfp1_gt_rxdata_4),
.serdes_rx_hdr(qsfp1_gt_rxheader_4),
.serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_4),
.rx_block_lock(qsfp1_rx_block_lock_4),
.rx_high_ber()
);
assign qsfp2_tx_clk_1_int = clk_156mhz_int;
assign qsfp2_tx_rst_1_int = rst_156mhz_int;
assign qsfp2_rx_clk_1_int = gt_rxusrclk[4];
sync_reset #(
.N(4)
)
qsfp2_rx_rst_1_reset_sync_inst (
.clk(qsfp2_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.out(qsfp2_rx_rst_1_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp2_phy_1_inst (
.tx_clk(qsfp2_tx_clk_1_int),
.tx_rst(qsfp2_tx_rst_1_int),
.rx_clk(qsfp2_rx_clk_1_int),
.rx_rst(qsfp2_rx_rst_1_int),
.xgmii_txd(qsfp2_txd_1_int),
.xgmii_txc(qsfp2_txc_1_int),
.xgmii_rxd(qsfp2_rxd_1_int),
.xgmii_rxc(qsfp2_rxc_1_int),
.serdes_tx_data(qsfp2_gt_txdata_1),
.serdes_tx_hdr(qsfp2_gt_txheader_1),
.serdes_rx_data(qsfp2_gt_rxdata_1),
.serdes_rx_hdr(qsfp2_gt_rxheader_1),
.serdes_rx_bitslip(qsfp2_gt_rxgearboxslip_1),
.rx_block_lock(qsfp2_rx_block_lock_1),
.rx_high_ber()
);
assign qsfp2_tx_clk_2_int = clk_156mhz_int;
assign qsfp2_tx_rst_2_int = rst_156mhz_int;
assign qsfp2_rx_clk_2_int = gt_rxusrclk[5];
sync_reset #(
.N(4)
)
qsfp2_rx_rst_2_reset_sync_inst (
.clk(qsfp2_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.out(qsfp2_rx_rst_2_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp2_phy_2_inst (
.tx_clk(qsfp2_tx_clk_2_int),
.tx_rst(qsfp2_tx_rst_2_int),
.rx_clk(qsfp2_rx_clk_2_int),
.rx_rst(qsfp2_rx_rst_2_int),
.xgmii_txd(qsfp2_txd_2_int),
.xgmii_txc(qsfp2_txc_2_int),
.xgmii_rxd(qsfp2_rxd_2_int),
.xgmii_rxc(qsfp2_rxc_2_int),
.serdes_tx_data(qsfp2_gt_txdata_2),
.serdes_tx_hdr(qsfp2_gt_txheader_2),
.serdes_rx_data(qsfp2_gt_rxdata_2),
.serdes_rx_hdr(qsfp2_gt_rxheader_2),
.serdes_rx_bitslip(qsfp2_gt_rxgearboxslip_2),
.rx_block_lock(qsfp2_rx_block_lock_2),
.rx_high_ber()
);
assign qsfp2_tx_clk_3_int = clk_156mhz_int;
assign qsfp2_tx_rst_3_int = rst_156mhz_int;
assign qsfp2_rx_clk_3_int = gt_rxusrclk[6];
sync_reset #(
.N(4)
)
qsfp2_rx_rst_3_reset_sync_inst (
.clk(qsfp2_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.out(qsfp2_rx_rst_3_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp2_phy_3_inst (
.tx_clk(qsfp2_tx_clk_3_int),
.tx_rst(qsfp2_tx_rst_3_int),
.rx_clk(qsfp2_rx_clk_3_int),
.rx_rst(qsfp2_rx_rst_3_int),
.xgmii_txd(qsfp2_txd_3_int),
.xgmii_txc(qsfp2_txc_3_int),
.xgmii_rxd(qsfp2_rxd_3_int),
.xgmii_rxc(qsfp2_rxc_3_int),
.serdes_tx_data(qsfp2_gt_txdata_3),
.serdes_tx_hdr(qsfp2_gt_txheader_3),
.serdes_rx_data(qsfp2_gt_rxdata_3),
.serdes_rx_hdr(qsfp2_gt_rxheader_3),
.serdes_rx_bitslip(qsfp2_gt_rxgearboxslip_3),
.rx_block_lock(qsfp2_rx_block_lock_3),
.rx_high_ber()
);
assign qsfp2_tx_clk_4_int = clk_156mhz_int;
assign qsfp2_tx_rst_4_int = rst_156mhz_int;
assign qsfp2_rx_clk_4_int = gt_rxusrclk[7];
sync_reset #(
.N(4)
)
qsfp2_rx_rst_4_reset_sync_inst (
.clk(qsfp2_rx_clk_4_int),
.rst(~gt_reset_rx_done),
.out(qsfp2_rx_rst_4_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp2_phy_4_inst (
.tx_clk(qsfp2_tx_clk_4_int),
.tx_rst(qsfp2_tx_rst_4_int),
.rx_clk(qsfp2_rx_clk_4_int),
.rx_rst(qsfp2_rx_rst_4_int),
.xgmii_txd(qsfp2_txd_4_int),
.xgmii_txc(qsfp2_txc_4_int),
.xgmii_rxd(qsfp2_rxd_4_int),
.xgmii_rxc(qsfp2_rxc_4_int),
.serdes_tx_data(qsfp2_gt_txdata_4),
.serdes_tx_hdr(qsfp2_gt_txheader_4),
.serdes_rx_data(qsfp2_gt_rxdata_4),
.serdes_rx_hdr(qsfp2_gt_rxheader_4),
.serdes_rx_bitslip(qsfp2_gt_rxgearboxslip_4),
.rx_block_lock(qsfp2_rx_block_lock_4),
.rx_high_ber()
);
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire [15:0] gig_eth_pcspma_status_vector;
wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0];
wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1];
wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2];
wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3];
wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4];
wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5];
wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6];
wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7];
wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8];
wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10];
wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12];
wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13];
wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14];
wire [4:0] gig_eth_pcspma_config_vector;
assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate
assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down
assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable
assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] gig_eth_pcspma_an_config_vector;
assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved
assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_ethernet_pcs_pma_0
eth_pcspma (
// SGMII
.txp_0 (phy_sgmii_tx_p),
.txn_0 (phy_sgmii_tx_n),
.rxp_0 (phy_sgmii_rx_p),
.rxn_0 (phy_sgmii_rx_n),
// Ref clock from PHY
.refclk625_p (phy_sgmii_clk_p),
.refclk625_n (phy_sgmii_clk_n),
// async reset
.reset (rst_125mhz_int),
// clock and reset outputs
.clk125_out (phy_gmii_clk_int),
.clk312_out (),
.rst_125_out (phy_gmii_rst_int),
.tx_logic_reset (),
.rx_logic_reset (),
.tx_locked (),
.rx_locked (),
.tx_pll_clk_out (),
.rx_pll_clk_out (),
// MAC clocking
.sgmii_clk_r_0 (),
.sgmii_clk_f_0 (),
.sgmii_clk_en_0 (phy_gmii_clk_en_int),
// Speed control
.speed_is_10_100_0 (gig_eth_pcspma_status_speed != 2'b10),
.speed_is_100_0 (gig_eth_pcspma_status_speed == 2'b01),
// Internal GMII
.gmii_txd_0 (phy_gmii_txd_int),
.gmii_tx_en_0 (phy_gmii_tx_en_int),
.gmii_tx_er_0 (phy_gmii_tx_er_int),
.gmii_rxd_0 (phy_gmii_rxd_int),
.gmii_rx_dv_0 (phy_gmii_rx_dv_int),
.gmii_rx_er_0 (phy_gmii_rx_er_int),
.gmii_isolate_0 (),
// Configuration
.configuration_vector_0 (gig_eth_pcspma_config_vector),
.an_interrupt_0 (),
.an_adv_config_vector_0 (gig_eth_pcspma_an_config_vector),
.an_restart_config_0 (1'b0),
// Status
.status_vector_0 (gig_eth_pcspma_status_vector),
.signal_detect_0 (1'b1),
// Cascade
.tx_bsc_rst_out (),
.rx_bsc_rst_out (),
.tx_bs_rst_out (),
.rx_bs_rst_out (),
.tx_rst_dly_out (),
.rx_rst_dly_out (),
.tx_bsc_en_vtc_out (),
.rx_bsc_en_vtc_out (),
.tx_bs_en_vtc_out (),
.rx_bs_en_vtc_out (),
.riu_clk_out (),
.riu_addr_out (),
.riu_wr_data_out (),
.riu_wr_en_out (),
.riu_nibble_sel_out (),
.riu_rddata_1 (16'b0),
.riu_valid_1 (1'b0),
.riu_prsnt_1 (1'b0),
.riu_rddata_2 (16'b0),
.riu_valid_2 (1'b0),
.riu_prsnt_2 (1'b0),
.riu_rddata_3 (16'b0),
.riu_valid_3 (1'b0),
.riu_prsnt_3 (1'b0),
.rx_btval_1 (),
.rx_btval_2 (),
.rx_btval_3 (),
.tx_dly_rdy_1 (1'b1),
.rx_dly_rdy_1 (1'b1),
.rx_vtc_rdy_1 (1'b1),
.tx_vtc_rdy_1 (1'b1),
.tx_dly_rdy_2 (1'b1),
.rx_dly_rdy_2 (1'b1),
.rx_vtc_rdy_2 (1'b1),
.tx_vtc_rdy_2 (1'b1),
.tx_dly_rdy_3 (1'b1),
.rx_dly_rdy_3 (1'b1),
.rx_vtc_rdy_3 (1'b1),
.tx_vtc_rdy_3 (1'b1),
.tx_rdclk_out ()
);
reg [19:0] delay_reg = 20'hfffff;
reg [4:0] mdio_cmd_phy_addr = 5'h03;
reg [4:0] mdio_cmd_reg_addr = 5'h00;
reg [15:0] mdio_cmd_data = 16'd0;
reg [1:0] mdio_cmd_opcode = 2'b01;
reg mdio_cmd_valid = 1'b0;
wire mdio_cmd_ready;
reg [3:0] state_reg = 0;
always @(posedge clk_125mhz_int) begin
if (rst_125mhz_int) begin
state_reg <= 0;
delay_reg <= 20'hfffff;
mdio_cmd_reg_addr <= 5'h00;
mdio_cmd_data <= 16'd0;
mdio_cmd_valid <= 1'b0;
end else begin
mdio_cmd_valid <= mdio_cmd_valid & !mdio_cmd_ready;
if (delay_reg > 0) begin
delay_reg <= delay_reg - 1;
end else if (!mdio_cmd_ready) begin
// wait for ready
state_reg <= state_reg;
end else begin
mdio_cmd_valid <= 1'b0;
case (state_reg)
// set SGMII autonegotiation timer to 11 ms
// write 0x0070 to CFG4 (0x0031)
4'd0: begin
// write to REGCR to load address
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h001F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd1;
end
4'd1: begin
// write address of CFG4 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h0031;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd2;
end
4'd2: begin
// write to REGCR to load data
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h401F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd3;
end
4'd3: begin
// write data for CFG4 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h0070;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd4;
end
// enable SGMII clock output
// write 0x4000 to SGMIICTL1 (0x00D3)
4'd4: begin
// write to REGCR to load address
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h001F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd5;
end
4'd5: begin
// write address of SGMIICTL1 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h00D3;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd6;
end
4'd6: begin
// write to REGCR to load data
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h401F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd7;
end
4'd7: begin
// write data for SGMIICTL1 to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h4000;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd8;
end
// enable 10Mbps operation
// write 0x0015 to 10M_SGMII_CFG (0x016F)
4'd8: begin
// write to REGCR to load address
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h001F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd9;
end
4'd9: begin
// write address of 10M_SGMII_CFG to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h016F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd10;
end
4'd10: begin
// write to REGCR to load data
mdio_cmd_reg_addr <= 5'h0D;
mdio_cmd_data <= 16'h401F;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd11;
end
4'd11: begin
// write data for 10M_SGMII_CFG to ADDAR
mdio_cmd_reg_addr <= 5'h0E;
mdio_cmd_data <= 16'h0015;
mdio_cmd_valid <= 1'b1;
state_reg <= 4'd12;
end
4'd12: begin
// done
state_reg <= 4'd12;
end
endcase
end
end
end
wire mdc;
wire mdio_i;
wire mdio_o;
wire mdio_t;
mdio_master
mdio_master_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.cmd_phy_addr(mdio_cmd_phy_addr),
.cmd_reg_addr(mdio_cmd_reg_addr),
.cmd_data(mdio_cmd_data),
.cmd_opcode(mdio_cmd_opcode),
.cmd_valid(mdio_cmd_valid),
.cmd_ready(mdio_cmd_ready),
.data_out(),
.data_out_valid(),
.data_out_ready(1'b1),
.mdc_o(mdc),
.mdio_i(mdio_i),
.mdio_o(mdio_o),
.mdio_t(mdio_t),
.busy(),
.prescale(8'd3)
);
assign phy_mdc = mdc;
assign mdio_i = phy_mdio;
assign phy_mdio = mdio_t ? 1'bz : mdio_o;
wire [7:0] led_int;
assign led = sw[0] ? {qsfp2_rx_block_lock_4, qsfp2_rx_block_lock_3, qsfp2_rx_block_lock_2, qsfp2_rx_block_lock_1, qsfp1_rx_block_lock_4, qsfp1_rx_block_lock_3, qsfp1_rx_block_lock_2, qsfp1_rx_block_lock_1} : led_int;
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led_int),
/*
* Ethernet: QSFP28
*/
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp2_tx_clk_1(qsfp2_tx_clk_1_int),
.qsfp2_tx_rst_1(qsfp2_tx_rst_1_int),
.qsfp2_txd_1(qsfp2_txd_1_int),
.qsfp2_txc_1(qsfp2_txc_1_int),
.qsfp2_rx_clk_1(qsfp2_rx_clk_1_int),
.qsfp2_rx_rst_1(qsfp2_rx_rst_1_int),
.qsfp2_rxd_1(qsfp2_rxd_1_int),
.qsfp2_rxc_1(qsfp2_rxc_1_int),
.qsfp2_tx_clk_2(qsfp2_tx_clk_2_int),
.qsfp2_tx_rst_2(qsfp2_tx_rst_2_int),
.qsfp2_txd_2(qsfp2_txd_2_int),
.qsfp2_txc_2(qsfp2_txc_2_int),
.qsfp2_rx_clk_2(qsfp2_rx_clk_2_int),
.qsfp2_rx_rst_2(qsfp2_rx_rst_2_int),
.qsfp2_rxd_2(qsfp2_rxd_2_int),
.qsfp2_rxc_2(qsfp2_rxc_2_int),
.qsfp2_tx_clk_3(qsfp2_tx_clk_3_int),
.qsfp2_tx_rst_3(qsfp2_tx_rst_3_int),
.qsfp2_txd_3(qsfp2_txd_3_int),
.qsfp2_txc_3(qsfp2_txc_3_int),
.qsfp2_rx_clk_3(qsfp2_rx_clk_3_int),
.qsfp2_rx_rst_3(qsfp2_rx_rst_3_int),
.qsfp2_rxd_3(qsfp2_rxd_3_int),
.qsfp2_rxc_3(qsfp2_rxc_3_int),
.qsfp2_tx_clk_4(qsfp2_tx_clk_4_int),
.qsfp2_tx_rst_4(qsfp2_tx_rst_4_int),
.qsfp2_txd_4(qsfp2_txd_4_int),
.qsfp2_txc_4(qsfp2_txc_4_int),
.qsfp2_rx_clk_4(qsfp2_rx_clk_4_int),
.qsfp2_rx_rst_4(qsfp2_rx_rst_4_int),
.qsfp2_rxd_4(qsfp2_rxd_4_int),
.qsfp2_rxc_4(qsfp2_rxc_4_int),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
|
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module memphy_alt_mem_phy_seq_wrapper (
// dss ports
phy_clk_1x,
reset_phy_clk_1x_n,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
ctl_cal_req,
int_RANK_HAS_ADDR_SWAP,
ctl_cal_byte_lane_sel_n,
seq_pll_inc_dec_n,
seq_pll_start_reconfig,
seq_pll_select,
phs_shft_busy,
pll_resync_clk_index,
pll_measure_clk_index,
sc_clk_dp,
scan_enable_dqs_config,
scan_update,
scan_din,
scan_enable_ck,
scan_enable_dqs,
scan_enable_dqsn,
scan_enable_dq,
scan_enable_dm,
hr_rsc_clk,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n,
seq_ac_sel,
seq_mem_clk_disable,
ctl_add_1t_ac_lat_internal,
ctl_add_1t_odt_lat_internal,
ctl_add_intermediate_regs_internal,
seq_rdv_doing_rd,
seq_rdp_reset_req_n,
seq_rdp_inc_read_lat_1x,
seq_rdp_dec_read_lat_1x,
ctl_rdata,
int_rdata_valid_1t,
seq_rdata_valid_lat_inc,
seq_rdata_valid_lat_dec,
ctl_rlat,
seq_poa_lat_dec_1x,
seq_poa_lat_inc_1x,
seq_poa_protection_override_1x,
seq_oct_oct_delay,
seq_oct_oct_extend,
seq_oct_val,
seq_wdp_dqs_burst,
seq_wdp_wdata_valid,
seq_wdp_wdata,
seq_wdp_dm,
seq_wdp_dqs,
seq_wdp_ovride,
seq_dqs_add_2t_delay,
ctl_wlat,
seq_mmc_start,
mmc_seq_done,
mmc_seq_value,
mem_err_out_n,
parity_error_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
//Inserted Generics
localparam SPEED_GRADE = "C8";
localparam MEM_IF_DQS_WIDTH = 1;
localparam MEM_IF_DWIDTH = 8;
localparam MEM_IF_DM_WIDTH = 1;
localparam MEM_IF_DQ_PER_DQS = 8;
localparam DWIDTH_RATIO = 4;
localparam CLOCK_INDEX_WIDTH = 3;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_ADDR_WIDTH = 14;
localparam MEM_IF_BANKADDR_WIDTH = 2;
localparam MEM_IF_CS_WIDTH = 1;
localparam RESYNCHRONISE_AVALON_DBG = 0;
localparam DBG_A_WIDTH = 13;
localparam DQS_PHASE_SETTING = 2;
localparam SCAN_CLK_DIVIDE_BY = 2;
localparam PLL_STEPS_PER_CYCLE = 80;
localparam MEM_IF_CLK_PS = 7692;
localparam DQS_DELAY_CTL_WIDTH = 6;
localparam MEM_IF_MEMTYPE = "DDR2";
localparam RANK_HAS_ADDR_SWAP = 0;
localparam MEM_IF_MR_0 = 578;
localparam MEM_IF_MR_1 = 1024;
localparam MEM_IF_MR_2 = 0;
localparam MEM_IF_MR_3 = 0;
localparam MEM_IF_OCT_EN = 0;
localparam IP_BUILDNUM = 0;
localparam FAMILY = "Cyclone IV E";
localparam FAMILYGROUP_ID = 2;
localparam MEM_IF_ADDR_CMD_PHASE = 90;
localparam CAPABILITIES = 2048;
localparam WRITE_DESKEW_T10 = 0;
localparam WRITE_DESKEW_HC_T10 = 0;
localparam WRITE_DESKEW_T9NI = 0;
localparam WRITE_DESKEW_HC_T9NI = 0;
localparam WRITE_DESKEW_T9I = 0;
localparam WRITE_DESKEW_HC_T9I = 0;
localparam WRITE_DESKEW_RANGE = 0;
localparam IOE_PHASES_PER_TCK = 12;
localparam ADV_LAT_WIDTH = 5;
localparam RDP_ADDR_WIDTH = 4;
localparam IOE_DELAYS_PER_PHS = 5;
localparam SINGLE_DQS_DELAY_CONTROL_CODE = 0;
localparam PRESET_RLAT = 0;
localparam FORCE_HC = 0;
localparam MEM_IF_DQS_CAPTURE_EN = 0;
localparam REDUCE_SIM_TIME = 0;
localparam TINIT_TCK = 13001;
localparam TINIT_RST = 0;
localparam GENERATE_ADDITIONAL_DBG_RTL = 0;
localparam MEM_IF_CS_PER_RANK = 1;
localparam MEM_IF_RANKS_PER_SLOT = 1;
localparam CHIP_OR_DIMM = "Discrete Device";
localparam RDIMM_CONFIG_BITS = "0000000000000000000000000000000000000000000000000000000000000000";
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
localparam GENERATE_TRACKING_PHASE_STORE = 0;
// note that num_ranks if the number of discrete chip select signals output from the sequencer
// cs_width is the total number of chip selects which go from the phy to the memory (there can
// be more than one chip select per rank).
localparam MEM_IF_NUM_RANKS = MEM_IF_CS_WIDTH/MEM_IF_CS_PER_RANK;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
input wire ctl_cal_req;
input wire [MEM_IF_NUM_RANKS - 1 : 0] int_RANK_HAS_ADDR_SWAP;
input wire [MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
output wire seq_pll_inc_dec_n;
output wire seq_pll_start_reconfig;
output wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
input wire phs_shft_busy;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
output [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs_config;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_update;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_din;
output wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqsn;
output wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
output wire [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
input wire hr_rsc_clk;
output wire [(DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 : 0] seq_ac_addr;
output wire [(DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 : 0] seq_ac_ba;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_cas_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_ras_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_we_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_cke;
output wire [(DWIDTH_RATIO/2) * MEM_IF_CS_WIDTH - 1 : 0] seq_ac_cs_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_odt;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_rst_n;
output wire seq_ac_sel;
output wire seq_mem_clk_disable;
output wire ctl_add_1t_ac_lat_internal;
output wire ctl_add_1t_odt_lat_internal;
output wire ctl_add_intermediate_regs_internal;
output wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_rdv_doing_rd;
output wire seq_rdp_reset_req_n;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_inc_read_lat_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_dec_read_lat_1x;
input wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] ctl_rdata;
input wire [DWIDTH_RATIO/2 - 1 : 0] int_rdata_valid_1t;
output wire seq_rdata_valid_lat_inc;
output wire seq_rdata_valid_lat_dec;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_rlat;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_dec_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_inc_1x;
output wire seq_poa_protection_override_1x;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend;
output wire seq_oct_val;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_dqs_burst;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_wdata_valid;
output wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] seq_wdp_wdata;
output wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0] seq_wdp_dm;
output wire [DWIDTH_RATIO - 1 : 0] seq_wdp_dqs;
output wire seq_wdp_ovride;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_dqs_add_2t_delay;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_wlat;
output wire seq_mmc_start;
input wire mmc_seq_done;
input wire mmc_seq_value;
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH - 1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [ 31 : 0] dbg_wr_data;
output wire [ 31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
input wire mem_err_out_n;
output wire parity_error_n;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// instantiate the deskew (DDR3) or non-deskew (DDR/DDR2/DDR3) sequencer:
//
memphy_alt_mem_phy_seq #(
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.DWIDTH_RATIO (DWIDTH_RATIO),
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_ADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
.MEM_IF_RANKS_PER_SLOT (MEM_IF_RANKS_PER_SLOT),
.ADV_LAT_WIDTH (ADV_LAT_WIDTH),
.RESYNCHRONISE_AVALON_DBG (RESYNCHRONISE_AVALON_DBG),
.AV_IF_ADDR_WIDTH (DBG_A_WIDTH),
.NOM_DQS_PHASE_SETTING (DQS_PHASE_SETTING),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.RDP_ADDR_WIDTH (RDP_ADDR_WIDTH),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE),
.IOE_PHASES_PER_TCK (IOE_PHASES_PER_TCK),
.IOE_DELAYS_PER_PHS (IOE_DELAYS_PER_PHS),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.PHY_DEF_MR_1ST (MEM_IF_MR_0),
.PHY_DEF_MR_2ND (MEM_IF_MR_1),
.PHY_DEF_MR_3RD (MEM_IF_MR_2),
.PHY_DEF_MR_4TH (MEM_IF_MR_3),
.MEM_IF_DQSN_EN (0),
.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
.FAMILY (FAMILY),
.FAMILYGROUP_ID (FAMILYGROUP_ID),
.SPEED_GRADE (SPEED_GRADE),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.WRITE_DESKEW_T10 (WRITE_DESKEW_T10),
.WRITE_DESKEW_HC_T10 (WRITE_DESKEW_HC_T10),
.WRITE_DESKEW_T9NI (WRITE_DESKEW_T9NI),
.WRITE_DESKEW_HC_T9NI (WRITE_DESKEW_HC_T9NI),
.WRITE_DESKEW_T9I (WRITE_DESKEW_T9I),
.WRITE_DESKEW_HC_T9I (WRITE_DESKEW_HC_T9I),
.WRITE_DESKEW_RANGE (WRITE_DESKEW_RANGE),
.SINGLE_DQS_DELAY_CONTROL_CODE (SINGLE_DQS_DELAY_CONTROL_CODE),
.PRESET_RLAT (PRESET_RLAT),
.EN_OCT (MEM_IF_OCT_EN),
.SIM_TIME_REDUCTIONS (REDUCE_SIM_TIME),
.FORCE_HC (FORCE_HC),
.CAPABILITIES (CAPABILITIES),
.GENERATE_ADDITIONAL_DBG_RTL (GENERATE_ADDITIONAL_DBG_RTL),
.TINIT_TCK (TINIT_TCK),
.TINIT_RST (TINIT_RST),
.GENERATE_TRACKING_PHASE_STORE (0),
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
.IP_BUILDNUM (IP_BUILDNUM),
.CHIP_OR_DIMM (CHIP_OR_DIMM),
.RDIMM_CONFIG_BITS (RDIMM_CONFIG_BITS)
) seq_inst (
.clk (phy_clk_1x),
.rst_n (reset_phy_clk_1x_n),
.ctl_init_success (ctl_cal_success),
.ctl_init_fail (ctl_cal_fail),
.ctl_init_warning (ctl_cal_warning),
.ctl_recalibrate_req (ctl_cal_req),
.MEM_AC_SWAPPED_RANKS (int_RANK_HAS_ADDR_SWAP),
.ctl_cal_byte_lanes (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.seq_pll_phs_shift_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.seq_scan_clk (sc_clk_dp),
.seq_scan_enable_dqs_config (scan_enable_dqs_config),
.seq_scan_update (scan_update),
.seq_scan_din (scan_din),
.seq_scan_enable_ck (scan_enable_ck),
.seq_scan_enable_dqs (scan_enable_dqs),
.seq_scan_enable_dqsn (scan_enable_dqsn),
.seq_scan_enable_dq (scan_enable_dq),
.seq_scan_enable_dm (scan_enable_dm),
.hr_rsc_clk (hr_rsc_clk),
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.seq_ac_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.seq_ac_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.seq_ac_add_2t (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_rdv_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.rdata (ctl_rdata),
.rdata_valid (int_rdata_valid_1t),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_value (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.seq_ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (mem_err_out_n),
.parity_error_n (parity_error_n),
.dbg_seq_clk (dbg_clk),
.dbg_seq_rst_n (dbg_reset_n),
.dbg_seq_addr (dbg_addr),
.dbg_seq_wr (dbg_wr),
.dbg_seq_rd (dbg_rd),
.dbg_seq_cs (dbg_cs),
.dbg_seq_wr_data (dbg_wr_data),
.seq_dbg_rd_data (dbg_rd_data),
.seq_dbg_waitrequest (dbg_waitrequest)
);
endmodule
|
module draw_screen(
input clk,
output [X_ADDR_WIDTH - 1 : 0] x,
output [Y_ADDR_WIDTH - 1 : 0] y,
output vs,
output vs_valid,
output hs,
output hs_valid
);
localparam X_MAX = 64;
localparam Y_MAX = 32;
localparam X_ADDR_WIDTH = $clog2(X_MAX);
localparam Y_ADDR_WIDTH = $clog2(Y_MAX);
localparam X_PIX = 640;
localparam Y_PIX = 480;
localparam X_DIV = X_PIX / X_MAX;
localparam Y_DIV = Y_PIX / Y_MAX;
localparam X_DIV_WIDTH = $clog2(X_DIV);
localparam Y_DIV_WIDTH = $clog2(Y_DIV);
reg [X_DIV_WIDTH - 1 : 0] x_div_ctr = 0;
reg [Y_DIV_WIDTH - 1 : 0] y_div_ctr = 0;
reg [X_ADDR_WIDTH - 1 : 0] _x = 0;
reg [Y_ADDR_WIDTH - 1 : 0] _y = 0;
wire _hs_valid, _vs_valid;
assign vs_valid = _vs_valid;
assign hs_valid = _hs_valid;
assign x = _x;
assign y = _y;
always @ (posedge clk)
begin
if (_hs_valid)
begin
if (x_div_ctr == X_DIV - 1)
begin
x_div_ctr <= 0;
end
else
begin
x_div_ctr <= x_div_ctr + 1;
end
end
else
begin
x_div_ctr <= 0;
end
end // always @ (posedge clk)
always @ (posedge clk)
begin
if (_vs_valid)
begin
if ( (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
y_div_ctr <= 0;
end
else if( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
y_div_ctr <= y_div_ctr + 1;
end
end
else
begin
y_div_ctr <= 0;
end
end
always @ (posedge clk)
begin
if ( (_x == X_MAX - 1) & (x_div_ctr == X_DIV - 1) )
begin
_x <= 0;
end
else if (x_div_ctr == X_DIV - 1)
begin
_x <= x + 1;
end
end
always @ (posedge clk)
begin
if ( (_y == Y_MAX - 1) & (y_div_ctr == Y_DIV - 1))
begin
_y <= 0;
end
else if ( (x_div_ctr == X_DIV - 1) & (y_div_ctr == Y_DIV - 1) & (_x == X_MAX - 1))
begin
_y <= _y + 1;
end
end
vga vga(
.clk(clk),
.vs_o(vs),
.vs_valid(_vs_valid),
.hs_o(hs),
.hs_valid(_hs_valid)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:29:10 04/17/2008
// Design Name:
// Module Name: DelayElement
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pdl_block(i,o,t);
(* KEEP = "TRUE" *) (* S = "TRUE" *) input i;
(* KEEP = "TRUE" *) (* S = "TRUE" *) input t;
(* KEEP = "TRUE" *) (* S = "TRUE" *) output o;
(* KEEP = "TRUE" *) (* S = "TRUE" *) wire w;
(* KEEP = "TRUE" *) (* S = "TRUE" *) wire t;
(* BEL ="D6LUT" *) //(* LOCK_PINS = "all" *)
LUT6 #(
.INIT(64'h5655555555555555) // Specify LUT Contents
) LUT6_inst_1 (
.O(w), // LUT general output
.I0(i), // LUT input
.I1(t), // LUT input
.I2(t), // LUT input
.I3(t), // LUT input
.I4(t), // LUT input
.I5(t) // LUT input
);
// End of LUT6_inst instantiation
(* BEL ="D6LUT" *) //(* LOCK_PINS = "all" *)
LUT6 #(
.INIT(64'h5655555555555555) // Specify LUT Contents
) LUT6_inst_0 (
.O(o), // LUT general output
.I0(w), // LUT input
.I1(t), // LUT input
.I2(t), // LUT input
.I3(t), // LUT input
.I4(t), // LUT input
.I5(t) // LUT input
);
// End of LUT6_inst instantiation
endmodule |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Instruction_Memory.v when simulating
// the core, Instruction_Memory. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Instruction_Memory(
a,
spo
);
input [13 : 0] a;
output [31 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(14),
.C_DEFAULT_DATA("0"),
.C_DEPTH(16384),
.C_FAMILY("spartan6"),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("Instruction_Memory.mif"),
.C_MEM_TYPE(0),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32)
)
inst (
.A(a),
.SPO(spo),
.D(),
.DPRA(),
.SPRA(),
.CLK(),
.WE(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBP_TB_V
`define SKY130_FD_SC_HD__DLXBP_TB_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hd__dlxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBP_TB_V
|
module instr_mem ( input [31:0] address,
output [31:0] instruction );
reg [31:0] memory [249:0];
integer i;
initial
begin
for (i=0; i<250; i=i+1) memory[i] = 32'b0;
// Insert MIPS's assembly here start at memory[10] = ...
//memory[10] = 32'b001000_00000_01000_0000000000000010; //addi $t0, $0, 2
//memory[11] = 32'b101011_01000_01001_0000000000000000; //110100 sw
//memory[12] = 32'b100011_01000_01100_0000000000000000; // 111000 lw
memory[10] = 32'b001000_00000_01000_0000000000000010; //addi $t0, $0, 2
memory[11] = 32'b001000_00000_01001_0000000000000010; //addi $t1, $0, 2
memory[12] = 32'b001000_00000_01011_0000000000000010; //addi $t1, $0, 2
memory[13] = 32'b000011_00000000000000000000001000;
/*memory[13] = 32'b000100_01000_01001_0000000000000010; //branch
memory[14] = 32'b001000_00000_01010_0000000000000010; //addi $t2, $0, 2
memory[15] = 32'b001000_00000_01100_0000000000000001; //addi $t3, $0, 1
memory[16] = 32'b001000_00000_01101_0000000000000011; //addi $t4, $0, 3
memory[17] = 32'b001000_00000_01000_0000000000000010; //addi $t0, $0, 2
memory[18] = 32'b101011_01100_01000_0000011111010000; //sw $t4(rs),$t0(rt)
memory[19] = 32'b100011_01000_01100_0000011111010000; //lw $t0(rs) ,$t4(rt)*/
end
assign instruction = memory[address >> 2];
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:30:56 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_exp_operation_A_S, intAS,
sign_final_result, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756,
n757, n758, n759, n760, n761, n762, n763, n764, n765,
DP_OP_42J129_122_8048_n20, DP_OP_42J129_122_8048_n19,
DP_OP_42J129_122_8048_n18, DP_OP_42J129_122_8048_n17,
DP_OP_42J129_122_8048_n16, DP_OP_42J129_122_8048_n15,
DP_OP_42J129_122_8048_n14, DP_OP_42J129_122_8048_n13,
DP_OP_42J129_122_8048_n8, DP_OP_42J129_122_8048_n7,
DP_OP_42J129_122_8048_n6, DP_OP_42J129_122_8048_n5,
DP_OP_42J129_122_8048_n4, DP_OP_42J129_122_8048_n3,
DP_OP_42J129_122_8048_n2, DP_OP_42J129_122_8048_n1,
DP_OP_45J129_125_5354_n56, DP_OP_45J129_125_5354_n55,
DP_OP_45J129_125_5354_n54, DP_OP_45J129_125_5354_n53,
DP_OP_45J129_125_5354_n52, DP_OP_45J129_125_5354_n51,
DP_OP_45J129_125_5354_n50, DP_OP_45J129_125_5354_n49,
DP_OP_45J129_125_5354_n48, DP_OP_45J129_125_5354_n47,
DP_OP_45J129_125_5354_n46, DP_OP_45J129_125_5354_n45,
DP_OP_45J129_125_5354_n44, DP_OP_45J129_125_5354_n43,
DP_OP_45J129_125_5354_n42, DP_OP_45J129_125_5354_n41,
DP_OP_45J129_125_5354_n40, DP_OP_45J129_125_5354_n39,
DP_OP_45J129_125_5354_n38, DP_OP_45J129_125_5354_n37,
DP_OP_45J129_125_5354_n36, DP_OP_45J129_125_5354_n35,
DP_OP_45J129_125_5354_n34, DP_OP_45J129_125_5354_n33,
DP_OP_45J129_125_5354_n32, DP_OP_45J129_125_5354_n31,
DP_OP_45J129_125_5354_n26, DP_OP_45J129_125_5354_n25,
DP_OP_45J129_125_5354_n24, DP_OP_45J129_125_5354_n23,
DP_OP_45J129_125_5354_n22, DP_OP_45J129_125_5354_n21,
DP_OP_45J129_125_5354_n20, DP_OP_45J129_125_5354_n19,
DP_OP_45J129_125_5354_n18, DP_OP_45J129_125_5354_n17,
DP_OP_45J129_125_5354_n16, DP_OP_45J129_125_5354_n15,
DP_OP_45J129_125_5354_n14, DP_OP_45J129_125_5354_n13,
DP_OP_45J129_125_5354_n12, DP_OP_45J129_125_5354_n11,
DP_OP_45J129_125_5354_n10, DP_OP_45J129_125_5354_n9,
DP_OP_45J129_125_5354_n8, DP_OP_45J129_125_5354_n7,
DP_OP_45J129_125_5354_n6, DP_OP_45J129_125_5354_n5,
DP_OP_45J129_125_5354_n4, DP_OP_45J129_125_5354_n3,
DP_OP_45J129_125_5354_n2, DP_OP_45J129_125_5354_n1, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329,
n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349,
n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359,
n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429,
n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459,
n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489,
n1490, n1491, n1492, n1493, n1494;
wire [1:0] FSM_selector_B;
wire [31:0] intDX;
wire [31:0] intDY;
wire [30:0] DMP;
wire [30:0] DmP;
wire [7:0] exp_oper_result;
wire [7:0] S_Oper_A_exp;
wire [4:0] LZA_output;
wire [25:0] Add_Subt_result;
wire [25:0] Sgf_normalized_result;
wire [25:0] S_A_S_Oper_A;
wire [3:0] FS_Module_state_reg;
wire [7:0] Exp_Operation_Module_Data_S;
wire [25:0] Add_Subt_Sgf_module_S_to_D;
wire [51:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n732), .CK(
clk), .RN(n1475), .Q(LZA_output[0]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n1478),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n1477),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n689),
.CK(clk), .RN(n1493), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n688),
.CK(clk), .RN(n1487), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n687),
.CK(clk), .RN(n1486), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n686),
.CK(clk), .RN(n797), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n685),
.CK(clk), .RN(n796), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n684),
.CK(clk), .RN(n1484), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n683),
.CK(clk), .RN(n1478), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n682),
.CK(clk), .RN(n1482), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n681),
.CK(clk), .RN(n1475), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n680),
.CK(clk), .RN(n1479), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n679),
.CK(clk), .RN(n1490), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n678),
.CK(clk), .RN(n1484), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n677),
.CK(clk), .RN(n1482), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n676),
.CK(clk), .RN(n1479), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n675),
.CK(clk), .RN(n1475), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n674),
.CK(clk), .RN(n1490), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n673),
.CK(clk), .RN(n1479), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n672),
.CK(clk), .RN(n1483), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n671),
.CK(clk), .RN(n1494), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n670),
.CK(clk), .RN(n1492), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n669),
.CK(clk), .RN(n1483), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n668),
.CK(clk), .RN(n1480), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n667),
.CK(clk), .RN(n1479), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n666),
.CK(clk), .RN(n1494), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n665),
.CK(clk), .RN(n1492), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n664),
.CK(clk), .RN(n1483), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n663),
.CK(clk), .RN(n1480), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n662),
.CK(clk), .RN(n1479), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n661),
.CK(clk), .RN(n1494), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n660),
.CK(clk), .RN(n1478), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n659),
.CK(clk), .RN(n1478), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n657),
.CK(clk), .RN(n1478), .Q(final_result_ieee[31]) );
DFFRXLTS ASRegister_Q_reg_0_ ( .D(n623), .CK(clk), .RN(n797), .Q(intAS) );
DFFRXLTS YRegister_Q_reg_31_ ( .D(n591), .CK(clk), .RN(n1493), .Q(intDY[31])
);
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n590), .CK(clk), .RN(
n1491), .Q(DMP[29]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n589), .CK(clk), .RN(
n1476), .Q(DMP[28]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n588), .CK(clk), .RN(
n796), .Q(DMP[27]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n587), .CK(clk), .RN(
n797), .Q(DMP[26]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n586), .CK(clk), .RN(
n1485), .Q(DMP[25]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n585), .CK(clk), .RN(
n1487), .Q(DMP[24]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n584), .CK(clk), .RN(
n1492), .Q(DMP[23]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n580), .CK(clk), .RN(
n1481), .Q(DMP[19]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n579), .CK(clk), .RN(
n1486), .Q(DMP[18]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n578), .CK(clk), .RN(
n1487), .Q(DMP[17]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n577), .CK(clk), .RN(
n1476), .Q(DMP[16]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n576), .CK(clk), .RN(
n1485), .Q(DMP[15]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n575), .CK(clk), .RN(
n1481), .Q(DMP[14]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n574), .CK(clk), .RN(
n1481), .Q(DMP[13]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n573), .CK(clk), .RN(
n1477), .Q(DMP[12]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n572), .CK(clk), .RN(
n1488), .Q(DMP[11]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n571), .CK(clk), .RN(
n1491), .Q(DMP[10]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n560), .CK(clk), .RN(
n1490), .Q(DMP[30]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n558), .CK(clk), .RN(
n1480), .Q(DmP[29]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n557), .CK(clk), .RN(
n1479), .Q(DmP[28]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n556), .CK(clk), .RN(
n1492), .Q(DmP[27]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n555), .CK(clk), .RN(
n1480), .Q(DmP[26]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n554), .CK(clk), .RN(
n1483), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n553), .CK(clk), .RN(
n1492), .Q(DmP[24]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n552), .CK(clk), .RN(
n1481), .Q(DmP[23]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n551), .CK(clk), .RN(
n1487), .Q(DmP[22]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n550), .CK(clk), .RN(
n1486), .Q(DmP[21]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n548), .CK(clk), .RN(
n1484), .Q(DmP[19]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n547), .CK(clk), .RN(
n1484), .Q(DmP[18]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n546), .CK(clk), .RN(
n1484), .Q(DmP[17]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n545), .CK(clk), .RN(
n1484), .Q(DmP[16]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n544), .CK(clk), .RN(
n1484), .Q(DmP[15]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n543), .CK(clk), .RN(
n1484), .Q(DmP[14]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n542), .CK(clk), .RN(
n1484), .Q(DmP[13]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n541), .CK(clk), .RN(
n1484), .Q(DmP[12]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n540), .CK(clk), .RN(
n1484), .Q(DmP[11]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n539), .CK(clk), .RN(
n1484), .Q(DmP[10]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n538), .CK(clk), .RN(
n1484), .Q(DmP[9]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n537), .CK(clk), .RN(
n1484), .Q(DmP[8]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n536), .CK(clk), .RN(
n1492), .Q(DmP[7]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n535), .CK(clk), .RN(
n1483), .Q(DmP[6]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n534), .CK(clk), .RN(
n1480), .Q(DmP[5]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n533), .CK(clk), .RN(
n1479), .Q(DmP[4]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n532), .CK(clk), .RN(
n1494), .Q(DmP[3]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n531), .CK(clk), .RN(
n1492), .Q(DmP[2]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n528), .CK(clk), .RN(
n1494), .Q(DmP[30]) );
CMPR32X2TS DP_OP_42J129_122_8048_U8 ( .A(DP_OP_42J129_122_8048_n19), .B(
S_Oper_A_exp[1]), .C(DP_OP_42J129_122_8048_n8), .CO(
DP_OP_42J129_122_8048_n7), .S(Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_42J129_122_8048_U7 ( .A(DP_OP_42J129_122_8048_n18), .B(
S_Oper_A_exp[2]), .C(DP_OP_42J129_122_8048_n7), .CO(
DP_OP_42J129_122_8048_n6), .S(Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_42J129_122_8048_U6 ( .A(DP_OP_42J129_122_8048_n17), .B(
S_Oper_A_exp[3]), .C(DP_OP_42J129_122_8048_n6), .CO(
DP_OP_42J129_122_8048_n5), .S(Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_42J129_122_8048_U5 ( .A(DP_OP_42J129_122_8048_n16), .B(
S_Oper_A_exp[4]), .C(DP_OP_42J129_122_8048_n5), .CO(
DP_OP_42J129_122_8048_n4), .S(Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_42J129_122_8048_U4 ( .A(DP_OP_42J129_122_8048_n15), .B(
S_Oper_A_exp[5]), .C(DP_OP_42J129_122_8048_n4), .CO(
DP_OP_42J129_122_8048_n3), .S(Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_42J129_122_8048_U3 ( .A(DP_OP_42J129_122_8048_n14), .B(
S_Oper_A_exp[6]), .C(DP_OP_42J129_122_8048_n3), .CO(
DP_OP_42J129_122_8048_n2), .S(Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_42J129_122_8048_U2 ( .A(DP_OP_42J129_122_8048_n13), .B(
S_Oper_A_exp[7]), .C(DP_OP_42J129_122_8048_n2), .CO(
DP_OP_42J129_122_8048_n1), .S(Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_45J129_125_5354_U27 ( .A(S_A_S_Oper_A[0]), .B(n1472), .C(
DP_OP_45J129_125_5354_n56), .CO(DP_OP_45J129_125_5354_n26), .S(
Add_Subt_Sgf_module_S_to_D[0]) );
CMPR32X2TS DP_OP_45J129_125_5354_U26 ( .A(DP_OP_45J129_125_5354_n55), .B(
S_A_S_Oper_A[1]), .C(DP_OP_45J129_125_5354_n26), .CO(
DP_OP_45J129_125_5354_n25), .S(Add_Subt_Sgf_module_S_to_D[1]) );
CMPR32X2TS DP_OP_45J129_125_5354_U25 ( .A(DP_OP_45J129_125_5354_n54), .B(
S_A_S_Oper_A[2]), .C(DP_OP_45J129_125_5354_n25), .CO(
DP_OP_45J129_125_5354_n24), .S(Add_Subt_Sgf_module_S_to_D[2]) );
CMPR32X2TS DP_OP_45J129_125_5354_U24 ( .A(DP_OP_45J129_125_5354_n53), .B(
S_A_S_Oper_A[3]), .C(DP_OP_45J129_125_5354_n24), .CO(
DP_OP_45J129_125_5354_n23), .S(Add_Subt_Sgf_module_S_to_D[3]) );
CMPR32X2TS DP_OP_45J129_125_5354_U23 ( .A(DP_OP_45J129_125_5354_n52), .B(
S_A_S_Oper_A[4]), .C(DP_OP_45J129_125_5354_n23), .CO(
DP_OP_45J129_125_5354_n22), .S(Add_Subt_Sgf_module_S_to_D[4]) );
CMPR32X2TS DP_OP_45J129_125_5354_U22 ( .A(DP_OP_45J129_125_5354_n51), .B(
S_A_S_Oper_A[5]), .C(DP_OP_45J129_125_5354_n22), .CO(
DP_OP_45J129_125_5354_n21), .S(Add_Subt_Sgf_module_S_to_D[5]) );
CMPR32X2TS DP_OP_45J129_125_5354_U21 ( .A(DP_OP_45J129_125_5354_n50), .B(
S_A_S_Oper_A[6]), .C(DP_OP_45J129_125_5354_n21), .CO(
DP_OP_45J129_125_5354_n20), .S(Add_Subt_Sgf_module_S_to_D[6]) );
CMPR32X2TS DP_OP_45J129_125_5354_U20 ( .A(DP_OP_45J129_125_5354_n49), .B(
S_A_S_Oper_A[7]), .C(DP_OP_45J129_125_5354_n20), .CO(
DP_OP_45J129_125_5354_n19), .S(Add_Subt_Sgf_module_S_to_D[7]) );
CMPR32X2TS DP_OP_45J129_125_5354_U19 ( .A(DP_OP_45J129_125_5354_n48), .B(
S_A_S_Oper_A[8]), .C(DP_OP_45J129_125_5354_n19), .CO(
DP_OP_45J129_125_5354_n18), .S(Add_Subt_Sgf_module_S_to_D[8]) );
CMPR32X2TS DP_OP_45J129_125_5354_U18 ( .A(DP_OP_45J129_125_5354_n47), .B(
S_A_S_Oper_A[9]), .C(DP_OP_45J129_125_5354_n18), .CO(
DP_OP_45J129_125_5354_n17), .S(Add_Subt_Sgf_module_S_to_D[9]) );
CMPR32X2TS DP_OP_45J129_125_5354_U17 ( .A(DP_OP_45J129_125_5354_n46), .B(
S_A_S_Oper_A[10]), .C(DP_OP_45J129_125_5354_n17), .CO(
DP_OP_45J129_125_5354_n16), .S(Add_Subt_Sgf_module_S_to_D[10]) );
CMPR32X2TS DP_OP_45J129_125_5354_U16 ( .A(DP_OP_45J129_125_5354_n45), .B(
S_A_S_Oper_A[11]), .C(DP_OP_45J129_125_5354_n16), .CO(
DP_OP_45J129_125_5354_n15), .S(Add_Subt_Sgf_module_S_to_D[11]) );
CMPR32X2TS DP_OP_45J129_125_5354_U15 ( .A(DP_OP_45J129_125_5354_n44), .B(
S_A_S_Oper_A[12]), .C(DP_OP_45J129_125_5354_n15), .CO(
DP_OP_45J129_125_5354_n14), .S(Add_Subt_Sgf_module_S_to_D[12]) );
CMPR32X2TS DP_OP_45J129_125_5354_U14 ( .A(DP_OP_45J129_125_5354_n43), .B(
S_A_S_Oper_A[13]), .C(DP_OP_45J129_125_5354_n14), .CO(
DP_OP_45J129_125_5354_n13), .S(Add_Subt_Sgf_module_S_to_D[13]) );
CMPR32X2TS DP_OP_45J129_125_5354_U13 ( .A(DP_OP_45J129_125_5354_n42), .B(
S_A_S_Oper_A[14]), .C(DP_OP_45J129_125_5354_n13), .CO(
DP_OP_45J129_125_5354_n12), .S(Add_Subt_Sgf_module_S_to_D[14]) );
CMPR32X2TS DP_OP_45J129_125_5354_U12 ( .A(DP_OP_45J129_125_5354_n41), .B(
S_A_S_Oper_A[15]), .C(DP_OP_45J129_125_5354_n12), .CO(
DP_OP_45J129_125_5354_n11), .S(Add_Subt_Sgf_module_S_to_D[15]) );
CMPR32X2TS DP_OP_45J129_125_5354_U11 ( .A(DP_OP_45J129_125_5354_n40), .B(
S_A_S_Oper_A[16]), .C(DP_OP_45J129_125_5354_n11), .CO(
DP_OP_45J129_125_5354_n10), .S(Add_Subt_Sgf_module_S_to_D[16]) );
CMPR32X2TS DP_OP_45J129_125_5354_U10 ( .A(DP_OP_45J129_125_5354_n39), .B(
S_A_S_Oper_A[17]), .C(DP_OP_45J129_125_5354_n10), .CO(
DP_OP_45J129_125_5354_n9), .S(Add_Subt_Sgf_module_S_to_D[17]) );
CMPR32X2TS DP_OP_45J129_125_5354_U9 ( .A(DP_OP_45J129_125_5354_n38), .B(
S_A_S_Oper_A[18]), .C(DP_OP_45J129_125_5354_n9), .CO(
DP_OP_45J129_125_5354_n8), .S(Add_Subt_Sgf_module_S_to_D[18]) );
CMPR32X2TS DP_OP_45J129_125_5354_U8 ( .A(DP_OP_45J129_125_5354_n37), .B(
S_A_S_Oper_A[19]), .C(DP_OP_45J129_125_5354_n8), .CO(
DP_OP_45J129_125_5354_n7), .S(Add_Subt_Sgf_module_S_to_D[19]) );
CMPR32X2TS DP_OP_45J129_125_5354_U7 ( .A(DP_OP_45J129_125_5354_n36), .B(
S_A_S_Oper_A[20]), .C(DP_OP_45J129_125_5354_n7), .CO(
DP_OP_45J129_125_5354_n6), .S(Add_Subt_Sgf_module_S_to_D[20]) );
CMPR32X2TS DP_OP_45J129_125_5354_U6 ( .A(DP_OP_45J129_125_5354_n35), .B(
S_A_S_Oper_A[21]), .C(DP_OP_45J129_125_5354_n6), .CO(
DP_OP_45J129_125_5354_n5), .S(Add_Subt_Sgf_module_S_to_D[21]) );
CMPR32X2TS DP_OP_45J129_125_5354_U5 ( .A(DP_OP_45J129_125_5354_n34), .B(
S_A_S_Oper_A[22]), .C(DP_OP_45J129_125_5354_n5), .CO(
DP_OP_45J129_125_5354_n4), .S(Add_Subt_Sgf_module_S_to_D[22]) );
CMPR32X2TS DP_OP_45J129_125_5354_U4 ( .A(DP_OP_45J129_125_5354_n33), .B(
S_A_S_Oper_A[23]), .C(DP_OP_45J129_125_5354_n4), .CO(
DP_OP_45J129_125_5354_n3), .S(Add_Subt_Sgf_module_S_to_D[23]) );
CMPR32X2TS DP_OP_45J129_125_5354_U3 ( .A(DP_OP_45J129_125_5354_n32), .B(
S_A_S_Oper_A[24]), .C(DP_OP_45J129_125_5354_n3), .CO(
DP_OP_45J129_125_5354_n2), .S(Add_Subt_Sgf_module_S_to_D[24]) );
CMPR32X2TS DP_OP_45J129_125_5354_U2 ( .A(DP_OP_45J129_125_5354_n31), .B(
S_A_S_Oper_A[25]), .C(DP_OP_45J129_125_5354_n2), .CO(
DP_OP_45J129_125_5354_n1), .S(Add_Subt_Sgf_module_S_to_D[25]) );
DFFRX1TS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n691), .CK(clk), .RN(
n1489), .Q(overflow_flag), .QN(n1471) );
DFFRX1TS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n559), .CK(clk),
.RN(n797), .Q(sign_final_result), .QN(n1470) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n1475),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[51]), .QN(n1467) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n796),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[50]), .QN(n1466) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n727), .CK(clk),
.RN(n1480), .Q(Sgf_normalized_result[24]), .QN(n1465) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n726), .CK(clk),
.RN(n1494), .Q(Sgf_normalized_result[23]), .QN(n1464) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n755), .CK(clk),
.RN(n796), .Q(Add_Subt_result[21]), .QN(n1463) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n725), .CK(clk),
.RN(n1486), .Q(Sgf_normalized_result[22]), .QN(n1459) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n724), .CK(clk),
.RN(n1487), .Q(Sgf_normalized_result[21]), .QN(n1458) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n723), .CK(clk),
.RN(n1493), .Q(Sgf_normalized_result[20]), .QN(n1456) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n739), .CK(clk),
.RN(n1493), .Q(Add_Subt_result[5]), .QN(n1455) );
DFFRX1TS XRegister_Q_reg_30_ ( .D(n655), .CK(clk), .RN(n1478), .Q(intDX[30]),
.QN(n1454) );
DFFRX1TS XRegister_Q_reg_8_ ( .D(n633), .CK(clk), .RN(n1489), .Q(intDX[8]),
.QN(n1451) );
DFFRX1TS XRegister_Q_reg_14_ ( .D(n639), .CK(clk), .RN(n1488), .Q(intDX[14]),
.QN(n1450) );
DFFRX1TS XRegister_Q_reg_22_ ( .D(n647), .CK(clk), .RN(n1478), .Q(intDX[22]),
.QN(n1448) );
DFFRX1TS XRegister_Q_reg_24_ ( .D(n649), .CK(clk), .RN(n1478), .Q(intDX[24]),
.QN(n1447) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(n625), .CK(clk), .RN(n1488), .Q(intDX[0]),
.QN(n1446) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(n634), .CK(clk), .RN(n1491), .Q(intDX[9]),
.QN(n1444) );
DFFRX1TS XRegister_Q_reg_11_ ( .D(n636), .CK(clk), .RN(n1487), .Q(intDX[11]),
.QN(n1443) );
DFFRX1TS XRegister_Q_reg_19_ ( .D(n644), .CK(clk), .RN(n1493), .Q(intDX[19]),
.QN(n1442) );
DFFRX1TS XRegister_Q_reg_25_ ( .D(n650), .CK(clk), .RN(n1478), .Q(intDX[25]),
.QN(n1441) );
DFFRX1TS XRegister_Q_reg_27_ ( .D(n652), .CK(clk), .RN(n1478), .Q(intDX[27]),
.QN(n1440) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n722), .CK(clk),
.RN(n1477), .Q(Sgf_normalized_result[19]), .QN(n1439) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n721), .CK(clk),
.RN(n1481), .Q(Sgf_normalized_result[18]), .QN(n1438) );
DFFRX1TS XRegister_Q_reg_18_ ( .D(n643), .CK(clk), .RN(n1477), .Q(intDX[18]),
.QN(n1436) );
DFFRX1TS XRegister_Q_reg_3_ ( .D(n628), .CK(clk), .RN(n797), .Q(intDX[3]),
.QN(n1435) );
DFFRX1TS XRegister_Q_reg_15_ ( .D(n640), .CK(clk), .RN(n1489), .Q(intDX[15]),
.QN(n1434) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n720), .CK(clk),
.RN(n1485), .Q(Sgf_normalized_result[17]), .QN(n1433) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n719), .CK(clk),
.RN(n1476), .Q(Sgf_normalized_result[16]), .QN(n1432) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n718), .CK(clk),
.RN(n1477), .Q(Sgf_normalized_result[15]), .QN(n1430) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n717), .CK(clk),
.RN(n1488), .Q(Sgf_normalized_result[14]), .QN(n1429) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n716), .CK(clk),
.RN(n1491), .Q(Sgf_normalized_result[13]), .QN(n1420) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n715), .CK(clk),
.RN(n797), .Q(Sgf_normalized_result[12]), .QN(n1419) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n714), .CK(clk),
.RN(n1486), .Q(Sgf_normalized_result[11]), .QN(n1412) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n713), .CK(clk),
.RN(n1487), .Q(Sgf_normalized_result[10]), .QN(n1409) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n711), .CK(clk),
.RN(n1476), .Q(Sgf_normalized_result[8]), .QN(n1407) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n710), .CK(clk),
.RN(n1493), .Q(Sgf_normalized_result[7]), .QN(n1406) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n752), .CK(clk),
.RN(n1488), .Q(Add_Subt_result[18]), .QN(n1405) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n709), .CK(clk),
.RN(n1485), .Q(Sgf_normalized_result[6]), .QN(n1403) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n708), .CK(clk),
.RN(n1481), .Q(Sgf_normalized_result[5]), .QN(n1402) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n707), .CK(clk),
.RN(n1490), .Q(Sgf_normalized_result[4]), .QN(n1401) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n706), .CK(clk),
.RN(n1490), .Q(Sgf_normalized_result[3]), .QN(n1400) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n705), .CK(clk),
.RN(n1490), .Q(Sgf_normalized_result[2]), .QN(n1399) );
DFFRX1TS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n690), .CK(clk), .RN(
n1491), .Q(underflow_flag), .QN(n1398) );
DFFRX1TS XRegister_Q_reg_12_ ( .D(n637), .CK(clk), .RN(n1491), .Q(intDX[12]),
.QN(n1396) );
DFFRX1TS XRegister_Q_reg_26_ ( .D(n651), .CK(clk), .RN(n1478), .Q(intDX[26]),
.QN(n1395) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n796), .Q(intDX[2]),
.QN(n1394) );
DFFRX1TS XRegister_Q_reg_29_ ( .D(n654), .CK(clk), .RN(n1478), .Q(intDX[29]),
.QN(n1393) );
DFFRX1TS XRegister_Q_reg_20_ ( .D(n645), .CK(clk), .RN(n1476), .Q(intDX[20]),
.QN(n1392) );
DFFRX1TS XRegister_Q_reg_13_ ( .D(n638), .CK(clk), .RN(n796), .Q(intDX[13]),
.QN(n1391) );
DFFRX1TS XRegister_Q_reg_21_ ( .D(n646), .CK(clk), .RN(n1481), .Q(intDX[21]),
.QN(n1390) );
DFFRX1TS XRegister_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1478), .Q(intDX[23]),
.QN(n1389) );
DFFRX1TS XRegister_Q_reg_17_ ( .D(n642), .CK(clk), .RN(n1485), .Q(intDX[17]),
.QN(n1388) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n704), .CK(clk),
.RN(n1490), .Q(Sgf_normalized_result[1]), .QN(n1379) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n701), .CK(clk), .RN(n656), .Q(
FSM_selector_B[0]), .QN(n1428) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n736), .CK(clk),
.RN(n1481), .Q(Add_Subt_result[2]), .QN(n1461) );
DFFRX2TS YRegister_Q_reg_30_ ( .D(n622), .CK(clk), .RN(n1488), .Q(intDY[30]),
.QN(n1426) );
DFFRX2TS YRegister_Q_reg_29_ ( .D(n621), .CK(clk), .RN(n1477), .Q(intDY[29]),
.QN(n1386) );
DFFRX2TS YRegister_Q_reg_26_ ( .D(n618), .CK(clk), .RN(n1493), .Q(intDY[26]),
.QN(n1422) );
DFFRX2TS YRegister_Q_reg_25_ ( .D(n617), .CK(clk), .RN(n1476), .Q(intDY[25]),
.QN(n1417) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n1486), .Q(intDY[23]),
.QN(n1385) );
DFFRX2TS YRegister_Q_reg_22_ ( .D(n614), .CK(clk), .RN(n1487), .Q(intDY[22]),
.QN(n1414) );
DFFRX2TS YRegister_Q_reg_21_ ( .D(n613), .CK(clk), .RN(n1481), .Q(intDY[21]),
.QN(n1424) );
DFFRX2TS YRegister_Q_reg_20_ ( .D(n612), .CK(clk), .RN(n1485), .Q(intDY[20]),
.QN(n1421) );
DFFRX2TS YRegister_Q_reg_19_ ( .D(n611), .CK(clk), .RN(n797), .Q(intDY[19]),
.QN(n1387) );
DFFRX2TS YRegister_Q_reg_18_ ( .D(n610), .CK(clk), .RN(n1482), .Q(intDY[18]),
.QN(n1431) );
DFFRX2TS YRegister_Q_reg_17_ ( .D(n609), .CK(clk), .RN(n1482), .Q(intDY[17]),
.QN(n1425) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(n607), .CK(clk), .RN(n1482), .Q(intDY[15]),
.QN(n1384) );
DFFRX2TS YRegister_Q_reg_14_ ( .D(n606), .CK(clk), .RN(n1482), .Q(intDY[14]),
.QN(n1410) );
DFFRX2TS YRegister_Q_reg_13_ ( .D(n605), .CK(clk), .RN(n1482), .Q(intDY[13]),
.QN(n1423) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(n604), .CK(clk), .RN(n1482), .Q(intDY[12]),
.QN(n1415) );
DFFRX2TS YRegister_Q_reg_11_ ( .D(n603), .CK(clk), .RN(n1482), .Q(intDY[11]),
.QN(n1418) );
DFFRX2TS YRegister_Q_reg_8_ ( .D(n600), .CK(clk), .RN(n1482), .Q(intDY[8]),
.QN(n1427) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(n595), .CK(clk), .RN(n1488), .Q(intDY[3]),
.QN(n1413) );
DFFRX2TS YRegister_Q_reg_1_ ( .D(n593), .CK(clk), .RN(n1477), .Q(intDY[1]),
.QN(n1416) );
DFFRX2TS XRegister_Q_reg_16_ ( .D(n641), .CK(clk), .RN(n1491), .Q(intDX[16]),
.QN(n1449) );
DFFRX2TS XRegister_Q_reg_10_ ( .D(n635), .CK(clk), .RN(n1488), .Q(intDX[10]),
.QN(n1437) );
DFFRX2TS XRegister_Q_reg_6_ ( .D(n631), .CK(clk), .RN(n1477), .Q(intDX[6]),
.QN(n1452) );
DFFRX2TS XRegister_Q_reg_4_ ( .D(n629), .CK(clk), .RN(n1493), .Q(intDX[4]),
.QN(n1453) );
DFFRX2TS XRegister_Q_reg_28_ ( .D(n653), .CK(clk), .RN(n1478), .Q(intDX[28]),
.QN(n1445) );
DFFRX2TS XRegister_Q_reg_1_ ( .D(n626), .CK(clk), .RN(n1476), .Q(intDX[1]),
.QN(n1469) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n741), .CK(clk),
.RN(n1481), .Q(Add_Subt_result[7]), .QN(n1468) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n760), .CK(clk), .RN(n1475), .Q(
FS_Module_state_reg[2]), .QN(n1404) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n761), .CK(clk), .RN(n1475), .Q(
FS_Module_state_reg[1]), .QN(n1377) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n745), .CK(clk),
.RN(n1487), .Q(Add_Subt_result[11]), .QN(n1457) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n763), .CK(clk), .RN(n1475), .Q(
FS_Module_state_reg[3]), .QN(n1382) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n750), .CK(clk),
.RN(n1485), .Q(Add_Subt_result[16]), .QN(n1397) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n751), .CK(clk),
.RN(n797), .Q(Add_Subt_result[17]), .QN(n1462) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n758), .CK(clk),
.RN(n1485), .Q(Add_Subt_result[24]), .QN(n1460) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n703), .CK(clk),
.RN(n1490), .Q(Sgf_normalized_result[0]), .QN(n1378) );
DFFRX4TS Sel_D_Q_reg_0_ ( .D(n702), .CK(clk), .RN(n656), .Q(n1376), .QN(
n1381) );
DFFRX2TS YRegister_Q_reg_5_ ( .D(n597), .CK(clk), .RN(n1486), .Q(intDY[5])
);
DFFRX2TS YRegister_Q_reg_7_ ( .D(n599), .CK(clk), .RN(n1482), .Q(intDY[7])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n733), .CK(clk),
.RN(n1490), .Q(Add_Subt_result[25]) );
DFFRX2TS YRegister_Q_reg_28_ ( .D(n620), .CK(clk), .RN(n796), .Q(intDY[28])
);
DFFRX2TS YRegister_Q_reg_10_ ( .D(n602), .CK(clk), .RN(n1482), .Q(intDY[10])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n737), .CK(clk),
.RN(n797), .Q(Add_Subt_result[3]) );
DFFRX2TS YRegister_Q_reg_16_ ( .D(n608), .CK(clk), .RN(n1482), .Q(intDY[16])
);
DFFRX2TS YRegister_Q_reg_24_ ( .D(n616), .CK(clk), .RN(n1489), .Q(intDY[24])
);
DFFRX2TS YRegister_Q_reg_2_ ( .D(n594), .CK(clk), .RN(n1487), .Q(intDY[2])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n744), .CK(clk),
.RN(n796), .Q(Add_Subt_result[10]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n753), .CK(clk),
.RN(n1493), .Q(Add_Subt_result[19]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n756), .CK(clk),
.RN(n796), .Q(Add_Subt_result[22]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n740), .CK(clk),
.RN(n1476), .Q(Add_Subt_result[6]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n735), .CK(clk),
.RN(n1489), .Q(Add_Subt_result[1]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n747), .CK(clk),
.RN(n1476), .Q(Add_Subt_result[13]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n743), .CK(clk),
.RN(n1489), .Q(Add_Subt_result[9]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n746), .CK(clk),
.RN(n1486), .Q(Add_Subt_result[12]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n738), .CK(clk),
.RN(n1491), .Q(Add_Subt_result[4]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n748), .CK(clk),
.RN(n1491), .Q(Add_Subt_result[14]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n695), .CK(clk), .RN(
n1487), .Q(exp_oper_result[4]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n1475),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[44]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n1489),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[49]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n1481),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[47]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n1491),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[48]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n1475),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[42]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n1475),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[43]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n698), .CK(clk), .RN(
n1489), .Q(exp_oper_result[1]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n1488),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[45]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n1485),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[46]) );
DFFRX1TS Sel_B_Q_reg_1_ ( .D(n700), .CK(clk), .RN(n656), .Q(
FSM_selector_B[1]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n699), .CK(clk), .RN(
n1477), .Q(exp_oper_result[0]) );
DFFRX1TS XRegister_Q_reg_31_ ( .D(n624), .CK(clk), .RN(n1477), .Q(intDX[31])
);
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n694), .CK(clk), .RN(
n797), .Q(exp_oper_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n765), .CK(clk),
.RN(n1493), .Q(Sgf_normalized_result[25]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n583), .CK(clk), .RN(
n1479), .Q(DMP[22]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n582), .CK(clk), .RN(
n1483), .Q(DMP[21]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n581), .CK(clk), .RN(
n1492), .Q(DMP[20]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n529), .CK(clk), .RN(
n1480), .Q(DmP[0]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n561), .CK(clk), .RN(
n1490), .Q(DMP[0]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n562), .CK(clk), .RN(
n1490), .Q(DMP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n564), .CK(clk), .RN(
n1479), .Q(DMP[3]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n565), .CK(clk), .RN(
n1480), .Q(DMP[4]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n567), .CK(clk), .RN(
n1476), .Q(DMP[6]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n569), .CK(clk), .RN(
n1493), .Q(DMP[8]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n749), .CK(clk),
.RN(n1479), .Q(Add_Subt_result[15]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n1484),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n1482),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n1475),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n1490),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n1478),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n1484),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX2TS YRegister_Q_reg_4_ ( .D(n596), .CK(clk), .RN(n1488), .Q(intDY[4])
);
DFFRX2TS YRegister_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1491), .Q(intDY[6])
);
DFFRX2TS XRegister_Q_reg_7_ ( .D(n632), .CK(clk), .RN(n796), .Q(intDX[7]),
.QN(n1474) );
DFFRX2TS YRegister_Q_reg_27_ ( .D(n619), .CK(clk), .RN(n1476), .Q(intDY[27])
);
DFFRX2TS YRegister_Q_reg_9_ ( .D(n601), .CK(clk), .RN(n1482), .Q(intDY[9])
);
DFFRX2TS XRegister_Q_reg_5_ ( .D(n630), .CK(clk), .RN(n1485), .Q(intDX[5]),
.QN(n1473) );
DFFRX2TS YRegister_Q_reg_0_ ( .D(n592), .CK(clk), .RN(n1477), .Q(intDY[0])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n757), .CK(clk),
.RN(n1485), .Q(Add_Subt_result[23]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n754), .CK(clk),
.RN(n796), .Q(Add_Subt_result[20]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n734), .CK(clk),
.RN(n1490), .Q(Add_Subt_result[0]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n742), .CK(clk),
.RN(n1494), .Q(Add_Subt_result[8]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n697), .CK(clk), .RN(
n1486), .Q(exp_oper_result[2]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n728), .CK(
clk), .RN(n1483), .Q(LZA_output[4]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n729), .CK(
clk), .RN(n1494), .Q(LZA_output[3]) );
DFFRX4TS FS_Module_state_reg_reg_0_ ( .D(n762), .CK(clk), .RN(n1475), .Q(
FS_Module_state_reg[0]), .QN(n1380) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n731), .CK(
clk), .RN(n1490), .Q(LZA_output[1]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n1483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n1494),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n1480),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n693), .CK(clk), .RN(
n1489), .Q(exp_oper_result[6]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n692), .CK(clk), .RN(
n1488), .Q(exp_oper_result[7]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n730), .CK(
clk), .RN(n1479), .Q(LZA_output[2]) );
DFFRX2TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n696), .CK(clk), .RN(
n1486), .Q(exp_oper_result[3]) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n764), .CK(
clk), .RN(n1490), .Q(add_overflow_flag), .QN(n1383) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n549), .CK(clk), .RN(
n797), .Q(DmP[20]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n530), .CK(clk), .RN(
n1483), .Q(DmP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n570), .CK(clk), .RN(
n1489), .Q(DMP[9]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n566), .CK(clk), .RN(
n1494), .Q(DMP[5]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n563), .CK(clk), .RN(
n1483), .Q(DMP[2]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n1492),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n1475),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n1475),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n1475),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n1483),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
ADDFX1TS DP_OP_42J129_122_8048_U9 ( .A(S_Oper_A_exp[0]), .B(
FSM_exp_operation_A_S), .CI(DP_OP_42J129_122_8048_n20), .CO(
DP_OP_42J129_122_8048_n8), .S(Exp_Operation_Module_Data_S[0]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n712), .CK(clk),
.RN(n1486), .Q(Sgf_normalized_result[9]), .QN(n1408) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n568), .CK(clk), .RN(
n1489), .Q(DMP[7]) );
DFFRX4TS Sel_C_Q_reg_0_ ( .D(n759), .CK(clk), .RN(n656), .Q(FSM_selector_C),
.QN(n1411) );
NAND2X4TS U868 ( .A(n1332), .B(n932), .Y(n941) );
AOI222X1TS U869 ( .A0(n1302), .A1(DmP[11]), .B0(Add_Subt_result[12]), .B1(
n1321), .C0(Add_Subt_result[13]), .C1(n1320), .Y(n1275) );
AOI222X1TS U870 ( .A0(n1411), .A1(DmP[8]), .B0(Add_Subt_result[10]), .B1(
n1261), .C0(Add_Subt_result[15]), .C1(n1292), .Y(n1284) );
AOI222X1TS U871 ( .A0(n1411), .A1(DmP[3]), .B0(Add_Subt_result[5]), .B1(
n1261), .C0(Add_Subt_result[20]), .C1(n1292), .Y(n1310) );
AOI222X1TS U872 ( .A0(n1411), .A1(DmP[7]), .B0(Add_Subt_result[9]), .B1(
n1261), .C0(Add_Subt_result[16]), .C1(n1292), .Y(n1288) );
XOR2XLTS U873 ( .A(DP_OP_45J129_125_5354_n1), .B(n1175), .Y(n820) );
INVX4TS U874 ( .A(n1021), .Y(n785) );
INVX3TS U875 ( .A(n1149), .Y(n1012) );
NAND2X4TS U876 ( .A(n801), .B(n1149), .Y(n996) );
CLKINVX3TS U877 ( .A(n1309), .Y(n775) );
OR2X4TS U878 ( .A(n822), .B(n1377), .Y(n1227) );
INVX4TS U879 ( .A(n1332), .Y(n931) );
BUFX4TS U880 ( .A(n802), .Y(n1369) );
NAND2BXLTS U881 ( .AN(intDY[9]), .B(intDX[9]), .Y(n855) );
NAND2BXLTS U882 ( .AN(intDX[27]), .B(intDY[27]), .Y(n828) );
NOR2XLTS U883 ( .A(n1383), .B(n1228), .Y(n809) );
OAI211XLTS U884 ( .A0(n831), .A1(n887), .B0(n830), .C0(n829), .Y(n836) );
NAND2BXLTS U885 ( .AN(intDY[27]), .B(intDX[27]), .Y(n829) );
NAND3BXLTS U886 ( .AN(n872), .B(n870), .C(n869), .Y(n890) );
OAI21XLTS U887 ( .A0(n1203), .A1(FSM_selector_C), .B0(n811), .Y(n812) );
AOI2BB1XLTS U888 ( .A0N(n1344), .A1N(FS_Module_state_reg[2]), .B0(n810), .Y(
n811) );
NAND2BXLTS U889 ( .AN(Add_Subt_result[14]), .B(n1196), .Y(n1205) );
AO22XLTS U890 ( .A0(n775), .A1(n1281), .B0(n1266), .B1(n1270), .Y(n781) );
AO22XLTS U891 ( .A0(n799), .A1(n1278), .B0(n1262), .B1(n1270), .Y(n783) );
AO22XLTS U892 ( .A0(n798), .A1(n1275), .B0(n1256), .B1(n1270), .Y(n779) );
NAND2BXLTS U893 ( .AN(Add_Subt_result[12]), .B(n1354), .Y(n1198) );
MX2X1TS U894 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n1204), .Y(
S_A_S_Oper_A[8]) );
NOR2XLTS U895 ( .A(n1407), .B(n1189), .Y(n1167) );
CLKAND2X2TS U896 ( .A(n1204), .B(Sgf_normalized_result[0]), .Y(
S_A_S_Oper_A[0]) );
AO22XLTS U897 ( .A0(n775), .A1(n1284), .B0(n1271), .B1(n1270), .Y(n784) );
AO22XLTS U898 ( .A0(n798), .A1(n1288), .B0(n1275), .B1(n1309), .Y(n780) );
AO22XLTS U899 ( .A0(n798), .A1(n1303), .B0(n1284), .B1(n1309), .Y(n778) );
AO22XLTS U900 ( .A0(n798), .A1(n1310), .B0(n1288), .B1(n1322), .Y(n782) );
MX2X1TS U901 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n1204), .Y(
S_A_S_Oper_A[4]) );
NOR2XLTS U902 ( .A(n1419), .B(n1376), .Y(n1163) );
MX2X1TS U903 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n1204), .Y(
S_A_S_Oper_A[9]) );
NOR2XLTS U904 ( .A(n1408), .B(n1376), .Y(n1166) );
NOR2XLTS U905 ( .A(n1420), .B(n1189), .Y(n1162) );
CLKAND2X2TS U906 ( .A(n1204), .B(Sgf_normalized_result[1]), .Y(
S_A_S_Oper_A[1]) );
MX2X1TS U907 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n1204), .Y(
S_A_S_Oper_A[6]) );
MX2X1TS U908 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(n1204), .Y(
S_A_S_Oper_A[10]) );
NOR2XLTS U909 ( .A(n1409), .B(n1189), .Y(n1165) );
MX2X1TS U910 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n1204), .Y(
S_A_S_Oper_A[3]) );
MX2X1TS U911 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n1376), .Y(
S_A_S_Oper_A[11]) );
NOR2XLTS U912 ( .A(n1412), .B(n1376), .Y(n1164) );
NAND2BXLTS U913 ( .AN(ack_FSM), .B(ready), .Y(n1343) );
MX2X1TS U914 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n1204), .Y(
S_A_S_Oper_A[7]) );
MX2X1TS U915 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n1204), .Y(
S_A_S_Oper_A[2]) );
MX2X1TS U916 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n1204), .Y(
S_A_S_Oper_A[5]) );
BUFX3TS U917 ( .A(n1322), .Y(n1309) );
AO22XLTS U918 ( .A0(n820), .A1(n1226), .B0(add_overflow_flag), .B1(n1227),
.Y(n764) );
OAI31X1TS U919 ( .A0(n1219), .A1(n1218), .A2(Add_Subt_result[19]), .B0(n1217), .Y(n1224) );
OAI211XLTS U920 ( .A0(n1353), .A1(n1198), .B0(n1197), .C0(n1206), .Y(n1199)
);
OAI21XLTS U921 ( .A0(n1210), .A1(n1209), .B0(n1208), .Y(n1211) );
AO22XLTS U922 ( .A0(Add_Subt_Sgf_module_S_to_D[8]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[8]), .Y(n742) );
AO22XLTS U923 ( .A0(Add_Subt_Sgf_module_S_to_D[0]), .A1(n1226), .B0(n1227),
.B1(Add_Subt_result[0]), .Y(n734) );
AO22XLTS U924 ( .A0(Add_Subt_Sgf_module_S_to_D[20]), .A1(n1228), .B0(n1333),
.B1(Add_Subt_result[20]), .Y(n754) );
AO22XLTS U925 ( .A0(Add_Subt_Sgf_module_S_to_D[23]), .A1(n1226), .B0(n1333),
.B1(Add_Subt_result[23]), .Y(n757) );
AO22XLTS U926 ( .A0(n1374), .A1(Data_Y[0]), .B0(n802), .B1(intDY[0]), .Y(
n592) );
AO22XLTS U927 ( .A0(n1374), .A1(Data_Y[9]), .B0(n1369), .B1(intDY[9]), .Y(
n601) );
AO22XLTS U928 ( .A0(n1375), .A1(Data_Y[27]), .B0(n1371), .B1(intDY[27]), .Y(
n619) );
AO22XLTS U929 ( .A0(n1374), .A1(Data_Y[6]), .B0(n802), .B1(intDY[6]), .Y(
n598) );
AO22XLTS U930 ( .A0(n1374), .A1(Data_Y[4]), .B0(n802), .B1(intDY[4]), .Y(
n596) );
AO22XLTS U931 ( .A0(Add_Subt_Sgf_module_S_to_D[15]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[15]), .Y(n749) );
AO22XLTS U932 ( .A0(n1375), .A1(Data_X[31]), .B0(n1371), .B1(intDX[31]), .Y(
n624) );
AOI32X1TS U933 ( .A0(n798), .A1(n1317), .A2(n1240), .B0(n1103), .B1(n1317),
.Y(n1050) );
AO22XLTS U934 ( .A0(Add_Subt_Sgf_module_S_to_D[14]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[14]), .Y(n748) );
AO22XLTS U935 ( .A0(Add_Subt_Sgf_module_S_to_D[4]), .A1(n1228), .B0(n1333),
.B1(Add_Subt_result[4]), .Y(n738) );
AO22XLTS U936 ( .A0(Add_Subt_Sgf_module_S_to_D[12]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[12]), .Y(n746) );
AO22XLTS U937 ( .A0(Add_Subt_Sgf_module_S_to_D[9]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[9]), .Y(n743) );
AO22XLTS U938 ( .A0(Add_Subt_Sgf_module_S_to_D[13]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[13]), .Y(n747) );
AO22XLTS U939 ( .A0(Add_Subt_Sgf_module_S_to_D[1]), .A1(n1226), .B0(n1333),
.B1(Add_Subt_result[1]), .Y(n735) );
AO22XLTS U940 ( .A0(Add_Subt_Sgf_module_S_to_D[6]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[6]), .Y(n740) );
AO22XLTS U941 ( .A0(Add_Subt_Sgf_module_S_to_D[22]), .A1(n1226), .B0(n1333),
.B1(Add_Subt_result[22]), .Y(n756) );
AO22XLTS U942 ( .A0(Add_Subt_Sgf_module_S_to_D[19]), .A1(n1228), .B0(n1333),
.B1(Add_Subt_result[19]), .Y(n753) );
AO22XLTS U943 ( .A0(Add_Subt_Sgf_module_S_to_D[10]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[10]), .Y(n744) );
AO22XLTS U944 ( .A0(n1374), .A1(Data_Y[2]), .B0(n802), .B1(intDY[2]), .Y(
n594) );
AO22XLTS U945 ( .A0(n1373), .A1(Data_Y[24]), .B0(n1371), .B1(intDY[24]), .Y(
n616) );
AO22XLTS U946 ( .A0(n1375), .A1(Data_Y[16]), .B0(n1371), .B1(intDY[16]), .Y(
n608) );
AO22XLTS U947 ( .A0(Add_Subt_Sgf_module_S_to_D[3]), .A1(n1226), .B0(n1333),
.B1(Add_Subt_result[3]), .Y(n737) );
AO22XLTS U948 ( .A0(n1374), .A1(Data_Y[10]), .B0(n1369), .B1(intDY[10]), .Y(
n602) );
AO22XLTS U949 ( .A0(n1375), .A1(Data_Y[28]), .B0(n1371), .B1(intDY[28]), .Y(
n620) );
AO22XLTS U950 ( .A0(Add_Subt_Sgf_module_S_to_D[25]), .A1(n1226), .B0(n1333),
.B1(Add_Subt_result[25]), .Y(n733) );
AO22XLTS U951 ( .A0(n1374), .A1(Data_Y[7]), .B0(n802), .B1(intDY[7]), .Y(
n599) );
AO22XLTS U952 ( .A0(n1374), .A1(Data_Y[5]), .B0(n802), .B1(intDY[5]), .Y(
n597) );
AO22XLTS U953 ( .A0(Add_Subt_Sgf_module_S_to_D[24]), .A1(n1226), .B0(n1333),
.B1(Add_Subt_result[24]), .Y(n758) );
AO22XLTS U954 ( .A0(Add_Subt_Sgf_module_S_to_D[17]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[17]), .Y(n751) );
AO22XLTS U955 ( .A0(Add_Subt_Sgf_module_S_to_D[16]), .A1(n1228), .B0(n1333),
.B1(Add_Subt_result[16]), .Y(n750) );
AO22XLTS U956 ( .A0(Add_Subt_Sgf_module_S_to_D[18]), .A1(n1226), .B0(n1227),
.B1(Add_Subt_result[18]), .Y(n752) );
AO22XLTS U957 ( .A0(Add_Subt_Sgf_module_S_to_D[21]), .A1(n1226), .B0(n1227),
.B1(Add_Subt_result[21]), .Y(n755) );
OAI2BB2XLTS U958 ( .B0(n1458), .B1(n1365), .A0N(final_result_ieee[19]),
.A1N(n1366), .Y(n662) );
OAI2BB2XLTS U959 ( .B0(n1456), .B1(n1365), .A0N(final_result_ieee[18]),
.A1N(n1366), .Y(n663) );
OAI2BB2XLTS U960 ( .B0(n1438), .B1(n1365), .A0N(final_result_ieee[16]),
.A1N(n1366), .Y(n665) );
OAI2BB2XLTS U961 ( .B0(n1432), .B1(n1365), .A0N(final_result_ieee[14]),
.A1N(n1366), .Y(n667) );
INVX2TS U962 ( .A(n785), .Y(n786) );
OR2X1TS U963 ( .A(n1008), .B(n1236), .Y(n776) );
OA22X1TS U964 ( .A0(n1203), .A1(n1302), .B0(n1380), .B1(n1334), .Y(n777) );
OAI221X1TS U965 ( .A0(n1442), .A1(intDY[19]), .B0(n1392), .B1(intDY[20]),
.C0(n902), .Y(n905) );
NOR3X1TS U966 ( .A(n1404), .B(n1380), .C(n1344), .Y(n803) );
NOR4X2TS U967 ( .A(Add_Subt_result[16]), .B(Add_Subt_result[15]), .C(
Add_Subt_result[17]), .D(n1209), .Y(n1196) );
OR2X2TS U968 ( .A(n1058), .B(n988), .Y(n1053) );
NOR2X2TS U969 ( .A(FS_Module_state_reg[0]), .B(n1334), .Y(n1109) );
AOI222X1TS U970 ( .A0(n1240), .A1(n1328), .B0(n1238), .B1(n1317), .C0(n1237),
.C1(n1308), .Y(n1106) );
AOI32X1TS U971 ( .A0(n1308), .A1(n775), .A2(n1239), .B0(n990), .B1(n799),
.Y(n991) );
CLKINVX3TS U972 ( .A(n1257), .Y(n1308) );
AOI222X4TS U973 ( .A0(n1302), .A1(DmP[16]), .B0(Add_Subt_result[7]), .B1(
n1321), .C0(Add_Subt_result[18]), .C1(n1261), .Y(n1252) );
BUFX4TS U974 ( .A(n1362), .Y(n1366) );
BUFX4TS U975 ( .A(n1309), .Y(n1270) );
BUFX4TS U976 ( .A(n948), .Y(n1024) );
CLKINVX6TS U977 ( .A(n941), .Y(n1040) );
BUFX4TS U978 ( .A(n819), .Y(n1175) );
NAND4X2TS U979 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .C(
n1382), .D(n1377), .Y(n1342) );
INVX2TS U980 ( .A(n777), .Y(n787) );
NOR3X2TS U981 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .C(
FS_Module_state_reg[1]), .Y(n1111) );
NAND2X4TS U982 ( .A(n1203), .B(n1202), .Y(n1341) );
NOR4X4TS U983 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .D(n1377), .Y(n1332) );
AOI22X4TS U984 ( .A0(LZA_output[3]), .A1(n1184), .B0(n1183), .B1(
exp_oper_result[3]), .Y(n1009) );
INVX2TS U985 ( .A(n776), .Y(n788) );
INVX2TS U986 ( .A(n779), .Y(n789) );
INVX2TS U987 ( .A(n780), .Y(n790) );
INVX2TS U988 ( .A(n782), .Y(n791) );
AOI22X2TS U989 ( .A0(n798), .A1(n1323), .B0(n1293), .B1(n1322), .Y(n1312) );
INVX2TS U990 ( .A(n783), .Y(n792) );
INVX2TS U991 ( .A(n781), .Y(n793) );
AOI22X2TS U992 ( .A0(n799), .A1(n1293), .B0(n1278), .B1(n1322), .Y(n1289) );
AOI22X2TS U993 ( .A0(n775), .A1(n1297), .B0(n1281), .B1(n1322), .Y(n1294) );
AOI222X4TS U994 ( .A0(n1411), .A1(DmP[5]), .B0(Add_Subt_result[7]), .B1(
n1320), .C0(Add_Subt_result[18]), .C1(n1292), .Y(n1297) );
INVX2TS U995 ( .A(n784), .Y(n794) );
INVX2TS U996 ( .A(n778), .Y(n795) );
INVX3TS U997 ( .A(n1369), .Y(n1374) );
AOI222X4TS U998 ( .A0(n1302), .A1(DmP[13]), .B0(Add_Subt_result[10]), .B1(
n1321), .C0(Add_Subt_result[15]), .C1(n1320), .Y(n1266) );
INVX3TS U999 ( .A(n801), .Y(n1321) );
INVX4TS U1000 ( .A(n1044), .Y(n1261) );
INVX4TS U1001 ( .A(n1053), .Y(n1272) );
CLKINVX3TS U1002 ( .A(n1102), .Y(n1313) );
INVX3TS U1003 ( .A(n1102), .Y(n1326) );
INVX3TS U1004 ( .A(n941), .Y(n1035) );
NOR2X1TS U1005 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[8]), .Y(n1136)
);
AOI222X4TS U1006 ( .A0(n1411), .A1(DmP[6]), .B0(Add_Subt_result[8]), .B1(
n1261), .C0(Add_Subt_result[17]), .C1(n1292), .Y(n1293) );
OAI22X2TS U1007 ( .A0(Add_Subt_result[0]), .A1(n801), .B0(
Add_Subt_result[25]), .B1(n1044), .Y(n1048) );
OAI32X1TS U1008 ( .A0(Add_Subt_result[25]), .A1(Add_Subt_result[23]), .A2(
n1347), .B0(n1460), .B1(Add_Subt_result[25]), .Y(n1348) );
NOR4X2TS U1009 ( .A(Add_Subt_result[24]), .B(Add_Subt_result[25]), .C(
Add_Subt_result[22]), .D(Add_Subt_result[23]), .Y(n1217) );
OAI221XLTS U1010 ( .A0(n1394), .A1(intDY[2]), .B0(n1446), .B1(intDY[0]),
.C0(n919), .Y(n920) );
AOI222X1TS U1011 ( .A0(intDY[4]), .A1(n1453), .B0(n844), .B1(n843), .C0(
intDY[5]), .C1(n1473), .Y(n846) );
OAI221XLTS U1012 ( .A0(n1473), .A1(intDY[5]), .B0(n1452), .B1(intDY[6]),
.C0(n917), .Y(n922) );
OAI221X1TS U1013 ( .A0(n1444), .A1(intDY[9]), .B0(n1437), .B1(intDY[10]),
.C0(n911), .Y(n912) );
OAI221X1TS U1014 ( .A0(n1440), .A1(intDY[27]), .B0(n1445), .B1(intDY[28]),
.C0(n894), .Y(n897) );
OAI221X1TS U1015 ( .A0(n1474), .A1(intDY[7]), .B0(n1451), .B1(intDY[8]),
.C0(n916), .Y(n923) );
OAI221X1TS U1016 ( .A0(n1435), .A1(intDY[3]), .B0(n1453), .B1(intDY[4]),
.C0(n918), .Y(n921) );
NOR3XLTS U1017 ( .A(Add_Subt_result[15]), .B(Add_Subt_result[16]), .C(
Add_Subt_result[17]), .Y(n1210) );
AOI222X4TS U1018 ( .A0(n1302), .A1(DmP[15]), .B0(Add_Subt_result[8]), .B1(
n1321), .C0(Add_Subt_result[17]), .C1(n1320), .Y(n1256) );
OAI211X2TS U1019 ( .A0(intDX[12]), .A1(n1415), .B0(n863), .C0(n849), .Y(n865) );
BUFX3TS U1020 ( .A(n815), .Y(n796) );
BUFX3TS U1021 ( .A(n815), .Y(n797) );
BUFX4TS U1022 ( .A(n1494), .Y(n1478) );
BUFX4TS U1023 ( .A(n1492), .Y(n1482) );
BUFX4TS U1024 ( .A(n1480), .Y(n1475) );
BUFX4TS U1025 ( .A(n1492), .Y(n1490) );
BUFX4TS U1026 ( .A(n1480), .Y(n1484) );
AOI211XLTS U1027 ( .A0(intDY[16]), .A1(n1449), .B0(n877), .C0(n878), .Y(n869) );
OAI211X2TS U1028 ( .A0(intDX[20]), .A1(n1421), .B0(n883), .C0(n868), .Y(n877) );
OAI21X4TS U1029 ( .A0(n787), .A1(n1338), .B0(add_overflow_flag), .Y(n1236)
);
AOI211X1TS U1030 ( .A0(FS_Module_state_reg[3]), .A1(n1339), .B0(n1338), .C0(
n1337), .Y(n1340) );
OAI21X2TS U1031 ( .A0(n1302), .A1(n1342), .B0(n825), .Y(n1338) );
CLKINVX3TS U1032 ( .A(n814), .Y(FSM_exp_operation_A_S) );
AOI211X1TS U1033 ( .A0(FS_Module_state_reg[1]), .A1(n1339), .B0(n804), .C0(
n813), .Y(n807) );
OAI21X2TS U1034 ( .A0(beg_FSM), .A1(n656), .B0(n1343), .Y(n1339) );
AOI32X2TS U1035 ( .A0(n890), .A1(n891), .A2(n889), .B0(n888), .B1(n891), .Y(
n932) );
NOR3X4TS U1036 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[0]), .C(
n1344), .Y(n1361) );
NAND2X2TS U1037 ( .A(FS_Module_state_reg[3]), .B(n1377), .Y(n1344) );
NOR2X4TS U1038 ( .A(n1114), .B(n996), .Y(n1131) );
OAI2BB2XLTS U1039 ( .B0(n1400), .B1(n1365), .A0N(final_result_ieee[1]),
.A1N(n1362), .Y(n680) );
OAI2BB2XLTS U1040 ( .B0(n1406), .B1(n1365), .A0N(final_result_ieee[5]),
.A1N(n1362), .Y(n676) );
BUFX4TS U1041 ( .A(n1364), .Y(n1365) );
OAI2BB1X1TS U1042 ( .A0N(n1428), .A1N(exp_oper_result[0]), .B0(n1186), .Y(
n989) );
AOI222X4TS U1043 ( .A0(n1302), .A1(DmP[18]), .B0(Add_Subt_result[5]), .B1(
n1292), .C0(Add_Subt_result[20]), .C1(n1320), .Y(n1244) );
INVX3TS U1044 ( .A(n801), .Y(n1292) );
INVX3TS U1045 ( .A(n1257), .Y(n1319) );
INVX2TS U1046 ( .A(n1309), .Y(n798) );
INVX2TS U1047 ( .A(n1309), .Y(n799) );
AOI32X2TS U1048 ( .A0(n1305), .A1(n775), .A2(n1304), .B0(n1303), .B1(n1309),
.Y(n1318) );
AOI22X2TS U1049 ( .A0(n799), .A1(n1271), .B0(n1252), .B1(n1270), .Y(n1267)
);
AOI22X2TS U1050 ( .A0(n775), .A1(n1266), .B0(n1248), .B1(n1270), .Y(n1263)
);
AOI22X2TS U1051 ( .A0(n799), .A1(n1262), .B0(n1244), .B1(n1270), .Y(n1258)
);
AOI32X2TS U1052 ( .A0(n1299), .A1(n798), .A2(n1298), .B0(n1297), .B1(n1322),
.Y(n1316) );
AOI22X2TS U1053 ( .A0(n799), .A1(n1248), .B0(n1056), .B1(n1270), .Y(n1245)
);
AOI22X2TS U1054 ( .A0(n799), .A1(n1049), .B0(n1048), .B1(n1270), .Y(n1104)
);
AOI22X2TS U1055 ( .A0(n775), .A1(n1256), .B0(n1049), .B1(n1270), .Y(n1253)
);
NOR2X2TS U1056 ( .A(n775), .B(n1236), .Y(n1103) );
AOI222X4TS U1057 ( .A0(n1302), .A1(DmP[12]), .B0(Add_Subt_result[11]), .B1(
n1321), .C0(Add_Subt_result[14]), .C1(n1320), .Y(n1271) );
AOI222X4TS U1058 ( .A0(n1411), .A1(DmP[9]), .B0(Add_Subt_result[11]), .B1(
n1261), .C0(Add_Subt_result[14]), .C1(n1292), .Y(n1281) );
AOI222X4TS U1059 ( .A0(n1302), .A1(DmP[19]), .B0(Add_Subt_result[4]), .B1(
n1292), .C0(Add_Subt_result[21]), .C1(n1261), .Y(n1049) );
AOI222X4TS U1060 ( .A0(n1302), .A1(DmP[2]), .B0(Add_Subt_result[4]), .B1(
n1261), .C0(Add_Subt_result[21]), .C1(n1292), .Y(n1323) );
AOI222X4TS U1061 ( .A0(n1302), .A1(DmP[10]), .B0(Add_Subt_result[12]), .B1(
n1261), .C0(Add_Subt_result[13]), .C1(n1292), .Y(n1278) );
AOI32X1TS U1062 ( .A0(Add_Subt_result[10]), .A1(n1354), .A2(n1457), .B0(
Add_Subt_result[12]), .B1(n1354), .Y(n1222) );
AOI222X4TS U1063 ( .A0(n1302), .A1(DmP[14]), .B0(Add_Subt_result[9]), .B1(
n1321), .C0(Add_Subt_result[16]), .C1(n1320), .Y(n1262) );
AOI222X4TS U1064 ( .A0(n1302), .A1(DmP[22]), .B0(Add_Subt_result[1]), .B1(
n1321), .C0(Add_Subt_result[24]), .C1(n1320), .Y(n1101) );
AOI222X4TS U1065 ( .A0(n1411), .A1(DmP[4]), .B0(Add_Subt_result[6]), .B1(
n1261), .C0(Add_Subt_result[19]), .C1(n1292), .Y(n1303) );
AOI222X4TS U1066 ( .A0(n1302), .A1(DmP[17]), .B0(Add_Subt_result[6]), .B1(
n1321), .C0(Add_Subt_result[19]), .C1(n1261), .Y(n1248) );
NOR2X2TS U1067 ( .A(Add_Subt_result[19]), .B(n1190), .Y(n1349) );
OAI221X1TS U1068 ( .A0(n1389), .A1(intDY[23]), .B0(n1447), .B1(intDY[24]),
.C0(n900), .Y(n907) );
OAI221X1TS U1069 ( .A0(n1434), .A1(intDY[15]), .B0(n1449), .B1(intDY[16]),
.C0(n908), .Y(n915) );
OAI2BB1X2TS U1070 ( .A0N(Add_Subt_result[3]), .A1N(n1292), .B0(n1045), .Y(
n1240) );
INVX2TS U1071 ( .A(n1381), .Y(n800) );
NOR2XLTS U1072 ( .A(n1376), .B(n1378), .Y(n1176) );
NOR2XLTS U1073 ( .A(n1376), .B(n1379), .Y(n1174) );
NOR2XLTS U1074 ( .A(n1401), .B(n1376), .Y(n1171) );
NOR2XLTS U1075 ( .A(n1402), .B(n1376), .Y(n1170) );
NOR2XLTS U1076 ( .A(n1403), .B(n1376), .Y(n1169) );
OR4X2TS U1077 ( .A(FS_Module_state_reg[1]), .B(add_overflow_flag), .C(n1411),
.D(n822), .Y(n801) );
OR4X4TS U1078 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .C(
FS_Module_state_reg[1]), .D(n1380), .Y(n802) );
OAI21XLTS U1079 ( .A0(intDX[1]), .A1(n1416), .B0(intDX[0]), .Y(n839) );
OAI21XLTS U1080 ( .A0(intDX[15]), .A1(n1384), .B0(intDX[14]), .Y(n859) );
NOR2XLTS U1081 ( .A(n872), .B(intDY[16]), .Y(n873) );
OAI21XLTS U1082 ( .A0(intDX[21]), .A1(n1424), .B0(intDX[20]), .Y(n871) );
NOR2XLTS U1083 ( .A(n1465), .B(n1189), .Y(n1151) );
NOR2XLTS U1084 ( .A(n1406), .B(n1189), .Y(n1168) );
NOR2XLTS U1085 ( .A(n1063), .B(n996), .Y(n997) );
NOR2XLTS U1086 ( .A(n1400), .B(n1189), .Y(n1172) );
NOR2XLTS U1087 ( .A(n1102), .B(n1270), .Y(n826) );
OAI211XLTS U1088 ( .A0(n1067), .A1(n996), .B0(n1018), .C0(n1017), .Y(n714)
);
OAI211XLTS U1089 ( .A0(n1147), .A1(n785), .B0(n999), .C0(n1076), .Y(n727) );
OAI21XLTS U1090 ( .A0(n1444), .A1(n948), .B0(n938), .Y(n538) );
OAI21XLTS U1091 ( .A0(n1389), .A1(n1024), .B0(n955), .Y(n552) );
OAI21XLTS U1092 ( .A0(n1442), .A1(n941), .B0(n964), .Y(n580) );
OAI21XLTS U1093 ( .A0(n1383), .A1(n1359), .B0(n821), .Y(n700) );
XOR2X1TS U1094 ( .A(intDY[31]), .B(intAS), .Y(n892) );
XNOR2X1TS U1095 ( .A(n892), .B(intDX[31]), .Y(n1107) );
NOR2X1TS U1096 ( .A(n1107), .B(n1376), .Y(n819) );
BUFX3TS U1097 ( .A(n819), .Y(n1472) );
NAND2X2TS U1098 ( .A(n1111), .B(n1404), .Y(n656) );
NOR4X1TS U1099 ( .A(FS_Module_state_reg[0]), .B(n1404), .C(n1382), .D(n1377),
.Y(ready) );
NAND2X1TS U1100 ( .A(FS_Module_state_reg[2]), .B(n1382), .Y(n822) );
BUFX3TS U1101 ( .A(n1227), .Y(n1333) );
NOR2XLTS U1102 ( .A(FSM_selector_C), .B(n1342), .Y(n804) );
NAND3X1TS U1103 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[1]),
.C(n1404), .Y(n1334) );
BUFX3TS U1104 ( .A(n803), .Y(n1368) );
OR4X2TS U1105 ( .A(n1109), .B(n1368), .C(n1332), .D(n1374), .Y(n813) );
INVX2TS U1106 ( .A(r_mode[0]), .Y(n806) );
OAI22X1TS U1107 ( .A0(sign_final_result), .A1(r_mode[1]), .B0(
Sgf_normalized_result[0]), .B1(Sgf_normalized_result[1]), .Y(n805) );
AOI221X1TS U1108 ( .A0(sign_final_result), .A1(n806), .B0(r_mode[1]), .B1(
r_mode[0]), .C0(n805), .Y(n1336) );
INVX2TS U1109 ( .A(n1344), .Y(n808) );
NAND3XLTS U1110 ( .A(FS_Module_state_reg[0]), .B(n808), .C(n1404), .Y(n1335)
);
INVX2TS U1111 ( .A(n1335), .Y(n1110) );
NAND2X1TS U1112 ( .A(n1336), .B(n1110), .Y(n1188) );
OAI211XLTS U1113 ( .A0(n1333), .A1(n1380), .B0(n807), .C0(n1188), .Y(n761)
);
NAND3X1TS U1114 ( .A(FS_Module_state_reg[2]), .B(n808), .C(n1380), .Y(n825)
);
NAND2X2TS U1115 ( .A(n825), .B(n1342), .Y(n1149) );
NAND2BX1TS U1116 ( .AN(n1404), .B(n1111), .Y(n1203) );
NAND2X1TS U1117 ( .A(FS_Module_state_reg[3]), .B(n1404), .Y(n1200) );
INVX4TS U1118 ( .A(n1227), .Y(n1228) );
OAI2BB1X1TS U1119 ( .A0N(n1200), .A1N(n822), .B0(n809), .Y(n810) );
NOR3X1TS U1120 ( .A(n1149), .B(n813), .C(n812), .Y(n814) );
INVX4TS U1121 ( .A(rst), .Y(n815) );
BUFX3TS U1122 ( .A(n815), .Y(n1494) );
BUFX3TS U1123 ( .A(n815), .Y(n1477) );
BUFX3TS U1124 ( .A(n815), .Y(n1485) );
BUFX3TS U1125 ( .A(n815), .Y(n1486) );
BUFX3TS U1126 ( .A(n815), .Y(n1488) );
BUFX3TS U1127 ( .A(n815), .Y(n1491) );
BUFX3TS U1128 ( .A(n815), .Y(n1483) );
BUFX3TS U1129 ( .A(n815), .Y(n1487) );
BUFX3TS U1130 ( .A(n815), .Y(n1481) );
BUFX3TS U1131 ( .A(n815), .Y(n1492) );
BUFX3TS U1132 ( .A(n815), .Y(n1479) );
BUFX3TS U1133 ( .A(n815), .Y(n1489) );
BUFX3TS U1134 ( .A(n815), .Y(n1476) );
BUFX3TS U1135 ( .A(n815), .Y(n1493) );
BUFX3TS U1136 ( .A(n815), .Y(n1480) );
NAND3BX1TS U1137 ( .AN(overflow_flag), .B(n1368), .C(n1398), .Y(n1364) );
BUFX3TS U1138 ( .A(n1364), .Y(n1363) );
INVX2TS U1139 ( .A(n1368), .Y(n1362) );
OAI2BB2XLTS U1140 ( .B0(n1420), .B1(n1363), .A0N(final_result_ieee[11]),
.A1N(n1362), .Y(n670) );
OAI2BB2XLTS U1141 ( .B0(n1419), .B1(n1363), .A0N(final_result_ieee[10]),
.A1N(n1362), .Y(n671) );
AO22XLTS U1142 ( .A0(Add_Subt_Sgf_module_S_to_D[5]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[5]), .Y(n739) );
AO22XLTS U1143 ( .A0(Add_Subt_Sgf_module_S_to_D[11]), .A1(n1228), .B0(n1227),
.B1(Add_Subt_result[11]), .Y(n745) );
BUFX4TS U1144 ( .A(n1411), .Y(n1302) );
NOR4BX1TS U1145 ( .AN(n787), .B(Exp_Operation_Module_Data_S[2]), .C(
Exp_Operation_Module_Data_S[1]), .D(Exp_Operation_Module_Data_S[0]),
.Y(n816) );
NOR4BX1TS U1146 ( .AN(n816), .B(Exp_Operation_Module_Data_S[5]), .C(
Exp_Operation_Module_Data_S[4]), .D(Exp_Operation_Module_Data_S[3]),
.Y(n817) );
XOR2X1TS U1147 ( .A(DP_OP_42J129_122_8048_n1), .B(FSM_exp_operation_A_S),
.Y(n1230) );
NOR4BX1TS U1148 ( .AN(n817), .B(n1230), .C(Exp_Operation_Module_Data_S[7]),
.D(Exp_Operation_Module_Data_S[6]), .Y(n818) );
AO21XLTS U1149 ( .A0(n777), .A1(underflow_flag), .B0(n818), .Y(n690) );
OAI21XLTS U1150 ( .A0(n1227), .A1(FS_Module_state_reg[0]), .B0(n1302), .Y(
n759) );
INVX2TS U1151 ( .A(n1361), .Y(n1359) );
AOI21X1TS U1152 ( .A0(FSM_selector_B[1]), .A1(n1359), .B0(n1109), .Y(n821)
);
OR2X1TS U1153 ( .A(n1321), .B(n1411), .Y(n1044) );
NOR2XLTS U1154 ( .A(n1428), .B(FSM_selector_B[1]), .Y(n823) );
CLKBUFX3TS U1155 ( .A(n823), .Y(n1184) );
NOR2XLTS U1156 ( .A(FSM_selector_B[0]), .B(FSM_selector_B[1]), .Y(n824) );
BUFX3TS U1157 ( .A(n824), .Y(n1183) );
AOI22X2TS U1158 ( .A0(LZA_output[1]), .A1(n1184), .B0(exp_oper_result[1]),
.B1(n1183), .Y(n1058) );
INVX2TS U1159 ( .A(n1058), .Y(n1233) );
AOI22X1TS U1160 ( .A0(n1184), .A1(LZA_output[0]), .B0(FSM_selector_B[1]),
.B1(n1428), .Y(n1186) );
OR2X2TS U1161 ( .A(n1233), .B(n989), .Y(n1102) );
AO22X2TS U1162 ( .A0(LZA_output[2]), .A1(n1184), .B0(n1183), .B1(
exp_oper_result[2]), .Y(n1322) );
OAI32X1TS U1163 ( .A0(n1048), .A1(n1102), .A2(n1309), .B0(n826), .B1(n1236),
.Y(Barrel_Shifter_module_Mux_Array_Data_array[25]) );
BUFX4TS U1164 ( .A(n931), .Y(n1033) );
BUFX4TS U1165 ( .A(n1033), .Y(n1037) );
NOR2X1TS U1166 ( .A(n1417), .B(intDX[25]), .Y(n886) );
NOR2XLTS U1167 ( .A(n886), .B(intDY[24]), .Y(n827) );
AOI22X1TS U1168 ( .A0(intDX[25]), .A1(n1417), .B0(intDX[24]), .B1(n827), .Y(
n831) );
OAI21X1TS U1169 ( .A0(intDX[26]), .A1(n1422), .B0(n828), .Y(n887) );
NAND3XLTS U1170 ( .A(n1422), .B(n828), .C(intDX[26]), .Y(n830) );
NOR2X1TS U1171 ( .A(n1426), .B(intDX[30]), .Y(n834) );
NOR2X1TS U1172 ( .A(n1386), .B(intDX[29]), .Y(n832) );
AOI211X1TS U1173 ( .A0(intDY[28]), .A1(n1445), .B0(n834), .C0(n832), .Y(n885) );
NOR3X1TS U1174 ( .A(n1445), .B(n832), .C(intDY[28]), .Y(n833) );
AOI221X1TS U1175 ( .A0(intDX[30]), .A1(n1426), .B0(intDX[29]), .B1(n1386),
.C0(n833), .Y(n835) );
AOI2BB2X1TS U1176 ( .B0(n836), .B1(n885), .A0N(n835), .A1N(n834), .Y(n891)
);
NOR2X1TS U1177 ( .A(n1425), .B(intDX[17]), .Y(n872) );
NAND2BXLTS U1178 ( .AN(intDX[9]), .B(intDY[9]), .Y(n853) );
NOR2X1TS U1179 ( .A(n1418), .B(intDX[11]), .Y(n851) );
AOI21X1TS U1180 ( .A0(intDY[10]), .A1(n1437), .B0(n851), .Y(n856) );
OAI211XLTS U1181 ( .A0(intDX[8]), .A1(n1427), .B0(n853), .C0(n856), .Y(n867)
);
OAI2BB1X1TS U1182 ( .A0N(n1473), .A1N(intDY[5]), .B0(intDX[4]), .Y(n837) );
OAI22X1TS U1183 ( .A0(intDY[4]), .A1(n837), .B0(n1473), .B1(intDY[5]), .Y(
n848) );
OAI2BB1X1TS U1184 ( .A0N(n1474), .A1N(intDY[7]), .B0(intDX[6]), .Y(n838) );
OAI22X1TS U1185 ( .A0(intDY[6]), .A1(n838), .B0(n1474), .B1(intDY[7]), .Y(
n847) );
OAI2BB2XLTS U1186 ( .B0(intDY[0]), .B1(n839), .A0N(intDX[1]), .A1N(n1416),
.Y(n841) );
NAND2BXLTS U1187 ( .AN(intDX[2]), .B(intDY[2]), .Y(n840) );
OAI211XLTS U1188 ( .A0(n1413), .A1(intDX[3]), .B0(n841), .C0(n840), .Y(n844)
);
OAI21XLTS U1189 ( .A0(intDX[3]), .A1(n1413), .B0(intDX[2]), .Y(n842) );
AOI2BB2XLTS U1190 ( .B0(intDX[3]), .B1(n1413), .A0N(intDY[2]), .A1N(n842),
.Y(n843) );
AOI22X1TS U1191 ( .A0(intDY[7]), .A1(n1474), .B0(intDY[6]), .B1(n1452), .Y(
n845) );
OAI32X1TS U1192 ( .A0(n848), .A1(n847), .A2(n846), .B0(n845), .B1(n847), .Y(
n866) );
OA22X1TS U1193 ( .A0(n1410), .A1(intDX[14]), .B0(n1384), .B1(intDX[15]), .Y(
n863) );
NAND2BXLTS U1194 ( .AN(intDX[13]), .B(intDY[13]), .Y(n849) );
OAI21XLTS U1195 ( .A0(intDX[13]), .A1(n1423), .B0(intDX[12]), .Y(n850) );
OAI2BB2XLTS U1196 ( .B0(intDY[12]), .B1(n850), .A0N(intDX[13]), .A1N(n1423),
.Y(n862) );
NOR2XLTS U1197 ( .A(n851), .B(intDY[10]), .Y(n852) );
AOI22X1TS U1198 ( .A0(intDX[11]), .A1(n1418), .B0(intDX[10]), .B1(n852), .Y(
n858) );
NAND3XLTS U1199 ( .A(n1427), .B(n853), .C(intDX[8]), .Y(n854) );
AOI21X1TS U1200 ( .A0(n855), .A1(n854), .B0(n865), .Y(n857) );
OAI2BB2XLTS U1201 ( .B0(n858), .B1(n865), .A0N(n857), .A1N(n856), .Y(n861)
);
OAI2BB2XLTS U1202 ( .B0(intDY[14]), .B1(n859), .A0N(intDX[15]), .A1N(n1384),
.Y(n860) );
AOI211X1TS U1203 ( .A0(n863), .A1(n862), .B0(n861), .C0(n860), .Y(n864) );
OAI31X1TS U1204 ( .A0(n867), .A1(n866), .A2(n865), .B0(n864), .Y(n870) );
OA22X1TS U1205 ( .A0(n1414), .A1(intDX[22]), .B0(n1385), .B1(intDX[23]), .Y(
n883) );
NAND2BXLTS U1206 ( .AN(intDX[21]), .B(intDY[21]), .Y(n868) );
NAND2BXLTS U1207 ( .AN(intDX[19]), .B(intDY[19]), .Y(n874) );
OAI21X1TS U1208 ( .A0(intDX[18]), .A1(n1431), .B0(n874), .Y(n878) );
OAI2BB2XLTS U1209 ( .B0(intDY[20]), .B1(n871), .A0N(intDX[21]), .A1N(n1424),
.Y(n882) );
AOI22X1TS U1210 ( .A0(intDX[17]), .A1(n1425), .B0(intDX[16]), .B1(n873), .Y(
n876) );
AOI32X1TS U1211 ( .A0(n1431), .A1(n874), .A2(intDX[18]), .B0(intDX[19]),
.B1(n1387), .Y(n875) );
OAI32X1TS U1212 ( .A0(n878), .A1(n877), .A2(n876), .B0(n875), .B1(n877), .Y(
n881) );
OAI21XLTS U1213 ( .A0(intDX[23]), .A1(n1385), .B0(intDX[22]), .Y(n879) );
OAI2BB2XLTS U1214 ( .B0(intDY[22]), .B1(n879), .A0N(intDX[23]), .A1N(n1385),
.Y(n880) );
AOI211X1TS U1215 ( .A0(n883), .A1(n882), .B0(n881), .C0(n880), .Y(n889) );
NAND2BXLTS U1216 ( .AN(intDX[24]), .B(intDY[24]), .Y(n884) );
NAND4BBX1TS U1217 ( .AN(n887), .BN(n886), .C(n885), .D(n884), .Y(n888) );
NOR2XLTS U1218 ( .A(n892), .B(n932), .Y(n930) );
AOI2BB2XLTS U1219 ( .B0(intDX[1]), .B1(intDY[1]), .A0N(intDY[1]), .A1N(
intDX[1]), .Y(n899) );
AOI22X1TS U1220 ( .A0(n1393), .A1(intDY[29]), .B0(n1454), .B1(intDY[30]),
.Y(n893) );
OAI221XLTS U1221 ( .A0(n1393), .A1(intDY[29]), .B0(n1454), .B1(intDY[30]),
.C0(n893), .Y(n898) );
AOI22X1TS U1222 ( .A0(n1440), .A1(intDY[27]), .B0(n1445), .B1(intDY[28]),
.Y(n894) );
AOI22X1TS U1223 ( .A0(n1441), .A1(intDY[25]), .B0(n1395), .B1(intDY[26]),
.Y(n895) );
OAI221XLTS U1224 ( .A0(n1441), .A1(intDY[25]), .B0(n1395), .B1(intDY[26]),
.C0(n895), .Y(n896) );
NOR4X1TS U1225 ( .A(n899), .B(n898), .C(n897), .D(n896), .Y(n927) );
AOI22X1TS U1226 ( .A0(n1389), .A1(intDY[23]), .B0(n1447), .B1(intDY[24]),
.Y(n900) );
AOI22X1TS U1227 ( .A0(n1390), .A1(intDY[21]), .B0(n1448), .B1(intDY[22]),
.Y(n901) );
OAI221XLTS U1228 ( .A0(n1390), .A1(intDY[21]), .B0(n1448), .B1(intDY[22]),
.C0(n901), .Y(n906) );
AOI22X1TS U1229 ( .A0(n1442), .A1(intDY[19]), .B0(n1392), .B1(intDY[20]),
.Y(n902) );
AOI22X1TS U1230 ( .A0(n1388), .A1(intDY[17]), .B0(n1436), .B1(intDY[18]),
.Y(n903) );
OAI221XLTS U1231 ( .A0(n1388), .A1(intDY[17]), .B0(n1436), .B1(intDY[18]),
.C0(n903), .Y(n904) );
NOR4X1TS U1232 ( .A(n907), .B(n906), .C(n905), .D(n904), .Y(n926) );
AOI22X1TS U1233 ( .A0(n1434), .A1(intDY[15]), .B0(n1449), .B1(intDY[16]),
.Y(n908) );
AOI22X1TS U1234 ( .A0(n1391), .A1(intDY[13]), .B0(n1450), .B1(intDY[14]),
.Y(n909) );
OAI221XLTS U1235 ( .A0(n1391), .A1(intDY[13]), .B0(n1450), .B1(intDY[14]),
.C0(n909), .Y(n914) );
AOI22X1TS U1236 ( .A0(n1443), .A1(intDY[11]), .B0(n1396), .B1(intDY[12]),
.Y(n910) );
OAI221XLTS U1237 ( .A0(n1443), .A1(intDY[11]), .B0(n1396), .B1(intDY[12]),
.C0(n910), .Y(n913) );
AOI22X1TS U1238 ( .A0(n1444), .A1(intDY[9]), .B0(n1437), .B1(intDY[10]), .Y(
n911) );
NOR4X1TS U1239 ( .A(n915), .B(n914), .C(n912), .D(n913), .Y(n925) );
AOI22X1TS U1240 ( .A0(n1474), .A1(intDY[7]), .B0(n1451), .B1(intDY[8]), .Y(
n916) );
AOI22X1TS U1241 ( .A0(n1473), .A1(intDY[5]), .B0(n1452), .B1(intDY[6]), .Y(
n917) );
AOI22X1TS U1242 ( .A0(n1435), .A1(intDY[3]), .B0(n1453), .B1(intDY[4]), .Y(
n918) );
AOI22X1TS U1243 ( .A0(n1394), .A1(intDY[2]), .B0(n1446), .B1(intDY[0]), .Y(
n919) );
NOR4X1TS U1244 ( .A(n923), .B(n922), .C(n921), .D(n920), .Y(n924) );
NAND4XLTS U1245 ( .A(n927), .B(n926), .C(n925), .D(n924), .Y(n1108) );
INVX2TS U1246 ( .A(n932), .Y(n928) );
AOI21X1TS U1247 ( .A0(n1108), .A1(n928), .B0(intDX[31]), .Y(n929) );
OAI32X1TS U1248 ( .A0(n1037), .A1(n930), .A2(n929), .B0(n1332), .B1(n1470),
.Y(n559) );
OR2X2TS U1249 ( .A(n932), .B(n931), .Y(n948) );
BUFX4TS U1250 ( .A(n1033), .Y(n1113) );
AOI22X1TS U1251 ( .A0(n1113), .A1(DmP[12]), .B0(intDY[12]), .B1(n1040), .Y(
n933) );
OAI21XLTS U1252 ( .A0(n1396), .A1(n1024), .B0(n933), .Y(n541) );
AOI22X1TS U1253 ( .A0(n1113), .A1(DmP[22]), .B0(intDY[22]), .B1(n1040), .Y(
n934) );
OAI21XLTS U1254 ( .A0(n1448), .A1(n1024), .B0(n934), .Y(n551) );
AOI22X1TS U1255 ( .A0(n1113), .A1(DmP[13]), .B0(intDY[13]), .B1(n1040), .Y(
n935) );
OAI21XLTS U1256 ( .A0(n1391), .A1(n1024), .B0(n935), .Y(n542) );
AOI22X1TS U1257 ( .A0(n1113), .A1(DmP[8]), .B0(intDY[8]), .B1(n1040), .Y(
n936) );
OAI21XLTS U1258 ( .A0(n1451), .A1(n948), .B0(n936), .Y(n537) );
AOI22X1TS U1259 ( .A0(n1033), .A1(DmP[10]), .B0(intDY[10]), .B1(n1040), .Y(
n937) );
OAI21XLTS U1260 ( .A0(n1437), .A1(n948), .B0(n937), .Y(n539) );
AOI22X1TS U1261 ( .A0(n1113), .A1(DmP[9]), .B0(intDY[9]), .B1(n1040), .Y(
n938) );
AOI22X1TS U1262 ( .A0(n1033), .A1(DmP[6]), .B0(intDY[6]), .B1(n1040), .Y(
n939) );
OAI21XLTS U1263 ( .A0(n1452), .A1(n948), .B0(n939), .Y(n535) );
AOI22X1TS U1264 ( .A0(n1113), .A1(DmP[7]), .B0(intDY[7]), .B1(n1040), .Y(
n940) );
OAI21XLTS U1265 ( .A0(n1474), .A1(n1024), .B0(n940), .Y(n536) );
BUFX4TS U1266 ( .A(n941), .Y(n983) );
INVX4TS U1267 ( .A(n948), .Y(n968) );
AOI22X1TS U1268 ( .A0(n968), .A1(intDY[27]), .B0(DMP[27]), .B1(n931), .Y(
n942) );
OAI21XLTS U1269 ( .A0(n1440), .A1(n983), .B0(n942), .Y(n588) );
AOI22X1TS U1270 ( .A0(n968), .A1(intDY[23]), .B0(DMP[23]), .B1(n931), .Y(
n943) );
OAI21XLTS U1271 ( .A0(n1389), .A1(n983), .B0(n943), .Y(n584) );
AOI22X1TS U1272 ( .A0(n968), .A1(intDY[26]), .B0(DMP[26]), .B1(n931), .Y(
n944) );
OAI21XLTS U1273 ( .A0(n1395), .A1(n983), .B0(n944), .Y(n587) );
AOI22X1TS U1274 ( .A0(n968), .A1(intDY[22]), .B0(DMP[22]), .B1(n931), .Y(
n945) );
OAI21XLTS U1275 ( .A0(n1448), .A1(n983), .B0(n945), .Y(n583) );
AOI22X1TS U1276 ( .A0(n968), .A1(intDY[29]), .B0(DMP[29]), .B1(n931), .Y(
n946) );
OAI21XLTS U1277 ( .A0(n1393), .A1(n983), .B0(n946), .Y(n590) );
AOI22X1TS U1278 ( .A0(n968), .A1(intDY[21]), .B0(DMP[21]), .B1(n931), .Y(
n947) );
OAI21XLTS U1279 ( .A0(n1390), .A1(n983), .B0(n947), .Y(n582) );
INVX4TS U1280 ( .A(n948), .Y(n981) );
AOI22X1TS U1281 ( .A0(n981), .A1(intDY[8]), .B0(DMP[8]), .B1(n1033), .Y(n949) );
OAI21XLTS U1282 ( .A0(n1451), .A1(n983), .B0(n949), .Y(n569) );
AOI22X1TS U1283 ( .A0(n968), .A1(intDY[2]), .B0(DMP[2]), .B1(n1037), .Y(n950) );
OAI21XLTS U1284 ( .A0(n1394), .A1(n983), .B0(n950), .Y(n563) );
AOI22X1TS U1285 ( .A0(n968), .A1(intDY[1]), .B0(DMP[1]), .B1(n1037), .Y(n951) );
OAI21XLTS U1286 ( .A0(n1469), .A1(n983), .B0(n951), .Y(n562) );
AOI22X1TS U1287 ( .A0(n968), .A1(intDY[25]), .B0(DMP[25]), .B1(n931), .Y(
n952) );
OAI21XLTS U1288 ( .A0(n1441), .A1(n983), .B0(n952), .Y(n586) );
AOI22X1TS U1289 ( .A0(n968), .A1(intDY[3]), .B0(DMP[3]), .B1(n1037), .Y(n953) );
OAI21XLTS U1290 ( .A0(n1435), .A1(n983), .B0(n953), .Y(n564) );
AOI22X1TS U1291 ( .A0(n968), .A1(intDY[20]), .B0(DMP[20]), .B1(n931), .Y(
n954) );
OAI21XLTS U1292 ( .A0(n1392), .A1(n983), .B0(n954), .Y(n581) );
AOI22X1TS U1293 ( .A0(n1035), .A1(intDY[23]), .B0(DmP[23]), .B1(n1113), .Y(
n955) );
AOI22X1TS U1294 ( .A0(n1035), .A1(intDY[29]), .B0(DmP[29]), .B1(n1037), .Y(
n956) );
OAI21XLTS U1295 ( .A0(n1393), .A1(n1024), .B0(n956), .Y(n558) );
AOI22X1TS U1296 ( .A0(n1035), .A1(intDY[25]), .B0(DmP[25]), .B1(n1037), .Y(
n957) );
OAI21XLTS U1297 ( .A0(n1441), .A1(n1024), .B0(n957), .Y(n554) );
AOI22X1TS U1298 ( .A0(n1035), .A1(intDY[26]), .B0(DmP[26]), .B1(n1037), .Y(
n958) );
OAI21XLTS U1299 ( .A0(n1395), .A1(n1024), .B0(n958), .Y(n555) );
AOI22X1TS U1300 ( .A0(n981), .A1(intDY[15]), .B0(DMP[15]), .B1(n1037), .Y(
n959) );
OAI21XLTS U1301 ( .A0(n1434), .A1(n941), .B0(n959), .Y(n576) );
AOI22X1TS U1302 ( .A0(n981), .A1(intDY[13]), .B0(DMP[13]), .B1(n1033), .Y(
n960) );
OAI21XLTS U1303 ( .A0(n1391), .A1(n941), .B0(n960), .Y(n574) );
AOI22X1TS U1304 ( .A0(n981), .A1(intDY[12]), .B0(DMP[12]), .B1(n1033), .Y(
n961) );
OAI21XLTS U1305 ( .A0(n1396), .A1(n941), .B0(n961), .Y(n573) );
AOI22X1TS U1306 ( .A0(n968), .A1(intDY[18]), .B0(DMP[18]), .B1(n931), .Y(
n962) );
OAI21XLTS U1307 ( .A0(n1436), .A1(n941), .B0(n962), .Y(n579) );
AOI22X1TS U1308 ( .A0(n968), .A1(intDY[24]), .B0(DMP[24]), .B1(n931), .Y(
n963) );
OAI21XLTS U1309 ( .A0(n1447), .A1(n941), .B0(n963), .Y(n585) );
AOI22X1TS U1310 ( .A0(n968), .A1(intDY[19]), .B0(DMP[19]), .B1(n931), .Y(
n964) );
AOI22X1TS U1311 ( .A0(n968), .A1(intDY[28]), .B0(DMP[28]), .B1(n931), .Y(
n965) );
OAI21XLTS U1312 ( .A0(n1445), .A1(n941), .B0(n965), .Y(n589) );
AOI22X1TS U1313 ( .A0(n981), .A1(intDY[11]), .B0(DMP[11]), .B1(n1033), .Y(
n966) );
OAI21XLTS U1314 ( .A0(n1443), .A1(n941), .B0(n966), .Y(n572) );
AOI22X1TS U1315 ( .A0(n981), .A1(intDY[14]), .B0(DMP[14]), .B1(n1033), .Y(
n967) );
OAI21XLTS U1316 ( .A0(n1450), .A1(n941), .B0(n967), .Y(n575) );
AOI22X1TS U1317 ( .A0(n968), .A1(intDY[17]), .B0(DMP[17]), .B1(n1033), .Y(
n969) );
OAI21XLTS U1318 ( .A0(n1388), .A1(n941), .B0(n969), .Y(n578) );
AOI22X1TS U1319 ( .A0(n981), .A1(intDY[30]), .B0(DMP[30]), .B1(n1037), .Y(
n970) );
OAI21XLTS U1320 ( .A0(n1454), .A1(n941), .B0(n970), .Y(n560) );
AOI22X1TS U1321 ( .A0(n981), .A1(intDY[0]), .B0(DMP[0]), .B1(n1037), .Y(n971) );
OAI21XLTS U1322 ( .A0(n1446), .A1(n983), .B0(n971), .Y(n561) );
AOI22X1TS U1323 ( .A0(n1035), .A1(intDY[27]), .B0(DmP[27]), .B1(n1037), .Y(
n972) );
OAI21XLTS U1324 ( .A0(n1440), .A1(n1024), .B0(n972), .Y(n556) );
AOI22X1TS U1325 ( .A0(n1035), .A1(intDY[24]), .B0(DmP[24]), .B1(n1037), .Y(
n973) );
OAI21XLTS U1326 ( .A0(n1447), .A1(n1024), .B0(n973), .Y(n553) );
AOI22X1TS U1327 ( .A0(n981), .A1(intDY[9]), .B0(DMP[9]), .B1(n1033), .Y(n974) );
OAI21XLTS U1328 ( .A0(n1444), .A1(n983), .B0(n974), .Y(n570) );
AOI22X1TS U1329 ( .A0(n981), .A1(intDY[10]), .B0(DMP[10]), .B1(n1033), .Y(
n975) );
OAI21XLTS U1330 ( .A0(n1437), .A1(n941), .B0(n975), .Y(n571) );
AOI22X1TS U1331 ( .A0(n981), .A1(intDY[4]), .B0(DMP[4]), .B1(n1037), .Y(n976) );
OAI21XLTS U1332 ( .A0(n1453), .A1(n983), .B0(n976), .Y(n565) );
AOI22X1TS U1333 ( .A0(n981), .A1(intDY[16]), .B0(DMP[16]), .B1(n1033), .Y(
n977) );
OAI21XLTS U1334 ( .A0(n1449), .A1(n941), .B0(n977), .Y(n577) );
AOI22X1TS U1335 ( .A0(n981), .A1(intDY[6]), .B0(DMP[6]), .B1(n1033), .Y(n979) );
OAI21XLTS U1336 ( .A0(n1452), .A1(n983), .B0(n979), .Y(n567) );
AOI22X1TS U1337 ( .A0(n981), .A1(intDY[5]), .B0(DMP[5]), .B1(n1033), .Y(n980) );
OAI21XLTS U1338 ( .A0(n1473), .A1(n983), .B0(n980), .Y(n566) );
AOI22X1TS U1339 ( .A0(n981), .A1(intDY[7]), .B0(DMP[7]), .B1(n1033), .Y(n982) );
OAI21XLTS U1340 ( .A0(n1474), .A1(n983), .B0(n982), .Y(n568) );
AOI22X1TS U1341 ( .A0(n1113), .A1(DmP[21]), .B0(intDY[21]), .B1(n1035), .Y(
n984) );
OAI21XLTS U1342 ( .A0(n1390), .A1(n1024), .B0(n984), .Y(n550) );
AOI22X1TS U1343 ( .A0(n1113), .A1(DmP[19]), .B0(intDY[19]), .B1(n1035), .Y(
n985) );
OAI21XLTS U1344 ( .A0(n1442), .A1(n1024), .B0(n985), .Y(n548) );
AOI22X1TS U1345 ( .A0(n1113), .A1(DmP[18]), .B0(intDY[18]), .B1(n1035), .Y(
n986) );
OAI21XLTS U1346 ( .A0(n1436), .A1(n1024), .B0(n986), .Y(n547) );
AOI22X1TS U1347 ( .A0(DmP[20]), .A1(n1113), .B0(intDY[20]), .B1(n1035), .Y(
n987) );
OAI21XLTS U1348 ( .A0(n1392), .A1(n1024), .B0(n987), .Y(n549) );
INVX2TS U1349 ( .A(n989), .Y(n988) );
INVX2TS U1350 ( .A(n1103), .Y(n1242) );
OR2X1TS U1351 ( .A(n1058), .B(n989), .Y(n1257) );
INVX2TS U1352 ( .A(n1048), .Y(n1239) );
NAND2X1TS U1353 ( .A(n1058), .B(n989), .Y(n1052) );
AOI222X4TS U1354 ( .A0(n1302), .A1(DmP[21]), .B0(Add_Subt_result[2]), .B1(
n1292), .C0(Add_Subt_result[23]), .C1(n1261), .Y(n1056) );
OAI22X1TS U1355 ( .A0(n1101), .A1(n1052), .B0(n1056), .B1(n1102), .Y(n990)
);
OAI211XLTS U1356 ( .A0(n1236), .A1(n1053), .B0(n1242), .C0(n991), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X2TS U1357 ( .A0(LZA_output[4]), .A1(n1184), .B0(n1183), .B1(
exp_oper_result[4]), .Y(n1008) );
INVX2TS U1358 ( .A(n1008), .Y(n993) );
NOR2XLTS U1359 ( .A(n1009), .B(n993), .Y(n992) );
BUFX4TS U1360 ( .A(n992), .Y(n1087) );
NAND2X1TS U1361 ( .A(n1009), .B(n1008), .Y(n1063) );
INVX2TS U1362 ( .A(n1063), .Y(n1019) );
NAND2X1TS U1363 ( .A(n1009), .B(n993), .Y(n1004) );
INVX2TS U1364 ( .A(n1004), .Y(n1088) );
AOI22X1TS U1365 ( .A0(n1019), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .B0(n1088), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n994) );
OAI31X1TS U1366 ( .A0(n1009), .A1(n1008), .A2(n1467), .B0(n994), .Y(n995) );
AOI21X1TS U1367 ( .A0(n1087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n995), .Y(n1147)
);
NOR2X2TS U1368 ( .A(n1012), .B(n801), .Y(n1021) );
BUFX4TS U1369 ( .A(n997), .Y(n1132) );
AOI22X1TS U1370 ( .A0(n1012), .A1(Sgf_normalized_result[24]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B1(n1132), .Y(n999)
);
INVX2TS U1371 ( .A(n1236), .Y(n998) );
NAND3X1TS U1372 ( .A(n998), .B(n1149), .C(n1063), .Y(n1076) );
AOI21X1TS U1373 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1(
n1087), .B0(n788), .Y(n1095) );
AOI22X1TS U1374 ( .A0(n1012), .A1(Sgf_normalized_result[16]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(n1132), .Y(n1002)
);
AOI22X1TS U1375 ( .A0(n1019), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n1000) );
NAND2BX1TS U1376 ( .AN(n1009), .B(n788), .Y(n1114) );
OAI211X1TS U1377 ( .A0(n1004), .A1(n1467), .B0(n1000), .C0(n1114), .Y(n1092)
);
NAND2X1TS U1378 ( .A(n1021), .B(n1092), .Y(n1001) );
OAI211XLTS U1379 ( .A0(n1095), .A1(n996), .B0(n1002), .C0(n1001), .Y(n719)
);
AOI21X1TS U1380 ( .A0(n1087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(n788), .Y(n1100)
);
AOI22X1TS U1381 ( .A0(n1012), .A1(Sgf_normalized_result[17]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .B1(n1132), .Y(n1006)
);
AOI22X1TS U1382 ( .A0(n1019), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n1003) );
OAI211X1TS U1383 ( .A0(n1466), .A1(n1004), .B0(n1003), .C0(n1114), .Y(n1096)
);
NAND2X1TS U1384 ( .A(n1021), .B(n1096), .Y(n1005) );
OAI211XLTS U1385 ( .A0(n1100), .A1(n996), .B0(n1006), .C0(n1005), .Y(n720)
);
AOI22X1TS U1386 ( .A0(n1019), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .B0(n1088), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n1007) );
OAI31X1TS U1387 ( .A0(n1009), .A1(n1008), .A2(n1466), .B0(n1007), .Y(n1010)
);
AOI21X1TS U1388 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[34]), .A1(
n1087), .B0(n1010), .Y(n1146) );
AOI22X1TS U1389 ( .A0(n1012), .A1(Sgf_normalized_result[25]), .B0(n1132),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[51]), .Y(n1011) );
OAI211XLTS U1390 ( .A0(n1146), .A1(n785), .B0(n1011), .C0(n1076), .Y(n765)
);
AOI21X1TS U1391 ( .A0(n1087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n788), .Y(n1075)
);
BUFX3TS U1392 ( .A(n1012), .Y(n1130) );
AOI22X1TS U1393 ( .A0(n1019), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(n1013) );
NAND2X1TS U1394 ( .A(n1013), .B(n776), .Y(n1072) );
AOI22X1TS U1395 ( .A0(n1130), .A1(Sgf_normalized_result[10]), .B0(n786),
.B1(n1072), .Y(n1015) );
NAND2X1TS U1396 ( .A(n1132), .B(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n1014) );
OAI211XLTS U1397 ( .A0(n1075), .A1(n996), .B0(n1015), .C0(n1014), .Y(n713)
);
AOI21X1TS U1398 ( .A0(n1087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n788), .Y(n1067)
);
AOI22X1TS U1399 ( .A0(n1019), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(n1016) );
NAND2X1TS U1400 ( .A(n1016), .B(n776), .Y(n1062) );
AOI22X1TS U1401 ( .A0(n1130), .A1(Sgf_normalized_result[11]), .B0(n786),
.B1(n1062), .Y(n1018) );
NAND2X1TS U1402 ( .A(n1132), .B(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n1017) );
AOI21X1TS U1403 ( .A0(n1087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n788), .Y(n1071)
);
AOI22X1TS U1404 ( .A0(n1019), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n1020) );
NAND2X1TS U1405 ( .A(n1020), .B(n776), .Y(n1068) );
AOI22X1TS U1406 ( .A0(n1130), .A1(Sgf_normalized_result[12]), .B0(n1021),
.B1(n1068), .Y(n1023) );
NAND2X1TS U1407 ( .A(n1132), .B(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1022) );
OAI211XLTS U1408 ( .A0(n1071), .A1(n996), .B0(n1023), .C0(n1022), .Y(n715)
);
BUFX3TS U1409 ( .A(n1024), .Y(n1042) );
AOI22X1TS U1410 ( .A0(n1113), .A1(DmP[17]), .B0(intDY[17]), .B1(n1040), .Y(
n1025) );
OAI21XLTS U1411 ( .A0(n1388), .A1(n1042), .B0(n1025), .Y(n546) );
AOI22X1TS U1412 ( .A0(n1113), .A1(DmP[15]), .B0(intDY[15]), .B1(n1040), .Y(
n1026) );
OAI21XLTS U1413 ( .A0(n1434), .A1(n1042), .B0(n1026), .Y(n544) );
AOI22X1TS U1414 ( .A0(n1033), .A1(DmP[4]), .B0(intDY[4]), .B1(n1040), .Y(
n1027) );
OAI21XLTS U1415 ( .A0(n1453), .A1(n1042), .B0(n1027), .Y(n533) );
AOI22X1TS U1416 ( .A0(n1113), .A1(DmP[14]), .B0(intDY[14]), .B1(n1040), .Y(
n1028) );
OAI21XLTS U1417 ( .A0(n1450), .A1(n1042), .B0(n1028), .Y(n543) );
AOI22X1TS U1418 ( .A0(n1035), .A1(intDY[28]), .B0(DmP[28]), .B1(n1037), .Y(
n1029) );
OAI21XLTS U1419 ( .A0(n1445), .A1(n1042), .B0(n1029), .Y(n557) );
AOI22X1TS U1420 ( .A0(n1113), .A1(DmP[16]), .B0(intDY[16]), .B1(n1040), .Y(
n1030) );
OAI21XLTS U1421 ( .A0(n1449), .A1(n1042), .B0(n1030), .Y(n545) );
AOI22X1TS U1422 ( .A0(DmP[1]), .A1(n1037), .B0(intDY[1]), .B1(n1040), .Y(
n1031) );
OAI21XLTS U1423 ( .A0(n1469), .A1(n1042), .B0(n1031), .Y(n530) );
AOI22X1TS U1424 ( .A0(n1037), .A1(DmP[5]), .B0(intDY[5]), .B1(n1040), .Y(
n1032) );
OAI21XLTS U1425 ( .A0(n1473), .A1(n1042), .B0(n1032), .Y(n534) );
AOI22X1TS U1426 ( .A0(n1035), .A1(intDY[30]), .B0(DmP[30]), .B1(n1033), .Y(
n1034) );
OAI21XLTS U1427 ( .A0(n1454), .A1(n1042), .B0(n1034), .Y(n528) );
AOI22X1TS U1428 ( .A0(n1037), .A1(DmP[3]), .B0(intDY[3]), .B1(n1035), .Y(
n1036) );
OAI21XLTS U1429 ( .A0(n1435), .A1(n1042), .B0(n1036), .Y(n532) );
AOI22X1TS U1430 ( .A0(DmP[0]), .A1(n1037), .B0(intDY[0]), .B1(n1040), .Y(
n1038) );
OAI21XLTS U1431 ( .A0(n1446), .A1(n1042), .B0(n1038), .Y(n529) );
AOI22X1TS U1432 ( .A0(n1113), .A1(DmP[2]), .B0(intDY[2]), .B1(n1040), .Y(
n1039) );
OAI21XLTS U1433 ( .A0(n1394), .A1(n1042), .B0(n1039), .Y(n531) );
AOI22X1TS U1434 ( .A0(n1113), .A1(DmP[11]), .B0(intDY[11]), .B1(n1040), .Y(
n1041) );
OAI21XLTS U1435 ( .A0(n1443), .A1(n1042), .B0(n1041), .Y(n540) );
AO22X1TS U1436 ( .A0(n1309), .A1(n1101), .B0(n775), .B1(n1244), .Y(n1057) );
INVX2TS U1437 ( .A(n1052), .Y(n1043) );
BUFX4TS U1438 ( .A(n1043), .Y(n1328) );
INVX2TS U1439 ( .A(n1044), .Y(n1320) );
AOI22X1TS U1440 ( .A0(Add_Subt_result[22]), .A1(n1320), .B0(DmP[20]), .B1(
n1302), .Y(n1045) );
AOI2BB2X2TS U1441 ( .B0(n798), .B1(n1252), .A0N(n1240), .A1N(n775), .Y(n1249) );
AOI22X1TS U1442 ( .A0(n1328), .A1(n1249), .B0(n1313), .B1(n1253), .Y(n1047)
);
NAND2X1TS U1443 ( .A(n1245), .B(n1308), .Y(n1046) );
OAI211XLTS U1444 ( .A0(n1053), .A1(n1057), .B0(n1047), .C0(n1046), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
AOI22X1TS U1445 ( .A0(n1313), .A1(n1245), .B0(n1308), .B1(n1104), .Y(n1051)
);
INVX2TS U1446 ( .A(n1053), .Y(n1317) );
OAI211XLTS U1447 ( .A0(n1057), .A1(n1052), .B0(n1051), .C0(n1050), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
AOI22X1TS U1448 ( .A0(n1328), .A1(n1245), .B0(n1313), .B1(n1249), .Y(n1055)
);
NAND2X1TS U1449 ( .A(n1104), .B(n1317), .Y(n1054) );
OAI211XLTS U1450 ( .A0(n1257), .A1(n1057), .B0(n1055), .C0(n1054), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
INVX2TS U1451 ( .A(n1056), .Y(n1237) );
AOI22X1TS U1452 ( .A0(n1308), .A1(n1240), .B0(n1317), .B1(n1237), .Y(n1061)
);
OAI22X1TS U1453 ( .A0(n1058), .A1(n1242), .B0(n1102), .B1(n1057), .Y(n1059)
);
AOI21X1TS U1454 ( .A0(n1328), .A1(n1104), .B0(n1059), .Y(n1060) );
OAI21XLTS U1455 ( .A0(n1061), .A1(n1270), .B0(n1060), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
INVX2TS U1456 ( .A(n996), .Y(n1097) );
AOI22X1TS U1457 ( .A0(n1130), .A1(Sgf_normalized_result[14]), .B0(n1097),
.B1(n1062), .Y(n1066) );
NOR2XLTS U1458 ( .A(n785), .B(n1063), .Y(n1064) );
BUFX4TS U1459 ( .A(n1064), .Y(n1145) );
NAND2X1TS U1460 ( .A(n1145), .B(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n1065) );
OAI211XLTS U1461 ( .A0(n1067), .A1(n785), .B0(n1066), .C0(n1065), .Y(n717)
);
AOI22X1TS U1462 ( .A0(n1130), .A1(Sgf_normalized_result[13]), .B0(n1097),
.B1(n1068), .Y(n1070) );
NAND2X1TS U1463 ( .A(n1145), .B(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1069) );
OAI211XLTS U1464 ( .A0(n1071), .A1(n785), .B0(n1070), .C0(n1069), .Y(n716)
);
AOI22X1TS U1465 ( .A0(n1012), .A1(Sgf_normalized_result[15]), .B0(n1097),
.B1(n1072), .Y(n1074) );
NAND2X1TS U1466 ( .A(n1145), .B(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n1073) );
OAI211XLTS U1467 ( .A0(n1075), .A1(n785), .B0(n1074), .C0(n1073), .Y(n718)
);
AOI22X1TS U1468 ( .A0(n1088), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n1117) );
AOI22X1TS U1469 ( .A0(n1012), .A1(Sgf_normalized_result[18]), .B0(n1145),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[33]), .Y(n1078) );
INVX2TS U1470 ( .A(n1076), .Y(n1089) );
AOI21X1TS U1471 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1132), .B0(n1089), .Y(n1077) );
OAI211XLTS U1472 ( .A0(n1117), .A1(n785), .B0(n1078), .C0(n1077), .Y(n721)
);
AOI22X1TS U1473 ( .A0(n1088), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n1129) );
AOI22X1TS U1474 ( .A0(n1012), .A1(Sgf_normalized_result[19]), .B0(n1132),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n1080) );
AOI21X1TS U1475 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[32]), .A1(
n1145), .B0(n1089), .Y(n1079) );
OAI211XLTS U1476 ( .A0(n1129), .A1(n785), .B0(n1080), .C0(n1079), .Y(n722)
);
AOI22X1TS U1477 ( .A0(n1088), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n1135) );
AOI22X1TS U1478 ( .A0(n1012), .A1(Sgf_normalized_result[20]), .B0(n1132),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n1082) );
AOI21X1TS U1479 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[31]), .A1(
n1145), .B0(n1089), .Y(n1081) );
OAI211XLTS U1480 ( .A0(n1135), .A1(n785), .B0(n1082), .C0(n1081), .Y(n723)
);
AOI22X1TS U1481 ( .A0(n1088), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n1126) );
AOI22X1TS U1482 ( .A0(n1012), .A1(Sgf_normalized_result[22]), .B0(n1132),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(n1084) );
AOI21X1TS U1483 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[29]), .A1(
n1145), .B0(n1089), .Y(n1083) );
OAI211XLTS U1484 ( .A0(n1126), .A1(n785), .B0(n1084), .C0(n1083), .Y(n725)
);
AOI22X1TS U1485 ( .A0(n1088), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n1123) );
AOI22X1TS U1486 ( .A0(n1012), .A1(Sgf_normalized_result[23]), .B0(n1132),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(n1086) );
AOI21X1TS U1487 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[28]), .A1(
n1145), .B0(n1089), .Y(n1085) );
OAI211XLTS U1488 ( .A0(n1123), .A1(n785), .B0(n1086), .C0(n1085), .Y(n726)
);
AOI22X1TS U1489 ( .A0(n1088), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n1087), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1120) );
AOI22X1TS U1490 ( .A0(n1012), .A1(Sgf_normalized_result[21]), .B0(n1132),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n1091) );
AOI21X1TS U1491 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[30]), .A1(
n1145), .B0(n1089), .Y(n1090) );
OAI211XLTS U1492 ( .A0(n1120), .A1(n785), .B0(n1091), .C0(n1090), .Y(n724)
);
AOI22X1TS U1493 ( .A0(n1130), .A1(Sgf_normalized_result[9]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(n1145), .Y(n1094)
);
NAND2X1TS U1494 ( .A(n1097), .B(n1092), .Y(n1093) );
OAI211XLTS U1495 ( .A0(n1095), .A1(n785), .B0(n1094), .C0(n1093), .Y(n712)
);
AOI22X1TS U1496 ( .A0(n1130), .A1(Sgf_normalized_result[8]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .B1(n1145), .Y(n1099)
);
NAND2X1TS U1497 ( .A(n1097), .B(n1096), .Y(n1098) );
OAI211XLTS U1498 ( .A0(n1100), .A1(n785), .B0(n1099), .C0(n1098), .Y(n711)
);
INVX2TS U1499 ( .A(n1101), .Y(n1238) );
AOI22X1TS U1500 ( .A0(n1313), .A1(n1104), .B0(n1103), .B1(n1102), .Y(n1105)
);
OAI21XLTS U1501 ( .A0(n1106), .A1(n1270), .B0(n1105), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
NOR2X1TS U1502 ( .A(n1108), .B(n1107), .Y(n1331) );
NOR4X1TS U1503 ( .A(n1111), .B(n1110), .C(n1109), .D(n1338), .Y(n1112) );
OAI32X1TS U1504 ( .A0(n1339), .A1(n1331), .A2(n1113), .B0(n1112), .B1(n1339),
.Y(n762) );
AOI22X1TS U1505 ( .A0(n1130), .A1(Sgf_normalized_result[7]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B1(n1145), .Y(n1116)
);
AOI21X1TS U1506 ( .A0(n1132), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .B0(n1131), .Y(n1115)
);
OAI211XLTS U1507 ( .A0(n1117), .A1(n996), .B0(n1116), .C0(n1115), .Y(n710)
);
AOI22X1TS U1508 ( .A0(n1130), .A1(Sgf_normalized_result[4]), .B0(n1145),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n1119) );
AOI21X1TS U1509 ( .A0(n1132), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .B0(n1131), .Y(n1118)
);
OAI211XLTS U1510 ( .A0(n1120), .A1(n996), .B0(n1119), .C0(n1118), .Y(n707)
);
AOI22X1TS U1511 ( .A0(n1130), .A1(Sgf_normalized_result[2]), .B0(n1145),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(n1122) );
AOI21X1TS U1512 ( .A0(n1132), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(n1131), .Y(n1121)
);
OAI211XLTS U1513 ( .A0(n1123), .A1(n996), .B0(n1122), .C0(n1121), .Y(n705)
);
AOI22X1TS U1514 ( .A0(n1130), .A1(Sgf_normalized_result[3]), .B0(n1145),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(n1125) );
AOI21X1TS U1515 ( .A0(n1132), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(n1131), .Y(n1124)
);
OAI211XLTS U1516 ( .A0(n1126), .A1(n996), .B0(n1125), .C0(n1124), .Y(n706)
);
AOI22X1TS U1517 ( .A0(n1130), .A1(Sgf_normalized_result[6]), .B0(n1145),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n1128) );
AOI21X1TS U1518 ( .A0(n1132), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .B0(n1131), .Y(n1127)
);
OAI211XLTS U1519 ( .A0(n1129), .A1(n996), .B0(n1128), .C0(n1127), .Y(n709)
);
AOI22X1TS U1520 ( .A0(n1130), .A1(Sgf_normalized_result[5]), .B0(n1145),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n1134) );
AOI21X1TS U1521 ( .A0(n1132), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .B0(n1131), .Y(n1133)
);
OAI211XLTS U1522 ( .A0(n1135), .A1(n996), .B0(n1134), .C0(n1133), .Y(n708)
);
NOR2X1TS U1523 ( .A(Add_Subt_result[20]), .B(Add_Subt_result[21]), .Y(n1216)
);
NAND2X1TS U1524 ( .A(n1216), .B(n1217), .Y(n1190) );
NAND2X1TS U1525 ( .A(n1349), .B(n1405), .Y(n1209) );
NOR2X2TS U1526 ( .A(Add_Subt_result[13]), .B(n1205), .Y(n1354) );
NOR3X1TS U1527 ( .A(Add_Subt_result[11]), .B(Add_Subt_result[10]), .C(n1198),
.Y(n1141) );
NAND2X1TS U1528 ( .A(n1136), .B(n1455), .Y(n1140) );
NAND2X1TS U1529 ( .A(n1136), .B(n1141), .Y(n1350) );
NOR3X1TS U1530 ( .A(Add_Subt_result[7]), .B(Add_Subt_result[6]), .C(n1350),
.Y(n1221) );
NAND2X1TS U1531 ( .A(n1221), .B(n1455), .Y(n1137) );
NOR2BX1TS U1532 ( .AN(Add_Subt_result[4]), .B(n1137), .Y(n1215) );
NOR2XLTS U1533 ( .A(Add_Subt_result[7]), .B(Add_Subt_result[6]), .Y(n1139)
);
NOR2XLTS U1534 ( .A(Add_Subt_result[3]), .B(Add_Subt_result[2]), .Y(n1138)
);
NOR2X1TS U1535 ( .A(n1137), .B(Add_Subt_result[4]), .Y(n1220) );
INVX2TS U1536 ( .A(n1220), .Y(n1212) );
OAI22X1TS U1537 ( .A0(n1139), .A1(n1350), .B0(n1138), .B1(n1212), .Y(n1192)
);
AOI211XLTS U1538 ( .A0(n1141), .A1(n1140), .B0(n1215), .C0(n1192), .Y(n1144)
);
NOR3X1TS U1539 ( .A(Add_Subt_result[3]), .B(Add_Subt_result[2]), .C(n1212),
.Y(n1207) );
OAI21XLTS U1540 ( .A0(Add_Subt_result[1]), .A1(Add_Subt_result[0]), .B0(
n1207), .Y(n1143) );
NOR2XLTS U1541 ( .A(LZA_output[4]), .B(n1361), .Y(n1142) );
AOI31XLTS U1542 ( .A0(n1144), .A1(n1361), .A2(n1143), .B0(n1142), .Y(n728)
);
INVX2TS U1543 ( .A(n1145), .Y(n1148) );
OAI222X1TS U1544 ( .A0(n1378), .A1(n1149), .B0(n1148), .B1(n1467), .C0(n1146), .C1(n996), .Y(n703) );
OAI222X1TS U1545 ( .A0(n1379), .A1(n1149), .B0(n1148), .B1(n1466), .C0(n1147), .C1(n996), .Y(n704) );
INVX4TS U1546 ( .A(n1381), .Y(n1189) );
NOR2BX1TS U1547 ( .AN(Sgf_normalized_result[25]), .B(n1189), .Y(n1150) );
XOR2X1TS U1548 ( .A(n1175), .B(n1150), .Y(DP_OP_45J129_125_5354_n31) );
XOR2X1TS U1549 ( .A(n1175), .B(n1151), .Y(DP_OP_45J129_125_5354_n32) );
NOR2XLTS U1550 ( .A(n1464), .B(n1189), .Y(n1152) );
XOR2X1TS U1551 ( .A(n1175), .B(n1152), .Y(DP_OP_45J129_125_5354_n33) );
NOR2XLTS U1552 ( .A(n1459), .B(n1189), .Y(n1153) );
XOR2X1TS U1553 ( .A(n1175), .B(n1153), .Y(DP_OP_45J129_125_5354_n34) );
NOR2XLTS U1554 ( .A(n1458), .B(n1189), .Y(n1154) );
XOR2X1TS U1555 ( .A(n1175), .B(n1154), .Y(DP_OP_45J129_125_5354_n35) );
NOR2XLTS U1556 ( .A(n1456), .B(n1189), .Y(n1155) );
XOR2X1TS U1557 ( .A(n1175), .B(n1155), .Y(DP_OP_45J129_125_5354_n36) );
NOR2XLTS U1558 ( .A(n1439), .B(n1189), .Y(n1156) );
XOR2X1TS U1559 ( .A(n1175), .B(n1156), .Y(DP_OP_45J129_125_5354_n37) );
NOR2XLTS U1560 ( .A(n1438), .B(n1189), .Y(n1157) );
XOR2X1TS U1561 ( .A(n1175), .B(n1157), .Y(DP_OP_45J129_125_5354_n38) );
NOR2XLTS U1562 ( .A(n1433), .B(n1189), .Y(n1158) );
XOR2X1TS U1563 ( .A(n1175), .B(n1158), .Y(DP_OP_45J129_125_5354_n39) );
NOR2XLTS U1564 ( .A(n1432), .B(n1189), .Y(n1159) );
XOR2X1TS U1565 ( .A(n1175), .B(n1159), .Y(DP_OP_45J129_125_5354_n40) );
NOR2XLTS U1566 ( .A(n1430), .B(n1189), .Y(n1160) );
XOR2X1TS U1567 ( .A(n1175), .B(n1160), .Y(DP_OP_45J129_125_5354_n41) );
NOR2XLTS U1568 ( .A(n1429), .B(n1189), .Y(n1161) );
XOR2X1TS U1569 ( .A(n1175), .B(n1161), .Y(DP_OP_45J129_125_5354_n42) );
XOR2X1TS U1570 ( .A(n1175), .B(n1162), .Y(DP_OP_45J129_125_5354_n43) );
XOR2X1TS U1571 ( .A(n1175), .B(n1163), .Y(DP_OP_45J129_125_5354_n44) );
XOR2X1TS U1572 ( .A(n1175), .B(n1164), .Y(DP_OP_45J129_125_5354_n45) );
XOR2X1TS U1573 ( .A(n1472), .B(n1165), .Y(DP_OP_45J129_125_5354_n46) );
XOR2X1TS U1574 ( .A(n1472), .B(n1166), .Y(DP_OP_45J129_125_5354_n47) );
XOR2X1TS U1575 ( .A(n1472), .B(n1167), .Y(DP_OP_45J129_125_5354_n48) );
XOR2X1TS U1576 ( .A(n1472), .B(n1168), .Y(DP_OP_45J129_125_5354_n49) );
XOR2X1TS U1577 ( .A(n1472), .B(n1169), .Y(DP_OP_45J129_125_5354_n50) );
XOR2X1TS U1578 ( .A(n1472), .B(n1170), .Y(DP_OP_45J129_125_5354_n51) );
XOR2X1TS U1579 ( .A(n1472), .B(n1171), .Y(DP_OP_45J129_125_5354_n52) );
XOR2X1TS U1580 ( .A(n1472), .B(n1172), .Y(DP_OP_45J129_125_5354_n53) );
NAND2X1TS U1581 ( .A(n1399), .B(n1381), .Y(n1173) );
XOR2X1TS U1582 ( .A(n1472), .B(n1173), .Y(DP_OP_45J129_125_5354_n54) );
XOR2X1TS U1583 ( .A(n1472), .B(n1174), .Y(DP_OP_45J129_125_5354_n55) );
XOR2X1TS U1584 ( .A(n1472), .B(n1176), .Y(DP_OP_45J129_125_5354_n56) );
CLKAND2X2TS U1585 ( .A(n1183), .B(DmP[30]), .Y(n1177) );
XOR2X1TS U1586 ( .A(FSM_exp_operation_A_S), .B(n1177), .Y(
DP_OP_42J129_122_8048_n13) );
CLKAND2X2TS U1587 ( .A(n1183), .B(DmP[29]), .Y(n1178) );
XOR2X1TS U1588 ( .A(FSM_exp_operation_A_S), .B(n1178), .Y(
DP_OP_42J129_122_8048_n14) );
CLKAND2X2TS U1589 ( .A(n1183), .B(DmP[28]), .Y(n1179) );
XOR2X1TS U1590 ( .A(FSM_exp_operation_A_S), .B(n1179), .Y(
DP_OP_42J129_122_8048_n15) );
AO22XLTS U1591 ( .A0(LZA_output[4]), .A1(n1184), .B0(n1183), .B1(DmP[27]),
.Y(n1180) );
XOR2X1TS U1592 ( .A(FSM_exp_operation_A_S), .B(n1180), .Y(
DP_OP_42J129_122_8048_n16) );
AO22XLTS U1593 ( .A0(LZA_output[3]), .A1(n1184), .B0(n1183), .B1(DmP[26]),
.Y(n1181) );
XOR2X1TS U1594 ( .A(FSM_exp_operation_A_S), .B(n1181), .Y(
DP_OP_42J129_122_8048_n17) );
AO22XLTS U1595 ( .A0(LZA_output[2]), .A1(n1184), .B0(n1183), .B1(DmP[25]),
.Y(n1182) );
XOR2X1TS U1596 ( .A(FSM_exp_operation_A_S), .B(n1182), .Y(
DP_OP_42J129_122_8048_n18) );
AO22XLTS U1597 ( .A0(LZA_output[1]), .A1(n1184), .B0(n1183), .B1(DmP[24]),
.Y(n1185) );
XOR2X1TS U1598 ( .A(FSM_exp_operation_A_S), .B(n1185), .Y(
DP_OP_42J129_122_8048_n19) );
OAI2BB1X1TS U1599 ( .A0N(DmP[23]), .A1N(n1428), .B0(n1186), .Y(n1187) );
XOR2X1TS U1600 ( .A(FSM_exp_operation_A_S), .B(n1187), .Y(
DP_OP_42J129_122_8048_n20) );
NAND2X1TS U1601 ( .A(n1381), .B(n1188), .Y(n702) );
NAND2BXLTS U1602 ( .AN(Sgf_normalized_result[25]), .B(n1189), .Y(
S_A_S_Oper_A[25]) );
CLKINVX6TS U1603 ( .A(n1381), .Y(n1204) );
MX2X1TS U1604 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n1204), .Y(
S_A_S_Oper_A[24]) );
MX2X1TS U1605 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(n800), .Y(
S_A_S_Oper_A[23]) );
MX2X1TS U1606 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n800), .Y(
S_A_S_Oper_A[22]) );
MX2X1TS U1607 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n800), .Y(
S_A_S_Oper_A[21]) );
MX2X1TS U1608 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n800), .Y(
S_A_S_Oper_A[20]) );
MX2X1TS U1609 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n1376), .Y(
S_A_S_Oper_A[19]) );
MX2X1TS U1610 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n1376), .Y(
S_A_S_Oper_A[18]) );
MX2X1TS U1611 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n1376), .Y(
S_A_S_Oper_A[17]) );
MX2X1TS U1612 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n1376), .Y(
S_A_S_Oper_A[16]) );
MX2X1TS U1613 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n1376), .Y(
S_A_S_Oper_A[15]) );
MX2X1TS U1614 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n1376), .Y(
S_A_S_Oper_A[14]) );
MX2X1TS U1615 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n1376), .Y(
S_A_S_Oper_A[13]) );
MX2X1TS U1616 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n1376), .Y(
S_A_S_Oper_A[12]) );
INVX2TS U1617 ( .A(n1227), .Y(n1226) );
NOR2X1TS U1618 ( .A(Add_Subt_result[11]), .B(Add_Subt_result[10]), .Y(n1353)
);
NOR2XLTS U1619 ( .A(Add_Subt_result[24]), .B(Add_Subt_result[25]), .Y(n1195)
);
OR2X1TS U1620 ( .A(Add_Subt_result[22]), .B(Add_Subt_result[23]), .Y(n1194)
);
AOI31XLTS U1621 ( .A0(Add_Subt_result[15]), .A1(n1397), .A2(n1462), .B0(
Add_Subt_result[19]), .Y(n1191) );
AOI21X1TS U1622 ( .A0(n1191), .A1(n1405), .B0(n1190), .Y(n1193) );
AOI211X1TS U1623 ( .A0(n1195), .A1(n1194), .B0(n1193), .C0(n1192), .Y(n1197)
);
NAND2X1TS U1624 ( .A(Add_Subt_result[14]), .B(n1196), .Y(n1206) );
AO22XLTS U1625 ( .A0(n1199), .A1(n1361), .B0(n1359), .B1(LZA_output[1]), .Y(
n731) );
NOR2XLTS U1626 ( .A(FS_Module_state_reg[0]), .B(n1200), .Y(n1201) );
MXI2X1TS U1627 ( .A(n1428), .B(add_overflow_flag), .S0(n1201), .Y(n701) );
NAND3BXLTS U1628 ( .AN(n1377), .B(n1404), .C(FS_Module_state_reg[0]), .Y(
n1202) );
MX2X1TS U1629 ( .A(exp_oper_result[7]), .B(Exp_Operation_Module_Data_S[7]),
.S0(n1341), .Y(n692) );
MX2X1TS U1630 ( .A(DMP[30]), .B(exp_oper_result[7]), .S0(n1204), .Y(
S_Oper_A_exp[7]) );
MX2X1TS U1631 ( .A(exp_oper_result[6]), .B(Exp_Operation_Module_Data_S[6]),
.S0(n1341), .Y(n693) );
MX2X1TS U1632 ( .A(DMP[29]), .B(exp_oper_result[6]), .S0(n1204), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U1633 ( .A(exp_oper_result[5]), .B(Exp_Operation_Module_Data_S[5]),
.S0(n1341), .Y(n694) );
MX2X1TS U1634 ( .A(DMP[28]), .B(exp_oper_result[5]), .S0(n1204), .Y(
S_Oper_A_exp[5]) );
MX2X1TS U1635 ( .A(exp_oper_result[4]), .B(Exp_Operation_Module_Data_S[4]),
.S0(n1341), .Y(n695) );
MX2X1TS U1636 ( .A(DMP[27]), .B(exp_oper_result[4]), .S0(n1204), .Y(
S_Oper_A_exp[4]) );
MX2X1TS U1637 ( .A(exp_oper_result[3]), .B(Exp_Operation_Module_Data_S[3]),
.S0(n1341), .Y(n696) );
MX2X1TS U1638 ( .A(DMP[26]), .B(exp_oper_result[3]), .S0(n1204), .Y(
S_Oper_A_exp[3]) );
MX2X1TS U1639 ( .A(exp_oper_result[2]), .B(Exp_Operation_Module_Data_S[2]),
.S0(n1341), .Y(n697) );
MX2X1TS U1640 ( .A(DMP[25]), .B(exp_oper_result[2]), .S0(n1204), .Y(
S_Oper_A_exp[2]) );
MX2X1TS U1641 ( .A(DMP[24]), .B(exp_oper_result[1]), .S0(n1204), .Y(
S_Oper_A_exp[1]) );
MX2X1TS U1642 ( .A(exp_oper_result[0]), .B(Exp_Operation_Module_Data_S[0]),
.S0(n1341), .Y(n699) );
MX2X1TS U1643 ( .A(DMP[23]), .B(exp_oper_result[0]), .S0(n1204), .Y(
S_Oper_A_exp[0]) );
AOI2BB1X1TS U1644 ( .A0N(Add_Subt_result[13]), .A1N(Add_Subt_result[11]),
.B0(n1205), .Y(n1218) );
NAND2X1TS U1645 ( .A(n1206), .B(n1222), .Y(n1351) );
AOI211XLTS U1646 ( .A0(Add_Subt_result[1]), .A1(n1207), .B0(n1218), .C0(
n1351), .Y(n1208) );
AO22XLTS U1647 ( .A0(n1211), .A1(n1361), .B0(LZA_output[3]), .B1(n1359), .Y(
n729) );
NAND2BXLTS U1648 ( .AN(Add_Subt_result[1]), .B(Add_Subt_result[0]), .Y(n1213) );
AOI211X1TS U1649 ( .A0(n1461), .A1(n1213), .B0(Add_Subt_result[3]), .C0(
n1212), .Y(n1214) );
AOI211X1TS U1650 ( .A0(n1349), .A1(Add_Subt_result[18]), .B0(n1215), .C0(
n1214), .Y(n1358) );
INVX2TS U1651 ( .A(n1216), .Y(n1219) );
AOI22X1TS U1652 ( .A0(Add_Subt_result[5]), .A1(n1221), .B0(
Add_Subt_result[3]), .B1(n1220), .Y(n1223) );
NAND4XLTS U1653 ( .A(n1358), .B(n1224), .C(n1223), .D(n1222), .Y(n1225) );
AO22XLTS U1654 ( .A0(n1225), .A1(n1361), .B0(n1359), .B1(LZA_output[2]), .Y(
n730) );
MX2X1TS U1655 ( .A(exp_oper_result[1]), .B(Exp_Operation_Module_Data_S[1]),
.S0(n1341), .Y(n698) );
AO22XLTS U1656 ( .A0(Add_Subt_Sgf_module_S_to_D[2]), .A1(n1228), .B0(n1333),
.B1(Add_Subt_result[2]), .Y(n736) );
AO22XLTS U1657 ( .A0(Add_Subt_Sgf_module_S_to_D[7]), .A1(n1228), .B0(n1333),
.B1(Add_Subt_result[7]), .Y(n741) );
AND4X1TS U1658 ( .A(Exp_Operation_Module_Data_S[3]), .B(
Exp_Operation_Module_Data_S[2]), .C(Exp_Operation_Module_Data_S[1]),
.D(Exp_Operation_Module_Data_S[0]), .Y(n1229) );
AND4X1TS U1659 ( .A(Exp_Operation_Module_Data_S[6]), .B(
Exp_Operation_Module_Data_S[5]), .C(Exp_Operation_Module_Data_S[4]),
.D(n1229), .Y(n1231) );
AOI21X1TS U1660 ( .A0(Exp_Operation_Module_Data_S[7]), .A1(n1231), .B0(n1230), .Y(n1232) );
MXI2X1TS U1661 ( .A(n1471), .B(n1232), .S0(n1341), .Y(n691) );
NOR2XLTS U1662 ( .A(n1309), .B(n1233), .Y(n1235) );
AOI22X1TS U1663 ( .A0(n1328), .A1(n1239), .B0(n1313), .B1(n1238), .Y(n1234)
);
OAI22X1TS U1664 ( .A0(n1236), .A1(n1235), .B0(n1234), .B1(n1322), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
AOI22X1TS U1665 ( .A0(n1238), .A1(n1308), .B0(n1237), .B1(n1328), .Y(n1243)
);
AOI22X1TS U1666 ( .A0(n1313), .A1(n1240), .B0(n1239), .B1(n1317), .Y(n1241)
);
AOI32X1TS U1667 ( .A0(n1243), .A1(n1242), .A2(n1241), .B0(n1322), .B1(n1242),
.Y(Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI22X1TS U1668 ( .A0(n1328), .A1(n1253), .B0(n1326), .B1(n1258), .Y(n1247)
);
AOI22X1TS U1669 ( .A0(n1245), .A1(n1272), .B0(n1308), .B1(n1249), .Y(n1246)
);
NAND2X1TS U1670 ( .A(n1247), .B(n1246), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
AOI22X1TS U1671 ( .A0(n1043), .A1(n1258), .B0(n1326), .B1(n1263), .Y(n1251)
);
AOI22X1TS U1672 ( .A0(n1308), .A1(n1253), .B0(n1272), .B1(n1249), .Y(n1250)
);
NAND2X1TS U1673 ( .A(n1251), .B(n1250), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
AOI22X1TS U1674 ( .A0(n1043), .A1(n1263), .B0(n1326), .B1(n1267), .Y(n1255)
);
AOI22X1TS U1675 ( .A0(n1308), .A1(n1258), .B0(n1272), .B1(n1253), .Y(n1254)
);
NAND2X1TS U1676 ( .A(n1255), .B(n1254), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI22X1TS U1677 ( .A0(n1328), .A1(n1267), .B0(n1326), .B1(n789), .Y(n1260)
);
AOI22X1TS U1678 ( .A0(n1319), .A1(n1263), .B0(n1272), .B1(n1258), .Y(n1259)
);
NAND2X1TS U1679 ( .A(n1260), .B(n1259), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI22X1TS U1680 ( .A0(n1043), .A1(n789), .B0(n1326), .B1(n792), .Y(n1265) );
AOI22X1TS U1681 ( .A0(n1319), .A1(n1267), .B0(n1272), .B1(n1263), .Y(n1264)
);
NAND2X1TS U1682 ( .A(n1265), .B(n1264), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI22X1TS U1683 ( .A0(n1043), .A1(n792), .B0(n1326), .B1(n793), .Y(n1269) );
AOI22X1TS U1684 ( .A0(n1319), .A1(n789), .B0(n1272), .B1(n1267), .Y(n1268)
);
NAND2X1TS U1685 ( .A(n1269), .B(n1268), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U1686 ( .A0(n1043), .A1(n793), .B0(n1326), .B1(n794), .Y(n1274) );
AOI22X1TS U1687 ( .A0(n1319), .A1(n792), .B0(n1272), .B1(n789), .Y(n1273) );
NAND2X1TS U1688 ( .A(n1274), .B(n1273), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U1689 ( .A0(n1328), .A1(n794), .B0(n1326), .B1(n790), .Y(n1277) );
AOI22X1TS U1690 ( .A0(n1319), .A1(n793), .B0(n1272), .B1(n792), .Y(n1276) );
NAND2X1TS U1691 ( .A(n1277), .B(n1276), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U1692 ( .A0(n1328), .A1(n790), .B0(n1326), .B1(n1289), .Y(n1280)
);
AOI22X1TS U1693 ( .A0(n1319), .A1(n794), .B0(n1272), .B1(n793), .Y(n1279) );
NAND2X1TS U1694 ( .A(n1280), .B(n1279), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U1695 ( .A0(n1328), .A1(n1289), .B0(n1313), .B1(n1294), .Y(n1283)
);
AOI22X1TS U1696 ( .A0(n1319), .A1(n790), .B0(n1317), .B1(n794), .Y(n1282) );
NAND2X1TS U1697 ( .A(n1283), .B(n1282), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U1698 ( .A0(n1328), .A1(n1294), .B0(n1313), .B1(n795), .Y(n1286)
);
AOI22X1TS U1699 ( .A0(n1319), .A1(n1289), .B0(n1317), .B1(n790), .Y(n1285)
);
NAND2X1TS U1700 ( .A(n1286), .B(n1285), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI22X1TS U1701 ( .A0(n1328), .A1(n795), .B0(n1313), .B1(n791), .Y(n1291) );
AOI22X1TS U1702 ( .A0(n1319), .A1(n1294), .B0(n1317), .B1(n1289), .Y(n1290)
);
NAND2X1TS U1703 ( .A(n1291), .B(n1290), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI22X1TS U1704 ( .A0(n1328), .A1(n791), .B0(n1313), .B1(n1312), .Y(n1296)
);
AOI22X1TS U1705 ( .A0(n1319), .A1(n795), .B0(n1272), .B1(n1294), .Y(n1295)
);
NAND2X1TS U1706 ( .A(n1296), .B(n1295), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U1707 ( .A0(Add_Subt_result[22]), .A1(n1321), .B0(DmP[1]), .B1(
n1302), .Y(n1299) );
NAND2X1TS U1708 ( .A(Add_Subt_result[3]), .B(n1261), .Y(n1298) );
AOI22X1TS U1709 ( .A0(n1328), .A1(n1312), .B0(n1326), .B1(n1316), .Y(n1301)
);
AOI22X1TS U1710 ( .A0(n1319), .A1(n791), .B0(n1272), .B1(n795), .Y(n1300) );
NAND2X1TS U1711 ( .A(n1301), .B(n1300), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U1712 ( .A0(Add_Subt_result[23]), .A1(n1321), .B0(DmP[0]), .B1(
n1302), .Y(n1305) );
NAND2X1TS U1713 ( .A(Add_Subt_result[2]), .B(n1261), .Y(n1304) );
AOI22X1TS U1714 ( .A0(n1328), .A1(n1316), .B0(n1326), .B1(n1318), .Y(n1307)
);
AOI22X1TS U1715 ( .A0(n1319), .A1(n1312), .B0(n1272), .B1(n791), .Y(n1306)
);
NAND2X1TS U1716 ( .A(n1307), .B(n1306), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U1717 ( .A0(n1328), .A1(n1318), .B0(n1308), .B1(n1316), .Y(n1315)
);
AOI22X1TS U1718 ( .A0(Add_Subt_result[24]), .A1(n1321), .B0(
Add_Subt_result[1]), .B1(n1261), .Y(n1311) );
AOI22X1TS U1719 ( .A0(n799), .A1(n1311), .B0(n1310), .B1(n1309), .Y(n1327)
);
AOI22X1TS U1720 ( .A0(n1326), .A1(n1327), .B0(n1272), .B1(n1312), .Y(n1314)
);
NAND2X1TS U1721 ( .A(n1315), .B(n1314), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
AOI22X1TS U1722 ( .A0(n1319), .A1(n1318), .B0(n1272), .B1(n1316), .Y(n1330)
);
AOI22X1TS U1723 ( .A0(Add_Subt_result[25]), .A1(n1321), .B0(
Add_Subt_result[0]), .B1(n1261), .Y(n1324) );
AOI22X1TS U1724 ( .A0(n798), .A1(n1324), .B0(n1323), .B1(n1322), .Y(n1325)
);
AOI22X1TS U1725 ( .A0(n1328), .A1(n1327), .B0(n1326), .B1(n1325), .Y(n1329)
);
NAND2X1TS U1726 ( .A(n1330), .B(n1329), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
AOI21X1TS U1727 ( .A0(n1332), .A1(n1331), .B0(n1368), .Y(n1346) );
OAI211XLTS U1728 ( .A0(n1336), .A1(n1335), .B0(n1334), .C0(n1333), .Y(n1337)
);
NAND2X1TS U1729 ( .A(n1346), .B(n1340), .Y(n763) );
AOI2BB1XLTS U1730 ( .A0N(FSM_selector_C), .A1N(n1342), .B0(n1341), .Y(n1345)
);
NAND4XLTS U1731 ( .A(n1346), .B(n1345), .C(n1344), .D(n1343), .Y(n760) );
AOI21X1TS U1732 ( .A0(Add_Subt_result[20]), .A1(n1463), .B0(
Add_Subt_result[22]), .Y(n1347) );
AOI31XLTS U1733 ( .A0(Add_Subt_result[16]), .A1(n1349), .A2(n1462), .B0(
n1348), .Y(n1357) );
INVX2TS U1734 ( .A(n1350), .Y(n1352) );
AOI31XLTS U1735 ( .A0(Add_Subt_result[6]), .A1(n1352), .A2(n1468), .B0(n1351), .Y(n1356) );
NAND4BXLTS U1736 ( .AN(Add_Subt_result[9]), .B(n1354), .C(Add_Subt_result[8]), .D(n1353), .Y(n1355) );
NAND4XLTS U1737 ( .A(n1358), .B(n1357), .C(n1356), .D(n1355), .Y(n1360) );
AO22XLTS U1738 ( .A0(n1361), .A1(n1360), .B0(n1359), .B1(LZA_output[0]), .Y(
n732) );
OA22X1TS U1739 ( .A0(exp_oper_result[0]), .A1(n1363), .B0(n1368), .B1(
final_result_ieee[23]), .Y(n689) );
OA22X1TS U1740 ( .A0(n1368), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1363), .Y(n688) );
OA22X1TS U1741 ( .A0(n1368), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1363), .Y(n687) );
OA22X1TS U1742 ( .A0(n1368), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1363), .Y(n686) );
OA22X1TS U1743 ( .A0(n1368), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1363), .Y(n685) );
OA22X1TS U1744 ( .A0(exp_oper_result[5]), .A1(n1363), .B0(n1368), .B1(
final_result_ieee[28]), .Y(n684) );
OA22X1TS U1745 ( .A0(exp_oper_result[6]), .A1(n1365), .B0(n1368), .B1(
final_result_ieee[29]), .Y(n683) );
OA22X1TS U1746 ( .A0(exp_oper_result[7]), .A1(n1365), .B0(n1368), .B1(
final_result_ieee[30]), .Y(n682) );
OAI2BB2XLTS U1747 ( .B0(n1399), .B1(n1365), .A0N(final_result_ieee[0]),
.A1N(n1362), .Y(n681) );
OAI2BB2XLTS U1748 ( .B0(n1401), .B1(n1365), .A0N(final_result_ieee[2]),
.A1N(n1362), .Y(n679) );
OAI2BB2XLTS U1749 ( .B0(n1402), .B1(n1365), .A0N(final_result_ieee[3]),
.A1N(n1362), .Y(n678) );
OAI2BB2XLTS U1750 ( .B0(n1403), .B1(n1365), .A0N(final_result_ieee[4]),
.A1N(n1362), .Y(n677) );
OAI2BB2XLTS U1751 ( .B0(n1407), .B1(n1365), .A0N(final_result_ieee[6]),
.A1N(n1362), .Y(n675) );
OAI2BB2XLTS U1752 ( .B0(n1408), .B1(n1365), .A0N(final_result_ieee[7]),
.A1N(n1366), .Y(n674) );
OAI2BB2XLTS U1753 ( .B0(n1409), .B1(n1365), .A0N(final_result_ieee[8]),
.A1N(n1366), .Y(n673) );
OAI2BB2XLTS U1754 ( .B0(n1412), .B1(n1365), .A0N(final_result_ieee[9]),
.A1N(n1366), .Y(n672) );
OAI2BB2XLTS U1755 ( .B0(n1429), .B1(n1363), .A0N(final_result_ieee[12]),
.A1N(n1366), .Y(n669) );
OAI2BB2XLTS U1756 ( .B0(n1430), .B1(n1363), .A0N(final_result_ieee[13]),
.A1N(n1366), .Y(n668) );
OAI2BB2XLTS U1757 ( .B0(n1433), .B1(n1363), .A0N(final_result_ieee[15]),
.A1N(n1366), .Y(n666) );
OAI2BB2XLTS U1758 ( .B0(n1439), .B1(n1363), .A0N(final_result_ieee[17]),
.A1N(n1366), .Y(n664) );
OAI2BB2XLTS U1759 ( .B0(n1459), .B1(n1363), .A0N(final_result_ieee[20]),
.A1N(n1366), .Y(n661) );
OAI2BB2XLTS U1760 ( .B0(n1464), .B1(n1364), .A0N(final_result_ieee[21]),
.A1N(n1366), .Y(n660) );
OAI2BB2XLTS U1761 ( .B0(n1465), .B1(n1365), .A0N(final_result_ieee[22]),
.A1N(n1366), .Y(n659) );
AOI21X1TS U1762 ( .A0(n1470), .A1(n1398), .B0(overflow_flag), .Y(n1367) );
AO22XLTS U1763 ( .A0(n1368), .A1(n1367), .B0(n1366), .B1(
final_result_ieee[31]), .Y(n657) );
INVX4TS U1764 ( .A(n1369), .Y(n1373) );
AO22XLTS U1765 ( .A0(n1369), .A1(intDX[30]), .B0(n1373), .B1(Data_X[30]),
.Y(n655) );
AO22XLTS U1766 ( .A0(n1369), .A1(intDX[29]), .B0(n1373), .B1(Data_X[29]),
.Y(n654) );
AO22XLTS U1767 ( .A0(n1369), .A1(intDX[28]), .B0(n1373), .B1(Data_X[28]),
.Y(n653) );
AO22XLTS U1768 ( .A0(n1369), .A1(intDX[27]), .B0(n1373), .B1(Data_X[27]),
.Y(n652) );
AO22XLTS U1769 ( .A0(n1369), .A1(intDX[26]), .B0(n1373), .B1(Data_X[26]),
.Y(n651) );
BUFX4TS U1770 ( .A(n1369), .Y(n1370) );
AO22XLTS U1771 ( .A0(n1370), .A1(intDX[25]), .B0(n1373), .B1(Data_X[25]),
.Y(n650) );
AO22XLTS U1772 ( .A0(n1369), .A1(intDX[24]), .B0(n1373), .B1(Data_X[24]),
.Y(n649) );
AO22XLTS U1773 ( .A0(n1369), .A1(intDX[23]), .B0(n1373), .B1(Data_X[23]),
.Y(n648) );
AO22XLTS U1774 ( .A0(n1370), .A1(intDX[22]), .B0(n1373), .B1(Data_X[22]),
.Y(n647) );
AO22XLTS U1775 ( .A0(n1370), .A1(intDX[21]), .B0(n1373), .B1(Data_X[21]),
.Y(n646) );
AO22XLTS U1776 ( .A0(n1369), .A1(intDX[20]), .B0(n1373), .B1(Data_X[20]),
.Y(n645) );
AO22XLTS U1777 ( .A0(n1370), .A1(intDX[19]), .B0(n1373), .B1(Data_X[19]),
.Y(n644) );
AO22XLTS U1778 ( .A0(n1370), .A1(intDX[18]), .B0(n1373), .B1(Data_X[18]),
.Y(n643) );
INVX4TS U1779 ( .A(n1369), .Y(n1372) );
AO22XLTS U1780 ( .A0(n1370), .A1(intDX[17]), .B0(n1372), .B1(Data_X[17]),
.Y(n642) );
AO22XLTS U1781 ( .A0(n1370), .A1(intDX[16]), .B0(n1372), .B1(Data_X[16]),
.Y(n641) );
AO22XLTS U1782 ( .A0(n1370), .A1(intDX[15]), .B0(n1372), .B1(Data_X[15]),
.Y(n640) );
AO22XLTS U1783 ( .A0(n1370), .A1(intDX[14]), .B0(n1372), .B1(Data_X[14]),
.Y(n639) );
AO22XLTS U1784 ( .A0(n1370), .A1(intDX[13]), .B0(n1372), .B1(Data_X[13]),
.Y(n638) );
AO22XLTS U1785 ( .A0(n1370), .A1(intDX[12]), .B0(n1372), .B1(Data_X[12]),
.Y(n637) );
AO22XLTS U1786 ( .A0(n1370), .A1(intDX[11]), .B0(n1372), .B1(Data_X[11]),
.Y(n636) );
AO22XLTS U1787 ( .A0(n1370), .A1(intDX[10]), .B0(n1372), .B1(Data_X[10]),
.Y(n635) );
AO22XLTS U1788 ( .A0(n1370), .A1(intDX[9]), .B0(n1372), .B1(Data_X[9]), .Y(
n634) );
AO22XLTS U1789 ( .A0(n1370), .A1(intDX[8]), .B0(n1372), .B1(Data_X[8]), .Y(
n633) );
AO22XLTS U1790 ( .A0(n1370), .A1(intDX[7]), .B0(n1372), .B1(Data_X[7]), .Y(
n632) );
AO22XLTS U1791 ( .A0(n1370), .A1(intDX[6]), .B0(n1372), .B1(Data_X[6]), .Y(
n631) );
AO22XLTS U1792 ( .A0(n1370), .A1(intDX[5]), .B0(n1372), .B1(Data_X[5]), .Y(
n630) );
AO22XLTS U1793 ( .A0(n1370), .A1(intDX[4]), .B0(n1372), .B1(Data_X[4]), .Y(
n629) );
BUFX4TS U1794 ( .A(n802), .Y(n1371) );
INVX4TS U1795 ( .A(n1369), .Y(n1375) );
AO22XLTS U1796 ( .A0(n1371), .A1(intDX[3]), .B0(n1375), .B1(Data_X[3]), .Y(
n628) );
AO22XLTS U1797 ( .A0(n1371), .A1(intDX[2]), .B0(n1375), .B1(Data_X[2]), .Y(
n627) );
AO22XLTS U1798 ( .A0(n1371), .A1(intDX[1]), .B0(n1375), .B1(Data_X[1]), .Y(
n626) );
AO22XLTS U1799 ( .A0(n1371), .A1(intDX[0]), .B0(n1375), .B1(Data_X[0]), .Y(
n625) );
AO22XLTS U1800 ( .A0(n1375), .A1(add_subt), .B0(n1371), .B1(intAS), .Y(n623)
);
AO22XLTS U1801 ( .A0(n1375), .A1(Data_Y[30]), .B0(n1371), .B1(intDY[30]),
.Y(n622) );
AO22XLTS U1802 ( .A0(n1375), .A1(Data_Y[29]), .B0(n1371), .B1(intDY[29]),
.Y(n621) );
AO22XLTS U1803 ( .A0(n1375), .A1(Data_Y[26]), .B0(n1371), .B1(intDY[26]),
.Y(n618) );
AO22XLTS U1804 ( .A0(n1375), .A1(Data_Y[25]), .B0(n1371), .B1(intDY[25]),
.Y(n617) );
AO22XLTS U1805 ( .A0(n1375), .A1(Data_Y[23]), .B0(n802), .B1(intDY[23]), .Y(
n615) );
AO22XLTS U1806 ( .A0(n1372), .A1(Data_Y[22]), .B0(n1371), .B1(intDY[22]),
.Y(n614) );
AO22XLTS U1807 ( .A0(n1373), .A1(Data_Y[21]), .B0(n1371), .B1(intDY[21]),
.Y(n613) );
AO22XLTS U1808 ( .A0(n1375), .A1(Data_Y[20]), .B0(n1371), .B1(intDY[20]),
.Y(n612) );
AO22XLTS U1809 ( .A0(n1372), .A1(Data_Y[19]), .B0(n1371), .B1(intDY[19]),
.Y(n611) );
AO22XLTS U1810 ( .A0(n1373), .A1(Data_Y[18]), .B0(n1371), .B1(intDY[18]),
.Y(n610) );
AO22XLTS U1811 ( .A0(n1375), .A1(Data_Y[17]), .B0(n1371), .B1(intDY[17]),
.Y(n609) );
AO22XLTS U1812 ( .A0(n1372), .A1(Data_Y[15]), .B0(n802), .B1(intDY[15]), .Y(
n607) );
AO22XLTS U1813 ( .A0(n1373), .A1(Data_Y[14]), .B0(n802), .B1(intDY[14]), .Y(
n606) );
AO22XLTS U1814 ( .A0(n1375), .A1(Data_Y[13]), .B0(n802), .B1(intDY[13]), .Y(
n605) );
AO22XLTS U1815 ( .A0(n1373), .A1(Data_Y[12]), .B0(n802), .B1(intDY[12]), .Y(
n604) );
AO22XLTS U1816 ( .A0(n1374), .A1(Data_Y[11]), .B0(n1370), .B1(intDY[11]),
.Y(n603) );
AO22XLTS U1817 ( .A0(n1374), .A1(Data_Y[8]), .B0(n1369), .B1(intDY[8]), .Y(
n600) );
AO22XLTS U1818 ( .A0(n1374), .A1(Data_Y[3]), .B0(n802), .B1(intDY[3]), .Y(
n595) );
AO22XLTS U1819 ( .A0(n1374), .A1(Data_Y[1]), .B0(n802), .B1(intDY[1]), .Y(
n593) );
AO22XLTS U1820 ( .A0(n1375), .A1(Data_Y[31]), .B0(n802), .B1(intDY[31]), .Y(
n591) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk30.tcl_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21OI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A21OI_FUNCTIONAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a21oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21OI_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_LP_V
`define SKY130_FD_SC_LP__XNOR3_LP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor3_lp (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor3_lp (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_TB_V
`define SKY130_FD_SC_MS__O211A_TB_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ms__o211a dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_TB_V
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_priority_encoder;
// parameters
localparam WIDTH = 32;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_unencoded = 0;
// Outputs
wire output_valid;
wire [$clog2(WIDTH)-1:0] output_encoded;
wire [WIDTH-1:0] output_unencoded;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_unencoded);
$to_myhdl(output_valid,
output_encoded,
output_unencoded);
// dump file
$dumpfile("test_priority_encoder.lxt");
$dumpvars(0, test_priority_encoder);
end
priority_encoder #(
.WIDTH(WIDTH)
)
UUT (
.input_unencoded(input_unencoded),
.output_valid(output_valid),
.output_encoded(output_encoded),
.output_unencoded(output_unencoded)
);
endmodule
|
//
//////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////////
//
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 2.10
// \ \ Filename: bbfifo_16x8.v
// / / Date Last Modified: March 19 2010
// /___/ /\ Date Created: October 14 2002
// \ \ / \
// \___\/\___\
//
// Device: Xilinx
// Purpose: 'Bucket Brigade' FIFO, 16 deep, 8-bit data
//
//
// This module was made for use with Spartan-3 Generation Devices and is also ideally
// suited for use with Virtex-II(PRO) and Virtex-4 devices. Will also work in Virtex-5,
// Virtex-6 and Spartan-6 devices but it is not specifically optimised for these
// architectures.
//
//
// Contact: e-mail [email protected]
//
//
// Revision History:
// Rev 1.00 - kc - Start of design entry in VHDL, October 14 2002.
// Rev 1.01 - sus - Converted to verilog, August 4 2004.
// Rev 1.02 - njs - Synplicity attributes added, September 6 2004.
// Rev 1.03 - njs - defparam values corrected, December 1 2005.
// Rev 1.04 - njs - INIT values specified using Verilog 2001 format, July 6 2005.
// Rev 1.03 - kc - Minor format changes, January 17 2007.
// Rev 2.10 - njs - March 19 2010.
// The Verilog coding style adjusted to be compatible with XST provided
// as part of the ISE v12.1i tools when targeting Spartan-6 and Virtex-6
// devices. No functional changes.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Format of this file.
//
// The module defines the implementation of the logic using Xilinx primitives.
// These ensure predictable synthesis results and maximise the density of the
// implementation. The Unisim Library is used to define Xilinx primitives.
// The source can be viewed at %XILINX%\verilog\src\unisims.
//
//////////////////////////////////////////////////////////////////////////////////
//
`timescale 1 ps / 1ps
module bbfifo_16x8(
input [7:0] data_in,
output [7:0] data_out,
input reset,
input write,
input read,
output full,
output half_full,
output data_present,
input clk);
//
//////////////////////////////////////////////////////////////////////////////////
//
// Signals used in BBFIFO_16x8
//
//////////////////////////////////////////////////////////////////////////////////
//
wire [3:0] pointer;
wire [3:0] next_count;
wire [3:0] half_count;
wire [2:0] count_carry;
wire pointer_zero;
wire pointer_full;
wire decode_data_present;
wire data_present_int;
wire valid_write;
//
//////////////////////////////////////////////////////////////////////////////////
//
// Start of BBFIFO_16x8 circuit description
//
//////////////////////////////////////////////////////////////////////////////////
//
// SRL16E data storage
genvar i ;
generate
for (i = 0; i <= 7; i = i + 1)
begin : data_width_loop
SRL16E #(
.INIT (16'h0000))
data_srl (
.D (data_in[i]),
.CE (valid_write),
.CLK (clk),
.A0 (pointer[0]),
.A1 (pointer[1]),
.A2 (pointer[2]),
.A3 (pointer[3]),
.Q (data_out[i])) ;
end
endgenerate
// 4-bit counter to act as data pointer
// Counter is clock enabled by 'data_present'
// Counter will be reset when 'reset' is active
// Counter will increment when 'valid_write' is active
generate
for (i = 0; i <= 3; i = i + 1)
begin : count_width_loop
FDRE register_bit(
.D (next_count[i]),
.Q (pointer[i]),
.CE (data_present_int),
.R (reset),
.C (clk));
LUT4 #(
.INIT (16'h6606))
count_lut(
.I0 (pointer[i]),
.I1 (read),
.I2 (pointer_zero),
.I3 (write),
.O (half_count[i])) ;
if (i == 0) begin : lsb_count
MUXCY count_muxcy_0(
.DI (pointer[i]),
.CI (valid_write),
.S (half_count[i]),
.O (count_carry[i]) );
XORCY count_xor_0(
.LI (half_count[i]),
.CI (valid_write),
.O (next_count[i]));
end
if (i > 0 && i < 3) begin : mid_count
MUXCY count_muxcy (
.DI (pointer[i]),
.CI (count_carry[i-1]),
.S (half_count[i]),
.O (count_carry[i]));
XORCY count_xor(
.LI (half_count[i]),
.CI (count_carry[i-1]),
.O (next_count[i]));
end
if (i == 3) begin : msb_count
XORCY count_xor(
.LI (half_count[i]),
.CI (count_carry[i-1]),
.O (next_count[i]));
end
end
endgenerate
// Detect when pointer is zero and maximum
LUT4 #(
.INIT (16'h0001))
zero_lut(
.I0 (pointer[0]),
.I1 (pointer[1]),
.I2 (pointer[2]),
.I3 (pointer[3]),
.O (pointer_zero)) ;
LUT4 #(
.INIT (16'h8000))
full_lut(
.I0 (pointer[0]),
.I1 (pointer[1]),
.I2 (pointer[2]),
.I3 (pointer[3]),
.O (pointer_full)) ;
// Data Present status
LUT4 #(
.INIT (16'hBFA0))
dp_lut(
.I0 (write),
.I1 (read),
.I2 (pointer_zero),
.I3 (data_present_int),
.O (decode_data_present)) ;
FDR dp_flop(
.D (decode_data_present),
.Q (data_present_int),
.R (reset),
.C (clk));
// Valid write wire
LUT3 #(
.INIT (8'hC4))
valid_lut(
.I0 (pointer_full),
.I1 (write),
.I2 (read),
.O (valid_write)) ;
// assign internal wires to outputs
assign full = pointer_full;
assign half_full = pointer[3];
assign data_present = data_present_int;
endmodule
//
//////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE BBFIFO_16x8.V
//
//////////////////////////////////////////////////////////////////////////////////
//
|
// Library - static, Cell - th34w3, View - schematic
// LAST TIME SAVED: May 23 17:03:47 2014
// NETLIST TIME: May 23 17:04:07 2014
`timescale 1ns / 1ns
module th34w3 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th34w3";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N7 ( .d(net30), .g(d), .s(net37), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net30), .g(c), .s(net37), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net30), .g(b), .s(net37), .b(cds_globals.gnd_));
nfet_b N2 ( .d(net30), .g(b), .s(net44), .b(cds_globals.gnd_));
nfet_b N0 ( .d(net30), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N8 ( .d(net37), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(c), .s(net43), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net43), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
inv I2 ( y, net30);
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net36));
pfet_b P0 ( .b(cds_globals.vdd_), .g(d), .s(cds_globals.vdd_),
.d(net46));
pfet_b P4 ( .b(cds_globals.vdd_), .g(c), .s(net36), .d(net33));
pfet_b P1 ( .b(cds_globals.vdd_), .g(c), .s(net46), .d(net45));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net36), .d(net33));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(net45), .d(net33));
pfet_b P6 ( .b(cds_globals.vdd_), .g(d), .s(net36), .d(net33));
pfet_b P3 ( .b(cds_globals.vdd_), .g(a), .s(net33), .d(net30));
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:45:52 11/03/2011
// Design Name: MGIA
// Module Name: /Users/kc5tja/tmp/kestrel/2/nexys2/uxa/mgia/T_uxa_mgia.v
// Project Name: mgia
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MGIA
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T_uxa_mgia;
// Inputs
reg CLK_I_50MHZ;
reg RST_I;
// Outputs
wire HSYNC_O;
wire VSYNC_O;
wire [2:0] RED_O;
wire [2:0] GRN_O;
wire [2:1] BLU_O;
// Instantiate the Unit Under Test (UUT)
MGIA uut (
.CLK_I_50MHZ(CLK_I_50MHZ),
.RST_I(RST_I),
.HSYNC_O(HSYNC_O),
.VSYNC_O(VSYNC_O),
.RED_O(RED_O),
.GRN_O(GRN_O),
.BLU_O(BLU_O)
);
always begin
#10 CLK_I_50MHZ <= ~CLK_I_50MHZ;
end
initial begin
// Initialize Inputs
CLK_I_50MHZ <= 0;
RST_I <= 1;
#100 RST_I <= 0;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: sum_18_19.v
// /___/ /\ Timestamp: Mon Mar 30 22:56:15 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/sum_18_19/tmp/_cg/sum_18_19.ngc C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/sum_18_19/tmp/_cg/sum_18_19.v
// Device : 6slx45csg324-2
// Input file : C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/sum_18_19/tmp/_cg/sum_18_19.ngc
// Output file : C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/sum_18_19/tmp/_cg/sum_18_19.v
// # of Modules : 1
// Design Name : sum_18_19
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module sum_18_19 (
clk, ce, a, b, s
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input [17 : 0] a;
input [18 : 0] b;
output [19 : 0] s;
// synthesis translate_off
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \NLW_blk00000001/blk000000a2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000009e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000009c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000009a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000098_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000096_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000094_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000092_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000090_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000008e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000008c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000008a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000056_O_UNCONNECTED ;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c8 ),
.Q(\blk00000001/sig00000040 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000a2 (
.A0(\blk00000001/sig0000003d ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000085 ),
.Q(\blk00000001/sig000000c8 ),
.Q15(\NLW_blk00000001/blk000000a2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c7 ),
.Q(\blk00000001/sig00000041 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000000a0 (
.A0(\blk00000001/sig0000003d ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000084 ),
.Q(\blk00000001/sig000000c7 ),
.Q15(\NLW_blk00000001/blk000000a0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c6 ),
.Q(\blk00000001/sig0000003f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000009e (
.A0(\blk00000001/sig0000003d ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000007f ),
.Q(\blk00000001/sig000000c6 ),
.Q15(\NLW_blk00000001/blk0000009e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c5 ),
.Q(\blk00000001/sig00000043 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000009c (
.A0(\blk00000001/sig0000003d ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000082 ),
.Q(\blk00000001/sig000000c5 ),
.Q15(\NLW_blk00000001/blk0000009c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c4 ),
.Q(\blk00000001/sig00000044 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000009a (
.A0(\blk00000001/sig0000003d ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000081 ),
.Q(\blk00000001/sig000000c4 ),
.Q15(\NLW_blk00000001/blk0000009a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000099 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c3 ),
.Q(\blk00000001/sig00000042 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000098 (
.A0(\blk00000001/sig0000003d ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000083 ),
.Q(\blk00000001/sig000000c3 ),
.Q15(\NLW_blk00000001/blk00000098_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000097 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c2 ),
.Q(s[0])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000096 (
.A0(\blk00000001/sig0000003c ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000058 ),
.Q(\blk00000001/sig000000c2 ),
.Q15(\NLW_blk00000001/blk00000096_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000095 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c1 ),
.Q(s[1])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000094 (
.A0(\blk00000001/sig0000003c ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000005d ),
.Q(\blk00000001/sig000000c1 ),
.Q15(\NLW_blk00000001/blk00000094_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000093 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c0 ),
.Q(\blk00000001/sig00000045 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000092 (
.A0(\blk00000001/sig0000003d ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000080 ),
.Q(\blk00000001/sig000000c0 ),
.Q15(\NLW_blk00000001/blk00000092_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000091 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000bf ),
.Q(s[2])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000090 (
.A0(\blk00000001/sig0000003c ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000005c ),
.Q(\blk00000001/sig000000bf ),
.Q15(\NLW_blk00000001/blk00000090_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000be ),
.Q(s[3])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000008e (
.A0(\blk00000001/sig0000003c ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000005b ),
.Q(\blk00000001/sig000000be ),
.Q15(\NLW_blk00000001/blk0000008e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000bd ),
.Q(s[4])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000008c (
.A0(\blk00000001/sig0000003c ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000005a ),
.Q(\blk00000001/sig000000bd ),
.Q15(\NLW_blk00000001/blk0000008c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000bc ),
.Q(s[5])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000008a (
.A0(\blk00000001/sig0000003c ),
.A1(\blk00000001/sig0000003d ),
.A2(\blk00000001/sig0000003d ),
.A3(\blk00000001/sig0000003d ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000059 ),
.Q(\blk00000001/sig000000bc ),
.Q15(\NLW_blk00000001/blk0000008a_Q15_UNCONNECTED )
);
INV \blk00000001/blk00000089 (
.I(\blk00000001/sig0000004f ),
.O(\blk00000001/sig000000bb )
);
MUXCY \blk00000001/blk00000088 (
.CI(\blk00000001/sig00000047 ),
.DI(\blk00000001/sig0000003c ),
.S(\blk00000001/sig000000bb ),
.O(\blk00000001/sig0000003e )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000087 (
.I0(\blk00000001/sig0000003f ),
.O(\blk00000001/sig000000ba )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000086 (
.I0(\blk00000001/sig00000040 ),
.O(\blk00000001/sig000000b9 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000085 (
.I0(\blk00000001/sig00000041 ),
.O(\blk00000001/sig000000b8 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000084 (
.I0(\blk00000001/sig00000045 ),
.O(\blk00000001/sig000000b7 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000083 (
.I0(\blk00000001/sig00000042 ),
.O(\blk00000001/sig000000b6 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000082 (
.I0(\blk00000001/sig00000043 ),
.O(\blk00000001/sig000000b5 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000081 (
.I0(\blk00000001/sig00000044 ),
.O(\blk00000001/sig000000b4 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000080 (
.I0(\blk00000001/sig00000050 ),
.O(\blk00000001/sig000000b3 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000007f (
.I0(\blk00000001/sig00000051 ),
.O(\blk00000001/sig000000b2 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000007e (
.I0(\blk00000001/sig00000052 ),
.O(\blk00000001/sig000000b1 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000007d (
.I0(\blk00000001/sig00000056 ),
.O(\blk00000001/sig000000b0 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000007c (
.I0(\blk00000001/sig00000053 ),
.O(\blk00000001/sig000000af )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000007b (
.I0(\blk00000001/sig00000054 ),
.O(\blk00000001/sig000000ae )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000007a (
.I0(\blk00000001/sig00000055 ),
.O(\blk00000001/sig000000ad )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000079 (
.I0(a[17]),
.I1(b[18]),
.O(\blk00000001/sig000000ac )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000078 (
.I0(a[17]),
.I1(b[18]),
.O(\blk00000001/sig00000086 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000077 (
.I0(a[17]),
.I1(b[17]),
.O(\blk00000001/sig00000087 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000076 (
.I0(a[16]),
.I1(b[16]),
.O(\blk00000001/sig00000088 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000075 (
.I0(a[15]),
.I1(b[15]),
.O(\blk00000001/sig00000089 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000074 (
.I0(a[14]),
.I1(b[14]),
.O(\blk00000001/sig0000008a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000073 (
.I0(a[13]),
.I1(b[13]),
.O(\blk00000001/sig0000008b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000072 (
.I0(a[12]),
.I1(b[12]),
.O(\blk00000001/sig00000076 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000071 (
.I0(a[11]),
.I1(b[11]),
.O(\blk00000001/sig00000071 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000070 (
.I0(a[10]),
.I1(b[10]),
.O(\blk00000001/sig00000072 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006f (
.I0(a[9]),
.I1(b[9]),
.O(\blk00000001/sig00000073 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006e (
.I0(a[8]),
.I1(b[8]),
.O(\blk00000001/sig00000074 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006d (
.I0(a[7]),
.I1(b[7]),
.O(\blk00000001/sig00000075 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006c (
.I0(a[6]),
.I1(b[6]),
.O(\blk00000001/sig00000077 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006b (
.I0(a[5]),
.I1(b[5]),
.O(\blk00000001/sig00000062 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006a (
.I0(a[4]),
.I1(b[4]),
.O(\blk00000001/sig0000005e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000069 (
.I0(a[3]),
.I1(b[3]),
.O(\blk00000001/sig0000005f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000068 (
.I0(a[2]),
.I1(b[2]),
.O(\blk00000001/sig00000060 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000067 (
.I0(a[1]),
.I1(b[1]),
.O(\blk00000001/sig00000061 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000066 (
.I0(a[0]),
.I1(b[0]),
.O(\blk00000001/sig00000063 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000065 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000048 ),
.Q(s[6])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000064 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000049 ),
.Q(s[7])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000063 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000004a ),
.Q(s[8])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000062 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000004b ),
.Q(s[9])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000061 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000004c ),
.Q(s[10])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000060 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000004d ),
.Q(s[11])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000004e ),
.Q(s[12])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000003e ),
.Q(\blk00000001/sig00000046 )
);
MUXCY \blk00000001/blk0000005d (
.CI(\blk00000001/sig00000046 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000ba ),
.O(\blk00000001/sig000000ab )
);
XORCY \blk00000001/blk0000005c (
.CI(\blk00000001/sig00000046 ),
.LI(\blk00000001/sig000000ba ),
.O(\blk00000001/sig000000aa )
);
MUXCY \blk00000001/blk0000005b (
.CI(\blk00000001/sig000000ab ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000000a9 )
);
XORCY \blk00000001/blk0000005a (
.CI(\blk00000001/sig000000ab ),
.LI(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000000a8 )
);
MUXCY \blk00000001/blk00000059 (
.CI(\blk00000001/sig000000a9 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig000000a7 )
);
XORCY \blk00000001/blk00000058 (
.CI(\blk00000001/sig000000a9 ),
.LI(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig000000a6 )
);
XORCY \blk00000001/blk00000057 (
.CI(\blk00000001/sig000000a0 ),
.LI(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000000a5 )
);
MUXCY \blk00000001/blk00000056 (
.CI(\blk00000001/sig000000a0 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b7 ),
.O(\NLW_blk00000001/blk00000056_O_UNCONNECTED )
);
MUXCY \blk00000001/blk00000055 (
.CI(\blk00000001/sig000000a7 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b6 ),
.O(\blk00000001/sig000000a4 )
);
XORCY \blk00000001/blk00000054 (
.CI(\blk00000001/sig000000a7 ),
.LI(\blk00000001/sig000000b6 ),
.O(\blk00000001/sig000000a3 )
);
MUXCY \blk00000001/blk00000053 (
.CI(\blk00000001/sig000000a4 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000000a2 )
);
XORCY \blk00000001/blk00000052 (
.CI(\blk00000001/sig000000a4 ),
.LI(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000000a1 )
);
MUXCY \blk00000001/blk00000051 (
.CI(\blk00000001/sig000000a2 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b4 ),
.O(\blk00000001/sig000000a0 )
);
XORCY \blk00000001/blk00000050 (
.CI(\blk00000001/sig000000a2 ),
.LI(\blk00000001/sig000000b4 ),
.O(\blk00000001/sig0000009f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000a5 ),
.Q(s[19])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000009f ),
.Q(s[18])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000a1 ),
.Q(s[17])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000a3 ),
.Q(s[16])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000a6 ),
.Q(s[15])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000a8 ),
.Q(s[14])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000049 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000aa ),
.Q(s[13])
);
MUXCY \blk00000001/blk00000048 (
.CI(\blk00000001/sig00000057 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig0000009e )
);
XORCY \blk00000001/blk00000047 (
.CI(\blk00000001/sig00000057 ),
.LI(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig0000009d )
);
MUXCY \blk00000001/blk00000046 (
.CI(\blk00000001/sig0000009e ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig0000009c )
);
XORCY \blk00000001/blk00000045 (
.CI(\blk00000001/sig0000009e ),
.LI(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig0000009b )
);
MUXCY \blk00000001/blk00000044 (
.CI(\blk00000001/sig0000009c ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b1 ),
.O(\blk00000001/sig0000009a )
);
XORCY \blk00000001/blk00000043 (
.CI(\blk00000001/sig0000009c ),
.LI(\blk00000001/sig000000b1 ),
.O(\blk00000001/sig00000099 )
);
XORCY \blk00000001/blk00000042 (
.CI(\blk00000001/sig00000093 ),
.LI(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig00000098 )
);
MUXCY \blk00000001/blk00000041 (
.CI(\blk00000001/sig00000093 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig00000047 )
);
MUXCY \blk00000001/blk00000040 (
.CI(\blk00000001/sig0000009a ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000af ),
.O(\blk00000001/sig00000097 )
);
XORCY \blk00000001/blk0000003f (
.CI(\blk00000001/sig0000009a ),
.LI(\blk00000001/sig000000af ),
.O(\blk00000001/sig00000096 )
);
MUXCY \blk00000001/blk0000003e (
.CI(\blk00000001/sig00000097 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000ae ),
.O(\blk00000001/sig00000095 )
);
XORCY \blk00000001/blk0000003d (
.CI(\blk00000001/sig00000097 ),
.LI(\blk00000001/sig000000ae ),
.O(\blk00000001/sig00000094 )
);
MUXCY \blk00000001/blk0000003c (
.CI(\blk00000001/sig00000095 ),
.DI(\blk00000001/sig0000003d ),
.S(\blk00000001/sig000000ad ),
.O(\blk00000001/sig00000093 )
);
XORCY \blk00000001/blk0000003b (
.CI(\blk00000001/sig00000095 ),
.LI(\blk00000001/sig000000ad ),
.O(\blk00000001/sig00000092 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000098 ),
.Q(\blk00000001/sig0000004e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000039 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000092 ),
.Q(\blk00000001/sig0000004d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000038 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000094 ),
.Q(\blk00000001/sig0000004c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000037 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000096 ),
.Q(\blk00000001/sig0000004b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000036 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000099 ),
.Q(\blk00000001/sig0000004a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000035 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000009b ),
.Q(\blk00000001/sig00000049 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000034 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000009d ),
.Q(\blk00000001/sig00000048 )
);
MUXCY \blk00000001/blk00000033 (
.CI(\blk00000001/sig0000003d ),
.DI(a[13]),
.S(\blk00000001/sig0000008b ),
.O(\blk00000001/sig00000091 )
);
MUXCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig00000091 ),
.DI(a[14]),
.S(\blk00000001/sig0000008a ),
.O(\blk00000001/sig00000090 )
);
MUXCY \blk00000001/blk00000031 (
.CI(\blk00000001/sig00000090 ),
.DI(a[15]),
.S(\blk00000001/sig00000089 ),
.O(\blk00000001/sig0000008f )
);
MUXCY \blk00000001/blk00000030 (
.CI(\blk00000001/sig0000008f ),
.DI(a[16]),
.S(\blk00000001/sig00000088 ),
.O(\blk00000001/sig0000008e )
);
MUXCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig0000008e ),
.DI(a[17]),
.S(\blk00000001/sig00000087 ),
.O(\blk00000001/sig0000008d )
);
MUXCY \blk00000001/blk0000002e (
.CI(\blk00000001/sig0000008d ),
.DI(a[17]),
.S(\blk00000001/sig000000ac ),
.O(\blk00000001/sig0000008c )
);
XORCY \blk00000001/blk0000002d (
.CI(\blk00000001/sig00000091 ),
.LI(\blk00000001/sig0000008a ),
.O(\blk00000001/sig00000085 )
);
XORCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig00000090 ),
.LI(\blk00000001/sig00000089 ),
.O(\blk00000001/sig00000084 )
);
XORCY \blk00000001/blk0000002b (
.CI(\blk00000001/sig0000008f ),
.LI(\blk00000001/sig00000088 ),
.O(\blk00000001/sig00000083 )
);
XORCY \blk00000001/blk0000002a (
.CI(\blk00000001/sig0000008e ),
.LI(\blk00000001/sig00000087 ),
.O(\blk00000001/sig00000082 )
);
XORCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig0000008d ),
.LI(\blk00000001/sig000000ac ),
.O(\blk00000001/sig00000081 )
);
XORCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig0000008c ),
.LI(\blk00000001/sig00000086 ),
.O(\blk00000001/sig00000080 )
);
XORCY \blk00000001/blk00000027 (
.CI(\blk00000001/sig0000003d ),
.LI(\blk00000001/sig0000008b ),
.O(\blk00000001/sig0000007f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000026 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006a ),
.Q(\blk00000001/sig00000050 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000025 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000070 ),
.Q(\blk00000001/sig00000051 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000024 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006f ),
.Q(\blk00000001/sig00000052 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000023 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006e ),
.Q(\blk00000001/sig00000053 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000022 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006d ),
.Q(\blk00000001/sig00000054 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000021 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006c ),
.Q(\blk00000001/sig00000055 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000020 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006b ),
.Q(\blk00000001/sig00000056 )
);
MUXCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig0000003d ),
.DI(a[6]),
.S(\blk00000001/sig00000077 ),
.O(\blk00000001/sig0000007e )
);
MUXCY \blk00000001/blk0000001e (
.CI(\blk00000001/sig00000078 ),
.DI(a[12]),
.S(\blk00000001/sig00000076 ),
.O(\blk00000001/sig0000007d )
);
MUXCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig0000007e ),
.DI(a[7]),
.S(\blk00000001/sig00000075 ),
.O(\blk00000001/sig0000007c )
);
MUXCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig0000007c ),
.DI(a[8]),
.S(\blk00000001/sig00000074 ),
.O(\blk00000001/sig0000007b )
);
MUXCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig0000007b ),
.DI(a[9]),
.S(\blk00000001/sig00000073 ),
.O(\blk00000001/sig0000007a )
);
MUXCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig0000007a ),
.DI(a[10]),
.S(\blk00000001/sig00000072 ),
.O(\blk00000001/sig00000079 )
);
MUXCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig00000079 ),
.DI(a[11]),
.S(\blk00000001/sig00000071 ),
.O(\blk00000001/sig00000078 )
);
XORCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig0000007e ),
.LI(\blk00000001/sig00000075 ),
.O(\blk00000001/sig00000070 )
);
XORCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig0000007c ),
.LI(\blk00000001/sig00000074 ),
.O(\blk00000001/sig0000006f )
);
XORCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig0000007b ),
.LI(\blk00000001/sig00000073 ),
.O(\blk00000001/sig0000006e )
);
XORCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig0000007a ),
.LI(\blk00000001/sig00000072 ),
.O(\blk00000001/sig0000006d )
);
XORCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig00000079 ),
.LI(\blk00000001/sig00000071 ),
.O(\blk00000001/sig0000006c )
);
XORCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig00000078 ),
.LI(\blk00000001/sig00000076 ),
.O(\blk00000001/sig0000006b )
);
XORCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig0000003d ),
.LI(\blk00000001/sig00000077 ),
.O(\blk00000001/sig0000006a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000011 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000007d ),
.Q(\blk00000001/sig0000004f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000010 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000068 ),
.Q(\blk00000001/sig00000057 )
);
MUXCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig0000003d ),
.DI(a[0]),
.S(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000069 )
);
MUXCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig00000064 ),
.DI(a[5]),
.S(\blk00000001/sig00000062 ),
.O(\blk00000001/sig00000068 )
);
MUXCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig00000069 ),
.DI(a[1]),
.S(\blk00000001/sig00000061 ),
.O(\blk00000001/sig00000067 )
);
MUXCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig00000067 ),
.DI(a[2]),
.S(\blk00000001/sig00000060 ),
.O(\blk00000001/sig00000066 )
);
MUXCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig00000066 ),
.DI(a[3]),
.S(\blk00000001/sig0000005f ),
.O(\blk00000001/sig00000065 )
);
MUXCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig00000065 ),
.DI(a[4]),
.S(\blk00000001/sig0000005e ),
.O(\blk00000001/sig00000064 )
);
XORCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig00000069 ),
.LI(\blk00000001/sig00000061 ),
.O(\blk00000001/sig0000005d )
);
XORCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig00000067 ),
.LI(\blk00000001/sig00000060 ),
.O(\blk00000001/sig0000005c )
);
XORCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig00000066 ),
.LI(\blk00000001/sig0000005f ),
.O(\blk00000001/sig0000005b )
);
XORCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig00000065 ),
.LI(\blk00000001/sig0000005e ),
.O(\blk00000001/sig0000005a )
);
XORCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig00000064 ),
.LI(\blk00000001/sig00000062 ),
.O(\blk00000001/sig00000059 )
);
XORCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig0000003d ),
.LI(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000058 )
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig0000003d )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig0000003c )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_dctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_dctl (/*AUTOARG*/
// Outputs
que_margin_reg, readqbank0vld0, readqbank0vld1, readqbank0vld2,
readqbank0vld3, writeqbank0vld0, writeqbank0vld1, writeqbank0vld2,
writeqbank0vld3, readqbank0vld4, readqbank0vld5, readqbank0vld6,
readqbank0vld7, writeqbank0vld4, writeqbank0vld5, writeqbank0vld6,
writeqbank0vld7, que_wr_req, dp_data_in, dp_ecc_in, que_scrb_addr,
dram_fail_over_mode, que_wr_entry_free, config_reg,
que_rank1_present, que_addr_bank_low_sel, que_eight_bank_mode,
que_mem_addr, dram_io_data_out, dram_io_addr, dram_io_bank,
dram_io_cas_l, dram_io_cke, dram_io_cs_l, dram_io_drive_data,
dram_io_drive_enable, dram_io_ras_l, dram_io_write_en_l,
dram_io_pad_enable, dram_io_clk_enable, dram_io_pad_clk_inv,
dram_io_ptr_clk_inv, dram_io_channel_disabled, que_l2if_ack_vld,
que_l2if_nack_vld, que_l2if_data, que_dram_clk_toggle,
dp_data_valid, que_l2if_send_info, dram_local_pt_opened_bank,
que_max_banks_open_valid, que_max_banks_open, que_max_time_valid,
que_int_wr_que_inv_info, que_ras_int_picked, que_b0_data_addr,
que_l2req_valids, que_b0_addr_picked, que_b0_id_picked,
que_b0_index_picked, que_b0_cmd_picked, que_channel_picked,
que_int_pos, que_channel_disabled, dp_data_mecc0, dp_data_mecc1,
dp_data_mecc2, dp_data_mecc3, dp_data_mecc4, dp_data_mecc5,
dp_data_mecc6, dp_data_mecc7, que_cas_int_picked,
que_wr_cas_ch01_picked, que_mux_write_en,
// Inputs
clk, rst_l, arst_l, sehold, l2if_que_selfrsh, dram_dbginit_l,
l2if_data_mecc0, l2if_data_mecc1, l2if_data_mecc2,
l2if_data_mecc3, l2if_data_mecc4, l2if_data_mecc5,
l2if_data_mecc6, l2if_data_mecc7, l2if_rd_id, l2if_rd_addr,
l2if_wr_addr, l2if_wr_req, l2if_rd_req, l2if_dbg_trig_en,
l2if_data_wr_addr, l2if_err_addr_reg, l2if_err_sts_reg,
l2if_err_loc, l2if_err_cnt, que_mem_data, io_dram_data_valid,
io_dram_data_in, io_dram_ecc_in, l2if_que_rd_req_vld,
l2if_que_wr_req_vld, l2if_que_addr, l2if_que_data,
l2if_scrb_data_en, l2if_scrb_data, l2if_scrb_ecc,
pt_ch_blk_new_openbank, pt_max_banks_open, pt_max_time,
ch0_que_ras_int_picked, ch0_que_b0_data_addr,
ch0_que_channel_picked, ch1_que_l2req_valids,
ch1_que_b0_addr_picked, ch1_que_b0_id_picked,
ch1_que_b0_index_picked, ch1_que_b0_cmd_picked,
other_que_channel_disabled, ch1_que_int_wr_que_inv_info,
other_que_pos, ch1_que_mem_data, ch1_dp_data_mecc0,
ch1_dp_data_mecc1, ch1_dp_data_mecc2, ch1_dp_data_mecc3,
ch1_dp_data_mecc4, ch1_dp_data_mecc5, ch1_dp_data_mecc6,
ch1_dp_data_mecc7, ch0_que_cas_int_picked,
ch0_que_wr_cas_ch01_picked, ch0_que_mux_write_en
);
input clk;
input rst_l;
input arst_l;
input sehold;
input l2if_que_selfrsh;
input dram_dbginit_l;
output [4:0] que_margin_reg;
// CPU CLK DOMAIN INTERFACE
input [3:0] l2if_data_mecc0;
input [3:0] l2if_data_mecc1;
input [3:0] l2if_data_mecc2;
input [3:0] l2if_data_mecc3;
input [3:0] l2if_data_mecc4;
input [3:0] l2if_data_mecc5;
input [3:0] l2if_data_mecc6;
input [3:0] l2if_data_mecc7;
input [2:0] l2if_rd_id;
input [35:0] l2if_rd_addr;
input [35:0] l2if_wr_addr;
input l2if_wr_req;
input l2if_rd_req;
input l2if_dbg_trig_en;
output readqbank0vld0;
output readqbank0vld1;
output readqbank0vld2;
output readqbank0vld3;
output writeqbank0vld0;
output writeqbank0vld1;
output writeqbank0vld2;
output writeqbank0vld3;
output readqbank0vld4;
output readqbank0vld5;
output readqbank0vld6;
output readqbank0vld7;
output writeqbank0vld4;
output writeqbank0vld5;
output writeqbank0vld6;
output writeqbank0vld7;
output que_wr_req;
output [255:0] dp_data_in;
output [31:0] dp_ecc_in;
input [2:0] l2if_data_wr_addr;
output [32:0] que_scrb_addr;
input [35:0] l2if_err_addr_reg;
input [22:0] l2if_err_sts_reg;
output dram_fail_over_mode;
output [3:0] que_wr_entry_free;
input [35:0] l2if_err_loc;
input [17:0] l2if_err_cnt;
output [8:0] config_reg;
output que_rank1_present;
output que_addr_bank_low_sel;
output que_eight_bank_mode;
// MEMORY INTERFACE
input [255:0] que_mem_data;
output [4:0] que_mem_addr;
// FROM THE PADS
input io_dram_data_valid;
input [255:0] io_dram_data_in;
input [31:0] io_dram_ecc_in;
// TO THE PADS
output [287:0] dram_io_data_out;
output [14:0] dram_io_addr;
output [2:0] dram_io_bank;
output dram_io_cas_l;
output dram_io_cke;
output [3:0] dram_io_cs_l;
output dram_io_drive_data;
output dram_io_drive_enable;
output dram_io_ras_l;
output dram_io_write_en_l;
output dram_io_pad_enable;
output dram_io_clk_enable;
output dram_io_pad_clk_inv;
output [4:0] dram_io_ptr_clk_inv;
output dram_io_channel_disabled;
// FROM L2if UCB
input l2if_que_rd_req_vld;
input l2if_que_wr_req_vld;
input [31:0] l2if_que_addr;
input [63:0] l2if_que_data;
// TO l2if UCB
output que_l2if_ack_vld;
output que_l2if_nack_vld;
output [63:0] que_l2if_data;
input l2if_scrb_data_en;
input [255:0] l2if_scrb_data;
input [33:0] l2if_scrb_ecc;
output que_dram_clk_toggle;
output dp_data_valid;
output [9:0] que_l2if_send_info;
// FROM POWER THROTTLE
output dram_local_pt_opened_bank;
output que_max_banks_open_valid;
output [16:0] que_max_banks_open;
output que_max_time_valid;
input pt_ch_blk_new_openbank;
input [16:0] pt_max_banks_open;
input [15:0] pt_max_time;
// NEW ADDITION DUE TO 2 CHANNEL MODE
input [7:0] ch0_que_ras_int_picked;
input [5:0] ch0_que_b0_data_addr;
input ch0_que_channel_picked;
input [7:0] ch1_que_l2req_valids;
input [35:0] ch1_que_b0_addr_picked;
input [2:0] ch1_que_b0_id_picked;
input [2:0] ch1_que_b0_index_picked;
input ch1_que_b0_cmd_picked;
input other_que_channel_disabled;
input [6:0] ch1_que_int_wr_que_inv_info;
input [4:0] other_que_pos;
output [6:0] que_int_wr_que_inv_info;
output [7:0] que_ras_int_picked;
output [5:0] que_b0_data_addr;
output [7:0] que_l2req_valids;
output [35:0] que_b0_addr_picked;
output [2:0] que_b0_id_picked;
output [2:0] que_b0_index_picked;
output que_b0_cmd_picked;
output que_channel_picked;
output [4:0] que_int_pos;
output que_channel_disabled;
input [255:0] ch1_que_mem_data;
input [3:0] ch1_dp_data_mecc0;
input [3:0] ch1_dp_data_mecc1;
input [3:0] ch1_dp_data_mecc2;
input [3:0] ch1_dp_data_mecc3;
input [3:0] ch1_dp_data_mecc4;
input [3:0] ch1_dp_data_mecc5;
input [3:0] ch1_dp_data_mecc6;
input [3:0] ch1_dp_data_mecc7;
output [3:0] dp_data_mecc0;
output [3:0] dp_data_mecc1;
output [3:0] dp_data_mecc2;
output [3:0] dp_data_mecc3;
output [3:0] dp_data_mecc4;
output [3:0] dp_data_mecc5;
output [3:0] dp_data_mecc6;
output [3:0] dp_data_mecc7;
// FOR PERF
input [7:0] ch0_que_cas_int_picked;
input ch0_que_wr_cas_ch01_picked;
input ch0_que_mux_write_en;
output [7:0] que_cas_int_picked;
output que_wr_cas_ch01_picked;
output que_mux_write_en;
//////////////////////////////////////////////////////////////////
// Wires
//////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [34:0] dram_fail_over_mask; // From dram_que of dram_que.v
wire err_inj_reg; // From dram_que of dram_que.v
wire [15:0] err_mask_reg; // From dram_que of dram_que.v
wire que_bypass_scrb_data; // From dram_que of dram_que.v
wire que_st_cmd_addr_parity; // From dram_que of dram_que.v
wire que_wr_channel_mux; // From dram_que of dram_que.v
// End of automatics
dram_que dram_que(/*AUTOINST*/
// Outputs
.sshot_err_reg(sshot_err_reg),
.que_margin_reg(que_margin_reg[4:0]),
.readqbank0vld0(readqbank0vld0),
.readqbank0vld1(readqbank0vld1),
.readqbank0vld2(readqbank0vld2),
.readqbank0vld3(readqbank0vld3),
.writeqbank0vld0(writeqbank0vld0),
.writeqbank0vld1(writeqbank0vld1),
.writeqbank0vld2(writeqbank0vld2),
.writeqbank0vld3(writeqbank0vld3),
.readqbank0vld4(readqbank0vld4),
.readqbank0vld5(readqbank0vld5),
.readqbank0vld6(readqbank0vld6),
.readqbank0vld7(readqbank0vld7),
.writeqbank0vld4(writeqbank0vld4),
.writeqbank0vld5(writeqbank0vld5),
.writeqbank0vld6(writeqbank0vld6),
.writeqbank0vld7(writeqbank0vld7),
.que_wr_req (que_wr_req),
.que_scrb_addr (que_scrb_addr[32:0]),
.dram_fail_over_mode(dram_fail_over_mode),
.que_wr_entry_free(que_wr_entry_free[3:0]),
.config_reg (config_reg[8:0]),
.que_rank1_present(que_rank1_present),
.que_addr_bank_low_sel(que_addr_bank_low_sel),
.dram_io_pad_enable(dram_io_pad_enable),
.dram_io_addr (dram_io_addr[14:0]),
.dram_io_bank (dram_io_bank[2:0]),
.dram_io_cs_l (dram_io_cs_l[3:0]),
.dram_io_ras_l (dram_io_ras_l),
.dram_io_cas_l (dram_io_cas_l),
.dram_io_cke (dram_io_cke),
.dram_io_write_en_l(dram_io_write_en_l),
.dram_io_drive_enable(dram_io_drive_enable),
.dram_io_drive_data(dram_io_drive_data),
.dram_io_clk_enable(dram_io_clk_enable),
.dram_io_pad_clk_inv(dram_io_pad_clk_inv),
.dram_io_ptr_clk_inv(dram_io_ptr_clk_inv[4:0]),
.dram_io_channel_disabled(dram_io_channel_disabled),
.dram_fail_over_mask(dram_fail_over_mask[34:0]),
.que_mem_addr (que_mem_addr[4:0]),
.que_bypass_scrb_data(que_bypass_scrb_data),
.que_l2if_ack_vld(que_l2if_ack_vld),
.que_l2if_nack_vld(que_l2if_nack_vld),
.que_l2if_data (que_l2if_data[63:0]),
.que_dram_clk_toggle(que_dram_clk_toggle),
.dram_local_pt_opened_bank(dram_local_pt_opened_bank),
.que_max_banks_open_valid(que_max_banks_open_valid),
.que_max_banks_open(que_max_banks_open[16:0]),
.que_max_time_valid(que_max_time_valid),
.err_inj_reg (err_inj_reg),
.err_mask_reg (err_mask_reg[15:0]),
.que_st_cmd_addr_parity(que_st_cmd_addr_parity),
.que_cas_int_picked(que_cas_int_picked[7:0]),
.que_wr_cas_ch01_picked(que_wr_cas_ch01_picked),
.que_mux_write_en(que_mux_write_en),
.que_l2if_send_info(que_l2if_send_info[9:0]),
.que_ras_int_picked(que_ras_int_picked[7:0]),
.que_b0_data_addr(que_b0_data_addr[5:0]),
.que_l2req_valids(que_l2req_valids[7:0]),
.que_b0_addr_picked(que_b0_addr_picked[35:0]),
.que_b0_id_picked(que_b0_id_picked[2:0]),
.que_b0_index_picked(que_b0_index_picked[2:0]),
.que_b0_cmd_picked(que_b0_cmd_picked),
.que_channel_picked(que_channel_picked),
.que_int_wr_que_inv_info(que_int_wr_que_inv_info[6:0]),
.que_int_pos (que_int_pos[4:0]),
.que_channel_disabled(que_channel_disabled),
.que_wr_channel_mux(que_wr_channel_mux),
.que_eight_bank_mode(que_eight_bank_mode),
// Inputs
.clk (clk),
.rst_l (rst_l),
.arst_l (arst_l),
.sehold (sehold),
.l2if_que_selfrsh(l2if_que_selfrsh),
.dram_dbginit_l(dram_dbginit_l),
.l2if_rd_id (l2if_rd_id[2:0]),
.l2if_rd_addr (l2if_rd_addr[35:0]),
.l2if_wr_addr (l2if_wr_addr[35:0]),
.l2if_wr_req (l2if_wr_req),
.l2if_rd_req (l2if_rd_req),
.l2if_que_rd_req_vld(l2if_que_rd_req_vld),
.l2if_que_wr_req_vld(l2if_que_wr_req_vld),
.l2if_que_addr (l2if_que_addr[31:0]),
.l2if_que_data (l2if_que_data[63:0]),
.pt_ch_blk_new_openbank(pt_ch_blk_new_openbank),
.pt_max_banks_open(pt_max_banks_open[16:0]),
.pt_max_time (pt_max_time[15:0]),
.l2if_data_wr_addr(l2if_data_wr_addr[2:0]),
.l2if_err_addr_reg(l2if_err_addr_reg[35:0]),
.l2if_err_sts_reg(l2if_err_sts_reg[22:0]),
.l2if_err_loc (l2if_err_loc[35:0]),
.l2if_err_cnt (l2if_err_cnt[17:0]),
.l2if_dbg_trig_en(l2if_dbg_trig_en),
.ch0_que_cas_int_picked(ch0_que_cas_int_picked[7:0]),
.ch0_que_wr_cas_ch01_picked(ch0_que_wr_cas_ch01_picked),
.ch0_que_mux_write_en(ch0_que_mux_write_en),
.ch0_que_ras_int_picked(ch0_que_ras_int_picked[7:0]),
.ch0_que_b0_data_addr(ch0_que_b0_data_addr[5:0]),
.ch0_que_channel_picked(ch0_que_channel_picked),
.ch1_que_l2req_valids(ch1_que_l2req_valids[7:0]),
.ch1_que_b0_addr_picked(ch1_que_b0_addr_picked[35:0]),
.ch1_que_b0_id_picked(ch1_que_b0_id_picked[2:0]),
.ch1_que_b0_index_picked(ch1_que_b0_index_picked[2:0]),
.ch1_que_b0_cmd_picked(ch1_que_b0_cmd_picked),
.other_que_channel_disabled(other_que_channel_disabled),
.other_que_pos (other_que_pos[4:0]),
.ch1_que_int_wr_que_inv_info(ch1_que_int_wr_que_inv_info[6:0]));
dram_dp dram_dp(/*AUTOINST*/
// Outputs
.dp_data_mecc0 (dp_data_mecc0[3:0]),
.dp_data_mecc1 (dp_data_mecc1[3:0]),
.dp_data_mecc2 (dp_data_mecc2[3:0]),
.dp_data_mecc3 (dp_data_mecc3[3:0]),
.dp_data_mecc4 (dp_data_mecc4[3:0]),
.dp_data_mecc5 (dp_data_mecc5[3:0]),
.dp_data_mecc6 (dp_data_mecc6[3:0]),
.dp_data_mecc7 (dp_data_mecc7[3:0]),
.dram_io_data_out(dram_io_data_out[287:0]),
.dp_data_in (dp_data_in[255:0]),
.dp_ecc_in (dp_ecc_in[31:0]),
.dp_data_valid (dp_data_valid),
// Inputs
.clk (clk),
.rst_l (rst_l),
.l2if_data_mecc0(l2if_data_mecc0[3:0]),
.l2if_data_mecc1(l2if_data_mecc1[3:0]),
.l2if_data_mecc2(l2if_data_mecc2[3:0]),
.l2if_data_mecc3(l2if_data_mecc3[3:0]),
.l2if_data_mecc4(l2if_data_mecc4[3:0]),
.l2if_data_mecc5(l2if_data_mecc5[3:0]),
.l2if_data_mecc6(l2if_data_mecc6[3:0]),
.l2if_data_mecc7(l2if_data_mecc7[3:0]),
.io_dram_data_in(io_dram_data_in[255:0]),
.io_dram_ecc_in (io_dram_ecc_in[31:0]),
.io_dram_data_valid(io_dram_data_valid),
.que_bypass_scrb_data(que_bypass_scrb_data),
.que_mem_addr (que_mem_addr[4:0]),
.que_mem_data (que_mem_data[255:0]),
.que_st_cmd_addr_parity(que_st_cmd_addr_parity),
.que_channel_disabled(que_channel_disabled),
.dram_fail_over_mask(dram_fail_over_mask[34:0]),
.l2if_scrb_data_en(l2if_scrb_data_en),
.l2if_scrb_data (l2if_scrb_data[255:0]),
.l2if_scrb_ecc (l2if_scrb_ecc[33:0]),
.err_inj_reg (err_inj_reg),
.err_mask_reg (err_mask_reg[15:0]),
.que_wr_channel_mux(que_wr_channel_mux),
.ch1_que_mem_data(ch1_que_mem_data[255:0]),
.ch1_dp_data_mecc0(ch1_dp_data_mecc0[3:0]),
.ch1_dp_data_mecc1(ch1_dp_data_mecc1[3:0]),
.ch1_dp_data_mecc2(ch1_dp_data_mecc2[3:0]),
.ch1_dp_data_mecc3(ch1_dp_data_mecc3[3:0]),
.ch1_dp_data_mecc4(ch1_dp_data_mecc4[3:0]),
.ch1_dp_data_mecc5(ch1_dp_data_mecc5[3:0]),
.ch1_dp_data_mecc6(ch1_dp_data_mecc6[3:0]),
.ch1_dp_data_mecc7(ch1_dp_data_mecc7[3:0]),
.sshot_err_reg(sshot_err_reg));
endmodule // dram_dctl
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gclk_inv_r90_192x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_gclk_inv_r90_192x.behV
// --------------------------------------------------
//
module bw_clk_gclk_inv_r90_192x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_V |
`timescale 1 ns / 1 ps
module counter_group
(
input selector,
input incrementor,
input reverse,
input clr,
input wire [15:0]cntr_def_0,
input wire [15:0]cntr_def_1,
input wire [15:0]cntr_def_2,
input wire [15:0]cntr_def_3,
input wire [15:0]cntr_def_4,
input wire [15:0]cntr_def_5,
input wire [15:0]cntr_def_6,
input wire [15:0]cntr_def_7,
output wire [15:0]cntr0,
output wire [15:0]cntr1,
output wire [15:0]cntr2,
output wire [15:0]cntr3,
output wire [15:0]cntr4,
output wire [15:0]cntr5,
output wire [15:0]cntr6,
output wire [15:0]cntr7,
output wire [15:0]cntr_sel,
output reg [7:0]cntr_ind
);
reg [2:0] cntr_cur;
reg [15:0] cntrs[7:0];
assign cntr0 = cntrs[0];
assign cntr1 = cntrs[1];
assign cntr2 = cntrs[2];
assign cntr3 = cntrs[3];
assign cntr4 = cntrs[4];
assign cntr5 = cntrs[5];
assign cntr6 = cntrs[6];
assign cntr7 = cntrs[7];
wire [15:0] cntrs_def_int[7:0];
assign cntrs_def_int[0] = cntr_def_0;
assign cntrs_def_int[1] = cntr_def_1;
assign cntrs_def_int[2] = cntr_def_2;
assign cntrs_def_int[3] = cntr_def_3;
assign cntrs_def_int[4] = cntr_def_4;
assign cntrs_def_int[5] = cntr_def_5;
assign cntrs_def_int[6] = cntr_def_6;
assign cntrs_def_int[7] = cntr_def_7;
assign cntr_sel = cntrs[cntr_cur];
wire s = selector | clr | incrementor;
always @(posedge s) begin
if (clr == 1) begin
/* cntrs[cntr_cur] <= 0; */
cntrs[cntr_cur] <= cntrs_def_int[cntr_cur];
end else if (selector == 1) begin
if (reverse == 1)
cntr_cur <= cntr_cur - 1;
else
cntr_cur <= cntr_cur + 1;
end else begin
if (reverse == 1)
cntrs[cntr_cur] <= cntrs[cntr_cur] - 1;
else
cntrs[cntr_cur] <= cntrs[cntr_cur] + 1;
end
end
always @(cntr_cur) begin
case(cntr_cur)
0: cntr_ind <= 8'H01;
1: cntr_ind <= 8'H02;
2: cntr_ind <= 8'H04;
3: cntr_ind <= 8'H08;
4: cntr_ind <= 8'H10;
5: cntr_ind <= 8'H20;
6: cntr_ind <= 8'H40;
7: cntr_ind <= 8'H80;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_V |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(*i $Id: Decidable.v 13323 2010-07-24 15:57:30Z herbelin $ i*)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
interface my_interface ();
logic [2:0] out2;
logic [2:0] out3;
endinterface: my_interface
module foobar (input [2:0] in2, output [2:0] out2);
endmodule
module foo_autowire_fails (my_interface itf);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] out2; // From foobar0 of foobar.v
// End of automatics
assign itf.out2 = out2; // perhaps a namespace collision?
foobar foobar0
(/*AUTOINST*/
// Outputs
.out2 (out2[2:0]),
// Inputs
.in2 (in2[2:0]));
endmodule
module foo_autowire_works (my_interface itf);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] out2; // From foobar0 of foobar.v
// End of automatics
assign itf.out3 = out2;
foobar foobar0
(/*AUTOINST*/
// Outputs
.out2 (out2[2:0]),
// Inputs
.in2 (in2[2:0]));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_V |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: capture_fifo.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module capture_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [4:0] rdusedw;
output wrempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 5 0 OUTPUT NODEFVAL "rdusedw[4..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 5 0 @rdusedw 0 0 5 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL capture_fifo_bb.v TRUE
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool(cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)] | no
- [d mumble (b a 5)] | yes
- [d bool (b a 5)] | yes
- [e bool true] | yes
- [e mumble (b c 0)] | yes
- [e bool (b c 0)] | no
- [c] | no
[] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
none.
[] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** If fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
Check ([3 + 4] ++ nil).
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
match count with
| 0 => nil
| S p => n :: repeat n p
end.
Example test_repeat1:
repeat true 2 = cons true (cons true nil). reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof. reflexivity. Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros X v s.
induction s as [|h t].
Case "nil". reflexivity.
Case "h :: t". simpl. rewrite IHt. reflexivity.
Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros X l.
induction l as [|h t].
Case "nil". reflexivity.
Case "h :: t". simpl. rewrite rev_snoc. rewrite IHt. reflexivity.
Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros X l1 l2 v.
induction l1 as [|h t].
Case "nil". reflexivity.
Case "h :: t".
simpl. rewrite IHt. reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print? []
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| [] => (nil, nil)
| (x,y) :: t => (x :: fst (split t), y :: snd (split t))
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
(* FILL IN HERE *) admit.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
(* FILL IN HERE *) Admitted.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : forall _ : X, forall _ : Y, Z) (p : X * Y) : Z := f (fst p) (snd p).
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
intros. reflexivity.
Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros. destruct p. reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 : forall (_ : list nat), list nat :=
filter (fun x => andb (ble_nat 8 x) (evenb x)).
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8]. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = []. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter test l, filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_snoc :
forall (X Y : Type) (f : X -> Y) (l : list X) (z : X),
map f (snoc l z) = snoc (map f l) (f z).
Proof.
intros.
induction l as [|h t].
Case "nil". reflexivity.
Case "h :: t".
simpl. rewrite IHt. reflexivity.
Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros X Y f l.
induction l as [|h t].
Case "[]". reflexivity.
Case "h :: t". simpl. rewrite map_snoc. rewrite IHt. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
match l with
| nil => nil
| x :: t => f x ++ flat_map f t
end.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* For implementing map using fold. *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof. reflexivity. Qed.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros.
unfold override.
rewrite H0. rewrite H. reflexivity.
Qed.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
intros.
induction l as [|h t].
Case "[]". reflexivity.
Case "h :: t".
unfold fold_length. simpl. fold (fold_length t).
rewrite IHt. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun e acc => f e :: acc) l [].
(** Write down a theorem in Coq stating that [fold_map] is correct,
and prove it. *)
Theorem fold_map_correct :
forall (X Y : Type) (l : list X) (f : X -> Y),
fold_map f l = map f l.
Proof.
intros.
induction l as [|h t].
Case "[]". reflexivity.
Case "h :: t". unfold fold_map. simpl. fold (fold_map f t). rewrite IHt. reflexivity.
Qed.
(** [] *)
(* $Date: 2013-09-26 14:40:26 -0400 (Thu, 26 Sep 2013) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__EDFXBP_PP_BLACKBOX_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__TAP_BLACKBOX_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAP_BLACKBOX_V
|
`timescale 1ns / 1ps
// Modified by: Adam Michael, CM1884
// Mohammad Almisbaa, CM2060
// Date: November 5, 2015
// Summary: This is just a square wave generator.
//File: CRTClockTemplate.v
//Generate 25MHz VGA clock from a SystemClock
//SystemClockFreq and CRTClockFreq are input parameters in MHz
//ECE333 Fall 2015
//Term Project on Pong game on VGA
//this is a template to be completed by students
module CRTClock(SystemClockFreq, CRTClockFreq, PixelClock, Reset, Clock);
parameter SystemClockSize=10;
input [SystemClockSize-1:0] SystemClockFreq;
input [SystemClockSize-1:0] CRTClockFreq;
output PixelClock;
input Reset;
input Clock;
reg [SystemClockSize-1:0] counter;
wire [SystemClockSize-1:0] MaxCounter;
assign MaxCounter = (SystemClockFreq / CRTClockFreq) - 1;
assign PixelClock = counter > (MaxCounter >> 1);
always @ (posedge Clock or posedge Reset)
if (Reset) counter <= 0;
else begin
if (counter == MaxCounter) counter <= 0;
else counter <= counter + 1'd1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hd__dlxtn (
Q ,
D ,
GATE_N
);
// Module ports
output Q ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q;
// Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V |
// soc_system_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module soc_system_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
soc_system_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXTP_1_V
`define SKY130_FD_SC_HS__SEDFXTP_1_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_1 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxtp_1 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXTP_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9122 (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
// master/slave
dac_sync_out,
dac_sync_in,
// dma interface
dac_div_clk,
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
// master/slave
output dac_sync_out;
input dac_sync_in;
// dma interface
output dac_div_clk;
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire mmcm_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire dac_frame_i0_s;
wire [15:0] dac_data_i0_s;
wire dac_frame_i1_s;
wire [15:0] dac_data_i1_s;
wire dac_frame_i2_s;
wire [15:0] dac_data_i2_s;
wire dac_frame_i3_s;
wire [15:0] dac_data_i3_s;
wire dac_frame_q0_s;
wire [15:0] dac_data_q0_s;
wire dac_frame_q1_s;
wire [15:0] dac_data_q1_s;
wire dac_frame_q2_s;
wire [15:0] dac_data_q2_s;
wire dac_frame_q3_s;
wire [15:0] dac_data_q3_s;
wire dac_status_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// device interface
axi_ad9122_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_SERDES_DDR_N (PCORE_SERDES_DDR_N),
.PCORE_MMCM_BUFIO_N (PCORE_MMCM_BUFIO_N))
i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_rst (dac_rst),
.dac_clk (),
.dac_div_clk (dac_div_clk),
.dac_status (dac_status_s),
.dac_frame_i0 (dac_frame_i0_s),
.dac_data_i0 (dac_data_i0_s),
.dac_frame_i1 (dac_frame_i1_s),
.dac_data_i1 (dac_data_i1_s),
.dac_frame_i2 (dac_frame_i2_s),
.dac_data_i2 (dac_data_i2_s),
.dac_frame_i3 (dac_frame_i3_s),
.dac_data_i3 (dac_data_i3_s),
.dac_frame_q0 (dac_frame_q0_s),
.dac_data_q0 (dac_data_q0_s),
.dac_frame_q1 (dac_frame_q1_s),
.dac_data_q1 (dac_data_q1_s),
.dac_frame_q2 (dac_frame_q2_s),
.dac_data_q2 (dac_data_q2_s),
.dac_frame_q3 (dac_frame_q3_s),
.dac_data_q3 (dac_data_q3_s),
.mmcm_rst (mmcm_rst),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s));
// core
axi_ad9122_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_frame_i0 (dac_frame_i0_s),
.dac_data_i0 (dac_data_i0_s),
.dac_frame_i1 (dac_frame_i1_s),
.dac_data_i1 (dac_data_i1_s),
.dac_frame_i2 (dac_frame_i2_s),
.dac_data_i2 (dac_data_i2_s),
.dac_frame_i3 (dac_frame_i3_s),
.dac_data_i3 (dac_data_i3_s),
.dac_frame_q0 (dac_frame_q0_s),
.dac_data_q0 (dac_data_q0_s),
.dac_frame_q1 (dac_frame_q1_s),
.dac_data_q1 (dac_data_q1_s),
.dac_frame_q2 (dac_frame_q2_s),
.dac_data_q2 (dac_data_q2_s),
.dac_frame_q3 (dac_frame_q3_s),
.dac_data_q3 (dac_data_q3_s),
.dac_status (dac_status_s),
.dac_sync_out (dac_sync_out),
.dac_sync_in (dac_sync_in),
.dac_valid_0 (dac_valid_0),
.dac_enable_0 (dac_enable_0),
.dac_ddata_0 (dac_ddata_0),
.dac_valid_1 (dac_valid_1),
.dac_enable_1 (dac_enable_1),
.dac_ddata_1 (dac_ddata_1),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.mmcm_rst (mmcm_rst),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKINV_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module fft32( CLK ,RST ,ED ,START ,DReal ,DImag ,RDY ,DOReal ,DOImag, ifft ); //Add overflow , check weather shift & ADDR is needed
parameter total_bits = 32;
input CLK;
input RST;
input ED;
input START;
input ifft;
input [total_bits-1:0] DReal;
input [total_bits-1:0] DImag;
output reg RDY;
output [total_bits-1:0] DOReal;
output [total_bits-1:0] DOImag;
wire [total_bits-1:0] dr1;
wire [total_bits-1:0] di1;
wire [total_bits+3:0] dr2;
wire [total_bits+3:0] di2;
wire [total_bits-1:0] dr3;
wire [total_bits-1:0] di3;
wire [total_bits-1:0] dr4;
wire [total_bits-1:0] di4;
wire rdy1,rdy2,rdy3;
wire [3:0] ADDR;
reg [5:0] AR;
assign ADDR = AR[3:0];
initial
AR<=0;
RAM1 #(total_bits) ram_1(.CLK(CLK),.RST(RST),.ED(ED),.START(START),.DReal(DReal),.DImag(DImag),.RDY(rdy1),.DOReal(dr1),.DOImag(di1));
fft16 #(total_bits) fft_16(.ED(ED),.RST(RST),.CLK(CLK),.START(rdy1),.ifft(ifft),.DIImag(di1),.DIReal(dr1),.DOImag(di2),.DOReal(dr2),.RDY(rdy2));
weight #(total_bits) wcalc(.CLK(CLK) ,.RST(RST),.ED(ED),.START(rdy2),.DReal(dr2[total_bits-1:0]),.DImag(di2[total_bits-1:0]),.DOReal(dr3),.DOImag(di3),.RDY(rdy3));
odd_RAM #(total_bits) oram(.CLK(CLK),.RST(RST),.ED(ED),.START(rdy2),.ADDR(ADDR),.DReal(dr2[total_bits-1:0]),.DImag(di2[total_bits-1:0]),.DOReal(dr4),.DOImag(di4));
reg [total_bits-1:0] data_ra[0:15];
reg [total_bits-1:0] data_im[0:15];
reg [1:0] state;
reg [total_bits-1:0] ra;
reg [total_bits-1:0] im;
assign DOReal = ra;
assign DOImag = im;
always@(posedge CLK)begin
if(RST) begin
AR<=32;
state<=0;
end
else if(rdy3) begin
AR<=0;
state<=1;
end
else if(ED)begin
RDY<=0;
if(state==1) begin //Check for overflow
ra<=dr4 + dr3;
im<=di4 + di3;
data_ra[AR[3:0]] <= dr4 - dr3;
data_im[AR[3:0]] <= di4 - di3;
end
else if(state==2) begin
ra <= data_ra[AR[3:0]];
im <= data_im[AR[3:0]];
end
if(AR==15)
state<=2;
if(AR<32)
AR<=AR+1;
if(AR==0&&state==1)
RDY<=1;
end
end
endmodule
|
/*
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
`include "config.vh"
module iddr_wrap(input c, input i, output[1:0] o);
`ifdef X7SERIES
IDDR #(.DDR_CLK_EDGE("SAME_EDGE"), .SRTYPE("ASYNC")) IDDR_i
(.Q1(o[0]), .Q2(o[1]),
.C(c),
.CE(1'b1),
.D(i),
.R(1'b0), .S(1'b0));
`else
IDDR2 #(.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) IDDR2_i
(.Q0(o[0]), .Q1(o[1]),
.C0(c), .C1(~c),
.CE(1'b1),
.D(i),
.R(1'b0), .S(1'b0)
);
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SRDLSTP_BEHAVIORAL_V
/**
* srdlstp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_psa_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srdlstp (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B
);
// Module ports
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire reset_delayed;
wire SET_B_delayed;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$PSa_pp$PKG$sN dlatch0 (buf_Q , D_delayed, GATE_delayed, SET_B_delayed, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b1 );
assign cond0 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B === 1'b1 ) );
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_BEHAVIORAL_V |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : des_top.v
// File : Drawing Engine Setup top.
// Author : Jim MacLeod
// Created : 01-Dec-2012
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module des_top
(
input se_clk, // setup engine clock.
input se_rstn, // setup engine reset.
input go_sup, // Start setup engine.
input color_mode_15, // Color Mode 0 = 8888, 1 = float.
input solid_2,
input [1:0] stpl_2, // [1:0]
input stpl_pk_1,
input apat32_2,
input nlst_2, // No last for 3D line.
input l3_fg_bgn, // From Line pattern register.
input mw_fip,
input pipe_busy,
input mcrdy,
input load_actv_3d,
// Vertex Buffer Interface.
input [351:0] vertex0_15,
input [351:0] vertex1_15,
input [351:0] vertex2_15,
input rect_15, // Rectangular Mode.
input line_3d_actv_15,
input bce_15, // Back face culling enable.
input bc_pol_15, // Back face culling polarity.
// Post setup parameters.
input [31:0] c3d_2, // 3D Command Register.
input [31:0] tex_2, // Texture Command Register.
input [31:0] hith_2, // Hither.
input [31:0] yon_2, // Yon.
input [2:0] clp_2, // Clip Control.
input [31:0] clptl_2, // Clip Top Left.
input [31:0] clpbr_2, // Clip Bottom Right.
output [7:0] tri_wrt, // [7:0]
output [31:0] tri_dout, // [31:0]
output sup_done, // Load active triangle command.
output abort_cmd, // If ns1 and ns2 = 0 abort command.
output last_pixel,
output msk_last_pixel,
output valid_z_col_spec, // Z, Color, and Specular are valid.
output [15:0] current_x,
output [15:0] current_y,
output [31:0] current_z,
output [31:0] current_argb,
output [23:0] current_spec,
output [7:0] current_fog,
output clip_xy,
output clip_uv,
output current_fg_bgn, // Pattern.
output valid_uv, // Z, Color, and Specular are valid.
output [19:0] current_u,
output [19:0] current_v,
output [8:0] current_bit_mask_x,
output [8:0] current_bit_mask_y,
output current_exact,
output [3:0] lod_num,
output [5:0] lod_gamma,
// Back to line pattern register.
output l3_incpat
);
`include "define_3d.h"
wire [15:0] l3_cpx0; // Line 3D destination x
wire [15:0] l3_cpy0; // Line 3D destination y
wire [15:0] l3_cpx1; // Line 3D source x
wire [15:0] l3_cpy1; // Line 3D source y
wire fg_bgn; // Pattern.
wire [447:0] vertex0;
wire [447:0] vertex1;
wire [447:0] vertex2;
wire [95:0] cmp_z_fp;
wire [95:0] cmp_w_fp;
wire [95:0] cmp_uw_fp;
wire [95:0] cmp_vw_fp;
wire [95:0] cmp_a_fp;
wire [95:0] cmp_r_fp;
wire [95:0] cmp_g_fp;
wire [95:0] cmp_b_fp;
wire [95:0] cmp_f_fp;
wire [95:0] cmp_rs_fp;
wire [95:0] cmp_gs_fp;
wire [95:0] cmp_bs_fp;
wire scan_dir; // Scan direction.
wire scan_dir_2; // Scan direction.
wire y_major_15; // Y major.
wire ns1_eqz_15; // Number of scan lines edge one equals zero.
wire ns2_eqz_15; // Number of scan lines edge two equals zero.
wire ld_frag; // Load Fragment from Execution Unit.
wire t3_pixreq;
wire l3_pixreq;
wire last_frag;
wire t3_last_frag;
wire l3_last_pixel;
wire msk_last_frag;
wire t3_msk_last_frag;
wire l3_pc_msk_last;
wire l3_active;
wire [15:0] current_x_fx; // Current X position from Execution Unit.
wire [15:0] current_y_fx; // Current Y position from Execution Unit.
wire [15:0] t3_cpx; // Current X position from triangle SM.
wire [15:0] t3_cpy; // Current Y position from triangle SM.
wire [15:0] l3_cpx; // Current X position from 3D Line SM.
wire [15:0] l3_cpy; // Current Y position from 3D Line SM.
wire [23:0] y0f; // Y0 fraction.
wire [23:0] y1f; // Y1 fraction.
wire [23:0] y2f; // Y2 fraction.
wire y1f_lt_y0f; // Y1 fraction is less than Y0 fraction.
wire y2f_lt_y0f; // Y1 fraction is less than Y0 fraction.
wire [2:0] ystat;
wire ymajor_15; // Y1 fraction is less than Y0 fraction.
wire [31:0] start_x_fp_2;
wire [31:0] start_y_fp_2;
wire [31:0] end_x_fp_2;
wire [31:0] end_y_fp_2;
assign y1f_lt_y0f = y1f < y0f;
assign y2f_lt_y0f = y2f < y0f;
assign ystat[0] = |y0f;
assign ystat[1] = |y1f;
assign ystat[2] = |y2f;
// Vertex 0.
assign vertex0`VXW = flt_snap_x(vertex0_15`VXW); // Snap to 1/16.
assign {y0f, vertex0`VYW} = flt_snap_y(vertex0_15`VYW); // Snap to 1/16.
// assign vertex0`VXW = vertex0_15`VXW; // No Snap
// assign vertex0`VYW = vertex0_15`VYW; // No Snap
// assign y0f = flt_frac(vertex0`VYW);
//
assign vertex0`VZW = vertex0_15`VZW;
assign vertex0`VWW = vertex0_15`VWW;
assign vertex0`VUW = vertex0_15`VUW;
assign vertex0`VVW = vertex0_15`VVW;
// Vertex 1.
assign vertex1`VXW = flt_snap_x(vertex1_15`VXW); // Snap to 1/16.
assign {y1f, vertex1`VYW} = flt_snap_y(vertex1_15`VYW); // Snap to 1/16.
// assign vertex1`VXW = vertex1_15`VXW; // No Snap
// assign vertex1`VYW = vertex1_15`VYW; // No Snap
// assign y1f = flt_frac(vertex1`VYW);
//
assign vertex1`VZW = vertex1_15`VZW;
assign vertex1`VWW = vertex1_15`VWW;
assign vertex1`VUW = vertex1_15`VUW;
assign vertex1`VVW = vertex1_15`VVW;
// Vertex 2.
assign vertex2`VXW = flt_snap_x(vertex2_15`VXW); // Snap to 1/16.
assign {y2f, vertex2`VYW} = flt_snap_y(vertex2_15`VYW); // Snap to 1/16.
// assign vertex2`VXW = vertex2_15`VXW; // No Snap
// assign vertex2`VYW = vertex2_15`VYW; // No Snap
// assign y2f = flt_frac(vertex2`VYW);
//
assign vertex2`VZW = vertex2_15`VZW;
assign vertex2`VWW = vertex2_15`VWW;
assign vertex2`VUW = vertex2_15`VUW;
assign vertex2`VVW = vertex2_15`VVW;
/*****************SWAPS FOR 3D LINES*********************************/
// assign p1x_fp = (line_3d_actv_15) ? p0x_fp : p1xi_fp;
// assign p1y_fp = (line_3d_actv_15) ? p2y_fp : p1yi_fp;
//////////////////////////////////////////////////////////////////
// Alpha, Red, Green, and Blue, Can be INT or Float. (T2R4 compatible).
assign vertex0`VAW = color_2_flt(2'b00, color_mode_15, vertex0_15`VAW);
assign vertex0`VRW = color_2_flt(2'b00, color_mode_15, vertex0_15`VRW);
assign vertex0`VGW = color_2_flt(2'b00, color_mode_15, vertex0_15`VGW);
assign vertex0`VBW = color_2_flt(2'b00, color_mode_15, vertex0_15`VBW);
assign vertex1`VAW = color_2_flt(2'b00, color_mode_15, vertex1_15`VAW);
assign vertex1`VRW = color_2_flt(2'b00, color_mode_15, vertex1_15`VRW);
assign vertex1`VGW = color_2_flt(2'b00, color_mode_15, vertex1_15`VGW);
assign vertex1`VBW = color_2_flt(2'b00, color_mode_15, vertex1_15`VBW);
assign vertex2`VAW = color_2_flt(2'b00, color_mode_15, vertex2_15`VAW);
assign vertex2`VRW = color_2_flt(2'b00, color_mode_15, vertex2_15`VRW);
assign vertex2`VGW = color_2_flt(2'b00, color_mode_15, vertex2_15`VGW);
assign vertex2`VBW = color_2_flt(2'b00, color_mode_15, vertex2_15`VBW);
// Fog, Rs, Gs, and Bs, are always INT for now (T2R4 compatible).
assign vertex0`VFW = color_2_flt(2'b11, 1'b0, vertex0_15`VSW);
assign vertex0`VRSW = color_2_flt(2'b10, 1'b0, vertex0_15`VSW);
assign vertex0`VGSW = color_2_flt(2'b01, 1'b0, vertex0_15`VSW);
assign vertex0`VBSW = color_2_flt(2'b00, 1'b0, vertex0_15`VSW);
assign vertex1`VFW = color_2_flt(2'b11, 1'b0, vertex1_15`VSW);
assign vertex1`VRSW = color_2_flt(2'b10, 1'b0, vertex1_15`VSW);
assign vertex1`VGSW = color_2_flt(2'b01, 1'b0, vertex1_15`VSW);
assign vertex1`VBSW = color_2_flt(2'b00, 1'b0, vertex1_15`VSW);
assign vertex2`VFW = color_2_flt(2'b11, 1'b0, vertex2_15`VSW);
assign vertex2`VRSW = color_2_flt(2'b10, 1'b0, vertex2_15`VSW);
assign vertex2`VGSW = color_2_flt(2'b01, 1'b0, vertex2_15`VSW);
assign vertex2`VBSW = color_2_flt(2'b00, 1'b0, vertex2_15`VSW);
wire co_linear;
wire det_eqz;
wire cull;
wire [29:0] ldg;
wire [2:0] lds;
wire [5:0] se_cstate;
wire [31:0] grad;
wire [31:0] spac;
wire [31:0] ns1_fp;
wire [31:0] ns2_fp;
wire [31:0] spy_fp;
wire [255:0] spac_bus_2; // Setup engine spacial bus.
wire line_actv_3d;
/***********************NOTES**********************************
NOTE 1:
U and V are multiplied by W in the register input stage.
There for there must be a valid W in the chip for the current
point being written befor you can write U and V.
NOTE 2:
All input values are with the "_fp" sufix are IEEE single
percision floating point.
**************************************************************/
/*********************MODULES***********************/
des_grad u_des_grad
(
.se_clk (se_clk),
.se_rstn (se_rstn),
.se_cstate (se_cstate),
.vertex0 (vertex0),
.vertex1 (vertex1),
.vertex2 (vertex2),
.rect_15 (rect_15),
.line_3d_actv_15 (line_3d_actv_15),
.bce_15 (bce_15),
.bc_pol_15 (bc_pol_15),
// Outputs.
.ldg (ldg),
.grad (grad),
.lds (lds),
.spac (spac),
.scan_dir (scan_dir),
.co_linear (co_linear),
.det_eqz (det_eqz),
.cull (cull),
.ns1_fp (ns1_fp),
.ns2_fp (ns2_fp),
.spy_fp (spy_fp)
);
/********************/
des_reg u_des_reg
(
.se_clk (se_clk),
.se_rstn (se_rstn),
.load_actv_3d (load_actv_3d),
.scan_dir (scan_dir),
.line_3d_actv_15 (line_3d_actv_15),
.ldg (ldg),
.grad (grad),
.lds (lds),
.spac (spac),
.ystat ({y2f_lt_y0f, y1f_lt_y0f, ystat}),
.v0x (vertex0`VXW),
.v0y (vertex0`VYW),
.v0z (vertex0`VZW),
.v0w (vertex0`VWW),
.v0uw (vertex0`VUW),
.v0vw (vertex0`VVW),
.v0a (vertex0`VAW),
.v0r (vertex0`VRW),
.v0g (vertex0`VGW),
.v0b (vertex0`VBW),
.v0f (vertex0`VFW),
.v0rs (vertex0`VRSW),
.v0gs (vertex0`VGSW),
.v0bs (vertex0`VBSW),
.ns1_fp (ns1_fp),
.ns2_fp (ns2_fp),
.spy_fp (spy_fp),
.v2x (vertex2`VXW),
.v2y (vertex2`VYW),
// Outputs.
.line_actv_3d (line_actv_3d),
.spac_bus_2 (spac_bus_2),
.cmp_z_fp (cmp_z_fp),
.cmp_w_fp (cmp_w_fp),
.cmp_uw_fp (cmp_uw_fp),
.cmp_vw_fp (cmp_vw_fp),
.cmp_a_fp (cmp_a_fp),
.cmp_r_fp (cmp_r_fp),
.cmp_g_fp (cmp_g_fp),
.cmp_b_fp (cmp_b_fp),
.cmp_f_fp (cmp_f_fp),
.cmp_rs_fp (cmp_rs_fp),
.cmp_gs_fp (cmp_gs_fp),
.cmp_bs_fp (cmp_bs_fp),
.ns1_eqz_15 (ns1_eqz_15),
.ns2_eqz_15 (ns2_eqz_15),
.scan_dir_2 (scan_dir_2),
.start_x_fp_2 (start_x_fp_2),
.start_y_fp_2 (start_y_fp_2),
.end_x_fp_2 (end_x_fp_2),
.end_y_fp_2 (end_y_fp_2)
);
des_state u_des_state
(
// Inputs.
.se_clk (se_clk),
.se_rstn (se_rstn),
.go_sup (go_sup),
.line_3d_actv_15 (line_3d_actv_15),
.ns1_eqz (ns1_eqz_15),
.ns2_eqz (ns2_eqz_15),
.co_linear (co_linear),
.det_eqz (det_eqz),
.cull (cull),
// Outputs.
.sup_done (sup_done),
.abort_cmd (abort_cmd),
.se_cstate (se_cstate)
);
//
// Triangle Scan converting statemachine.
//
des_smtri u_des_smtri
(
.de_clk (se_clk),
.de_rstn (se_rstn),
.load_actv_3d (load_actv_3d),
.line_actv_3d (line_actv_3d),
.scan_dir_2 (scan_dir_2),
.stpl_2 (stpl_2), // [1:0]
.stpl_pk_1 (stpl_pk_1),
.apat32_2 (apat32_2),
.mw_fip (mw_fip),
.pipe_busy (pipe_busy),
.mcrdy (mcrdy),
.spac_bus (spac_bus_2), // [255:0]
.t3_pixreq (t3_pixreq),
.t3_last_pixel (t3_last_frag),
.t3_msk_last (t3_msk_last_frag),
.cpx (t3_cpx), // [15:0]
.cpy (t3_cpy), // [15:0]
.tri_wrt (tri_wrt), // [7:0]
.tri_dout (tri_dout) // [31:0]
);
//
// 3D Line statemachine.
//
des_smline_3d u_des_smline_3d
(
.de_clk (se_clk),
.de_rstn (se_rstn),
.load_actv_3d (load_actv_3d),
.line_actv_3d (line_actv_3d),
.nlst_2 (nlst_2),
.cpx0 (l3_cpx0),
.cpy0 (l3_cpy0),
.cpx1 (l3_cpx1),
.cpy1 (l3_cpy1),
.pipe_busy (pipe_busy),
.l_pixreq (l3_pixreq),
.l_last_pixel (l3_last_pixel),
.l_pc_msk_last (l3_pc_msk_last),
.cpx (l3_cpx),
.cpy (l3_cpy),
.l_incpat (l3_incpat), // Goes back to the line pattern reg.
.l_active (l3_active) // 3D line is active.
);
//
// Multiplex the fragments between line and triangle.
//
assign ld_frag = t3_pixreq | l3_pixreq;
assign last_frag = t3_last_frag | l3_last_pixel;
assign msk_last_frag = t3_msk_last_frag | l3_pc_msk_last;
assign current_x_fx = (l3_active) ? l3_cpx : t3_cpx;
assign current_y_fx = (l3_active) ? l3_cpy : t3_cpy;
assign fg_bgn = (l3_active) ? l3_fg_bgn : 1'b1;
//
// Fragment Generater.
//
des_frag_gen u_des_frag_gen
(
// Inputs.
.clk (se_clk),
.rstn (se_rstn),
.ld_frag (ld_frag),
.last_frag (last_frag),
.msk_last_frag (msk_last_frag),
.scan_dir_2 (scan_dir_2),
.clp_2 (clp_2),
.clptl_2 (clptl_2),
.clpbr_2 (clpbr_2),
.tex_2 (tex_2),
.c3d_2 (c3d_2),
.start_x_fp_2 (start_x_fp_2),
.start_y_fp_2 (start_y_fp_2),
.end_x_fp_2 (end_x_fp_2),
.end_y_fp_2 (end_y_fp_2),
.current_x_fx (current_x_fx),
.current_y_fx (current_y_fx),
.z_cmp_fp (cmp_z_fp),
.w_cmp_fp (cmp_w_fp),
.uw_cmp_fp (cmp_uw_fp),
.vw_cmp_fp (cmp_vw_fp),
.a_cmp_fp (cmp_a_fp),
.r_cmp_fp (cmp_r_fp),
.g_cmp_fp (cmp_g_fp),
.b_cmp_fp (cmp_b_fp),
.f_cmp_fp (cmp_f_fp),
.rs_cmp_fp (cmp_rs_fp),
.gs_cmp_fp (cmp_gs_fp),
.bs_cmp_fp (cmp_bs_fp),
.hith_2 (hith_2),
.yon_2 (yon_2),
.fg_bgn (fg_bgn),
// Outputs.
.last_pixel (last_pixel),
.msk_last_pixel (msk_last_pixel),
.valid_z_col_spec (valid_z_col_spec),
.valid_uv (valid_uv),
.x_cur_o (current_x), // [15:0]
.y_cur_o (current_y), // [15:0]
.z_cur_fx (current_z), // [31:0], 24.8
.current_argb (current_argb), // [31:0]
.current_spec (current_spec), // [23:0]
.current_fog (current_fog), // [7:0]
.current_u (current_u), // [19:0]
.current_v (current_v), // [19:0]
.lod_num (lod_num), // [3:0]
.lod_gamma (lod_gamma), // [5:0]
.clip_xy (clip_xy),
.clip_uv (clip_uv),
.addr_exact (current_exact),
.bit_mask_x (current_bit_mask_x),
.bit_mask_y (current_bit_mask_y),
.l3_cpx0 (l3_cpx0),
.l3_cpy0 (l3_cpy0),
.l3_cpx1 (l3_cpx1),
.l3_cpy1 (l3_cpy1),
.current_fg_bgn (current_fg_bgn)
);
//////////////////////////////////////////////////////////////
//
// Functions.
//
// Color to Float function.
function [31:0] color_2_flt;
input [1:0] color_channel;
input color_mode;
input [31:0] color_in;
reg [7:0] afx;
begin
case(color_channel)
2'b00: afx = color_in[7:0];
2'b01: afx = color_in[15:8];
2'b10: afx = color_in[23:16];
2'b11: afx = color_in[31:24];
endcase
casex({color_mode, afx})
9'b1xxxxxxxx:color_2_flt = color_in;
9'b000000000:color_2_flt = 32'h0;
9'b01xxxxxxx:color_2_flt = {1'b0, 8'h86, afx[6:0], 16'h0};
9'b001xxxxxx:color_2_flt = {1'b0, 8'h85, afx[5:0], 17'h0};
9'b0001xxxxx:color_2_flt = {1'b0, 8'h84, afx[4:0], 18'h0};
9'b00001xxxx:color_2_flt = {1'b0, 8'h83, afx[3:0], 19'h0};
9'b000001xxx:color_2_flt = {1'b0, 8'h83, afx[2:0], 20'h0};
9'b0000001xx:color_2_flt = {1'b0, 8'h81, afx[1:0], 21'h0};
9'b00000001x:color_2_flt = {1'b0, 8'h80, afx[0], 22'h0};
9'b000000001:color_2_flt = {1'b0, 8'h7F, 23'h0};
endcase
end
endfunction
// Snap X floating point value to 1/16th.
function [31:0] flt_snap_x;
input [31:0] afl;
reg [23:0] mask;
begin
casex(afl[30:23])
8'b00xx_xxxx: mask = 24'b000000000000000000000000; // 63 - 0, 3f - 0
8'b010x_xxxx: mask = 24'b000000000000000000000000; // 95 - 64, 5f - 40
8'b0110_xxxx: mask = 24'b000000000000000000000000; // 111 - 96, 6f - 60
8'b0111_0xxx: mask = 24'b000000000000000000000000; // 119 - 112, 77 - 70
8'b0111_100x: mask = 24'b000000000000000000000000; // 121 - 120, 79 - 78
8'b0111_1010: mask = 24'b000000000000000000000000; // 122, 7A
8'b0111_1011: mask = 24'b100000000000000000000000; // 123
8'b0111_1100: mask = 24'b110000000000000000000000; // 124
8'b0111_1101: mask = 24'b111000000000000000000000; // 125
8'b0111_1110: mask = 24'b111100000000000000000000; // 126
8'b0111_1111: mask = 24'b1_11110000000000000000000; // 127
8'b1000_0000: mask = 24'b11_1111000000000000000000; // 128
8'b1000_0001: mask = 24'b111_111100000000000000000; // 129
8'b1000_0010: mask = 24'b1111_11110000000000000000; // 130
8'b1000_0011: mask = 24'b11111_1111000000000000000; // 131
8'b1000_0100: mask = 24'b111111_111100000000000000; // 132
8'b1000_0101: mask = 24'b1111111_11110000000000000; // 133
8'b1000_0110: mask = 24'b11111111_1111000000000000; // 134
8'b1000_0111: mask = 24'b111111111_111100000000000; // 135
8'b1000_1000: mask = 24'b1111111111_11110000000000; // 136
8'b1000_1001: mask = 24'b11111111111_1111000000000; // 137
8'b1000_1010: mask = 24'b111111111111_111100000000; // 138
8'b1000_1011: mask = 24'b1111111111111_11110000000; // 139
8'b1000_1100: mask = 24'b11111111111111_1111000000; // 140
8'b1000_1101: mask = 24'b111111111111111_111100000; // 141
8'b1000_1110: mask = 24'b1111111111111111_11110000; // 142
8'b1000_1111: mask = 24'b11111111111111111_1111000; // 143
8'b1001_0000: mask = 24'b111111111111111111_111100; // 144
8'b1001_0001: mask = 24'b1111111111111111111_11110; // 145
8'b1001_0010: mask = 24'b11111111111111111111_1111; // 146
8'b1001_0011: mask = 24'b111111111111111111111_111; // 147
8'b1001_0100: mask = 24'b1111111111111111111111_11; // 148
8'b1001_0101: mask = 24'b11111111111111111111111_1; // 149
default: mask = 24'b111111111111111111111111_; // 150 - 255
endcase
flt_snap_x = (mask[23]) ? {afl[31:23], (mask[22:0] & afl[22:0])} : 32'h0;
end
endfunction
// Snap Y floating point value to 1/16th.
function [35:0] flt_snap_y;
input [31:0] afl;
reg [23:0] mask;
reg [3:0] frac_y;
begin
casex(afl[30:23])
8'b00xx_xxxx: begin mask = 24'b000000000000000000000000; frac_y = 4'b0000; end // 63 - 0, 3f - 0
8'b010x_xxxx: begin mask = 24'b000000000000000000000000; frac_y = 4'b0000; end // 95 - 64, 5f - 40
8'b0110_xxxx: begin mask = 24'b000000000000000000000000; frac_y = 4'b0000; end // 111 - 96, 6f - 60
8'b0111_0xxx: begin mask = 24'b000000000000000000000000; frac_y = 4'b0000; end // 119 - 112, 77 - 70
8'b0111_100x: begin mask = 24'b000000000000000000000000; frac_y = 4'b0000; end // 121 - 120, 79 - 78
8'b0111_1010: begin mask = 24'b000000000000000000000000; frac_y = 4'b0000; end // 122, 7A
8'b0111_1011: begin mask = 24'b100000000000000000000000; frac_y = 4'b0001; end // 123
8'b0111_1100: begin mask = 24'b110000000000000000000000; frac_y = {3'b001, afl[22]}; end // 124
8'b0111_1101: begin mask = 24'b111000000000000000000000; frac_y = {2'b01, afl[22:21]}; end // 125
8'b0111_1110: begin mask = 24'b111100000000000000000000; frac_y = {1'b1, afl[22:20]}; end // 126
8'b0111_1111: begin mask = 24'b1_11110000000000000000000; frac_y = afl[22:19]; end // 127
8'b1000_0000: begin mask = 24'b11_1111000000000000000000; frac_y = afl[21:18]; end // 128
8'b1000_0001: begin mask = 24'b111_111100000000000000000; frac_y = afl[20:17]; end // 129
8'b1000_0010: begin mask = 24'b1111_11110000000000000000; frac_y = afl[19:16]; end // 130
8'b1000_0011: begin mask = 24'b11111_1111000000000000000; frac_y = afl[18:15]; end // 131
8'b1000_0100: begin mask = 24'b111111_111100000000000000; frac_y = afl[17:14]; end // 132
8'b1000_0101: begin mask = 24'b1111111_11110000000000000; frac_y = afl[16:13]; end // 133
8'b1000_0110: begin mask = 24'b11111111_1111000000000000; frac_y = afl[15:12]; end // 134
8'b1000_0111: begin mask = 24'b111111111_111100000000000; frac_y = afl[14:11]; end // 135
8'b1000_1000: begin mask = 24'b1111111111_11110000000000; frac_y = afl[13:10]; end // 136
8'b1000_1001: begin mask = 24'b11111111111_1111000000000; frac_y = afl[12:9]; end // 137
8'b1000_1010: begin mask = 24'b111111111111_111100000000; frac_y = afl[11:8]; end // 138
8'b1000_1011: begin mask = 24'b1111111111111_11110000000; frac_y = afl[10:7]; end // 139
8'b1000_1100: begin mask = 24'b11111111111111_1111000000; frac_y = afl[9:6]; end // 140
8'b1000_1101: begin mask = 24'b111111111111111_111100000; frac_y = afl[8:5]; end // 141
8'b1000_1110: begin mask = 24'b1111111111111111_11110000; frac_y = afl[7:4]; end // 142
8'b1000_1111: begin mask = 24'b11111111111111111_1111000; frac_y = afl[6:3]; end // 143
8'b1001_0000: begin mask = 24'b111111111111111111_111100; frac_y = afl[5:2]; end // 144
8'b1001_0001: begin mask = 24'b1111111111111111111_11110; frac_y = afl[4:1]; end // 145
8'b1001_0010: begin mask = 24'b11111111111111111111_1111; frac_y = afl[3:0]; end // 146
8'b1001_0011: begin mask = 24'b111111111111111111111_111; frac_y = {afl[2:0], 1'b0}; end // 147
8'b1001_0100: begin mask = 24'b1111111111111111111111_11; frac_y = {afl[1:0], 2'b00}; end // 148
8'b1001_0101: begin mask = 24'b11111111111111111111111_1; frac_y = {afl[0], 3'b0}; end // 149
default: begin mask = 24'b111111111111111111111111_; frac_y = 4'b0000; end // 150 - 255
endcase
flt_snap_y = { frac_y, ((mask[23]) ? {afl[31:23], (mask[22:0] & afl[22:0])} : 32'h0)};
end
endfunction
function [23:0]flt_frac;
input [31:0] afl;
reg [7:0] exp;
begin
exp = afl[30:23];
case(afl[30:23])
8'd102: flt_frac = 24'h0;
8'd103: flt_frac = {23'h0, 1'b1};
8'd104: flt_frac = {22'h0, 1'b1, afl[22]};
8'd105: flt_frac = {21'h0, 1'b1, afl[22:21]};
8'd106: flt_frac = {20'h0, 1'b1, afl[22:20]};
8'd107: flt_frac = {19'h0, 1'b1, afl[22:19]};
8'd108: flt_frac = {18'h0, 1'b1, afl[22:18]};
8'd109: flt_frac = {17'h0, 1'b1, afl[22:17]};
8'd110: flt_frac = {16'h0, 1'b1, afl[22:16]};
8'd111: flt_frac = {15'h0, 1'b1, afl[22:15]};
8'd112: flt_frac = {14'h0, 1'b1, afl[22:14]};
8'd113: flt_frac = {13'h0, 1'b1, afl[22:13]};
8'd114: flt_frac = {12'h0, 1'b1, afl[22:12]};
8'd115: flt_frac = {11'h0, 1'b1, afl[22:11]};
8'd116: flt_frac = {10'h0, 1'b1, afl[22:10]};
8'd117: flt_frac = {9'h0, 1'b1, afl[22:9]};
8'd118: flt_frac = {8'h0, 1'b1, afl[22:8]};
8'd119: flt_frac = {7'h0, 1'b1, afl[22:7]};
8'd120: flt_frac = {6'h0, 1'b1, afl[22:6]};
8'd121: flt_frac = {5'h0, 1'b1, afl[22:5]};
8'd122: flt_frac = {4'h0, 1'b1, afl[22:4]};
8'd123: flt_frac = {3'h0, 1'b1, afl[22:3]};
8'd124: flt_frac = {2'h0, 1'b1, afl[22:2]};
8'd125: flt_frac = {1'h0, 1'b1, afl[22:1]};
8'd126: flt_frac = {1'b1, afl[22:0]}; // 0.5
8'd127: flt_frac = {afl[22:0], 1'h0}; // 1.0
8'd128: flt_frac = {afl[21:0], 2'h0}; // 2.0
8'd129: flt_frac = {afl[20:0], 3'h0}; // 4.0
8'd130: flt_frac = {afl[19:0], 4'h0}; // 8.0
8'd131: flt_frac = {afl[18:0], 5'h0}; // 16.0
8'd132: flt_frac = {afl[17:0], 6'h0}; // 32.0
8'd133: flt_frac = {afl[16:0], 7'h0}; // 64.0
8'd134: flt_frac = {afl[15:0], 8'h0}; // 128.0
8'd135: flt_frac = {afl[14:0], 9'h0}; // 256.0
8'd136: flt_frac = {afl[13:0], 10'h0}; // 512.0
8'd137: flt_frac = {afl[12:0], 11'h0}; // 1024.0
8'd138: flt_frac = {afl[11:0], 12'h0}; // 2048.0
8'd139: flt_frac = {afl[10:0], 13'h0}; // 4096.0
8'd140: flt_frac = {afl[9:0], 14'h0}; // 8192.0
8'd141: flt_frac = {afl[8:0], 15'h0}; // 16384.0
8'd142: flt_frac = {afl[7:0], 16'h0}; // 32K.0
8'd143: flt_frac = {afl[6:0], 17'h0}; // 64K.0
8'd144: flt_frac = {afl[5:0], 18'h0}; // 128K.0
8'd145: flt_frac = {afl[4:0], 19'h0}; // 256K.0
8'd146: flt_frac = {afl[3:0], 20'h0}; // 512K.0
8'd147: flt_frac = {afl[2:0], 21'h0}; // 1M.0
8'd148: flt_frac = {afl[1:0], 22'h0}; // 2M.0
8'd149: flt_frac = {afl[0], 23'h0}; // 4M.0
default: flt_frac = 24'h0; // 8M or greater, no fraction.
endcase
end
endfunction
endmodule
|
module bcd_to_7seg_dec (bcd_in, segments_out, invert);
output reg [6:0] segments_out;
input [3:0] bcd_in;
input invert;
// 7-segment encoding
// 0
// ---
// 5 | | 1
// --- <--6
// 4 | | 2
// ---
// 3
reg [6:0] seg_reg;
always @*
case (bcd_in)
// this is the decoding for common anode displays:
4'b0001 : seg_reg = 7'b1111001; // 1
4'b0010 : seg_reg = 7'b0100100; // 2
4'b0011 : seg_reg = 7'b0110000; // 3
4'b0100 : seg_reg = 7'b0011001; // 4
4'b0101 : seg_reg = 7'b0010010; // 5
4'b0110 : seg_reg = 7'b0000010; // 6
4'b0111 : seg_reg = 7'b1111000; // 7
4'b1000 : seg_reg = 7'b0000000; // 8 -> all on
4'b1001 : seg_reg = 7'b0010000; // 9
4'b1010 : seg_reg = 7'b0001000; // A
4'b1011 : seg_reg = 7'b0000011; // b
4'b1100 : seg_reg = 7'b1000110; // C
4'b1101 : seg_reg = 7'b0100001; // d
4'b1110 : seg_reg = 7'b0000110; // E
4'b1111 : seg_reg = 7'b0001110; // F
default : seg_reg = 7'b1000000; // 0
endcase
always @*
case (invert)
1'b1 : segments_out = seg_reg; // do not invert segments for common anode display
1'b0 : segments_out = ~seg_reg; // invert segments for common cathode display
endcase
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
// Engineer:
//
// Create Date: 03.06.2015 14:58:39
// Design Name:
// Module Name: harness
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
module data_memory();
parameter ROWS = 133;
parameter COLS = 200;
// -- Modelo de memoria -------------------------------------- >>>>>
reg [7:0] MEM [0:(ROWS*COLS)-1];
// -- Rutina de inicializacion de memoria -------------------- >>>>>
initial
$readmemh("/home/hcabrera/Dropbox/tesis/noc/work/verilog/project_lancetfish/shared/scripts/python/data/133x200.dat", MEM);
// -- Task --------------------------------------------------- >>>>>
reg [0:63] memory_data;
task read;
input [31:0] address;
begin
address = address * 8;
$display("Address: ",address);
memory_data = {MEM[address], MEM[address + 1],
MEM[address + 2], MEM[address + 3],
MEM[address + 4], MEM[address + 5],
MEM[address + 6], MEM[address + 7]};
end
endtask : read
endmodule // data_memory |
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_babasu_CURRENTSTATE (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 2: 0] in_port;
input reset_n;
wire clk_en;
wire [ 2: 0] data_in;
wire [ 2: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {3 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
//
// Copyright 2011, Kevin Lindsey
// See LICENSE file for licensing information
//
module pram_sram_top(
input wire clk,
input wire button,
output wire [6:0] a_to_g,
output wire [3:0] an,
output wire [6:0] a_to_g2,
output wire [3:0] an2,
output reg good,
output reg bad,
output wire [1:0] hi_addr,
output wire [18:0] addr,
inout wire [15:0] data,
output wire ce,
output wire be,
output wire we,
output wire oe
);
wire clr, en, dclk, bclk, fclk;
wire [15:0] dataio, din1;
wire [17:0] sram_addr;
wire [5:0] pattern;
wire button_d;
assign clr = button_d;
assign ce = 0;
assign be = 0;
assign oe = en;
assign data = dataio;
assign addr = {1'b0, sram_addr};
assign hi_addr = sram_addr[17:16];
// custom clock
dcm_clock main_clock (
.CLKIN_IN(clk),
.RST_IN(clr),
.CLKFX_OUT(fclk)
//.CLKIN_IBUFG_OUT(),
//.CLK0_OUT(CLK0_OUT)
);
// controller
pram_sram_ctrl sram_ctrl (
.clk(fclk),
.clr(clr),
.go(bclk),
.halt(bad),
.we(we),
.sram_addr(sram_addr),
.pattern(pattern),
.en(en)
);
// ROM
pattern_rom pattern_rom (
.clk(fclk),
.addr(pattern),
.data(din1)
);
tristate_generic #(.N(16))
data_tristate (
.in(din1),
.en(en),
.out(dataio)
);
// button input
clock_divider clock_divider(
.clk(fclk),
.clr(clr),
.clk6(bclk),
.clk17(dclk)
);
debounce_generic button_debouncer(
.in(button),
.clk(dclk),
.clr(clr),
.out(button_d)
);
// address and value display
hex_7_segment data_display(
.x(data),
.clk(fclk),
.clr(clr),
.a_to_g(a_to_g),
.an(an)
);
hex_7_segment addr_display(
.x(addr[15:0]),
.clk(fclk),
.clr(clr),
.a_to_g(a_to_g2),
.an(an2)
);
always @*
if (data == din1)
begin
bad <= 0;
good <= 1;
end
else
begin
bad <= 1;
good <= 0;
end
endmodule
|
//==============================================================================
// Copyright (C) John-Philip Taylor
// [email protected]
//
// This file is part of a library
//
// This file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>
//==============================================================================
module UART_Sender #(
parameter N = 5,
parameter Full = 5'd29 // Clk / BAUD - 1
)(
input Clk,
input Reset,
input [7:0]Data,
input Send,
output reg Busy,
output reg Tx // Tx line on the board.
);
//------------------------------------------------------------------------------
reg tSend;
reg [ 7:0]Temp;
reg [N-1:0]Count;
reg [ 2:0]BitCount;
//------------------------------------------------------------------------------
reg [1:0]State;
localparam Idle = 2'b00;
localparam Sending = 2'b01;
localparam StopBit = 2'b11;
localparam Done = 2'b10;
//------------------------------------------------------------------------------
reg tReset;
always @(posedge Clk) begin
tReset <= Reset;
if(tReset) begin
Busy <= 1'b0;
Tx <= 1'b1;
tSend <= 0;
Count <= 0;
BitCount <= 0;
State <= Idle;
//------------------------------------------------------------------------------
end else begin
tSend <= Send;
if(~|Count) begin
case(State)
Idle: begin
if(tSend) begin
Count <= Full;
BitCount <= 3'd7;
{Temp, Tx} <= {Data, 1'b0};
Busy <= 1'b1;
State <= Sending;
end
end
//------------------------------------------------------------------------------
Sending: begin
Count <= Full;
{Temp[6:0], Tx} <= Temp;
if(~|BitCount) State <= StopBit;
BitCount <= BitCount - 1'b1;
end
//------------------------------------------------------------------------------
StopBit: begin
Tx <= 1'b1;
Count <= Full;
State <= Done;
end
//------------------------------------------------------------------------------
Done: begin
if(~tSend) begin
Busy <= 1'b0;
Count <= 0;
State <= Idle;
end
end
//------------------------------------------------------------------------------
default:;
endcase
end else begin
Count <= Count - 1'b1;
end
end
end
//------------------------------------------------------------------------------
endmodule
|
module i2c_cpu( input CLK,
input CLK_I2C,
input RESET,
input WE,
input [31:0] DATA_IN,
output [31:0] DATA_OUT,
inout SDA,
inout SCL );
wire ready, active;
reg [8:0] datain;
wire [8:0] dataout;
reg [1:0] state = 0, nextstate;
reg req_start, req_stop, req_io;
wire req_en = (state == 2'd1);
always@(*)
case(state)
2'd0: if(WE) nextstate = 2'd1;
else nextstate = 2'd0;
2'd1: if(!ready) nextstate = 2'd2;
else nextstate = 2'd1;
2'd2: if(ready) nextstate = 2'd0;
else nextstate = 2'd2;
default: nextstate = 2'd0;
endcase
always@ (posedge CLK)
if(RESET) state <= 2'd0;
else
begin
state <= nextstate;
if(WE)
begin
datain <= { DATA_IN[7:0], DATA_IN[8] };
req_start <= DATA_IN[18];
req_io <= DATA_IN[17];
req_stop <= DATA_IN[16];
end
end
assign DATA_OUT = { state != 2'd0,
active,
21'd0,
dataout[0],
dataout[8:1] };
/*
reg CLK_I2C = 0;
reg [6:0] clk_div = 0;
always@ (posedge CLK)
begin
if(clk_div == 16)
begin
clk_div <= 6'd0;
CLK_I2C <= ~CLK_I2C;
end
else clk_div <= clk_div + 6'd1;
end
*/
i2c i2c_module( .CLK ( CLK_I2C ),
.RESET ( RESET ),
.DATA_IN ( datain ),
.DATA_OUT ( dataout ),
.REQUEST_IO ( req_io & req_en ),
.REQUEST_START ( req_start & req_en ),
.REQUEST_STOP ( req_stop & req_en ),
.READY ( ready ),
.ACTIVE ( active ),
.SDA ( SDA ),
.SCL ( SCL ) );
endmodule
//=================================================================//
module i2c( input CLK,
input RESET,
input [8:0] DATA_IN,
output [8:0] DATA_OUT,
input REQUEST_IO,
input REQUEST_START,
input REQUEST_STOP,
output READY,
output ACTIVE,
inout SDA,
inout SCL );
reg [2:0] state = 0, nextstate;
wire sda_w, scl_w, sda_smachine, sda_override,
shift_in, shift_out;
reg [8:0] datain;
reg [8:0] dataout;
reg [3:0] bit_cnt;
parameter ST_IDLE = 0;
parameter ST_START = 1;
parameter ST_WAIT_IO = 2;
parameter ST_SETUP = 3;
parameter ST_DRIVE = 4;
parameter ST_CHECK = 5;
parameter ST_HOLD = 6;
parameter ST_STOP = 7;
always@ (*)
case(state)
ST_IDLE: if(REQUEST_START) nextstate = ST_START; //accept only start request in idle state
else nextstate = ST_IDLE;
ST_START: nextstate = ST_WAIT_IO;
ST_WAIT_IO: if (REQUEST_IO) nextstate = ST_SETUP;
else if(REQUEST_STOP) nextstate = ST_STOP;
else nextstate = ST_WAIT_IO;
ST_SETUP: nextstate = ST_DRIVE;
ST_DRIVE: nextstate = ST_CHECK;
ST_CHECK: nextstate = ST_HOLD;
ST_HOLD: if(bit_cnt == 8) nextstate = ST_WAIT_IO;
else nextstate = ST_SETUP;
ST_STOP: nextstate = ST_IDLE;
default: nextstate = ST_IDLE;
endcase
reg [4:0] controls;
assign {sda_override, sda_smachine, scl_w, shift_in, shift_out} = controls;
always@ (*)
case(state) //OM_C_IO
ST_IDLE: controls = 5'b11_1_00;
ST_START: controls = 5'b10_1_00;
ST_WAIT_IO: controls = 5'b10_0_00;
ST_SETUP: controls = 5'b0X_0_00;
ST_DRIVE: controls = 5'b0X_1_10;
ST_CHECK: controls = 5'b0X_1_00;
ST_HOLD: controls = 5'b0X_0_01;
ST_STOP: controls = 5'b10_1_00;
default: controls = 5'b11_1_00;
endcase
always@ (posedge CLK)
begin
if(RESET)
begin
bit_cnt <= 4'd0;
state <= 4'd0;
end
else
begin
state <= nextstate;
if(READY)
begin
if(REQUEST_IO)
begin
dataout <= DATA_IN[8:0];
datain <= 8'd0;
bit_cnt <= 0;
end
end
else
begin
if(shift_in)
begin
datain[8:1] <= datain[7:0];
datain[0] <= SDA;
end
if(shift_out)
begin
dataout[8:1] <= dataout[7:0];
dataout[0] <= 0;
bit_cnt <= bit_cnt + 4'd1;
end
end
end
end
assign sda_w = sda_override ? sda_smachine : dataout[8];
assign SDA = sda_w ? 1'bZ : 1'b0;
assign SCL = scl_w ? 1'bZ : 1'b0;
assign READY = ((state == ST_IDLE) | (state == ST_WAIT_IO));
assign ACTIVE = (state != ST_IDLE);
assign DATA_OUT = datain;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_1_V
`define SKY130_FD_SC_LP__A2111O_1_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S4S_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLYMETAL6S4S_BEHAVIORAL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlymetal6s4s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S4S_BEHAVIORAL_V |
// -*- Mode: Verilog -*-
// Filename : fw_interface_logic.v
// Description : FW Interface Test Logic
// Author : Philip Tracton
// Created On : Wed Dec 21 14:09:23 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 21 14:09:23 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "timescale.v"
`ifdef SIMULATION
`include "simulation_includes.vh"
`endif
module fw_interface_logic (/*AUTOARG*/
// Inputs
wb_clk_i, wb_rst_i, new_report, new_warning, new_error,
new_compare, report_reg, warning_reg, error_reg, expected_reg,
measured_reg, index, data, write_mem
) ;
input wire wb_clk_i;
input wire wb_rst_i;
input wire new_report;
input wire new_warning;
input wire new_error;
input wire new_compare;
input wire [31:0] report_reg;
input wire [31:0] warning_reg;
input wire [31:0] error_reg;
input wire [31:0] expected_reg;
input wire [31:0] measured_reg;
input wire [5:0] index;
input wire [7:0] data;
input wire write_mem;
`ifdef SIMULATION
reg [7:0] string_mem[8*64:0];
always @(posedge wb_clk_i)
if (write_mem) begin
string_mem[index] <= data;
end
wire new_report_rising;
edge_detection new_report_edge(
// Outputs
.rising(new_report_rising),
.failling(),
// Inputs
.clk_i(wb_clk_i),
.rst_i(wb_rst_i),
.signal(new_report)
);
integer i;
reg [8*64:0] test_string;
always @ (posedge new_report_rising) begin
i = 0;
test_string = 0;
while (string_mem[i] != 8'h0) begin
#1 test_string = {test_string[8*29:0], string_mem[i]};
#1 string_mem[i] = 0;
#1 i = i + 1;
end
`TEST_COMPARE(test_string,0,0);
end // always @ (posedge new_report_rising)
wire new_compare_rising;
edge_detection new_compare_edge(
// Outputs
.rising(new_compare_rising),
.failling(),
// Inputs
.clk_i(wb_clk_i),
.rst_i(wb_rst_i),
.signal(new_compare)
);
always @ (posedge new_compare_rising) begin
i = 0;
test_string = 0;
while (string_mem[i] != 8'h0) begin
#1 test_string = {test_string[8*29:0], string_mem[i]};
#1 string_mem[i] = 0;
#1 i = i + 1;
end
`TEST_COMPARE(test_string,expected_reg,measured_reg);
end // always @ (posedge new_report_rising)
`endif
endmodule // fw_interface_logic
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__EINVP_BEHAVIORAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_BEHAVIORAL_PP_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:57:55 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_auto_pc_0_stub.v
// Design : design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
`ifdef ALLOW_UNOPT
/*verilator lint_off UNOPTFLAT*/
`endif
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] b; // From file of file.v
wire [31:0] c; // From file of file.v
wire [31:0] d; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.b (b[31:0]),
.c (c[31:0]),
.d (d[31:0]),
// Inputs
.crc (crc[31:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {b, d}
^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h649ee1713d624dd9) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
b, c, d,
// Inputs
crc
);
input [31:0] crc;
`ifdef ISOLATE
output reg [31:0] b /* verilator isolate_assignments*/;
`else
output reg [31:0] b;
`endif
output reg [31:0] c;
output reg [31:0] d;
always @* begin
// Note that while c and b depend on crc, b doesn't depend on c.
casez (crc[3:0])
4'b??01: begin
b = {crc[15:0],get_31_16(crc)};
d = c;
end
4'b??00: begin
b = {crc[15:0],~crc[31:16]};
d = {crc[15:0],~c[31:16]};
end
default: begin
set_b_d(crc, c);
end
endcase
end
function [31:16] get_31_16 /* verilator isolate_assignments*/;
input [31:0] t_crc /* verilator isolate_assignments*/;
get_31_16 = t_crc[31:16];
endfunction
task set_b_d;
`ifdef ISOLATE
input [31:0] t_crc /* verilator isolate_assignments*/;
input [31:0] t_c /* verilator isolate_assignments*/;
`else
input [31:0] t_crc;
input [31:0] t_c;
`endif
begin
b = {t_crc[31:16],~t_crc[23:8]};
d = {t_crc[31:16], ~t_c[23:8]};
end
endtask
always @* begin
// Any complicated equation we can't optimize
casez (crc[3:0])
4'b00??: begin
c = {b[29:0],2'b11};
end
4'b01??: begin
c = {b[30:1],2'b01};
end
4'b10??: begin
c = {b[31:2],2'b10};
end
4'b11??: begin
c = {b[31:2],2'b00};
end
endcase
end
endmodule
|
`timescale 1ns/1ns
// READ: Tag response to a 'read' command.
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// readbit* = talking to tx module
// read_sample_* = talking to external source (adc or msp430)
// which supplies sample data to be transmitted.
// handle = current handle from random number generator
module read(reset, readbitclk, readbitout, readbitdone,
read_sample_ctl, read_sample_clk, read_sample_datain,
handle);
input reset, readbitclk;
output readbitout, readbitdone;
input read_sample_datain;
output read_sample_ctl, read_sample_clk;
input [15:0] handle;
wire [32:0] packet;
assign packet[32] = 1'b0;
assign packet[31:16] = 16'h0000;
assign packet[15:0] = handle[15:0];
reg [5:0] bitoutcounter;
reg read_sample_ctl;
wire read_sample_clk, readbitout, readbitdone;
assign read_sample_clk = readbitclk & (bitoutcounter > 15);
assign readbitout = (bitoutcounter!=32 && bitoutcounter>15) ? read_sample_datain : packet[bitoutcounter];
assign readbitdone = (bitoutcounter == 0);
reg initialized;
always @ (posedge readbitclk or posedge reset) begin
if (reset) begin
bitoutcounter <= 0;
initialized <= 0;
read_sample_ctl <= 0;
end else if (!initialized) begin
initialized <= 1;
read_sample_ctl <= 1;
bitoutcounter <= 32;
end else if (!readbitdone) begin
bitoutcounter <= bitoutcounter - 4'd1;
if (bitoutcounter >= 15) read_sample_ctl <= 1;
else read_sample_ctl <= 0;
end else begin
read_sample_ctl<= 0;
end // ~reset
end // always
endmodule
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2014 - Russ Dill <[email protected]>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "bch_defs.vh"
/*
* serial with inversion
* Berlekamp–Massey algorithm
*
* sigma_i^(r) = sigma_i^(r-1) + d_rp * beta_i^(r) (i = 1 to t-1)
* d_r = summation sigma_i^(r) * S_(2 * r - i + 1) from i = 0 to t
* d_rp = d_p^-1 * d_r
*
* combine above equations:
* d_r = summation (simga_i^(r-1) + d_rp * beta_i^(r)) * S_(2 * r - i + 1) from i = 0 to t
*/
module bch_sigma_bma_serial #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE
) (
input clk,
input start,
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
input ack_done,
output reg done = 0,
output ready,
output [`BCH_SIGMA_SZ(P)-1:0] sigma,
output reg [`BCH_ERR_SZ(P)-1:0] err_count = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam T = `BCH_T(P);
wire [M-1:0] d_r;
wire [M-1:0] d_rp_dual;
wire [T:0] cin;
wire [T:0] sigma_serial; /* 0 bits of each sigma */
wire [M-1:0] syn1 = syndromes[0+:M];
wire [T*M-1:0] _sigma;
wire [M-1:0] sigma_1;
/* because of inversion, sigma0 is always 1 */
assign sigma = {_sigma, {M-1{1'b0}}, 1'b1};
reg [(T+1)*M-1:0] beta = 0;
reg [(T-1)*M-1:0] sigma_last = 0; /* Last sigma values */
reg first_cycle = 0;
reg second_cycle = 0;
reg penult2_cycle = 0;
reg penult1_cycle = 0;
reg last_cycle = 0;
reg first_calc = 0; /* bch_n == 0 */
reg final_calc = 0; /* bch_n == T - 1 */
reg counting = 0;
reg busy = 0;
/* beta(1)(x) = syn1 ? x^2 : x^3 */
wire [M*4-1:0] beta0; /* Initial beta */
assign beta0 = {{{M-1{1'b0}}, !syn1}, {{M-1{1'b0}}, |syn1}, {(M*2){1'b0}}};
/* d_r(0) = 1 + S_1 * x */
wire [(T+1)*M-1:0] d_r0; /* Initial dr */
assign d_r0 = {syn1, {(M-1){1'b0}}, 1'b1};
wire [`BCH_ERR_SZ(P)-1:0] bch_n;
counter #(T+1) u_bch_n_counter(
.clk(clk),
.reset(start),
.ce(last_cycle),
.count(bch_n)
);
wire [log2(M-4)-1:0] count;
counter #(M-4) u_counter(
.clk(clk),
.reset(second_cycle),
.ce(counting),
.count(count)
);
wire [(2*T-1)*M-1:0] syn_shuffled;
bch_syndrome_shuffle #(P) u_bch_syndrome_shuffle(
.clk(clk),
.start(start),
.ce(last_cycle),
.syndromes(syndromes),
.syn_shuffled(syn_shuffled)
);
reg d_r_nonzero = 0;
wire bsel;
assign bsel = d_r_nonzero && bch_n >= err_count;
reg bsel_last = 0;
assign ready = !busy && (!done || ack_done);
always @(posedge clk) begin
if (start)
busy <= #TCQ 1;
else if (penult2_cycle && final_calc)
busy <= #TCQ 0;
if (penult2_cycle && final_calc)
done <= #TCQ 1;
else if (ack_done)
done <= #TCQ 0;
if (last_cycle || start)
final_calc <= #TCQ T == 2 ? first_calc : (bch_n == T - 2);
if (start)
first_calc <= #TCQ 1;
else if (last_cycle)
first_calc <= #TCQ 0;
if (start) begin
beta <= #TCQ beta0;
sigma_last <= #TCQ beta0[2*M+:2*M]; /* beta(1) */
err_count <= #TCQ {{`BCH_ERR_SZ(P)-1{1'b0}}, |syn1};
bsel_last <= #TCQ 1'b1;
end else if (first_cycle) begin
if (bsel)
err_count <= #TCQ 2 * bch_n - err_count + 1;
bsel_last <= #TCQ bsel;
end else if (last_cycle) begin
d_r_nonzero <= #TCQ |d_r;
sigma_last <= #TCQ sigma[0+:(T-1)*M];
/* b^(r+1)(x) = x^2 * (bsel ? sigmal^(r-1)(x) : b_(r)(x)) */
beta[2*M+:(T-1)*M] <= #TCQ bsel_last ?
sigma_last[0*M+:(T-1)*M] :
beta[0*M+:(T-1)*M];
end
penult2_cycle <= #TCQ counting && count == M - 4;
penult1_cycle <= #TCQ penult2_cycle && !final_calc;
last_cycle <= #TCQ penult1_cycle;
first_cycle <= #TCQ last_cycle;
second_cycle <= #TCQ first_cycle || start;
if (second_cycle)
counting <= #TCQ 1;
else if (count == M - 4)
counting <= #TCQ 0;
end
wire [M-1:0] d_p0 = syn1 ? syn1 : 1;
/* d_rp = d_p^-1 * d_r */
finite_divider #(M) u_dinv(
.clk(clk),
.start(start || (first_cycle && bsel && !final_calc)),
.busy(),
.standard_numer(d_r),
/* d_p = S_1 ? S_1 : 1 */
.standard_denom(start ? d_p0 : d_r), /* syn1 is d_p initial value */
.dual_out(d_rp_dual)
);
/* mbN SDBM d_rp * beta_i(r) */
serial_mixed_multiplier_dss #(M, T + 1) u_serial_mixed_multiplier(
.clk(clk),
.start(last_cycle),
.dual_in(d_rp_dual),
.standard_in(beta),
.standard_out(cin)
);
/* Add Beta * drp to sigma (Summation) */
/* sigma_i^(r-1) + d_rp * beta_i^(r) */
wire [T:0] _cin = first_calc ? {T+1{1'b0}} : cin;
finite_serial_adder #(M) u_cN [T:0] (
.clk(clk),
.start(start),
.ce(!last_cycle && !penult1_cycle),
.parallel_in(d_r0),
.serial_in(_cin), /* First time through, we just shift out d_r0 */
.parallel_out({_sigma, sigma_1}),
.serial_out(sigma_serial)
);
/* d_r = summation (sigma_i^(r-1) + d_rp * beta_i^(r)) * S_(2 * r - i + 1) from i = 0 to t */
serial_standard_multiplier #(M, T+1) msm_serial_standard_multiplier(
.clk(clk),
.reset(start || first_cycle),
.ce(!last_cycle),
.parallel_in(syn_shuffled[0+:M*(T+1)]),
.serial_in(sigma_serial),
.out(d_r)
);
endmodule
|
//-----------------------------------------------------------------------------
// File : memory_controller.v
// Creation date : 27.07.2017
// Creation time : 15:08:05
// Description : Used to control local memory as well as peripherals.
//
// Ports prefixes:
// -local denotes local memory access, explained in interface.local_memory
// -periph denotes peripheral access, explained in interface.peripheral_control
// -sys denotes CPU system bus, explained in interface.intra_cpu
// Created by : TermosPullo
// Tool : Kactus2 3.4.110 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:cpu.logic:memory_controller:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.logic/memory_controller/1.0/memory_controller.1.0.xml
//-----------------------------------------------------------------------------
module memory_controller #(
parameter DATA_WIDTH = 16, // Width for data in registers and instructions.
parameter AUB = 8, // Addressable unit bits, size of byte.
parameter ADDR_WIDTH = 16, // Width of the addresses.
parameter MEMORY_SIZE = 256, // How many bytes are in memory at total.
parameter PERIPHERAL_BASE = 128, // The first address for peripherals.
parameter REGISTER_COUNT = 8, // How many registers are supported in the core.
parameter DATA_BYTES = DATA_WIDTH/AUB, // How many bytes in data width.
parameter CONTROL_RANGE = 'h40 // How many AUBs are reserved for control data.
) (
// Interface: cpu_clk_sink
// The clock and reset comes through this interface.
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i, // The mandatory reset, as this is synchronous logic.
// Interface: cpu_system
// Connects the component to other CPU components.
input sys_active_i,
input [ADDR_WIDTH-1:0] sys_address_i,
input [DATA_WIDTH-1:0] sys_data_i,
input sys_we_i,
output [DATA_WIDTH-1:0] sys_data_o,
output sys_rdy_o,
output sys_read_rdy_o,
// Interface: local_data
// Connects to the local data memory.
input [DATA_WIDTH-1:0] local_read_data,
output [ADDR_WIDTH-1:0] local_address_o,
output [DATA_WIDTH-1:0] local_write_data,
output local_write_o,
// Interface: peripheral_access
// Controller accesses peripherals through this interface.
input [DATA_WIDTH-1:0] periph_data_i,
input periph_slave_rdy,
output reg [ADDR_WIDTH-1:0] periph_address_o,
output reg [DATA_WIDTH-1:0] periph_data_o,
output reg periph_master_rdy,
output reg periph_we_o
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// Choose the active address block, if any.
wire local_mem_active = sys_active_i && sys_address_i < PERIPHERAL_BASE;
wire periph_mem_active = sys_active_i && sys_address_i >= PERIPHERAL_BASE;
reg periph_mem_rdy;
reg local_mem_rdy;
reg [DATA_WIDTH-1:0] periph_load_value;
// 1 = Last operation was read, else zero.
reg read_operation;
assign sys_data_o = periph_mem_active ? periph_load_value : local_read_data;
assign local_write_data = sys_data_i;
assign local_write_o = sys_we_i;
assign local_address_o = sys_address_i;
assign sys_rdy_o = local_mem_rdy | periph_mem_rdy;
assign sys_read_rdy_o = sys_rdy_o && read_operation;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
local_mem_rdy <= 0;
read_operation <= 0;
end
else begin
if (local_mem_active) begin
local_mem_rdy <= 1;
end
else begin
local_mem_rdy <= 0;
end
if (local_mem_active || sys_active_i) begin
read_operation <= ~sys_we_i;
end
else begin
read_operation <= 0;
end
end
end
// The state of peripheral access.
reg [1:0] state;
// The available states for peripheral access.
parameter [1:0]
S_WAIT = 2'd0,
S_WAIT_WRITE = 2'd1,
S_WAIT_READ = 2'd2,
S_DEASSERT = 2'd3;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
// Start with wait
state <= S_WAIT;
periph_mem_rdy <= 0;
periph_load_value <= 0;
// Outputs are zero by default.
periph_address_o <= 0;
periph_data_o <= 0;
periph_master_rdy <= 0;
periph_we_o <= 0;
end
else begin
case(state)
S_WAIT: begin
if (periph_mem_active == 1) begin
if (sys_we_i == 1) begin
periph_we_o <= 1;
periph_data_o <= sys_data_i;
state <= S_WAIT_WRITE;
end
else begin
state <= S_WAIT_READ;
end
periph_master_rdy <= 1;
periph_address_o <= sys_address_i - PERIPHERAL_BASE;
end
end
S_WAIT_WRITE: begin
periph_master_rdy <= 0;
if (periph_slave_rdy == 1) begin
state <= S_DEASSERT;
periph_mem_rdy <= 1;
// Deassert write.
periph_we_o <= 0;
end
end
S_WAIT_READ: begin
periph_master_rdy <= 0;
if (periph_slave_rdy == 1) begin
state <= S_DEASSERT;
periph_load_value <= periph_data_i;
periph_mem_rdy <= 1;
end
end
S_DEASSERT: begin
state <= S_WAIT;
periph_mem_rdy <= 0;
end
default: begin
$display("ERROR: Unkown state: %d", state);
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVPWRVGND_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__TAPVPWRVGND_FUNCTIONAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvpwrvgnd (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVPWRVGND_FUNCTIONAL_PP_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:13:47 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_3_stub.v
// Design : zqynq_lab_1_design_auto_pc_3
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:27:08 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_sim_netlist.v
// Design : system_vga_color_test_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_color_test_0_0,vga_color_test,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_color_test,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_color_test_0_0
(clk_25,
xaddr,
yaddr,
rgb);
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
wire clk_25;
wire [23:3]\^rgb ;
wire [9:0]xaddr;
wire [9:0]yaddr;
assign rgb[23:22] = \^rgb [23:22];
assign rgb[21] = \^rgb [20];
assign rgb[20] = \^rgb [20];
assign rgb[19] = \^rgb [20];
assign rgb[18] = \^rgb [20];
assign rgb[17] = \^rgb [20];
assign rgb[16] = \^rgb [20];
assign rgb[15:14] = \^rgb [15:14];
assign rgb[13] = \^rgb [12];
assign rgb[12] = \^rgb [12];
assign rgb[11] = \^rgb [12];
assign rgb[10] = \^rgb [12];
assign rgb[9] = \^rgb [12];
assign rgb[8] = \^rgb [12];
assign rgb[7:5] = \^rgb [7:5];
assign rgb[4] = \^rgb [3];
assign rgb[3] = \^rgb [3];
assign rgb[2] = \^rgb [3];
assign rgb[1] = \^rgb [3];
assign rgb[0] = \^rgb [3];
system_vga_color_test_0_0_vga_color_test U0
(.clk_25(clk_25),
.rgb({\^rgb [23:22],\^rgb [20],\^rgb [15:14],\^rgb [12],\^rgb [7:5],\^rgb [3]}),
.xaddr(xaddr),
.yaddr(yaddr[9:3]));
endmodule
(* ORIG_REF_NAME = "vga_color_test" *)
module system_vga_color_test_0_0_vga_color_test
(rgb,
yaddr,
xaddr,
clk_25);
output [9:0]rgb;
input [6:0]yaddr;
input [9:0]xaddr;
input clk_25;
wire clk_25;
wire [9:0]rgb;
wire \rgb[13]_i_1_n_0 ;
wire \rgb[14]_i_1_n_0 ;
wire \rgb[14]_i_2_n_0 ;
wire \rgb[14]_i_3_n_0 ;
wire \rgb[14]_i_4_n_0 ;
wire \rgb[14]_i_5_n_0 ;
wire \rgb[14]_i_6_n_0 ;
wire \rgb[15]_i_1_n_0 ;
wire \rgb[15]_i_2_n_0 ;
wire \rgb[15]_i_3_n_0 ;
wire \rgb[15]_i_4_n_0 ;
wire \rgb[15]_i_5_n_0 ;
wire \rgb[15]_i_6_n_0 ;
wire \rgb[15]_i_7_n_0 ;
wire \rgb[21]_i_1_n_0 ;
wire \rgb[22]_i_10_n_0 ;
wire \rgb[22]_i_11_n_0 ;
wire \rgb[22]_i_1_n_0 ;
wire \rgb[22]_i_2_n_0 ;
wire \rgb[22]_i_3_n_0 ;
wire \rgb[22]_i_4_n_0 ;
wire \rgb[22]_i_5_n_0 ;
wire \rgb[22]_i_6_n_0 ;
wire \rgb[22]_i_7_n_0 ;
wire \rgb[22]_i_8_n_0 ;
wire \rgb[22]_i_9_n_0 ;
wire \rgb[23]_i_10_n_0 ;
wire \rgb[23]_i_11_n_0 ;
wire \rgb[23]_i_12_n_0 ;
wire \rgb[23]_i_13_n_0 ;
wire \rgb[23]_i_14_n_0 ;
wire \rgb[23]_i_15_n_0 ;
wire \rgb[23]_i_16_n_0 ;
wire \rgb[23]_i_17_n_0 ;
wire \rgb[23]_i_18_n_0 ;
wire \rgb[23]_i_1_n_0 ;
wire \rgb[23]_i_2_n_0 ;
wire \rgb[23]_i_3_n_0 ;
wire \rgb[23]_i_4_n_0 ;
wire \rgb[23]_i_5_n_0 ;
wire \rgb[23]_i_6_n_0 ;
wire \rgb[23]_i_7_n_0 ;
wire \rgb[23]_i_8_n_0 ;
wire \rgb[23]_i_9_n_0 ;
wire \rgb[4]_i_1_n_0 ;
wire \rgb[4]_i_2_n_0 ;
wire \rgb[5]_i_1_n_0 ;
wire \rgb[5]_i_2_n_0 ;
wire \rgb[6]_i_1_n_0 ;
wire \rgb[6]_i_2_n_0 ;
wire \rgb[6]_i_3_n_0 ;
wire \rgb[6]_i_4_n_0 ;
wire \rgb[6]_i_5_n_0 ;
wire \rgb[7]_i_1_n_0 ;
wire \rgb[7]_i_2_n_0 ;
wire \rgb[7]_i_3_n_0 ;
wire \rgb[7]_i_4_n_0 ;
wire \rgb[7]_i_5_n_0 ;
wire \rgb[7]_i_6_n_0 ;
wire [9:0]xaddr;
wire [6:0]yaddr;
LUT5 #(
.INIT(32'h5555FF02))
\rgb[13]_i_1
(.I0(\rgb[15]_i_4_n_0 ),
.I1(\rgb[14]_i_2_n_0 ),
.I2(\rgb[14]_i_3_n_0 ),
.I3(\rgb[22]_i_2_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.O(\rgb[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'h55555555FFFFFF02))
\rgb[14]_i_1
(.I0(\rgb[15]_i_4_n_0 ),
.I1(\rgb[14]_i_2_n_0 ),
.I2(\rgb[14]_i_3_n_0 ),
.I3(\rgb[22]_i_3_n_0 ),
.I4(\rgb[22]_i_2_n_0 ),
.I5(\rgb[23]_i_6_n_0 ),
.O(\rgb[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'h02F20202))
\rgb[14]_i_2
(.I0(\rgb[14]_i_4_n_0 ),
.I1(\rgb[23]_i_11_n_0 ),
.I2(xaddr[9]),
.I3(\rgb[14]_i_5_n_0 ),
.I4(\rgb[23]_i_10_n_0 ),
.O(\rgb[14]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'hE))
\rgb[14]_i_3
(.I0(\rgb[14]_i_6_n_0 ),
.I1(yaddr[6]),
.O(\rgb[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFEFEFEFEFEFEFEEE))
\rgb[14]_i_4
(.I0(xaddr[4]),
.I1(xaddr[5]),
.I2(xaddr[3]),
.I3(xaddr[0]),
.I4(xaddr[1]),
.I5(xaddr[2]),
.O(\rgb[14]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFF8))
\rgb[14]_i_5
(.I0(xaddr[2]),
.I1(xaddr[5]),
.I2(xaddr[7]),
.I3(xaddr[6]),
.I4(xaddr[8]),
.O(\rgb[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'hA888A888A8888888))
\rgb[14]_i_6
(.I0(yaddr[5]),
.I1(yaddr[4]),
.I2(yaddr[2]),
.I3(yaddr[3]),
.I4(yaddr[1]),
.I5(yaddr[0]),
.O(\rgb[14]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000FFFF55455545))
\rgb[15]_i_1
(.I0(\rgb[23]_i_4_n_0 ),
.I1(\rgb[22]_i_2_n_0 ),
.I2(\rgb[15]_i_2_n_0 ),
.I3(\rgb[15]_i_3_n_0 ),
.I4(\rgb[15]_i_4_n_0 ),
.I5(\rgb[23]_i_6_n_0 ),
.O(\rgb[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h7))
\rgb[15]_i_2
(.I0(\rgb[22]_i_8_n_0 ),
.I1(\rgb[23]_i_12_n_0 ),
.O(\rgb[15]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hAAA88888))
\rgb[15]_i_3
(.I0(\rgb[14]_i_3_n_0 ),
.I1(xaddr[9]),
.I2(xaddr[6]),
.I3(xaddr[7]),
.I4(xaddr[8]),
.O(\rgb[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'hECEEEEEEECECECEC))
\rgb[15]_i_4
(.I0(xaddr[8]),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(\rgb[15]_i_5_n_0 ),
.I4(\rgb[15]_i_6_n_0 ),
.I5(\rgb[15]_i_7_n_0 ),
.O(\rgb[15]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h1F))
\rgb[15]_i_5
(.I0(xaddr[0]),
.I1(xaddr[1]),
.I2(xaddr[2]),
.O(\rgb[15]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h7))
\rgb[15]_i_6
(.I0(xaddr[5]),
.I1(xaddr[4]),
.O(\rgb[15]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h8880))
\rgb[15]_i_7
(.I0(xaddr[6]),
.I1(xaddr[5]),
.I2(xaddr[4]),
.I3(xaddr[3]),
.O(\rgb[15]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFFBF0FB))
\rgb[21]_i_1
(.I0(\rgb[22]_i_2_n_0 ),
.I1(\rgb[22]_i_4_n_0 ),
.I2(\rgb[23]_i_2_n_0 ),
.I3(\rgb[23]_i_6_n_0 ),
.I4(\rgb[23]_i_7_n_0 ),
.O(\rgb[21]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEFFF00FFEF))
\rgb[22]_i_1
(.I0(\rgb[22]_i_2_n_0 ),
.I1(\rgb[22]_i_3_n_0 ),
.I2(\rgb[22]_i_4_n_0 ),
.I3(\rgb[23]_i_2_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[23]_i_7_n_0 ),
.O(\rgb[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h01))
\rgb[22]_i_10
(.I0(xaddr[9]),
.I1(xaddr[6]),
.I2(xaddr[7]),
.O(\rgb[22]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0070))
\rgb[22]_i_11
(.I0(xaddr[3]),
.I1(xaddr[4]),
.I2(xaddr[8]),
.I3(xaddr[5]),
.O(\rgb[22]_i_11_n_0 ));
LUT6 #(
.INIT(64'h00000000AAABABAB))
\rgb[22]_i_2
(.I0(\rgb[22]_i_5_n_0 ),
.I1(xaddr[8]),
.I2(xaddr[9]),
.I3(xaddr[6]),
.I4(xaddr[7]),
.I5(\rgb[22]_i_6_n_0 ),
.O(\rgb[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000FD0000))
\rgb[22]_i_3
(.I0(\rgb[23]_i_15_n_0 ),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\rgb[22]_i_7_n_0 ),
.I4(xaddr[9]),
.I5(\rgb[22]_i_6_n_0 ),
.O(\rgb[22]_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\rgb[22]_i_4
(.I0(\rgb[23]_i_7_n_0 ),
.I1(\rgb[22]_i_8_n_0 ),
.I2(\rgb[23]_i_8_n_0 ),
.I3(\rgb[14]_i_3_n_0 ),
.O(\rgb[22]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000200030003))
\rgb[22]_i_5
(.I0(\rgb[15]_i_5_n_0 ),
.I1(xaddr[9]),
.I2(xaddr[8]),
.I3(xaddr[5]),
.I4(xaddr[3]),
.I5(xaddr[4]),
.O(\rgb[22]_i_5_n_0 ));
LUT6 #(
.INIT(64'h111111111111111F))
\rgb[22]_i_6
(.I0(\rgb[14]_i_6_n_0 ),
.I1(yaddr[6]),
.I2(\rgb[22]_i_9_n_0 ),
.I3(xaddr[7]),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(\rgb[22]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFFEFEFEFFFFFFFF))
\rgb[22]_i_7
(.I0(xaddr[8]),
.I1(xaddr[6]),
.I2(xaddr[7]),
.I3(xaddr[5]),
.I4(xaddr[2]),
.I5(\rgb[23]_i_10_n_0 ),
.O(\rgb[22]_i_7_n_0 ));
LUT6 #(
.INIT(64'h5515551555151515))
\rgb[22]_i_8
(.I0(\rgb[23]_i_14_n_0 ),
.I1(\rgb[22]_i_10_n_0 ),
.I2(\rgb[22]_i_11_n_0 ),
.I3(xaddr[4]),
.I4(xaddr[1]),
.I5(xaddr[2]),
.O(\rgb[22]_i_8_n_0 ));
LUT6 #(
.INIT(64'hCCCC000088800000))
\rgb[22]_i_9
(.I0(xaddr[3]),
.I1(xaddr[6]),
.I2(xaddr[2]),
.I3(xaddr[1]),
.I4(xaddr[5]),
.I5(xaddr[4]),
.O(\rgb[22]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAAEAAAEAAAE))
\rgb[23]_i_1
(.I0(\rgb[23]_i_2_n_0 ),
.I1(\rgb[23]_i_3_n_0 ),
.I2(\rgb[23]_i_4_n_0 ),
.I3(\rgb[23]_i_5_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[23]_i_7_n_0 ),
.O(\rgb[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h1F))
\rgb[23]_i_10
(.I0(xaddr[3]),
.I1(xaddr[4]),
.I2(xaddr[5]),
.O(\rgb[23]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h7F))
\rgb[23]_i_11
(.I0(xaddr[8]),
.I1(xaddr[6]),
.I2(xaddr[7]),
.O(\rgb[23]_i_11_n_0 ));
LUT2 #(
.INIT(4'h1))
\rgb[23]_i_12
(.I0(yaddr[6]),
.I1(\rgb[14]_i_6_n_0 ),
.O(\rgb[23]_i_12_n_0 ));
LUT6 #(
.INIT(64'h0515555515155555))
\rgb[23]_i_13
(.I0(\rgb[23]_i_18_n_0 ),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\rgb[23]_i_17_n_0 ),
.I4(xaddr[6]),
.I5(xaddr[3]),
.O(\rgb[23]_i_13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h1))
\rgb[23]_i_14
(.I0(xaddr[9]),
.I1(xaddr[8]),
.O(\rgb[23]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h15))
\rgb[23]_i_15
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[2]),
.O(\rgb[23]_i_15_n_0 ));
LUT2 #(
.INIT(4'hE))
\rgb[23]_i_16
(.I0(xaddr[7]),
.I1(xaddr[6]),
.O(\rgb[23]_i_16_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'hE))
\rgb[23]_i_17
(.I0(xaddr[2]),
.I1(xaddr[1]),
.O(\rgb[23]_i_17_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hFE))
\rgb[23]_i_18
(.I0(xaddr[7]),
.I1(xaddr[8]),
.I2(xaddr[9]),
.O(\rgb[23]_i_18_n_0 ));
LUT6 #(
.INIT(64'h0000000000022222))
\rgb[23]_i_2
(.I0(\rgb[15]_i_4_n_0 ),
.I1(yaddr[6]),
.I2(yaddr[4]),
.I3(yaddr[3]),
.I4(yaddr[5]),
.I5(\rgb[23]_i_8_n_0 ),
.O(\rgb[23]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAAFFFB))
\rgb[23]_i_3
(.I0(\rgb[14]_i_3_n_0 ),
.I1(\rgb[15]_i_4_n_0 ),
.I2(\rgb[23]_i_9_n_0 ),
.I3(xaddr[9]),
.I4(\rgb[23]_i_7_n_0 ),
.O(\rgb[23]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00004440))
\rgb[23]_i_4
(.I0(xaddr[9]),
.I1(\rgb[23]_i_9_n_0 ),
.I2(\rgb[23]_i_10_n_0 ),
.I3(\rgb[23]_i_11_n_0 ),
.I4(\rgb[23]_i_12_n_0 ),
.O(\rgb[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0057FFFF00570057))
\rgb[23]_i_5
(.I0(yaddr[5]),
.I1(yaddr[3]),
.I2(yaddr[4]),
.I3(yaddr[6]),
.I4(\rgb[23]_i_12_n_0 ),
.I5(\rgb[23]_i_13_n_0 ),
.O(\rgb[23]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0155))
\rgb[23]_i_6
(.I0(yaddr[6]),
.I1(yaddr[4]),
.I2(yaddr[3]),
.I3(yaddr[5]),
.O(\rgb[23]_i_6_n_0 ));
LUT6 #(
.INIT(64'h40CC44CC44CC44CC))
\rgb[23]_i_7
(.I0(xaddr[6]),
.I1(\rgb[23]_i_14_n_0 ),
.I2(\rgb[23]_i_15_n_0 ),
.I3(xaddr[7]),
.I4(xaddr[4]),
.I5(xaddr[5]),
.O(\rgb[23]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFD500000000))
\rgb[23]_i_8
(.I0(\rgb[23]_i_10_n_0 ),
.I1(xaddr[2]),
.I2(xaddr[5]),
.I3(\rgb[23]_i_16_n_0 ),
.I4(xaddr[8]),
.I5(xaddr[9]),
.O(\rgb[23]_i_8_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFFFFE0))
\rgb[23]_i_9
(.I0(\rgb[23]_i_17_n_0 ),
.I1(xaddr[0]),
.I2(xaddr[3]),
.I3(xaddr[5]),
.I4(xaddr[4]),
.I5(\rgb[23]_i_11_n_0 ),
.O(\rgb[23]_i_9_n_0 ));
LUT5 #(
.INIT(32'h04770404))
\rgb[4]_i_1
(.I0(\rgb[6]_i_2_n_0 ),
.I1(\rgb[23]_i_6_n_0 ),
.I2(\rgb[23]_i_7_n_0 ),
.I3(\rgb[4]_i_2_n_0 ),
.I4(\rgb[5]_i_2_n_0 ),
.O(\rgb[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF2F2FFFFF202F))
\rgb[4]_i_2
(.I0(\rgb[22]_i_8_n_0 ),
.I1(\rgb[15]_i_4_n_0 ),
.I2(\rgb[23]_i_12_n_0 ),
.I3(\rgb[6]_i_5_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[23]_i_13_n_0 ),
.O(\rgb[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAFEAAAAAAAA))
\rgb[5]_i_1
(.I0(\rgb[7]_i_4_n_0 ),
.I1(\rgb[15]_i_2_n_0 ),
.I2(\rgb[15]_i_4_n_0 ),
.I3(\rgb[15]_i_3_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[5]_i_2_n_0 ),
.O(\rgb[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h7F7F0F7F))
\rgb[5]_i_2
(.I0(\rgb[14]_i_2_n_0 ),
.I1(\rgb[22]_i_8_n_0 ),
.I2(\rgb[23]_i_12_n_0 ),
.I3(\rgb[23]_i_7_n_0 ),
.I4(\rgb[7]_i_3_n_0 ),
.O(\rgb[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000F000FFFFF0045))
\rgb[6]_i_1
(.I0(\rgb[14]_i_3_n_0 ),
.I1(\rgb[7]_i_3_n_0 ),
.I2(\rgb[23]_i_7_n_0 ),
.I3(\rgb[6]_i_2_n_0 ),
.I4(\rgb[6]_i_3_n_0 ),
.I5(\rgb[23]_i_6_n_0 ),
.O(\rgb[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hEA))
\rgb[6]_i_2
(.I0(\rgb[14]_i_2_n_0 ),
.I1(\rgb[22]_i_8_n_0 ),
.I2(\rgb[7]_i_6_n_0 ),
.O(\rgb[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00FF0002))
\rgb[6]_i_3
(.I0(xaddr[9]),
.I1(\rgb[22]_i_7_n_0 ),
.I2(\rgb[6]_i_4_n_0 ),
.I3(\rgb[22]_i_6_n_0 ),
.I4(\rgb[6]_i_5_n_0 ),
.O(\rgb[6]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00000007))
\rgb[6]_i_4
(.I0(xaddr[2]),
.I1(xaddr[1]),
.I2(xaddr[3]),
.I3(xaddr[4]),
.I4(xaddr[5]),
.O(\rgb[6]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0057))
\rgb[6]_i_5
(.I0(xaddr[8]),
.I1(xaddr[7]),
.I2(xaddr[6]),
.I3(xaddr[9]),
.O(\rgb[6]_i_5_n_0 ));
LUT5 #(
.INIT(32'h0000222A))
\rgb[7]_i_1
(.I0(\rgb[7]_i_3_n_0 ),
.I1(yaddr[5]),
.I2(yaddr[3]),
.I3(yaddr[4]),
.I4(yaddr[6]),
.O(\rgb[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF000000FB))
\rgb[7]_i_2
(.I0(\rgb[7]_i_3_n_0 ),
.I1(\rgb[23]_i_7_n_0 ),
.I2(\rgb[14]_i_3_n_0 ),
.I3(\rgb[23]_i_4_n_0 ),
.I4(\rgb[23]_i_6_n_0 ),
.I5(\rgb[7]_i_4_n_0 ),
.O(\rgb[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h0000000D))
\rgb[7]_i_3
(.I0(xaddr[6]),
.I1(\rgb[7]_i_5_n_0 ),
.I2(xaddr[9]),
.I3(xaddr[8]),
.I4(xaddr[7]),
.O(\rgb[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000444))
\rgb[7]_i_4
(.I0(\rgb[23]_i_7_n_0 ),
.I1(\rgb[23]_i_6_n_0 ),
.I2(\rgb[7]_i_6_n_0 ),
.I3(\rgb[22]_i_8_n_0 ),
.I4(\rgb[14]_i_2_n_0 ),
.O(\rgb[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h1515155515155555))
\rgb[7]_i_5
(.I0(xaddr[5]),
.I1(xaddr[3]),
.I2(xaddr[4]),
.I3(xaddr[0]),
.I4(xaddr[2]),
.I5(xaddr[1]),
.O(\rgb[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000007F55))
\rgb[7]_i_6
(.I0(\rgb[15]_i_7_n_0 ),
.I1(xaddr[4]),
.I2(xaddr[5]),
.I3(\rgb[15]_i_5_n_0 ),
.I4(xaddr[7]),
.I5(xaddr[9]),
.O(\rgb[7]_i_6_n_0 ));
FDRE \rgb_reg[13]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[13]_i_1_n_0 ),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[14]_i_1_n_0 ),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[15]_i_1_n_0 ),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[21]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[21]_i_1_n_0 ),
.Q(rgb[7]),
.R(1'b0));
FDRE \rgb_reg[22]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[22]_i_1_n_0 ),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[23]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[23]_i_1_n_0 ),
.Q(rgb[9]),
.R(1'b0));
FDSE \rgb_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[4]_i_1_n_0 ),
.Q(rgb[0]),
.S(\rgb[7]_i_1_n_0 ));
FDSE \rgb_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[5]_i_1_n_0 ),
.Q(rgb[1]),
.S(\rgb[7]_i_1_n_0 ));
FDSE \rgb_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[6]_i_1_n_0 ),
.Q(rgb[2]),
.S(\rgb[7]_i_1_n_0 ));
FDSE \rgb_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(\rgb[7]_i_2_n_0 ),
.Q(rgb[3]),
.S(\rgb[7]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.03.2017 00:48:48
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Referenced from fpga4fun
//
//////////////////////////////////////////////////////////////////////////////////
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 1152000;
parameter Oversampling = 16; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
////////////////////////////////
reg [3:0] RxD_state = 0;
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
endmodule
////////////////////////////////////////////////////////
// dummy module used to be able to raise an assertion in Verilog
module ASSERTION_ERROR();
endmodule
////////////////////////////////////////////////////////
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 1152000;
parameter Oversampling = 16;
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
//////////////////////////////////////////////////////// |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__OR4B_BEHAVIORAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_BEHAVIORAL_V |
/*
* Copyright 2013-2016 Colin Weltin-Wu ([email protected])
* UC San Diego Integrated Signal Processing Group
*
* Licensed under GNU General Public License 3.0 or later.
* Some rights reserved. See LICENSE.
*
* spi_core.v
*
* General SPI interface
* Services the 4 SPI modes defined as (CPOL,CPHA)
* See: http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
*
* CPOL = 0: Base value of clock is 0
* -- CPHA = 0: SDI sampled on rising edge, SDO changes on falling edge
* -- CPHA = 1: SDO changes on rising edge, SDI sampled on falling edge
* CPOL = 1: Base value of clock is 1
* -- CPHA = 0: SDI sampled on falling edge, SDO changes on rising edge
* -- CPHA = 1: SDO changes on falling edge, SDI sampled on rising edge
*
* The signals i_epol, i_cpol, i_cpha configure the chip select polarity,
* the clock polarity, and the clock phase respectively.
*
* BITS_IN_BYTE determines how many bits form a single byte (serial to perallel
* conversion)
*
* NBIT_BIT_CTR needs to be ceil(log2(BITS_IN_BYTE)) e.g. the counter needs
* enough bits to be able to reach a count of BITS_IN_BYTE maximum count.
*
* NBIT_BYTE_CTR needs to be able to count up to the maximum number of bytes
* expected in one CS period. For example, if we are expecting up to 56 bytes,
* NBIT_BYTE_CTR needs to be at least 6.
*
* The output byte_num indicates the number of successfully received bytes
* on the SPI interface for the current chip select period.
*
* The output o_rx_valid goes high as the LSB of the current byte is latched;
* therefore it would make sense to delay rx_valid slightly before sampling
* o_data.
*
* The data on vi_data is latched into the SPI interface on the opposite
* polarity clock edge, when the bit counter is equal to the MSB.
*
*/
module spi_core (/*AUTOARG*/
// Outputs
o_sdo, o_drvb, o_spi_active, o_rx_valid, vo_byte_num, vo_data_rx,
// Inputs
i_rstb, i_cs, i_sck, i_sdi, i_epol, i_cpol, i_cpha, vi_data_tx
);
parameter BITS_IN_BYTE = 8;
parameter NBIT_BIT_CTR = 3;
parameter NBIT_BYTE_CTR = 3;
// Global reset
input i_rstb;
// spi wires
input i_cs; // Chip select
input i_sck; // SPI clock
input i_sdi; // SPI data input
output o_sdo; // SPI data output
output o_drvb; // Pad tristate driver
// spi configuration
input i_epol; // 1 = inverted chip select
input i_cpol; // SPI mode configuration
input i_cpha;
// parallel interface
output o_spi_active; // High with chip select
output o_rx_valid; // When high, indicates valid data
output [NBIT_BYTE_CTR-1:0] vo_byte_num; // Indicates number of bytes rx'd
input [BITS_IN_BYTE-1:0] vi_data_tx; // Data to be transmitted
output [BITS_IN_BYTE-1:0] vo_data_rx; // Data received
// Registered outputs
reg o_rx_valid;
reg [NBIT_BYTE_CTR-1:0] vo_byte_num;
/*
* Generate an active high chip select (regardless of configuration)
* sck_core is the scan clock which always latches in data on the rising
* edge, and cycles it out on the falling edge. When cpha=1, it is shifted
* by half a period.
*/
wire chip_select;
wire sck_core;
assign chip_select = i_rstb && (i_epol ^ i_cs);
assign o_spi_active = chip_select;
assign sck_core = i_cpha ^ i_cpol ^ i_sck;
// Bring pad driver low when chip select is enabled
assign o_drvb = !chip_select;
/*
* TX shift register and state machine. The inactive edge of the sck_core
* cycles the data output, and also changes the bit and byte counters.
*
* Data is only shifted out AFTER the first byte is received. As an SPI
* slave, it is not expected to send anything out during the first byte
*
* Byte counter is also incremented here to be aligned with the bit counter
*/
reg [BITS_IN_BYTE-1:0] rv_tx;
reg [NBIT_BIT_CTR-1:0] rv_tx_ptr;
always @( negedge sck_core or negedge chip_select ) begin : tx_fsm
if ( !chip_select ) begin
// Set data pointer to the MSB of the shift reg
rv_tx_ptr <= $unsigned(BITS_IN_BYTE - 1);
// Reset the byte counter
vo_byte_num <= 0;
// Reset the data in the shift register
rv_tx <= 0;
end else begin
// If the bit counter has reached 0, load in a new byte
if ( 0 == rv_tx_ptr ) begin
rv_tx <= vi_data_tx;
rv_tx_ptr <= $unsigned(BITS_IN_BYTE - 1);
vo_byte_num <= vo_byte_num + 1;
end else begin
rv_tx_ptr <= rv_tx_ptr - 1;
end
end // else: !if( !chip_select )
end // block: tx_fsm
// Point the output data to the correct bit in the tx_reg (not true shift)
assign o_sdo = rv_tx[rv_tx_ptr];
/*
* RX shift register state machine
* The shift register to receive data has one fewer bit than the actual
* data length since the LSB points directly to the i_sdi pin.
*
* The rx_valid flag is triggered on the last rising edge of sck_core
* within each byte. It is assumed the data at vo_data_rx will be latched
* by listening blocks on this edge.
*/
reg [BITS_IN_BYTE-2:0] rv_rx;
always @( posedge sck_core or negedge chip_select ) begin : rx_fsm
if ( !chip_select ) begin
// Clear RX register
rv_rx <= 0;
// Clear valid bit
o_rx_valid <= 0;
end else begin
// If this is the last bit, do not shift rx data, raise valid flag
if ( 0 == rv_tx_ptr ) begin
o_rx_valid <= 1;
end else begin
// RX is not valid
o_rx_valid <= 0;
// Begin clocking in data, MSB first
rv_rx[BITS_IN_BYTE-2:1] <= rv_rx[BITS_IN_BYTE-3:0];
rv_rx[0] <= i_sdi;
end // else: !if( 0 == rv_bit_ctr )
end // else: !if( !chip_select )
end // block: rx_fsm
assign vo_data_rx = {rv_rx,i_sdi};
endmodule
|
module SigmaDeltaFast #(
parameter WIDTH = 4,
parameter OUTLEN = (1 << WIDTH)
)
(
input clk, ///< System clock
input rst, ///< Reset, synchronous active high
input en, ///< Enable to run the modulator
input signed [WIDTH-1:0] in, ///< Input to modulator
output reg [OUTLEN-1:0] sdOut ///< Sigma delta stream, LSB=first sample, MSB=last sample
);
localparam DEPTH = 2**(2*WIDTH);
reg signed [WIDTH-1:0] feedback;
reg [WIDTH-1:0] fbLookup [DEPTH-1:0];
reg [OUTLEN-1:0] outLookup [DEPTH-1:0];
integer i;
integer j;
integer k;
reg [WIDTH-1:0] tempFb;
reg [WIDTH-1:0] tempIn;
initial begin
feedback = 'd0;
sdOut = 32'hAAAA_AAAA;
// i = input
// j = feedback
// k = bit in sequence
for (i=0; i<(2**WIDTH); i=i+1) begin
for (j=0; j<(2**WIDTH); j=j+1) begin
tempIn = i[WIDTH-1:0];
tempFb = j[WIDTH-1:0];
for (k=0; k<OUTLEN; k=k+1) begin
{outLookup[{i[WIDTH-1:0],j[WIDTH-1:0]}][k], tempFb} = tempFb + {~tempIn[WIDTH-1], tempIn[WIDTH-2:0]};
end
fbLookup[{i[WIDTH-1:0],j[WIDTH-1:0]}] = tempFb;
end
end
end
always @(posedge clk) begin
if (rst) begin
feedback <= 'd0;
sdOut <= 32'hAAAA_AAAA;
end
else if (en) begin
sdOut <= outLookup[{in, feedback}];
feedback <= fbLookup[{in,feedback}];
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 09:37:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_1_0/system_inverter_1_0_sim_netlist.v
// Design : system_inverter_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_1_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_1_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O211AI_PP_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211AI_PP_BLACKBOX_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Dynamic_Saturation_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Dynamic_Saturation_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/PI_Sat/Dynamic Saturation
// Hierarchy Level: 7
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Dynamic_Saturation_block
(
up,
u,
lo,
y,
sat_mode
);
input signed [17:0] up; // sfix18_En13
input signed [35:0] u; // sfix36_En23
input signed [17:0] lo; // sfix18_En13
output signed [35:0] y; // sfix36_En23
output sat_mode;
wire signed [35:0] LowerRelop1_1_cast; // sfix36_En23
wire LowerRelop1_relop1;
wire signed [35:0] UpperRelop_1_cast; // sfix36_En23
wire UpperRelop_relop1;
wire signed [35:0] lo_dtc; // sfix36_En23
wire signed [35:0] Switch_out1; // sfix36_En23
wire signed [35:0] up_dtc; // sfix36_En23
wire signed [35:0] Switch2_out1; // sfix36_En23
wire LowerRelop1_out1;
// <S24>/LowerRelop1
assign LowerRelop1_1_cast = {{8{up[17]}}, {up, 10'b0000000000}};
assign LowerRelop1_relop1 = (u > LowerRelop1_1_cast ? 1'b1 :
1'b0);
// <S24>/UpperRelop
assign UpperRelop_1_cast = {{8{lo[17]}}, {lo, 10'b0000000000}};
assign UpperRelop_relop1 = (u < UpperRelop_1_cast ? 1'b1 :
1'b0);
assign lo_dtc = {{8{lo[17]}}, {lo, 10'b0000000000}};
// <S24>/Switch
assign Switch_out1 = (UpperRelop_relop1 == 1'b0 ? u :
lo_dtc);
assign up_dtc = {{8{up[17]}}, {up, 10'b0000000000}};
// <S24>/Switch2
assign Switch2_out1 = (LowerRelop1_relop1 == 1'b0 ? Switch_out1 :
up_dtc);
assign y = Switch2_out1;
// <S24>/Logical Operator
assign LowerRelop1_out1 = LowerRelop1_relop1 | UpperRelop_relop1;
assign sat_mode = LowerRelop1_out1;
endmodule // velocityControlHdl_Dynamic_Saturation_block
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_PP_SYMBOL_V
`define SKY130_FD_SC_LS__EBUFN_PP_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_BLACKBOX_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_PP_V |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stage1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module stage1 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/bachelors.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/bachelors.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [4:0] sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
// altpll_component.clk0_divide_by = 2,
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
// altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
);
wire [15:0] wIP,wIP_temp,IMUL_Result;
wire [7:0] imul_result;
reg rWriteEnable,rBranchTaken;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg signed [32:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination;
wire signed [15:0] wSourceData0,wSourceData1,wImmediateValue;
wire [15:0] wIPInitialValue;
wire [15:0] oIMUL2;
IMUL2 Multiply4(
.iSourceData0(wSourceData0),
.iSourceData1(wSourceData1),
.oResult(oIMUL2)
);
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0 ),
.oDataOut1( wSourceData1 )
);
assign wIPInitialValue = (Reset) ? 8'b0 : wDestination;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1 ),
.Q( oLed )
);
//***************************** IMUL16 **********************************
IMUL16 #(16) MULT16
(
.A(wSourceData0),
.B(wSourceData1),
.oResult(IMUL_Result)
);
//************************************************************************
mult imultiplier( .opA(wSourceData0), .opB(wSourceData1), .result(imul_result));
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
end
//-------------------------------------
`SMUL:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 * wSourceData0;
end
//-------------------------------------
`IMUL:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult[7:0] <= imul_result;
rResult[15:8] <= 7'b0;
end
//-------------------------------------
`IMUL2: // Juan
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= oIMUL2;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
`IMUL16:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= IMUL_Result;
rBranchTaken <= 1'b0;
end
//-------------------------------------
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
module io1_sub(
/*AUTOARG*/);
wire [42:0] bscan_data; // boundary scan stitch
parameter bscan_count = 0;
assign bscan_data[0] = bscan_in;
/*
* Emacs template to auto instaniate MD[31:0] pads
*/
/*
autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@]),
.pin_in({SDRAM_DQ_in[@],SDRAM_DQ_in[@]}),
.pin_out(SDRAM_DQ_out[@]),
.pin_outen(SDRAM_DQ_outen),
.sdrmode(SDRAM_single_rate),
.hw_enb(SDRAM_upper_word_enb),
.ff_rptr(SDRAM_ddr_inff_sel),
.ff_wptr(ddr_inff_enbH),
.clk(data_strobeH),
.bscan_so(bscan_data[@ + 1]),
.bscan_si(bscan_data[@]),
.bscan_shift(BScanShift),
.bscan_clock(BScanClock),
.bscan_mode(BScanMode),
.bscan_update(BScanUpdate),
.bscan_outen(SDRAM_DQ_bscan_outen),
);
*/
autoinst_lopaz_srpad MD31_pad (/*AUTOINST*/
// Outputs
.pin_in ({SDRAM_DQ_in[31],SDRAM_DQ_in[31]}), // Templated
// Inouts
.pin (MD[31]), // Templated
// Inputs
.clk (data_strobeH), // Templated
.pin_out (SDRAM_DQ_out[31]), // Templated
.pin_outen (SDRAM_DQ_outen)); // Templated
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 1)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inouts
.pin (MD[1]), // Templated
// Inputs
.clk (clk),
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 2)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inouts
.pin (MD[2]), // Templated
// Inputs
.clk (clk),
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S18_1_V
`define SKY130_FD_SC_LP__DLYGATE4S18_1_V
/**
* dlygate4s18: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog wrapper for dlygate4s18 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlygate4s18.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlygate4s18_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlygate4s18 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlygate4s18_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlygate4s18 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S18_1_V
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_timers(
input clk,
input rst,
input [9:0] value_A,
input [7:0] value_B,
input load_A,
input load_B,
input clr_flag_A,
input clr_flag_B,
input set_run_A,
input set_run_B,
input clr_run_A,
input clr_run_B,
input enable_irq_A,
input enable_irq_B,
output flag_A,
output flag_B,
output overflow_A,
output irq_n
);
assign irq_n = ~( (flag_A&enable_irq_A) | (flag_B&enable_irq_B) );
jt51_timer #(.mult_width(6), .counter_width(10)) timer_A(
.clk ( clk ),
.rst ( rst ),
.start_value( value_A ),
.load ( load_A ),
.clr_flag ( clr_flag_A),
.set_run ( set_run_A ),
.clr_run ( clr_run_A ),
.flag ( flag_A ),
.overflow ( overflow_A)
);
jt51_timer #(.mult_width(10), .counter_width(8)) timer_B(
.clk ( clk ),
.rst ( rst ),
.start_value( value_B ),
.load ( load_B ),
.clr_flag ( clr_flag_B),
.set_run ( set_run_B ),
.clr_run ( clr_run_B ),
.flag ( flag_B ),
.overflow ( )
);
endmodule
module jt51_timer #(parameter counter_width = 10, mult_width=5 )
(
input clk,
input rst,
input [counter_width-1:0] start_value,
input load,
input clr_flag,
input set_run,
input clr_run,
output reg flag,
output reg overflow
);
reg run;
reg [ mult_width-1:0] mult;
reg [counter_width-1:0] cnt;
always@(posedge clk)
if( clr_flag || rst)
flag <= 1'b0;
else if(overflow) flag<=1'b1;
always@(posedge clk)
if( clr_run || rst)
run <= 1'b0;
else if(set_run || load) run<=1'b1;
reg [mult_width+counter_width-1:0] next, init;
always @(*) begin
{overflow, next } = { 1'b0, cnt, mult } + 1'b1;
init = { start_value, { (mult_width){1'b0} } };
end
always @(posedge clk) begin : counter
if( load ) begin
mult <= { (mult_width){1'b0} };
cnt <= start_value;
end
else if( run )
{ cnt, mult } <= overflow ? init : next;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_1_V
`define SKY130_FD_SC_HD__AND2B_1_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_1_V
|
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <[email protected]>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// Module for receiving RGB565 pixel data from OV camera.
//
//##################################################################################################
module RGB656Receive (d_i, vsync_i, href_i, pclk_i, rst_i, pixelReady_o, pixel_o);
input [7:0] d_i; // D0 - D7
input vsync_i; // VSYNC
input href_i; // HREF
input pclk_i; // PCLK
input rst_i; // 0 - Reset.
output reg pixelReady_o; // Indicates that a pixel has been received.
output reg [15:0] pixel_o; // RGB565 pixel.
reg odd = 0;
reg frameValid = 0;
always @(posedge pclk_i) begin
pixelReady_o <= 0;
if (rst_i == 0) begin
odd <= 0;
frameValid <= 0;
end else begin
if (frameValid == 1 && vsync_i == 0 && href_i == 1) begin
if (odd == 0) begin
pixel_o[15:8] <= d_i;
end else begin
pixel_o[7:0] <= d_i;
pixelReady_o <= 1;
end
odd <= ~odd;
// skip inital frame in case we started receiving in the middle of it
end else if (frameValid == 0 && vsync_i == 1) begin
frameValid <= 1;
end
end
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/1ps
module system_tb();
reg sys_clk;
reg resetin;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
initial begin
resetin = 1'b0;
#200 resetin = 1'b1;
end
wire [24:0] flash_adr;
reg [31:0] flash_d;
reg [31:0] flash[0:32767];
initial $readmemh("bios.rom", flash);
always @(flash_adr) #110 flash_d = flash[flash_adr/2];
system system(
.clkin(sys_clk),
.resetin(resetin),
.flash_adr(flash_adr),
.flash_d(flash_d),
.uart_rxd(),
.uart_txd()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A32O_FUNCTIONAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_FUNCTIONAL_V |
`timescale 1ns/1ns
module chain_tb();
wire clk_20;
sim_clk #(20) sim_clk_20_inst(.clk(clk_20));
wire clk_25;
sim_clk #(25) sim_clk_25_inst(.clk(clk_25));
wire clk_50;
sim_clk #(50) sim_clk_50_inst(.clk(clk_50));
wire clk_48;
sim_clk #(48) sim_clk_48_inst(.clk(clk_48));
wire clk_100;
sim_clk #(100) sim_clk_100_inst(.clk(clk_100));
localparam CHAIN_LEN = 3;
wire [CHAIN_LEN-1:0] enet_rst, enet_mdc, enet_mdio;
wire [CHAIN_LEN*4-1:0] enet_leds;
wire [CHAIN_LEN*2-1:0] enet_txclk, enet_txen, enet_rxcclk, enet_rxdv;
wire [CHAIN_LEN*4-1:0] enet_txd, enet_rxd;
wire [CHAIN_LEN*16-1:0] outb;
wire [CHAIN_LEN*5-1:0] usb_oe, usb_rcv, usb_pwr, usb_vp, usb_vm;
wire [CHAIN_LEN*3-1:0] mosfet_hi, mosfet_lo, mclk;
reg [CHAIN_LEN*3-1:0] mdata;
wire [CHAIN_LEN-1:0] mosfet_en;
wire [CHAIN_LEN*9-1:0] mcu_io;
wire [CHAIN_LEN-1:0] led;
//assign enet_mdc = {CHAIN_LEN{1'b0}};
//assign enet_mdc = {CHAIN_LEN{1'bz}};
meganode meganodes[CHAIN_LEN-1:0]
(.*);
fake_rmii_phy #(.INPUT_FILE_NAME("chain_tb.dat")) sim_rmii_phy_0_0
(.refclk(clk_50), .rst(1'b1),
.txd(enet_txd[1:0]), .txen(enet_txen[0]),
.rxd(enet_rxd[1:0]), .rxdv(enet_rxdv[0]));
fake_rmii_phy #(.INPUT_FILE_NAME("chain_tb.dat")) sim_rmii_phy_0_1
(.refclk(clk_50), .rst(1'b1),
.txd(enet_txd[3:2]), .txen(enet_txen[1]),
.rxd(enet_rxd[3:2]), .rxdv(enet_rxdv[1]));
fake_rmii_phy #(.INPUT_FILE_NAME("chain_tb.dat")) sim_rmii_phy_1_0
(.refclk(clk_50), .rst(1'b1),
.txd(enet_txd[5:4]), .txen(enet_txen[2]),
.rxd(enet_rxd[5:4]), .rxdv(enet_rxdv[2]));
fake_rmii_phy #(.INPUT_FILE_NAME("chain_tb.dat")) sim_rmii_phy_1_1
(.refclk(clk_50), .rst(1'b1),
.txd(enet_txd[7:6]), .txen(enet_txen[3]),
.rxd(enet_rxd[7:6]), .rxdv(enet_rxdv[3]));
fake_rmii_phy #(.INPUT_FILE_NAME("chain_tb.dat")) sim_rmii_phy_2_0
(.refclk(clk_50), .rst(1'b1),
.txd(enet_txd[9:8]), .txen(enet_txen[4]),
.rxd(enet_rxd[9:8]), .rxdv(enet_rxdv[4]));
fake_rmii_phy #(.INPUT_FILE_NAME("chain_tb.dat")) sim_rmii_phy_2_1
(.refclk(clk_50), .rst(1'b1),
.txd(enet_txd[11:10]), .txen(enet_txen[5]),
.rxd(enet_rxd[11:10]), .rxdv(enet_rxdv[5]));
initial begin
$dumpfile("chain.lxt");
$dumpvars();
#200000 $finish();
end
endmodule
|
//
// clk_reset.v -- clock and reset generator
//
module clk_reset(clk_in, reset_inout_n,
sdram_clk, sdram_fb,
clk, clk_ok, reset);
input clk_in;
inout reset_inout_n;
output sdram_clk;
input sdram_fb;
output clk;
output clk_ok;
output reset;
wire clk_in_buf;
wire int_clk;
wire int_locked;
wire ext_rst_n;
wire ext_fb;
wire ext_locked;
reg reset_p_n;
reg reset_s_n;
reg [23:0] reset_counter;
wire reset_counting;
//------------------------------------------------------------
IBUFG clk_in_buffer(
.I(clk_in),
.O(clk_in_buf)
);
DCM int_dcm(
.CLKIN(clk_in_buf),
.CLKFB(clk),
.RST(1'b0),
.CLK0(int_clk),
.LOCKED(int_locked)
);
BUFG int_clk_buffer(
.I(int_clk),
.O(clk)
);
//------------------------------------------------------------
SRL16 ext_dll_rst_gen(
.CLK(clk_in_buf),
.D(int_locked),
.Q(ext_rst_n),
.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1)
);
defparam ext_dll_rst_gen.INIT = 16'h0000;
//------------------------------------------------------------
IBUFG ext_fb_buffer(
.I(sdram_fb),
.O(ext_fb)
);
DCM ext_dcm(
.CLKIN(clk_in_buf),
.CLKFB(ext_fb),
.RST(~ext_rst_n),
.CLK0(sdram_clk),
.LOCKED(ext_locked)
);
assign clk_ok = int_locked & ext_locked;
//------------------------------------------------------------
assign reset_counting = (reset_counter == 24'hFFFFFF) ? 0 : 1;
assign reset_inout_n = (reset_counter[23] == 0) ? 1'b0 : 1'bz;
always @(posedge clk_in_buf) begin
reset_p_n <= reset_inout_n;
reset_s_n <= reset_p_n;
if (reset_counting == 1) begin
reset_counter <= reset_counter + 1;
end else begin
if (~reset_s_n | ~clk_ok) begin
reset_counter <= 24'h000000;
end
end
end
assign reset = reset_counting;
endmodule
|
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_encoder_decoder_wrapper #
( parameter
CFG_LOCAL_DATA_WIDTH = 80,
CFG_LOCAL_ADDR_WIDTH = 32,
CFG_DWIDTH_RATIO = 2,
CFG_MEM_IF_DQ_WIDTH = 40,
CFG_MEM_IF_DQS_WIDTH = 5,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_MULTIPLES = 1,
CFG_ECC_ENC_REG = 0,
CFG_ECC_DEC_REG = 0,
CFG_ECC_RDATA_REG = 0,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_GEN_SBE = 1,
CFG_PORT_WIDTH_GEN_DBE = 1,
CFG_PORT_WIDTH_ENABLE_INTR = 1,
CFG_PORT_WIDTH_MASK_SBE_INTR = 1,
CFG_PORT_WIDTH_MASK_DBE_INTR = 1,
CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR = 1,
CFG_PORT_WIDTH_CLR_INTR = 1,
STS_PORT_WIDTH_SBE_ERROR = 1,
STS_PORT_WIDTH_DBE_ERROR = 1,
STS_PORT_WIDTH_SBE_COUNT = 8,
STS_PORT_WIDTH_DBE_COUNT = 8,
STS_PORT_WIDTH_CORR_DROP_ERROR = 1,
STS_PORT_WIDTH_CORR_DROP_COUNT = 8
)
(
ctl_clk,
ctl_reset_n,
// MMR Interface
cfg_interface_width,
cfg_enable_ecc,
cfg_gen_sbe,
cfg_gen_dbe,
cfg_enable_intr,
cfg_mask_sbe_intr,
cfg_mask_dbe_intr,
cfg_mask_corr_dropped_intr,
cfg_clr_intr,
// Wdata & Rdata Interface Inputs
wdatap_dm,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
rdatap_rcvd_addr,
rdatap_rcvd_cmd,
rdatap_rcvd_corr_dropped,
// AFI Interface Inputs
afi_rdata,
afi_rdata_valid,
// Wdata & Rdata Interface Outputs
ecc_rdata,
ecc_rdata_valid,
// AFI Inteface Outputs
ecc_dm,
ecc_wdata,
// ECC Error Information
ecc_sbe,
ecc_dbe,
ecc_code,
ecc_interrupt,
// MMR ECC Information
sts_sbe_error,
sts_dbe_error,
sts_sbe_count,
sts_dbe_count,
sts_err_addr,
sts_corr_dropped,
sts_corr_dropped_count,
sts_corr_dropped_addr
);
//--------------------------------------------------------------------------------------------------------
//
// Important Note:
//
// This block is coded with the following consideration in mind
// - Parameter
// - maximum LOCAL_DATA_WIDTH will be (40 * DWIDTH_RATIO)
// - maximum ECC_DATA_WIDTH will be (40 * DWIDTH_RATIO)
// - MMR configuration
// - ECC option disabled:
// - maximum DQ width is 40
// - maximum LOCAL_DATA width is (40 * DWIDTH_RATIO)
// - WDATAP_DATA and ECC_DATA size will match (no ECC code)
// - ECC option enabled:
// - maximum DQ width is 40
// - maximum LOCAL_DATA width is (32 * DWIDTH_RATIO)
// - WDATAP_DATA width will be (8 * DWIDTH_RATIO) lesser than ECC_DATA (ECC code)
//
// Block level diagram
// -----------------------------------
// Write Data Path (Per DRATE)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// Local Write Data | Data | | | | |
// ---- 40 bits ---->| Mask |---- 32 bits ---->| Encoder |---- 40 bits ---->| ECC MUX |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//
// -----------------------------------
// Read Data Path (Per DRATE)
// -----------------------------------
// __________ ___________ ___________
// | | | | | |
// AFI Read Data | Data | | | | |
// ---- 40 bits ---->| Mask |---- 40 bits ---->| Decoder |---- 32 bits ---->| ECC MUX |---- 40 bits ---->
// | | | | | | |
// | |__________| |___________| |___________|
// | ^
// |---------------------------------- 40 bits ---------------------------|
//
//--------------------------------------------------------------------------------------------------------
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_ECC_DATA_WIDTH = CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_ECC_DM_WIDTH = CFG_ECC_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS;
localparam CFG_LOCAL_DATA_PER_WORD_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_LOCAL_DM_PER_WORD_WIDTH = CFG_LOCAL_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DATA_PER_WORD_WIDTH = CFG_ECC_DATA_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_ECC_DM_PER_WORD_WIDTH = CFG_ECC_DM_WIDTH / CFG_ECC_MULTIPLES;
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_LOCAL_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
localparam CFG_MMR_LOCAL_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
// The following 2 parameters should match!
localparam CFG_ENCODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH; // supports only 24, 40 and 72
localparam CFG_DECODER_DATA_WIDTH = CFG_ECC_DATA_PER_WORD_WIDTH; // supports only 24, 40 and 72
input ctl_clk;
input ctl_reset_n;
// MMR Interface
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_GEN_SBE - 1 : 0] cfg_gen_sbe;
input [CFG_PORT_WIDTH_GEN_DBE - 1 : 0] cfg_gen_dbe;
input [CFG_PORT_WIDTH_ENABLE_INTR - 1 : 0] cfg_enable_intr;
input [CFG_PORT_WIDTH_MASK_SBE_INTR - 1 : 0] cfg_mask_sbe_intr;
input [CFG_PORT_WIDTH_MASK_DBE_INTR - 1 : 0] cfg_mask_dbe_intr;
input [CFG_PORT_WIDTH_MASK_CORR_DROPPED_INTR - 1 : 0] cfg_mask_corr_dropped_intr;
input [CFG_PORT_WIDTH_CLR_INTR - 1 : 0] cfg_clr_intr;
// Wdata & Rdata Interface Inputs
input [CFG_LOCAL_DM_WIDTH - 1 : 0] wdatap_dm;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_partial_data;
input [CFG_LOCAL_DATA_WIDTH - 1 : 0] wdatap_rmw_correct_data;
input wdatap_rmw_partial;
input wdatap_rmw_correct;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
input [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
input [CFG_LOCAL_ADDR_WIDTH - 1 : 0] rdatap_rcvd_addr;
input rdatap_rcvd_cmd;
input rdatap_rcvd_corr_dropped;
// AFI Interface Inputs
input [CFG_ECC_DATA_WIDTH - 1 : 0] afi_rdata;
input [CFG_DWIDTH_RATIO / 2 - 1 : 0] afi_rdata_valid;
// Wdata & Rdata Interface Outputs
output [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
output ecc_rdata_valid;
// AFI Inteface Outputs
output [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
output [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
// ECC Error Information
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
output [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
output ecc_interrupt;
// MMR ECC Information
output [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
output [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
output [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
output [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
output [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
output [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
output [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// Output registers
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] ecc_rdata;
reg ecc_rdata_valid;
reg [CFG_ECC_DM_WIDTH - 1 : 0] ecc_dm;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] ecc_wdata;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] ecc_dbe;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] ecc_code;
reg ecc_interrupt;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] sts_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] sts_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] sts_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] sts_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_err_addr;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] sts_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] sts_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] sts_corr_dropped_addr;
// Common
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_local_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
reg [CFG_MMR_LOCAL_DM_WIDTH - 1 : 0] cfg_local_dm_width;
// Input Logic
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_encoder_input_rmw_correct_data;
reg int_encoder_input_rmw_partial;
reg int_encoder_input_rmw_correct;
reg wdatap_rmw_partial_r;
reg wdatap_rmw_correct_r;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg int_decoder_input_data_valid;
// Output Logic
reg [CFG_ECC_MULTIPLES - 1 : 0] int_sbe;
reg [CFG_ECC_MULTIPLES - 1 : 0] int_dbe;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm;
reg [CFG_ECC_DM_WIDTH - 1 : 0] int_encoder_output_dm_r;
wire [CFG_ECC_MULTIPLES - 1 : 0] int_decoder_output_data_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] int_encoder_output_data_r;
wire [CFG_LOCAL_DATA_WIDTH - 1 : 0] int_decoder_output_data;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] int_ecc_code;
// ECC specific logic
reg [1 : 0] inject_data_error;
reg int_sbe_detected;
reg int_dbe_detected;
wire int_be_detected;
reg int_sbe_store;
reg int_dbe_store;
reg int_sbe_valid;
reg int_dbe_valid;
reg int_sbe_valid_r;
reg int_dbe_valid_r;
reg int_ecc_interrupt;
wire int_interruptable_error_detected;
reg [STS_PORT_WIDTH_SBE_ERROR - 1 : 0] int_sbe_error;
reg [STS_PORT_WIDTH_DBE_ERROR - 1 : 0] int_dbe_error;
reg [STS_PORT_WIDTH_SBE_COUNT - 1 : 0] int_sbe_count;
reg [STS_PORT_WIDTH_DBE_COUNT - 1 : 0] int_dbe_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_err_addr ;
reg [STS_PORT_WIDTH_CORR_DROP_ERROR - 1 : 0] int_corr_dropped;
reg [STS_PORT_WIDTH_CORR_DROP_COUNT - 1 : 0] int_corr_dropped_count;
reg [CFG_LOCAL_ADDR_WIDTH - 1 : 0] int_corr_dropped_addr ;
reg int_corr_dropped_detected;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// DRAM and local data width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_data_width <= 0;
end
else
begin
// Important note, if we set memory interface width (DQ width) to 8 and enable_ecc to 1,
// this will result in local data width of 0, this case is not supported
// this must be checked with assertion so that this case will not happen in regression
if (cfg_enable_ecc)
begin
cfg_local_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH;
end
else
begin
cfg_local_data_width <= cfg_interface_width;
end
end
end
//----------------------------------------------------------------------------------------------------
// DRAM and local be width
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_local_dm_width <= 0;
end
else
begin
cfg_local_dm_width <= cfg_local_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_rmw_partial_r <= 1'b0;
wdatap_rmw_correct_r <= 1'b0;
end
else
begin
wdatap_rmw_partial_r <= wdatap_rmw_partial;
wdatap_rmw_correct_r <= wdatap_rmw_correct;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_encoder_output_data_r <= 0;
int_encoder_output_dm_r <= 0;
end
else
begin
int_encoder_output_data_r <= int_encoder_output_data;
int_encoder_output_dm_r <= int_encoder_output_dm;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [ENC] Common
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Write data & byte enable from wdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_encoder_input_data = wdatap_data;
int_encoder_input_rmw_partial_data = wdatap_rmw_partial_data;
int_encoder_input_rmw_correct_data = wdatap_rmw_correct_data;
if (CFG_ECC_ENC_REG)
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial_r;
int_encoder_input_rmw_correct = wdatap_rmw_correct_r;
end
else
begin
int_encoder_input_rmw_partial = wdatap_rmw_partial;
int_encoder_input_rmw_correct = wdatap_rmw_correct;
end
end
generate
genvar i_drate;
for (i_drate = 0;i_drate < CFG_ECC_MULTIPLES;i_drate = i_drate + 1)
begin : encoder_input_dm_mux_per_dm_drate
wire [CFG_LOCAL_DM_PER_WORD_WIDTH-1:0] int_encoder_input_dm = wdatap_dm [(i_drate + 1) * CFG_LOCAL_DM_PER_WORD_WIDTH - 1 : i_drate * CFG_LOCAL_DM_PER_WORD_WIDTH];
wire int_encoder_input_dm_all_zeros = ~(|int_encoder_input_dm);
always @ (*)
begin
if (cfg_enable_ecc)
begin
if (int_encoder_input_dm_all_zeros)
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b1}},int_encoder_input_dm};
end
end
else
begin
int_encoder_output_dm [ ((i_drate + 1) * CFG_ECC_DM_PER_WORD_WIDTH) - 1 : (i_drate * CFG_ECC_DM_PER_WORD_WIDTH)] = {{(CFG_ECC_DM_PER_WORD_WIDTH - CFG_LOCAL_DM_PER_WORD_WIDTH){1'b0}},int_encoder_input_dm};
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Read data & read data valid from AFI
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
int_decoder_input_data = afi_rdata;
end
always @ (*)
begin
int_decoder_input_data_valid = afi_rdata_valid [0];
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Write data & byte enable to AFI interface
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_wdata = int_encoder_output_data;
end
always @ (*)
begin
if (CFG_ECC_ENC_REG)
begin
ecc_dm = int_encoder_output_dm_r;
end
else
begin
ecc_dm = int_encoder_output_dm;
end
end
//----------------------------------------------------------------------------------------------------
// Read data to rdata_path
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
ecc_rdata = int_decoder_output_data;
end
always @ (*)
begin
ecc_rdata_valid = |int_decoder_output_data_valid;
end
//----------------------------------------------------------------------------------------------------
// ECC specific logic
//----------------------------------------------------------------------------------------------------
// Single bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_sbe = int_sbe;
else
ecc_sbe = 0;
end
// Double bit error
always @ (*)
begin
if (cfg_enable_ecc)
ecc_dbe = int_dbe;
else
ecc_dbe = 0;
end
// ECC code
always @ (*)
begin
if (cfg_enable_ecc)
ecc_code = int_ecc_code;
else
ecc_code = 0;
end
// Interrupt signal
always @ (*)
begin
ecc_interrupt = int_ecc_interrupt;
end
//----------------------------------------------------------------------------------------------------
// MMR ECC specific logic
//----------------------------------------------------------------------------------------------------
// Single bit error
always @ (*)
begin
sts_sbe_error = int_sbe_error;
end
// Double bit error
always @ (*)
begin
sts_dbe_error = int_dbe_error;
end
// Single bit error count
always @ (*)
begin
sts_sbe_count = int_sbe_count;
end
// Double bit error count
always @ (*)
begin
sts_dbe_count = int_dbe_count;
end
// Error address
always @ (*)
begin
sts_err_addr = int_err_addr;
end
// Correctable Error dropped
always @ (*)
begin
sts_corr_dropped = int_corr_dropped;
end
// Single bit error count
always @ (*)
begin
sts_corr_dropped_count = int_corr_dropped_count;
end
// Correctable Error dropped address
always @ (*)
begin
sts_corr_dropped_addr = int_corr_dropped_addr;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Output Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Encoder / Decoder Instantiation
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Encoder
//----------------------------------------------------------------------------------------------------
generate
genvar m_drate;
for (m_drate = 0;m_drate < CFG_ECC_MULTIPLES;m_drate = m_drate + 1)
begin : encoder_inst_per_drate
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_partial_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_partial_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] input_rmw_correct_data = {{CFG_ENCODER_DATA_WIDTH - CFG_LOCAL_DATA_PER_WORD_WIDTH{1'b0}}, int_encoder_input_rmw_correct_data [(m_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH]};
wire [CFG_ECC_CODE_WIDTH - 1 : 0] input_ecc_code = wdatap_ecc_code [(m_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : m_drate * CFG_ECC_CODE_WIDTH];
wire input_ecc_code_overwrite = wdatap_ecc_code_overwrite [m_drate];
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_partial_data;
wire [CFG_ENCODER_DATA_WIDTH - 1 : 0] output_rmw_correct_data;
always @ (*)
begin
if (int_encoder_input_rmw_partial)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_partial_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_partial_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else if (int_encoder_input_rmw_correct)
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_rmw_correct_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_rmw_correct_data [1 : 0] ^ inject_data_error [1 : 0])};
end
else
begin
int_encoder_output_data [(m_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : m_drate * CFG_ECC_DATA_PER_WORD_WIDTH] = {output_data [CFG_ECC_DATA_PER_WORD_WIDTH - 1 : 2], (output_data [1 : 0] ^ inject_data_error [1 : 0])};
end
end
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ECC code overwrite feature is only needed during RMW correct phase
.output_data (output_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_partial_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_partial_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (1'b0 ), // ECC code overwrite feature is only needed during RMW correct phase
.output_data (output_rmw_partial_data )
);
alt_mem_ddrx_ecc_encoder #
(
.CFG_DATA_WIDTH (CFG_ENCODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
rmw_correct_encoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_rmw_correct_data ),
.input_ecc_code (input_ecc_code ),
.input_ecc_code_overwrite (input_ecc_code_overwrite ),
.output_data (output_rmw_correct_data )
);
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Decoder
//----------------------------------------------------------------------------------------------------
generate
genvar n_drate;
for (n_drate = 0;n_drate < CFG_ECC_MULTIPLES;n_drate = n_drate + 1)
begin : decoder_inst_per_drate
wire err_corrected;
wire err_detected;
wire err_fatal;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] input_data = {{CFG_DECODER_DATA_WIDTH - CFG_ECC_DATA_PER_WORD_WIDTH{1'b0}}, int_decoder_input_data [(n_drate + 1) * CFG_ECC_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_ECC_DATA_PER_WORD_WIDTH]};
wire input_data_valid = int_decoder_input_data_valid;
wire [CFG_DECODER_DATA_WIDTH - 1 : 0] output_data;
wire output_data_valid;
wire [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
assign int_decoder_output_data [(n_drate + 1) * CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : n_drate * CFG_LOCAL_DATA_PER_WORD_WIDTH] = output_data [CFG_LOCAL_DATA_PER_WORD_WIDTH - 1 : 0];
assign int_ecc_code [(n_drate + 1) * CFG_ECC_CODE_WIDTH - 1 : n_drate * CFG_ECC_CODE_WIDTH ] = output_ecc_code;
assign int_decoder_output_data_valid [n_drate] = output_data_valid;
alt_mem_ddrx_ecc_decoder #
(
.CFG_DATA_WIDTH (CFG_DECODER_DATA_WIDTH ),
.CFG_ECC_CODE_WIDTH (CFG_ECC_CODE_WIDTH ),
.CFG_ECC_DEC_REG (CFG_ECC_DEC_REG ),
.CFG_ECC_RDATA_REG (CFG_ECC_RDATA_REG ),
.CFG_MMR_DRAM_DATA_WIDTH (CFG_MMR_DRAM_DATA_WIDTH ),
.CFG_MMR_LOCAL_DATA_WIDTH (CFG_MMR_LOCAL_DATA_WIDTH ),
.CFG_PORT_WIDTH_ENABLE_ECC (CFG_PORT_WIDTH_ENABLE_ECC )
)
decoder_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_local_data_width (cfg_local_data_width ),
.cfg_dram_data_width (cfg_dram_data_width ),
.cfg_enable_ecc (cfg_enable_ecc ),
.input_data (input_data ),
.input_data_valid (input_data_valid ),
.output_data (output_data ),
.output_data_valid (output_data_valid ),
.output_ecc_code (output_ecc_code ),
.err_corrected (err_corrected ),
.err_detected (err_detected ),
.err_fatal (err_fatal )
);
// Error detection
always @ (*)
begin
if (err_detected)
begin
if (err_corrected)
begin
int_sbe [n_drate] = 1'b1;
int_dbe [n_drate] = 1'b0;
end
else if (err_fatal)
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b1;
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
else
begin
int_sbe [n_drate] = 1'b0;
int_dbe [n_drate] = 1'b0;
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Encoder / Decoder Instantiation
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] ECC Specific Logic
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Common Logic
//----------------------------------------------------------------------------------------------------
// Below information valid on same clock, when rdatap_rcvd_cmd is asserted (at end of every dram command)
// - int_sbe_detected
// - int_dbe_detected
// - int_be_detected
// - int_corr_dropped_detected
// - rdatap_rcvd_addr
//
// see SPR:362993
always @ (*)
begin
int_sbe_valid = |int_sbe & ecc_rdata_valid;
int_dbe_valid = |int_dbe & ecc_rdata_valid;
int_sbe_detected = ( int_sbe_store | int_sbe_valid_r ) & rdatap_rcvd_cmd;
int_dbe_detected = ( int_dbe_store | int_dbe_valid_r ) & rdatap_rcvd_cmd;
int_corr_dropped_detected = rdatap_rcvd_corr_dropped;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_sbe_valid_r <= 0;
int_dbe_valid_r <= 0;
int_sbe_store <= 0;
int_dbe_store <= 0;
end
else
begin
int_sbe_valid_r <= int_sbe_valid;
int_dbe_valid_r <= int_dbe_valid;
int_sbe_store <= (int_sbe_store | int_sbe_valid_r) & ~rdatap_rcvd_cmd;
int_dbe_store <= (int_dbe_store | int_dbe_valid_r) & ~rdatap_rcvd_cmd;
end
end
//----------------------------------------------------------------------------------------------------
// Error Innjection Logic
//----------------------------------------------------------------------------------------------------
// Data error injection, this will cause output data to be injected with single/double bit error
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
inject_data_error <= 0;
end
else
begin
// Put DBE 1st so that when user sets both gen_sbe and gen_dbe, DBE will have higher priority
if (cfg_gen_dbe)
inject_data_error <= 2'b11;
else if (cfg_gen_sbe)
inject_data_error <= 2'b01;
else
inject_data_error <= 2'b00;
end
end
//----------------------------------------------------------------------------------------------------
// Single bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_sbe_detected)
int_sbe_error <= 1'b1;
else if (cfg_clr_intr)
int_sbe_error <= 1'b0;
end
else
begin
int_sbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Single bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_sbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_sbe_detected)
int_sbe_count <= 1;
else
int_sbe_count <= 0;
else if (int_sbe_detected)
int_sbe_count <= int_sbe_count + 1'b1;
end
else
begin
int_sbe_count <= {STS_PORT_WIDTH_SBE_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Double bit error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_error <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_dbe_detected)
int_dbe_error <= 1'b1;
else if (cfg_clr_intr)
int_dbe_error <= 1'b0;
end
else
begin
int_dbe_error <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Double bit error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_dbe_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_dbe_detected)
int_dbe_count <= 1;
else
int_dbe_count <= 0;
else if (int_dbe_detected)
int_dbe_count <= int_dbe_count + 1'b1;
end
else
begin
int_dbe_count <= {STS_PORT_WIDTH_DBE_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_err_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_be_detected)
int_err_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_err_addr <= 0;
end
else
begin
int_err_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped <= 1'b0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped <= 1'b1;
else if (cfg_clr_intr)
int_corr_dropped <= 1'b0;
end
else
begin
int_corr_dropped <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error count
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_count <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (cfg_clr_intr)
if (int_corr_dropped_detected)
int_corr_dropped_count <= 1;
else
int_corr_dropped_count <= 0;
else if (int_corr_dropped_detected)
int_corr_dropped_count <= int_corr_dropped_count + 1'b1;
end
else
begin
int_corr_dropped_count <= {STS_PORT_WIDTH_CORR_DROP_COUNT{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Dropped Correctable Error address
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_corr_dropped_addr <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
if (int_corr_dropped_detected)
int_corr_dropped_addr <= rdatap_rcvd_addr;
else if (cfg_clr_intr)
int_corr_dropped_addr <= 0;
end
else
begin
int_corr_dropped_addr <= {CFG_LOCAL_ADDR_WIDTH{1'b0}};
end
end
end
//----------------------------------------------------------------------------------------------------
// Interrupt logic
//----------------------------------------------------------------------------------------------------
assign int_interruptable_error_detected = (int_sbe_detected & ~cfg_mask_sbe_intr) | (int_dbe_detected & ~cfg_mask_dbe_intr) | (int_corr_dropped_detected & ~cfg_mask_corr_dropped_intr);
assign int_be_detected = int_sbe_detected | int_dbe_detected;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_interrupt <= 1'b0;
end
else
begin
if (cfg_enable_ecc && cfg_enable_intr)
begin
if (int_interruptable_error_detected)
int_ecc_interrupt <= 1'b1;
else if (cfg_clr_intr)
int_ecc_interrupt <= 1'b0;
end
else
begin
int_ecc_interrupt <= 1'b0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] ECC Specific Logic
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
//-----------------------------------------------------------------------------
// Jonathan Westhues, March 2006
// iZsh <izsh at fail0verflow.com>, June 2014
// Piwi, Feb 2019
// Anon, 2019
//-----------------------------------------------------------------------------
// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
// Note: the definitions here are without shifts
// Commands:
`define FPGA_CMD_SET_CONFREG 1
`define FPGA_CMD_SET_DIVISOR 2
`define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD 3
// Major modes:
`define FPGA_MAJOR_MODE_LF_READER 0
`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
`define FPGA_MAJOR_MODE_LF_ADC 3
// Options for LF_READER
`define FPGA_LF_ADC_READER_FIELD 1
// Options for LF_EDGE_DETECT
`define FPGA_LF_EDGE_DETECT_READER_FIELD 1
`define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 2
`include "lo_read.v"
`include "lo_passthru.v"
`include "lo_edge_detect.v"
`include "lo_adc.v"
`include "util.v"
`include "clk_divider.v"
module fpga_lf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
/*
Attempt to write up how its hooked up. Iceman 2020.
Communication between ARM / FPGA is done inside armsrc/fpgaloader.c see: function FpgaSendCommand()
Send 16 bit command / data pair to FPGA
The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
where
C is 4bit command
D is 12bit data
shift_reg receive this 16bit frame
LF command
----------
shift_reg[15:12] == 4bit command
LF has three commands (FPGA_CMD_SET_CONFREG, FPGA_CMD_SET_DIVISOR, FPGA_CMD_SET_EDGE_DETECT_THRESHOLD)
Current commands uses only 2bits. We have room for up to 4bits of commands total (7).
LF data
-------
shift_reg[11:0] == 12bit data
lf data is divided into MAJOR MODES and configuration values.
The major modes uses 3bits (0,1,2,3,7 | 000, 001, 010, 011, 111)
000 FPGA_MAJOR_MODE_LF_READER = Act as LF reader (modulate)
001 FPGA_MAJOR_MODE_LF_EDGE_DETECT = Simulate LF
010 FPGA_MAJOR_MODE_LF_PASSTHRU = Passthrough mode, CROSS_LO line connected to SSP_DIN. SSP_DOUT logic level controls if we modulate / listening
011 FPGA_MAJOR_MODE_LF_ADC = refactor hitag2, clear ADC sampling
111 FPGA_MAJOR_MODE_OFF = turn off sampling.
Each one of this major modes can have options. Currently these two major modes uses options.
- FPGA_MAJOR_MODE_LF_READER
- FPGA_MAJOR_MODE_LF_EDGE_DETECT
FPGA_MAJOR_MODE_LF_READER
-------------------------------------
lf_field = 1bit (FPGA_LF_ADC_READER_FIELD)
You can send FPGA_CMD_SET_DIVISOR to set with FREQUENCY the fpga should sample at
divisor = 8bits shift_reg[7:0]
FPGA_MAJOR_MODE_LF_EDGE_DETECT
------------------------------------------
lf_ed_toggle_mode = 1bits
lf_ed_threshold = 8bits threshold defaults to 127
You can send FPGA_CMD_SET_EDGE_DETECT_THRESHOLD to set a custom threshold
lf_ed_threshold = 8bits threshold value.
conf_word 12bits
conf_word[8:6] = 3bit major mode.
conf_word[0] = 1bit lf_field
conf_word[1] = 1bit lf_ed_toggle_mode
conf_word[7:0] = 8bit divisor
conf_word[7:0] = 8bit threshold
-----+--------- frame layout --------------------
bit | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-----+-------------------------------------------
cmd | x x x x
major| x x x
opt | x x
divi | x x x x x x x x
thres| x x x x x x x x
-----+-------------------------------------------
*/
reg [15:0] shift_reg;
reg [7:0] divisor;
reg [7:0] lf_ed_threshold;
reg [11:0] conf_word;
wire [2:0] major_mode = conf_word[8:6];
wire lf_field = conf_word[0];
wire lf_ed_toggle_mode = conf_word[1];
// Handles cmd / data frame from ARM
always @(posedge ncs)
begin
// 4 bit command
case (shift_reg[15:12])
`FPGA_CMD_SET_CONFREG:
begin
// 12 bit data
conf_word <= shift_reg[11:0];
if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
begin
lf_ed_threshold <= 127; // default threshold
end
end
`FPGA_CMD_SET_DIVISOR:
divisor <= shift_reg[7:0]; // 8bits
`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
lf_ed_threshold <= shift_reg[7:0]; // 8 bits
endcase
end
// Receive 16bits of data from ARM here.
always @(posedge spck)
begin
if (~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
wire [7:0] pck_cnt;
wire pck_divclk;
clk_divider div_clk(pck0, divisor, pck_cnt, pck_divclk);
lo_read lr(
pck0, pck_cnt, pck_divclk,
lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
adc_d, lr_adc_clk,
lr_ssp_frame, lr_ssp_din, lr_ssp_clk,
lr_dbg, lf_field
);
lo_passthru lp(
pck_divclk,
lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
lp_adc_clk,
lp_ssp_din, ssp_dout,
cross_lo,
lp_dbg
);
lo_edge_detect le(
pck0, pck_divclk,
le_pwr_lo, le_pwr_hi, le_pwr_oe1, le_pwr_oe2, le_pwr_oe3, le_pwr_oe4,
adc_d, le_adc_clk,
le_ssp_frame, ssp_dout, le_ssp_clk,
cross_lo,
le_dbg,
lf_field,
lf_ed_toggle_mode, lf_ed_threshold
);
lo_adc la(
pck0,
la_pwr_lo, la_pwr_hi, la_pwr_oe1, la_pwr_oe2, la_pwr_oe3, la_pwr_oe4,
adc_d, la_adc_clk,
la_ssp_frame, la_ssp_din, ssp_dout, la_ssp_clk,
la_dbg, divisor,
lf_field
);
// Major modes:
// 000 -- LF reader (generic)
// 001 -- LF edge detect (generic)
// 010 -- LF passthrough
// 011 -- LF ADC (read/write)
// 100 -- unused
// 101 -- unused
// 110 -- unused
// 111 -- FPGA_MAJOR_MODE_OFF
// 000 001 010 011 100 101 110 111
mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, la_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, la_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, la_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, la_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, la_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, la_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, la_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, la_pwr_lo, 1'b0, 1'b0, 1'b1, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, la_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, la_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, la_dbg, 1'b0, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sub_inputs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 8: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 8: 0] data_out;
wire [ 8: 0] out_port;
wire [ 8: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {9 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[8 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: M.63c
// \ \ Application: netgen
// / / Filename: softusb_dpram_11_8.v
// /___/ /\ Timestamp: Wed Sep 15 21:30:45 2010
// \ \ / \
// \___\/\___\
//
// Command : -ofmt verilog -w -insert_glbl false softusb_dpram.ngc softusb_dpram_11_8.v
// Device : xc4vlx25-ff668-10
// Input file : softusb_dpram.ngc
// Output file : softusb_dpram_11_8.v
// # of Modules : 1
// Design Name : softusb_dpram
// Xilinx : /usr/Xilinx/12.2/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module softusb_dpram_11_8 (
clk, we2, clk2, we, ce2, do2, do, di, a, a2, di2
);
input clk;
input we2;
input clk2;
input we;
input ce2;
output [7 : 0] do2;
output [7 : 0] do;
input [7 : 0] di;
input [10 : 0] a;
input [10 : 0] a2;
input [7 : 0] di2;
wire N0;
wire N1;
wire NLW_Mram_ram_CASCADEINA_UNCONNECTED;
wire NLW_Mram_ram_CASCADEINB_UNCONNECTED;
wire NLW_Mram_ram_CASCADEOUTA_UNCONNECTED;
wire NLW_Mram_ram_CASCADEOUTB_UNCONNECTED;
wire \NLW_Mram_ram_ADDRA<2>_UNCONNECTED ;
wire \NLW_Mram_ram_ADDRA<1>_UNCONNECTED ;
wire \NLW_Mram_ram_ADDRA<0>_UNCONNECTED ;
wire \NLW_Mram_ram_ADDRB<2>_UNCONNECTED ;
wire \NLW_Mram_ram_ADDRB<1>_UNCONNECTED ;
wire \NLW_Mram_ram_ADDRB<0>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<31>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<30>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<29>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<28>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<27>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<26>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<25>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<24>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<23>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<22>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<21>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<20>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<19>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<18>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<17>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<16>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<15>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<14>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<13>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<12>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<11>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<10>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<9>_UNCONNECTED ;
wire \NLW_Mram_ram_DIA<8>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<31>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<30>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<29>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<28>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<27>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<26>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<25>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<24>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<23>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<22>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<21>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<20>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<19>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<18>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<17>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<16>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<15>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<14>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<13>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<12>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<11>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<10>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<9>_UNCONNECTED ;
wire \NLW_Mram_ram_DIB<8>_UNCONNECTED ;
wire \NLW_Mram_ram_DIPA<3>_UNCONNECTED ;
wire \NLW_Mram_ram_DIPA<2>_UNCONNECTED ;
wire \NLW_Mram_ram_DIPA<1>_UNCONNECTED ;
wire \NLW_Mram_ram_DIPB<3>_UNCONNECTED ;
wire \NLW_Mram_ram_DIPB<2>_UNCONNECTED ;
wire \NLW_Mram_ram_DIPB<1>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<31>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<30>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<29>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<28>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<27>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<26>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<25>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<24>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<23>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<22>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<21>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<20>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<19>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<18>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<17>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<16>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<15>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<14>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<13>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<12>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<11>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<10>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<9>_UNCONNECTED ;
wire \NLW_Mram_ram_DOA<8>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<31>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<30>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<29>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<28>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<27>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<26>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<25>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<24>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<23>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<22>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<21>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<20>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<19>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<18>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<17>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<16>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<15>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<14>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<13>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<12>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<11>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<10>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<9>_UNCONNECTED ;
wire \NLW_Mram_ram_DOB<8>_UNCONNECTED ;
wire \NLW_Mram_ram_DOPA<3>_UNCONNECTED ;
wire \NLW_Mram_ram_DOPA<2>_UNCONNECTED ;
wire \NLW_Mram_ram_DOPA<1>_UNCONNECTED ;
wire \NLW_Mram_ram_DOPA<0>_UNCONNECTED ;
wire \NLW_Mram_ram_DOPB<3>_UNCONNECTED ;
wire \NLW_Mram_ram_DOPB<2>_UNCONNECTED ;
wire \NLW_Mram_ram_DOPB<1>_UNCONNECTED ;
wire \NLW_Mram_ram_DOPB<0>_UNCONNECTED ;
GND XST_GND (
.G(N0)
);
VCC XST_VCC (
.P(N1)
);
RAMB16 #(
.WRITE_MODE_A ( "NO_CHANGE" ),
.WRITE_MODE_B ( "NO_CHANGE" ),
.READ_WIDTH_A ( 9 ),
.READ_WIDTH_B ( 9 ),
.WRITE_WIDTH_A ( 9 ),
.WRITE_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.INIT_FILE ( "NONE" ),
.SRVAL_A ( 36'h000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INVERT_CLK_DOA_REG ( "FALSE" ),
.INVERT_CLK_DOB_REG ( "FALSE" ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.SRVAL_B ( 36'h000000000 ))
Mram_ram (
.CASCADEINA(NLW_Mram_ram_CASCADEINA_UNCONNECTED),
.CASCADEINB(NLW_Mram_ram_CASCADEINB_UNCONNECTED),
.CLKA(clk),
.CLKB(clk2),
.ENA(N1),
.REGCEA(N0),
.REGCEB(N0),
.ENB(ce2),
.SSRA(N0),
.SSRB(N0),
.CASCADEOUTA(NLW_Mram_ram_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_Mram_ram_CASCADEOUTB_UNCONNECTED),
.ADDRA({N0, a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0], \NLW_Mram_ram_ADDRA<2>_UNCONNECTED ,
\NLW_Mram_ram_ADDRA<1>_UNCONNECTED , \NLW_Mram_ram_ADDRA<0>_UNCONNECTED }),
.ADDRB({N0, a2[10], a2[9], a2[8], a2[7], a2[6], a2[5], a2[4], a2[3], a2[2], a2[1], a2[0], \NLW_Mram_ram_ADDRB<2>_UNCONNECTED ,
\NLW_Mram_ram_ADDRB<1>_UNCONNECTED , \NLW_Mram_ram_ADDRB<0>_UNCONNECTED }),
.DIA({\NLW_Mram_ram_DIA<31>_UNCONNECTED , \NLW_Mram_ram_DIA<30>_UNCONNECTED , \NLW_Mram_ram_DIA<29>_UNCONNECTED ,
\NLW_Mram_ram_DIA<28>_UNCONNECTED , \NLW_Mram_ram_DIA<27>_UNCONNECTED , \NLW_Mram_ram_DIA<26>_UNCONNECTED , \NLW_Mram_ram_DIA<25>_UNCONNECTED ,
\NLW_Mram_ram_DIA<24>_UNCONNECTED , \NLW_Mram_ram_DIA<23>_UNCONNECTED , \NLW_Mram_ram_DIA<22>_UNCONNECTED , \NLW_Mram_ram_DIA<21>_UNCONNECTED ,
\NLW_Mram_ram_DIA<20>_UNCONNECTED , \NLW_Mram_ram_DIA<19>_UNCONNECTED , \NLW_Mram_ram_DIA<18>_UNCONNECTED , \NLW_Mram_ram_DIA<17>_UNCONNECTED ,
\NLW_Mram_ram_DIA<16>_UNCONNECTED , \NLW_Mram_ram_DIA<15>_UNCONNECTED , \NLW_Mram_ram_DIA<14>_UNCONNECTED , \NLW_Mram_ram_DIA<13>_UNCONNECTED ,
\NLW_Mram_ram_DIA<12>_UNCONNECTED , \NLW_Mram_ram_DIA<11>_UNCONNECTED , \NLW_Mram_ram_DIA<10>_UNCONNECTED , \NLW_Mram_ram_DIA<9>_UNCONNECTED ,
\NLW_Mram_ram_DIA<8>_UNCONNECTED , di[7], di[6], di[5], di[4], di[3], di[2], di[1], di[0]}),
.DIB({\NLW_Mram_ram_DIB<31>_UNCONNECTED , \NLW_Mram_ram_DIB<30>_UNCONNECTED , \NLW_Mram_ram_DIB<29>_UNCONNECTED ,
\NLW_Mram_ram_DIB<28>_UNCONNECTED , \NLW_Mram_ram_DIB<27>_UNCONNECTED , \NLW_Mram_ram_DIB<26>_UNCONNECTED , \NLW_Mram_ram_DIB<25>_UNCONNECTED ,
\NLW_Mram_ram_DIB<24>_UNCONNECTED , \NLW_Mram_ram_DIB<23>_UNCONNECTED , \NLW_Mram_ram_DIB<22>_UNCONNECTED , \NLW_Mram_ram_DIB<21>_UNCONNECTED ,
\NLW_Mram_ram_DIB<20>_UNCONNECTED , \NLW_Mram_ram_DIB<19>_UNCONNECTED , \NLW_Mram_ram_DIB<18>_UNCONNECTED , \NLW_Mram_ram_DIB<17>_UNCONNECTED ,
\NLW_Mram_ram_DIB<16>_UNCONNECTED , \NLW_Mram_ram_DIB<15>_UNCONNECTED , \NLW_Mram_ram_DIB<14>_UNCONNECTED , \NLW_Mram_ram_DIB<13>_UNCONNECTED ,
\NLW_Mram_ram_DIB<12>_UNCONNECTED , \NLW_Mram_ram_DIB<11>_UNCONNECTED , \NLW_Mram_ram_DIB<10>_UNCONNECTED , \NLW_Mram_ram_DIB<9>_UNCONNECTED ,
\NLW_Mram_ram_DIB<8>_UNCONNECTED , di2[7], di2[6], di2[5], di2[4], di2[3], di2[2], di2[1], di2[0]}),
.DIPA({\NLW_Mram_ram_DIPA<3>_UNCONNECTED , \NLW_Mram_ram_DIPA<2>_UNCONNECTED , \NLW_Mram_ram_DIPA<1>_UNCONNECTED , N0}),
.DIPB({\NLW_Mram_ram_DIPB<3>_UNCONNECTED , \NLW_Mram_ram_DIPB<2>_UNCONNECTED , \NLW_Mram_ram_DIPB<1>_UNCONNECTED , N0}),
.WEA({we, we, we, we}),
.WEB({we2, we2, we2, we2}),
.DOA({\NLW_Mram_ram_DOA<31>_UNCONNECTED , \NLW_Mram_ram_DOA<30>_UNCONNECTED , \NLW_Mram_ram_DOA<29>_UNCONNECTED ,
\NLW_Mram_ram_DOA<28>_UNCONNECTED , \NLW_Mram_ram_DOA<27>_UNCONNECTED , \NLW_Mram_ram_DOA<26>_UNCONNECTED , \NLW_Mram_ram_DOA<25>_UNCONNECTED ,
\NLW_Mram_ram_DOA<24>_UNCONNECTED , \NLW_Mram_ram_DOA<23>_UNCONNECTED , \NLW_Mram_ram_DOA<22>_UNCONNECTED , \NLW_Mram_ram_DOA<21>_UNCONNECTED ,
\NLW_Mram_ram_DOA<20>_UNCONNECTED , \NLW_Mram_ram_DOA<19>_UNCONNECTED , \NLW_Mram_ram_DOA<18>_UNCONNECTED , \NLW_Mram_ram_DOA<17>_UNCONNECTED ,
\NLW_Mram_ram_DOA<16>_UNCONNECTED , \NLW_Mram_ram_DOA<15>_UNCONNECTED , \NLW_Mram_ram_DOA<14>_UNCONNECTED , \NLW_Mram_ram_DOA<13>_UNCONNECTED ,
\NLW_Mram_ram_DOA<12>_UNCONNECTED , \NLW_Mram_ram_DOA<11>_UNCONNECTED , \NLW_Mram_ram_DOA<10>_UNCONNECTED , \NLW_Mram_ram_DOA<9>_UNCONNECTED ,
\NLW_Mram_ram_DOA<8>_UNCONNECTED , do[7], do[6], do[5], do[4], do[3], do[2], do[1], do[0]}),
.DOB({\NLW_Mram_ram_DOB<31>_UNCONNECTED , \NLW_Mram_ram_DOB<30>_UNCONNECTED , \NLW_Mram_ram_DOB<29>_UNCONNECTED ,
\NLW_Mram_ram_DOB<28>_UNCONNECTED , \NLW_Mram_ram_DOB<27>_UNCONNECTED , \NLW_Mram_ram_DOB<26>_UNCONNECTED , \NLW_Mram_ram_DOB<25>_UNCONNECTED ,
\NLW_Mram_ram_DOB<24>_UNCONNECTED , \NLW_Mram_ram_DOB<23>_UNCONNECTED , \NLW_Mram_ram_DOB<22>_UNCONNECTED , \NLW_Mram_ram_DOB<21>_UNCONNECTED ,
\NLW_Mram_ram_DOB<20>_UNCONNECTED , \NLW_Mram_ram_DOB<19>_UNCONNECTED , \NLW_Mram_ram_DOB<18>_UNCONNECTED , \NLW_Mram_ram_DOB<17>_UNCONNECTED ,
\NLW_Mram_ram_DOB<16>_UNCONNECTED , \NLW_Mram_ram_DOB<15>_UNCONNECTED , \NLW_Mram_ram_DOB<14>_UNCONNECTED , \NLW_Mram_ram_DOB<13>_UNCONNECTED ,
\NLW_Mram_ram_DOB<12>_UNCONNECTED , \NLW_Mram_ram_DOB<11>_UNCONNECTED , \NLW_Mram_ram_DOB<10>_UNCONNECTED , \NLW_Mram_ram_DOB<9>_UNCONNECTED ,
\NLW_Mram_ram_DOB<8>_UNCONNECTED , do2[7], do2[6], do2[5], do2[4], do2[3], do2[2], do2[1], do2[0]}),
.DOPA({\NLW_Mram_ram_DOPA<3>_UNCONNECTED , \NLW_Mram_ram_DOPA<2>_UNCONNECTED , \NLW_Mram_ram_DOPA<1>_UNCONNECTED ,
\NLW_Mram_ram_DOPA<0>_UNCONNECTED }),
.DOPB({\NLW_Mram_ram_DOPB<3>_UNCONNECTED , \NLW_Mram_ram_DOPB<2>_UNCONNECTED , \NLW_Mram_ram_DOPB<1>_UNCONNECTED ,
\NLW_Mram_ram_DOPB<0>_UNCONNECTED })
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_TB_V
`define SKY130_FD_SC_LP__NOR2B_TB_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2b.v"
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B_N = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B_N = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B_N = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B_N = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__nor2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_0_V
`define SKY130_FD_SC_LP__O2BB2A_0_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_0 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_0 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_0_V
|
/*
* ram_w.v
*
* Created on: 09/10/2012
* Author: Lord_Rafa
*/
`timescale 1 ps / 1 ps
module ram_w(
input clk,
input rst,
output wire[ADD_WIDTH-1:0] ram_w_address,
input ram_w_waitrequest,
output wire[BYTE_ENABLE_WIDTH-1:0] ram_w_byteenable,
output wire ram_w_write,
output wire[DATA_WIDTH-1:0] ram_w_writedata,
output wire[BURST_WIDTH_W-1:0] ram_w_burstcount,
input [DATA_WIDTH-1:0] data_fifo_out,
input data_valid_fifo_out,
input start_fifo_out,
input [ADD_WIDTH-1:0] address_fifo_out,
input [DATA_WIDTH-1:0] n_burst_fifo_out,
output wire bussy_fifo_out,
output wire full_fifo_out,
output wire [FIFO_DEPTH_LOG2:0] usedw_fifo_out
);
parameter DATA_WIDTH = 32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter MAX_BURST_COUNT_W = 32;
parameter BURST_WIDTH_W = 5;
parameter FIFO_DEPTH_LOG2 = 8;
parameter FIFO_DEPTH = 256;
reg write;
wire set_write;
wire reset_write;
wire write_complete;
reg [BURST_WIDTH_W:0] burst_write_n;
wire write_burst_end;
reg [DATA_WIDTH-1:0] out_n;
reg [ADD_WIDTH-1:0] write_address;
wire fifo_full;
wire [FIFO_DEPTH_LOG2:0] fifo_used;
scfifo master_to_st_fifo(
.aclr(start_fifo_out),
.clock(clk),
.data(data_fifo_out),
.wrreq(data_valid_fifo_out),
.q(ram_w_writedata),
.rdreq(write_complete),
.full(fifo_full),
.usedw(fifo_used[FIFO_DEPTH_LOG2-1:0])
);
defparam master_to_st_fifo.lpm_width = DATA_WIDTH;
defparam master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam master_to_st_fifo.lpm_showahead = "ON";
defparam master_to_st_fifo.use_eab = "ON";
defparam master_to_st_fifo.add_ram_output_register = "ON";
defparam master_to_st_fifo.underflow_checking = "OFF";
defparam master_to_st_fifo.overflow_checking = "OFF";
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
write <= 0;
end else begin
if (reset_write == 1) begin
write <= 0;
end else begin
if (set_write == 1) begin
write <= 1;
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
out_n <= 0;
end else begin
if (start_fifo_out == 1) begin
out_n <= n_burst_fifo_out * MAX_BURST_COUNT_W;
end else begin
if (write_complete == 1) begin
out_n <= out_n - 1;
end
end
end
end
always @(posedge clk) begin
if (start_fifo_out == 1) begin
burst_write_n <= MAX_BURST_COUNT_W;
end
else begin
if (write_burst_end == 1) begin
burst_write_n <= MAX_BURST_COUNT_W;
end else begin
if (write_complete == 1) begin
burst_write_n <= burst_write_n - 1;
end
end
end
end
always @(posedge clk) begin
if (start_fifo_out == 1) begin
write_address <= address_fifo_out;
end else begin
if (write_burst_end == 1) begin
write_address <= write_address + MAX_BURST_COUNT_W * BYTE_ENABLE_WIDTH;
end
end
end
assign write_complete = (write == 1) & (ram_w_waitrequest == 0);
assign write_burst_end = (burst_write_n == 1) & (write_complete == 1);
assign fifo_used[FIFO_DEPTH_LOG2] = fifo_full;
assign set_write = (out_n != 0) & (fifo_used >= MAX_BURST_COUNT_W);
assign reset_write = ((fifo_used <= MAX_BURST_COUNT_W) | (out_n == 1)) & (write_burst_end == 1);
assign ram_w_address = write_address;
assign ram_w_write = write;
assign ram_w_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_w_burstcount = MAX_BURST_COUNT_W;
assign bussy_fifo_out = out_n != 0;
assign full_fifo_out = fifo_full;
assign usedw_fifo_out = fifo_used;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BOI_TB_V
`define SKY130_FD_SC_HS__A21BOI_TB_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21boi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1_N = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1_N = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1_N = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1_N = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__a21boi dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BOI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_TB_V
`define SKY130_FD_SC_LS__O31AI_TB_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o31ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ls__o31ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_TB_V
|
Require Import Coq.Classes.RelationClasses.
Require Import Coq.Reals.Rdefinitions.
Require Import ExtLib.Structures.Applicative.
Require Import ExtLib.Structures.Functor.
Require Import ExtLib.Data.Fun.
Require Import ExtLib.Tactics.
Require Import ChargeCore.Logics.ILogic.
Require Import ChargeCore.Logics.ILEmbed.
Require ChargeCore.Logics.ILInsts.
Require Import ChargeCore.Tactics.Tactics.
Require Import Temporal.ActionStream.
Section parametric.
Variable tlaState : Type.
Definition Var (T : Type) : Type := tlaState -> T.
Local Existing Instance Applicative_Fun.
Local Existing Instance Functor_Fun.
Definition StateVal (T : Type) : Type :=
tlaState -> T.
Definition DActionVal (T : Type) : Type :=
tlaState -> tlaState -> T.
Definition ActionVal (T : Type) : Type :=
tlaState -> Step tlaState -> T.
Definition TraceVal (T : Type) :=
trace tlaState -> T.
Definition StateProp := StateVal Prop.
Definition DActionProp := DActionVal Prop.
Definition ActionProp := ActionVal Prop.
Definition TraceProp := TraceVal Prop.
Global Instance ILogicOps_StateProp : ILogicOps StateProp :=
@ILInsts.ILFun_Ops _ _ _.
Global Instance ILogicOps_ActionProp : ILogicOps ActionProp :=
@ILInsts.ILFun_Ops _ _ _.
Global Instance ILogicOps_DActionProp : ILogicOps DActionProp :=
@ILInsts.ILFun_Ops _ _ _.
Global Instance ILogicOps_TraceProp : ILogicOps TraceProp :=
@ILInsts.ILFun_Ops _ _ _.
Global Instance ILogic_StateProp : ILogic StateProp := _.
Global Instance ILogic_ActionProp : ILogic ActionProp := _.
Global Instance ILogic_DActionProp : ILogic DActionProp := _.
Global Instance ILogic_TraceProp : ILogic TraceProp := _.
Local Transparent ILInsts.ILFun_Ops.
Global Instance EmbedOp_Prop_StateProp : EmbedOp Prop StateProp :=
{ embed := fun P _ => P }.
Global Instance Embed_Prop_StateProp : Embed Prop StateProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_Prop_ActionProp : EmbedOp Prop ActionProp :=
{ embed := fun P _ _ => P }.
Global Instance Embed_Prop_ActionProp : Embed Prop ActionProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_Prop_DActionProp : EmbedOp Prop DActionProp :=
{ embed := fun P _ _ => P }.
Global Instance Embed_Prop_DActionProp : Embed Prop DActionProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_Prop_TraceProp : EmbedOp Prop TraceProp :=
{ embed := fun P _ => P }.
Global Instance Embed_Prop_TraceProp : Embed Prop TraceProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_StateVal_StateProp : EmbedOp (StateVal Prop) StateProp :=
{ embed := fun P => P }.
Global Instance Embed_StateVal_StateProp : Embed (StateVal Prop) StateProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_ActionVal_ActionProp : EmbedOp (ActionVal Prop) ActionProp :=
{ embed := fun P => P }.
Global Instance Embed_ActionVal_ActionProp : Embed (ActionVal Prop) ActionProp.
Proof.
constructor; simpl; intuition.
Qed.
Global Instance EmbedOp_TraceVal_TraceProp : EmbedOp (TraceVal Prop) TraceProp :=
{ embed := fun P => P }.
Global Instance Embed_TraceVal_TraceProp : Embed (TraceVal Prop) TraceProp.
Proof.
constructor; simpl; intuition.
Qed.
(* These are the "obvious" definitions, needed to help Coq *)
Global Instance Applicative_Action
: Applicative ActionVal :=
{ pure := fun _ x => fun _ _ => x
; ap := fun _ _ f x => fun st st' => (f st st') (x st st')
}.
Global Instance Functor_Action
: Functor ActionVal :=
{ fmap := fun _ _ f x => ap (pure f) x }.
Global Instance Applicative_DAction
: Applicative DActionVal :=
{ pure := fun _ x => fun _ _ => x
; ap := fun _ _ f x => fun st st' => (f st st') (x st st')
}.
Global Instance Functor_DAction
: Functor DActionVal :=
{ fmap := fun _ _ f x => ap (pure f) x }.
Global Instance Applicative_State
: Applicative StateVal :=
{ pure := fun _ x => fun _ => x
; ap := fun _ _ f x => fun st => (f st) (x st)
}.
Global Instance Functor_State
: Functor StateVal :=
{ fmap := fun _ _ f x => ap (pure f) x }.
Definition now : StateProp -> TraceProp :=
fun P tr => P (hd tr).
(* This does not make sense
Definition next : StateProp -> TraceProp :=
fun P tr => P (hd (tl tr)).
*)
Definition always (P : TraceProp) : TraceProp :=
fun s =>
forall s', skips_to s s' -> P s'.
Definition eventually (P : TraceProp) : TraceProp :=
fun s =>
exists s', skips_to s s' /\ P s'.
Definition discretely (P : DActionProp) : ActionProp :=
fun start step =>
match step with
| DiscreteTo st' => P start st'
end.
Definition pre {T} (f : tlaState -> T) : DActionVal T :=
fun st _ => f st.
Definition post {T} (f : tlaState -> T) : DActionVal T :=
fun _ st' => f st'.
(*
Definition continuously (P : CActionProp) : ActionProp :=
fun start step =>
match step with
| ContinuousBy r f => P r (fun x => hybrid_join (f x) (snd (hybrid_split start)))
| _ => False
end.
*)
Definition stutter {T} (f : tlaState -> T) : DActionProp :=
fun st st' => f st = f st'.
Definition starts (P : ActionProp) : TraceProp :=
fun tr =>
P (hd tr) (firstStep tr).
Lemma always_skips_to : forall P t1 t2,
skips_to t1 t2 ->
always P t1 -> always P t2.
Proof.
unfold always. intros.
eapply H0. etransitivity; eauto.
Qed.
Definition through (P : TraceProp) : TraceProp :=
fun tr =>
match firstStep tr with
| DiscreteTo tr' =>
(** This is making an assumption about the underlying stream **)
P (tl tr)
end.
(** Always Facts **)
Lemma always_and : forall P Q,
always P //\\ always Q -|- always (P //\\ Q).
Proof.
intros. split.
{ red. red. simpl. unfold always. intuition. }
{ red. red. simpl. unfold always.
intuition; edestruct H; eauto. }
Qed.
Lemma always_or : forall P Q,
always P \\// always Q |-- always (P \\// Q).
Proof.
red. red. simpl. unfold always. intuition.
Qed.
Lemma always_impl : forall P Q,
always (P -->> Q) |-- always P -->> always Q.
Proof.
red. red. simpl. unfold always. intuition.
Qed.
Lemma always_tauto
: forall G P, |-- P -> G |-- always P.
Proof. compute; intuition. Qed.
(** Generic logic lemma **)
Lemma uncurry : forall P Q R,
(P //\\ Q) -->> R -|- P -->> Q -->> R.
Proof. compute. tauto. Qed.
Lemma and_forall : forall {T} (F G : T -> Prop),
((forall x, F x) /\ (forall x, G x)) <->
(forall x, F x /\ G x).
Proof. firstorder. Qed.
Lemma now_entails : forall (A B : StateProp),
now (A -->> B) |-- now A -->> now B.
Proof. unfold now. simpl. auto. Qed.
Definition before (P : StateProp) : ActionProp :=
fun st _ => P st.
(*
Definition after (P : StateProp) : DActionProp :=
fun _ st' => P st'.
*)
(*
Coercion starts : ActionProp >-> TraceProp.
Coercion discretely : DActionProp >-> ActionProp.
*)
Lemma now_starts_discretely_and : forall P Q,
now P //\\ starts Q -|- starts (before P //\\ Q).
Proof.
intros. split.
{ red; simpl. destruct t.
unfold starts, discretely; destruct c; simpl; tauto. }
{ red; simpl. destruct t.
unfold starts, discretely; destruct c; simpl; tauto. }
Qed.
(*
Lemma starts_next_impl : forall (P : DActionProp) (Q : StateProp),
starts (discretely (fun st st' => P st st' -> Q st')) |-- starts (discretely P) -->> through (now Q).
Proof.
intros.
{ red; simpl. destruct t.
unfold starts, discretely; destruct c; simpl. tauto.
tauto. }
Qed.
*)
Lemma starts_discretely_through : forall (P : DActionProp) (Q : StateProp),
(forall st, P st |-- Q) ->
|-- starts (discretely P) -->> through (now Q).
Proof.
intros. unfold starts, discretely, through.
red. simpl. intros.
forward_reason.
destruct t. destruct c. simpl in *.
unfold tl. simpl. red. simpl. eauto.
Qed.
Definition enabled (ap : ActionProp) : StateProp :=
Exists st', fun st => ap st st'.
(** Reasoning about [through] **)
Lemma through_and : forall P Q, through P //\\ through Q -|- through (P //\\ Q).
Proof.
intros. apply and_forall. intros.
unfold through. simpl. destruct (firstStep x); intuition; firstorder.
Qed.
Lemma through_or : forall P Q, through P \\// through Q |-- through (P \\// Q).
Proof.
intros. red. simpl.
unfold through. intro. destruct (firstStep t); intuition; firstorder.
Qed.
Lemma through_impl : forall P Q, through P -->> through Q |-- through (P -->> Q).
Proof.
intros. red. simpl.
unfold through. intro. destruct (firstStep t); intuition; firstorder.
Qed.
Lemma through_ex : forall T (P : T -> _),
Exists x : T, through (P x) |-- through (lexists P).
Proof.
intros; red; simpl.
unfold through. intro. intros.
destruct H. destruct (firstStep t); eauto.
Qed.
Lemma through_all : forall T (P : T -> _),
Forall x : T, through (P x) |-- through (lforall P).
Proof.
intros; red; simpl.
unfold through. intro. intros.
destruct (firstStep t); eauto.
Qed.
(*
Definition throughD (P : StateProp) : DActionProp :=
fun _ fin => P fin.
*)
(** This is induction over the phase changes **)
Lemma dind_lem : forall G P,
G |-- P -->> always (P -->> through P) -->> always P.
Proof.
intros. red. red.
red.
intros. red. simpl. red.
intros. clear H. clear G. revert H0 H1.
induction H2 using skips_to_ind; simpl.
{ (* Now *)
intros. assumption. }
{ (* AfterD *)
intros.
eapply IHskips_to.
{ red in H1.
eapply H1 in H0; try reflexivity.
eapply H0. }
{ eapply always_skips_to. 2: eapply H1.
eapply skips_to_next. reflexivity. } }
Qed.
Theorem hybrid_induction
: forall G P T,
G |-- always T ->
G |-- P ->
G |-- always (P -->> T -->> through P) ->
G |-- always P.
Proof.
intros G P T.
generalize (dind_lem G P).
unfold lentails, ILogicOps_TraceProp. simpl.
intros.
eapply H; eauto.
specialize (H2 _ H3).
specialize (H0 _ H3).
revert H2. revert H0.
clear. revert t.
cut (|-- always T -->> always (P -->> T -->> through P) -->> always (P -->> through P)).
{ intros. eapply H. exact I. auto. auto. }
{ rewrite <- uncurry.
rewrite always_and.
rewrite <- always_impl.
apply always_tauto.
charge_tauto. }
Qed.
End parametric.
Arguments pre {_ _} _ _ _.
Arguments post {_ _} _ _ _.
Arguments always {_} _ _.
Arguments eventually {_} _ _.
Arguments starts {_} _ _.
Arguments discretely {_} _ _ _.
Arguments now {_} _ _.
Arguments stutter {_ _} _ _ _.
Arguments through {_} _ _.
Export ChargeCore.Logics.ILogic. |
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool := negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool := andb b1 (andb b2 b3).
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => n * factorial n'
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool := andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H I.
rewrite -> H.
rewrite -> I.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m H.
rewrite -> H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n as [| n'].
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite -> H.
rewrite -> H.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite -> H.
rewrite -> H.
destruct b.
reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b as [false | true].
simpl.
intros H.
rewrite -> H.
reflexivity.
simpl.
intros I.
rewrite -> I.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
Inductive binary : Type :=
| zero : binary
| double : binary -> binary
| double_plus_one : binary -> binary.
Fixpoint incr (b : binary) : binary :=
match b with
| zero => double_plus_one zero
| double b' => double_plus_one b'
| double_plus_one b' => double (incr b')
end.
Fixpoint bin_to_nat (b : binary) : nat :=
match b with
| zero => 0
| double b' => 2 * bin_to_nat b'
| double_plus_one b' => 1 + 2 * bin_to_nat b'
end.
Example test_bin_incr1 : bin_to_nat (incr zero) = 1 + bin_to_nat zero.
Proof. reflexivity. Qed.
Example test_bin_incr2 : bin_to_nat (incr (double_plus_one zero)) = 1 + bin_to_nat (double_plus_one zero).
Proof. reflexivity. Qed.
Example test_bin_incr3 : bin_to_nat (incr (double (double_plus_one zero))) = 1 + bin_to_nat (double (double_plus_one zero)).
Proof. reflexivity. Qed.
Example test_bin_incr4 : bin_to_nat (incr (double_plus_one (double_plus_one zero))) = 1 + bin_to_nat (double_plus_one (double_plus_one zero)).
Proof. reflexivity. Qed.
Example test_bin_incr5 : bin_to_nat (incr (double (double (double_plus_one zero)))) = 1 + bin_to_nat (double (double (double_plus_one zero))).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
Fixpoint decreasing (n m : nat) : nat :=
match n, m with
| 0, 0 => 0
| 0, n => decreasing 0 (n - 1)
| n, m => decreasing (n - 1) m
end.
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_2_V
`define SKY130_FD_SC_HS__O41A_2_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41a_2 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41a_2 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_2_V
|
`timescale 1ns/1ps
module tb;
reg E;
wire Y;
wire clk;
parameter NAND2_DEFAULT_DELAY = 1;
/* chip AUTO_TEMPLATE(
.notE(!E),
.G(clk),
); */
chip #(.NAND2_DELAY(NAND2_DEFAULT_DELAY))
U_CHIP
(
/*AUTOINST*/
// Outputs
.Y (Y),
// Inputs
.notE (!E), // Templated
.G (clk)); // Templated
clock_gen #(.period(20)) U_CLK_GEN (
/*AUTOINST*/
// Outputs
.clk (clk));
// Dump all nets to a vcd file called tb.vcd
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
E = 0;
#100;
E=1;
#205;
E=0;
#10;
E=1;
#194;
E=0;
// @(posedge done_r); // wait for done signal to rise
#1;
@(posedge clk);
@(posedge clk);
$display("-I- Done !");
#1;
$finish;
end
endmodule // tb
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_ac701.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: RIFFA wrapper for the AC701 (REV C) Development board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "xilinx.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_ac701
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
// 4-Byte Name for this FPGA
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "KC105")
(// Interface: Xilinx RX
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST,
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [`SIG_XIL_RX_TUSER_W-1:0] M_AXIS_RX_TUSER,
output RX_NP_OK,
output RX_NP_REQ,
// Interface: Xilinx TX
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
input S_AXIS_TX_TREADY,
output [`SIG_XIL_TX_TUSER_W-1:0] S_AXIS_TX_TUSER,
output TX_CFG_GNT,
// Interface: Xilinx Configuration
input [`SIG_BUSID_W-1:0] CFG_BUS_NUMBER,
input [`SIG_DEVID_W-1:0] CFG_DEVICE_NUMBER,
input [`SIG_FNID_W-1:0] CFG_FUNCTION_NUMBER,
input [`SIG_CFGREG_W-1:0] CFG_COMMAND,
input [`SIG_CFGREG_W-1:0] CFG_DCOMMAND,
input [`SIG_CFGREG_W-1:0] CFG_LSTATUS,
input [`SIG_CFGREG_W-1:0] CFG_LCOMMAND,
// Interface: Xilinx Flow Control
input [`SIG_FC_CPLD_W-1:0] FC_CPLD,
input [`SIG_FC_CPLH_W-1:0] FC_CPLH,
output [`SIG_FC_SEL_W-1:0] FC_SEL,
// Interface: Xilinx Interrupt
input CFG_INTERRUPT_MSIEN,
input CFG_INTERRUPT_RDY,
output CFG_INTERRUPT,
input USER_CLK,
input USER_RESET,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
// ALTERA, XILINX or ULTRASCALE
localparam C_VENDOR = "XILINX";
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire rx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_tlp;
wire rx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset;
wire rx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset;
wire rx_tlp_valid;
wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode;
wire tx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_tlp;
wire tx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset;
wire tx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset;
wire tx_tlp_valid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
reg rRxTlpValid;
reg rRxTlpEndFlag;
assign clk = USER_CLK;
assign rst_in = USER_RESET;
translation_xilinx
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(
// Outputs
.RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (tx_tlp_ready),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (rx_tlp_ready),
.TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.M_AXIS_RX_TREADY (M_AXIS_RX_TREADY),
.RX_NP_OK (RX_NP_OK),
.RX_NP_REQ (RX_NP_REQ),
.S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (S_AXIS_TX_TLAST),
.S_AXIS_TX_TVALID (S_AXIS_TX_TVALID),
.S_AXIS_TX_TUSER (S_AXIS_TX_TUSER[`SIG_XIL_TX_TUSER_W-1:0]),
.TX_CFG_GNT (TX_CFG_GNT),
.FC_SEL (FC_SEL[`SIG_FC_SEL_W-1:0]),
.CFG_INTERRUPT (CFG_INTERRUPT),
// Inputs
.M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (M_AXIS_RX_TLAST),
.M_AXIS_RX_TVALID (M_AXIS_RX_TVALID),
.M_AXIS_RX_TUSER (M_AXIS_RX_TUSER[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (S_AXIS_TX_TREADY),
.CFG_BUS_NUMBER (CFG_BUS_NUMBER[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (CFG_DEVICE_NUMBER[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (CFG_FUNCTION_NUMBER[`SIG_FNID_W-1:0]),
.CFG_COMMAND (CFG_COMMAND[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (CFG_DCOMMAND[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (CFG_LSTATUS[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (CFG_LCOMMAND[`SIG_CFGREG_W-1:0]),
.FC_CPLD (FC_CPLD[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (FC_CPLH[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN),
.CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY));
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset),
.RX_TLP_READY (rx_tlp_ready),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (rx_tlp),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode),
.TX_TLP_READY (tx_tlp_ready),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rst),
/*AUTOINST*/
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
reg rst_async_n; // asynchronous reset
wire req0, req1, req2;
wire ack0, ack1, ack2;
reg req0_reg;
reg start;
wire [7:0] data0;
reg [7:0] data0_reg;
wire [7:0] data1;
wire [7:0] data2;
wire [7:0] data3;
// assign data0 = data0_reg;
// two_phase_event_gen U_PORT1_EVENT_GEN (
// .run(rst_async_n),
// .req(req0),
// .ack(a)
// );
mousetrap_elt U_MOUSETRAP_STAGE0(
.ackNm1(), // out
.reqN(req0), // In
.ackN(a), // In
.doneN(done0), // Out
.datain(data0),
.dataout(data1),
.rstn(rst_async_n)
);
buff #(.DELAY(20)) U_DELAY0(.i(done0), .z(done0_d));
assign #10 data0 = data1 + 4;
inv U_INV(.i(done0_d), .zn(req0_tmp));
assign req0 = req0_tmp;
assign a =done0_d ;
// two_phase_slave U_SLAVE(.req(req3), .ack(ack2));
// assign #30 ack2_tmp = req3;
// assign ack2 = (ack2_tmp === 1'b1);
// Dump all nets to a vcd file called tb.vcd
event dbg_finish;
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n <= 1'b0;
start <= 1'b0;
// Wait long enough for the X's in the delay elements to disappears
#50;
rst_async_n = 1'b1;
$display("-I- Reset is released");
#5;
start <= 1'b1;
#5;
#200000;
start <= 1'b0;
$display("-I- Done !");
$finish;
end
endmodule // tb
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pipe_user.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_user.v
// Description : PIPE User Module for 7 Series Transceiver
// Version : 15.3.3
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE User Module --------------------------------------------------
module pcie_7x_v1_11_0_pipe_user #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_USE_MODE = "3.0", // PCIe sim version
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter RXCDRLOCK_MAX = 4'd15, // RXCDRLOCK max count
parameter RXVALID_MAX = 4'd15, // RXVALID max count
parameter CONVERGE_MAX = 22'd3125000 // Convergence max count
)
(
//---------- Input -------------------------------------
input USER_TXUSRCLK,
input USER_RXUSRCLK,
input USER_OOBCLK_IN,
input USER_RST_N,
input USER_RXUSRCLK_RST_N,
input USER_PCLK_SEL,
input USER_RESETOVRD_START,
input USER_TXRESETDONE,
input USER_RXRESETDONE,
input USER_TXELECIDLE,
input USER_TXCOMPLIANCE,
input USER_RXCDRLOCK_IN,
input USER_RXVALID_IN,
input USER_RXSTATUS_IN,
input USER_PHYSTATUS_IN,
input USER_RATE_DONE,
input USER_RST_IDLE,
input USER_RATE_RXSYNC,
input USER_RATE_IDLE,
input USER_RATE_GEN3,
input USER_RXEQ_ADAPT_DONE,
//---------- Output ------------------------------------
output USER_OOBCLK,
output USER_RESETOVRD,
output USER_TXPMARESET,
output USER_RXPMARESET,
output USER_RXCDRRESET,
output USER_RXCDRFREQRESET,
output USER_RXDFELPMRESET,
output USER_EYESCANRESET,
output USER_TXPCSRESET,
output USER_RXPCSRESET,
output USER_RXBUFRESET,
output USER_RESETOVRD_DONE,
output USER_RESETDONE,
output USER_ACTIVE_LANE,
output USER_RXCDRLOCK_OUT,
output USER_RXVALID_OUT,
output USER_PHYSTATUS_OUT,
output USER_PHYSTATUS_RST,
output USER_GEN3_RDY,
output USER_RX_CONVERGE
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg pclk_sel_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txcompliance_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxvalid_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxstatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_rxsync_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_adapt_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 1:0] oobclk_cnt = 2'd0;
reg [ 7:0] reset_cnt = 8'd127;
reg [ 3:0] rxcdrlock_cnt = 4'd0;
reg [ 3:0] rxvalid_cnt = 4'd0;
reg [21:0] converge_cnt = 22'd0;
reg converge_gen3 = 1'd0;
//---------- Output Registers --------------------------
reg oobclk = 1'd0;
reg [ 7:0] reset = 8'h00;
reg gen3_rdy = 1'd0;
reg [ 1:0] fsm = 2'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 2'd0;
localparam FSM_RESETOVRD = 2'd1;
localparam FSM_RESET_INIT = 2'd2;
localparam FSM_RESET = 2'd3;
//---------- Simulation Speedup ------------------------
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd100 : CONVERGE_MAX;
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= 1'd0;
resetovrd_start_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txelecidle_reg1 <= 1'd0;
txcompliance_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
rxeq_adapt_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= 1'd0;
resetovrd_start_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txelecidle_reg2 <= 1'd0;
txcompliance_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
rxeq_adapt_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= USER_PCLK_SEL;
resetovrd_start_reg1 <= USER_RESETOVRD_START;
txresetdone_reg1 <= USER_TXRESETDONE;
rxresetdone_reg1 <= USER_RXRESETDONE;
txelecidle_reg1 <= USER_TXELECIDLE;
txcompliance_reg1 <= USER_TXCOMPLIANCE;
rxcdrlock_reg1 <= USER_RXCDRLOCK_IN;
rxeq_adapt_done_reg1 <= USER_RXEQ_ADAPT_DONE;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
resetovrd_start_reg2 <= resetovrd_start_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txelecidle_reg2 <= txelecidle_reg1;
txcompliance_reg2 <= txcompliance_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
rxeq_adapt_done_reg2 <= rxeq_adapt_done_reg1;
end
end
//---------- Input FF ----------------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= 1'd0;
rxstatus_reg1 <= 1'd0;
rst_idle_reg1 <= 1'd0;
rate_done_reg1 <= 1'd0;
rate_rxsync_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
rate_gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= 1'd0;
rxstatus_reg2 <= 1'd0;
rst_idle_reg2 <= 1'd0;
rate_done_reg2 <= 1'd0;
rate_rxsync_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
rate_gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rxvalid_reg1 <= USER_RXVALID_IN;
rxstatus_reg1 <= USER_RXSTATUS_IN;
rst_idle_reg1 <= USER_RST_IDLE;
rate_done_reg1 <= USER_RATE_DONE;
rate_rxsync_reg1 <= USER_RATE_RXSYNC;
rate_idle_reg1 <= USER_RATE_IDLE;
rate_gen3_reg1 <= USER_RATE_GEN3;
//---------- 2nd Stage FF --------------------------
rxvalid_reg2 <= rxvalid_reg1;
rxstatus_reg2 <= rxstatus_reg1;
rst_idle_reg2 <= rst_idle_reg1;
rate_done_reg2 <= rate_done_reg1;
rate_rxsync_reg2 <= rate_rxsync_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rate_gen3_reg2 <= rate_gen3_reg1;
end
end
//---------- Generate Reset Override -------------------------------------------
generate if (PCIE_USE_MODE == "1.0")
begin : resetovrd
//---------- Reset Counter -------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset_cnt <= 8'd127;
else
//---------- Decrement Counter ---------------------
if (((fsm == FSM_RESETOVRD) || (fsm == FSM_RESET)) && (reset_cnt != 8'd0))
reset_cnt <= reset_cnt - 8'd1;
//---------- Reset Counter -------------------------
else
case (reset)
8'b00000000 : reset_cnt <= 8'd127; // Programmable PMARESET time
8'b11111111 : reset_cnt <= 8'd127; // Programmable RXCDRRESET time
8'b11111110 : reset_cnt <= 8'd127; // Programmable RXCDRFREQRESET time
8'b11111100 : reset_cnt <= 8'd127; // Programmable RXDFELPMRESET time
8'b11111000 : reset_cnt <= 8'd127; // Programmable EYESCANRESET time
8'b11110000 : reset_cnt <= 8'd127; // Programmable PCSRESET time
8'b11100000 : reset_cnt <= 8'd127; // Programmable RXBUFRESET time
8'b11000000 : reset_cnt <= 8'd127; // Programmable RESETOVRD deassertion time
8'b10000000 : reset_cnt <= 8'd127;
default : reset_cnt <= 8'd127;
endcase
end
//---------- Reset Shift Register ------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
reset <= 8'h00;
else
//---------- Initialize Reset Register ---------
if (fsm == FSM_RESET_INIT)
reset <= 8'hFF;
//---------- Shift Reset Register --------------
else if ((fsm == FSM_RESET) && (reset_cnt == 8'd0))
reset <= {reset[6:0], 1'd0};
//---------- Hold Reset Register ---------------
else
reset <= reset;
end
//---------- Reset Override FSM --------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
fsm <= FSM_IDLE;
else
begin
case (fsm)
//---------- Idle State ------------------------
FSM_IDLE : fsm <= resetovrd_start_reg2 ? FSM_RESETOVRD : FSM_IDLE;
//---------- Assert RESETOVRD ------------------
FSM_RESETOVRD : fsm <= (reset_cnt == 8'd0) ? FSM_RESET_INIT : FSM_RESETOVRD;
//---------- Initialize Reset ------------------
FSM_RESET_INIT : fsm <= FSM_RESET;
//---------- Shift Reset -----------------------
FSM_RESET : fsm <= ((reset == 8'd0) && rxresetdone_reg2) ? FSM_IDLE : FSM_RESET;
//---------- Default State ---------------------
default : fsm <= FSM_IDLE;
endcase
end
end
end
//---------- Disable Reset Override --------------------------------------------
else
begin : resetovrd_disble
//---------- Generate Default Signals --------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
else
begin
reset_cnt <= 8'hFF;
reset <= 8'd0;
fsm <= 2'd0;
end
end
end
endgenerate
//---------- Generate OOB Clock Divider ------------------------
generate if (PCIE_OOBCLK_MODE == 1)
begin : oobclk_div
//---------- OOB Clock Divider -----------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= oobclk_cnt + 2'd1;
oobclk <= pclk_sel_reg2 ? oobclk_cnt[1] : oobclk_cnt[0];
end
end
end
else
begin : oobclk_div_disable
//---------- OOB Clock Default -------------------------
always @ (posedge USER_OOBCLK_IN)
begin
if (!USER_RST_N)
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
else
begin
oobclk_cnt <= 2'd0;
oobclk <= 1'd0;
end
end
end
endgenerate
//---------- RXCDRLOCK Filter --------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
rxcdrlock_cnt <= 4'd0;
else
//---------- Increment RXCDRLOCK Counter -----------
if (rxcdrlock_reg2 && (rxcdrlock_cnt != RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt + 4'd1;
//---------- Hold RXCDRLOCK Counter ----------------
else if (rxcdrlock_reg2 && (rxcdrlock_cnt == RXCDRLOCK_MAX))
rxcdrlock_cnt <= rxcdrlock_cnt;
//---------- Reset RXCDRLOCK Counter ---------------
else
rxcdrlock_cnt <= 4'd0;
end
//---------- RXVALID Filter ----------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
rxvalid_cnt <= 4'd0;
else
//---------- Increment RXVALID Counter -------------
if (rxvalid_reg2 && (rxvalid_cnt != RXVALID_MAX) && (!rxstatus_reg2))
rxvalid_cnt <= rxvalid_cnt + 4'd1;
//---------- Hold RXVALID Counter ------------------
else if (rxvalid_reg2 && (rxvalid_cnt == RXVALID_MAX))
rxvalid_cnt <= rxvalid_cnt;
//---------- Reset RXVALID Counter -----------------
else
rxvalid_cnt <= 4'd0;
end
//---------- Converge Counter --------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
converge_cnt <= 22'd0;
else
//---------- Enter Gen1/Gen2 -----------------------
if (rst_idle_reg2 && rate_idle_reg2 && !rate_gen3_reg2)
begin
//---------- Increment Converge Counter --------
if (converge_cnt < converge_max_cnt)
converge_cnt <= converge_cnt + 22'd1;
//---------- Hold Converge Counter -------------
else
converge_cnt <= converge_cnt;
end
//---------- Reset Converge Counter ----------------
else
converge_cnt <= 22'd0;
end
//---------- Converge ----------------------------------------------------------
always @ (posedge USER_TXUSRCLK)
begin
if (!USER_RST_N)
converge_gen3 <= 1'd0;
else
//---------- Enter Gen3 ----------------------------
if (rate_gen3_reg2)
//---------- Wait for RX equalization adapt done
if (rxeq_adapt_done_reg2)
converge_gen3 <= 1'd1;
else
converge_gen3 <= converge_gen3;
//-------- Exit Gen3 -------------------------------
else
converge_gen3 <= 1'd0;
end
//---------- GEN3_RDY Generator ------------------------------------------------
always @ (posedge USER_RXUSRCLK)
begin
if (!USER_RXUSRCLK_RST_N)
gen3_rdy <= 1'd0;
else
gen3_rdy <= rate_idle_reg2 && rate_gen3_reg2;
end
//---------- PIPE User Override Reset Output -----------------------------------
assign USER_RESETOVRD = (fsm != FSM_IDLE);
assign USER_TXPMARESET = 1'd0;
assign USER_RXPMARESET = reset[0];
assign USER_RXCDRRESET = reset[1];
assign USER_RXCDRFREQRESET = reset[2];
assign USER_RXDFELPMRESET = reset[3];
assign USER_EYESCANRESET = reset[4];
assign USER_TXPCSRESET = 1'd0;
assign USER_RXPCSRESET = reset[5];
assign USER_RXBUFRESET = reset[6];
assign USER_RESETOVRD_DONE = (fsm == FSM_IDLE);
//---------- PIPE User Output --------------------------------------------------
assign USER_OOBCLK = oobclk;
assign USER_RESETDONE = (txresetdone_reg2 && rxresetdone_reg2);
assign USER_ACTIVE_LANE = !(txelecidle_reg2 && txcompliance_reg2);
//----------------------------------------------------------
assign USER_RXCDRLOCK_OUT = (USER_RXCDRLOCK_IN && (rxcdrlock_cnt == RXCDRLOCK_MAX)); // Filtered RXCDRLOCK
//----------------------------------------------------------
assign USER_RXVALID_OUT = ((USER_RXVALID_IN && (rxvalid_cnt == RXVALID_MAX)) && // Filtered RXVALID
rst_idle_reg2 && // Force RXVALID = 0 during reset
rate_idle_reg2); // Force RXVALID = 0 during rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_OUT = (!rst_idle_reg2 || // Force PHYSTATUS = 1 during reset
((rate_idle_reg2 || rate_rxsync_reg2) && USER_PHYSTATUS_IN) || // Raw PHYSTATUS
rate_done_reg2); // Gated PHYSTATUS for rate change
//----------------------------------------------------------
assign USER_PHYSTATUS_RST = !rst_idle_reg2; // Filtered PHYSTATUS for reset
//----------------------------------------------------------
assign USER_GEN3_RDY = 0;//gen3_rdy;
//----------------------------------------------------------
assign USER_RX_CONVERGE = (converge_cnt == converge_max_cnt) || converge_gen3;
endmodule
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