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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module alt_ifconv #(
// parameters
parameter WIDTH = 1,
parameter INTERFACE_NAME_IN = "input-interface-name",
parameter INTERFACE_NAME_OUT = "output-interface-name",
parameter SIGNAL_NAME_IN = "input-signal-name",
parameter SIGNAL_NAME_OUT = "output-signal-name") (
// bad tools - ugly stuff
input [(WIDTH-1):0] din,
output [(WIDTH-1):0] dout);
// avoiding qsys signal conflicts
assign dout = din;
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NOR2_PP_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2_PP_SYMBOL_V
|
`timescale 1ps/1ps
`include "alink_define.v"
module alink(
// system clock and reset
input CLK_I ,
input RST_I ,
// wishbone interface signals
input ALINK_CYC_I ,//NC
input ALINK_STB_I ,
input ALINK_WE_I ,
input ALINK_LOCK_I,//NC
input [2:0] ALINK_CTI_I ,//NC
input [1:0] ALINK_BTE_I ,//NC
input [5:0] ALINK_ADR_I ,
input [31:0] ALINK_DAT_I ,
input [3:0] ALINK_SEL_I ,
output ALINK_ACK_O ,
output ALINK_ERR_O ,//const 0
output ALINK_RTY_O ,//const 0
output [31:0] ALINK_DAT_O ,
//TX.PHY
output [`PHY_NUM-1:0] TX_P ,
output [`PHY_NUM-1:0] TX_N ,
//RX.PHY
input [`PHY_NUM-1:0] RX_P ,
input [`PHY_NUM-1:0] RX_N ,
output [4:0] ALINK_led
);
//-------------------------------------------------
// WBBUS
//-------------------------------------------------
assign ALINK_ERR_O = 1'b0 ;
assign ALINK_RTY_O = 1'b0 ;
wire [31:0] reg_tout ;
wire txfifo_push ;
wire [31:0] txfifo_din ;
wire [3:0] rxcnt ;
wire rxempty ;
wire [3:0] txcnt ;
wire reg_flush ;
wire txfull ;
wire [31:0] reg_mask ;
wire reg_scan ;
wire [31:0] busy ;
assign ALINK_led[0] = ~reg_mask[0] ;
assign ALINK_led[1] = ~reg_mask[1] ;
assign ALINK_led[2] = ~reg_mask[2] ;
assign ALINK_led[3] = ~reg_mask[3] ;
assign ALINK_led[4] = ~reg_mask[4] ;
wire rxfifo_pop ;
wire [31:0] rxfifo_dout ;
wire [31 : 0] tx_din ;
wire tx_wr_en ;
wire tx_rd_en ;
wire [31 : 0] tx_dout ;
wire [10 : 0] tx_data_count ;
wire [31 : 0] rx_din ;
wire rx_wr_en ;
wire [9 : 0] rx_data_count ;
wire tx_phy_start ;
wire [`PHY_NUM-1:0] tx_phy_sel ;
wire tx_phy_done ;
wire [1:0] cur_state ;
wire [1:0] nxt_state ;
wire [32*`PHY_NUM-1:0] timer_cnt ;//to slave
wire task_id_vld ;
wire [31:0] rx_phy_sel ;
wire [31:0] task_id_h ;
wire [31:0] task_id_l ;
//-------------------------------------------------
// Slave
//-------------------------------------------------
alink_slave alink_slave(
// system clock and reset
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I ) ,
// wishbone interface signals
/*input */ .ALINK_CYC_I (ALINK_CYC_I ) ,//NC
/*input */ .ALINK_STB_I (ALINK_STB_I ) ,
/*input */ .ALINK_WE_I (ALINK_WE_I ) ,
/*input */ .ALINK_LOCK_I(ALINK_LOCK_I ) ,//NC
/*input [2:0] */ .ALINK_CTI_I (ALINK_CTI_I ) ,//NC
/*input [1:0] */ .ALINK_BTE_I (ALINK_BTE_I ) ,//NC
/*input [5:0] */ .ALINK_ADR_I (ALINK_ADR_I ) ,
/*input [31:0] */ .ALINK_DAT_I (ALINK_DAT_I ) ,
/*input [3:0] */ .ALINK_SEL_I (ALINK_SEL_I ) ,
/*output reg */ .ALINK_ACK_O (ALINK_ACK_O ) ,
/*output */ .ALINK_ERR_O (ALINK_ERR_O ) ,//const 0
/*output */ .ALINK_RTY_O (ALINK_RTY_O ) ,//const 0
/*output reg [31:0] */ .ALINK_DAT_O (ALINK_DAT_O ) ,
/*output reg */ .txfifo_push (tx_wr_en ) ,
/*output reg [31:0] */ .txfifo_din (tx_din ) ,
/*input [9:0] */ .rxcnt (rx_data_count ) ,
/*input */ .rxempty (rxempty ) ,
/*input [10:0] */ .txcnt (tx_data_count ) ,
/*output reg */ .reg_flush (reg_flush ) ,
/*input */ .txfull (txfull ) ,
/*output reg [31:0] */ .reg_mask (reg_mask ) ,
/*output reg */ .reg_scan (reg_scan ) ,
/*input [31:0] */ .busy (busy ) ,
/*output */ .rxfifo_pop (rxfifo_pop ) ,
/*input [31:0] */ .rxfifo_dout (rxfifo_dout )
);
//-------------------------------------------------
// TX.FIFO
//-------------------------------------------------
assign txfull = ~((tx_data_count+`TX_DATA_LEN+`TX_TASKID_LEN) < `TX_FIFO_DEPTH) ;//tx fifo almost full
wire tx_task_vld = tx_data_count >= (`TX_DATA_LEN+`TX_TASKID_LEN) ;//at list ONE task in tx_fifo
tx_fifo tx_fifo(
/*input */ .clk (CLK_I ),
/*input */ .srst (RST_I|reg_flush ),
/*input [31 : 0]*/ .din (tx_din ),
/*input */ .wr_en (tx_wr_en ),
/*input */ .rd_en (tx_rd_en ),
/*output [31 : 0]*/ .dout (tx_dout ),
/*output */ .full ( ),
/*output */ .empty ( ),
/*output [10 : 0]*/ .data_count(tx_data_count )
) ;
//-------------------------------------------------
// RX.FIFO
//-------------------------------------------------
assign rxempty = rx_data_count < `RX_DATA_LEN ;
wire rx_almost_full = (rx_data_count + `RX_DATA_LEN*2) > `RX_FIFO_DEPTH ; //at list ONE report can be pull into rx_fifo
`ifdef SIM
always @ ( posedge rx_almost_full ) begin
#200 ;
$display("[WAR] rx fifo full:%d",rx_data_count);
end
`endif
rx_fifo rx_fifo(
/*input */ .clk (CLK_I ),
/*input */ .srst (RST_I|reg_flush ),
/*input [31 : 0]*/ .din (rx_din ),
/*input */ .wr_en (rx_wr_en ),
/*input */ .rd_en (rxfifo_pop ),
/*output [31 : 0]*/ .dout (rxfifo_dout ),
/*output */ .full (rx_full ),
/*output */ .empty ( ),
/*output [9 : 0] */ .data_count(rx_data_count )
);
//-------------------------------------------------
// TX.arbiter
//-------------------------------------------------
txc txc(
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I|reg_flush ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input [`PHY_NUM-1:0] */ .reg_mask (reg_mask ) ,
/*input */ .task_id_vld (task_id_vld ) ,
/*input [31:0] */ .reg_tout (reg_tout ) ,
/*input */ .tx_task_vld (tx_task_vld ) ,//tx fifo not empty
/*output reg */ .tx_phy_start(tx_phy_start ) ,
/*output reg [`PHY_NUM-1:0]*/ .tx_phy_sel (tx_phy_sel ) ,
/*input */ .tx_phy_done (tx_phy_done ) ,
/*output reg [1:0] */ .cur_state (cur_state ) ,
/*output reg [1:0] */ .nxt_state (nxt_state ) ,
/*output [32*`PHY_NUM-1:0] */ .timer_cnt (timer_cnt ) ,//to slave
/*output [`PHY_NUM-1:0] */ .reg_busy (busy )
);
//-------------------------------------------------
// TX.PHY
//-------------------------------------------------
tx_phy tx_phy(
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I|reg_flush ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input */ .reg_scan (reg_scan ) ,
/*input */ .tx_phy_start(tx_phy_start ) ,
/*input [31:0] */ .tx_phy_sel (tx_phy_sel ) ,
/*output */ .tx_phy_done (tx_phy_done ) ,
/*input [31:0] */ .tx_dout (tx_dout ) ,
/*output */ .tx_rd_en (tx_rd_en ) ,
/*output reg */ .task_id_vld (task_id_vld ) ,
/*output reg [31:0]*/ .rx_phy_sel (rx_phy_sel ) ,
/*output reg [31:0]*/ .task_id_h (task_id_h ) ,
/*output reg [31:0]*/ .task_id_l (task_id_l ) ,
/*output reg [31:0]*/ .reg_tout (reg_tout ) ,
/*output [31:0] */ .TX_P (TX_P ) ,
/*output [31:0] */ .TX_N (TX_N )
);
/*
// VIO/ILA and ICON {{{
wire [35:0] icon_ctrl_0;
wire [255:0] trig0 = {
4'ha ,//94:91
tx_data_count[10:0],//90:80
rx_data_count[9:0],//79:70
tx_dout[31:0],//69:38
tx_rd_en,//37
TX_P[1] ,//36
TX_N[1] ,//35
RX_P[1] ,//34
RX_N[1] ,//33
rx_wr_en ,//32
rx_din[31:0]//31:0
} ;
icon icon_test(.CONTROL0(icon_ctrl_0));
ila ila_test(.CONTROL(icon_ctrl_0), .CLK(CLK_I), .TRIG0(trig0)
);
*/
//-------------------------------------------------
// RX.PHY
//-------------------------------------------------
rxc rxc(
/*input */ .clk (CLK_I ) ,
/*input */ .rst (RST_I|reg_flush ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input [31:0]*/ .reg_mask (reg_mask ) ,
/*input [31:0]*/ .reg_busy (busy ) ,
/*input */ .rx_almost_full (rx_almost_full ) ,
/*input */ .tx_phy_start (tx_phy_start ) ,
/*input [31:0]*/ .tx_phy_sel (tx_phy_sel ) ,
/*input */ .task_id_vld (task_id_vld ) ,
/*input [31:0]*/ .rx_phy_sel (rx_phy_sel ) ,
/*input [31:0]*/ .task_id_h (task_id_h ) ,
/*input [31:0]*/ .task_id_l (task_id_l ) ,
/*input [32*`PHY_NUM-1:0]*/ .timer_cnt (timer_cnt ) ,
/*output */ .rx_vld (rx_wr_en ) ,
/*output [31:0]*/ .rx_dat (rx_din ) ,
/*input [31:0]*/ .RX_P (RX_P ) ,
/*input [31:0]*/ .RX_N (RX_N )
);
endmodule
|
module touch (
input ENABLE,
input clk,
input Rx,
input reset,
output [7:0] data,
output DONE,
output CLKOUT
);
wire [7:0] data_in;
wire wr;
wire ps2_error;
wire read;
wire write;
wire ps2_done;
wire fifo_empty;
wire fifo_full;
divisorfrec divisorfrec0 (
.clk ( clk ),
.CLKOUT ( CLKOUT )
);
ps2 ps2_0 (
.Rx ( Rx ),
.clk ( CLKOUT ),
.Rx_error( ps2_error ),
.DATA ( data_in ),
.DONE ( ps2_done )
);
fifo fifo0 (
.clk ( CLKOUT ),
.reset ( reset ),
.rd ( read ),
.wr ( write ),
.data_in ( data_in ),
.data_out( data ),
.full ( fifo_full ),
.empty ( fifo_empty )
);
controller controller0 (
.ENABLE ( ENABLE ),
.reset ( reset ),
.fifo_Empty ( fifo_empty ),
.fifo_full ( fifo_full ),
.ps2_done ( ps2_done ),
.ps2_error ( ps2_error ),
.DONE ( DONE ),
.read ( read ),
.write ( write )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_FUNCTIONAL_PP_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__inputisolatch (
Q ,
D ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SLEEP_B_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, SLEEP_B, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_1_V
`define SKY130_FD_SC_HD__DLRTN_1_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtn_1 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_1_V
|
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: double hash miner
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
module miner253 (clk, reset, midstate, data, golden_nonce, nonce2, hash2);
parameter NONCE_OFFS = 32'd0;
parameter NONCE_INCR = 32'd1;
parameter NONCE2_OFFS = 32'd0;
input clk, reset;
input [255:0] midstate;
input [95:0] data;
output reg [31:0] golden_nonce, hash2, nonce2;
reg [31:0] nonce;
wire [255:0] hash;
wire [31:0] hash2_w;
reg reset_b1, reset_b2, reset_b3, is_golden_nonce;
sha256_pipe130 p1 (
.clk(clk),
.state(midstate),
.state2(midstate),
.data({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash(hash)
);
sha256_pipe123 p2 (
.clk(clk),
.data({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash(hash2_w)
);
always @ (posedge clk)
begin
if ( reset_b1 )
begin
nonce <= 32'd254 + NONCE_OFFS;
end else begin
nonce <= nonce + NONCE_INCR;
end
if ( reset_b2 )
begin
nonce2 <= NONCE_OFFS + NONCE2_OFFS;
end else begin
nonce2 <= nonce2 + NONCE_INCR;
end
if ( reset_b3 )
begin
golden_nonce1 <= 32'd0;
golden_nonce2 <= 32'd0;
end
else if ( is_golden_nonce )
begin
golden_nonce1 <= nonce2;
golgen_nonce2 <= golden_nonce1;
end
reset_b1 <= reset;
reset_b2 <= reset;
reset_b3 <= reset;
hash2 <= hash2_w;
is_golden_nonce <= hash2_w == 32'ha41f32e7;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311O_2_V
`define SKY130_FD_SC_HD__A311O_2_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311O_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, rstn, dval0, dval1
);
input clk;
input rstn;
output wire [7:0] dout;
input [7:0] dval0;
input [7:0] dval1;
wire [7:0] dbgsel_w = '0;
tsub tsub (/*AUTOINST*/
// Outputs
.dout (dout[7:0]),
// Inputs
.clk (clk),
.rstn (rstn),
.dval0 (dval0[7:0]),
.dval1 (dval1[7:0]),
.dbgsel_w (dbgsel_w[7:0]));
endmodule
module tsub (/*AUTOARG*/
// Outputs
dout,
// Inputs
clk, rstn, dval0, dval1, dbgsel_w
);
input clk;
input rstn;
input [7:0] dval0;
input [7:0] dval1;
input [7:0] dbgsel_w;
output [7:0] dout;
wire [7:0] dout = dout0 | dout1;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] dout0; // From sub0 of sub0.v
wire [7:0] dout1; // From sub1 of sub1.v
// End of automatics
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
reg [7:0] dbgsel_msk;
always_comb begin
reg [7:0] mask;
mask = 8'hff;
dbgsel_msk = (dbgsel_w & mask);
end
// TODO this should optimize away, but presently does not because
// V3Gate constifies then doesn't see all other input edges have disappeared
reg [7:0] dbgsel;
always @(posedge clk) begin
if ((rstn == 0)) begin
dbgsel <= 0;
end
else begin
dbgsel <= dbgsel_msk;
end
end
sub0 sub0 (/*AUTOINST*/
// Outputs
.dout0 (dout0[7:0]),
// Inputs
.rstn (rstn),
.clk (clk),
.dval0 (dval0[7:0]),
.dbgsel (dbgsel[7:0]));
sub1 sub1 (/*AUTOINST*/
// Outputs
.dout1 (dout1[7:0]),
// Inputs
.rstn (rstn),
.clk (clk),
.dval1 (dval1[7:0]),
.dbgsel (dbgsel[7:0]));
endmodule
module sub0
(
/*AUTOARG*/
// Outputs
dout0,
// Inputs
rstn, clk, dval0, dbgsel
);
input rstn;
input clk;
input [7:0] dval0;
input [7:0] dbgsel;
output reg [7:0] dout0;
reg [7:0] dbgsel_d1r;
always_comb begin
// verilator lint_off WIDTH
if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin
// verilator lint_on WIDTH
dout0 = dval0;
end
else begin
dout0 = 0;
end
end
always @(posedge clk) begin
if ((rstn == 0)) begin
dbgsel_d1r <= 0;
end
else begin
dbgsel_d1r <= dbgsel;
end
end
endmodule
module sub1
(
/*AUTOARG*/
// Outputs
dout1,
// Inputs
rstn, clk, dval1, dbgsel
);
input rstn;
input clk;
input [7:0] dval1;
input [7:0] dbgsel;
output reg [7:0] dout1;
reg [7:0] dbgsel_d1r;
always_comb begin
if (((dbgsel_d1r >= 84) && (dbgsel_d1r < 95))) begin
dout1 = dval1;
end
else begin
dout1 = 0;
end
end
always @(posedge clk) begin
if ((rstn == 0)) begin
dbgsel_d1r <= 0;
end
else begin
dbgsel_d1r <= dbgsel;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_4_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_4_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for isobufsrc with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_4 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_4 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLCLKP_4_V
`define SKY130_FD_SC_HS__DLCLKP_4_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlclkp_4 (
GCLK,
GATE,
CLK ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlclkp_4 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLCLKP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFBBP_BLACKBOX_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_1_V
`define SKY130_FD_SC_LP__O2BB2A_1_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2bb2a_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_1_V
|
/*
* TOP2049 Open Source programming suite
*
* Cypress M8C/M7C In System Serial Programmer
* FPGA bottomhalf implementation
*
* Copyright (c) 2010-2011 Michael Buesch <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
/* The runtime ID and revision. */
`define RUNTIME_ID 16'h0007
`define RUNTIME_REV 16'h01
module m8c_issp(data, ale, write, read, osc_in, zif);
inout [7:0] data;
input ale;
input write;
input read;
input osc_in; /* 24MHz oscillator */
inout [48:1] zif;
/* Interface to the microcontroller */
wire read_oe; /* Read output-enable */
reg [7:0] address; /* Cached address value */
reg [7:0] read_data; /* Cached read data */
wire low, high; /* Constant lo/hi */
/* The M8C programmer context */
`define ISSP_VEC_SIZE 22 /* bits */
reg [1:0] issp_busy; /* Busy state. We're busy, if bits are unequal */
reg [7:0] issp_command; /* Currently loaded command */
reg [`ISSP_VEC_SIZE-1:0] issp_vector; /* Currently loaded output vector */
reg [5:0] issp_vecbit; /* Currently TXed/RXed bit */
reg [7:0] issp_count; /* General purpose counter */
reg [3:0] issp_state; /* Statemachine */
/* The M8C programmer commands */
`define ISSPCMD_NONE 0 /* No command loaded */
`define ISSPCMD_POR 1 /* Perform a power-on-reset */
`define ISSPCMD_PWROFF 2 /* Turn power off */
`define ISSPCMD_EXEC 3 /* Do an "execute" transfer */
`define IS_BUSY (issp_busy[0] != issp_busy[1])
`define SET_FINISHED issp_busy[1] <= issp_busy[0]
/* The M8C device signals */
wire sig_sdata;
wire sig_sdata_input;
wire sig_sclk;
wire sig_sclk_z;
reg dut_sdata;
reg dut_sdata_input;
reg dut_sclk;
reg dut_sclk_z;
reg dut_bitbang_disabled;
reg dut_bitbang_sdata;
reg dut_bitbang_sdata_input;
reg dut_bitbang_sclk;
reg dut_bitbang_sclk_z;
reg dut_vdd;
`define VDD_ON 1
`define VDD_OFF 0
`define ZIF_SDATA 22 /* SDATA ZIF pin */
assign low = 0;
assign high = 1;
/* The delay counter. Based on the 24MHz input clock. */
reg [15:0] delay_count;
wire osc;
IBUF osc_ibuf(.I(osc_in), .O(osc));
`define DELAY_250NS 6 - 1 /* 250 ns */
`define DELAY_1US 24 - 1 /* 1 us */
`define DELAY_1MS 24000 - 1 /* 1 ms */
`define DELAY_1P5MS 36000 - 1 /* 1.5 ms */
`define DELAY_2MS 48000 - 1 /* 2 ms */
initial begin
address <= 0;
read_data <= 0;
issp_busy <= 0;
issp_command <= 0;
issp_vector <= 0;
issp_vecbit <= 0;
issp_count <= 0;
issp_state <= 0;
dut_sdata <= 0;
dut_sdata_input <= 1;
dut_sclk <= 0;
dut_sclk_z <= 1;
dut_vdd <= `VDD_OFF;
dut_bitbang_disabled <= 0;
dut_bitbang_sdata <= 0;
dut_bitbang_sdata_input <= 1;
dut_bitbang_sclk <= 0;
dut_bitbang_sclk_z <= 1;
delay_count <= 0;
end
always @(posedge osc) begin
if (delay_count == 0 && `IS_BUSY) begin
case (issp_command)
`ISSPCMD_POR: begin
case (issp_state)
0: begin
/* Turn on power and wait vDDwait time */
dut_vdd <= `VDD_ON;
dut_bitbang_disabled <= 1;
dut_sclk_z <= 1;
dut_sclk <= 0;
dut_sdata_input <= 1;
delay_count <= `DELAY_1MS; /* TvDDwait */
issp_state <= 1;
end
1: begin
dut_sclk_z <= 0;
dut_sclk <= 0;
if (zif[`ZIF_SDATA] == 0) begin
issp_state <= 2;
issp_vecbit <= `ISSP_VEC_SIZE;
end
// delay_count <= `DELAY_250NS;
end
2: begin
if (issp_vecbit == 0) begin
issp_state <= 4;
end else begin
/* Ok, ready to send the next bit */
dut_sdata_input <= 0;
dut_sdata <= issp_vector[issp_vecbit - 1];
dut_sclk <= 1;
issp_state <= 3;
end
delay_count <= `DELAY_250NS;
end
3: begin
dut_sclk <= 0;
issp_state <= 2;
issp_vecbit <= issp_vecbit - 1;
delay_count <= `DELAY_250NS;
end
4: begin
/* We're done. */
`SET_FINISHED;
dut_bitbang_disabled <= 0;
dut_sclk <= 0;
dut_sdata_input <= 1;
issp_state <= 0;
end
endcase
end
`ISSPCMD_PWROFF: begin
dut_vdd <= `VDD_OFF;
dut_bitbang_disabled <= 0;
dut_sdata <= 0;
dut_sdata_input <= 1;
dut_sclk <= 0;
dut_sclk_z <= 1;
issp_state <= 0;
delay_count <= 0;
/* We're done. */
`SET_FINISHED;
end
`ISSPCMD_EXEC: begin
case (issp_state)
0: begin /* Init */
dut_bitbang_disabled <= 1;
dut_sdata <= 0;
dut_sdata_input <= 1;
dut_sclk_z <= 0;
dut_sclk <= 0;
issp_count <= 10;
issp_state <= 1;
end
1: begin /* Wait for SDATA=1 */
if (zif[`ZIF_SDATA]) begin
issp_state <= 5; /* goto wait-for-SDATA=0 */
end else begin
delay_count <= `DELAY_1US;
issp_count <= issp_count - 1;
issp_state <= 2;
end
end
2: begin
if (issp_count == 0) begin
/* Timeout */
issp_state <= 3; /* Send 33 CLKs */
issp_count <= 33;
end else begin
issp_state <= 1;
end
end
3: begin /* Send 33 CLKs */
dut_sclk <= 1;
issp_count <= issp_count - 1;
delay_count <= `DELAY_250NS;
issp_state <= 4;
end
4: begin
dut_sclk <= 0;
if (issp_count == 0) begin
/* Sent all */
if (zif[`ZIF_SDATA]) begin
issp_state <= 5; /* goto wait-for-SDATA=0 */
end else begin
/* goto send-50-CLKs */
issp_state <= 6;
issp_count <= 50;
end
end else begin
issp_state <= 3;
end
delay_count <= `DELAY_250NS;
end
5: begin /* Wait for SDATA=0 */
if (zif[`ZIF_SDATA] == 0) begin
issp_state <= 6;
issp_count <= 50;
end else begin
issp_state <= 5;
end
delay_count <= `DELAY_250NS;
end
6: begin /* Send 50 CLKs */
dut_sclk <= 1;
issp_count <= issp_count - 1;
delay_count <= `DELAY_250NS;
issp_state <= 7;
end
7: begin
dut_sclk <= 0;
if (issp_count == 0) begin
issp_state <= 8; /* done */
end else begin
issp_state <= 6;
end
delay_count <= `DELAY_250NS;
end
8: begin /* finish */
/* We're done. */
dut_bitbang_disabled <= 0;
issp_state <= 0;
`SET_FINISHED;
end
endcase
end
endcase
end else begin
if (delay_count) begin
delay_count <= delay_count - 1;
end
end
end
always @(posedge write) begin
case (address)
8'h10: begin
/* Bitbanging */
dut_bitbang_sdata <= data[0];
dut_bitbang_sdata_input <= data[1];
dut_bitbang_sclk <= data[2];
dut_bitbang_sclk_z <= data[3];
end
8'h11: begin
/* Load and execute command */
issp_command <= data;
issp_busy[0] <= ~issp_busy[1];
end
8'h12: begin
/* Load vector low */
issp_vector[7:0] <= data;
end
8'h13: begin
/* Load vector med */
issp_vector[15:8] <= data;
end
8'h14: begin
/* Load vector high */
issp_vector[21:16] <= data[5:0];
end
endcase
end
always @(negedge read) begin
case (address)
8'h10: begin
/* Read status */
read_data[0] <= issp_busy[0];
read_data[1] <= issp_busy[1];
read_data[2] <= issp_state[0];
read_data[3] <= issp_state[1];
read_data[4] <= issp_state[2];
read_data[5] <= zif[`ZIF_SDATA];
read_data[6] <= 0;
read_data[7] <= 0;
end
8'hFD: read_data <= `RUNTIME_ID & 16'hFF;
8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF;
8'hFF: read_data <= `RUNTIME_REV;
endcase
end
always @(negedge ale) begin
address <= data;
end
assign read_oe = !read && address[4];
assign sig_sdata = dut_bitbang_disabled ? dut_sdata : dut_bitbang_sdata;
assign sig_sdata_input = dut_bitbang_disabled ? dut_sdata_input : dut_bitbang_sdata_input;
assign sig_sclk = dut_bitbang_disabled ? dut_sclk : dut_bitbang_sclk;
assign sig_sclk_z = dut_bitbang_disabled ? dut_sclk_z : dut_bitbang_sclk_z;
bufif0(zif[1], low, low);
bufif0(zif[2], low, low);
bufif0(zif[3], low, low);
bufif0(zif[4], low, low);
bufif0(zif[5], low, low);
bufif0(zif[6], low, low);
bufif0(zif[7], low, low);
bufif0(zif[8], low, low);
bufif0(zif[9], low, low);
bufif0(zif[10], low, low);
bufif0(zif[11], low, low);
bufif0(zif[12], low, low);
bufif0(zif[13], low, low);
bufif0(zif[14], low, low);
bufif0(zif[15], low, low);
bufif0(zif[16], low, low);
bufif0(zif[17], low, low);
bufif0(zif[18], low, low);
bufif0(zif[19], low, low);
bufif0(zif[20], low, low); /* GND */
bufif0(zif[21], high, low); /* VDD */
bufif0(zif[`ZIF_SDATA], sig_sdata, sig_sdata_input); /* SDATA */
bufif0(zif[23], sig_sclk, sig_sclk_z); /* SCLK */
bufif0(zif[24], dut_vdd, low); /* VDDen */
bufif0(zif[25], low, low);
bufif0(zif[26], low, low);
bufif0(zif[27], low, low);
bufif0(zif[28], low, low);
bufif0(zif[29], low, low);
bufif0(zif[30], low, low);
bufif0(zif[31], low, low);
bufif0(zif[32], low, low);
bufif0(zif[33], low, low);
bufif0(zif[34], low, low);
bufif0(zif[35], low, low);
bufif0(zif[36], low, low);
bufif0(zif[37], low, low);
bufif0(zif[38], low, low);
bufif0(zif[39], low, low);
bufif0(zif[40], low, low);
bufif0(zif[41], low, low);
bufif0(zif[42], low, low);
bufif0(zif[43], low, low);
bufif0(zif[44], low, low);
bufif0(zif[45], low, low);
bufif0(zif[46], low, low);
bufif0(zif[47], low, low);
bufif0(zif[48], low, low);
bufif1(data[0], read_data[0], read_oe);
bufif1(data[1], read_data[1], read_oe);
bufif1(data[2], read_data[2], read_oe);
bufif1(data[3], read_data[3], read_oe);
bufif1(data[4], read_data[4], read_oe);
bufif1(data[5], read_data[5], read_oe);
bufif1(data[6], read_data[6], read_oe);
bufif1(data[7], read_data[7], read_oe);
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFRBP_FUNCTIONAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRBP_FUNCTIONAL_PP_V |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_cmd_gen
# (parameter
// cmd_gen settings
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 4,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_DWIDTH_RATIO = 2, // 2-FR,4-HR,8-QR
CFG_CTL_QUEUE_DEPTH = 8,
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary coded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_ENABLE_QUEUE = 1,
CFG_ENABLE_BURST_MERGE = 1,
CFG_CMD_GEN_OUTPUT_REG = 0,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1
)
(
ctl_clk,
ctl_reset_n,
// tbp interface
tbp_full,
tbp_load,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
cmd_gen_load,
cmd_gen_waiting_to_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_multicast,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
cmd_gen_busy,
// input interface
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_id,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
// datapath interface
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
proc_read,
proc_size,
proc_localid,
wdatap_free_id_valid, // from wdata path
wdatap_free_id_dataid, // from wdata path
rdatap_free_id_valid, // from rdata path
rdatap_free_id_dataid, // from rdata path
tbp_load_index,
data_complete,
data_rmw_complete,
// nodm and ecc signal
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
data_partial_be,
// configuration ports
cfg_enable_cmd_split,
cfg_burst_length,
cfg_addr_order,
cfg_enable_ecc,
cfg_enable_no_dm,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width
);
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam BUFFER_WIDTH = 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + CFG_DATA_ID_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH;
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2(CFG_LOCAL_ADDR_WIDTH);
localparam INT_LOCAL_ADDR_WIDTH = 2**CFG_LOCAL_ADDR_BITSELECT_WIDTH;
localparam CFG_CMD_GEN_SPLIT_REGISTERED = 1;
localparam CFG_LOCAL_BURST_MERGE_IDCMP = 0; //Enable/Disable Local ID compare for burst merge
//ECC State Machine
localparam IDLE = 4'h0;
localparam CORRECT_RD = 4'h1;
localparam PARWR_WR = 4'h2;
localparam FULL_WR = 4'h3;
localparam PARWR_RD = 4'h4;
localparam FULL_RD = 4'h6;
localparam CORRECT_WR = 4'h8;
input ctl_clk;
input ctl_reset_n;
input tbp_full;
input [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] tbp_read;
input [CFG_CTL_TBP_NUM-1:0] tbp_write;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output cmd_gen_load;
output cmd_gen_waiting_to_load;
output [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
output cmd_gen_write;
output cmd_gen_read;
output cmd_gen_multicast;
output [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
output [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
output cmd_gen_priority;
output cmd_gen_rmw_correct;
output cmd_gen_rmw_partial;
output cmd_gen_autopch;
output cmd_gen_complete;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output cmd_gen_busy;
output cmd_gen_full;
input cmd_valid;
input [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
input cmd_write;
input cmd_read;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
input cmd_multicast;
input [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
input cmd_priority;
input cmd_autoprecharge;
output proc_busy;
output proc_load;
output proc_load_dataid;
output proc_write;
output proc_read;
output [CFG_INT_SIZE_WIDTH-1:0] proc_size;
output [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
input wdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
input rdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input data_rmw_complete;
output errcmd_ready; // high means cmd_gen accepts command
input errcmd_valid;
input [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
input [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
input data_partial_be;
input cfg_enable_cmd_split;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length; // this contains immediate BL value, max is 31
input [CFG_PORT_WIDTH_ADDR_ORDER-1:0] cfg_addr_order; // 0 is chiprowbankcol , 1 is chipbankrowcol , 2 is rowchipbankcol
input cfg_enable_ecc;
input cfg_enable_no_dm;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH-1:0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH-1:0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH-1:0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH-1:0] cfg_cs_addr_width;
// === address mapping
integer n;
integer j;
integer k;
integer m;
wire cfg_enable_rmw;
wire take_from_ecc_correct;
wire ecc_queue_load;
wire split_queue_load;
wire split_queue_load_for_avl;
wire split_queue_load_init;
wire split_queue_load_ecc_load;
reg split_queue_load_open;
wire split_queue_load_open_final;
wire split_queue_fast_unload;
reg [3:0] ecc_state_sm;
wire [INT_LOCAL_ADDR_WIDTH-1:0] int_cmd_address;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_col_addr;
// === command splitting block
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_split_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_split_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_split_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_split_col_addr;
reg int_split_read;
wire int_split_read_final;
reg int_split_write;
wire int_split_write_final;
reg [CFG_INT_SIZE_WIDTH-1:0] int_split_size;
reg int_split_autopch;
reg int_split_multicast;
reg int_split_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] int_split_localid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] split_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] split_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] split_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] split_col_addr;
reg split_read;
reg split_write;
reg [CFG_INT_SIZE_WIDTH-1:0] split_size;
reg split_autopch;
reg split_multicast;
reg split_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] split_localid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] buf_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] buf_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] buf_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] buf_col_addr;
reg buf_read_req;
reg buf_write_req;
reg buf_autopch_req;
reg buf_multicast;
reg buf_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] buf_localid;
reg [CFG_LOCAL_SIZE_WIDTH:0] buf_size;
reg buf_chip_addr_reach_max;
reg buf_bank_addr_reach_max;
reg buf_row_addr_reach_max;
reg buf_col_addr_reach_max;
reg [3 : 0] int_buf_row_addr_reach_max;
reg [CFG_INT_SIZE_WIDTH-1:0] decrmntd_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] incrmntd_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] incrmntd_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] incrmntd_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] incrmntd_col_addr;
reg [CFG_MEM_IF_CS_WIDTH-1:0] max_chip_from_csr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] max_bank_from_csr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] max_row_from_csr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] max_col_from_csr;
wire copy;
reg [2:0] unaligned_burst; // because planned max native size is 8, unaligned burst can be a max of 7
reg [3:0] native_size; // support native size up to 15, bl16 FR have native size of 8
reg [4:0] native_size_x2;
wire require_gen;
reg deassert_ready;
reg registered;
reg generating;
// === ecc mux
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr;
reg ecc_read;
reg ecc_write;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size;
reg ecc_autopch;
reg ecc_multicast;
reg ecc_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid;
reg ecc_correct;
reg ecc_partial;
reg ecc_rmw_read;
reg ecc_rmw_write;
reg errcmd_ready;
reg correct;
reg partial_opr;
wire mux_busy;
wire mux_busy_non_ecc;
wire mux_busy_ecc;
wire [CFG_MEM_IF_CS_WIDTH-1:0] muxed_cs_addr;
wire [CFG_MEM_IF_BA_WIDTH-1:0] muxed_bank_addr;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] muxed_row_addr;
wire [CFG_MEM_IF_COL_WIDTH-1:0] muxed_col_addr;
wire muxed_read;
wire muxed_write;
wire [CFG_INT_SIZE_WIDTH-1:0] muxed_size;
wire muxed_autopch;
wire muxed_multicast;
wire muxed_priority;
wire [CFG_LOCAL_ID_WIDTH-1:0] muxed_localid;
wire [CFG_DATA_ID_WIDTH-1:0] muxed_dataid;
wire muxed_complete;
wire muxed_correct;
wire muxed_partial;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
reg ecc_proc_busy;
reg ecc_proc_busy_parwr_read_queue_load;
reg ecc_proc_load;
reg ecc_proc_load_dataid;
reg ecc_proc_write;
reg ecc_proc_read;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_proc_size;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_proc_localid;
reg waiting_to_load;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_row;
// === queue
reg [BUFFER_WIDTH-1:0] pipe[CFG_CTL_QUEUE_DEPTH-1:0];
reg pipefull[CFG_CTL_QUEUE_DEPTH-1:0];
wire fetch;
wire [BUFFER_WIDTH-1:0] buffer_input;
wire write_to_queue;
wire queue_full;
wire cmd_gen_load;
wire cmd_gen_waiting_to_load;
wire [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_row_addr;
reg read [CFG_CTL_TBP_NUM-1:0];
reg write [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
wire [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_ecc_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_ecc_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_ecc_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_ecc_col_addr;
reg int_ecc_read;
wire int_ecc_read_final;
reg int_ecc_write;
wire int_ecc_write_final;
reg [CFG_INT_SIZE_WIDTH-1:0] int_ecc_size;
reg int_ecc_autopch;
reg int_ecc_multicast;
reg int_ecc_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] int_ecc_localid;
reg [CFG_DATA_ID_WIDTH-1:0] int_ecc_dataid;
reg int_ecc_data_complete;
reg int_ecc_partial_be;
wire int_ecc_data_complete_final;
wire int_ecc_partial_be_final;
//Burst merge
wire cmd_gen_full_postq;
wire cmd_valid_postq;
wire cmd_write_postq;
wire cmd_read_postq;
wire [CFG_LOCAL_ID_WIDTH-1:0] cmd_id_postq;
wire cmd_multicast_postq;
wire [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size_postq;
wire [CFG_LOCAL_SIZE_WIDTH:0] cmd_size_plus_unaligned_size;
wire cmd_priority_postq;
wire cmd_autoprecharge_postq;
wire [CFG_MEM_IF_CS_WIDTH-1:0] int_cs_addr_postq;
wire [CFG_MEM_IF_BA_WIDTH-1:0] int_bank_addr_postq;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] int_row_addr_postq;
wire [CFG_MEM_IF_COL_WIDTH-1:0] int_col_addr_postq;
wire one;
//======================================================================================
//
// [START] General
//
//======================================================================================
assign cfg_enable_rmw = cfg_enable_ecc | cfg_enable_no_dm;
assign one = 1'b1;
//======================================================================================
//
// [END] General
//
//======================================================================================
//======================================================================================
//
// [START] TBP Info
//
//======================================================================================
generate
genvar p;
for (p=0; p<CFG_CTL_TBP_NUM; p=p+1)
begin : info_per_tbp
always @ (*)
begin
read [p] = tbp_read [p];
write [p] = tbp_write [p];
chipsel[p] = tbp_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
bank [p] = tbp_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
row [p] = tbp_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
col [p] = tbp_col [(p+1)*CFG_MEM_IF_COL_WIDTH-1:p*CFG_MEM_IF_COL_WIDTH];
end
end
for (p=0; p<CFG_CTL_SHADOW_TBP_NUM; p=p+1)
begin : info_per_shadow_tbp
assign shadow_chipsel[p] = tbp_shadow_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
assign shadow_bank [p] = tbp_shadow_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
assign shadow_row [p] = tbp_shadow_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
end
endgenerate
//======================================================================================
//
// [END] TBP Info
//
//======================================================================================
//======================================================================================
//
// [START] Address re-mapping
//
//======================================================================================
// Pre-calculate int_*_addr chipsel, bank, row, col bit select offsets
always @ (*)
begin
// Row width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_row = cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_row = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_row = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Bank width info
if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_bank = cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_bank = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Chipsel width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
end
assign int_cmd_address = cmd_address;
// Supported addr order
// 0 - chip-row-bank-col
// 1 - chip-bank-row-col
// 2 - row-chip-bank-col
// Derive column address from address
always @(*)
begin : Col_addr_loop
int_col_addr[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0] = int_cmd_address[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0];
for (n = MIN_COL - log2(CFG_DWIDTH_RATIO);n < MAX_COL;n = n + 1'b1)
begin
if (n < (cfg_col_addr_width - log2(CFG_DWIDTH_RATIO))) // Bit of col_addr can be configured in CSR using cfg_col_addr_width
begin
int_col_addr[n] = int_cmd_address[n];
end
else
begin
int_col_addr[n] = 1'b0;
end
end
int_col_addr = int_col_addr << log2(CFG_DWIDTH_RATIO);
end
// Derive row address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_2;
always @(*)
begin : Row_addr_loop
for (j = 0;j < MIN_ROW;j = j + 1'b1) // The purpose of using this for-loop is to get rid of "if (j < cfg_row_addr_width) begin" which causes multiplexers
begin
row_addr_loop_1 = j + cfg_addr_bitsel_row;
int_row_addr[j] = int_cmd_address[row_addr_loop_1];
end
for (j = MIN_ROW;j < MAX_ROW;j = j + 1'b1)
begin
row_addr_loop_2 = j + cfg_addr_bitsel_row;
if(j < cfg_row_addr_width) // Bit of row_addr can be configured in CSR using cfg_row_addr_width
begin
int_row_addr[j] = int_cmd_address[row_addr_loop_2];
end
else
begin
int_row_addr[j] = 1'b0;
end
end
end
// Derive bank address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_2;
always @(*)
begin : Bank_addr_loop
for (k = 0;k < MIN_BANK;k = k + 1'b1) // The purpose of using this for-loop is to get rid of "if (k < cfg_bank_addr_width) begin" which causes multiplexers
begin
bank_addr_loop_1 = k + cfg_addr_bitsel_bank;
int_bank_addr[k] = int_cmd_address[bank_addr_loop_1];
end
for (k = MIN_BANK;k < MAX_BANK;k = k + 1'b1)
begin
bank_addr_loop_2 = k + cfg_addr_bitsel_bank;
if (k < cfg_bank_addr_width) // Bit of bank_addr can be configured in CSR using cfg_bank_addr_width
begin
int_bank_addr[k] = int_cmd_address[bank_addr_loop_2];
end
else
begin
int_bank_addr[k] = 1'b0;
end
end
end
// Derive chipsel address from address
always @(*)
begin
m = 0;
if (cfg_cs_addr_width > 1'b0) // If cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
begin
for (m=0; m<MIN_CS; m=m+1'b1) // The purpose of using this for-loop is to get rid of "if (m < cfg_cs_addr_width) begin" which causes multiplexers
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1)
begin
if (m < cfg_cs_addr_width) // Bit of cs_addr can be configured in CSR using cfg_cs_addr_width
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
else
begin
int_cs_addr[m] = 1'b0;
end
end
end
else // If CFG_MEM_IF_CS_WIDTH = 1, then set cs_addr to 0 (one chip, one rank)
begin
int_cs_addr = {CFG_MEM_IF_CS_WIDTH{1'b0}};
end
end
//======================================================================================
//
// [END] Address re-mapping
//
//======================================================================================
//======================================================================================
//
// [START] Burst Merge
//
//======================================================================================
generate
if (CFG_ENABLE_BURST_MERGE == 1)
begin
reg cmd_write_str[1:0];
wire cmd_read_str[1:0];
reg [CFG_LOCAL_ID_WIDTH-1:0] cmd_id_str[1:0];
reg cmd_multicast_str[1:0];
reg [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size_str[1:0];
reg cmd_priority_str[1:0];
reg cmd_autoprecharge_str[1:0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cs_addr_str[1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_bank_addr_str[1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_row_addr_str[1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_col_addr_str[1:0];
reg [1:0] bm_write_ptr;
reg [1:0] bm_read_ptr;
wire bm_cs_can_merge;
wire bm_bank_can_merge;
wire bm_row_can_merge;
wire bm_read_can_merge;
wire bm_write_can_merge;
wire bm_localid_can_merge;
wire bm_valid_can_merge;
wire bm_seqcol_can_merge;
wire [CFG_MEM_IF_COL_WIDTH:0] bm_nextcol_can_merge;
wire [CFG_MEM_IF_COL_WIDTH-1:0] bm_base_col_addr;
wire [CFG_LOCAL_SIZE_WIDTH-1:0] bm_base_size;
wire [CFG_MEM_IF_COL_WIDTH-1:0] bm_nextbase_col_addr;
wire [CFG_LOCAL_SIZE_WIDTH:0] bm_total_merge_size;
wire bm_oversize;
wire bm_cross_row;
wire bm_can_merge;
assign cmd_gen_full = (bm_write_ptr[1] != bm_read_ptr[1]) && (bm_write_ptr[0] == bm_read_ptr[0]);
assign cmd_valid_postq = (bm_write_ptr != bm_read_ptr);
assign cmd_read_str[0] = !cmd_write_str[0];
assign cmd_read_str[1] = !cmd_write_str[1];
assign int_col_addr_postq = bm_read_ptr[0] ? int_col_addr_str[1] : int_col_addr_str[0];
assign int_row_addr_postq = bm_read_ptr[0] ? int_row_addr_str[1] : int_row_addr_str[0];
assign int_bank_addr_postq = bm_read_ptr[0] ? int_bank_addr_str[1] : int_bank_addr_str[0];
assign int_cs_addr_postq = bm_read_ptr[0] ? int_cs_addr_str[1] : int_cs_addr_str[0];
assign cmd_write_postq = bm_read_ptr[0] ? cmd_write_str[1] : cmd_write_str[0];
assign cmd_read_postq = bm_read_ptr[0] ? cmd_read_str[1] : cmd_read_str[0];
assign cmd_id_postq = bm_read_ptr[0] ? cmd_id_str[1] : cmd_id_str[0];
assign cmd_multicast_postq = bm_read_ptr[0] ? cmd_multicast_str[1] : cmd_multicast_str[0];
assign cmd_size_postq = bm_read_ptr[0] ? cmd_size_str[1] : cmd_size_str[0];
assign cmd_priority_postq = bm_read_ptr[0] ? cmd_priority_str[1] : cmd_priority_str[0];
assign cmd_autoprecharge_postq = bm_read_ptr[0] ? cmd_autoprecharge_str[1] : cmd_autoprecharge_str[0];
assign bm_cs_can_merge = (int_cs_addr_str[1] == int_cs_addr_str[0]);
assign bm_bank_can_merge = (int_bank_addr_str[1] == int_bank_addr_str[0]);
assign bm_row_can_merge = (int_row_addr_str[1] == int_row_addr_str[0]);
assign bm_read_can_merge = (cmd_read_str[1] == cmd_read_str[0]);
assign bm_write_can_merge = (cmd_write_str[1] == cmd_write_str[0]);
assign bm_localid_can_merge = (CFG_LOCAL_BURST_MERGE_IDCMP == 1) ? (cmd_id_str[1] == cmd_id_str[0]) : 1'b1;
assign bm_valid_can_merge = cmd_gen_full;
assign bm_nextcol_can_merge = bm_base_col_addr + (bm_base_size * CFG_DWIDTH_RATIO);
assign bm_base_col_addr = int_col_addr_postq;
assign bm_base_size = cmd_size_postq;
assign bm_nextbase_col_addr = bm_read_ptr[0] ? int_col_addr_str[0] : int_col_addr_str[1]; //reverse ordr
assign bm_seqcol_can_merge = (bm_nextcol_can_merge == bm_nextbase_col_addr);
assign bm_total_merge_size = cmd_size_str[1] + cmd_size_str[0];
assign bm_oversize = (bm_total_merge_size[CFG_LOCAL_SIZE_WIDTH] == 1);
assign bm_cross_row = (bm_nextcol_can_merge[CFG_MEM_IF_COL_WIDTH] == 1);
assign bm_can_merge = (CFG_ENABLE_BURST_MERGE == 1) ? (bm_valid_can_merge && bm_read_can_merge && bm_write_can_merge && bm_localid_can_merge && bm_bank_can_merge && bm_row_can_merge && bm_cs_can_merge && bm_seqcol_can_merge && !bm_oversize && !bm_cross_row && cmd_gen_full_postq) : 0;
//2 deep queue
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_col_addr_str[0] <= 0;
int_row_addr_str[0] <= 0;
int_bank_addr_str[0] <= 0;
int_cs_addr_str[0] <= 0;
cmd_write_str[0] <= 0;
cmd_id_str[0] <= 0;
cmd_multicast_str[0] <= 0;
cmd_size_str[0] <= 0;
cmd_priority_str[0] <= 0;
cmd_autoprecharge_str[0] <= 0;
end
else
begin
if (cmd_valid && !cmd_gen_full && (bm_write_ptr[0] == 0))
begin
int_col_addr_str[0] <= int_col_addr;
int_row_addr_str[0] <= int_row_addr;
int_bank_addr_str[0] <= int_bank_addr;
int_cs_addr_str[0] <= int_cs_addr;
cmd_write_str[0] <= cmd_write;
cmd_id_str[0] <= cmd_id;
cmd_multicast_str[0] <= cmd_multicast;
cmd_size_str[0] <= cmd_size;
cmd_priority_str[0] <= cmd_priority;
cmd_autoprecharge_str[0] <= cmd_autoprecharge;
end
else if (bm_can_merge)
begin
if ((bm_read_ptr[0] == 1))
begin
int_col_addr_str[0] <= int_col_addr_str[1];
end
cmd_size_str[0] <= cmd_size_str[0] + cmd_size_str[1];
cmd_priority_str[0] <= cmd_priority_str[0] || cmd_priority_str[1];
cmd_autoprecharge_str[0] <= cmd_autoprecharge_str[0] || cmd_autoprecharge_str[1];
cmd_multicast_str[0] <= cmd_multicast_str[0] || cmd_multicast_str[1];
end
end
end
//2 deep queue
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_col_addr_str[1] <= 0;
int_row_addr_str[1] <= 0;
int_bank_addr_str[1] <= 0;
int_cs_addr_str[1] <= 0;
cmd_write_str[1] <= 0;
cmd_id_str[1] <= 0;
cmd_multicast_str[1] <= 0;
cmd_size_str[1] <= 0;
cmd_priority_str[1] <= 0;
cmd_autoprecharge_str[1] <= 0;
end
else
begin
if (cmd_valid && !cmd_gen_full && (bm_write_ptr[0] == 1))
begin
int_col_addr_str[1] <= int_col_addr;
int_row_addr_str[1] <= int_row_addr;
int_bank_addr_str[1] <= int_bank_addr;
int_cs_addr_str[1] <= int_cs_addr;
cmd_write_str[1] <= cmd_write;
cmd_id_str[1] <= cmd_id;
cmd_multicast_str[1] <= cmd_multicast;
cmd_size_str[1] <= cmd_size;
cmd_priority_str[1] <= cmd_priority;
cmd_autoprecharge_str[1] <= cmd_autoprecharge;
end
end
end
//write pointer
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bm_write_ptr <= 0;
end
else
begin
if (cmd_valid && !cmd_gen_full)
begin
bm_write_ptr <= bm_write_ptr + 1;
end
else if (bm_can_merge)
begin
bm_write_ptr <= 1;
end
end
end
//read pointer
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bm_read_ptr <= 0;
end
else
begin
if (cmd_valid_postq && !cmd_gen_full_postq)
begin
bm_read_ptr <= bm_read_ptr + 1;
end
else if (bm_can_merge)
begin
bm_read_ptr <= 0;
end
end
end
end
else
begin
assign cmd_gen_full = cmd_gen_full_postq;
assign cmd_valid_postq = cmd_valid;
assign cmd_write_postq = cmd_write;
assign cmd_read_postq = cmd_read;
assign cmd_id_postq = cmd_id;
assign cmd_multicast_postq = cmd_multicast;
assign cmd_size_postq = cmd_size;
assign cmd_priority_postq = cmd_priority;
assign cmd_autoprecharge_postq = cmd_autoprecharge;
assign int_cs_addr_postq = int_cs_addr;
assign int_bank_addr_postq = int_bank_addr;
assign int_row_addr_postq = int_row_addr;
assign int_col_addr_postq = int_col_addr;
end
endgenerate
//======================================================================================
//
// [END] Burst Merge
//
//======================================================================================
//======================================================================================
//
// [START] Burst splitting
//
//======================================================================================
assign cmd_gen_busy = cmd_gen_load || cmd_valid;
assign cmd_gen_full_postq = mux_busy | deassert_ready;
assign copy = ~cmd_gen_full_postq & cmd_valid_postq; // Copy current input command info into a register
assign cmd_size_plus_unaligned_size = unaligned_burst + cmd_size_postq;
assign require_gen = (cmd_size_postq > native_size | cmd_size_plus_unaligned_size > native_size) & cfg_enable_cmd_split; // Indicate that current input command require splitting
// CSR address calculation
always @ (*)
begin
max_chip_from_csr = (2**cfg_cs_addr_width) - 1'b1;
max_bank_from_csr = (2**cfg_bank_addr_width) - 1'b1;
max_row_from_csr = (2**cfg_row_addr_width) - 1'b1;
max_col_from_csr = (2**cfg_col_addr_width) - 1'b1;
end
// Calculate native size for selected burstlength and controller rate
always @ (*)
begin
native_size = 1 * (cfg_burst_length / CFG_DWIDTH_RATIO); // 1 for bl2 FR, 2 for bl8 HR, ...
native_size_x2 = 2 * (cfg_burst_length / CFG_DWIDTH_RATIO); // 2X of original native size
end
always @(*)
begin
if (native_size == 1)
begin
unaligned_burst = 0;
end
else if (native_size == 2)
begin
unaligned_burst = {2'd0,int_col_addr_postq[log2(CFG_DWIDTH_RATIO)]};
end
else if (native_size == 4)
begin
unaligned_burst = {1'd0,int_col_addr_postq[(log2(CFG_DWIDTH_RATIO)+1):log2(CFG_DWIDTH_RATIO)]};
end
else // native_size == 8
begin
unaligned_burst = int_col_addr_postq[(log2(CFG_DWIDTH_RATIO)+2):log2(CFG_DWIDTH_RATIO)];
end
end
// Deassert local_ready signal because need to split local command into multiple memory commands
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
deassert_ready <= 0;
end
else
begin
if (copy && require_gen)
begin
deassert_ready <= 1;
end
else if ((buf_size > native_size_x2) && cfg_enable_cmd_split)
begin
deassert_ready <= 1;
end
else if (generating && ~mux_busy)
begin
deassert_ready <= 0;
end
end
end
// Assert register signal so that we will pass split command into TBP
always @ (*)
begin
if (copy && require_gen)
begin
registered = 1;
end
else
begin
registered = 0;
end
end
// Generating signal will notify that current command in under splitting process
// Signal stays high until the last memory burst aligned command is generated
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
generating <= 0;
end
else
begin
if (registered)
begin
generating <= 1;
end
else if ((generating && buf_size > native_size_x2) && cfg_enable_cmd_split)
begin
generating <= 1;
end
else if (~mux_busy)
begin
generating <= 0;
end
end
end
// Determine the correct size
always @(*)
begin
if (!generating)
begin
if ((cmd_size_plus_unaligned_size < native_size) || !cfg_enable_cmd_split) //(local_size > 1 && !unaligned_burst)
begin
int_split_size = cmd_size_postq;
end
else
begin
int_split_size = native_size - unaligned_burst;
end
end
else
begin
int_split_size = decrmntd_size;
end
end
// MUX logic to determine where to take the command info from
always @(*)
begin
if (!generating) // not generating so take direct input from avalon if
begin
int_split_read = cmd_read_postq & cmd_valid_postq;
int_split_write = cmd_write_postq & cmd_valid_postq;
int_split_autopch = cmd_autoprecharge_postq;
int_split_multicast = cmd_multicast_postq;
int_split_priority = cmd_priority_postq;
int_split_localid = cmd_id_postq;
int_split_cs_addr = int_cs_addr_postq;
int_split_bank_addr = int_bank_addr_postq;
int_split_row_addr = int_row_addr_postq;
int_split_col_addr = int_col_addr_postq;
end
else // generating cmd so process buffer content
begin
int_split_read = buf_read_req;
int_split_write = buf_write_req;
int_split_autopch = buf_autopch_req;
int_split_multicast = buf_multicast;
int_split_priority = buf_priority;
int_split_localid = buf_localid;
int_split_cs_addr = incrmntd_cs_addr;
int_split_bank_addr = incrmntd_bank_addr;
int_split_row_addr = incrmntd_row_addr;
if (cfg_burst_length == 2)
begin
int_split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:1], 1'b0};
end
else if (cfg_burst_length == 4)
begin
int_split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:2], 2'b00};
end
else if (cfg_burst_length == 8)
begin
int_split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:3], 3'b000};
end
else // if (cfg_burst_length == 16)
begin
int_split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:4], 4'b0000};
end
end
end
// Split command information
generate
if (CFG_CMD_GEN_SPLIT_REGISTERED)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
split_cs_addr <= 0;
split_bank_addr <= 0;
split_row_addr <= 0;
split_col_addr <= 0;
split_read <= 0;
split_write <= 0;
split_size <= 0;
split_autopch <= 0;
split_multicast <= 0;
split_priority <= 0;
split_localid <= 0;
end
else
begin
if (!queue_full)
begin
split_cs_addr <= int_split_cs_addr;
split_bank_addr <= int_split_bank_addr;
split_row_addr <= int_split_row_addr;
split_col_addr <= int_split_col_addr;
split_read <= int_split_read;
split_write <= int_split_write;
split_size <= int_split_size;
split_autopch <= int_split_autopch;
split_multicast <= int_split_multicast;
split_priority <= int_split_priority;
split_localid <= int_split_localid;
end
end
end
end
else
begin
always @ (*)
begin
split_cs_addr = int_split_cs_addr;
split_bank_addr = int_split_bank_addr;
split_row_addr = int_split_row_addr;
split_col_addr = int_split_col_addr;
split_read = int_split_read;
split_write = int_split_write;
split_size = int_split_size;
split_autopch = int_split_autopch;
split_multicast = int_split_multicast;
split_priority = int_split_priority;
split_localid = int_split_localid;
end
end
endgenerate
//======================================================================================
//
// [END] Burst splitting
//
//======================================================================================
//======================================================================================
//
// [START] Command buffer
//
//======================================================================================
// Keep track of command size during a split process
// will keep decreasing when a split command was sent to TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_size <= 0;
decrmntd_size <= 0;
end
else
begin
if (copy)
begin
buf_size <= cmd_size_plus_unaligned_size;
if ((cmd_size_plus_unaligned_size) > native_size_x2)
begin
decrmntd_size <= native_size;
end
else
begin
decrmntd_size <= cmd_size_plus_unaligned_size - native_size;
end
end
else if (!registered && (buf_size > native_size) && ~mux_busy)
begin
buf_size <= buf_size - native_size;
if ((buf_size - native_size) > native_size_x2)
begin
decrmntd_size <= native_size;
end
else
begin
decrmntd_size <= buf_size - native_size_x2;
end
end
end
end
// Address max logic, assert '1' if address reaches boundary
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_chip_addr_reach_max <= 1'b0;
buf_bank_addr_reach_max <= 1'b0;
buf_col_addr_reach_max <= 1'b0;
int_buf_row_addr_reach_max <= 0;
end
else
begin
if (copy)
begin
buf_chip_addr_reach_max <= (int_cs_addr_postq == max_chip_from_csr) ? 1'b1 : 1'b0;
buf_bank_addr_reach_max <= (int_bank_addr_postq == max_bank_from_csr) ? 1'b1 : 1'b0;
int_buf_row_addr_reach_max [3] <= (int_row_addr_postq [ CFG_MEM_IF_ROW_WIDTH - 1 : 3 * (CFG_MEM_IF_ROW_WIDTH / 4)] == max_row_from_csr [ CFG_MEM_IF_ROW_WIDTH - 1 : 3 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
int_buf_row_addr_reach_max [2] <= (int_row_addr_postq [3 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 2 * (CFG_MEM_IF_ROW_WIDTH / 4)] == max_row_from_csr [3 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 2 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
int_buf_row_addr_reach_max [1] <= (int_row_addr_postq [2 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 1 * (CFG_MEM_IF_ROW_WIDTH / 4)] == max_row_from_csr [2 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 1 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
int_buf_row_addr_reach_max [0] <= (int_row_addr_postq [1 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 0 * (CFG_MEM_IF_ROW_WIDTH / 4)] == max_row_from_csr [1 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 0 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
if ((cfg_burst_length == 16 && int_col_addr_postq[CFG_MEM_IF_COL_WIDTH-1:4] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:4])
||
(cfg_burst_length == 8 && int_col_addr_postq[CFG_MEM_IF_COL_WIDTH-1:3] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:3])
||
(cfg_burst_length == 4 && int_col_addr_postq[CFG_MEM_IF_COL_WIDTH-1:2] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:2])
||
(cfg_burst_length == 2 && int_col_addr_postq[CFG_MEM_IF_COL_WIDTH-1:1] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:1])
)
begin
buf_col_addr_reach_max <= 1'b1;
end
else
begin
buf_col_addr_reach_max <= 1'b0;
end
end
else if (generating && ~mux_busy)
begin
buf_chip_addr_reach_max <= (buf_cs_addr == max_chip_from_csr) ? 1'b1 : 1'b0;
buf_bank_addr_reach_max <= (buf_bank_addr == max_bank_from_csr) ? 1'b1 : 1'b0;
int_buf_row_addr_reach_max [3] <= (buf_row_addr [ CFG_MEM_IF_ROW_WIDTH - 1 : 3 * (CFG_MEM_IF_ROW_WIDTH / 4)] == max_row_from_csr [ CFG_MEM_IF_ROW_WIDTH - 1 : 3 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
int_buf_row_addr_reach_max [2] <= (buf_row_addr [3 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 2 * (CFG_MEM_IF_ROW_WIDTH / 4)] == max_row_from_csr [3 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 2 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
int_buf_row_addr_reach_max [1] <= (buf_row_addr [2 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 1 * (CFG_MEM_IF_ROW_WIDTH / 4)] == max_row_from_csr [2 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 1 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
int_buf_row_addr_reach_max [0] <= (buf_row_addr [1 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 0 * (CFG_MEM_IF_ROW_WIDTH / 4)] == max_row_from_csr [1 * (CFG_MEM_IF_ROW_WIDTH / 4) - 1 : 0 * (CFG_MEM_IF_ROW_WIDTH / 4)]) ? 1'b1 : 1'b0;
if ((cfg_burst_length == 16 && (buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] + 1'b1) == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:4])
||
(cfg_burst_length == 8 && (buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] + 1'b1) == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:3])
||
(cfg_burst_length == 4 && (buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] + 1'b1) == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:2])
||
(cfg_burst_length == 2 && (buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] + 1'b1) == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:1])
)
begin
buf_col_addr_reach_max <= 1'b1;
end
else
begin
buf_col_addr_reach_max <= 1'b0;
end
end
end
end
always @ (*)
begin
buf_row_addr_reach_max = &int_buf_row_addr_reach_max;
end
// Buffered command info, to be used in split process
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_read_req <= 1'b0;
buf_write_req <= 1'b0;
buf_autopch_req <= 1'b0;
buf_multicast <= 1'b0;
buf_priority <= 1'b0;
buf_localid <= 0;
end
else
begin
if (copy)
begin
buf_read_req <= cmd_read_postq;
buf_write_req <= cmd_write_postq;
buf_autopch_req <= cmd_autoprecharge_postq;
buf_multicast <= cmd_multicast_postq;
buf_priority <= cmd_priority_postq;
buf_localid <= cmd_id_postq;
end
end
end
// Keep track of command address during a split process
// will keep increasing when a split command was sent to TBP
// also takes into account address order
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_cs_addr <= 0;
buf_bank_addr <= 0;
buf_row_addr <= 0;
buf_col_addr <= 0;
end
else
if (copy)
begin
buf_cs_addr <= int_cs_addr_postq;
buf_bank_addr <= int_bank_addr_postq;
buf_row_addr <= int_row_addr_postq;
buf_col_addr <= int_col_addr_postq;
end
else if (generating && ~mux_busy)
begin
buf_cs_addr <= incrmntd_cs_addr;
buf_bank_addr <= incrmntd_bank_addr;
buf_row_addr <= incrmntd_row_addr;
buf_col_addr <= incrmntd_col_addr;
end
end
always @ (*)
begin
if (buf_col_addr_reach_max)
begin
incrmntd_cs_addr = buf_cs_addr;
incrmntd_bank_addr = buf_bank_addr;
incrmntd_row_addr = buf_row_addr;
incrmntd_col_addr = buf_col_addr;
if (cfg_burst_length == 16)
begin
incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] = 0;
end
else if (cfg_burst_length == 8)
begin
incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] = 0;
end
else if (cfg_burst_length == 4)
begin
incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] = 0;
end
else // if (cfg_burst_length == 2)
begin
incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] = 0;
end
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL) // 2 is rowchipbankcol
begin
if (buf_bank_addr_reach_max)
begin
incrmntd_bank_addr = 0;
if (buf_chip_addr_reach_max)
begin
incrmntd_cs_addr = 0;
if (buf_row_addr_reach_max)
begin
incrmntd_row_addr = 0;
end
else
begin
incrmntd_row_addr = buf_row_addr + 1'b1;
end
end
else
begin
incrmntd_cs_addr = buf_cs_addr + 1'b1;
end
end
else
begin
incrmntd_bank_addr = buf_bank_addr + 1'b1;
end
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL) // 1 is chipbankrowcol
begin
if (buf_row_addr_reach_max)
begin
incrmntd_row_addr = 0;
if (buf_bank_addr_reach_max)
begin
incrmntd_bank_addr = 0;
if (buf_chip_addr_reach_max)
begin
incrmntd_cs_addr = 0;
end
else
begin
incrmntd_cs_addr = buf_cs_addr + 1'b1;
end
end
else
begin
incrmntd_bank_addr = buf_bank_addr + 1'b1;
end
end
else
begin
incrmntd_row_addr = buf_row_addr + 1'b1;
end
end
else // 0 is chiprowbankcol
begin
if (buf_bank_addr_reach_max)
begin
incrmntd_bank_addr = 0;
if (buf_row_addr_reach_max)
begin
incrmntd_row_addr = 0;
if (buf_chip_addr_reach_max)
begin
incrmntd_cs_addr = 0;
end
else
begin
incrmntd_cs_addr = buf_cs_addr + 1'b1;
end
end
else
begin
incrmntd_row_addr = buf_row_addr + 1'b1;
end
end
else
begin
incrmntd_bank_addr = buf_bank_addr + 1'b1;
end
end
end
else
begin
incrmntd_cs_addr = buf_cs_addr;
incrmntd_bank_addr = buf_bank_addr;
incrmntd_row_addr = buf_row_addr;
incrmntd_col_addr = buf_col_addr + cfg_burst_length;
end
end
//======================================================================================
//
// [END] Command buffer
//
//======================================================================================
//======================================================================================
//
// [START] Data ID related logic
//
//======================================================================================
// proc signals to datapath
assign proc_busy = (cfg_enable_rmw) ? ecc_proc_busy : tbp_full;
assign proc_load = (cfg_enable_rmw) ? ecc_proc_load : cmd_gen_load;
assign proc_load_dataid = (cfg_enable_rmw) ? ecc_proc_load_dataid : cmd_gen_load;
assign proc_write = (cfg_enable_rmw) ? ecc_proc_write : cmd_gen_write;
assign proc_read = (cfg_enable_rmw) ? ecc_proc_read : cmd_gen_read;
assign proc_size = (cfg_enable_rmw) ? ecc_proc_size : cmd_gen_size;
assign proc_localid = (cfg_enable_rmw) ? ecc_proc_localid : cmd_gen_localid;
assign tbp_load_index = (cfg_enable_rmw) ? 1 : tbp_load; // set to '1' in RMW mode, because we need data_complete[0] to toggle indicating wdata is complete
always @ (*)
begin
ecc_proc_busy = !ecc_proc_busy_parwr_read_queue_load && !split_queue_load_for_avl;
ecc_proc_busy_parwr_read_queue_load = !queue_full && ((ecc_state_sm == 4'h4) || (ecc_state_sm == 4'h1));
ecc_proc_load = (ecc_proc_write | ecc_proc_read);
ecc_proc_load_dataid = !ecc_rmw_read; // De-assert when we're loading an RMW read
end
// Seperate into 2 process because ecc_proc read/write needs to be assigned seperately, due to blocking assignments
always @ (*)
begin
ecc_proc_write = int_split_write;
ecc_proc_read = int_split_read | ecc_rmw_read; // Assert when we're loading an RMW read
ecc_proc_size = int_split_size;
ecc_proc_localid = int_split_localid;
end
//======================================================================================
//
// [END] Data ID related logic
//
//======================================================================================
//======================================================================================
//
// [START] ECC related logic
//
//======================================================================================
//State Machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_state_sm <= IDLE;
ecc_read <= 1'b0;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
case (ecc_state_sm)
IDLE :
begin
if (cfg_enable_ecc && errcmd_valid)
begin
ecc_state_sm <= CORRECT_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b1;
errcmd_ready <= 1'b1;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final)
begin
ecc_state_sm <= FULL_WR; //4'h3
ecc_read <= 1'b0;
ecc_write <= 1'b1;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final)
begin
ecc_state_sm <= PARWR_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b1;
end
else if (cfg_enable_rmw && int_ecc_read_final)
begin
ecc_state_sm <= FULL_RD; //4'h6
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_state_sm <= IDLE;
ecc_read <= 1'b0;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
end
CORRECT_RD :
begin
errcmd_ready <= 1'b0;
if (!queue_full)
begin
ecc_state_sm <= CORRECT_WR;
ecc_read <= 1'b0;
ecc_write <= 1'b1;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b1;
correct <= 1'b1;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
end
CORRECT_WR :
begin
if (!queue_full)
begin
if (cfg_enable_ecc && errcmd_valid)
begin
ecc_state_sm <= CORRECT_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b1;
errcmd_ready <= 1'b1;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final)
begin
ecc_state_sm <= FULL_WR;
ecc_read <= 1'b0;
ecc_write <= 1'b1;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final)
begin
ecc_state_sm <= PARWR_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b1;
end
else if (cfg_enable_rmw && int_ecc_read_final)
begin
ecc_state_sm <= FULL_RD; //4'h6
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_state_sm <= IDLE;
ecc_read <= 1'b0;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
end
end
PARWR_RD :
begin
if (!queue_full)
begin
ecc_state_sm <= PARWR_WR; //4'h2
ecc_read <= 1'b0;
ecc_write <= 1'b1;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b1;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b1;
end
end
PARWR_WR : //4'h2
begin
if (!queue_full)
begin
if (cfg_enable_ecc && errcmd_valid)
begin
ecc_state_sm <= CORRECT_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b1;
errcmd_ready <= 1'b1;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final)
begin
ecc_state_sm <= FULL_WR;
ecc_read <= 1'b0;
ecc_write <= 1'b1;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final)
begin
ecc_state_sm <= PARWR_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b1;
end
else if (cfg_enable_rmw && int_ecc_read_final)
begin
ecc_state_sm <= FULL_RD; //4'h6
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_state_sm <= IDLE;
ecc_read <= 1'b0;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
end
end
FULL_WR : //4'h3
begin
if (!queue_full)
begin
if (cfg_enable_ecc && errcmd_valid)
begin
ecc_state_sm <= CORRECT_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b1;
errcmd_ready <= 1'b1;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final)
begin
ecc_state_sm <= PARWR_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b1;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final)
begin
ecc_state_sm <= FULL_WR;
ecc_read <= 1'b0;
ecc_write <= 1'b1;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_read_final)
begin
ecc_state_sm <= FULL_RD; //4'h6
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_state_sm <= IDLE;
ecc_read <= 1'b0;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
end
end
FULL_RD : //4'h6
begin
if (!queue_full)
begin
if (cfg_enable_ecc && errcmd_valid)
begin
ecc_state_sm <= CORRECT_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b1;
errcmd_ready <= 1'b1;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && !int_ecc_partial_be_final)
begin
ecc_state_sm <= FULL_WR;
ecc_read <= 1'b0;
ecc_write <= 1'b1;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else if (cfg_enable_rmw && int_ecc_write_final && int_ecc_data_complete_final && int_ecc_partial_be_final)
begin
ecc_state_sm <= PARWR_RD;
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b1;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b1;
end
else if (cfg_enable_rmw && int_ecc_read_final)
begin
ecc_state_sm <= FULL_RD; //4'h6
ecc_read <= 1'b1;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_state_sm <= IDLE;
ecc_read <= 1'b0;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
end
end
default :
begin
ecc_state_sm <= IDLE;
ecc_read <= 1'b0;
ecc_write <= 1'b0;
ecc_rmw_read <= 1'b0;
ecc_rmw_write <= 1'b0;
correct <= 1'b0;
errcmd_ready <= 1'b0;
partial_opr <= 1'b0;
end
endcase
end
end
// for ECC usage only
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
split_queue_load_open <= 1'b0;
end
else
begin
if (split_queue_load_for_avl)
begin
split_queue_load_open <= int_split_write; //set flag to indicate waiting for data_complete
end
else if (data_complete[0])
begin
split_queue_load_open <= 1'b0; //clear flag to indicate data_complete has arrived
end
end
end
// Delay cmd_gen command by one cycle
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_cs_addr <= 0;
int_ecc_bank_addr <= 0;
int_ecc_row_addr <= 0;
int_ecc_col_addr <= 0;
int_ecc_read <= 0;
int_ecc_write <= 0;
int_ecc_size <= 0;
int_ecc_autopch <= 0;
int_ecc_multicast <= 0;
int_ecc_priority <= 0;
int_ecc_localid <= 0;
int_ecc_dataid <= 0;
end
else if (split_queue_load) // hold off the next command when ECC logic is busy
begin
int_ecc_cs_addr <= int_split_cs_addr;
int_ecc_bank_addr <= int_split_bank_addr;
int_ecc_row_addr <= int_split_row_addr;
int_ecc_col_addr <= int_split_col_addr;
int_ecc_read <= int_split_read_final; //When data_id not ready, suppress load
int_ecc_write <= int_split_write_final; //When data_id not ready, suppress load
int_ecc_size <= int_split_size;
int_ecc_autopch <= int_split_autopch;
int_ecc_multicast <= int_split_multicast;
int_ecc_priority <= int_split_priority;
int_ecc_localid <= int_split_localid;
if (int_split_write)
begin
int_ecc_dataid <= wdatap_free_id_dataid;
end
else
begin
int_ecc_dataid <= rdatap_free_id_dataid;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_ecc_data_complete <= 0;
int_ecc_partial_be <= 0;
end
else
begin
if (data_complete[0])
begin
int_ecc_data_complete <= data_complete[0];
int_ecc_partial_be <= data_partial_be;
end
else if (split_queue_load_for_avl)
begin
int_ecc_data_complete <= 0;
int_ecc_partial_be <= 0;
end
end
end
// Buffer for ECC command information
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_cs_addr <= 0;
ecc_bank_addr <= 0;
ecc_row_addr <= 0;
ecc_col_addr <= 0;
ecc_size <= 0;
ecc_autopch <= 0;
ecc_multicast <= 0;
ecc_dataid <= 0;
ecc_localid <= 0;
ecc_priority <= 0;
end
else
begin
if (ecc_queue_load) //when queue take, load in new command
//except when doing correction
begin
ecc_cs_addr <= take_from_ecc_correct ? errcmd_chipsel : int_ecc_cs_addr;
ecc_bank_addr <= take_from_ecc_correct ? errcmd_bank : int_ecc_bank_addr;
ecc_row_addr <= take_from_ecc_correct ? errcmd_row : int_ecc_row_addr;
ecc_col_addr <= take_from_ecc_correct ? errcmd_column : int_ecc_col_addr;
ecc_size <= take_from_ecc_correct ? errcmd_size : int_ecc_size;
ecc_autopch <= take_from_ecc_correct ? 1'b0 : int_ecc_autopch;
ecc_multicast <= take_from_ecc_correct ? 1'b0 : int_ecc_multicast;
ecc_localid <= take_from_ecc_correct ? 0 : int_ecc_localid;
ecc_priority <= take_from_ecc_correct ? errcmd_localid : int_ecc_priority;
ecc_dataid <= take_from_ecc_correct ? 1'b0 : int_ecc_dataid;
end
else //on hold
begin
ecc_cs_addr <= ecc_cs_addr;
ecc_bank_addr <= ecc_bank_addr;
ecc_row_addr <= ecc_row_addr;
ecc_col_addr <= ecc_col_addr;
ecc_size <= ecc_size;
ecc_autopch <= ecc_autopch;
ecc_multicast <= ecc_multicast;
ecc_localid <= ecc_localid;
ecc_priority <= ecc_priority;
ecc_dataid <= ecc_dataid;
end
end
end
assign ecc_queue_load = (((ecc_state_sm == 4'b0000) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid)) ||
((ecc_state_sm == 4'b0011) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid) && !queue_full) ||
((ecc_state_sm == 4'b0110) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid) && !queue_full) ||
((ecc_state_sm == 4'b1000) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid) && !queue_full) ||
((ecc_state_sm == 4'b0010) && (int_ecc_read_final || int_ecc_write_final || errcmd_valid) && !queue_full));
assign split_queue_load = (split_queue_load_init || split_queue_load_ecc_load);
assign split_queue_load_init = (!int_ecc_read && !int_ecc_write && (int_split_read_final || int_split_write_final) && (ecc_state_sm != 4'h4) && (ecc_state_sm != 4'h1));
assign split_queue_load_ecc_load = (ecc_queue_load && (!take_from_ecc_correct));
assign split_queue_load_for_avl = split_queue_load && (int_split_read_final || int_split_write_final);
assign int_split_read_final = (int_split_read && rdatap_free_id_valid);
assign int_split_write_final = (int_split_write && wdatap_free_id_valid);
assign split_queue_fast_unload = data_complete[0] && split_queue_load_ecc_load;
assign int_ecc_data_complete_final = split_queue_fast_unload ? data_complete[0] : int_ecc_data_complete;
assign int_ecc_partial_be_final = split_queue_fast_unload ? data_partial_be : int_ecc_partial_be;
assign split_queue_load_open_final = split_queue_load_open && !data_complete[0];
assign int_ecc_read_final = int_ecc_read && !split_queue_load_open_final;
assign int_ecc_write_final = int_ecc_write && !split_queue_load_open_final;
assign take_from_ecc_correct = cfg_enable_ecc && errcmd_valid &&
((ecc_state_sm == 4'h0) ||
((ecc_state_sm == 4'h8) && !queue_full) ||
((ecc_state_sm == 4'h2) && !queue_full) ||
((ecc_state_sm == 4'h3) && !queue_full) ||
((ecc_state_sm == 4'h6) && !queue_full));
// ECC partial and correct information
always @ (*)
begin
ecc_correct = correct;
ecc_partial = partial_opr;
end
// Waiting to load signal, indicate to TBP that we're about to load TBP but cmd_gen_load signal is not high
// this signal is required so that TBP will flush old contents in no-DM or ECC mode, else it'll cause in-efficiency
// in no-DM or ECC mode, we need to wait for write data to arrive before asserting read (partial write) or write (full write) request to TBP
// therefore TBP won't flush existing content in TBP because it didn't know command generator is about to load new command
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
waiting_to_load <= 1'b0;
end
else
begin
if (tbp_full) // need to load when TBP is full, case:93272, avl_ready will stuck low if we keep all tbp slots with open page, this will free up at least one slot
begin
waiting_to_load <= 1'b1;
end
else
begin
waiting_to_load <= 1'b0;
end
end
end
//======================================================================================
//
// [END] ECC related logic
//
//======================================================================================
//======================================================================================
//
// [START] Mux Logic
//
//======================================================================================
assign mux_busy = cfg_enable_rmw ? mux_busy_ecc : mux_busy_non_ecc;
assign mux_busy_non_ecc = queue_full;
assign mux_busy_ecc = (!split_queue_load_for_avl);
assign muxed_cs_addr = (cfg_enable_rmw) ? ecc_cs_addr : split_cs_addr;
assign muxed_bank_addr = (cfg_enable_rmw) ? ecc_bank_addr : split_bank_addr;
assign muxed_row_addr = (cfg_enable_rmw) ? ecc_row_addr : split_row_addr;
assign muxed_col_addr = (cfg_enable_rmw) ? ecc_col_addr : split_col_addr;
assign muxed_read = (cfg_enable_rmw) ? ecc_read : split_read;
assign muxed_write = (cfg_enable_rmw) ? ecc_write : split_write;
assign muxed_size = (cfg_enable_rmw) ? ecc_size : split_size;
assign muxed_autopch = (cfg_enable_rmw) ? ecc_autopch : split_autopch;
assign muxed_multicast = (cfg_enable_rmw) ? ecc_multicast : split_multicast;
assign muxed_localid = (cfg_enable_rmw) ? ecc_localid : split_localid;
assign muxed_priority = (cfg_enable_rmw) ? ecc_priority : split_priority;
assign muxed_dataid = (cfg_enable_rmw) ? ecc_dataid : (muxed_read ? rdatap_free_id_dataid : wdatap_free_id_dataid);
assign muxed_complete = (cfg_enable_rmw) ? !ecc_rmw_write : split_read; // Data is always complete for read command, therefore set it to split_read
assign muxed_correct = (cfg_enable_rmw) ? ecc_correct : 1'b0;
assign muxed_partial = (cfg_enable_rmw) ? ecc_partial : 1'b0;
//======================================================================================
//
// [END] Mux Logic
//
//======================================================================================
//======================================================================================
//
// [START] Queue Logic
//
//======================================================================================
// mapping of buffer_input
assign buffer_input = {muxed_read,muxed_write,muxed_multicast,muxed_autopch,muxed_priority,muxed_complete,muxed_correct,muxed_partial,muxed_dataid,muxed_localid,muxed_size,muxed_cs_addr,muxed_row_addr,muxed_bank_addr,muxed_col_addr};
// avalon_write_req & avalon_read_req is AND with internal_ready in alt_ddrx_avalon_if.v
assign write_to_queue = (muxed_read | muxed_write) & ~queue_full;
assign fetch = cmd_gen_load & ~tbp_full;
//pipefull and pipe register chain
//feed 0 to pipefull entry that is empty
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
pipefull[j] <= 1'b0;
pipe [j] <= 0;
end
end
else
begin
if (fetch) // fetch and write
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= pipefull[CFG_CTL_QUEUE_DEPTH-1] & write_to_queue;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe [CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
else if (write_to_queue) // write only
begin
for(j=1; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
if(pipefull[j-1] == 1'b1 & pipefull[j] == 1'b0)
begin
pipefull[j] <= 1'b1;
pipe [j] <= buffer_input;
end
end
if(pipefull[0] == 1'b0)
begin
pipefull[0] <= 1'b1;
pipe [0] <= buffer_input;
end
end
end
end
//======================================================================================
//
// [END] Queue Logic
//
//======================================================================================
//======================================================================================
//
// [START] Output Logic
//
//======================================================================================
generate
begin
wire int_queue_full;
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
reg int_register_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cmd_gen_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_cmd_gen_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_cmd_gen_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_cmd_gen_col;
reg int_cmd_gen_write;
reg int_cmd_gen_read;
reg int_cmd_gen_multicast;
reg [CFG_INT_SIZE_WIDTH-1:0] int_cmd_gen_size;
reg [CFG_LOCAL_ID_WIDTH-1:0] int_cmd_gen_localid;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid;
reg int_cmd_gen_priority;
reg int_cmd_gen_rmw_correct;
reg int_cmd_gen_rmw_partial;
reg int_cmd_gen_autopch;
reg int_cmd_gen_complete;
// TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (int_cmd_gen_chipsel == chipsel[j])
begin
int_same_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (int_cmd_gen_bank == bank[j])
begin
int_same_bank_addr[j] = 1'b1;
end
else
begin
int_same_bank_addr[j] = 1'b0;
end
// Row addr
if (int_cmd_gen_row[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
int_same_row_addr_0[j] = 1'b1;
end
else
begin
int_same_row_addr_0[j] = 1'b0;
end
if (int_cmd_gen_row[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
int_same_row_addr_1[j] = 1'b1;
end
else
begin
int_same_row_addr_1[j] = 1'b0;
end
if (int_cmd_gen_row[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
int_same_row_addr_2[j] = 1'b1;
end
else
begin
int_same_row_addr_2[j] = 1'b0;
end
if (int_cmd_gen_row[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
int_same_row_addr_3[j] = 1'b1;
end
else
begin
int_same_row_addr_3[j] = 1'b0;
end
// Col addr
if (int_cmd_gen_col == col[j])
begin
int_same_col_addr[j] = 1'b1;
end
else
begin
int_same_col_addr[j] = 1'b0;
end
// Read command
if (int_cmd_gen_read == read[j])
begin
int_same_read_cmd[j] = 1'b1;
end
else
begin
int_same_read_cmd[j] = 1'b0;
end
// Write command
if (int_cmd_gen_write == write[j])
begin
int_same_write_cmd[j] = 1'b1;
end
else
begin
int_same_write_cmd[j] = 1'b0;
end
end
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (int_queue_full)
begin
// Chipselect address
if (int_cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (int_cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (int_cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
else
begin
// Chipselect address
if (muxed_cs_addr == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (muxed_bank_addr == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (muxed_row_addr == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
end
assign int_queue_full = tbp_full | ((cmd_gen_read & ~rdatap_free_id_valid) | (cmd_gen_write & ~wdatap_free_id_valid));
always @ (*)
begin
int_register_valid = one;
int_cmd_gen_read = muxed_read;
int_cmd_gen_write = muxed_write;
int_cmd_gen_multicast = muxed_multicast;
int_cmd_gen_autopch = muxed_autopch;
int_cmd_gen_priority = muxed_priority;
int_cmd_gen_complete = muxed_complete;
int_cmd_gen_rmw_correct = muxed_correct;
int_cmd_gen_rmw_partial = muxed_partial;
int_cmd_gen_dataid = muxed_dataid;
int_cmd_gen_localid = muxed_localid;
int_cmd_gen_size = muxed_size;
int_cmd_gen_chipsel = muxed_cs_addr;
int_cmd_gen_row = muxed_row_addr;
int_cmd_gen_bank = muxed_bank_addr;
int_cmd_gen_col = muxed_col_addr;
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1 & int_same_row_addr_2 & int_same_row_addr_3;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
assign queue_full = int_queue_full;
assign cmd_gen_load = (cmd_gen_read & rdatap_free_id_valid) | (cmd_gen_write & wdatap_free_id_valid);
assign cmd_gen_waiting_to_load = waiting_to_load;
assign cmd_gen_read = int_cmd_gen_read;
assign cmd_gen_write = int_cmd_gen_write;
assign cmd_gen_multicast = int_cmd_gen_multicast;
assign cmd_gen_autopch = int_cmd_gen_autopch;
assign cmd_gen_priority = int_cmd_gen_priority;
assign cmd_gen_complete = int_cmd_gen_complete;
assign cmd_gen_rmw_correct = int_cmd_gen_rmw_correct;
assign cmd_gen_rmw_partial = int_cmd_gen_rmw_partial;
assign cmd_gen_dataid = int_cmd_gen_dataid;
assign cmd_gen_localid = int_cmd_gen_localid;
assign cmd_gen_size = int_cmd_gen_size;
assign cmd_gen_chipsel = int_cmd_gen_chipsel;
assign cmd_gen_row = int_cmd_gen_row;
assign cmd_gen_bank = int_cmd_gen_bank;
assign cmd_gen_col = int_cmd_gen_col;
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
endgenerate
//======================================================================================
//
// [END] Output Logic
//
//======================================================================================
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
|
// 21 Jul 2021
//
// Multiply-add often takes more than one cycle of time.
// This module provides a mechanism for indicating the degree
// of pipelining required. The implementation still relies upon
// retiming support from the cad tools. The basejump_stl
// /hard mechanisms allows for platform-specific implementations
// to be swapped in.
`include "bsg_defines.v"
module bsg_mul_add_unsigned #(
parameter `BSG_INV_PARAM(width_a_p)
,parameter `BSG_INV_PARAM(width_b_p)
,parameter width_c_p = width_a_p + width_b_p
,parameter width_o_p = `BSG_SAFE_CLOG2( ((1 << width_a_p) - 1) * ((1 << width_b_p) - 1) +
((1 << width_c_p)-1) + 1 )
,parameter pipeline_p = 0
) (
input clk_i
,input [width_a_p-1 : 0] a_i
,input [width_b_p-1 : 0] b_i
,input [width_c_p-1 : 0] c_i
,output [width_o_p-1 : 0] o
);
localparam pre_pipeline_lp = 0;
localparam post_pipeline_lp = pipeline_p;
wire [width_a_p-1:0] a_r;
wire [width_b_p-1:0] b_r;
wire [width_c_p-1:0] c_r;
bsg_dff_chain #(width_a_p + width_b_p + width_c_p, pre_pipeline_lp)
pre_mul_add (
.clk_i(clk_i)
,.data_i({a_i, b_i, c_i})
,.data_o({a_r, b_r, c_r})
);
wire [width_o_p-1:0] o_r = a_r * b_r + c_r;
bsg_dff_chain #(width_o_p, post_pipeline_lp)
post_mul_add (
.clk_i(clk_i)
,.data_i(o_r)
,.data_o(o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_mul_add_unsigned)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_BLACKBOX_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_BLACKBOX_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputisolatch (
Q ,
D ,
SLEEP_B
);
output Q ;
input D ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Loop_loop_height_kbM_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_kbM_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_kbM(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
Loop_loop_height_kbM_rom Loop_loop_height_kbM_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_4_V
`define SKY130_FD_SC_LP__INV_4_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_4_V
|
module eb15_ctrl #(
parameter S0 = 5'b1_0_10_0,
parameter S1 = 5'b1_1_01_0,
parameter S2 = 5'b0_1_00_0,
parameter S3 = 5'b1_1_10_1,
parameter S4 = 5'b0_1_00_1
) (
input t_0_req,
output t_0_ack,
output i_0_req,
input i_0_ack,
output en0, en1, sel,
input clk, reset_n
);
// State machine
reg [4:0] state, state_nxt;
always @(posedge clk or negedge reset_n)
if (~reset_n) state <= S0;
else state <= state_nxt;
// state d0 d1 t.ack i.req en0 en1 sel
// 0 x x 1 0 t.req 0 0 1_0_10_0
// 1 0 x 1 1 0 t.req 0 1_1_01_0
// 2 0 1 0 1 0 0 0 0_1_00_0
// 3 x 0 1 1 t.req 0 1 1_1_10_1
// 4 1 0 0 1 0 0 1 0_1_00_1
always @*
casez({state, t_0_req, i_0_ack})
{S0, 2'b1?} : state_nxt = S1;
{S1, 2'b01} : state_nxt = S0;
{S1, 2'b10} : state_nxt = S2;
{S1, 2'b11} : state_nxt = S3;
{S2, 2'b?1} : state_nxt = S3;
{S3, 2'b01} : state_nxt = S0;
{S3, 2'b10} : state_nxt = S4;
{S3, 2'b11} : state_nxt = S1;
{S4, 2'b?1} : state_nxt = S1;
default state_nxt = state;
endcase
assign t_0_ack = state[4];
assign i_0_req = state[3];
assign en0 = state[2] & t_0_req;
assign en1 = state[1] & t_0_req;
assign sel = state[0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_2_V
`define SKY130_FD_SC_HS__EINVP_2_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvp_2 (
A ,
TE ,
Z ,
VPWR,
VGND
);
input A ;
input TE ;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__einvp base (
.A(A),
.TE(TE),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvp_2 (
A ,
TE,
Z
);
input A ;
input TE;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__einvp base (
.A(A),
.TE(TE),
.Z(Z)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_2_V
|
//****************************************************************************/
// Copyright (C) yyyy Ronan Barzic - [email protected]
// Date : Fri Apr 22 09:40:43 2016
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA.
//
//
// Filename : two_phase_event_gen.v
//
// Description : A random 2-phase event generator
//
//
//
//****************************************************************************/
`timescale 1ns/1ps
module two_phase_event_gen (/*AUTOARG*/
// Outputs
req,
// Inputs
run, ack
);
input run;
output req;
input ack;
parameter spread=200;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
reg req;
task handshake_2ph_rise;
begin
wait(ack === 1'b0);
req <= 1'b1;
wait(ack === 1'b1);
end
endtask
task handshake_2ph_fall;
begin
wait(ack === 1'b1);
req = 1'b0;
wait(ack === 1'b0);
end
endtask
initial begin
req <= 0;
#1;
while(1) begin
wait(run===1'b1);
#($unsigned($random) % spread);
handshake_2ph_rise();
#($unsigned($random) % spread);
handshake_2ph_fall();
end
end
endmodule // two_phase_event_gen
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_MS__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PS_TB_V
|
module phyInital (
input clk,reset,
input iniStart,
input [3:0]ram_read_addr,
input [31:0] command,
input [15:0]command_and,
inout md_inout,
output mdc,
output reg [3: 0] comm_addr,
output reg iniEnd,
output reg [12:0]stateout,
output [15:0]readDataoutRam,
output busy,
output WCtrlDataStartout
);
wire Busy;
wire WCtrlDataStart, RStatStart, UpdateMIIRX_DATAReg, Nvalid;
wire [15:0] writeData;
wire [15:0] readData;
wire [15:0] writeData_and;
assign busy = Busy;
assign WCtrlDataStartout = WCtrlDataStart;
//assign readDataout = readData;
reg save ;
reg [3:0]mi_addr;
always @ (posedge clk)
begin
if (reset) begin
mi_addr<= 4'b0;
end
else begin
if (save) begin
if (mi_addr < 4'b1110)
mi_addr <= mi_addr + 1'b1;
end
end
end
mi_data_ram mi_data_ram_ins(
.data_a(readData),
//.data_b,
.addr_a(mi_addr),
.addr_b(ram_read_addr),
.we_a(save),
.we_b(1'b0),
.clk(clk),
//.q_a,
.q_b(readDataoutRam)
);
wire [4:0] pyhAddr;
wire [4:0] regAddr;
wire writeOp;
assign writeOp = command[31];
assign pyhAddr = command[30:26];
assign regAddr = command[25:21];
assign writeData = command[15:0];
assign writeData_and = command_and;
wire [15: 0] ctrlData;
assign ctrlData = (readData | writeData) & writeData_and;
reg WCtrlData,RStat;
wire md_we, md_out,md_in;
assign md_inout = md_we? md_out:1'bz;
assign md_in = md_inout;
reg comm_addr_rst, comm_addr_en;
eth_miim eth_miim_ins (
.Clk(clk),
.Reset(reset),
.Divider(8'd50),
.NoPre(1'b0),
.CtrlData(ctrlData),
.Rgad(regAddr),
.Fiad(pyhAddr),
.WCtrlData(WCtrlData),
.RStat(RStat),
.ScanStat(1'b0),
.Mdi(md_in),
.Mdo(md_out),
.MdoEn(md_we),
.Mdc(mdc),
.Busy(Busy),
.Prsd(readData),
//.LinkFail(LEDG[1]),
.Nvalid(Nvalid),
.WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart),
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
always @ (posedge clk)
begin
if (comm_addr_rst) begin
comm_addr <= 4'b0;
end
else begin
if (comm_addr_en ) comm_addr <= comm_addr + 4'b1;
end
end
reg [3:0]state, next_state;
// Declare states
parameter s_rst = 0, s_ini = 1, s_read1 = 2, s_read2 = 3, s_wait= 4, s_write1 = 5 , s_write2 = 6, s_delay1=7, s_delay2=8, s_delay3=9 ;
// Determine the next state synchronously, based on the
// current state and the input
always @ (posedge clk ) begin
if (reset)
state <= s_rst;
else
state <= next_state;
end
// Determine the output based only on the current state
// and the input (do not wait for a clock edge).
always @ (state or iniStart or UpdateMIIRX_DATAReg or command or Busy or RStatStart or WCtrlDataStart)
begin
next_state = state;
WCtrlData = 1'b0;
RStat = 1'b0;
comm_addr_en = 0;
comm_addr_rst = 0;
stateout=0;
save = 0;
iniEnd = 0 ;
case (state)
s_rst:
begin
comm_addr_rst = 1;
if (iniStart) begin
next_state = s_ini;
end
else begin
next_state = s_rst;
end
end
s_ini:
begin
if ( |command & ~Busy) begin
next_state = s_read1; stateout=1;
end
else if ( ~(|command) & ~Busy) begin
next_state = s_ini;
iniEnd = 1;
end
else begin
next_state = s_ini; stateout=2;
end
end
s_read1:
begin
WCtrlData = 1'b0;
RStat = 1'b1;
if ( RStatStart ) begin
next_state = s_read2;stateout=4;
end
else begin
next_state = s_read1;stateout=8;
end
end
s_read2:
begin
WCtrlData = 1'b0;
RStat = 1'b1;
if (UpdateMIIRX_DATAReg) begin
next_state = s_wait;stateout=16;
save = 1;
end
else begin
next_state = s_read2;stateout=32;
end
end
s_wait:
begin
WCtrlData = 1'b0;
RStat = 1'b0;
if (~Busy) begin
next_state = s_write1;
end
else begin
next_state = s_wait;stateout=1024;
end
end
s_write1:
begin
WCtrlData = 1'b1;
RStat = 1'b0;
if ( WCtrlDataStart ) begin
next_state = s_write2; stateout=64;
end
else begin
next_state = s_write1;stateout=128;
end
end
s_write2:
begin
WCtrlData = 1'b0;
RStat = 1'b0;
if ( ~Busy ) begin
next_state = s_delay1;stateout=256;
comm_addr_en = 1;
end
else begin
next_state = s_write2;stateout=512;
end
end
s_delay1:
begin
next_state = s_delay2;
end
s_delay2:
begin
next_state = s_delay3;
end
s_delay3:
begin
next_state = s_ini;
end
endcase
end
endmodule
|
module m0(clk, key, rstn, leds);
parameter width=8;
input clk;
input key;
input rstn;
output reg [width-1:0] leds;
reg [width-1:0] r0;
initial begin
leds = 0;
r0 = 0;
end
always @(negedge key, negedge rstn) begin
if (rstn == 0)
r0 = {width{1'b0}};
else
r0 = r0 + {{width-1{1'b0}}, 1'b1};
end
always @(posedge clk) begin
if (rstn == 0)
leds <= {width{1'b0}};
else
leds <= r0;
end
endmodule
module m0_de0nano(sys_clk, key, rstn, leds);
input sys_clk;
input key;
input rstn;
output [7:0] leds;
m0 #(.width(8)) m0I(sys_clk, key, rstn, leds);
endmodule
module m0_mock(leds, key, rstn);
parameter width = 8;
input [width-1:0] leds;
output reg key;
output reg rstn;
initial begin
key = 1;
rstn = 1;
forever begin
key = #5 !key;
end
end
initial #30 rstn = 0;
initial #50 rstn = 1;
endmodule
module m0_sim;
wire [7:0] leds;
wire key;
wire clk;
wire rstn;
sim_clk m0IClk(clk);
m0 #(.width(8)) m0I(clk, key, rstn, leds);
m0_mock #(.width(8)) m0_mockI(leds, key, rstn);
initial begin
$dumpfile(`VCD_PATH);
$dumpvars();
$monitor("T=%t, clk=%d key=%d rstn=%0d leds=%0d", $time, clk, key, rstn, leds);
#70 $finish;
end
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
(* $Id: RelationClasses.v 13476 2010-09-30 11:42:11Z letouzey $ *)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
(** We allow to unfold the [relation] definition while doing morphism search. *)
Notation inverse R := (flip (R:relation _) : relation _).
Definition complement {A} (R : relation A) : relation A := fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement.
(** These are convertible. *)
Lemma complement_inverse : forall A (R : relation A), complement (inverse R) = inverse (complement R).
Proof. reflexivity. Qed.
(** We rebind relations in separate classes to be able to overload each proof. *)
Set Implicit Arguments.
Unset Strict Implicit.
Class Reflexive {A} (R : relation A) :=
reflexivity : forall x, R x x.
Class Irreflexive {A} (R : relation A) :=
irreflexivity : Reflexive (complement R).
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Class Symmetric {A} (R : relation A) :=
symmetry : forall x y, R x y -> R y x.
Class Asymmetric {A} (R : relation A) :=
asymmetry : forall x y, R x y -> R y x -> False.
Class Transitive {A} (R : relation A) :=
transitivity : forall x y z, R x y -> R y z -> R x z.
Hint Resolve @irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for relations. *)
Ltac solve_relation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_relation : relations.
(** We can already dualize all these properties. *)
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Lemma flip_Reflexive `{Reflexive A R} : Reflexive (flip R).
Proof. tauto. Qed.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Program Definition flip_Irreflexive `(Irreflexive A R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric A R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric A R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive A R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Definition Reflexive_complement_Irreflexive `(Reflexive A (R : relation A))
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric A (R : relation A)) : Symmetric (complement R).
Proof. firstorder. Qed.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply Reflexive_complement_Irreflexive : typeclass_instances.
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_relation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ intuition ]).
Local Obligation Tactic := simpl_relation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Program Instance iff_Reflexive : Reflexive iff.
Program Instance iff_Symmetric : Symmetric iff.
Program Instance iff_Transitive : Transitive iff.
(** Leibniz equality. *)
Instance eq_Reflexive {A} : Reflexive (@eq A) := @eq_refl A.
Instance eq_Symmetric {A} : Symmetric (@eq A) := @eq_sym A.
Instance eq_Transitive {A} : Transitive (@eq A) := @eq_trans A.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder {A} (R : relation A) : Prop := {
PreOrder_Reflexive :> Reflexive R ;
PreOrder_Transitive :> Transitive R }.
(** A partial equivalence relation is Symmetric and Transitive. *)
Class PER {A} (R : relation A) : Prop := {
PER_Symmetric :> Symmetric R ;
PER_Transitive :> Transitive R }.
(** Equivalence relations. *)
Class Equivalence {A} (R : relation A) : Prop := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Instance Equivalence_PER `(Equivalence A R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence relation on the carrier. *)
Class Antisymmetric A eqA `{equ : Equivalence A eqA} (R : relation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Program Definition flip_antiSymmetric `(Antisymmetric A eqA R) :
Antisymmetric A eqA (flip R).
Proof. firstorder. Qed.
(** Leibinz equality [eq] is an equivalence relation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Program Instance eq_equivalence : Equivalence (@eq A) | 10.
(** Logical equivalence [iff] is an equivalence relation. *)
Program Instance iff_equivalence : Equivalence iff.
(** We now develop a generalization of results on relations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary relations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(* Notation " [ ] " := nil : list_scope. *)
(* Notation " [ x ; .. ; y ] " := (cons x .. (cons y nil) ..) (at level 1) : list_scope. *)
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
Fixpoint arrows (l : list Type) (r : Type) : Type :=
match l with
| nil => r
| A :: l' => A -> arrows l' r
end.
(** We can define abbreviations for operation and relation types based on [arrows]. *)
Definition unary_operation A := arrows (A::nil) A.
Definition binary_operation A := arrows (A::A::nil) A.
Definition ternary_operation A := arrows (A::A::A::nil) A.
(** We define n-ary [predicate]s as functions into [Prop]. *)
Notation predicate l := (arrows l Prop).
(** Unary predicates, or sets. *)
Definition unary_predicate A := predicate (A::nil).
(** Homogeneous binary relations, equivalent to [relation A]. *)
Definition binary_relation A := predicate (A::A::nil).
(** We can close a predicate by universal or existential quantification. *)
Fixpoint predicate_all (l : list Type) : predicate l -> Prop :=
match l with
| nil => fun f => f
| A :: tl => fun f => forall x : A, predicate_all tl (f x)
end.
Fixpoint predicate_exists (l : list Type) : predicate l -> Prop :=
match l with
| nil => fun f => f
| A :: tl => fun f => exists x : A, predicate_exists tl (f x)
end.
(** Pointwise extension of a binary operation on [T] to a binary operation
on functions whose codomain is [T].
For an operator on [Prop] this lifts the operator to a binary operation. *)
Fixpoint pointwise_extension {T : Type} (op : binary_operation T)
(l : list Type) : binary_operation (arrows l T) :=
match l with
| nil => fun R R' => op R R'
| A :: tl => fun R R' =>
fun x => pointwise_extension op tl (R x) (R' x)
end.
(** Pointwise lifting, equivalent to doing [pointwise_extension] and closing using [predicate_all]. *)
Fixpoint pointwise_lifting (op : binary_relation Prop) (l : list Type) : binary_relation (predicate l) :=
match l with
| nil => fun R R' => op R R'
| A :: tl => fun R R' =>
forall x, pointwise_lifting op tl (R x) (R' x)
end.
(** The n-ary equivalence relation, defined by lifting the 0-ary [iff] relation. *)
Definition predicate_equivalence {l : list Type} : binary_relation (predicate l) :=
pointwise_lifting iff l.
(** The n-ary implication relation, defined by lifting the 0-ary [impl] relation. *)
Definition predicate_implication {l : list Type} :=
pointwise_lifting impl l.
(** Notations for pointwise equivalence and implication of predicates. *)
Infix "<∙>" := predicate_equivalence (at level 95, no associativity) : predicate_scope.
Infix "-∙>" := predicate_implication (at level 70, right associativity) : predicate_scope.
Open Local Scope predicate_scope.
(** The pointwise liftings of conjunction and disjunctions.
Note that these are [binary_operation]s, building new relations out of old ones. *)
Definition predicate_intersection := pointwise_extension and.
Definition predicate_union := pointwise_extension or.
Infix "/∙\" := predicate_intersection (at level 80, right associativity) : predicate_scope.
Infix "\∙/" := predicate_union (at level 85, right associativity) : predicate_scope.
(** The always [True] and always [False] predicates. *)
Fixpoint true_predicate {l : list Type} : predicate l :=
match l with
| nil => True
| A :: tl => fun _ => @true_predicate tl
end.
Fixpoint false_predicate {l : list Type} : predicate l :=
match l with
| nil => False
| A :: tl => fun _ => @false_predicate tl
end.
Notation "∙⊤∙" := true_predicate : predicate_scope.
Notation "∙⊥∙" := false_predicate : predicate_scope.
(** Predicate equivalence is an equivalence, and predicate implication defines a preorder. *)
Program Instance predicate_equivalence_equivalence : Equivalence (@predicate_equivalence l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
fold pointwise_lifting.
induction l. firstorder.
intros. simpl in *. pose (IHl (x x0) (y x0) (z x0)).
firstorder.
Qed.
Program Instance predicate_implication_preorder :
PreOrder (@predicate_implication l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l. firstorder.
unfold predicate_implication in *. simpl in *.
intro. pose (IHl (x x0) (y x0) (z x0)). firstorder.
Qed.
(** We define the various operations which define the algebra on binary relations,
from the general ones. *)
Definition relation_equivalence {A : Type} : relation (relation A) :=
@predicate_equivalence (_::_::nil).
Class subrelation {A:Type} (R R' : relation A) : Prop :=
is_subrelation : @predicate_implication (A::A::nil) R R'.
Implicit Arguments subrelation [[A]].
Definition relation_conjunction {A} (R : relation A) (R' : relation A) : relation A :=
@predicate_intersection (A::A::nil) R R'.
Definition relation_disjunction {A} (R : relation A) (R' : relation A) : relation A :=
@predicate_union (A::A::nil) R R'.
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Set Automatic Introduction.
Instance relation_equivalence_equivalence (A : Type) :
Equivalence (@relation_equivalence A).
Proof. exact (@predicate_equivalence_equivalence (A::A::nil)). Qed.
Instance relation_implication_preorder A : PreOrder (@subrelation A).
Proof. exact (@predicate_implication_preorder (A::A::nil)). Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence relation
on the carrier. *)
Class PartialOrder {A} eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (inverse R)).
(** The equivalence proof is sufficient for proving that [R] must be a morphism
for equivalence (see Morphisms).
It is also sufficient to show that [R] is antisymmetric w.r.t. [eqA] *)
Instance partial_order_antisym `(PartialOrder A eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
pose proof partial_order_equivalence as poe. do 3 red in poe.
apply <- poe. firstorder.
Qed.
(** The partial order defined by subrelation and relation equivalence. *)
Program Instance subrelation_partial_order :
! PartialOrder (relation A) relation_equivalence subrelation.
Next Obligation.
Proof.
unfold relation_equivalence in *. firstorder.
Qed.
Typeclasses Opaque arrows predicate_implication predicate_equivalence
relation_equivalence pointwise_lifting.
(** Rewrite relation on a given support: declares a relation as a rewrite
relation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
relations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation {A : Type} (RA : relation A).
Instance: RewriteRelation impl.
Instance: RewriteRelation iff.
Instance: RewriteRelation (@relation_equivalence A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite relation. *)
Instance equivalence_rewrite_relation `(Equivalence A eqA) : RewriteRelation eqA.
(** Strict Order *)
Class StrictOrder {A : Type} (R : relation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R
}.
Instance StrictOrder_Asymmetric `(StrictOrder A R) : Asymmetric R.
Proof. firstorder. Qed.
(** Inversing a [StrictOrder] gives another [StrictOrder] *)
Lemma StrictOrder_inverse `(StrictOrder A R) : StrictOrder (inverse R).
Proof. firstorder. Qed.
(** Same for [PartialOrder]. *)
Lemma PreOrder_inverse `(PreOrder A R) : PreOrder (inverse R).
Proof. firstorder. Qed.
Hint Extern 3 (StrictOrder (inverse _)) => class_apply StrictOrder_inverse : typeclass_instances.
Hint Extern 3 (PreOrder (inverse _)) => class_apply PreOrder_inverse : typeclass_instances.
Lemma PartialOrder_inverse `(PartialOrder A eqA R) : PartialOrder eqA (inverse R).
Proof. firstorder. Qed.
Hint Extern 3 (PartialOrder (inverse _)) => class_apply PartialOrder_inverse : typeclass_instances.
|
/**
* bsg_cache_to_axi_tx.v
*
* @author tommy
*/
`include "bsg_defines.v"
module bsg_cache_to_axi_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
,parameter `BSG_INV_PARAM(data_width_p)
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter tag_fifo_els_p=num_cache_p
,parameter `BSG_INV_PARAM(axi_id_width_p)
,parameter `BSG_INV_PARAM(axi_addr_width_p)
,parameter `BSG_INV_PARAM(axi_data_width_p)
,parameter `BSG_INV_PARAM(axi_burst_len_p)
,parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
,parameter axi_strb_width_lp=(axi_data_width_p>>3)
,parameter data_width_ratio_lp=(axi_data_width_p/data_width_p)
)
(
input clk_i
,input reset_i
,input v_i
,output logic yumi_o
,input [lg_num_cache_lp-1:0] tag_i
,input [axi_addr_width_p-1:0] axi_addr_i
// cache dma write channel
,input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
,input [num_cache_p-1:0] dma_data_v_i
,output logic [num_cache_p-1:0] dma_data_yumi_o
// axi write address channel
,output logic [axi_id_width_p-1:0] axi_awid_o
,output logic [axi_addr_width_p-1:0] axi_awaddr_o
,output logic [7:0] axi_awlen_o
,output logic [2:0] axi_awsize_o
,output logic [1:0] axi_awburst_o
,output logic [3:0] axi_awcache_o
,output logic [2:0] axi_awprot_o
,output logic axi_awlock_o
,output logic axi_awvalid_o
,input axi_awready_i
// axi write data channel
,output logic [axi_data_width_p-1:0] axi_wdata_o
,output logic [axi_strb_width_lp-1:0] axi_wstrb_o
,output logic axi_wlast_o
,output logic axi_wvalid_o
,input axi_wready_i
// axi write response channel
,input [axi_id_width_p-1:0] axi_bid_i
,input [1:0] axi_bresp_i
,input axi_bvalid_i
,output logic axi_bready_o
);
// tag fifo
//
logic tag_fifo_v_li;
logic tag_fifo_ready_lo;
logic tag_fifo_v_lo;
logic tag_fifo_yumi_li;
logic [lg_num_cache_lp-1:0] tag_lo;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(tag_fifo_els_p)
) tag_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(tag_fifo_v_li)
,.ready_o(tag_fifo_ready_lo)
,.data_i(tag_i)
,.v_o(tag_fifo_v_lo)
,.data_o(tag_lo)
,.yumi_i(tag_fifo_yumi_li)
);
// suppress unused
//
wire [axi_id_width_p-1:0] unused_bid = axi_bid_i;
wire [1:0] unused_bresp = axi_bresp_i;
wire unused_bvalid = axi_bvalid_i;
// tag
//
// yumi when both tag_fifo and axi_aw are ready
assign yumi_o = v_i & axi_awready_i & tag_fifo_ready_lo;
// tag_fifo is valid when axi_aw is ready
assign tag_fifo_v_li = v_i & axi_awready_i;
// axi write address channel
//
assign axi_awid_o = {axi_id_width_p{1'b0}};
assign axi_awaddr_o = axi_addr_i;
assign axi_awlen_o = (8)'(axi_burst_len_p-1); // burst len
assign axi_awsize_o = (3)'(`BSG_SAFE_CLOG2(axi_data_width_p>>3));
assign axi_awburst_o = 2'b01; // incr
assign axi_awcache_o = 4'b0000; // non-bufferable
assign axi_awprot_o = 2'b00; // unprivileged
assign axi_awlock_o = 1'b0; // normal access
// axi_aw is valid when tag_fifo is ready
assign axi_awvalid_o = v_i & tag_fifo_ready_lo;
// axi write data channel
//
logic sipo_v_li;
logic sipo_ready_lo;
logic [data_width_p-1:0] sipo_data_li;
logic [$clog2(data_width_ratio_lp+1)-1:0] sipo_yumi_cnt_li;
logic [data_width_ratio_lp-1:0] sipo_v_lo;
logic [num_cache_p-1:0] cache_sel;
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_lo)
,.v_i(tag_fifo_v_lo)
,.o(cache_sel)
);
assign sipo_data_li = dma_data_i[tag_lo];
assign dma_data_yumi_o = cache_sel & dma_data_v_i & {num_cache_p{sipo_ready_lo}};
bsg_serial_in_parallel_out #(
.width_p(data_width_p)
,.els_p(data_width_ratio_lp)
) sipo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.valid_i(sipo_v_li)
,.data_i(sipo_data_li)
,.ready_o(sipo_ready_lo)
,.valid_o(sipo_v_lo)
,.data_o(axi_wdata_o)
,.yumi_cnt_i(sipo_yumi_cnt_li)
);
assign axi_wvalid_o = &sipo_v_lo;
assign sipo_v_li = tag_fifo_v_lo & dma_data_v_i[tag_lo];
assign sipo_yumi_cnt_li = axi_wvalid_o & axi_wready_i
? ($clog2(data_width_ratio_lp+1))'(data_width_ratio_lp)
: '0;
assign axi_wstrb_o = {axi_strb_width_lp{1'b1}};
// word counter
//
logic [`BSG_SAFE_CLOG2(block_size_in_words_p)-1:0] word_count_lo;
logic word_up_li;
logic word_clear_li;
bsg_counter_clear_up #(
.max_val_p(block_size_in_words_p-1)
,.init_val_p(0)
) word_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(word_clear_li)
,.up_i(word_up_li)
,.count_o(word_count_lo)
);
logic pop_word;
assign pop_word = dma_data_v_i[tag_lo] & dma_data_yumi_o[tag_lo] & tag_fifo_v_lo;
always_comb begin
if (word_count_lo == block_size_in_words_p-1) begin
word_clear_li = pop_word;
word_up_li = 1'b0;
tag_fifo_yumi_li = pop_word;
end
else begin
word_clear_li = 1'b0;
word_up_li = pop_word;
tag_fifo_yumi_li = 1'b0;
end
end
// burst counter
//
logic [`BSG_SAFE_CLOG2(axi_burst_len_p)-1:0] burst_count_lo;
logic burst_up_li;
logic burst_clear_li;
bsg_counter_clear_up #(
.max_val_p(axi_burst_len_p-1)
,.init_val_p(0)
) burst_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(burst_clear_li)
,.up_i(burst_up_li)
,.count_o(burst_count_lo)
);
always_comb begin
if (burst_count_lo == axi_burst_len_p-1) begin
burst_clear_li = axi_wvalid_o & axi_wready_i;
burst_up_li = 1'b0;
axi_wlast_o = axi_wvalid_o;
end
else begin
burst_clear_li = 1'b0;
burst_up_li = axi_wvalid_o & axi_wready_i;
axi_wlast_o = 1'b0;
end
end
// axi write response channel
//
assign axi_bready_o = 1'b1; // don't really care about the resp.
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_axi_tx)
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_vuaddp_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_vuaddp_ctl
(/*AUTOARG*/
// Outputs
so, vuad_sel_c2, vuad_sel_c2_d1, vuad_sel_c2orc3, vuad_sel_c4,
vuad_sel_rd, vuad_tagdp_sel_c2_d1, st_to_data_array_c3,
wr64_inst_c3, vuad_evict_c3, alloc_set_cond_c3, alloc_rst_cond_c3,
vuad_error_c8, hit_wayvld_c3, fill_way_c3, lru_way_c3,
bistordiag_wr_vd_c4, bistordiag_wr_ua_c4, sel_ua_wr_data_byp,
sel_vd_wr_data_byp, sel_diag0_data_wr_c3, sel_diag1_data_wr_c3,
vuad_array_wr_en0_c4, vuad_array_wr_en1_c4, vuad_idx_c4,
// Inputs
rclk, si, se, bist_vuad_idx_c3, vuad_idx_c3, bist_wr_vd_c3,
tagctl_hit_way_vld_c3, lru_way_sel_c3, tagctl_st_to_data_array_c3,
decdp_wr64_inst_c2, evict_c3, arbctl_acc_vd_c2, arbctl_acc_ua_c2,
sehold, idx_c1c2comp_c1, idx_c1c3comp_c1, idx_c1c4comp_c1,
idx_c1c5comp_c1, decdp_inst_int_c1, l2_bypass_mode_on,
arbctl_inst_diag_c1, bist_vuad_wr_en, arbctl_inst_vld_c2,
arbctl_inst_l2vuad_vld_c3, decdp_st_inst_c3, arbdp_inst_fb_c2,
parity_c4, arbdp_inst_way_c2, arbdp_vuadctl_pst_no_ctrue_c2,
decdp_cas1_inst_c2, arbdp_pst_with_ctrue_c2, decdp_cas2_inst_c2,
arbdp_inst_mb_c2, vuadctl_no_bypass_px2
) ;
input rclk;
input si, se;
output so;
input [9:0] bist_vuad_idx_c3 ; // NEW_PIN
input [9:0] vuad_idx_c3; // NEW_PIN
input bist_wr_vd_c3 ; // NEW_PIN
input [11:0] tagctl_hit_way_vld_c3; // Top
input [11:0] lru_way_sel_c3; // Top
input tagctl_st_to_data_array_c3; // Top
input decdp_wr64_inst_c2; // Top
input evict_c3; // Top
input arbctl_acc_vd_c2; // Top // diagnostic access only
input arbctl_acc_ua_c2; // Top // diagnostic access only
input sehold ; // POST_4.2
// C1 outputs
input idx_c1c2comp_c1 ; // from arbaddr Top
input idx_c1c3comp_c1 ; // from arbaddr Top
input idx_c1c4comp_c1 ; // from arbaddr Top
input idx_c1c5comp_c1 ; // from arbaddr. POST_3.0 Top
input decdp_inst_int_c1; // Top
input l2_bypass_mode_on; // Top
input arbctl_inst_diag_c1; // Top
input bist_vuad_wr_en; // Top // This is a C3 signal.
input arbctl_inst_vld_c2; // Top
input arbctl_inst_l2vuad_vld_c3; // Top
input decdp_st_inst_c3; // Top
input arbdp_inst_fb_c2; // Top
input [3:0] parity_c4; // Bottom
input [3:0] arbdp_inst_way_c2;
input arbdp_vuadctl_pst_no_ctrue_c2; // Top
input decdp_cas1_inst_c2; // Top
input arbdp_pst_with_ctrue_c2; // Top
input decdp_cas2_inst_c2; // Top
input arbdp_inst_mb_c2; // Top
input vuadctl_no_bypass_px2; // Top
output vuad_sel_c2; // Bottom
output vuad_sel_c2_d1; // Bottom
output vuad_sel_c2orc3; // Bottom
output vuad_sel_c4; // Bottom
output vuad_sel_rd; // Bottom
output vuad_tagdp_sel_c2_d1; // Top
output st_to_data_array_c3; // Bottom
output wr64_inst_c3 ; // Bottom
output vuad_evict_c3 ; // Bottom
output alloc_set_cond_c3; // Bottom
output alloc_rst_cond_c3; // Bottom
output vuad_error_c8; // Bottom
output [11:0] hit_wayvld_c3; // Bottom
output [11:0] fill_way_c3; // Bottom
output [11:0] lru_way_c3; // Bottom
output bistordiag_wr_vd_c4 ; // Bottom // bist or diag access
output bistordiag_wr_ua_c4 ; // Bottom // bist or diag access
output sel_ua_wr_data_byp; // Bottom
output sel_vd_wr_data_byp; // Bottom
output sel_diag0_data_wr_c3; // Bottom sel between diagnostic and bist data
output sel_diag1_data_wr_c3; // Bottom sel between diagnostic and bist data
output vuad_array_wr_en0_c4; // Bottom // Change to C4
output vuad_array_wr_en1_c4; // Bottom // Change to C4
output [9:0] vuad_idx_c4; // NEW PIN
wire vuad_array_wr_en0_c3, vuad_array_wr_en0_c5, vuad_array_wr_en0_c6;
wire vuad_array_wr_en1_c3, vuad_array_wr_en1_c5, vuad_array_wr_en1_c6;
wire vuad_sel_wr, vuad_sel_c4orc5;
wire inst_vld_c3;
wire inst_vld_c4;
wire inst_vld_c5;
wire arbctl_inst_diag_c2;
wire arbctl_inst_diag_c3;
wire arbctl_inst_diag_c4;
wire l2_bypass_mode_on_d1;
wire wr_disable_c3;
wire vuad_error_c4, vuad_error_c5;
wire vuad_error_c6, vuad_error_c7;
wire alloc_set_cond_c2;
wire alloc_rst_cond_c2;
wire fill_inst_vld_c2;
wire [3:0] dec_lo_fill_way_c2;
wire [3:0] dec_hi_fill_way_c2;
wire [11:0] fill_way_c2;
wire acc_vd_c3;
wire acc_ua_c3;
wire bistordiag_wr_vd_c3, bistordiag_wr_ua_c3 ;
wire [9:0] vuad_acc_idx_c3;
wire vuadctl_no_bypass_c1;
wire inst_int_c2, inst_int_c3, inst_int_c4, inst_int_c5;
assign st_to_data_array_c3 = tagctl_st_to_data_array_c3;
assign lru_way_c3 = lru_way_sel_c3;
assign hit_wayvld_c3 = tagctl_hit_way_vld_c3 ;
dff_s #(1) ff_vuadctl_no_bypass_c1 (.din(vuadctl_no_bypass_px2),
.clk(rclk),
.q(vuadctl_no_bypass_c1), .se(se), .si(), .so());
////////////////////////////////////////////////////////////////////////
// index compares to for vuad mux selects.
////////////////////////////////////////////////////////////////////////
assign vuad_sel_c2 = idx_c1c2comp_c1 & arbctl_inst_vld_c2 &
~( decdp_inst_int_c1 | inst_int_c2 ) ;
assign vuad_sel_c4 = idx_c1c4comp_c1 & inst_vld_c4 &
~( decdp_inst_int_c1 | inst_int_c4) ;
assign vuad_sel_c2orc3 = ( (( idx_c1c3comp_c1 & inst_vld_c3) &
~( decdp_inst_int_c1 | inst_int_c3) ) |
vuad_sel_c2
) ;
assign vuad_sel_wr = ( idx_c1c5comp_c1 & inst_vld_c5) &
~( decdp_inst_int_c1 | inst_int_c5) ;
assign vuad_sel_c4orc5 = vuad_sel_c4 | vuad_sel_wr ;
/////// ----\/ Fix for macrotest \/---------
// sehold will cause the vuad_sel_rd signal
// to be high during macrotest and hence
// cause the array output to be flopped in C2
/////// ----\/ Fix for macrotest \/---------
assign vuad_sel_rd = ~( vuad_sel_c2orc3 | vuad_sel_c4orc5 ) |
vuadctl_no_bypass_c1 | // BIST or DECC read of VUAD
sehold ;
dff_s #(1) ff_vuad_sel_c2_d1 (.din(vuad_sel_c2), .clk(rclk),
.q(vuad_sel_c2_d1), .se(se), .si(), .so());
dff_s #(1) ff_vuad_sel_wr_d1 (.din(vuad_sel_wr), .clk(rclk),
.q(vuad_sel_wr_d1), .se(se), .si(), .so());
dff_s #(1) ff_vuad_tagdp_sel_c2_d1 (.din(vuad_sel_c2), .clk(rclk),
.q(vuad_tagdp_sel_c2_d1), .se(se), .si(), .so());
assign vuad_evict_c3 = evict_c3;
dff_s #(1) ff_inst_int_c2
(.din(decdp_inst_int_c1), .clk(rclk),
.q(inst_int_c2), .se(se), .si(), .so()
);
dff_s #(1) ff_inst_int_c3
(.din(inst_int_c2), .clk(rclk),
.q(inst_int_c3), .se(se), .si(), .so()
);
dff_s #(1) ff_wr64_inst_c3
(.din(decdp_wr64_inst_c2), .clk(rclk),
.q(wr64_inst_c3), .se(se), .si(), .so()
);
dff_s #(1) ff_arbctl_acc_vd_c3
(.q (acc_vd_c3), .din (arbctl_acc_vd_c2),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_arbctl_acc_ua_c3
(.q (acc_ua_c3), .din (arbctl_acc_ua_c2),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_inst_vld_c3
(.q (inst_vld_c3), .din (arbctl_inst_vld_c2),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_inst_vld_c4
(.q (inst_vld_c4), .din (inst_vld_c3),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_inst_vld_c5
(.q (inst_vld_c5), .din (inst_vld_c4),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_arbctl_inst_diag_c2
(.q (arbctl_inst_diag_c2), .din (arbctl_inst_diag_c1),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_arbctl_inst_diag_c3
(.q (arbctl_inst_diag_c3), .din (arbctl_inst_diag_c2),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_arbctl_inst_diag_c4
(.q (arbctl_inst_diag_c4), .din (arbctl_inst_diag_c3),
.clk (rclk), .se(se), .si (), .so ()
) ;
//dff #(1) ff_fbctl_vuad_bypassed_c3
//(.q (fbctl_vuad_bypassed_c3), .din (fbctl_vuad_bypassed_c2),
//.clk (rclk), .se(se), .si (), .so ()
//) ;
mux2ds #(10) mux_idx_c3 (.dout (vuad_acc_idx_c3[9:0]) ,
.in0(bist_vuad_idx_c3[9:0] ),
.in1(vuad_idx_c3[9:0]),
.sel0(bist_vuad_wr_en),
.sel1(~bist_vuad_wr_en)) ;
dff_s #(10) ff_mux_idx_c4
(.q (vuad_idx_c4[9:0]), .din (vuad_acc_idx_c3[9:0]),
.clk (rclk), .se(se), .si (), .so ()
) ;
//////////////////////////////////////////////////////////////////////////////////////////
// Disable L2 VUAD writes if
// 1. Instruction is an INT.
// 2. L2 is OFF and the instruction is a non-diag instruction.
// 3. diag instruction is not a VUAD store.
// (in implementation disable the write whenever there is Diag Inst and
// enable it if the inst is a Diag write to the VUAD array.)
//////////////////////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_l2_bypass_mode_on_d1
(.q (l2_bypass_mode_on_d1), .din (l2_bypass_mode_on),
.clk (rclk), .se(se), .si (), .so ()
) ;
assign wr_disable_c3 = inst_int_c3 |
(l2_bypass_mode_on_d1 & ~arbctl_inst_diag_c3) |
arbctl_inst_diag_c3 ;
//////////////////////////
// access PV, PD, V, P
//////////////////////////
assign sel_diag0_data_wr_c3 = arbctl_inst_l2vuad_vld_c3 &
decdp_st_inst_c3 & acc_vd_c3 ; // sel diag over bist data
assign bistordiag_wr_vd_c3 = sel_diag0_data_wr_c3 | // diagorbist over normal data
( bist_vuad_wr_en & bist_wr_vd_c3 );
dff_s #(1) ff_bistordiag_wr_vd_c4
(.q (bistordiag_wr_vd_c4), .din (bistordiag_wr_vd_c3),
.clk (rclk), .se(se), .si (), .so ()
) ;
assign vuad_array_wr_en1_c3 = (inst_vld_c3 & ~wr_disable_c3) | // normal write
bistordiag_wr_vd_c3; // bist or diag write
//////////////////////////
// access PU, PA, U, A
//////////////////////////
assign sel_diag1_data_wr_c3 = arbctl_inst_l2vuad_vld_c3 &
decdp_st_inst_c3 & acc_ua_c3 ; // sel diag over bist data
assign bistordiag_wr_ua_c3 = sel_diag1_data_wr_c3 | // diagorbist over normal data
( bist_vuad_wr_en & ~bist_wr_vd_c3 );
dff_s #(1) ff_bistordiag_wr_ua_c4
(.q (bistordiag_wr_ua_c4), .din (bistordiag_wr_ua_c3),
.clk (rclk), .se(se), .si (), .so ()
) ;
assign vuad_array_wr_en0_c3 = ( inst_vld_c3 & ~wr_disable_c3) | // normal write
bistordiag_wr_ua_c3 ; // bist or diag write
dff_s #(1) ff_vuad_array_wr_en0_c4
(.din(vuad_array_wr_en0_c3), .clk(rclk),
.q(vuad_array_wr_en0_c4), .se(se), .si(), .so()
);
dff_s #(1) ff_vuad_array_wr_en1_c4
(.din(vuad_array_wr_en1_c3), .clk(rclk),
.q(vuad_array_wr_en1_c4), .se(se), .si(), .so()
);
dff_s #(1) ff_vuad_array_wr_en0_c5
(.din(vuad_array_wr_en0_c4), .clk(rclk),
.q(vuad_array_wr_en0_c5), .se(se), .si(), .so()
);
dff_s #(1) ff_vuad_array_wr_en1_c5
(.din(vuad_array_wr_en1_c4), .clk(rclk),
.q(vuad_array_wr_en1_c5), .se(se), .si(), .so()
);
dff_s #(1) ff_vuad_array_wr_en0_c6
(.din(vuad_array_wr_en0_c5), .clk(rclk),
.q(vuad_array_wr_en0_c6), .se(se), .si(), .so()
);
dff_s #(1) ff_vuad_array_wr_en1_c6
(.din(vuad_array_wr_en1_c5), .clk(rclk),
.q(vuad_array_wr_en1_c6), .se(se), .si(), .so()
);
assign sel_ua_wr_data_byp = vuad_sel_wr_d1
& vuad_array_wr_en1_c6 ;
assign sel_vd_wr_data_byp = vuad_sel_wr_d1
& vuad_array_wr_en0_c6 ;
//* All errors are qualififed in the block that generates them
dff_s #(1) ff_inst_int_c4
(.q (inst_int_c4), .din (inst_int_c3),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_inst_int_c5
(.q (inst_int_c5), .din (inst_int_c4),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Used bit error will not be reported as they are harmless.
// This is accomplished by tying parity_c4[1] to 0 in the
// top level file.
assign vuad_error_c4 = ~(arbctl_inst_diag_c4 | inst_int_c4) &
((|(parity_c4[3:2])) | (|(parity_c4[1:0])) ) &
inst_vld_c4;
dff_s #(1) ff_vuad_error_c5
(.q (vuad_error_c5), .din (vuad_error_c4),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_vuad_error_c6
(.q (vuad_error_c6), .din (vuad_error_c5),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_vuad_error_c7
(.q (vuad_error_c7), .din (vuad_error_c6),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_vuad_error_c8
(.q (vuad_error_c8), .din (vuad_error_c7),
.clk (rclk), .se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// 4-12 decoder for the fill way
// Conditions for altering the VUAD bits.
////////////////////////////////////////////////////////////////////////////////
assign fill_inst_vld_c2 = arbdp_inst_fb_c2 & arbctl_inst_vld_c2 ;
assign dec_lo_fill_way_c2[0] = ( arbdp_inst_way_c2[1:0]==2'd0 )
& fill_inst_vld_c2 ;
assign dec_lo_fill_way_c2[1] = ( arbdp_inst_way_c2[1:0]==2'd1 )
& fill_inst_vld_c2 ;
assign dec_lo_fill_way_c2[2] = ( arbdp_inst_way_c2[1:0]==2'd2 )
& fill_inst_vld_c2 ;
assign dec_lo_fill_way_c2[3] = ( arbdp_inst_way_c2[1:0]==2'd3 )
& fill_inst_vld_c2 ;
assign dec_hi_fill_way_c2[0] = ( arbdp_inst_way_c2[3:2]==2'd0 ) ;
assign dec_hi_fill_way_c2[1] = ( arbdp_inst_way_c2[3:2]==2'd1 ) ;
assign dec_hi_fill_way_c2[2] = ( arbdp_inst_way_c2[3:2]==2'd2 ) ;
assign dec_hi_fill_way_c2[3] = ( arbdp_inst_way_c2[3:2]==2'd3 ) ;
assign fill_way_c2[0] = dec_hi_fill_way_c2[0] &
dec_lo_fill_way_c2[0] ; // 0000
assign fill_way_c2[1] = dec_hi_fill_way_c2[0] &
dec_lo_fill_way_c2[1] ; // 0001
assign fill_way_c2[2] = dec_hi_fill_way_c2[0] &
dec_lo_fill_way_c2[2] ; // 0010
assign fill_way_c2[3] = dec_hi_fill_way_c2[0] &
dec_lo_fill_way_c2[3] ; // 0011
assign fill_way_c2[4] = ( dec_hi_fill_way_c2[1] |
dec_hi_fill_way_c2[3] ) &
dec_lo_fill_way_c2[0] ; // 0100 or 1100
assign fill_way_c2[5] = ( dec_hi_fill_way_c2[1] |
dec_hi_fill_way_c2[3] ) &
dec_lo_fill_way_c2[1] ; // 0101 or 1101
assign fill_way_c2[6] = ( dec_hi_fill_way_c2[1] |
dec_hi_fill_way_c2[3] ) &
dec_lo_fill_way_c2[2] ; // 0110 or 1110
assign fill_way_c2[7] = ( dec_hi_fill_way_c2[1] |
dec_hi_fill_way_c2[3] ) &
dec_lo_fill_way_c2[3] ; // 0111 or 1111
assign fill_way_c2[8] = dec_hi_fill_way_c2[2] &
dec_lo_fill_way_c2[0] ; // 1000
assign fill_way_c2[9] = dec_hi_fill_way_c2[2] &
dec_lo_fill_way_c2[1] ; // 1001
assign fill_way_c2[10] = dec_hi_fill_way_c2[2] &
dec_lo_fill_way_c2[2] ; // 1010
assign fill_way_c2[11] = dec_hi_fill_way_c2[2] &
dec_lo_fill_way_c2[3] ; // 1011
dff_s #(12) ff_fill_way_c3
(.q (fill_way_c3[11:0]), .din (fill_way_c2[11:0]),
.clk (rclk), .se(se), .si (), .so ()
) ;
assign alloc_set_cond_c2 = (arbdp_vuadctl_pst_no_ctrue_c2 | decdp_cas1_inst_c2) ;
assign alloc_rst_cond_c2 = arbdp_pst_with_ctrue_c2 |
(decdp_cas2_inst_c2 & arbdp_inst_mb_c2) |
(arbdp_inst_mb_c2 & ~alloc_set_cond_c2) ;
dff_s #(1) ff_alloc_set_cond_c3
(.q (alloc_set_cond_c3), .din (alloc_set_cond_c2),
.clk (rclk), .se(se), .si (), .so ()
) ;
dff_s #(1) ff_alloc_rst_cond_c3
(.q (alloc_rst_cond_c3), .din (alloc_rst_cond_c2),
.clk (rclk), .se(se), .si (), .so ()
) ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_SN_TB_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_SN_TB_V
/**
* udp_dlatch$P_pp$PKG$sN: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dlatch_p_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 NOTIFIER = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 NOTIFIER = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 NOTIFIER = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 NOTIFIER = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$sN dut (.D(D), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PKG_SN_TB_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altera_mem_if_ddr3_phy_0001_pll_memphy.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 208 07/03/2011 SP 1.10 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_mem_if_ddr3_phy_0001_pll_memphy (
areset,
inclk0,
c0,
c1,
c2,
c3,
c4,
c5,
c6,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output c6;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0;
wire sub_wire8;
wire [0:0] sub_wire11 = 1'h0;
wire [3:3] sub_wire7 = sub_wire0[3:3];
wire [6:6] sub_wire6 = sub_wire0[6:6];
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire c4 = sub_wire5;
wire c6 = sub_wire6;
wire c3 = sub_wire7;
wire locked = sub_wire8;
wire sub_wire9 = inclk0;
wire [1:0] sub_wire10 = {sub_wire11, sub_wire9};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire10),
.clk (sub_wire0),
.locked (sub_wire8),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 80,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 213,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 40,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 213,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 40,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 213,
altpll_component.clk2_phase_shift = "235",
altpll_component.clk3_divide_by = 80,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 213,
altpll_component.clk3_phase_shift = "2817",
altpll_component.clk4_divide_by = 160,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 213,
altpll_component.clk4_phase_shift = "0",
altpll_component.clk5_divide_by = 80,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 71,
altpll_component.clk5_phase_shift = "0",
altpll_component.clk6_divide_by = 320,
altpll_component.clk6_duty_cycle = 50,
altpll_component.clk6_multiply_by = 71,
altpll_component.clk6_phase_shift = "0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altera_mem_if_ddr3_phy_0001_pll_memphy",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_USED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "80"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "40"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "40"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "80"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "160"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "80"
// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "320"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "266.250000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "532.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "532.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "266.250000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "133.125000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "88.750000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE6 STRING "22.187500"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "10000.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "ps"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "71"
// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "71"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "235.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "2817.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altera_mem_if_ddr3_phy_0001_pll_memphy.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK6 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_CLK6 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "235"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2817"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "160"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK6_DIVIDE_BY NUMERIC "320"
// Retrieval info: CONSTANT: CLK6_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK6_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK6_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: c6 0 0 0 0 OUTPUT_CLK_EXT VCC "c6"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: c6 0 0 0 0 @clk 0 0 1 6
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_mem_if_ddr3_phy_0001_pll_memphy.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_mem_if_ddr3_phy_0001_pll_memphy.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_mem_if_ddr3_phy_0001_pll_memphy.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_mem_if_ddr3_phy_0001_pll_memphy.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_mem_if_ddr3_phy_0001_pll_memphy.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_mem_if_ddr3_phy_0001_pll_memphy_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_mem_if_ddr3_phy_0001_pll_memphy_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * An light axiomatization of integers (used in MSetAVL). *)
(** We define a signature for an integer datatype based on [Z].
The goal is to allow a switch after extraction to ocaml's
[big_int] or even [int] when finiteness isn't a problem
(typically : when mesuring the height of an AVL tree).
*)
Require Import BinInt.
Delimit Scope Int_scope with I.
Local Open Scope Int_scope.
(** * A specification of integers *)
Module Type Int.
Parameter t : Set.
Bind Scope Int_scope with t.
Parameter i2z : t -> Z.
Parameter _0 : t.
Parameter _1 : t.
Parameter _2 : t.
Parameter _3 : t.
Parameter add : t -> t -> t.
Parameter opp : t -> t.
Parameter sub : t -> t -> t.
Parameter mul : t -> t -> t.
Parameter max : t -> t -> t.
Notation "0" := _0 : Int_scope.
Notation "1" := _1 : Int_scope.
Notation "2" := _2 : Int_scope.
Notation "3" := _3 : Int_scope.
Infix "+" := add : Int_scope.
Infix "-" := sub : Int_scope.
Infix "*" := mul : Int_scope.
Notation "- x" := (opp x) : Int_scope.
(** For logical relations, we can rely on their counterparts in Z,
since they don't appear after extraction. Moreover, using tactics
like omega is easier this way. *)
Notation "x == y" := (i2z x = i2z y)
(at level 70, y at next level, no associativity) : Int_scope.
Notation "x <= y" := (i2z x <= i2z y)%Z : Int_scope.
Notation "x < y" := (i2z x < i2z y)%Z : Int_scope.
Notation "x >= y" := (i2z x >= i2z y)%Z : Int_scope.
Notation "x > y" := (i2z x > i2z y)%Z : Int_scope.
Notation "x <= y <= z" := (x <= y /\ y <= z) : Int_scope.
Notation "x <= y < z" := (x <= y /\ y < z) : Int_scope.
Notation "x < y < z" := (x < y /\ y < z) : Int_scope.
Notation "x < y <= z" := (x < y /\ y <= z) : Int_scope.
(** Informative comparisons. *)
Axiom eqb : t -> t -> bool.
Axiom ltb : t -> t -> bool.
Axiom leb : t -> t -> bool.
Infix "=?" := eqb.
Infix "<?" := ltb.
Infix "<=?" := leb.
(** For compatibility, some decidability fonctions (informative). *)
Axiom gt_le_dec : forall x y : t, {x > y} + {x <= y}.
Axiom ge_lt_dec : forall x y : t, {x >= y} + {x < y}.
Axiom eq_dec : forall x y : t, { x == y } + {~ x==y }.
(** Specifications *)
(** First, we ask [i2z] to be injective. Said otherwise, our ad-hoc equality
[==] and the generic [=] are in fact equivalent. We define [==]
nonetheless since the translation to [Z] for using automatic tactic
is easier. *)
Axiom i2z_eq : forall n p : t, n == p -> n = p.
(** Then, we express the specifications of the above parameters using their
Z counterparts. *)
Axiom i2z_0 : i2z _0 = 0%Z.
Axiom i2z_1 : i2z _1 = 1%Z.
Axiom i2z_2 : i2z _2 = 2%Z.
Axiom i2z_3 : i2z _3 = 3%Z.
Axiom i2z_add : forall n p, i2z (n + p) = (i2z n + i2z p)%Z.
Axiom i2z_opp : forall n, i2z (-n) = (-i2z n)%Z.
Axiom i2z_sub : forall n p, i2z (n - p) = (i2z n - i2z p)%Z.
Axiom i2z_mul : forall n p, i2z (n * p) = (i2z n * i2z p)%Z.
Axiom i2z_max : forall n p, i2z (max n p) = Z.max (i2z n) (i2z p).
Axiom i2z_eqb : forall n p, eqb n p = Z.eqb (i2z n) (i2z p).
Axiom i2z_ltb : forall n p, ltb n p = Z.ltb (i2z n) (i2z p).
Axiom i2z_leb : forall n p, leb n p = Z.leb (i2z n) (i2z p).
End Int.
(** * Facts and tactics using [Int] *)
Module MoreInt (Import I:Int).
Local Notation int := I.t.
Lemma eqb_eq n p : (n =? p) = true <-> n == p.
Proof.
now rewrite i2z_eqb, Z.eqb_eq.
Qed.
Lemma eqb_neq n p : (n =? p) = false <-> ~(n == p).
Proof.
rewrite <- eqb_eq. destruct (n =? p); intuition.
Qed.
Lemma ltb_lt n p : (n <? p) = true <-> n < p.
Proof.
now rewrite i2z_ltb, Z.ltb_lt.
Qed.
Lemma ltb_nlt n p : (n <? p) = false <-> ~(n < p).
Proof.
rewrite <- ltb_lt. destruct (n <? p); intuition.
Qed.
Lemma leb_le n p : (n <=? p) = true <-> n <= p.
Proof.
now rewrite i2z_leb, Z.leb_le.
Qed.
Lemma leb_nle n p : (n <=? p) = false <-> ~(n <= p).
Proof.
rewrite <- leb_le. destruct (n <=? p); intuition.
Qed.
(** A magic (but costly) tactic that goes from [int] back to the [Z]
friendly world ... *)
Hint Rewrite ->
i2z_0 i2z_1 i2z_2 i2z_3 i2z_add i2z_opp i2z_sub i2z_mul i2z_max
i2z_eqb i2z_ltb i2z_leb : i2z.
Ltac i2z := match goal with
| H : ?a = ?b |- _ =>
generalize (f_equal i2z H);
try autorewrite with i2z; clear H; intro H; i2z
| |- ?a = ?b =>
apply (i2z_eq a b); try autorewrite with i2z; i2z
| H : _ |- _ => progress autorewrite with i2z in H; i2z
| _ => try autorewrite with i2z
end.
(** A reflexive version of the [i2z] tactic *)
(** this [i2z_refl] is actually weaker than [i2z]. For instance, if a
[i2z] is buried deep inside a subterm, [i2z_refl] may miss it.
See also the limitation about [Set] or [Type] part below.
Anyhow, [i2z_refl] is enough for applying [romega]. *)
Ltac i2z_gen := match goal with
| |- ?a = ?b => apply (i2z_eq a b); i2z_gen
| H : ?a = ?b |- _ =>
generalize (f_equal i2z H); clear H; i2z_gen
| H : eq (A:=Z) ?a ?b |- _ => revert H; i2z_gen
| H : Z.lt ?a ?b |- _ => revert H; i2z_gen
| H : Z.le ?a ?b |- _ => revert H; i2z_gen
| H : Z.gt ?a ?b |- _ => revert H; i2z_gen
| H : Z.ge ?a ?b |- _ => revert H; i2z_gen
| H : _ -> ?X |- _ =>
(* A [Set] or [Type] part cannot be dealt with easily
using the [ExprP] datatype. So we forget it, leaving
a goal that can be weaker than the original. *)
match type of X with
| Type => clear H; i2z_gen
| Prop => revert H; i2z_gen
end
| H : _ <-> _ |- _ => revert H; i2z_gen
| H : _ /\ _ |- _ => revert H; i2z_gen
| H : _ \/ _ |- _ => revert H; i2z_gen
| H : ~ _ |- _ => revert H; i2z_gen
| _ => idtac
end.
Inductive ExprI : Set :=
| EI0 : ExprI
| EI1 : ExprI
| EI2 : ExprI
| EI3 : ExprI
| EIadd : ExprI -> ExprI -> ExprI
| EIopp : ExprI -> ExprI
| EIsub : ExprI -> ExprI -> ExprI
| EImul : ExprI -> ExprI -> ExprI
| EImax : ExprI -> ExprI -> ExprI
| EIraw : int -> ExprI.
Inductive ExprZ : Set :=
| EZadd : ExprZ -> ExprZ -> ExprZ
| EZopp : ExprZ -> ExprZ
| EZsub : ExprZ -> ExprZ -> ExprZ
| EZmul : ExprZ -> ExprZ -> ExprZ
| EZmax : ExprZ -> ExprZ -> ExprZ
| EZofI : ExprI -> ExprZ
| EZraw : Z -> ExprZ.
Inductive ExprP : Type :=
| EPeq : ExprZ -> ExprZ -> ExprP
| EPlt : ExprZ -> ExprZ -> ExprP
| EPle : ExprZ -> ExprZ -> ExprP
| EPgt : ExprZ -> ExprZ -> ExprP
| EPge : ExprZ -> ExprZ -> ExprP
| EPimpl : ExprP -> ExprP -> ExprP
| EPequiv : ExprP -> ExprP -> ExprP
| EPand : ExprP -> ExprP -> ExprP
| EPor : ExprP -> ExprP -> ExprP
| EPneg : ExprP -> ExprP
| EPraw : Prop -> ExprP.
(** [int] to [ExprI] *)
Ltac i2ei trm :=
match constr:(trm) with
| 0 => constr:(EI0)
| 1 => constr:(EI1)
| 2 => constr:(EI2)
| 3 => constr:(EI3)
| ?x + ?y => let ex := i2ei x with ey := i2ei y in constr:(EIadd ex ey)
| ?x - ?y => let ex := i2ei x with ey := i2ei y in constr:(EIsub ex ey)
| ?x * ?y => let ex := i2ei x with ey := i2ei y in constr:(EImul ex ey)
| max ?x ?y => let ex := i2ei x with ey := i2ei y in constr:(EImax ex ey)
| - ?x => let ex := i2ei x in constr:(EIopp ex)
| ?x => constr:(EIraw x)
end
(** [Z] to [ExprZ] *)
with z2ez trm :=
match constr:(trm) with
| (?x + ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZadd ex ey)
| (?x - ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZsub ex ey)
| (?x * ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZmul ex ey)
| (Z.max ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EZmax ex ey)
| (- ?x)%Z => let ex := z2ez x in constr:(EZopp ex)
| i2z ?x => let ex := i2ei x in constr:(EZofI ex)
| ?x => constr:(EZraw x)
end.
(** [Prop] to [ExprP] *)
Ltac p2ep trm :=
match constr:(trm) with
| (?x <-> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPequiv ex ey)
| (?x -> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPimpl ex ey)
| (?x /\ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPand ex ey)
| (?x \/ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPor ex ey)
| (~ ?x) => let ex := p2ep x in constr:(EPneg ex)
| (eq (A:=Z) ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EPeq ex ey)
| (?x < ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPlt ex ey)
| (?x <= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPle ex ey)
| (?x > ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPgt ex ey)
| (?x >= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPge ex ey)
| ?x => constr:(EPraw x)
end.
(** [ExprI] to [int] *)
Fixpoint ei2i (e:ExprI) : int :=
match e with
| EI0 => 0
| EI1 => 1
| EI2 => 2
| EI3 => 3
| EIadd e1 e2 => (ei2i e1)+(ei2i e2)
| EIsub e1 e2 => (ei2i e1)-(ei2i e2)
| EImul e1 e2 => (ei2i e1)*(ei2i e2)
| EImax e1 e2 => max (ei2i e1) (ei2i e2)
| EIopp e => -(ei2i e)
| EIraw i => i
end.
(** [ExprZ] to [Z] *)
Fixpoint ez2z (e:ExprZ) : Z :=
match e with
| EZadd e1 e2 => ((ez2z e1)+(ez2z e2))%Z
| EZsub e1 e2 => ((ez2z e1)-(ez2z e2))%Z
| EZmul e1 e2 => ((ez2z e1)*(ez2z e2))%Z
| EZmax e1 e2 => Z.max (ez2z e1) (ez2z e2)
| EZopp e => (-(ez2z e))%Z
| EZofI e => i2z (ei2i e)
| EZraw z => z
end.
(** [ExprP] to [Prop] *)
Fixpoint ep2p (e:ExprP) : Prop :=
match e with
| EPeq e1 e2 => (ez2z e1) = (ez2z e2)
| EPlt e1 e2 => ((ez2z e1)<(ez2z e2))%Z
| EPle e1 e2 => ((ez2z e1)<=(ez2z e2))%Z
| EPgt e1 e2 => ((ez2z e1)>(ez2z e2))%Z
| EPge e1 e2 => ((ez2z e1)>=(ez2z e2))%Z
| EPimpl e1 e2 => (ep2p e1) -> (ep2p e2)
| EPequiv e1 e2 => (ep2p e1) <-> (ep2p e2)
| EPand e1 e2 => (ep2p e1) /\ (ep2p e2)
| EPor e1 e2 => (ep2p e1) \/ (ep2p e2)
| EPneg e => ~ (ep2p e)
| EPraw p => p
end.
(** [ExprI] (supposed under a [i2z]) to a simplified [ExprZ] *)
Fixpoint norm_ei (e:ExprI) : ExprZ :=
match e with
| EI0 => EZraw (0%Z)
| EI1 => EZraw (1%Z)
| EI2 => EZraw (2%Z)
| EI3 => EZraw (3%Z)
| EIadd e1 e2 => EZadd (norm_ei e1) (norm_ei e2)
| EIsub e1 e2 => EZsub (norm_ei e1) (norm_ei e2)
| EImul e1 e2 => EZmul (norm_ei e1) (norm_ei e2)
| EImax e1 e2 => EZmax (norm_ei e1) (norm_ei e2)
| EIopp e => EZopp (norm_ei e)
| EIraw i => EZofI (EIraw i)
end.
(** [ExprZ] to a simplified [ExprZ] *)
Fixpoint norm_ez (e:ExprZ) : ExprZ :=
match e with
| EZadd e1 e2 => EZadd (norm_ez e1) (norm_ez e2)
| EZsub e1 e2 => EZsub (norm_ez e1) (norm_ez e2)
| EZmul e1 e2 => EZmul (norm_ez e1) (norm_ez e2)
| EZmax e1 e2 => EZmax (norm_ez e1) (norm_ez e2)
| EZopp e => EZopp (norm_ez e)
| EZofI e => norm_ei e
| EZraw z => EZraw z
end.
(** [ExprP] to a simplified [ExprP] *)
Fixpoint norm_ep (e:ExprP) : ExprP :=
match e with
| EPeq e1 e2 => EPeq (norm_ez e1) (norm_ez e2)
| EPlt e1 e2 => EPlt (norm_ez e1) (norm_ez e2)
| EPle e1 e2 => EPle (norm_ez e1) (norm_ez e2)
| EPgt e1 e2 => EPgt (norm_ez e1) (norm_ez e2)
| EPge e1 e2 => EPge (norm_ez e1) (norm_ez e2)
| EPimpl e1 e2 => EPimpl (norm_ep e1) (norm_ep e2)
| EPequiv e1 e2 => EPequiv (norm_ep e1) (norm_ep e2)
| EPand e1 e2 => EPand (norm_ep e1) (norm_ep e2)
| EPor e1 e2 => EPor (norm_ep e1) (norm_ep e2)
| EPneg e => EPneg (norm_ep e)
| EPraw p => EPraw p
end.
Lemma norm_ei_correct (e:ExprI) : ez2z (norm_ei e) = i2z (ei2i e).
Proof.
induction e; simpl; i2z; auto; try congruence.
Qed.
Lemma norm_ez_correct (e:ExprZ) : ez2z (norm_ez e) = ez2z e.
Proof.
induction e; simpl; i2z; auto; try congruence; apply norm_ei_correct.
Qed.
Lemma norm_ep_correct (e:ExprP) : ep2p (norm_ep e) <-> ep2p e.
Proof.
induction e; simpl; rewrite ?norm_ez_correct; intuition.
Qed.
Lemma norm_ep_correct2 (e:ExprP) : ep2p (norm_ep e) -> ep2p e.
Proof.
intros; destruct (norm_ep_correct e); auto.
Qed.
Ltac i2z_refl :=
i2z_gen;
match goal with |- ?t =>
let e := p2ep t in
change (ep2p e); apply norm_ep_correct2; simpl
end.
(* i2z_refl can be replaced below by (simpl in *; i2z).
The reflexive version improves compilation of AVL files by about 15% *)
End MoreInt.
(** * An implementation of [Int] *)
(** It's always nice to know that our [Int] interface is realizable :-) *)
Module Z_as_Int <: Int.
Local Open Scope Z_scope.
Definition t := Z.
Definition _0 := 0.
Definition _1 := 1.
Definition _2 := 2.
Definition _3 := 3.
Definition add := Z.add.
Definition opp := Z.opp.
Definition sub := Z.sub.
Definition mul := Z.mul.
Definition max := Z.max.
Definition eqb := Z.eqb.
Definition ltb := Z.ltb.
Definition leb := Z.leb.
Definition eq_dec := Z.eq_dec.
Definition gt_le_dec i j : {i > j} + { i <= j }.
Proof.
generalize (Z.ltb_spec j i).
destruct (j <? i); [left|right]; inversion H; trivial.
now apply Z.lt_gt.
Defined.
Definition ge_lt_dec i j : {i >= j} + { i < j }.
Proof.
generalize (Z.ltb_spec i j).
destruct (i <? j); [right|left]; inversion H; trivial.
now apply Z.le_ge.
Defined.
Definition i2z : t -> Z := fun n => n.
Lemma i2z_eq n p : i2z n = i2z p -> n = p. Proof. trivial. Qed.
Lemma i2z_0 : i2z _0 = 0. Proof. reflexivity. Qed.
Lemma i2z_1 : i2z _1 = 1. Proof. reflexivity. Qed.
Lemma i2z_2 : i2z _2 = 2. Proof. reflexivity. Qed.
Lemma i2z_3 : i2z _3 = 3. Proof. reflexivity. Qed.
Lemma i2z_add n p : i2z (n + p) = i2z n + i2z p.
Proof. reflexivity. Qed.
Lemma i2z_opp n : i2z (- n) = - i2z n.
Proof. reflexivity. Qed.
Lemma i2z_sub n p : i2z (n - p) = i2z n - i2z p.
Proof. reflexivity. Qed.
Lemma i2z_mul n p : i2z (n * p) = i2z n * i2z p.
Proof. reflexivity. Qed.
Lemma i2z_max n p : i2z (max n p) = Z.max (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_eqb n p : eqb n p = Z.eqb (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_leb n p : leb n p = Z.leb (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_ltb n p : ltb n p = Z.ltb (i2z n) (i2z p).
Proof. reflexivity. Qed.
(** Compatibility notations for Coq v8.4 *)
Notation plus := add (only parsing).
Notation minus := sub (only parsing).
Notation mult := mul (only parsing).
End Z_as_Int.
|
// example from rapid protyping of digital systems book
// 2 circular tracks and 2 trains running on the track
// there is a switch that connect inner to outer tracks
// sensors there to notify when trains are nearing the
// switching point of track
// state machine tracks when the train need to stop
// before it can switch tracks
// force declartation of all types
`default_nettype none
`timescale 1 ps / 1 ps
module trainsim
(
input wire rst,
input wire clk,
input wire [4:0] sensor,
output reg [2:0] sw,
output reg [1:0] dira,
output reg [1:0] dirb
);
localparam ABOUT = 0;
localparam AIN = 1;
localparam BIN = 2;
localparam ASTOP = 3;
localparam BSTOP = 4;
reg [2:0] state;
wire [1:0] s12 = {sensor[0], sensor[1]};
wire [1:0] s13 = {sensor[0], sensor[2]};
wire [1:0] s24 = {sensor[1], sensor[3]};
always @ (posedge clk) begin
sw[2] = 0;
end
always @ (posedge clk or posedge rst) begin
if (rst)
state = ABOUT;
else
case (state)
ABOUT:
case (s12)
'b00: state = ABOUT;
'b01: state = BIN;
'b10: state = AIN;
'b11: state = AIN;
default: state = ABOUT;
endcase
AIN:
case (s24)
'b00: state = AIN;
'b01: state = ABOUT;
'b10: state = BSTOP;
'b11: state = ABOUT;
default: state = ABOUT;
endcase
BIN:
case (s13)
'b00: state = BIN;
'b01: state = ABOUT;
'b10: state = ASTOP;
'b11: state = ABOUT;
default: state = ABOUT;
endcase
ASTOP:
if (sensor[2])
state = AIN;
else
state = ASTOP;
BSTOP:
if (sensor[3])
state = BIN;
else
state = BSTOP;
default:
state = ABOUT;
endcase
end
always @ (state) begin
case (state)
ABOUT: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b01;
dirb = 'b01;
end
AIN: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b01;
dirb = 'b01;
end
BIN: begin
sw[0] = 1;
sw[1] = 1;
dira = 'b01;
dirb = 'b01;
end
ASTOP: begin
sw[0] = 1;
sw[1] = 1;
dira = 'b00;
dirb = 'b01;
end
BSTOP: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b01;
dirb = 'b00;
end
default: begin
sw[0] = 0;
sw[1] = 0;
dira = 'b00;
dirb = 'b00;
end
endcase
end
endmodule
// from http://www.fpga4fun.com/Counters3.html
module LFSR8_11D
(
input wire clk,
output reg [7:0] LFSR = 255
);
// modified feedback allows to reach 256 states instead of 255
wire feedback = LFSR[7] ^ (LFSR[6:0] == 7'b0000000);
always @(posedge clk) begin
LFSR[0] <= feedback;
LFSR[1] <= LFSR[0];
LFSR[2] <= LFSR[1] ^ feedback;
LFSR[3] <= LFSR[2] ^ feedback;
LFSR[4] <= LFSR[3] ^ feedback;
LFSR[5] <= LFSR[4];
LFSR[6] <= LFSR[5];
LFSR[7] <= LFSR[6];
end
endmodule
module trainsim_test();
reg rst, clk;
wire [7:0] rnd;
wire [4:0] sensor;
wire [2:0] sw;
wire [1:0] dira, dirb;
initial begin
clk = 0;
#5 rst = 1;
#1 rst = 0;
end
initial forever #0.5 clk = !clk;
assign sensor = rnd[4:0];
LFSR8_11D l(clk, rnd);
trainsim t(rst, clk, sensor, sw, dira, dirb);
endmodule
|
/*
* Generated by harness_gen.py
* From: picorv32_def.v
*/
module top(input wire clk, input wire stb, input wire di, output wire do);
localparam integer DIN_N = 101;
localparam integer DOUT_N = 307;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
picorv32 dut(
.clk(clk),
.resetn(din[0]),
.trap(dout[0]),
.mem_valid(dout[1]),
.mem_instr(dout[2]),
.mem_ready(din[1]),
.mem_addr(dout[34:3]),
.mem_wdata(dout[66:35]),
.mem_wstrb(dout[70:67]),
.mem_rdata(din[33:2]),
.mem_la_read(dout[71]),
.mem_la_write(dout[72]),
.mem_la_addr(dout[104:73]),
.mem_la_wdata(dout[136:105]),
.mem_la_wstrb(dout[140:137]),
.pcpi_valid(dout[141]),
.pcpi_insn(dout[173:142]),
.pcpi_rs1(dout[205:174]),
.pcpi_rs2(dout[237:206]),
.pcpi_wr(din[34]),
.pcpi_rd(din[66:35]),
.pcpi_wait(din[67]),
.pcpi_ready(din[68]),
.irq(din[100:69]),
.eoi(dout[269:238]),
.trace_valid(dout[270]),
.trace_data(dout[306:271])
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:31:27 03/28/2014
// Design Name:
// Module Name: sccpu_cpu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sccpu_cpu(
input clk,
input clrn,
output reg[31:0] pc,
output [31:0] inst,
output wire[31:0] dataout,result,d,
output zero,wreg,m2reg,
output wire[1:0] pcsource
);
wire [4:0] rs1,rs2,rd,rna,rnb,wn,sa;
wire [31:0] qa,qb,a,b;
wire sst,shift,aluimm,sext,wmem,wzero;
wire [1:0] adepend,bdepend,sdepend;
wire loaddepend;
wire[3:0] aluc;
wire [15:0] imme;
wire[31:0] inst_out;
wire[31:0] eximme,next_pc,ex_sa;
reg[31:0] clk_cnt;
wire ewreg,em2reg,eshift,ealuimm,ewmem,ewzero;
wire [1:0] eadepend,ebdepend,esdepend;
wire[3:0] ealuc;
wire[4:0] erd,esa;
wire[31:0] eqa,eqb,eeximme;
wire mwreg,mm2reg,mwmem;
wire[1:0] msdepend;
wire[4:0] mrd;
wire[31:0] mresult,mqb;
wire wwreg,wm2reg;
wire[4:0] wrd;
wire[31:0] wresult,wdataout;
wire[31:0] pre_d;
wire[31:0] m_data;
initial begin
pc = 0;
clk_cnt= 0;
end
IP_ROM InstMem(pc,inst_out);
dffinst ip(inst_out,clk,clrn,loaddepend,inst);
next_pc go_pc(inst,pcsource,clk,loaddepend,pc,next_pc);
always @(next_pc)
begin
pc <= next_pc;
end
assign rs1 = inst[20:16];
assign rs2 = inst[4:0];
assign rd = inst[25:21];
assign imme = inst[15:0];
assign sa = inst[20:16];
cu control_unit(inst,zero,rs1,rs2,rd,erd,mrd,ewreg,mwreg,em2reg,
wreg,sst,m2reg,shift,aluimm,sext,aluc,wmem,pcsource,adepend,bdepend,sdepend,loaddepend,wzero);
assign rna = rs1;
mux2x5 slct_rnb(rs2,rd,sst,rnb);
mux2x32 slct_d(wresult,wdataout,wm2reg,d);
assign wn = wrd;
dffd push_d(d,clk,clrn,pre_d);
regfile rf(rna,rnb,d,wn,wwreg,clk,clrn,qa,qb);
expand expand_imme(imme,sext,eximme);
diff_d2e push_d2e(
clk,clrn,
wreg,m2reg,shift,aluimm,wmem,wzero,aluc,rd,qa,qb,eximme,sa,adepend,bdepend,sdepend,
ewreg,em2reg,eshift,ealuimm,ewmem,ewzero,ealuc,erd,eqa,eqb,eeximme,esa,eadepend,ebdepend,esdepend
);
assign ex_sa = {{27{esa[4]}},esa[4:0]};
//mux2x32 slct_a(eqa,ex_sa,eshift,a);
//mux2x32 slct_b(eqb,eeximme,ealuimm,b);
mux4x32 slct_a(eqa,ex_sa,mresult,d,eadepend,a);
mux4x32 slct_b(eqb,eeximme,mresult,d,ebdepend,b);
alu alu_unit(a,b,ealuc,ewzero,zero,result);
diff_e2m push_e2m(
clk,clrn,
ewreg,em2reg,ewmem,erd,result,eqb,esdepend,
mwreg,mm2reg,mwmem,mrd,mresult,mqb,msdepend
);
mux4x32 slct_m_data(mqb,mqb,d,pre_d,msdepend,m_data);
IP_RAM DataMem(mwmem,mresult,m_data,clk,dataout);
diff_m2w push_m2w(
clk,clrn,
mwreg,mm2reg,mrd,mresult,dataout,
wwreg,wm2reg,wrd,wresult,wdataout
);
//ÒÔÏÂΪ²âÊÔÓÃ
always @(posedge clk) //¿ØÖÆʱÖÓÖÜÆÚÖ´ÐиöÊý
begin
clk_cnt = clk_cnt + 1;
if (clk_cnt==550)
$stop;
end
always @(inst) //ÈôÖ¸ÁîÈ«ÁãÔòÖÕÖ¹
begin
if (inst==0)
$stop;
end
endmodule
|
//
// Paul Gao 03/2019
//
// Input DDR PHY
//
// The output data is a 2x wide data bus synchronized to the posedge of clk_i
// The MSBs of the output data is the negedge registered data while the LSBs of the
// output data is the posedge registered data
// * Posedge (LSB) data received earlier in time than MSB data
//
// Note that input clock edges must be center-aligned to input data signals
// Need input delay constraint(s) to ensure clock and data delay are same
//
// Schematic and more information: (Google Doc)
// https://docs.google.com/document/d/1lmkOxvlAvxrk_MM5W8xv3ho2DS26xbOMTCqUIyS6di8/edit?ts=5cf76063#heading=h.o6ptt6mn49us
//
//
`include "bsg_defines.v"
module bsg_link_iddr_phy
#(parameter `BSG_INV_PARAM(width_p ))
(input clk_i
,input [width_p-1:0] data_i
,output [2*width_p-1:0] data_r_o
);
logic [2*width_p-1:0] data_rr;
logic [width_p-1:0] data_n_r, data_p_r;
assign data_r_o = data_rr;
always_ff @(posedge clk_i)
// First buffer posedge data into data_p_r
data_p_r <= data_i;
always_ff @(negedge clk_i)
// Then buffer negedge data into data_n_r
data_n_r <= data_i;
always_ff @(posedge clk_i)
// Finally output to the data_rr flop
// data_p_r occurs logically earlier in time than data_n_r
data_rr <= {data_n_r, data_p_r};
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_iddr_phy)
|
// file: Clock48MHZ.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____48.031______0.000______50.0______108.043_____75.988
// CLK_OUT2___190.625______0.000______50.0_______84.594_____75.988
// CLK_OUT3___101.667______0.000______50.0_______94.528_____75.988
// CLK_OUT4____14.806______0.000______50.0______133.516_____75.988
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clock48MHZ,clk_wiz_v3_6,{component_name=Clock48MHZ,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module Clock48MHZ
(// Clock in ports
input CLK_100,
// Clock out ports
output CLK_48,
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT4,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_100));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (15.250),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (31.750),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (8),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (15),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (103),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_48),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT1),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT2),
.I (clkout2));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkout3));
endmodule
|
//% @file sdm_adc_data_aurora_recv.v
//% @brief Receive external ADC and TMS_SDM data sent through aurora.
//% @author Yuan Mei
//%
//% The rate of ADC and TMS_SDM data words must be of fixed ratio relation.
//% @param[in] NCH_ADC total number of external ADC channels
//% @param[in] ADC_CYC # of CLK cycles per ADC data. Make sure this is an integer multiple of SDM_CYC.
//% @param[in] NCH_SDM total number of SDMs channels (each channel has 2 OUTs)
//% @param[in] SDM_CYC # of CLK cycles per SDM data
`timescale 1ns / 1ps
module sdm_adc_data_aurora_recv
#(
parameter NCH_ADC = 20,
parameter ADC_CYC = 20,
parameter NCH_SDM = 19,
parameter SDM_CYC = 4
)
(
input RESET,
input CLK,
input USER_CLK,
input [63:0] M_AXI_RX_TDATA,
input M_AXI_RX_TVALID,
output [511:0] DOUT,
output DOUT_VALID,
output reg FIFO_FULL
);
localparam ADC_SDM_CYC_RATIO = ADC_CYC / SDM_CYC;
localparam FIFO_DIN64_CYC = 9;
reg [ADC_SDM_CYC_RATIO*NCH_SDM*2 + NCH_ADC*16 - 1 : 0] sdm_adc_v;
reg sdm_adc_v_valid;
// aggregate data into sdm_adc_v
reg [3:0] cnt;
always @ (posedge USER_CLK or posedge RESET) begin
if (RESET) begin
sdm_adc_v <= 0;
sdm_adc_v_valid <= 0;
cnt <= 0;
end
else begin
sdm_adc_v_valid <= 0;
if (M_AXI_RX_TVALID) begin
cnt <= cnt + 1;
if (cnt >= FIFO_DIN64_CYC-1) begin
cnt <= 0;
end
sdm_adc_v[63*cnt +: 63] <= M_AXI_RX_TDATA[62:0];
if (M_AXI_RX_TDATA[63] == 1'b1) begin
cnt <= 0;
sdm_adc_v[63*cnt +: 6] <= M_AXI_RX_TDATA[5:0];
sdm_adc_v_valid <= 1;
end
end
end
end
assign DOUT[0 +: ADC_SDM_CYC_RATIO*NCH_SDM*2 + NCH_ADC*16] = sdm_adc_v;
assign DOUT[511 -: 2] = 2'b00;
assign DOUT_VALID = sdm_adc_v_valid;
endmodule // sdm_adc_data_aurora_recv
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:17:42 07/10/2015
// Design Name:
// Module Name: Test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Test
( input PixelClk2,
input VSync,
output reg [5:0] XOffsetData,
output reg [9:0] YOffsetData,
output reg OffsetWrite
);
integer StatusL1;
integer Xdir;
integer Ydir;
initial
begin
StatusL1 = 0;
XOffsetData = 0;
YOffsetData = 0;
OffsetWrite = 0;
Xdir = 1;
Ydir = 1;
end
always @(negedge PixelClk2)
begin
case(StatusL1)
0: begin
XOffsetData = 0;
YOffsetData = 0;
Xdir = 1;
Ydir = 1;
StatusL1 = 1;
end
1: begin
if (VSync == 1) StatusL1 = 2;
end
2: begin
if (VSync == 0) StatusL1 = 3;
end
3: begin
OffsetWrite = 1;
StatusL1 = 4;
end
4: begin
OffsetWrite = 0;
if (XOffsetData == 6'b111111) Xdir = -1;
else if (XOffsetData == 6'b000000) Xdir = 1;
else Xdir = Xdir;
if (YOffsetData == 10'b1111111111) Ydir = -1;
else if (YOffsetData == 10'b0000000000) Ydir = 1;
else Ydir = Ydir;
StatusL1 = 5;
end
5: begin
XOffsetData = XOffsetData + Xdir;
YOffsetData = YOffsetData + Ydir;
StatusL1 = 1;
end
6: begin
StatusL1 = 6;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21OI_1_V
`define SKY130_FD_SC_MS__A21OI_1_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21oi_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21OI_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_jp_sstl_bscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_jp_sstl_bscan(in ,update_dr ,mode_ctl ,shift_dr ,clock_dr ,
bsr_so ,out ,bsr_si );
output bsr_so ;
output out ;
input in ;
input update_dr ;
input mode_ctl ;
input shift_dr ;
input clock_dr ;
input bsr_si ;
wire net033 ;
wire net035 ;
wire net042 ;
wire update_q ;
bw_u1_muxi21_2x bs_mux (
.z (net033 ),
.d0 (in ),
.d1 (update_q ),
.s (net042 ) );
bw_u1_inv_2x ctl_inv2x (
.z (net042 ),
.a (net035 ) );
bw_io_jp_bs_baseblk bs_baseblk (
.upd_q (update_q ),
.bsr_si (bsr_si ),
.update_dr (update_dr ),
.clock_dr (clock_dr ),
.shift_dr (shift_dr ),
.bsr_so (bsr_so ),
.in (in ) );
bw_u1_inv_1x ctl_inv1x (
.z (net035 ),
.a (mode_ctl ) );
bw_u1_inv_5x out_inv5x (
.z (out ),
.a (net033 ) );
endmodule
|
module SSEG_Driver( clk, reset, data, sseg, an );
input wire clk;
input wire reset;
input wire[15:0] data;
output reg[6:0] sseg;
output reg[3:0] an;
wire[3:0] hex3,hex2,hex1,hex0;
assign hex3 = data[15:12];
assign hex2 = data[11:8];
assign hex1 = data[7:4];
assign hex0 = data[3:0];
localparam N = 18;
reg[N-1:0] q_reg;
wire[N-1:0] q_next;
reg[3:0] hex_in;
always@( posedge clk or posedge reset )
if( reset )
q_reg <= 0;
else
q_reg <= q_next;
assign q_next = q_reg + 1;
always@( * )
case( q_reg[N-1:N-2] )
2'b00:
begin
an = 4'b1110;
hex_in = hex0;
end
2'b01:
begin
an = 4'b1101;
hex_in = hex1;
end
2'b10:
begin
an = 4'b1011;
hex_in = hex2;
end
2'b11:
begin
an = 4'b0111;
hex_in = hex3;
end
endcase
always@( * )
begin
case( hex_in )
0 : sseg[6:0] = 7'b1000000; //'0'
1 : sseg[6:0] = 7'b1111001; //'1'
2 : sseg[6:0] = 7'b0100100; //'2'
3 : sseg[6:0] = 7'b0110000; //'3'
4 : sseg[6:0] = 7'b0011001; //'4'
5 : sseg[6:0] = 7'b0010010; //'5'
6 : sseg[6:0] = 7'b0000010; //'6'
7 : sseg[6:0] = 7'b1111000; //'7'
8 : sseg[6:0] = 7'b0000000; //'8'
9 : sseg[6:0] = 7'b0010000; //'9'
'hA : sseg[6:0] = 7'b0001000; //'A'
'hB : sseg[6:0] = 7'b0000011; //'b'
'hC : sseg[6:0] = 7'b1000110; //'C'
'hD : sseg[6:0] = 7'b0100001; //'d'
'hE : sseg[6:0] = 7'b0000110; //'E'
'hF : sseg[6:0] = 7'b0001110; //'F'
default : sseg[6:0] = 7'b1111111;
endcase
end
endmodule
|
`timescale 1 ns / 100 ps
module mem2serial_tb ();
reg reset;
reg clock;
reg empty;
wire read_clock_enable;
reg [47:0] read_data;
wire uart_clock_enable;
reg uart_ready;
wire [7:0] uart_data;
reg read_clock;
mem2serial MEM_SERIAL(
.reset(reset),
.clock(clock),
.read_empty(empty),
.read_clock_enable(read_clock_enable),
.read_data(read_data),
.uart_clock_enable(uart_clock_enable),
.uart_ready(uart_ready),
.uart_data(uart_data));
initial begin
$dumpfile ("mem2serial_tb.vcd");
$dumpvars (1, mem2serial_tb);
#1;
read_data = 48'h0;
empty = 1;
clock = 0;
reset = 0;
uart_ready = 0;
#1;
clock = 1;
#1;
clock = 0;
#1;
reset = 1;
#1;
clock = 1;
#1;
// test if data read when ~uart_ready but it should not read more than
clock = 0;
empty = 0;
read_data = 48'h123456789a;
uart_ready = 0;
#1;
clock = 1;
#1;
clock = 0;
read_data = 48'h0;
// it should disable read_clock_enable
if (read_clock_enable == 'b1) begin
$display("read_clock_enable still high. Expected: low");
$stop;
end
// ensure no data will read when uart_ready + empty
// check if data successful read when uart_ready
// ensure nodata will read when ~uart_ready + ~empty
$finish;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_sctrdq_fifo.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_sctrdq_fifo - SCTRDQ ratio synchronous fifo queue implementation.
// _____________________________________________________________________________
//
// Description:
// The implementation uses recirculating read and write pointers to the RAM.
//
// Interface:
// enqueue - Add the entry composed 'data' to the top-of-queue. Should not
// be issued if 'full' is asserted.
//
// din - The data value to put onto the fifo.
//
// full - No more available entries in the fifo.
//
// dequeue - Remove the top entry from the fifo exposing the next entry if
// available. Should not be issued if 'empty' is asserted.
//
// dout - The data at the top of the fifo. Must be qualified with 'empty'.
//
// empty - No entries currently in the fifo.
// _____________________________________________________________________________
`include "sys.h"
module jbi_sctrdq_fifo (/*AUTOARG*/
// Outputs
full, dout, empty,
// Inputs
enqueue, din, cclk, tx_en, crst_l, dequeue, clk, rst_l, hold,
testmux_sel, rst_tri_en, arst_l
);
// Enqueue port.
input enqueue;
input [137:0] din;
output full;
input cclk;
input tx_en;
input crst_l;
// Dequeue port.
input dequeue;
output [137:0] dout;
output empty;
input clk;
input rst_l;
// Misc.
input hold;
input testmux_sel; // Memory and ATPG test mode signal.
input rst_tri_en;
input arst_l;
// Wires and Regs.
wire rd_enb;
wire [4:0] wr_addr_presync, wr_addr_sync, rd_addr_presync, rd_addr_sync;
// Write Address pointer.
// Points to the next available write entry. This is the write address about to be registered into the memory.
wire [4:0] ram_wr_addr_m1;
wire [4:0] next_ram_wr_addr_m1 = (enqueue)? ram_wr_addr_m1+1'b1: ram_wr_addr_m1;
dffrl_ns #(5) ram_wr_addr_m1_reg (.din(next_ram_wr_addr_m1), .q(ram_wr_addr_m1), .rst_l(crst_l), .clk(cclk));
// Read Address pointer.
// Points to the top-of-queue entry. This is the read address currently in the memory.
wire [4:0] ram_rd_addr; // Points to the top-of-queue entry.
wire [4:0] next_ram_rd_addr = (dequeue)? ram_rd_addr+1'b1: ram_rd_addr;
dffrl_ns #(5) ram_rd_addr_reg (.din(next_ram_rd_addr), .q(ram_rd_addr), .rst_l(rst_l), .clk(clk));
wire [4:0] ram_rd_addr_m1 = next_ram_rd_addr[4:0];
// Create fifo status bits 'full' and 'empty'.
//
// Full status.
assign full = (rd_addr_sync[3:0] == ram_wr_addr_m1[3:0]) && (rd_addr_sync[4] != ram_wr_addr_m1[4]);
//
// Empty status.
// (Needs to delay 1-cycle when going from empty to not empty (push to an empty fifo)
// since the memory read enable signals are registered and take a cycle to produce the data).
assign empty = (ram_rd_addr[4:0] == wr_addr_sync[4:0]) || !rd_enb;
// Register Array.
wire [21:0] unused;
wire rd_enb_m1 = (ram_rd_addr_m1[4:0] != wr_addr_sync[4:0]);
jbi_1r1w_16x160 array_scan (
// Write port.
.wrclk (cclk),
.wr_en (enqueue),
.wr_adr (ram_wr_addr_m1[3:0]),
.din ({ 22'b0, din }),
// Read port.
.rdclk (clk),
.read_en (rd_enb_m1),
.rd_adr (ram_rd_addr_m1[3:0]),
.dout ({ unused[21:0], dout }),
// Other.
.rst_l (arst_l),
.hold (hold),
.testmux_sel (testmux_sel),
.rst_tri_en (rst_tri_en)
);
// Signal staging and synchronizers.
//
// 'rd_enb' pipeline.
wire next_rd_enb = rd_enb_m1;
dff_ns rd_enb_reg (.din(next_rd_enb), .q(rd_enb), .clk(clk));
// 'ram_wr_addr' synchronizer (Cmp -> JBus).
wire [4:0] next_wr_addr_presync = ram_wr_addr_m1;
wire wr_addr_presync_en = tx_en;
dffe_ns #(5) wr_addr_presync_reg (.din(next_wr_addr_presync), .en(wr_addr_presync_en), .q(wr_addr_presync), .clk(cclk));
//
wire [4:0] next_wr_addr_sync = wr_addr_presync;
dff_ns #(5) wr_addr_sync_reg (.din(next_wr_addr_sync), .q(wr_addr_sync), .clk(clk));
// 'ram_rd_addr' synchronizer (JBus -> Cmp).
wire [4:0] next_rd_addr_presync = ram_rd_addr;
dff_ns #(5) rd_addr_presync_reg (.din(next_rd_addr_presync), .q(rd_addr_presync), .clk(clk));
//
wire [4:0] next_rd_addr_sync = rd_addr_presync;
dff_ns #(5) rd_addr_sync_reg (.din(next_rd_addr_sync), .q(rd_addr_sync), .clk(cclk));
// simtech modcovoff -bpen
// synopsys translate_off
// Check that no dequeue is done when empty.
always @(posedge clk) begin
if (dequeue && empty) begin
$dispmon ("jbi_mout_jbi_sctrdq_fifo", 49, "%d %m: ERROR - Attempt made to dequeue an empty queue.", $time);
end
end
// Check that no enqueue is done when full.
always @(posedge cclk) begin
if (enqueue && full) begin
$dispmon ("jbi_mout_jbi_sctrdq_fifo", 49, "%d %m: ERROR - Attempt made to enqueue a full queue.", $time);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("../../../include" "../../common/rtl")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-module-parents:("jbi_sctrdq")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_select.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Based on granta_r and grantc_r, this module selects a
// row and column command from the request information
// provided by the bank machines.
//
// Depending on address mode configuration, nCL and nCWL, a column
// command pipeline of up to three states will be created.
`timescale 1 ps / 1 ps
module arb_select #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter nSLOTS = 2,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(
// Outputs
output wire col_periodic_rd,
output wire [RANK_WIDTH-1:0] col_ra,
output wire [BANK_WIDTH-1:0] col_ba,
output wire [ROW_WIDTH-1:0] col_a,
output wire col_rmw,
output wire col_rd_wr,
output wire col_size,
output wire [ROW_WIDTH-1:0] col_row,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output wire [5:0] mc_data_offset,
output wire [1:0] mc_cas_slot,
output wire [RANK_WIDTH:0] io_config,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [RANK_VECT_INDX:0] req_rank_r,
input [BANK_VECT_INDX:0] req_bank_r,
input [nBANK_MACHS-1:0] req_ras,
input [nBANK_MACHS-1:0] req_cas,
input [nBANK_MACHS-1:0] req_wr_r,
input [nBANK_MACHS-1:0] grant_row_r,
input [nBANK_MACHS-1:0] grant_pre_r,
input [ROW_VECT_INDX:0] row_addr,
input [nBANK_MACHS-1:0] row_cmd_wr,
input insert_maint_r1,
input maint_zq_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input [nBANK_MACHS-1:0] req_periodic_rd_r,
input [nBANK_MACHS-1:0] req_size_r,
input [nBANK_MACHS-1:0] rd_wr_r,
input [ROW_VECT_INDX:0] req_row_r,
input [ROW_VECT_INDX:0] col_addr,
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,
input [nBANK_MACHS-1:0] grant_col_r,
input [nBANK_MACHS-1:0] grant_col_wr,
input [5:0] calib_rddata_offset,
input [5:0] col_channel_offset,
input force_io_config_rd_r1,
input [nBANK_MACHS-1:0] grant_config_r,
input io_config_strobe,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
input send_cmd1_col,
input send_cmd1_pre,
input send_cmd2_col,
input send_cmd2_pre,
input send_cmd3_col,
input send_cmd3_pre,
input send_cmd0_col,
input send_cmd1_row,
input sent_col,
input cs_en0,
input cs_en1,
input cs_en2,
input cs_en3
);
localparam OUT_CMD_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + 1 + 1 + 1;
reg col_rd_wr_ns;
reg col_rd_wr_r;
// Disable CKE toggle
assign mc_aux_out0[0] = 1'b0;
assign mc_aux_out0[2] = 1'b0;
// Disable ODT & CKE toggle enable high bits
assign mc_aux_out1 = 4'b0;
// implement PHY command word
assign mc_cmd[0] = sent_col;
assign mc_cmd[1] = sent_col & col_rd_wr_ns;
assign mc_cmd[2] = ~sent_col;
// generate data offset
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
calib_rddata_offset + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_cas_slot = col_channel_offset[1:0];
// Based on arbitration results, select the row and column commands.
integer i;
reg [OUT_CMD_WIDTH-1:0] row_cmd_ns;
generate
begin : row_mux
reg [OUT_CMD_WIDTH-1:0] row_cmd_r = {OUT_CMD_WIDTH {1'b0}};
wire [OUT_CMD_WIDTH-1:0] maint_cmd =
{maint_rank_r, // maintenance rank
row_cmd_r[15+:(BANK_WIDTH+ROW_WIDTH-11)],
// bank plus upper address bits
1'b0, // A10 = 0 for ZQCS
row_cmd_r[3+:10], // address bits [9:0]
(maint_zq_r ? 3'b110 : 3'b001) // ZQ or REFRESH
};
always @(/*AS*/grant_row_r or insert_maint_r1 or maint_cmd
or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or row_cmd_r or row_cmd_wr or rst)
begin
row_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: insert_maint_r1
? maint_cmd
: row_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_row_r[i])
row_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
if (~((nCK_PER_CLK == 2) && (ADDR_CMD_MODE != "2T")))
always @(posedge clk) row_cmd_r <= #TCQ row_cmd_ns;
end // row_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] pre_cmd_ns;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_mux
reg [OUT_CMD_WIDTH-1:0] pre_cmd_r = {OUT_CMD_WIDTH {1'b0}};
always @(/*AS*/grant_pre_r or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or pre_cmd_r or row_cmd_wr or rst)
begin
pre_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: pre_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_pre_r[i])
pre_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
end // pre_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] col_cmd_ns;
generate
begin : col_mux
reg col_periodic_rd_ns;
reg col_periodic_rd_r;
reg [OUT_CMD_WIDTH-1:0] col_cmd_r = {OUT_CMD_WIDTH {1'b0}};
reg col_rmw_ns;
reg col_rmw_r;
reg col_size_ns;
reg col_size_r;
reg [ROW_WIDTH-1:0] col_row_ns;
reg [ROW_WIDTH-1:0] col_row_r;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_r;
always @(col_addr or col_cmd_r or col_data_buf_addr_r
or col_periodic_rd_r or col_rmw_r or col_row_r
or col_size_r or grant_col_r or rd_wr_r or req_bank_r
or req_data_buf_addr_r or req_periodic_rd_r
or req_rank_r or req_row_r or req_size_r or req_wr_r
or rst or col_rd_wr_r)
begin
col_periodic_rd_ns = ~rst && col_periodic_rd_r;
col_cmd_ns = {(rst ? {RANK_WIDTH{1'b0}}
: col_cmd_r[(OUT_CMD_WIDTH-1)-:RANK_WIDTH]),
((rst && ECC != "OFF")
? {OUT_CMD_WIDTH-3-RANK_WIDTH{1'b0}}
: col_cmd_r[3+:(OUT_CMD_WIDTH-3-RANK_WIDTH)]),
(rst ? 3'b0 : col_cmd_r[2:0])};
col_rmw_ns = col_rmw_r;
col_size_ns = rst ? 1'b0 : col_size_r;
col_row_ns = col_row_r;
col_rd_wr_ns = col_rd_wr_r;
col_data_buf_addr_ns = col_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_r[i]) begin
col_periodic_rd_ns = req_periodic_rd_r[i];
col_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
col_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
1'b1,
1'b0,
rd_wr_r[i]};
col_rmw_ns = req_wr_r[i] && rd_wr_r[i];
col_size_ns = req_size_r[i];
col_row_ns = req_row_r[(ROW_WIDTH*i)+:ROW_WIDTH];
col_rd_wr_ns = rd_wr_r[i];
col_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
end // always @ (...
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_data_addr_off
assign col_wr_data_buf_addr = col_data_buf_addr_ns;
end
else begin : early_wr_data_addr_on
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(/*AS*/col_wr_data_buf_addr_r or grant_col_wr
or req_data_buf_addr_r) begin
col_wr_data_buf_addr_ns = col_wr_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_wr[i])
col_wr_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr_ns;
assign col_wr_data_buf_addr = col_wr_data_buf_addr_ns;
end
always @(posedge clk) col_periodic_rd_r <= #TCQ col_periodic_rd_ns;
always @(posedge clk) col_rmw_r <= #TCQ col_rmw_ns;
always @(posedge clk) col_size_r <= #TCQ col_size_ns;
always @(posedge clk) col_data_buf_addr_r <=
#TCQ col_data_buf_addr_ns;
if (ECC != "OFF") begin
always @(posedge clk) col_cmd_r <= #TCQ col_cmd_ns;
always @(posedge clk) col_row_r <= #TCQ col_row_ns;
end
always @(posedge clk) col_rd_wr_r <= #TCQ col_rd_wr_ns;
assign col_periodic_rd = col_periodic_rd_ns;
assign col_ra = col_cmd_ns[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_ns[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_ns[3+:ROW_WIDTH];
assign col_rmw = col_rmw_ns;
assign col_rd_wr = col_rd_wr_ns;
assign col_size = col_size_ns;
assign col_row = col_row_ns;
assign col_data_buf_addr = col_data_buf_addr_ns;
end // col_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd0;
always @(/*AS*/col_cmd_ns or row_cmd_ns or send_cmd0_col) begin
cmd0 = row_cmd_ns;
if (send_cmd0_col) cmd0 = col_cmd_ns;
end
reg [OUT_CMD_WIDTH-1:0] cmd1 = {OUT_CMD_WIDTH{1'b1}};
generate
if ((nCK_PER_CLK == 2) || (nCK_PER_CLK == 4))
always @(col_cmd_ns or row_cmd_ns or pre_cmd_ns or send_cmd1_row or send_cmd1_pre) begin
cmd1 = col_cmd_ns;
if (send_cmd1_row) cmd1 = row_cmd_ns;
if (send_cmd1_pre) cmd1 = pre_cmd_ns;
end
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd2 = {OUT_CMD_WIDTH{1'b1}};
reg [OUT_CMD_WIDTH-1:0] cmd3 = {OUT_CMD_WIDTH{1'b1}};
generate
if (nCK_PER_CLK == 4)
always @(col_cmd_ns or pre_cmd_ns or send_cmd2_col or send_cmd3_col) begin
cmd2 = pre_cmd_ns;
cmd3 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd2_col) cmd2 = col_cmd_ns;
if (send_cmd3_col) cmd3 = col_cmd_ns;
end
endgenerate
// Output command bus 0.
wire [RANK_WIDTH-1:0] ra0;
// assign address
assign {ra0, mc_bank[BANK_WIDTH-1:0], mc_address[ROW_WIDTH-1:0]} =
cmd0[OUT_CMD_WIDTH-1:3]; // omit RAS, CAS, WE
// assign control. issue true NOOP when CS disabled.
assign {mc_ras_n[0], mc_cas_n[0], mc_we_n[0]} = cs_en0 ? cmd0[2:0] : 3'b111;
// Output command bus 1.
wire [RANK_WIDTH-1:0] ra1;
// assign address
assign {ra1, mc_bank[2*BANK_WIDTH-1:BANK_WIDTH], mc_address[2*ROW_WIDTH-1:ROW_WIDTH]} =
cmd1[OUT_CMD_WIDTH-1:3]; // omit RAS, CAS, WE
// assign control. issue true NOOP when CS disabled.
assign {mc_ras_n[1], mc_cas_n[1], mc_we_n[1]} = cs_en1 ? cmd1[2:0] : 3'b111;
wire [RANK_WIDTH-1:0] ra2;
wire [RANK_WIDTH-1:0] ra3;
generate
if(nCK_PER_CLK == 4) begin
// Output command bus 2.
// assign address
assign {ra2, mc_bank[3*BANK_WIDTH-1:2*BANK_WIDTH], mc_address[3*ROW_WIDTH-1:2*ROW_WIDTH]} =
cmd2[OUT_CMD_WIDTH-1:3]; // omit RAS, CAS, WE
// assign control. issue true NOOP when CS disabled.
assign {mc_ras_n[2], mc_cas_n[2], mc_we_n[2]} = cs_en2 ? cmd2[2:0] : 3'b111;
// Output command bus 3.
// assign address
assign {ra3, mc_bank[4*BANK_WIDTH-1:3*BANK_WIDTH], mc_address[4*ROW_WIDTH-1:3*ROW_WIDTH]} =
cmd3[OUT_CMD_WIDTH-1:3]; // omit RAS, CAS, WE
// assign control. issue true NOOP when CS disabled.
assign {mc_ras_n[3], mc_cas_n[3], mc_we_n[3]} = cs_en3 ? cmd3[2:0] : 3'b111;
end
endgenerate
// Output cs busses.
localparam ONE = {nCS_PER_RANK{1'b1}};
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] cs_one_hot =
{{CS_WIDTH{1'b0}},ONE};
assign mc_cs_n[CS_WIDTH*nCS_PER_RANK -1 :0 ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra0)) | {CS_WIDTH*nCS_PER_RANK{~cs_en0}})};
assign mc_cs_n[2*CS_WIDTH*nCS_PER_RANK -1 : CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra1)) | {CS_WIDTH*nCS_PER_RANK{~cs_en1}})};
generate
if(nCK_PER_CLK == 4) begin
assign mc_cs_n[3*CS_WIDTH*nCS_PER_RANK -1 :2*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra2)) | {CS_WIDTH*nCS_PER_RANK{~cs_en2}})};
assign mc_cs_n[4*CS_WIDTH*nCS_PER_RANK -1 :3*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra3)) | {CS_WIDTH*nCS_PER_RANK{~cs_en3}})};
end
endgenerate
// Output io_config info.
reg [RANK_WIDTH:0] io_config_ns;
reg [RANK_WIDTH:0] io_config_r;
always @(/*AS*/force_io_config_rd_r1 or grant_config_r
or io_config_r or io_config_strobe or rd_wr_r or req_rank_r
or rst) begin
if (rst) io_config_ns = {RANK_WIDTH{1'b0}};
else begin
io_config_ns = io_config_r;
if (io_config_strobe)
if (force_io_config_rd_r1) io_config_ns =
{1'b0, io_config_r[RANK_WIDTH-1:0]};
else
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_config_r[i]) io_config_ns =
{~rd_wr_r[i], req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH]};
end // else: !if(rst)
end
always @(posedge clk) io_config_r <= #TCQ io_config_ns;
assign io_config = io_config_ns;
// Generate ODT signals.
wire [CS_WIDTH-1:0] col_ra_one_hot = cs_one_hot << col_ra;
wire slot_0_select = (nSLOTS == 1) ? |(col_ra_one_hot & slot_0_present)
: (slot_0_present[2] & slot_0_present[0]) ?
|(col_ra_one_hot[CS_WIDTH-1:0] & {slot_0_present[2],
slot_0_present[0]}) : (slot_0_present[0])?
col_ra_one_hot[0] : 1'b0;
wire slot_0_read = slot_0_select && col_rd_wr_ns;
wire slot_0_write = slot_0_select && ~col_rd_wr_ns;
reg [1:0] slot_1_population = 2'b0;
reg[1:0] slot_0_population;
always @(/*AS*/slot_0_present) begin
slot_0_population = 2'b0;
for (i=0; i<8; i=i+1)
if (~slot_0_population[1])
if (slot_0_present[i] == 1'b1) slot_0_population =
slot_0_population + 2'b1;
end
// ODT on in slot 0 for writes to slot 0 (and R/W to slot 1 for DDR3)
wire slot_0_odt = (DRAM_TYPE == "DDR3") ? ~slot_0_read : slot_0_write;
assign mc_aux_out0[1] = slot_0_odt & sent_col; // Only send for COL cmds
generate
if (nSLOTS > 1) begin : slot_1_configured
wire slot_1_select = (slot_1_present[3] & slot_1_present[1])?
|({col_ra_one_hot[slot_0_population+1],
col_ra_one_hot[slot_0_population]}) :
(slot_1_present[1]) ? col_ra_one_hot[slot_0_population] :1'b0;
wire slot_1_read = slot_1_select && col_rd_wr_ns;
wire slot_1_write = slot_1_select && ~col_rd_wr_ns;
// ODT on in slot 1 for writes to slot 1 (and R/W to slot 0 for DDR3)
wire slot_1_odt = (DRAM_TYPE == "DDR3") ? ~slot_1_read : slot_1_write;
assign mc_aux_out0[3] = slot_1_odt & sent_col; // Only send for COL cmds
end // if (nSLOTS > 1)
else begin
// Disable slot 1 ODT when not present
assign mc_aux_out0[3] = 1'b0;
end // else: !if(nSLOTS > 1)
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_EP_MEM_ACCESS.v
// Version : 2.4
//--
//-- Description: Endpoint Memory Access Unit. This module provides access functions
//-- to the Endpoint memory aperture.
//--
//-- Read Access: Module returns data for the specifed address and
//-- byte enables selected.
//--
//-- Write Access: Module accepts data, byte enables and updates
//-- data when write enable is asserted. Modules signals write busy
//-- when data write is in progress.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
`define TCQ 1
`define PIO_MEM_ACCESS_WR_RST 3'b000
`define PIO_MEM_ACCESS_WR_WAIT 3'b001
`define PIO_MEM_ACCESS_WR_READ 3'b010
`define PIO_MEM_ACCESS_WR_WRITE 3'b100
module PIO_EP_MEM_ACCESS (
clk,
rst_n,
// Read Access
rd_addr_i, // I [10:0]
rd_be_i, // I [3:0]
rd_data_o, // O [31:0]
// Write Access
wr_addr_i, // I [10:0]
wr_be_i, // I [7:0]
wr_data_i, // I [31:0]
wr_en_i, // I
wr_busy_o // O
);
input clk;
input rst_n;
// * Read Port
input [10:0] rd_addr_i;
input [3:0] rd_be_i;
output [31:0] rd_data_o;
// * Write Port
input [10:0] wr_addr_i;
input [7:0] wr_be_i;
input [31:0] wr_data_i;
input wr_en_i;
output wr_busy_o;
wire [31:0] rd_data_o;
reg [31:0] rd_data_raw_o;
wire [31:0] rd_data0_o, rd_data1_o, rd_data2_o, rd_data3_o;
wire wr_busy_o;
reg write_en;
reg [31:0] post_wr_data;
reg [31:0] w_pre_wr_data;
reg [2:0] wr_mem_state;
reg [31:0] pre_wr_data;
wire [31:0] w_pre_wr_data0;
wire [31:0] w_pre_wr_data1;
wire [31:0] w_pre_wr_data2;
wire [31:0] w_pre_wr_data3;
reg [31:0] pre_wr_data0_q, pre_wr_data1_q, pre_wr_data2_q, pre_wr_data3_q;
reg [31:0] DW0, DW1, DW2;
// ** Memory Write Process
// * Extract current data bytes. These need to be swizzled
// * BRAM storage format :
// * data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
wire [7:0] w_pre_wr_data_b3 = pre_wr_data[31:24];
wire [7:0] w_pre_wr_data_b2 = pre_wr_data[23:16];
wire [7:0] w_pre_wr_data_b1 = pre_wr_data[15:08];
wire [7:0] w_pre_wr_data_b0 = pre_wr_data[07:00];
// * Extract new data bytes from payload
// * TLP Payload format :
// * data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
wire [7:0] w_wr_data_b3 = wr_data_i[07:00];
wire [7:0] w_wr_data_b2 = wr_data_i[15:08];
wire [7:0] w_wr_data_b1 = wr_data_i[23:16];
wire [7:0] w_wr_data_b0 = wr_data_i[31:24];
always @(posedge clk or negedge rst_n) begin
if ( !rst_n ) begin
pre_wr_data <= 32'b0;
post_wr_data <= 32'b0;
pre_wr_data <= 32'b0;
write_en <= 1'b0;
pre_wr_data0_q <= 32'b0;
pre_wr_data1_q <= 32'b0;
pre_wr_data2_q <= 32'b0;
pre_wr_data3_q <= 32'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
end else begin
case ( wr_mem_state )
`PIO_MEM_ACCESS_WR_RST : begin
if (wr_en_i) begin // read state
wr_mem_state <= `PIO_MEM_ACCESS_WR_WAIT; //Pipelining happens in RAM's internal output reg.
end else begin
write_en <= 1'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
end
end
`PIO_MEM_ACCESS_WR_WAIT : begin
// * Pipeline B port data before processing. Virtex 5 Block RAMs have internal
// output register enabled.
//pre_wr_data0_q <= w_pre_wr_data0;
// pre_wr_data1_q <= w_pre_wr_data1;
// pre_wr_data2_q <= w_pre_wr_data2;
// pre_wr_data3_q <= w_pre_wr_data3;
write_en <= 1'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_READ ;
end
`PIO_MEM_ACCESS_WR_READ : begin
// * Now save the selected BRAM B port data out
pre_wr_data <= w_pre_wr_data;
write_en <= 1'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_WRITE;
end
`PIO_MEM_ACCESS_WR_WRITE : begin
// * Merge new enabled data and write target BlockRAM location
post_wr_data <= {{wr_be_i[3] ? w_wr_data_b3 : w_pre_wr_data_b3},
{wr_be_i[2] ? w_wr_data_b2 : w_pre_wr_data_b2},
{wr_be_i[1] ? w_wr_data_b1 : w_pre_wr_data_b1},
{wr_be_i[0] ? w_wr_data_b0 : w_pre_wr_data_b0}};
write_en <= 1'b1;
wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
end
endcase
end
end
// * Write controller busy
assign wr_busy_o = wr_en_i | (wr_mem_state != `PIO_MEM_ACCESS_WR_RST);
// * Select BlockRAM output based on higher 2 address bits
always @* // (wr_addr_i or pre_wr_data0_q or pre_wr_data1_q or pre_wr_data2_q or pre_wr_data3_q) begin
begin
case ({wr_addr_i[10:9]}) // synthesis parallel_case full_case
2'b00 : w_pre_wr_data = w_pre_wr_data0;
2'b01 : w_pre_wr_data = w_pre_wr_data1;
2'b10 : w_pre_wr_data = w_pre_wr_data2;
2'b11 : w_pre_wr_data = w_pre_wr_data3;
endcase
end
// * Memory Read Controller
wire rd_data0_en = {rd_addr_i[10:9] == 2'b00};
wire rd_data1_en = {rd_addr_i[10:9] == 2'b01};
wire rd_data2_en = {rd_addr_i[10:9] == 2'b10};
wire rd_data3_en = {rd_addr_i[10:9] == 2'b11};
always @(rd_addr_i or rd_data0_o or rd_data1_o or rd_data2_o or rd_data3_o)
begin
case ({rd_addr_i[10:9]}) // synthesis parallel_case full_case
2'b00 : rd_data_raw_o = rd_data0_o;
2'b01 : rd_data_raw_o = rd_data1_o;
2'b10 : rd_data_raw_o = rd_data2_o;
2'b11 : rd_data_raw_o = rd_data3_o;
endcase
end
// Handle Read byte enables
assign rd_data_o = {{rd_be_i[0] ? rd_data_raw_o[07:00] : 8'h0},
{rd_be_i[1] ? rd_data_raw_o[15:08] : 8'h0},
{rd_be_i[2] ? rd_data_raw_o[23:16] : 8'h0},
{rd_be_i[3] ? rd_data_raw_o[31:24] : 8'h0}};
EP_MEM EP_MEM (
.clk_i(clk),
.a_rd_a_i_0(rd_addr_i[8:0]), // I [8:0]
.a_rd_en_i_0(rd_data0_en), // I [1:0]
.a_rd_d_o_0(rd_data0_o), // O [31:0]
.b_wr_a_i_0(wr_addr_i[8:0]), // I [8:0]
.b_wr_d_i_0(post_wr_data), // I [31:0]
.b_wr_en_i_0({write_en & (wr_addr_i[10:9] == 2'b00)}), // I
.b_rd_d_o_0(w_pre_wr_data0[31:0]), // O [31:0]
.b_rd_en_i_0({wr_addr_i[10:9] == 2'b00}), // I
.a_rd_a_i_1(rd_addr_i[8:0]), // I [8:0]
.a_rd_en_i_1(rd_data1_en), // I [1:0]
.a_rd_d_o_1(rd_data1_o), // O [31:0]
.b_wr_a_i_1(wr_addr_i[8:0]), // [8:0]
.b_wr_d_i_1(post_wr_data), // [31:0]
.b_wr_en_i_1({write_en & (wr_addr_i[10:9] == 2'b01)}), // I
.b_rd_d_o_1(w_pre_wr_data1[31:0]), // [31:0]
.b_rd_en_i_1({wr_addr_i[10:9] == 2'b01}), // I
.a_rd_a_i_2(rd_addr_i[8:0]), // I [8:0]
.a_rd_en_i_2(rd_data2_en), // I [1:0]
.a_rd_d_o_2(rd_data2_o), // O [31:0]
.b_wr_a_i_2(wr_addr_i[8:0]), // I [8:0]
.b_wr_d_i_2(post_wr_data), // I [31:0]
.b_wr_en_i_2({write_en & (wr_addr_i[10:9] == 2'b10)}), // I
.b_rd_d_o_2(w_pre_wr_data2[31:0]), // I [31:0]
.b_rd_en_i_2({wr_addr_i[10:9] == 2'b10}), // I
.a_rd_a_i_3(rd_addr_i[8:0]), // [8:0]
.a_rd_en_i_3(rd_data3_en), // [1:0]
.a_rd_d_o_3(rd_data3_o), // O [31:0]
.b_wr_a_i_3(wr_addr_i[8:0]), // I [8:0]
.b_wr_d_i_3(post_wr_data), // I [31:0]
.b_wr_en_i_3({write_en & (wr_addr_i[10:9] == 2'b11)}), // I
.b_rd_d_o_3(w_pre_wr_data3[31:0]), // I [31:0]
.b_rd_en_i_3({wr_addr_i[10:9] == 2'b11}) // I
);
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(wr_mem_state)
begin
case (wr_mem_state)
`PIO_MEM_ACCESS_WR_RST : state_ascii <= #`TCQ "PIO_MEM_WR_RST";
`PIO_MEM_ACCESS_WR_WAIT : state_ascii <= #`TCQ "PIO_MEM_WR_WAIT";
`PIO_MEM_ACCESS_WR_READ : state_ascii <= #`TCQ "PIO_MEM_WR_READ";
`PIO_MEM_ACCESS_WR_WRITE : state_ascii <= #`TCQ "PIO_MEM_WR_WRITE";
default : state_ascii <= #`TCQ "PIO MEM STATE ERR";
endcase
end
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NAND3B_FUNCTIONAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_FUNCTIONAL_PP_V |
//-----------------------------------------------------------------------------
// File : hierarchical_wb_slave_0.v
// Creation date : 28.11.2017
// Creation time : 16:51:22
// Description : A wishbone slave containing another wishbone slave, so now you can use a wishbone slave while using a wishbone slave.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1176 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:peripheral.subsystem:hierarchical_wb_slave:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/peripheral.subsystem/hierarchical_wb_slave/1.0/hierarchical_wb_slave.1.0.xml
//-----------------------------------------------------------------------------
module hierarchical_wb_slave_0 #(
parameter ADDR_WIDTH = 32, // The width of the address.
parameter BASE_ADDRESS = 128, // The first referred address of the master.
parameter DATA_COUNT = 8, // How many values there are in the register array.
parameter DATA_WIDTH = 32 // The width of the both transferred and inputted data.
) (
// Interface: wb_slave
input [31:0] adr_i, // The address of the data.
input cyc_i, // Asserted by master for transfer.
input [31:0] dat_i, // Data from slave to master.
input stb_i, // Asserted, when this specific slave is selected.
input we_i, // Write = 1, Read = 0.
output ack_o, // Slave asserts acknowledge.
output [31:0] dat_o, // Data from master to slave.
// Interface: wb_system
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// sub_slave_wb_system_to_wb_system wires:
wire sub_slave_wb_system_to_wb_systemclk;
wire sub_slave_wb_system_to_wb_systemrst;
// sub_slave_wb_slave_to_wb_slave wires:
wire sub_slave_wb_slave_to_wb_slaveack;
wire [31:0] sub_slave_wb_slave_to_wb_slaveadr;
wire sub_slave_wb_slave_to_wb_slavecyc;
wire [31:0] sub_slave_wb_slave_to_wb_slavedat_ms;
wire [31:0] sub_slave_wb_slave_to_wb_slavedat_sm;
wire sub_slave_wb_slave_to_wb_slaveerr;
wire sub_slave_wb_slave_to_wb_slavestb;
wire sub_slave_wb_slave_to_wb_slavewe;
// sub_slave port wires:
wire sub_slave_ack_o;
wire [31:0] sub_slave_adr_i;
wire sub_slave_clk_i;
wire sub_slave_cyc_i;
wire [31:0] sub_slave_dat_i;
wire [31:0] sub_slave_dat_o;
wire sub_slave_err_o;
wire sub_slave_rst_i;
wire sub_slave_stb_i;
wire sub_slave_we_i;
// Assignments for the ports of the encompassing component:
assign ack_o = sub_slave_wb_slave_to_wb_slaveack;
assign sub_slave_wb_slave_to_wb_slaveadr[31:0] = adr_i[31:0];
assign sub_slave_wb_system_to_wb_systemclk = clk_i;
assign sub_slave_wb_slave_to_wb_slavecyc = cyc_i;
assign sub_slave_wb_slave_to_wb_slavedat_ms[31:0] = dat_i[31:0];
assign dat_o[31:0] = sub_slave_wb_slave_to_wb_slavedat_sm[31:0];
assign sub_slave_wb_system_to_wb_systemrst = rst_i;
assign sub_slave_wb_slave_to_wb_slavestb = stb_i;
assign sub_slave_wb_slave_to_wb_slavewe = we_i;
// sub_slave assignments:
assign sub_slave_wb_slave_to_wb_slaveack = sub_slave_ack_o;
assign sub_slave_adr_i[31:0] = sub_slave_wb_slave_to_wb_slaveadr[31:0];
assign sub_slave_clk_i = sub_slave_wb_system_to_wb_systemclk;
assign sub_slave_cyc_i = sub_slave_wb_slave_to_wb_slavecyc;
assign sub_slave_dat_i[31:0] = sub_slave_wb_slave_to_wb_slavedat_ms[31:0];
assign sub_slave_wb_slave_to_wb_slavedat_sm[31:0] = sub_slave_dat_o[31:0];
assign sub_slave_rst_i = sub_slave_wb_system_to_wb_systemrst;
assign sub_slave_stb_i = sub_slave_wb_slave_to_wb_slavestb;
assign sub_slave_we_i = sub_slave_wb_slave_to_wb_slavewe;
// An instantiation of the same wishbone slave as used in wb_example design.
// IP-XACT VLNV: tut.fi:communication.template:wb_slave:1.0
wb_slave #(
.ADDR_WIDTH (32),
.DATA_WIDTH (32),
.DATA_COUNT (8),
.BASE_ADDRESS (128))
sub_slave(
// Interface: wb_slave
.adr_i (sub_slave_adr_i),
.cyc_i (sub_slave_cyc_i),
.dat_i (sub_slave_dat_i),
.stb_i (sub_slave_stb_i),
.we_i (sub_slave_we_i),
.ack_o (sub_slave_ack_o),
.dat_o (sub_slave_dat_o),
.err_o (sub_slave_err_o),
// Interface: wb_system
.clk_i (sub_slave_clk_i),
.rst_i (sub_slave_rst_i));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NAND2B_FUNCTIONAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_FUNCTIONAL_V |
`timescale 1 ns / 1 ps
`include "MIPI_D_PHY_RX_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S_AXI_LITE_MAX_BURST_LENGTH 1
`define S_AXI_LITE_DATA_BUS_WIDTH 32
`define S_AXI_LITE_ADDRESS_BUS_WIDTH 32
`define S_AXI_LITE_MAX_DATA_SIZE (`S_AXI_LITE_DATA_BUS_WIDTH*`S_AXI_LITE_MAX_BURST_LENGTH)/8
module MIPI_D_PHY_RX_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S_AXI_LITE AXI4 Lite Local Reg
reg [`S_AXI_LITE_DATA_BUS_WIDTH-1:0] S_AXI_LITE_rd_data_lite;
reg [`S_AXI_LITE_DATA_BUS_WIDTH-1:0] S_AXI_LITE_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S_AXI_LITE_lite_response;
reg [`S_AXI_LITE_ADDRESS_BUS_WIDTH-1:0] S_AXI_LITE_mtestAddress;
reg [3-1:0] S_AXI_LITE_mtestProtection_lite;
integer S_AXI_LITE_mtestvectorlite; // Master side testvector
integer S_AXI_LITE_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S_AXI_LITE_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S_AXI_LITE");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S_AXI_LITE_mtestvectorlite = 0;
S_AXI_LITE_mtestAddress = `S_AXI_LITE_SLAVE_ADDRESS;
S_AXI_LITE_mtestProtection_lite = 0;
S_AXI_LITE_mtestdatasizelite = `S_AXI_LITE_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S_AXI_LITE_mtestvectorlite = 0; S_AXI_LITE_mtestvectorlite <= 3; S_AXI_LITE_mtestvectorlite = S_AXI_LITE_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S_AXI_LITE_mtestAddress,
S_AXI_LITE_mtestProtection_lite,
S_AXI_LITE_test_data_lite[S_AXI_LITE_mtestvectorlite],
S_AXI_LITE_mtestdatasizelite,
S_AXI_LITE_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S_AXI_LITE_mtestvectorlite,S_AXI_LITE_test_data_lite[S_AXI_LITE_mtestvectorlite],S_AXI_LITE_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_LITE_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S_AXI_LITE_mtestAddress,
S_AXI_LITE_mtestProtection_lite,
S_AXI_LITE_rd_data_lite,
S_AXI_LITE_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S_AXI_LITE_mtestvectorlite,S_AXI_LITE_rd_data_lite,S_AXI_LITE_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_LITE_lite_response);
COMPARE_LITE_DATA(S_AXI_LITE_test_data_lite[S_AXI_LITE_mtestvectorlite],S_AXI_LITE_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S_AXI_LITE_mtestvectorlite,S_AXI_LITE_mtestvectorlite);
S_AXI_LITE_mtestAddress = S_AXI_LITE_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S_AXI_LITE: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S_AXI_LITE_test_data_lite[0] = 32'h0101FFFF;
S_AXI_LITE_test_data_lite[1] = 32'habcd0001;
S_AXI_LITE_test_data_lite[2] = 32'hdead0011;
S_AXI_LITE_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S_AXI_LITE_TEST();
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
//////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: serdes_n_to_1_s8_diff.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: August 1 2008
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: D-bit generic n:1 transmitter module
// Takes in n bits of data and serialises this to 1 bit
// data is transmitted LSB first
// Parallel input word
// DS, DS-1 ..... 1, 0
// Serial output words
// Line0 : 0, ...... DS-(S+1)
// Line1 : 1, ...... DS-(S+2)
// Line(D-1) : . .
// Line0(D) : D-1, ...... DS
// Data inversion can be accomplished via the TX_SWAP_MASK
// parameter if required
//
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
//////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module serdes_n_to_1_s8_diff (txioclk, txserdesstrobe, reset, gclk, datain, dataout_p, dataout_n) ;
parameter integer S = 8 ; // Parameter to set the serdes factor 1..8
parameter integer D = 16 ; // Set the number of inputs and outputs
input txioclk ; // IO Clock network
input txserdesstrobe ; // Parallel data capture strobe
input reset ; // Reset
input gclk ; // Global clock
input [(D*S)-1:0] datain ; // Data for output
output [D-1:0] dataout_p ; // output data
output [D-1:0] dataout_n ; // output data
wire [D:0] cascade_di ; //
wire [D:0] cascade_do ; //
wire [D:0] cascade_ti ; //
wire [D:0] cascade_to ; //
wire [D:0] tx_data_out ; //
wire [D*8:0] mdataina ; //
wire [D*4:0] mdatainb ; //
parameter [D-1:0] TX_SWAP_MASK = 16'h0000 ; // pinswap mask for output bits (0 = no swap (default), 1 = swap). Allows outputs to be connected the 'wrong way round' to ease PCB routing.
genvar i ;
genvar j ;
generate
for (i = 0 ; i <= (D-1) ; i = i+1)
begin : loop0
OBUFDS io_data_out (
.O (dataout_p[i]),
.OB (dataout_n[i]),
.I (tx_data_out[i]));
if (S > 4) begin // Two oserdes are needed for serdes > 4
for (j = 0 ; j <= (S-1) ; j = j+1)
begin : loop1
// re-arrange data bits for transmission and invert lines as given by the mask
// NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
// This can be avoided by doing the inversion (if necessary) in the user logic
assign mdataina[(8*i)+j] = datain[(i)+(D*j)] ^ TX_SWAP_MASK[i] ;
end
OSERDES2 #(
.DATA_WIDTH (S), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("MASTER"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_m (
.OQ (tx_data_out[i]),
.OCE (1'b1),
.CLK0 (txioclk),
.CLK1 (1'b0),
.IOCE (txserdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdataina[(8*i)+7]),
.D3 (mdataina[(8*i)+6]),
.D2 (mdataina[(8*i)+5]),
.D1 (mdataina[(8*i)+4]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (1'b1), // Dummy input in Master
.SHIFTIN2 (1'b1), // Dummy input in Master
.SHIFTIN3 (cascade_do[i]), // Cascade output D data from slave
.SHIFTIN4 (cascade_to[i]), // Cascade output T data from slave
.SHIFTOUT1 (cascade_di[i]), // Cascade input D data to slave
.SHIFTOUT2 (cascade_ti[i]), // Cascade input T data to slave
.SHIFTOUT3 (), // Dummy output in Master
.SHIFTOUT4 ()) ; // Dummy output in Master
OSERDES2 #(
.DATA_WIDTH (S), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("SLAVE"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_s (
.OQ (),
.OCE (1'b1),
.CLK0 (txioclk),
.CLK1 (1'b0),
.IOCE (txserdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdataina[(8*i)+3]),
.D3 (mdataina[(8*i)+2]),
.D2 (mdataina[(8*i)+1]),
.D1 (mdataina[(8*i)+0]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (cascade_di[i]), // Cascade input D from Master
.SHIFTIN2 (cascade_ti[i]), // Cascade input T from Master
.SHIFTIN3 (1'b1), // Dummy input in Slave
.SHIFTIN4 (1'b1), // Dummy input in Slave
.SHIFTOUT1 (), // Dummy output in Slave
.SHIFTOUT2 (), // Dummy output in Slave
.SHIFTOUT3 (cascade_do[i]), // Cascade output D data to Master
.SHIFTOUT4 (cascade_to[i])) ; // Cascade output T data to Master
end
if (S < 5) begin // Only one oserdes needed for serdes < 5
for (j = 0 ; j <= (S-1) ; j = j+1)
begin : loop1
// re-arrange data bits for transmission and invert lines as given by the mask
// NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2
// This can be avoided by doing the inversion (if necessary) in the user logic
assign mdatainb[(4*i)+j] = datain[(i)+(D*j)] ^ TX_SWAP_MASK[i] ;
end
OSERDES2 #(
.DATA_WIDTH (S), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR")) // <SDR>, DDR
// .SERDES_MODE ("NONE")) // <DEFAULT>, MASTER, SLAVE
// .OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_m (
.OQ (tx_data_out[i]),
.OCE (1'b1),
.CLK0 (txioclk),
.CLK1 (1'b0),
.IOCE (txserdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatainb[(4*i)+3]),
.D3 (mdatainb[(4*i)+2]),
.D2 (mdatainb[(4*i)+1]),
.D1 (mdatainb[(4*i)+0]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (1'b1), // No cascades needed
.SHIFTIN2 (1'b1), // No cascades needed
.SHIFTIN3 (1'b1), // No cascades needed
.SHIFTIN4 (1'b1), // No cascades needed
.SHIFTOUT1 (), // No cascades needed
.SHIFTOUT2 (), // No cascades needed
.SHIFTOUT3 (), // No cascades needed
.SHIFTOUT4 ()) ; // No cascades needed
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKMUX2_2_V
`define SKY130_FD_SC_HDLL__CLKMUX2_2_V
/**
* clkmux2: Clock mux.
*
* Verilog wrapper for clkmux2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkmux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkmux2_2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkmux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkmux2_2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkmux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKMUX2_2_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's ALU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// ALU ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_alu.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Defines added, flags are corrected.
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_alu(
a, b, mult_mac_result, macrc_op,
alu_op, alu_op2, comp_op,
cust5_op, cust5_limm,
result, flagforw, flag_we,
ovforw, ov_we,
cyforw, cy_we, carry, flag
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [width-1:0] a;
input [width-1:0] b;
input [width-1:0] mult_mac_result;
input macrc_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
input [4:0] cust5_op;
input [5:0] cust5_limm;
output [width-1:0] result;
output flagforw;
output flag_we;
output cyforw;
output cy_we;
output ovforw;
output ov_we;
input carry;
input flag;
wire [width-1:0] result_sum;
//
// Internal wires and regs
//
reg [width-1:0] result;
reg [width-1:0] shifted_rotated;
reg [width-1:0] extended;
`ifdef OR1200_IMPL_ALU_CUST5
reg [width-1:0] result_cust5;
`endif
reg flagforw;
reg flagcomp;
reg flag_we;
reg cyforw;
reg cy_we;
reg ovforw;
reg ov_we;
wire [width-1:0] comp_a;
wire [width-1:0] comp_b;
wire a_eq_b;
wire a_lt_b;
wire [width-1:0] result_and;
wire cy_sum;
`ifdef OR1200_IMPL_SUB
wire cy_sub;
`endif
wire ov_sum;
wire [width-1:0] carry_in;
wire [width-1:0] b_mux;
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`ifdef OR1200_IMPL_ALU_COMP3
assign a_eq_b = !(|result_sum);
// signed compare when comp_op[3] is set
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
(!a[width-1] & !b[width-1] & result_sum[width-1])|
(a[width-1] & b[width-1] & result_sum[width-1])):
(a < b);
`endif
`ifdef OR1200_IMPL_SUB
`ifdef OR1200_IMPL_ALU_COMP3
assign cy_sub = a_lt_b;
`else
assign cy_sub = (comp_a < comp_b);
`endif
`endif
`ifdef OR1200_IMPL_ADDC
assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
{{width-1{1'b0}},carry} : {width{1'b0}};
`else
assign carry_in = {width-1{1'b0}};
`endif
`ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
(~b)+1 : b;
`else
assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
`endif
`else // ! `ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
`else
assign b_mux = b;
`endif
`endif
assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
// Numbers either both +ve and bit 31 of result set
assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
`ifdef OR1200_IMPL_SUB
// Subtract larger negative from smaller positive
((!a[width-1] & b_mux[width-1]) & result_sum[width-1] &
alu_op==`OR1200_ALUOP_SUB) |
`endif
// or both -ve and bit 31 of result clear
((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
assign result_and = a & b;
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
if (result === 32'bx)
$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
//
// Central part of the ALU
//
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
or shifted_rotated or mult_mac_result or flag or carry
`ifdef OR1200_IMPL_ALU_EXT
or extended
`endif
`ifdef OR1200_IMPL_ALU_CUST5
or result_cust5
`endif
) begin
`ifdef OR1200_CASE_DEFAULT
casez (alu_op) // synopsys parallel_case
`else
casez (alu_op) // synopsys full_case parallel_case
`endif
`ifdef OR1200_IMPL_ALU_FFL1
`OR1200_ALUOP_FFL1: begin
`ifdef OR1200_CASE_DEFAULT
casez (alu_op2) // synopsys parallel_case
`else
casez (alu_op2) // synopsys full_case parallel_case
`endif
0: begin // FF1
result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
end
default: begin // FL1
result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
end
endcase // casez (alu_op2)
end // case: `OR1200_ALUOP_FFL1
`endif // `ifdef OR1200_IMPL_ALU_FFL1
`ifdef OR1200_IMPL_ALU_CUST5
`OR1200_ALUOP_CUST5 : begin
result = result_cust5;
end
`endif
`OR1200_ALUOP_SHROT : begin
result = shifted_rotated;
end
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC,
`endif
`ifdef OR1200_IMPL_SUB
`OR1200_ALUOP_SUB,
`endif
`OR1200_ALUOP_ADD : begin
result = result_sum;
end
`OR1200_ALUOP_XOR : begin
result = a ^ b;
end
`OR1200_ALUOP_OR : begin
result = a | b;
end
`ifdef OR1200_IMPL_ALU_EXT
`OR1200_ALUOP_EXTHB : begin
result = extended;
end
`OR1200_ALUOP_EXTW : begin
result = a;
end
`endif
`OR1200_ALUOP_MOVHI : begin
if (macrc_op) begin
result = mult_mac_result;
end
else begin
result = b << 16;
end
end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIV,
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL,
`OR1200_ALUOP_MULU : begin
result = mult_mac_result;
end
`endif
`OR1200_ALUOP_CMOV: begin
result = flag ? a : b;
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
`endif
result=result_and;
end
endcase
end
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp
) begin
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC,
`endif
`OR1200_ALUOP_ADD : begin
flagforw = (result_sum == 32'h0000_0000);
flag_we = 1'b1;
end
`OR1200_ALUOP_AND: begin
flagforw = (result_and == 32'h0000_0000);
flag_we = 1'b1;
end
`endif
`OR1200_ALUOP_COMP: begin
flagforw = flagcomp;
flag_we = 1'b1;
end
default: begin
flagforw = flagcomp;
flag_we = 1'b0;
end
endcase
end
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_SUB
or cy_sub
`endif
`endif
) begin
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC,
`endif
`OR1200_ALUOP_ADD : begin
cyforw = cy_sum;
cy_we = 1'b1;
end
`ifdef OR1200_IMPL_SUB
`OR1200_ALUOP_SUB: begin
cyforw = cy_sub;
cy_we = 1'b1;
end
`endif
`endif
default: begin
cyforw = 1'b0;
cy_we = 1'b0;
end
endcase
end
//
// Generate SR[OV] write enable
//
always @(alu_op or ov_sum) begin
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_OV
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC,
`endif
`ifdef OR1200_IMPL_SUB
`OR1200_ALUOP_SUB,
`endif
`OR1200_ALUOP_ADD : begin
ovforw = ov_sum;
ov_we = 1'b1;
end
`endif
default: begin
ovforw = 1'b0;
ov_we = 1'b0;
end
endcase
end
//
// Shifts and rotation
//
always @(alu_op2 or a or b) begin
case (alu_op2) // synopsys parallel_case
`OR1200_SHROTOP_SLL :
shifted_rotated = (a << b[4:0]);
`OR1200_SHROTOP_SRL :
shifted_rotated = (a >> b[4:0]);
`ifdef OR1200_IMPL_ALU_ROTATE
`OR1200_SHROTOP_ROR :
shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
(a >> b[4:0]);
`endif
default:
shifted_rotated = ({32{a[31]}} <<
(6'd32-{1'b0, b[4:0]})) |
a >> b[4:0];
endcase
end
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = a_eq_b;
`OR1200_COP_SFNE:
flagcomp = ~a_eq_b;
`OR1200_COP_SFGT:
flagcomp = ~(a_eq_b | a_lt_b);
`OR1200_COP_SFGE:
flagcomp = ~a_lt_b;
`OR1200_COP_SFLT:
flagcomp = a_lt_b;
`OR1200_COP_SFLE:
flagcomp = a_eq_b | a_lt_b;
default:
flagcomp = 1'b0;
endcase
end
`endif
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = (comp_a == comp_b);
`OR1200_COP_SFNE:
flagcomp = (comp_a != comp_b);
`OR1200_COP_SFGT:
flagcomp = (comp_a > comp_b);
`OR1200_COP_SFGE:
flagcomp = (comp_a >= comp_b);
`OR1200_COP_SFLT:
flagcomp = (comp_a < comp_b);
`OR1200_COP_SFLE:
flagcomp = (comp_a <= comp_b);
default:
flagcomp = 1'b0;
endcase
end
`endif // `ifdef OR1200_IMPL_ALU_COMP2
`ifdef OR1200_IMPL_ALU_COMP3
always @(comp_op or a_eq_b or a_lt_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = a_eq_b;
`OR1200_COP_SFNE:
flagcomp = ~a_eq_b;
`OR1200_COP_SFGT:
flagcomp = ~(a_eq_b | a_lt_b);
`OR1200_COP_SFGE:
flagcomp = ~a_lt_b;
`OR1200_COP_SFLT:
flagcomp = a_lt_b;
`OR1200_COP_SFLE:
flagcomp = a_eq_b | a_lt_b;
default:
flagcomp = 1'b0;
endcase
end
`endif
`ifdef OR1200_IMPL_ALU_EXT
always @(alu_op or alu_op2 or a) begin
casez (alu_op2)
`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
`OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
`OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
default: extended = a; // Used for l.extw instructions
endcase // casez (alu_op2)
end
`endif
//
// l.cust5 custom instructions
//
`ifdef OR1200_IMPL_ALU_CUST5
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
casez (cust5_op) // synopsys parallel_case
5'h1 : begin
casez (cust5_limm[1:0])
2'h0: result_cust5 = {a[31:8], b[7:0]};
2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
2'h3: result_cust5 = {b[7:0], a[23:0]};
endcase
end
5'h2 :
result_cust5 = a | (1 << cust5_limm);
5'h3 :
result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
default: begin
result_cust5 = a;
end
endcase
end // always @ (cust5_op or cust5_limm or a or b)
`endif
endmodule
|
/* Static version of the census transform stereo vision algorithm.
*
* Copyright (c) 2016, Stephen Longfield, stephenlongfield.com
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This file contains a simple static example of one possible configuration for
* the census transform implementation of the stereo vision algorithm. Its main
* purpose is reference, and integration testing.
*
* This is the equivalent of running gen_stereo.py with:
* census_gen.py
* --bit_width 8
* --line_width 450
* --window_width = 20
* --window_height = 20
* --max_disparity = 40
*/
`ifndef STEREO_CENSUS_BASIC_V_
`define STEREO_CENSUS_BASIC_V_
`include "line_buffer.v"
`include "census.v"
`include "pop_count_9.v" // Generated
`include "argmin_40.v" // Generated
module census_basic (
input wire clk,
input wire rst,
input wire [7:0] inp_left,
input wire [7:0] inp_right,
output wire [5:0] outp
);
wire [(8*20*20-1):0] left_window;
wire [(8*20*20-1):0] right_window;
line_buffer#(.WIDTH(8), .LINE_LENGTH(450), .NUM_LINES(20), .WINDOW_WIDTH(20))
left_buf(clk, rst, inp_left, left_window);
line_buffer#(.WIDTH(8), .LINE_LENGTH(450), .NUM_LINES(20), .WINDOW_WIDTH(20))
right_buf(clk, rst, inp_right, right_window);
wire [(20*20-1):0] left_census;
wire [(20*20-1):0] right_census;
census#(.WIDTH(8), .WINDOW_WIDTH(20), .WINDOW_HEIGHT(20))
lcensus(clk, rst, left_window, left_census);
census#(.WIDTH(8), .WINDOW_WIDTH(20), .WINDOW_HEIGHT(20))
rcensus(clk, rst, right_window, right_census);
wire [20*20*40-1:0] left_census_history;
wire [20*20-1:0] unused;
tapped_fifo#(.WIDTH(20*20), .DEPTH(40))
census_samples(clk, rst, left_census, left_census_history, unused);
// Unpack the values of the census history.
wire [20*20-1:0] left_unpacked[40];
genvar i;
generate
for (i = 0; i < 40; i++) begin : unpack
assign left_unpacked[i] =
left_census_history[(20*20*(i+1)-1):(20*20*i)];
end
endgenerate
// Compute the hamming distances.
wire [8:0] hamming_distance[40];
generate
for (i = 0; i < 40; i++) begin: ham
pop_count_9#(.WIDTH(400))
count(clk, rst, right_census ^ left_unpacked[i], hamming_distance[i]);
end
endgenerate
// Repack the hamming distances to feed them into the argmin.
wire [(9*40-1):0] packed_ham;
generate
for (i = 0; i < 40; i++) begin: pack
assign packed_ham[(9*(i+1)-1):(9*i)] = hamming_distance[i];
end
endgenerate
wire [8:0] unused_min;
argmin_40#(.WIDTH(9)) amin(clk, rst, packed_ham, unused_min, outp);
endmodule
`endif // STEREO_CENSUS_BASIC_V_
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC FSM ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Data cache state machine ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_fsm.v,v $
// Revision 1.1 2008/05/07 22:43:21 daughtry
// Initial Demo RTL check-in
//
// Revision 1.9 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.7 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/28 19:10:40 lampret
// Optimized cache controller FSM.
//
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:15:59 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_DCFSM_IDLE 3'd0
`define OR1200_DCFSM_CLOAD 3'd1
`define OR1200_DCFSM_LREFILL3 3'd2
`define OR1200_DCFSM_CSTORE 3'd3
`define OR1200_DCFSM_SREFILL4 3'd4
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
module or1200_dc_fsm(
// Clock and reset
clk, rst,
// Internal i/f to top level DC
dc_en, dcqmem_cycstb_i, dcqmem_ci_i, dcqmem_we_i, dcqmem_sel_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we, dc_addr
);
//
// I/O
//
input clk;
input rst;
input dc_en;
input dcqmem_cycstb_i;
input dcqmem_ci_i;
input dcqmem_we_i;
input [3:0] dcqmem_sel_i;
input tagcomp_miss;
input biudata_valid;
input biudata_error;
input [31:0] start_addr;
output [31:0] saved_addr;
output [3:0] dcram_we;
output biu_read;
output biu_write;
output first_hit_ack;
output first_miss_ack;
output first_miss_err;
output burst;
output tag_we;
output [31:0] dc_addr;
//
// Internal wires and regs
//
reg [31:0] saved_addr_r;
reg [2:0] state;
reg [2:0] cnt;
reg hitmiss_eval;
reg store;
reg load;
reg cache_inhibit;
wire first_store_hit_ack;
//
// Generate of DCRAM write enables
//
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcqmem_sel_i;
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
assign biu_write = store;
assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
assign saved_addr = saved_addr_r;
//
// Assert for cache hit first word ready
// Assert for store cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcqmem_ci_i | first_store_hit_ack;
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcqmem_ci_i;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
| (state == `OR1200_DCFSM_LREFILL3)
`ifdef OR1200_DC_STORE_REFILL
| (state == `OR1200_DCFSM_SREFILL4)
`endif
;
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= #1 `OR1200_DCFSM_IDLE;
saved_addr_r <= #1 32'b0;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
load <= #1 1'b0;
cnt <= #1 3'b000;
cache_inhibit <= #1 1'b0;
end
else
case (state) // synopsys parallel_case
`OR1200_DCFSM_IDLE :
if (dc_en & dcqmem_cycstb_i & dcqmem_we_i) begin // store
state <= #1 `OR1200_DCFSM_CSTORE;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
store <= #1 1'b1;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (dc_en & dcqmem_cycstb_i) begin // load
state <= #1 `OR1200_DCFSM_CLOAD;
saved_addr_r <= #1 start_addr;
hitmiss_eval <= #1 1'b1;
store <= #1 1'b0;
load <= #1 1'b1;
cache_inhibit <= #1 1'b0;
end
else begin // idle
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
`OR1200_DCFSM_CLOAD: begin // load
if (dcqmem_cycstb_i & dcqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((hitmiss_eval & !dcqmem_cycstb_i) || // load aborted (usually caused by DMMU)
(biudata_error) || // load terminated with an error
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // load from cache-inhibited area
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill
state <= #1 `OR1200_DCFSM_LREFILL3;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
hitmiss_eval <= #1 1'b0;
cnt <= #1 `OR1200_DCLS-2;
cache_inhibit <= #1 1'b0;
end
else if (!tagcomp_miss & !dcqmem_ci_i) begin // load hit, finish immediately
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else // load in-progress
hitmiss_eval <= #1 1'b0;
end
`OR1200_DCFSM_LREFILL3 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
cnt <= #1 cnt - 3'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last load of line refill
state <= #1 `OR1200_DCFSM_IDLE;
load <= #1 1'b0;
end
end
`OR1200_DCFSM_CSTORE: begin // store
if (dcqmem_cycstb_i & dcqmem_ci_i)
cache_inhibit <= #1 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= #1 start_addr[31:13];
if ((hitmiss_eval & !dcqmem_cycstb_i) || // store aborted (usually caused by DMMU)
(biudata_error) || // store terminated with an error
((cache_inhibit | dcqmem_ci_i) & biudata_valid)) begin // store to cache-inhibited area
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
`ifdef OR1200_DC_STORE_REFILL
else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and doq load refill
state <= #1 `OR1200_DCFSM_SREFILL4;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
load <= #1 1'b1;
cnt <= #1 `OR1200_DCLS-1;
cache_inhibit <= #1 1'b0;
end
`endif
else if (biudata_valid) begin // store hit, finish write-through
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
cache_inhibit <= #1 1'b0;
end
else // store write-through in-progress
hitmiss_eval <= #1 1'b0;
end
`ifdef OR1200_DC_STORE_REFILL
`OR1200_DCFSM_SREFILL4 : begin
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
cnt <= #1 cnt - 1'd1;
saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 1'd1;
end
else if (biudata_valid) begin // last load of line refill
state <= #1 `OR1200_DCFSM_IDLE;
load <= #1 1'b0;
end
end
`endif
default:
state <= #1 `OR1200_DCFSM_IDLE;
endcase
end
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:32:37 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_gcd_0_1/gcd_block_design_gcd_0_1_stub.v
// Design : gcd_block_design_gcd_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "gcd,Vivado 2018.2" *)
module gcd_block_design_gcd_0_1(s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_AWREADY, s_axi_gcd_bus_WDATA, s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID, s_axi_gcd_bus_WREADY, s_axi_gcd_bus_BRESP, s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY, s_axi_gcd_bus_ARADDR, s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_RDATA, s_axi_gcd_bus_RRESP, s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY, ap_clk, ap_rst_n, interrupt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_gcd_bus_AWADDR[5:0],s_axi_gcd_bus_AWVALID,s_axi_gcd_bus_AWREADY,s_axi_gcd_bus_WDATA[31:0],s_axi_gcd_bus_WSTRB[3:0],s_axi_gcd_bus_WVALID,s_axi_gcd_bus_WREADY,s_axi_gcd_bus_BRESP[1:0],s_axi_gcd_bus_BVALID,s_axi_gcd_bus_BREADY,s_axi_gcd_bus_ARADDR[5:0],s_axi_gcd_bus_ARVALID,s_axi_gcd_bus_ARREADY,s_axi_gcd_bus_RDATA[31:0],s_axi_gcd_bus_RRESP[1:0],s_axi_gcd_bus_RVALID,s_axi_gcd_bus_RREADY,ap_clk,ap_rst_n,interrupt" */;
input [5:0]s_axi_gcd_bus_AWADDR;
input s_axi_gcd_bus_AWVALID;
output s_axi_gcd_bus_AWREADY;
input [31:0]s_axi_gcd_bus_WDATA;
input [3:0]s_axi_gcd_bus_WSTRB;
input s_axi_gcd_bus_WVALID;
output s_axi_gcd_bus_WREADY;
output [1:0]s_axi_gcd_bus_BRESP;
output s_axi_gcd_bus_BVALID;
input s_axi_gcd_bus_BREADY;
input [5:0]s_axi_gcd_bus_ARADDR;
input s_axi_gcd_bus_ARVALID;
output s_axi_gcd_bus_ARREADY;
output [31:0]s_axi_gcd_bus_RDATA;
output [1:0]s_axi_gcd_bus_RRESP;
output s_axi_gcd_bus_RVALID;
input s_axi_gcd_bus_RREADY;
input ap_clk;
input ap_rst_n;
output interrupt;
endmodule
|
//wbs_spi.v
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000005
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_spi
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x05
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:12
*/
`include "project_defines.v"
`include "spi_defines.v"
`include "timescale.v"
`unconnected_drive pull0
module wb_spi #(
parameter SPI_CHAR_LEN_BITS = 8
)(
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
// SPI signals
output [31:0] ss_pad_o, // slave select
//output ss_pad_o, // slave select
output sclk_pad_o, // serial clock
output mosi_pad_o, // master out slave in
input miso_pad_i // master in slave out
);
localparam SPI_MAX_CHAR = 2 ** SPI_CHAR_LEN_BITS;
localparam SPI_MAX_REG_SIZE = SPI_MAX_CHAR / 32;
//parameters
localparam SPI_CTRL = 0;
localparam SPI_CLOCK_RATE = 1;
localparam SPI_DIVIDER = 2;
localparam SPI_SS = 3;
localparam SPI_BIT_COUNT = 4;
localparam SPI_MAX_BITSIZE = 5;
localparam SPI_RX_DATA = 6;
localparam SPI_TX_DATA = ((SPI_RX_DATA) + (SPI_MAX_REG_SIZE));
//Registers/Wires
reg [31:0] divider = 100; // Divider register
reg [31:0] ctrl = 0; // Control and status register
reg [31:0] ss = 0; // Slave select register
//reg ss = 0; // Slave select register
reg [31:0] char_len= 8; // char len
wire [SPI_MAX_CHAR - 1:0] rx_data; // Rx register
wire [SPI_MAX_CHAR - 1:0] tx_data;
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire inv_clk; // invert clock
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
wire sclk;
wire [31:0] read_reg_pos;
wire [31:0] write_reg_pos;
reg [31:0] tx_data_array [(SPI_MAX_REG_SIZE - 1):0];
wire [31:0] rx_data_array [(SPI_MAX_REG_SIZE - 1):0];
integer i;
//Submodules
spi_clkgen clgen (
.clk_in (clk ),
.rst (rst ),
.go (go ),
.enable (tip ),
.last_clk (last_bit ),
.divider (divider ),
.clk_out (sclk ),
.pos_edge (pos_edge ),
.neg_edge (neg_edge )
);
spi_shift #(
.SPI_CHAR_LEN_BITS (SPI_CHAR_LEN_BITS )
) shift (
.clk (clk ),
.rst (rst ),
.len (char_len ),
.lsb (lsb ),
.go (go ),
.pos_edge (pos_edge ),
.neg_edge (neg_edge ),
.rx_negedge (rx_negedge ),
.tx_negedge (tx_negedge ),
.tip (tip ),
.last (last_bit ),
.s_clk (sclk ),
.s_in (miso_pad_i ),
.s_out (mosi_pad_o ),
.mosi_data (tx_data ),
.miso_data (rx_data )
);
//Asynchronous Logic
genvar gv;
generate
for (gv = 0; gv < SPI_MAX_REG_SIZE; gv = gv + 1) begin : wb_spi_init
assign tx_data[((gv << 5) + 31): (gv << 5)] = tx_data_array[(SPI_MAX_REG_SIZE - 1) - gv];
assign rx_data_array[(SPI_MAX_REG_SIZE - 1) - gv] = rx_data[(gv << 5) + 31: (gv << 5)];
end
endgenerate
// Address decoder
assign read_reg_valid = ((i_wbs_adr >= SPI_RX_DATA) && (i_wbs_adr < SPI_TX_DATA));
assign read_reg_pos = read_reg_valid ? (i_wbs_adr - SPI_RX_DATA): 0;
assign write_reg_valid = (i_wbs_adr >= SPI_TX_DATA) && (i_wbs_adr < (SPI_TX_DATA + (SPI_MAX_REG_SIZE)));
assign write_reg_pos = write_reg_valid ? (i_wbs_adr - SPI_TX_DATA): 0;
assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
assign go = ctrl[`SPI_CTRL_GO];
assign lsb = ctrl[`SPI_CTRL_LSB];
assign ie = ctrl[`SPI_CTRL_IE];
assign ass = ctrl[`SPI_CTRL_ASS];
assign inv_clk = ctrl[`SPI_CTRL_INV_CLK];
assign ss_pad_o = ~((ss & {32{tip & ass}}) | (ss & {32{!ass}}));
//assign ss_pad_o = ~((ss & tip & ass) | (ss & !ass));
//assign ss_pad_o = !ss;
assign sclk_pad_o = inv_clk ? ~sclk : sclk;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h00000000;
o_wbs_ack <= 0;
char_len <= 0;
ctrl <= 0;
divider <= 100;
ss <= 0;
for (i = 0; i < SPI_MAX_REG_SIZE; i = i + 1) begin
tx_data_array[i] <= i;
end
end
else begin
//interrupts
if (ie && tip && last_bit && pos_edge) begin
o_wbs_int <= 1;
end
else if (o_wbs_ack) begin
o_wbs_int <= 0;
end
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (go && last_bit && pos_edge) begin
ctrl[`SPI_CTRL_GO] <= 0;
end
if (i_wbs_stb & i_wbs_cyc & !o_wbs_ack) begin
//master is requesting somethign
if (i_wbs_we && !tip) begin
//write request
case (i_wbs_adr)
SPI_CTRL: begin
ctrl <= i_wbs_dat;
end
SPI_BIT_COUNT: begin
char_len <= i_wbs_dat;
end
SPI_DIVIDER: begin
divider <= i_wbs_dat;
end
SPI_SS: begin
//ss <= i_wbs_dat[0];
ss <= i_wbs_dat;
end
default: begin
end
endcase
if (write_reg_valid) begin
tx_data_array[write_reg_pos] <= i_wbs_dat;
end
end
else begin
//read request
case (i_wbs_adr)
SPI_CTRL: begin
o_wbs_dat <= ctrl;
end
SPI_BIT_COUNT: begin
o_wbs_dat <= char_len;
end
SPI_DIVIDER: begin
o_wbs_dat <= divider;
end
SPI_SS: begin
//o_wbs_dat <= {31'h0, ss};
o_wbs_dat <= ss;
end
SPI_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
SPI_MAX_BITSIZE: begin
o_wbs_dat <= SPI_MAX_CHAR;
end
default: begin
o_wbs_dat <= 32'bx;
end
endcase
if (read_reg_valid) begin
o_wbs_dat <= rx_data_array[read_reg_pos];
end
end
o_wbs_ack <= 1;
end
end
end
endmodule
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : chip_top.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/chip.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
`include "../sys_include.h"
`include "isa.h"
`include "cpu.h"
module id_reg (
input wire clk, //
input wire reset, //
input wire [`AluOpBus] alu_op, //
input wire [`WordDataBus] alu_in_0, //
input wire [`WordDataBus] alu_in_1, //
input wire br_flag, //
input wire [`MemOpBus] mem_op, //
input wire [`WordDataBus] mem_wr_data, //
input wire [`CtrlOpBus] ctrl_op, //
input wire [`RegAddrBus] dst_addr, //
input wire gpr_we_n, //
input wire [`IsaExpBus] exp_code, //
input wire stall, //
input wire flush, //
input wire [`WordAddrBus] if_pc, //
input wire if_en, //
output reg [`WordAddrBus] id_pc, //
output reg id_en, //
output reg [`AluOpBus] id_alu_op, //
output reg [`WordDataBus] id_alu_in_0, //
output reg [`WordDataBus] id_alu_in_1, //
output reg id_br_flag, //
output reg [`MemOpBus] id_mem_op, //
output reg [`WordDataBus] id_mem_wr_data, //
output reg [`CtrlOpBus] id_ctrl_op, //
output reg [`RegAddrBus] id_dst_addr, //
output reg id_gpr_we_n, //
output reg [`IsaExpBus] id_exp_code //
);
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
id_pc <= #1 `WORD_ADDR_W'h0;
id_en <= #1 `DISABLE;
id_alu_op <= #1 `ALU_OP_NOP;
id_alu_in_0 <= #1 `WORD_DATA_W'h0;
id_alu_in_1 <= #1 `WORD_DATA_W'h0;
id_br_flag <= #1 `DISABLE;
id_mem_op <= #1 `MEM_OP_NOP;
id_mem_wr_data <= #1 `WORD_DATA_W'h0;
id_ctrl_op <= #1 `CTRL_OP_NOP;
id_dst_addr <= #1 `REG_ADDR_W'd0;
id_gpr_we_n <= #1 `DISABLE_N;
id_exp_code <= #1 `ISA_EXP_NO_EXP;
end else begin
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin
id_pc <= #1 `WORD_ADDR_W'h0;
id_en <= #1 `DISABLE;
id_alu_op <= #1 `ALU_OP_NOP;
id_alu_in_0 <= #1 `WORD_DATA_W'h0;
id_alu_in_1 <= #1 `WORD_DATA_W'h0;
id_br_flag <= #1 `DISABLE;
id_mem_op <= #1 `MEM_OP_NOP;
id_mem_wr_data <= #1 `WORD_DATA_W'h0;
id_ctrl_op <= #1 `CTRL_OP_NOP;
id_dst_addr <= #1 `REG_ADDR_W'd0;
id_gpr_we_n <= #1 `DISABLE_N;
id_exp_code <= #1 `ISA_EXP_NO_EXP;
end else begin
id_pc <= #1 if_pc;
id_en <= #1 if_en;
id_alu_op <= #1 alu_op;
id_alu_in_0 <= #1 alu_in_0;
id_alu_in_1 <= #1 alu_in_1;
id_br_flag <= #1 br_flag;
id_mem_op <= #1 mem_op;
id_mem_wr_data <= #1 mem_wr_data;
id_ctrl_op <= #1 ctrl_op;
id_dst_addr <= #1 dst_addr;
id_gpr_we_n <= #1 gpr_we_n;
id_exp_code <= #1 exp_code;
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:23:39 04/29/2015
// Design Name: control_unit
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_control_unit.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: control_unit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_control_unit;
// Inputs
reg [15:0] IR;
// Outputs
wire [2:0] reg_read_adr1_d;
wire [2:0] reg_read_adr2_d;
wire [2:0] reg_write_adr_d;
wire reg_write_d;
wire ALU_source2_d;
wire [7:0] ALU_con_d;
wire [15:0] offset_register_d;
wire mem_write_d;
wire mem_to_reg_d;
wire branch_d;
wire [3:0] branch_condition_d;
wire IEN_d;
wire IOF_d;
wire RTI_d;
// Instantiate the Unit Under Test (UUT)
control_unit uut (
.IR(IR),
.reg_read_adr1_d(reg_read_adr1_d),
.reg_read_adr2_d(reg_read_adr2_d),
.reg_write_adr_d(reg_write_adr_d),
.reg_write_d(reg_write_d),
.ALU_source2_d(ALU_source2_d),
.ALU_con_d(ALU_con_d),
.offset_register_d(offset_register_d),
.mem_write_d(mem_write_d),
.mem_to_reg_d(mem_to_reg_d),
.branch_d(branch_d),
.branch_condition_d(branch_condition_d),
.IEN_d(IEN_d),
.IOF_d(IOF_d),
.RTI_d(RTI_d)
);
initial begin
// Initialize Inputs
IR = 0;
// Wait 100 ns for global reset to finish
//#100;
IR = 16'h1000;
#1;
IR = 16'h2000;
#1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_V
`define SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_V
/**
* iso1n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__iso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_V |
/*
* Example of simple simulation.
*/
`timescale 1ns / 1ns
module main;
/*
* Signals.
*/
reg clock; /* Clock input of the design */
reg reset; /* Active high, synchronous Reset */
reg enable; /* Active high enable signal for counter */
reg [3:0] count; /* 4-bit counter */
/*
* Clock generator.
*/
always begin
clock <= 0;
#10;
clock <= 1;
#10;
end
/*
* 4-bit up-counter with synchronous active high reset and
* with active high enable signal.
*/
always @(posedge clock) begin
if (reset)
count <= 0;
else if (enable) begin
$display("(%0d) Incremented Counter %d", $time, count);
count <= count + 1;
end
end
initial begin
#100;
reset <= 1;
$display ("(%0d) Asserting Reset", $time);
#200;
reset <= 0;
$display ("(%0d) De-Asserting Reset", $time);
#100;
$display ("(%0d) Asserting Enable", $time);
enable <= 1;
#400;
$display ("(%0d) De-Asserting Enable", $time);
enable <= 0;
$display ("(%0d) Terminating simulation", $time);
$finish;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_gtx_cpllpd_ovrd.v
// Version : 4.1
`timescale 1ns / 1ps
module pcie3_7x_0_gtx_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF;
always @(posedge i_ibufds_gte2)
begin
cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end
assign o_cpllpd_ovrd = cpllpd_wait[95];
assign o_cpllreset_ovrd = cpllreset_wait[127];
endmodule
|
//Need at least one LUT per frame base address we want
`ifndef N_LUT
`define N_LUT 100
`endif
`ifndef N_BRAM
`define N_BRAM 8
`endif
`ifndef N_DI
`define N_DI 1
`endif
module top(input clk, stb, [DIN_N-1:0] di, output do);
parameter integer DIN_N = `N_DI;
parameter integer DOUT_N = `N_LUT + `N_BRAM;
wire [DIN_N-1:0] di_buf;
genvar i;
generate
for (i = 0; i < `N_DI; i = i+1) begin:di_bufs
IBUF ibuf(.I(di[i]), .O(di_buf[i]));
end
endgenerate
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di_buf};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din[7:0]),
.dout(dout)
);
endmodule
module roi(input clk, input [7:0] din, output [`N_LUT + `N_BRAM-1:0] dout);
genvar i;
generate
for (i = 0; i < `N_LUT; i = i+1) begin:luts
LUT6 #(
.INIT(64'h8000_0000_0000_0001 + (i << 16))
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(dout[i])
);
end
endgenerate
genvar j;
generate
for (j = 0; j < `N_BRAM; j = j+1) begin:brams
(* KEEP, DONT_TOUCH *)
RAMB36E1 #(
.INIT_00(256'h8000000000000000000000000000000000000000000000000000000000000000 + (j << 16))
) bram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[j + `N_LUT]),
.DOBDO(),
.DOPADOP(),
.DOPBDOP());
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSBP_SYMBOL_V
`define SKY130_FD_SC_LS__DFSBP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSBP_SYMBOL_V
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module rm_hdr
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8
)
(
in_data,
in_ctrl,
in_wr,
in_rdy,
out_data,
out_ctrl,
out_wr,
out_rdy,
// --- Misc
reset,
clk
);
input [DATA_WIDTH-1:0] in_data;
input [CTRL_WIDTH-1:0] in_ctrl;
input in_wr;
output in_rdy;
output [DATA_WIDTH-1:0] out_data;
output [CTRL_WIDTH-1:0] out_ctrl;
output reg out_wr;
input out_rdy;
// --- Misc
input reset;
input clk;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Regs/ wires -----------
reg in_pkt;
wire fifo_wr;
wire almost_full;
wire empty;
// ------------ Modules -------------
// hdr_fifo rm_hdr_fifo
// (
// .din({in_ctrl, in_data}),
// .wr_en(fifo_wr),
//
// .dout({out_ctrl, out_data}),
// .rd_en(out_rdy && !empty),
//
// .empty(empty),
// .full(),
// .almost_full(almost_full),
// .rst(reset),
// .clk(clk)
// ); xCG
hdr_fifo hdr_fifo_inst (
.aclr (reset),
.clock (clk),
.data ({in_ctrl, in_data}),
.rdreq (out_rdy && !empty),
.wrreq (fifo_wr),
.almost_full (almost_full),
.empty (empty),
.full (),
.q ({out_ctrl, out_data})
);
// ------------- Logic ------------
// Work out whether we're in a packet or not
always @(posedge clk) begin
if (reset)
in_pkt <= 1'b0;
else if (in_wr) begin
if (in_pkt && |in_ctrl)
in_pkt <= 1'b0;
else if (!in_pkt && !(|in_ctrl))
in_pkt <= 1'b1;
end
end
assign fifo_wr = in_wr && (!(|in_ctrl) || in_pkt);
always @(posedge clk)
out_wr <= out_rdy && !empty;
assign in_rdy = !almost_full;
endmodule // rm_hdr
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:51:15 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_auto_pc_0_sim_netlist.v
// Design : ip_design_auto_pc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_arready,
s_axi_rready,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_axi_awready,
s_axi_awvalid,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_arready;
input s_axi_rready;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input m_axi_awready;
input s_axi_awvalid;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [22:0]Q;
wire \RD.ar_channel_0_n_0 ;
wire \RD.ar_channel_0_n_38 ;
wire \RD.ar_channel_0_n_39 ;
wire \RD.ar_channel_0_n_40 ;
wire \RD.ar_channel_0_n_41 ;
wire \RD.ar_channel_0_n_8 ;
wire \RD.ar_channel_0_n_9 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_1 ;
wire SI_REG_n_10;
wire SI_REG_n_103;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_144;
wire SI_REG_n_145;
wire SI_REG_n_146;
wire SI_REG_n_147;
wire SI_REG_n_148;
wire SI_REG_n_153;
wire SI_REG_n_154;
wire SI_REG_n_161;
wire SI_REG_n_162;
wire SI_REG_n_163;
wire SI_REG_n_164;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_168;
wire SI_REG_n_169;
wire SI_REG_n_170;
wire SI_REG_n_171;
wire SI_REG_n_172;
wire SI_REG_n_173;
wire SI_REG_n_174;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_45;
wire SI_REG_n_83;
wire SI_REG_n_84;
wire SI_REG_n_85;
wire SI_REG_n_86;
wire \WR.aw_channel_0_n_2 ;
wire \WR.aw_channel_0_n_42 ;
wire \WR.aw_channel_0_n_43 ;
wire \WR.aw_channel_0_n_44 ;
wire \WR.aw_channel_0_n_45 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire \WR.b_channel_0_n_3 ;
wire aclk;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire [1:0]\aw_cmd_fsm_0/state ;
wire [11:0]axaddr_incr;
wire [11:0]b_awid;
wire [3:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ;
wire \gen_simple_ar.ar_pipe/m_valid_i0 ;
wire \gen_simple_ar.ar_pipe/p_1_in ;
wire \gen_simple_aw.aw_pipe/p_1_in ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_push;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire shandshake;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [2:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:0]wrap_cnt;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel \RD.ar_channel_0
(.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.E(\gen_simple_ar.ar_pipe/p_1_in ),
.O({SI_REG_n_145,SI_REG_n_146,SI_REG_n_147,SI_REG_n_148}),
.Q({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_103,si_rs_arsize,si_rs_araddr}),
.S({\RD.ar_channel_0_n_38 ,\RD.ar_channel_0_n_39 ,\RD.ar_channel_0_n_40 ,\RD.ar_channel_0_n_41 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\cnt_read_reg[1]_rep__0 (\RD.r_channel_0_n_1 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_8 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_9 ),
.\m_payload_i_reg[35] (SI_REG_n_161),
.\m_payload_i_reg[35]_0 (SI_REG_n_163),
.\m_payload_i_reg[3] (SI_REG_n_173),
.\m_payload_i_reg[3]_0 ({SI_REG_n_83,SI_REG_n_84,SI_REG_n_85,SI_REG_n_86}),
.\m_payload_i_reg[44] (SI_REG_n_162),
.\m_payload_i_reg[47] (SI_REG_n_164),
.\m_payload_i_reg[47]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
.\m_payload_i_reg[6] ({SI_REG_n_166,SI_REG_n_167,SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172}),
.\m_payload_i_reg[7] ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
.m_valid_i0(\gen_simple_ar.ar_pipe/m_valid_i0 ),
.\r_arid_r_reg[11] (s_arid_r),
.r_push(r_push),
.r_rlast(r_rlast),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg(s_axi_arready),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_0 ),
.\wrap_second_len_r_reg[2] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_0 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_push(r_push),
.r_rlast(r_rlast),
.s_ready_i_reg(SI_REG_n_165),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice SI_REG
(.D({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}),
.E(\gen_simple_aw.aw_pipe/p_1_in ),
.O({SI_REG_n_145,SI_REG_n_146,SI_REG_n_147,SI_REG_n_148}),
.Q({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_45,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_42 ,\WR.aw_channel_0_n_43 ,\WR.aw_channel_0_n_44 ,\WR.aw_channel_0_n_45 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[3] ({SI_REG_n_83,SI_REG_n_84,SI_REG_n_85,SI_REG_n_86}),
.\axaddr_incr_reg[7] ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.axaddr_offset_0(\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
.\axaddr_offset_r_reg[0] (SI_REG_n_173),
.\axaddr_offset_r_reg[1] (SI_REG_n_161),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
.\axaddr_offset_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axlen_cnt_reg[3] (SI_REG_n_153),
.\axlen_cnt_reg[3]_0 (SI_REG_n_164),
.b_push(b_push),
.\cnt_read_reg[0]_rep__1 (SI_REG_n_165),
.\cnt_read_reg[3]_rep__0 (\RD.r_channel_0_n_0 ),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_38 ,\RD.ar_channel_0_n_39 ,\RD.ar_channel_0_n_40 ,\RD.ar_channel_0_n_41 }),
.m_valid_i0(\gen_simple_ar.ar_pipe/m_valid_i0 ),
.next_pending_r_reg(SI_REG_n_154),
.next_pending_r_reg_0(SI_REG_n_162),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_103,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.shandshake(shandshake),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\RD.ar_channel_0_n_9 ),
.\state_reg[1] (\aw_cmd_fsm_0/state ),
.\state_reg[1]_rep (\WR.aw_channel_0_n_2 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_0 ),
.\state_reg[1]_rep_1 (\RD.ar_channel_0_n_8 ),
.\state_reg[1]_rep_2 (\gen_simple_ar.ar_pipe/p_1_in ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_166,SI_REG_n_167,SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_174,SI_REG_n_175,SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180}),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
.\wrap_second_len_r_reg[2] (\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[2]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3] (SI_REG_n_163),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel \WR.aw_channel_0
(.D(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.E(\gen_simple_aw.aw_pipe/p_1_in ),
.Q(\aw_cmd_fsm_0/state ),
.S({\WR.aw_channel_0_n_42 ,\WR.aw_channel_0_n_43 ,\WR.aw_channel_0_n_44 ,\WR.aw_channel_0_n_45 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_3 ),
.\cnt_read_reg[1]_rep__0_0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[46] (SI_REG_n_154),
.\m_payload_i_reg[47] (SI_REG_n_153),
.\m_payload_i_reg[61] ({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_45,si_rs_awsize,si_rs_awaddr}),
.\m_payload_i_reg[6] ({SI_REG_n_174,SI_REG_n_175,SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180}),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_boundary_axaddr_r_reg[0] (\WR.aw_channel_0_n_2 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
.\wrap_second_len_r_reg[3]_1 ({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.shandshake(shandshake),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp),
.\state_reg[0]_rep (\WR.b_channel_0_n_3 ));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_ar_channel
(\wrap_boundary_axaddr_r_reg[11] ,
\wrap_second_len_r_reg[2] ,
axaddr_offset,
\axaddr_offset_r_reg[3] ,
r_push,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
m_axi_arvalid,
r_rlast,
m_valid_i0,
E,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
\m_payload_i_reg[47] ,
m_axi_arready,
si_rs_arvalid,
\cnt_read_reg[1]_rep__0 ,
Q,
D,
\m_payload_i_reg[35] ,
\m_payload_i_reg[47]_0 ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[44] ,
areset_d1,
s_axi_arvalid,
s_ready_i_reg,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3]_0 ,
\m_payload_i_reg[6] );
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]\wrap_second_len_r_reg[2] ;
output [0:0]axaddr_offset;
output [2:0]\axaddr_offset_r_reg[3] ;
output r_push;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output m_axi_arvalid;
output r_rlast;
output m_valid_i0;
output [0:0]E;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input \m_payload_i_reg[47] ;
input m_axi_arready;
input si_rs_arvalid;
input \cnt_read_reg[1]_rep__0 ;
input [30:0]Q;
input [1:0]D;
input \m_payload_i_reg[35] ;
input [2:0]\m_payload_i_reg[47]_0 ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[44] ;
input areset_d1;
input s_axi_arvalid;
input s_ready_i_reg;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6] ;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [30:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_11;
wire ar_cmd_fsm_0_n_14;
wire ar_cmd_fsm_0_n_16;
wire ar_cmd_fsm_0_n_17;
wire ar_cmd_fsm_0_n_18;
wire ar_cmd_fsm_0_n_21;
wire ar_cmd_fsm_0_n_3;
wire ar_cmd_fsm_0_n_4;
wire ar_cmd_fsm_0_n_5;
wire ar_cmd_fsm_0_n_6;
wire areset_d1;
wire [0:0]axaddr_offset;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_4;
wire cmd_translator_0_n_5;
wire cmd_translator_0_n_6;
wire cmd_translator_0_n_8;
wire \cnt_read_reg[1]_rep__0 ;
wire \incr_cmd_0/sel_first ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[47] ;
wire [2:0]\m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire m_valid_i0;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push;
wire r_rlast;
wire s_axi_arvalid;
wire s_ready_i_reg;
wire sel_first_i;
wire si_rs_arvalid;
wire [1:0]state;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [0:0]\wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\wrap_cmd_0/wrap_second_len ;
wire [3:0]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [1:0]\wrap_second_len_r_reg[2] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D({ar_cmd_fsm_0_n_3,ar_cmd_fsm_0_n_4,ar_cmd_fsm_0_n_5}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(state),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[0] (ar_cmd_fsm_0_n_21),
.\axaddr_offset_r_reg[0] (axaddr_offset),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r }),
.\axlen_cnt_reg[3] (cmd_translator_0_n_6),
.\axlen_cnt_reg[4] (ar_cmd_fsm_0_n_16),
.\axlen_cnt_reg[6] (cmd_translator_0_n_5),
.\axlen_cnt_reg[7] (ar_cmd_fsm_0_n_0),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[35]_0 (\m_payload_i_reg[35]_0 ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[44] (Q[16:15]),
.\m_payload_i_reg[44]_0 (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 [2:1]),
.m_valid_i0(m_valid_i0),
.next_pending_r_reg(cmd_translator_0_n_1),
.r_push_r_reg(r_push),
.s_axburst_eq0_reg(ar_cmd_fsm_0_n_11),
.s_axburst_eq1_reg(ar_cmd_fsm_0_n_14),
.s_axburst_eq1_reg_0(cmd_translator_0_n_8),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg(s_ready_i_reg),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_17),
.sel_first_reg_0(ar_cmd_fsm_0_n_18),
.sel_first_reg_1(cmd_translator_0_n_4),
.sel_first_reg_2(cmd_translator_0_n_2),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_cnt_r_reg[0] (ar_cmd_fsm_0_n_6),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[2] (D),
.\wrap_second_len_r_reg[3] ({\wrap_cmd_0/wrap_second_len [3],\wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_cmd_0/wrap_second_len_r [3],\wrap_cmd_0/wrap_second_len_r [0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 cmd_translator_0
(.D({\m_payload_i_reg[47]_0 ,axaddr_offset}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q(Q[18:0]),
.S(S),
.aclk(aclk),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] ,\wrap_cmd_0/axaddr_offset_r }),
.\axaddr_offset_r_reg[3]_0 (ar_cmd_fsm_0_n_6),
.\axlen_cnt_reg[0] (cmd_translator_0_n_5),
.\axlen_cnt_reg[0]_0 (cmd_translator_0_n_6),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[39] (ar_cmd_fsm_0_n_11),
.\m_payload_i_reg[39]_0 (ar_cmd_fsm_0_n_14),
.\m_payload_i_reg[3] (\m_payload_i_reg[3]_0 ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(ar_cmd_fsm_0_n_16),
.next_pending_r_reg(cmd_translator_0_n_1),
.r_rlast(r_rlast),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(cmd_translator_0_n_4),
.sel_first_reg_2(ar_cmd_fsm_0_n_18),
.sel_first_reg_3(ar_cmd_fsm_0_n_17),
.sel_first_reg_4(ar_cmd_fsm_0_n_21),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (cmd_translator_0_n_8),
.\state_reg[0]_rep_0 (\m_payload_i_reg[0]_0 ),
.\state_reg[1] (ar_cmd_fsm_0_n_0),
.\state_reg[1]_0 (state),
.\state_reg[1]_rep (r_push),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_cmd_0/wrap_second_len_r [3],\wrap_second_len_r_reg[2] ,\wrap_cmd_0/wrap_second_len_r [0]}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_cmd_0/wrap_second_len [3],D,\wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_1 ({ar_cmd_fsm_0_n_3,ar_cmd_fsm_0_n_4,ar_cmd_fsm_0_n_5}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[19]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(Q[29]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(Q[30]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[25]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[26]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(Q[27]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(Q[28]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_aw_channel
(Q,
\wrap_boundary_axaddr_r_reg[0] ,
m_axi_awvalid,
E,
b_push,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
in,
S,
aclk,
si_rs_awvalid,
\m_payload_i_reg[47] ,
\m_payload_i_reg[61] ,
\m_payload_i_reg[46] ,
areset_d1,
\cnt_read_reg[1]_rep__0 ,
m_axi_awready,
\cnt_read_reg[1]_rep__0_0 ,
\cnt_read_reg[0]_rep__0 ,
axaddr_incr,
D,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output [1:0]Q;
output \wrap_boundary_axaddr_r_reg[0] ;
output m_axi_awvalid;
output [0:0]E;
output b_push;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [15:0]in;
output [3:0]S;
input aclk;
input si_rs_awvalid;
input \m_payload_i_reg[47] ;
input [31:0]\m_payload_i_reg[61] ;
input \m_payload_i_reg[46] ;
input areset_d1;
input \cnt_read_reg[1]_rep__0 ;
input m_axi_awready;
input \cnt_read_reg[1]_rep__0_0 ;
input \cnt_read_reg[0]_rep__0 ;
input [11:0]axaddr_incr;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_0;
wire aw_cmd_fsm_0_n_10;
wire aw_cmd_fsm_0_n_11;
wire aw_cmd_fsm_0_n_12;
wire aw_cmd_fsm_0_n_3;
wire aw_cmd_fsm_0_n_5;
wire aw_cmd_fsm_0_n_6;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_5;
wire cmd_translator_0_n_6;
wire cmd_translator_0_n_7;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire [15:0]in;
wire \incr_cmd_0/sel_first ;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [31:0]\m_payload_i_reg[61] ;
wire [6:0]\m_payload_i_reg[6] ;
wire sel_first;
wire sel_first_i;
wire si_rs_awvalid;
wire \wrap_boundary_axaddr_r_reg[0] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.E(aw_cmd_fsm_0_n_0),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axlen_cnt_reg[0] (aw_cmd_fsm_0_n_3),
.\axlen_cnt_reg[1] (cmd_translator_0_n_7),
.\axlen_cnt_reg[6] (cmd_translator_0_n_5),
.\axlen_cnt_reg[7] (aw_cmd_fsm_0_n_5),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0_0 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[39] (\m_payload_i_reg[61] [15]),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_6),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_10),
.s_axburst_eq1_reg_0(cmd_translator_0_n_6),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_11),
.sel_first_reg_0(aw_cmd_fsm_0_n_12),
.sel_first_reg_1(cmd_translator_0_n_2),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_boundary_axaddr_r_reg[0] (\wrap_boundary_axaddr_r_reg[0] ),
.wrap_next_pending(wrap_next_pending));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator cmd_translator_0
(.D(D),
.E(\wrap_boundary_axaddr_r_reg[0] ),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axlen_cnt_reg[0] (cmd_translator_0_n_5),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_6),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_10),
.\m_payload_i_reg[46] (\m_payload_i_reg[61] [18:0]),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.next_pending_r_reg_1(cmd_translator_0_n_7),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_12),
.sel_first_reg_2(aw_cmd_fsm_0_n_11),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (aw_cmd_fsm_0_n_0),
.\state_reg[0]_rep (cmd_translator_0_n_6),
.\state_reg[0]_rep_0 (aw_cmd_fsm_0_n_5),
.\state_reg[1]_rep (aw_cmd_fsm_0_n_3),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_1 ));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [30]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [31]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [23]),
.Q(in[7]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [25]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [26]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [27]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [28]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [29]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [19]),
.Q(in[3]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__0 ,
\state_reg[0]_rep ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
shandshake,
aclk,
b_push,
si_rs_bready,
m_axi_bvalid,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__0 ;
output \state_reg[0]_rep ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input shandshake;
input aclk;
input b_push;
input si_rs_bready;
input m_axi_bvalid;
input [15:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_3;
wire bid_fifo_0_n_5;
wire \bresp_cnt[7]_i_7_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire [15:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
wire \state_reg[0]_rep ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_5),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bresp_push(bresp_push),
.bvalid_i_reg(bid_fifo_0_n_3),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\state_reg[0]_rep (\state_reg[0]_rep ));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[0]),
.I1(bresp_cnt_reg__0[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_7_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_7_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_7
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_7_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_5),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_3),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT6 #(
.INIT(64'h00000000EACECCCC))
\s_bresp_acc[0]_i_1
(.I0(m_axi_bresp[0]),
.I1(\s_bresp_acc_reg_n_0_[0] ),
.I2(\s_bresp_acc_reg_n_0_[1] ),
.I3(m_axi_bresp[1]),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EA))
\s_bresp_acc[1]_i_1
(.I0(\s_bresp_acc_reg_n_0_[1] ),
.I1(m_axi_bresp[1]),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator
(next_pending_r_reg,
next_pending_r_reg_0,
sel_first_reg_0,
sel_first_0,
sel_first,
\axlen_cnt_reg[0] ,
\state_reg[0]_rep ,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
sel_first_reg_2,
\m_payload_i_reg[47] ,
Q,
si_rs_awvalid,
\m_payload_i_reg[46] ,
E,
\state_reg[1]_rep ,
axaddr_incr,
\state_reg[0] ,
\state_reg[0]_rep_0 ,
D,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output next_pending_r_reg;
output next_pending_r_reg_0;
output sel_first_reg_0;
output sel_first_0;
output sel_first;
output \axlen_cnt_reg[0] ;
output \state_reg[0]_rep ;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input sel_first_reg_2;
input \m_payload_i_reg[47] ;
input [1:0]Q;
input si_rs_awvalid;
input [18:0]\m_payload_i_reg[46] ;
input [0:0]E;
input \state_reg[1]_rep ;
input [11:0]axaddr_incr;
input [0:0]\state_reg[0] ;
input \state_reg[0]_rep_0 ;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axlen_cnt_reg[0] ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_3;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [18:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire \state_reg[1]_rep ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd incr_cmd_0
(.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[0]_0 (sel_first_0),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12}),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[11] (incr_cmd_0_n_13),
.\m_axi_awaddr[2] (incr_cmd_0_n_15),
.\m_axi_awaddr[3] (incr_cmd_0_n_14),
.\m_payload_i_reg[46] ({\m_payload_i_reg[46] [18:16],\m_payload_i_reg[46] [14:12],\m_payload_i_reg[46] [3:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[46] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd wrap_cmd_0
(.D(D),
.E(E),
.Q(Q),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[46] ({\m_payload_i_reg[46] [18:15],\m_payload_i_reg[46] [13:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg_0(next_pending_r_reg_0),
.next_pending_r_reg_1(next_pending_r_reg_1),
.sel_first_reg_0(sel_first),
.sel_first_reg_1(sel_first_reg_2),
.sel_first_reg_2(incr_cmd_0_n_13),
.sel_first_reg_3(incr_cmd_0_n_14),
.sel_first_reg_4(incr_cmd_0_n_15),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_cmd_translator" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1
(incr_next_pending,
next_pending_r_reg,
sel_first_reg_0,
sel_first,
sel_first_reg_1,
\axlen_cnt_reg[0] ,
\axlen_cnt_reg[0]_0 ,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
S,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_2,
sel_first_reg_3,
\m_payload_i_reg[47] ,
E,
Q,
\state_reg[1]_rep ,
\m_payload_i_reg[44] ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
si_rs_arvalid,
\state_reg[0]_rep_0 ,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
m_valid_i_reg,
\state_reg[1] ,
D,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
sel_first_reg_4,
m_axi_arready,
\state_reg[1]_0 );
output incr_next_pending;
output next_pending_r_reg;
output sel_first_reg_0;
output sel_first;
output sel_first_reg_1;
output \axlen_cnt_reg[0] ;
output \axlen_cnt_reg[0]_0 ;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_2;
input sel_first_reg_3;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [18:0]Q;
input \state_reg[1]_rep ;
input \m_payload_i_reg[44] ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input si_rs_arvalid;
input \state_reg[0]_rep_0 ;
input \axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]m_valid_i_reg;
input \state_reg[1] ;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [0:0]sel_first_reg_4;
input m_axi_arready;
input [1:0]\state_reg[1]_0 ;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [18:0]Q;
wire [3:0]S;
wire aclk;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[0] ;
wire \axlen_cnt_reg[0]_0 ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_3;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire [0:0]sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 incr_cmd_0
(.E(E),
.O(O),
.Q({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[0]_0 (sel_first),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[11] (incr_cmd_0_n_15),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[46] ({Q[18:16],Q[14:12],Q[3:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_4),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_0 (\state_reg[1]_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(Q[15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_2
(.I0(s_axburst_eq1),
.I1(Q[15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 wrap_cmd_0
(.D(D),
.E(E),
.Q({Q[18:15],Q[13:0]}),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0]_0 ),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_15),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[0]_0 ,
\axlen_cnt_reg[0]_0 ,
\axaddr_incr_reg[11]_0 ,
\m_axi_awaddr[11] ,
\m_axi_awaddr[3] ,
\m_axi_awaddr[2] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
\m_payload_i_reg[47] ,
Q,
si_rs_awvalid,
\m_payload_i_reg[46] ,
E,
\state_reg[1]_rep ,
axaddr_incr,
\state_reg[0] ,
\state_reg[0]_rep );
output next_pending_r_reg_0;
output \axaddr_incr_reg[0]_0 ;
output \axlen_cnt_reg[0]_0 ;
output [9:0]\axaddr_incr_reg[11]_0 ;
output \m_axi_awaddr[11] ;
output \m_axi_awaddr[3] ;
output \m_axi_awaddr[2] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input \m_payload_i_reg[47] ;
input [1:0]Q;
input si_rs_awvalid;
input [9:0]\m_payload_i_reg[46] ;
input [0:0]E;
input \state_reg[1]_rep ;
input [11:0]axaddr_incr;
input [0:0]\state_reg[0] ;
input \state_reg[0]_rep ;
wire [0:0]E;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire \axaddr_incr[11]_i_1_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [9:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4_n_1 ;
wire \axaddr_incr_reg[11]_i_4_n_2 ;
wire \axaddr_incr_reg[11]_i_4_n_3 ;
wire \axaddr_incr_reg[11]_i_4_n_4 ;
wire \axaddr_incr_reg[11]_i_4_n_5 ;
wire \axaddr_incr_reg[11]_i_4_n_6 ;
wire \axaddr_incr_reg[11]_i_4_n_7 ;
wire \axaddr_incr_reg[3]_i_3_n_0 ;
wire \axaddr_incr_reg[3]_i_3_n_1 ;
wire \axaddr_incr_reg[3]_i_3_n_2 ;
wire \axaddr_incr_reg[3]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_3_n_4 ;
wire \axaddr_incr_reg[3]_i_3_n_5 ;
wire \axaddr_incr_reg[3]_i_3_n_6 ;
wire \axaddr_incr_reg[3]_i_3_n_7 ;
wire \axaddr_incr_reg[7]_i_3_n_0 ;
wire \axaddr_incr_reg[7]_i_3_n_1 ;
wire \axaddr_incr_reg[7]_i_3_n_2 ;
wire \axaddr_incr_reg[7]_i_3_n_3 ;
wire \axaddr_incr_reg[7]_i_3_n_4 ;
wire \axaddr_incr_reg[7]_i_3_n_5 ;
wire \axaddr_incr_reg[7]_i_3_n_6 ;
wire \axaddr_incr_reg[7]_i_3_n_7 ;
wire \axaddr_incr_reg_n_0_[2] ;
wire \axaddr_incr_reg_n_0_[3] ;
wire \axlen_cnt[0]_i_1__1_n_0 ;
wire \axlen_cnt[1]_i_1_n_0 ;
wire \axlen_cnt[2]_i_1_n_0 ;
wire \axlen_cnt[3]_i_2__0_n_0 ;
wire \axlen_cnt[4]_i_1_n_0 ;
wire \axlen_cnt[5]_i_1_n_0 ;
wire \axlen_cnt[6]_i_1_n_0 ;
wire \axlen_cnt[7]_i_2_n_0 ;
wire \axlen_cnt[7]_i_3_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[11] ;
wire \m_axi_awaddr[2] ;
wire \m_axi_awaddr[3] ;
wire [9:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire next_pending_r_i_5_n_0;
wire next_pending_r_reg_0;
wire [11:0]p_1_in;
wire sel_first_reg_0;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1
(.I0(axaddr_incr[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_7 ),
.O(p_1_in[0]));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1
(.I0(axaddr_incr[10]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_5 ),
.O(p_1_in[10]));
LUT2 #(
.INIT(4'hB))
\axaddr_incr[11]_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\state_reg[1]_rep ),
.O(\axaddr_incr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2
(.I0(axaddr_incr[11]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_4 ),
.O(p_1_in[11]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1
(.I0(axaddr_incr[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_6 ),
.O(p_1_in[1]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1
(.I0(axaddr_incr[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_5 ),
.O(p_1_in[2]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1
(.I0(axaddr_incr[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_4 ),
.O(p_1_in[3]));
LUT4 #(
.INIT(16'h0009))
\axaddr_incr[3]_i_10
(.I0(\m_payload_i_reg[46] [0]),
.I1(\state_reg[1]_rep ),
.I2(\m_payload_i_reg[46] [4]),
.I3(\m_payload_i_reg[46] [5]),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg_n_0_[3] ),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg_n_0_[2] ),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg[11]_0 [1]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_14_n_0 ));
LUT4 #(
.INIT(16'h9AAA))
\axaddr_incr[3]_i_7
(.I0(\m_payload_i_reg[46] [3]),
.I1(\state_reg[1]_rep ),
.I2(\m_payload_i_reg[46] [4]),
.I3(\m_payload_i_reg[46] [5]),
.O(S[3]));
LUT4 #(
.INIT(16'h0A9A))
\axaddr_incr[3]_i_8
(.I0(\m_payload_i_reg[46] [2]),
.I1(\state_reg[1]_rep ),
.I2(\m_payload_i_reg[46] [5]),
.I3(\m_payload_i_reg[46] [4]),
.O(S[2]));
LUT4 #(
.INIT(16'h009A))
\axaddr_incr[3]_i_9
(.I0(\m_payload_i_reg[46] [1]),
.I1(\state_reg[1]_rep ),
.I2(\m_payload_i_reg[46] [4]),
.I3(\m_payload_i_reg[46] [5]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1
(.I0(axaddr_incr[4]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_7 ),
.O(p_1_in[4]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1
(.I0(axaddr_incr[5]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_6 ),
.O(p_1_in[5]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1
(.I0(axaddr_incr[6]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_5 ),
.O(p_1_in[6]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1
(.I0(axaddr_incr[7]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_4 ),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1
(.I0(axaddr_incr[8]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_7 ),
.O(p_1_in[8]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1
(.I0(axaddr_incr[9]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_6 ),
.O(p_1_in[9]));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[0]),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[10]),
.Q(\axaddr_incr_reg[11]_0 [8]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[11]),
.Q(\axaddr_incr_reg[11]_0 [9]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4
(.CI(\axaddr_incr_reg[7]_i_3_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4_n_1 ,\axaddr_incr_reg[11]_i_4_n_2 ,\axaddr_incr_reg[11]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4_n_4 ,\axaddr_incr_reg[11]_i_4_n_5 ,\axaddr_incr_reg[11]_i_4_n_6 ,\axaddr_incr_reg[11]_i_4_n_7 }),
.S(\axaddr_incr_reg[11]_0 [9:6]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[1]),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[2]),
.Q(\axaddr_incr_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[3]),
.Q(\axaddr_incr_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3_n_0 ,\axaddr_incr_reg[3]_i_3_n_1 ,\axaddr_incr_reg[3]_i_3_n_2 ,\axaddr_incr_reg[3]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr_reg_n_0_[3] ,\axaddr_incr_reg_n_0_[2] ,\axaddr_incr_reg[11]_0 [1:0]}),
.O({\axaddr_incr_reg[3]_i_3_n_4 ,\axaddr_incr_reg[3]_i_3_n_5 ,\axaddr_incr_reg[3]_i_3_n_6 ,\axaddr_incr_reg[3]_i_3_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[4]),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[5]),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[6]),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[7]),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3
(.CI(\axaddr_incr_reg[3]_i_3_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3_n_0 ,\axaddr_incr_reg[7]_i_3_n_1 ,\axaddr_incr_reg[7]_i_3_n_2 ,\axaddr_incr_reg[7]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3_n_4 ,\axaddr_incr_reg[7]_i_3_n_5 ,\axaddr_incr_reg[7]_i_3_n_6 ,\axaddr_incr_reg[7]_i_3_n_7 }),
.S(\axaddr_incr_reg[11]_0 [5:2]));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[8]),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[9]),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
LUT6 #(
.INIT(64'h44444F4444444444))
\axlen_cnt[0]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[0] ),
.I1(\axlen_cnt_reg[0]_0 ),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(\m_payload_i_reg[46] [7]),
.O(\axlen_cnt[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1
(.I0(E),
.I1(\m_payload_i_reg[46] [8]),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1
(.I0(E),
.I1(\m_payload_i_reg[46] [9]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[4] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'h9A))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.O(\axlen_cnt[7]_i_3_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[4]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[5]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[6]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[7]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[0]_rep ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT2 #(
.INIT(4'hB))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\m_payload_i_reg[46] [6]),
.O(\m_axi_awaddr[11] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[2]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[2] ),
.I2(\m_payload_i_reg[46] [6]),
.I3(\m_payload_i_reg[46] [2]),
.O(\m_axi_awaddr[2] ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[3]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[3] ),
.I2(\m_payload_i_reg[46] [6]),
.I3(\m_payload_i_reg[46] [3]),
.O(\m_axi_awaddr[3] ));
LUT5 #(
.INIT(32'h55545555))
next_pending_r_i_4__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.I4(next_pending_r_i_5_n_0),
.O(\axlen_cnt_reg[0]_0 ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_5
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_i_5_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_incr_cmd" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2
(incr_next_pending,
\axaddr_incr_reg[0]_0 ,
\axlen_cnt_reg[0]_0 ,
Q,
\m_axi_araddr[11] ,
S,
aclk,
sel_first_reg_0,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[46] ,
\state_reg[1]_rep ,
\m_payload_i_reg[44] ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
si_rs_arvalid,
\state_reg[0]_rep ,
m_valid_i_reg,
\state_reg[1] ,
sel_first_reg_1,
m_axi_arready,
\state_reg[1]_0 );
output incr_next_pending;
output \axaddr_incr_reg[0]_0 ;
output \axlen_cnt_reg[0]_0 ;
output [11:0]Q;
output \m_axi_araddr[11] ;
output [3:0]S;
input aclk;
input sel_first_reg_0;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [9:0]\m_payload_i_reg[46] ;
input \state_reg[1]_rep ;
input \m_payload_i_reg[44] ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input si_rs_arvalid;
input \state_reg[0]_rep ;
input [0:0]m_valid_i_reg;
input \state_reg[1] ;
input [0:0]sel_first_reg_1;
input m_axi_arready;
input [1:0]\state_reg[1]_0 ;
wire [0:0]E;
wire [3:0]O;
wire [11:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[0]_i_1__0_n_0 ;
wire \axaddr_incr[10]_i_1__0_n_0 ;
wire \axaddr_incr[11]_i_2__0_n_0 ;
wire \axaddr_incr[1]_i_1__0_n_0 ;
wire \axaddr_incr[2]_i_1__0_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr[3]_i_1__0_n_0 ;
wire \axaddr_incr[4]_i_1__0_n_0 ;
wire \axaddr_incr[5]_i_1__0_n_0 ;
wire \axaddr_incr[6]_i_1__0_n_0 ;
wire \axaddr_incr[7]_i_1__0_n_0 ;
wire \axaddr_incr[8]_i_1__0_n_0 ;
wire \axaddr_incr[9]_i_1__0_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire \axaddr_incr_reg[11]_i_4__0_n_1 ;
wire \axaddr_incr_reg[11]_i_4__0_n_2 ;
wire \axaddr_incr_reg[11]_i_4__0_n_3 ;
wire \axaddr_incr_reg[11]_i_4__0_n_4 ;
wire \axaddr_incr_reg[11]_i_4__0_n_5 ;
wire \axaddr_incr_reg[11]_i_4__0_n_6 ;
wire \axaddr_incr_reg[11]_i_4__0_n_7 ;
wire \axaddr_incr_reg[3]_i_3__0_n_0 ;
wire \axaddr_incr_reg[3]_i_3__0_n_1 ;
wire \axaddr_incr_reg[3]_i_3__0_n_2 ;
wire \axaddr_incr_reg[3]_i_3__0_n_3 ;
wire \axaddr_incr_reg[3]_i_3__0_n_4 ;
wire \axaddr_incr_reg[3]_i_3__0_n_5 ;
wire \axaddr_incr_reg[3]_i_3__0_n_6 ;
wire \axaddr_incr_reg[3]_i_3__0_n_7 ;
wire \axaddr_incr_reg[7]_i_3__0_n_0 ;
wire \axaddr_incr_reg[7]_i_3__0_n_1 ;
wire \axaddr_incr_reg[7]_i_3__0_n_2 ;
wire \axaddr_incr_reg[7]_i_3__0_n_3 ;
wire \axaddr_incr_reg[7]_i_3__0_n_4 ;
wire \axaddr_incr_reg[7]_i_3__0_n_5 ;
wire \axaddr_incr_reg[7]_i_3__0_n_6 ;
wire \axaddr_incr_reg[7]_i_3__0_n_7 ;
wire \axlen_cnt[0]_i_1_n_0 ;
wire \axlen_cnt[1]_i_1__1_n_0 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_2__1_n_0 ;
wire \axlen_cnt[4]_i_1__2_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[11] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire [9:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__1_n_0;
wire next_pending_r_i_4_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire [0:0]sel_first_reg_1;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_7 ),
.O(\axaddr_incr[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1__0
(.I0(O[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_5 ),
.O(\axaddr_incr[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2__0
(.I0(O[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_4 ),
.O(\axaddr_incr[11]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_6 ),
.O(\axaddr_incr[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_5 ),
.O(\axaddr_incr[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0202010202020202))
\axaddr_incr[3]_i_10
(.I0(\m_payload_i_reg[46] [0]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(Q[3]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(Q[2]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(Q[1]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(Q[0]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_4 ),
.O(\axaddr_incr[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA6AAAAAAAAAAA))
\axaddr_incr[3]_i_7
(.I0(\m_payload_i_reg[46] [3]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[3]));
LUT6 #(
.INIT(64'h2A2A262A2A2A2A2A))
\axaddr_incr[3]_i_8
(.I0(\m_payload_i_reg[46] [2]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[2]));
LUT6 #(
.INIT(64'h0A0A060A0A0A0A0A))
\axaddr_incr[3]_i_9
(.I0(\m_payload_i_reg[46] [1]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1__0
(.I0(\m_payload_i_reg[7] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_7 ),
.O(\axaddr_incr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1__0
(.I0(\m_payload_i_reg[7] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_6 ),
.O(\axaddr_incr[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1__0
(.I0(\m_payload_i_reg[7] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_5 ),
.O(\axaddr_incr[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1__0
(.I0(\m_payload_i_reg[7] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_4 ),
.O(\axaddr_incr[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1__0
(.I0(O[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_7 ),
.O(\axaddr_incr[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1__0
(.I0(O[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_6 ),
.O(\axaddr_incr[9]_i_1__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[11]_i_2__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4__0
(.CI(\axaddr_incr_reg[7]_i_3__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4__0_n_1 ,\axaddr_incr_reg[11]_i_4__0_n_2 ,\axaddr_incr_reg[11]_i_4__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4__0_n_4 ,\axaddr_incr_reg[11]_i_4__0_n_5 ,\axaddr_incr_reg[11]_i_4__0_n_6 ,\axaddr_incr_reg[11]_i_4__0_n_7 }),
.S(Q[11:8]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3__0_n_0 ,\axaddr_incr_reg[3]_i_3__0_n_1 ,\axaddr_incr_reg[3]_i_3__0_n_2 ,\axaddr_incr_reg[3]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI(Q[3:0]),
.O({\axaddr_incr_reg[3]_i_3__0_n_4 ,\axaddr_incr_reg[3]_i_3__0_n_5 ,\axaddr_incr_reg[3]_i_3__0_n_6 ,\axaddr_incr_reg[3]_i_3__0_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3__0
(.CI(\axaddr_incr_reg[3]_i_3__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3__0_n_0 ,\axaddr_incr_reg[7]_i_3__0_n_1 ,\axaddr_incr_reg[7]_i_3__0_n_2 ,\axaddr_incr_reg[7]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3__0_n_4 ,\axaddr_incr_reg[7]_i_3__0_n_5 ,\axaddr_incr_reg[7]_i_3__0_n_6 ,\axaddr_incr_reg[7]_i_3__0_n_7 }),
.S(Q[7:4]));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h20FF2020))
\axlen_cnt[0]_i_1
(.I0(si_rs_arvalid),
.I1(\state_reg[0]_rep ),
.I2(\m_payload_i_reg[46] [7]),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[46] [8]),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[1]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[46] [9]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_2__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h55545555))
\axlen_cnt[3]_i_3__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.I4(next_pending_r_i_4_n_0),
.O(\axlen_cnt_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[4]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[4] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hA6))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt[7]_i_3__0_n_0 ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_2__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[1] ));
LUT2 #(
.INIT(4'hB))
\m_axi_araddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\m_payload_i_reg[46] [6]),
.O(\m_axi_araddr[11] ));
LUT5 #(
.INIT(32'hFFFF505C))
next_pending_r_i_1__2
(.I0(next_pending_r_i_2__1_n_0),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(E),
.I4(\m_payload_i_reg[44] ),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0002))
next_pending_r_i_2__1
(.I0(next_pending_r_i_4_n_0),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[6] ),
.O(next_pending_r_i_2__1_n_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_4
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_4_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_r_channel
(m_valid_i_reg,
\state_reg[1]_rep ,
m_axi_rready,
out,
\skid_buffer_reg[46] ,
r_push,
aclk,
r_rlast,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output m_axi_rready;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input r_push;
input aclk;
input r_rlast;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_3;
wire rd_data_fifo_0_n_5;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire [12:0]trans_in;
wire transaction_fifo_0_n_2;
wire wr_en0;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_push),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[3]_rep__0_0 (m_valid_i_reg),
.\cnt_read_reg[3]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_3),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.s_ready_i_reg_0(transaction_fifo_0_n_2),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_5),
.wr_en0(wr_en0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__2 (rd_data_fifo_0_n_5),
.\cnt_read_reg[2]_rep__2 (rd_data_fifo_0_n_3),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (transaction_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wr_en0(wr_en0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm
(\axlen_cnt_reg[7] ,
Q,
D,
\wrap_cnt_r_reg[0] ,
\axaddr_offset_r_reg[0] ,
E,
\wrap_second_len_r_reg[3] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
s_axburst_eq1_reg,
r_push_r_reg,
\axlen_cnt_reg[4] ,
sel_first_reg,
sel_first_reg_0,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\axaddr_incr_reg[0] ,
m_axi_arvalid,
m_valid_i0,
\m_payload_i_reg[0]_1 ,
m_axi_arready,
si_rs_arvalid,
\axlen_cnt_reg[6] ,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[2] ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[47] ,
\m_payload_i_reg[35]_0 ,
\axaddr_offset_r_reg[3] ,
\m_payload_i_reg[44] ,
\m_payload_i_reg[3] ,
incr_next_pending,
\m_payload_i_reg[44]_0 ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
sel_first_reg_1,
areset_d1,
sel_first,
sel_first_reg_2,
s_axi_arvalid,
s_ready_i_reg,
aclk);
output \axlen_cnt_reg[7] ;
output [1:0]Q;
output [2:0]D;
output \wrap_cnt_r_reg[0] ;
output [0:0]\axaddr_offset_r_reg[0] ;
output [0:0]E;
output [1:0]\wrap_second_len_r_reg[3] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output s_axburst_eq1_reg;
output r_push_r_reg;
output [0:0]\axlen_cnt_reg[4] ;
output sel_first_reg;
output sel_first_reg_0;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [0:0]\axaddr_incr_reg[0] ;
output m_axi_arvalid;
output m_valid_i0;
output [0:0]\m_payload_i_reg[0]_1 ;
input m_axi_arready;
input si_rs_arvalid;
input \axlen_cnt_reg[6] ;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__0 ;
input [1:0]\wrap_second_len_r_reg[3]_0 ;
input [1:0]\wrap_second_len_r_reg[2] ;
input \m_payload_i_reg[35] ;
input [1:0]\m_payload_i_reg[47] ;
input \m_payload_i_reg[35]_0 ;
input [1:0]\axaddr_offset_r_reg[3] ;
input [1:0]\m_payload_i_reg[44] ;
input \m_payload_i_reg[3] ;
input incr_next_pending;
input \m_payload_i_reg[44]_0 ;
input \axlen_cnt_reg[3] ;
input next_pending_r_reg;
input sel_first_reg_1;
input areset_d1;
input sel_first;
input sel_first_reg_2;
input s_axi_arvalid;
input s_ready_i_reg;
input aclk;
wire [2:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [0:0]\axaddr_incr_reg[0] ;
wire [0:0]\axaddr_offset_r_reg[0] ;
wire [1:0]\axaddr_offset_r_reg[3] ;
wire \axlen_cnt_reg[3] ;
wire [0:0]\axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[6] ;
wire \axlen_cnt_reg[7] ;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [1:0]\m_payload_i_reg[44] ;
wire \m_payload_i_reg[44]_0 ;
wire [1:0]\m_payload_i_reg[47] ;
wire m_valid_i0;
wire next_pending_r_reg;
wire [1:0]next_state;
wire r_push_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire s_axi_arvalid;
wire s_ready_i_reg;
wire sel_first;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire \wrap_cnt_r[3]_i_2__0_n_0 ;
wire \wrap_cnt_r_reg[0] ;
wire wrap_next_pending;
wire [1:0]\wrap_second_len_r_reg[2] ;
wire [1:0]\wrap_second_len_r_reg[3] ;
wire [1:0]\wrap_second_len_r_reg[3]_0 ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAEAA))
\axaddr_incr[11]_i_1__0
(.I0(sel_first),
.I1(\m_payload_i_reg[0]_0 ),
.I2(\m_payload_i_reg[0] ),
.I3(m_axi_arready),
.O(\axaddr_incr_reg[0] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [0]),
.I1(\m_payload_i_reg[44] [1]),
.I2(Q[0]),
.I3(si_rs_arvalid),
.I4(Q[1]),
.I5(\m_payload_i_reg[3] ),
.O(\axaddr_offset_r_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h0E02))
\axlen_cnt[3]_i_1
(.I0(si_rs_arvalid),
.I1(Q[0]),
.I2(Q[1]),
.I3(m_axi_arready),
.O(\axlen_cnt_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00002320))
\axlen_cnt[7]_i_1
(.I0(m_axi_arready),
.I1(Q[1]),
.I2(Q[0]),
.I3(si_rs_arvalid),
.I4(\axlen_cnt_reg[6] ),
.O(\axlen_cnt_reg[7] ));
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[31]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.O(\m_payload_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFF70FFFF))
m_valid_i_i_1__1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.I3(s_axi_arvalid),
.I4(s_ready_i_reg),
.O(m_valid_i0));
LUT5 #(
.INIT(32'hFFABEEAA))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[44]_0 ),
.I1(r_push_r_reg),
.I2(E),
.I3(\axlen_cnt_reg[3] ),
.I4(next_pending_r_reg),
.O(wrap_next_pending));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h20))
r_push_r_i_1
(.I0(m_axi_arready),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[44] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[44] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__2
(.I0(m_axi_arready),
.I1(sel_first_reg_1),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__4
(.I0(m_axi_arready),
.I1(sel_first_reg_2),
.I2(\m_payload_i_reg[0] ),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_i));
LUT6 #(
.INIT(64'h0000770000FFFFF0))
\state[0]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(m_axi_arready),
.I2(si_rs_arvalid),
.I3(Q[0]),
.I4(Q[1]),
.I5(\cnt_read_reg[1]_rep__0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h0FC00040))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.I4(\cnt_read_reg[1]_rep__0 ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(E));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(\axaddr_offset_r_reg[0] ),
.O(D[0]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[2] [1]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(E),
.I3(\wrap_cnt_r_reg[0] ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\wrap_second_len_r_reg[2] [0]),
.O(D[1]));
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_second_len_r_reg[2] [0]),
.I2(\wrap_cnt_r[3]_i_2__0_n_0 ),
.I3(\wrap_second_len_r_reg[2] [1]),
.O(D[2]));
LUT6 #(
.INIT(64'hD1D1D1D1D1D1DFD1))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[47] [1]),
.I5(\m_payload_i_reg[47] [0]),
.O(\wrap_cnt_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(\axaddr_offset_r_reg[0] ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'h0000000004000404))
\wrap_second_len_r[0]_i_2__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(\m_payload_i_reg[35] ),
.I2(\m_payload_i_reg[35]_0 ),
.I3(E),
.I4(\axaddr_offset_r_reg[3] [1]),
.I5(\m_payload_i_reg[47] [0]),
.O(\wrap_cnt_r_reg[0] ));
LUT6 #(
.INIT(64'hFB00FFFFFB00FB00))
\wrap_second_len_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(\m_payload_i_reg[35] ),
.I2(\m_payload_i_reg[47] [0]),
.I3(\m_payload_i_reg[35]_0 ),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__0_0 ,
\state_reg[0]_rep ,
bvalid_i_reg,
SR,
D,
bresp_push,
out,
b_push,
shandshake_r,
areset_d1,
si_rs_bvalid,
si_rs_bready,
Q,
\bresp_cnt_reg[7] ,
mhandshake_r,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__0_0 ;
output \state_reg[0]_rep ;
output bvalid_i_reg;
output [0:0]SR;
output [0:0]D;
output bresp_push;
output [11:0]out;
input b_push;
input shandshake_r;
input areset_d1;
input si_rs_bvalid;
input si_rs_bready;
input [1:0]Q;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input [15:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire \bresp_cnt[7]_i_3_n_0 ;
wire \bresp_cnt[7]_i_4_n_0 ;
wire \bresp_cnt[7]_i_5_n_0 ;
wire \bresp_cnt[7]_i_6_n_0 ;
wire [7:0]\bresp_cnt_reg[7] ;
wire bresp_push;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [15:0]in;
wire \memory_reg[3][0]_srl4_i_2__0_n_0 ;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire \state_reg[0]_rep ;
LUT5 #(
.INIT(32'hAAABAAAA))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(\bresp_cnt[7]_i_4_n_0 ),
.I3(\bresp_cnt[7]_i_5_n_0 ),
.I4(\bresp_cnt[7]_i_6_n_0 ),
.O(SR));
LUT6 #(
.INIT(64'h22F2FFFF22F222F2))
\bresp_cnt[7]_i_3
(.I0(\memory_reg[3][1]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [1]),
.I2(\bresp_cnt_reg[7] [3]),
.I3(\memory_reg[3][3]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [0]),
.I5(\memory_reg[3][0]_srl4_n_0 ),
.O(\bresp_cnt[7]_i_3_n_0 ));
LUT5 #(
.INIT(32'hAEAEFFAE))
\bresp_cnt[7]_i_4
(.I0(\bresp_cnt_reg[7] [4]),
.I1(\bresp_cnt_reg[7] [1]),
.I2(\memory_reg[3][1]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [0]),
.I4(\memory_reg[3][0]_srl4_n_0 ),
.O(\bresp_cnt[7]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT5 #(
.INIT(32'hEAFFEAEA))
\bresp_cnt[7]_i_5
(.I0(\bresp_cnt_reg[7] [6]),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.I2(\cnt_read_reg[1]_rep__0_0 ),
.I3(\bresp_cnt_reg[7] [3]),
.I4(\memory_reg[3][3]_srl4_n_0 ),
.O(\bresp_cnt[7]_i_5_n_0 ));
LUT5 #(
.INIT(32'h00004004))
\bresp_cnt[7]_i_6
(.I0(\bresp_cnt_reg[7] [5]),
.I1(mhandshake_r),
.I2(\bresp_cnt_reg[7] [2]),
.I3(\memory_reg[3][2]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [7]),
.O(\bresp_cnt[7]_i_6_n_0 ));
LUT4 #(
.INIT(16'h0444))
bvalid_i_i_1
(.I0(areset_d1),
.I1(bvalid_i_i_2_n_0),
.I2(si_rs_bvalid),
.I3(si_rs_bready),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(\cnt_read_reg[1]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[0]),
.I4(Q[1]),
.I5(si_rs_bvalid),
.O(bvalid_i_i_2_n_0));
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1
(.I0(bresp_push),
.I1(Q[0]),
.I2(shandshake_r),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
LUT6 #(
.INIT(64'h0000000000004100))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\bresp_cnt_reg[7] [7]),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\bresp_cnt_reg[7] [2]),
.I3(mhandshake_r),
.I4(\bresp_cnt_reg[7] [5]),
.I5(\memory_reg[3][0]_srl4_i_2__0_n_0 ),
.O(bresp_push));
LUT6 #(
.INIT(64'hFFFEFFFFFFFEFFFE))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\bresp_cnt[7]_i_3_n_0 ),
.I1(\bresp_cnt[7]_i_4_n_0 ),
.I2(\bresp_cnt_reg[7] [6]),
.I3(\memory_reg[3][0]_srl4_i_3_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][3]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT2 #(
.INIT(4'h8))
\memory_reg[3][0]_srl4_i_3
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(\cnt_read_reg[1]_rep__0_0 ),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(out[1]));
LUT2 #(
.INIT(4'h2))
\state[0]_i_2
(.I0(\cnt_read_reg[1]_rep__0_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.O(\state_reg[0]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0
(mhandshake,
Q,
m_axi_bready,
\skid_buffer_reg[1] ,
m_axi_bvalid,
mhandshake_r,
shandshake_r,
sel,
in,
aclk,
areset_d1,
D);
output mhandshake;
output [1:0]Q;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input m_axi_bvalid;
input mhandshake_r;
input shandshake_r;
input sel;
input [1:0]in;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire sel;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT4 #(
.INIT(16'h9AA6))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(shandshake_r),
.I2(Q[0]),
.I3(sel),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[0]),
.I1(Q[1]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[1]),
.I3(Q[0]),
.O(mhandshake));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1
(\cnt_read_reg[3]_rep__2_0 ,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
si_rs_rready,
\cnt_read_reg[3]_rep__0_0 ,
s_ready_i_reg_0,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[3]_rep__2_0 ;
output wr_en0;
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input si_rs_rready;
input \cnt_read_reg[3]_rep__0_0 ;
input s_ready_i_reg_0;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_2__0_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep__2_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(wr_en0),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hA96A))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(wr_en0),
.I3(s_ready_i_reg),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hA6AAAA9A))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(wr_en0),
.I2(s_ready_i_reg),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.I4(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA96AAAAAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[0]_rep__2_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(wr_en0),
.I5(s_ready_i_reg),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAA55AA6A6AAA6AAA))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read[4]_i_2__0_n_0 ),
.I2(\cnt_read[4]_i_3_n_0 ),
.I3(s_ready_i_reg_0),
.I4(\cnt_read_reg[4]_rep__2_1 ),
.I5(\cnt_read_reg[3]_rep__2_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0004))
\cnt_read[4]_i_2__0
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(si_rs_rready),
.I2(\cnt_read_reg[3]_rep__0_0 ),
.I3(wr_en0),
.O(\cnt_read[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_3
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_1 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hF77F777F))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read_reg[3]_rep__2_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hAA2A2AAA2A2A2AAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[3]_rep__2_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[1]_rep__2_n_0 ),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h7C000000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.I3(\cnt_read_reg[3]_rep__2_0 ),
.I4(\cnt_read_reg[4]_rep__2_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2
(m_valid_i_reg,
\state_reg[1]_rep ,
\cnt_read_reg[4]_rep__2 ,
\skid_buffer_reg[46] ,
si_rs_rready,
r_push_r,
s_ready_i_reg,
\cnt_read_reg[0]_rep__2 ,
wr_en0,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[2]_rep__2 ,
in,
aclk,
areset_d1);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output \cnt_read_reg[4]_rep__2 ;
output [12:0]\skid_buffer_reg[46] ;
input si_rs_rready;
input r_push_r;
input s_ready_i_reg;
input \cnt_read_reg[0]_rep__2 ;
input wr_en0;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[4]_rep__2_0 ;
input \cnt_read_reg[2]_rep__2 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__2 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_i_3_n_0;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__1_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[0]_rep__1_n_0 ),
.I1(r_push_r),
.I2(s_ready_i_reg),
.I3(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[1]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hFE7F0180))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hDFFFFFFB20000004))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[2]_rep__0_n_0 ),
.I5(\cnt_read_reg[3]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h9AAA9AAA9AAA9AA6))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read_reg[2]_rep__0_n_0 ),
.I3(\cnt_read_reg[3]_rep__0_n_0 ),
.I4(\cnt_read[4]_i_3__0_n_0 ),
.I5(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h5DFFFFFF))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(r_push_r),
.I4(\cnt_read_reg[0]_rep__1_n_0 ),
.O(\cnt_read[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'hFFEF))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(m_valid_i_reg),
.I2(si_rs_rready),
.I3(r_push_r),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h4F))
\cnt_read[4]_i_4
(.I0(m_valid_i_reg),
.I1(si_rs_rready),
.I2(wr_en0),
.O(\cnt_read_reg[4]_rep__2 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT6 #(
.INIT(64'hFF08080808080808))
m_valid_i_i_2
(.I0(\cnt_read_reg[3]_rep__0_n_0 ),
.I1(\cnt_read_reg[4]_rep__0_n_0 ),
.I2(m_valid_i_i_3_n_0),
.I3(\cnt_read_reg[3]_rep__2 ),
.I4(\cnt_read_reg[4]_rep__2_0 ),
.I5(\cnt_read_reg[2]_rep__2 ),
.O(m_valid_i_reg));
LUT3 #(
.INIT(8'h7F))
m_valid_i_i_3
(.I0(\cnt_read_reg[0]_rep__1_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.O(m_valid_i_i_3_n_0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBEAAAAAAFEAAAAAA))
\state[1]_i_3
(.I0(\cnt_read_reg[0]_rep__2 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[2]_rep__0_n_0 ),
.I3(\cnt_read_reg[4]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm
(E,
Q,
\axlen_cnt_reg[0] ,
\wrap_boundary_axaddr_r_reg[0] ,
\axlen_cnt_reg[7] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
sel_first_reg,
sel_first_reg_0,
m_axi_awvalid,
\m_payload_i_reg[0] ,
b_push,
si_rs_awvalid,
\axlen_cnt_reg[6] ,
\m_payload_i_reg[39] ,
\m_payload_i_reg[46] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axlen_cnt_reg[1] ,
sel_first,
areset_d1,
sel_first_0,
sel_first_reg_1,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__0 ,
m_axi_awready,
\cnt_read_reg[1]_rep__0_0 ,
\cnt_read_reg[0]_rep__0 ,
aclk);
output [0:0]E;
output [1:0]Q;
output \axlen_cnt_reg[0] ;
output [0:0]\wrap_boundary_axaddr_r_reg[0] ;
output \axlen_cnt_reg[7] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output sel_first_reg;
output sel_first_reg_0;
output m_axi_awvalid;
output [0:0]\m_payload_i_reg[0] ;
output b_push;
input si_rs_awvalid;
input \axlen_cnt_reg[6] ;
input [0:0]\m_payload_i_reg[39] ;
input \m_payload_i_reg[46] ;
input next_pending_r_reg;
input next_pending_r_reg_0;
input \axlen_cnt_reg[1] ;
input sel_first;
input areset_d1;
input sel_first_0;
input sel_first_reg_1;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__0 ;
input m_axi_awready;
input \cnt_read_reg[1]_rep__0_0 ;
input \cnt_read_reg[0]_rep__0 ;
input aclk;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axlen_cnt_reg[0] ;
wire \axlen_cnt_reg[1] ;
wire \axlen_cnt_reg[6] ;
wire \axlen_cnt_reg[7] ;
wire b_push;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]\m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[39] ;
wire \m_payload_i_reg[46] ;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [1:0]next_state;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire si_rs_awvalid;
wire \state_reg[0]_rep_n_0 ;
wire \state_reg[1]_rep_n_0 ;
wire [0:0]\wrap_boundary_axaddr_r_reg[0] ;
wire wrap_next_pending;
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'h04FF))
\axlen_cnt[3]_i_1__0
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[0] ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT5 #(
.INIT(32'h000004FF))
\axlen_cnt[7]_i_1__0
(.I0(\state_reg[0]_rep_n_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[1]_rep_n_0 ),
.I3(\axlen_cnt_reg[0] ),
.I4(\axlen_cnt_reg[6] ),
.O(\axlen_cnt_reg[7] ));
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(\state_reg[0]_rep_n_0 ),
.I1(\state_reg[1]_rep_n_0 ),
.O(m_axi_awvalid));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(b_push),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0] ));
LUT6 #(
.INIT(64'hCFCF000045000000))
\memory_reg[3][0]_srl4_i_1
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[0]_rep__0 ),
.I2(\cnt_read_reg[1]_rep__0_0 ),
.I3(m_axi_awready),
.I4(\state_reg[0]_rep_n_0 ),
.I5(\state_reg[1]_rep_n_0 ),
.O(b_push));
LUT5 #(
.INIT(32'hB8BBB888))
next_pending_r_i_1
(.I0(\m_payload_i_reg[46] ),
.I1(\wrap_boundary_axaddr_r_reg[0] ),
.I2(next_pending_r_reg),
.I3(\axlen_cnt_reg[0] ),
.I4(\axlen_cnt_reg[6] ),
.O(incr_next_pending));
LUT5 #(
.INIT(32'hB888B8BB))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[46] ),
.I1(\wrap_boundary_axaddr_r_reg[0] ),
.I2(next_pending_r_reg_0),
.I3(\axlen_cnt_reg[0] ),
.I4(\axlen_cnt_reg[1] ),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'h5555DD551515DD15))
next_pending_r_i_3
(.I0(\state_reg[1]_rep_n_0 ),
.I1(\state_reg[0]_rep_n_0 ),
.I2(m_axi_awready),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.I4(\cnt_read_reg[0]_rep__0 ),
.I5(s_axburst_eq1_reg_0),
.O(\axlen_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[39] ),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[39] ),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFFFFFFF88888F88))
sel_first_i_1
(.I0(\axlen_cnt_reg[0] ),
.I1(sel_first),
.I2(\state_reg[1]_rep_n_0 ),
.I3(si_rs_awvalid),
.I4(\state_reg[0]_rep_n_0 ),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF88888F88))
sel_first_i_1__0
(.I0(\axlen_cnt_reg[0] ),
.I1(sel_first_0),
.I2(\state_reg[1]_rep_n_0 ),
.I3(si_rs_awvalid),
.I4(\state_reg[0]_rep_n_0 ),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFFFFFFFF88888F88))
sel_first_i_1__1
(.I0(\axlen_cnt_reg[0] ),
.I1(sel_first_reg_1),
.I2(\state_reg[1]_rep_n_0 ),
.I3(si_rs_awvalid),
.I4(\state_reg[0]_rep_n_0 ),
.I5(areset_d1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hAEFE0E0EFEFE5E5E))
\state[0]_i_1
(.I0(\state_reg[1]_rep_n_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[0]_rep_n_0 ),
.I3(s_axburst_eq1_reg_0),
.I4(\cnt_read_reg[1]_rep__0 ),
.I5(m_axi_awready),
.O(next_state[0]));
LUT6 #(
.INIT(64'h2E220E0000000000))
\state[1]_i_1
(.I0(m_axi_awready),
.I1(\state_reg[1]_rep_n_0 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.I4(s_axburst_eq1_reg_0),
.I5(\state_reg[0]_rep_n_0 ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\state_reg[0]_rep_n_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\state_reg[1]_rep_n_0 ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\state_reg[1]_rep_n_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[0]_rep_n_0 ),
.O(\wrap_boundary_axaddr_r_reg[0] ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
Q,
si_rs_awvalid,
\m_payload_i_reg[46] ,
\m_payload_i_reg[47] ,
\state_reg[1]_rep ,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
sel_first_reg_3,
sel_first_reg_4,
D,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[0] ,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [1:0]Q;
input si_rs_awvalid;
input [17:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[47] ;
input \state_reg[1]_rep ;
input sel_first_reg_2;
input [9:0]\axaddr_incr_reg[11] ;
input sel_first_reg_3;
input sel_first_reg_4;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire [9:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_3_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_2_n_1 ;
wire \axaddr_wrap_reg[11]_i_2_n_2 ;
wire \axaddr_wrap_reg[11]_i_2_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_2_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire [11:0]m_axi_awaddr;
wire [17:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[1]_rep ;
wire [11:0]wrap_boundary_axaddr_r;
wire [3:0]wrap_cnt_r;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[0]_i_1
(.I0(\m_payload_i_reg[46] [0]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[0]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[10]_i_1
(.I0(\m_payload_i_reg[46] [10]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[10]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[11]_i_1
(.I0(\m_payload_i_reg[46] [11]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[11]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFFF6))
\axaddr_wrap[11]_i_3
(.I0(wrap_cnt_r[3]),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axaddr_wrap[11]_i_4_n_0 ),
.I3(\axlen_cnt_reg_n_0_[4] ),
.O(\axaddr_wrap[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(wrap_cnt_r[1]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(wrap_cnt_r[2]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[1]_i_1
(.I0(\m_payload_i_reg[46] [1]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[1]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[2]_i_1
(.I0(\m_payload_i_reg[46] [2]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[2]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[3]_i_1
(.I0(\m_payload_i_reg[46] [3]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[3]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[46] [13]),
.I2(\m_payload_i_reg[46] [12]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[46] [12]),
.I2(\m_payload_i_reg[46] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[46] [13]),
.I2(\m_payload_i_reg[46] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[46] [13]),
.I2(\m_payload_i_reg[46] [12]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[4]_i_1
(.I0(\m_payload_i_reg[46] [4]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[4]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[5]_i_1
(.I0(\m_payload_i_reg[46] [5]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[5]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[6]_i_1
(.I0(\m_payload_i_reg[46] [6]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[6]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[7]_i_1
(.I0(\m_payload_i_reg[46] [7]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[7]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[8]_i_1
(.I0(\m_payload_i_reg[46] [8]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[8]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[9]_i_1
(.I0(\m_payload_i_reg[46] [9]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[9]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_2
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_2_n_1 ,\axaddr_wrap_reg[11]_i_2_n_2 ,\axaddr_wrap_reg[11]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S(axaddr_wrap[11:8]));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S(axaddr_wrap[7:4]));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h44444F4444444444))
\axlen_cnt[0]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[0] ),
.I1(\axlen_cnt[3]_i_2_n_0 ),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(\m_payload_i_reg[46] [15]),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[46] [16]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt[3]_i_2_n_0 ),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[46] [17]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt[3]_i_2_n_0 ),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt[3]_i_2_n_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT5 #(
.INIT(32'h55555554))
\axlen_cnt[3]_i_2
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h4444444444444440))
\axlen_cnt[4]_i_1__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [8]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [9]),
.O(m_axi_awaddr[11]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[1]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [1]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_awaddr[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[2]_INST_0
(.I0(\m_payload_i_reg[46] [2]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[2]),
.I3(\m_payload_i_reg[46] [14]),
.I4(sel_first_reg_4),
.O(m_axi_awaddr[2]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[3]_INST_0
(.I0(\m_payload_i_reg[46] [3]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[3]),
.I3(\m_payload_i_reg[46] [14]),
.I4(sel_first_reg_3),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[5]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [5]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_awaddr[9]));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_2__0
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_wrap_cmd" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3
(next_pending_r_reg_0,
sel_first_reg_0,
\axlen_cnt_reg[0]_0 ,
m_axi_araddr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
Q,
\state_reg[1]_rep ,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
si_rs_arvalid,
\state_reg[0]_rep ,
\axaddr_offset_r_reg[3]_1 ,
\m_payload_i_reg[35] ,
D,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output \axlen_cnt_reg[0]_0 ;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input \m_payload_i_reg[47] ;
input [17:0]Q;
input \state_reg[1]_rep ;
input sel_first_reg_2;
input [11:0]\axaddr_incr_reg[11] ;
input si_rs_arvalid;
input \state_reg[0]_rep ;
input \axaddr_offset_r_reg[3]_1 ;
input \m_payload_i_reg[35] ;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [17:0]Q;
wire aclk;
wire [11:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_3__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__0_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__2_n_0 ;
wire \axlen_cnt[4]_i_1__1_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r[1]_i_1_n_0 ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I3(\state_reg[1]_rep ),
.I4(Q[0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_5 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I3(\state_reg[1]_rep ),
.I4(Q[10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_4 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I3(\state_reg[1]_rep ),
.I4(Q[11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'hFFF6))
\axaddr_wrap[11]_i_3__0
(.I0(\wrap_cnt_r_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axaddr_wrap[11]_i_4__0_n_0 ),
.I3(\axlen_cnt_reg_n_0_[4] ),
.O(\axaddr_wrap[11]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\wrap_cnt_r_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\wrap_cnt_r_reg_n_0_[1] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I3(\state_reg[1]_rep ),
.I4(Q[1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I3(\state_reg[1]_rep ),
.I4(Q[2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I3(\state_reg[1]_rep ),
.I4(Q[3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I3(\state_reg[1]_rep ),
.I4(Q[4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I3(\state_reg[1]_rep ),
.I4(Q[5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I3(\state_reg[1]_rep ),
.I4(Q[6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I3(\state_reg[1]_rep ),
.I4(Q[7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_7 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I3(\state_reg[1]_rep ),
.I4(Q[8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_6 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I3(\state_reg[1]_rep ),
.I4(Q[9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_2__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_2__0_n_1 ,\axaddr_wrap_reg[11]_i_2__0_n_2 ,\axaddr_wrap_reg[11]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_2__0_n_4 ,\axaddr_wrap_reg[11]_i_2__0_n_5 ,\axaddr_wrap_reg[11]_i_2__0_n_6 ,\axaddr_wrap_reg[11]_i_2__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[11] ,\axaddr_wrap_reg_n_0_[10] ,\axaddr_wrap_reg_n_0_[9] ,\axaddr_wrap_reg_n_0_[8] }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[7] ,\axaddr_wrap_reg_n_0_[6] ,\axaddr_wrap_reg_n_0_[5] ,\axaddr_wrap_reg_n_0_[4] }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h20FF2020))
\axlen_cnt[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(\state_reg[0]_rep ),
.I2(Q[15]),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__2
(.I0(E),
.I1(Q[16]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__2
(.I0(E),
.I1(Q[17]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h55555554))
\axlen_cnt[3]_i_2__2
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt_reg[0]_0 ));
LUT6 #(
.INIT(64'h4444444444444440))
\axlen_cnt[4]_i_1__1
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1__1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(Q[14]),
.I3(Q[0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(Q[14]),
.I3(Q[10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [10]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(Q[14]),
.I3(Q[11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [11]),
.O(m_axi_araddr[11]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[1] ),
.I2(Q[14]),
.I3(Q[1]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_araddr[1]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[2] ),
.I2(Q[14]),
.I3(Q[2]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[3] ),
.I2(Q[14]),
.I3(Q[3]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(Q[14]),
.I3(Q[4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_araddr[4]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[5] ),
.I2(Q[14]),
.I3(Q[5]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(Q[14]),
.I3(Q[6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(Q[14]),
.I3(Q[7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(Q[14]),
.I3(Q[8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [8]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(Q[14]),
.I3(Q[9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [9]),
.O(m_axi_araddr[9]));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(Q[10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(Q[11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(Q[7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(Q[8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(Q[9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h313D020E))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_1 ),
.I3(\m_payload_i_reg[35] ),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_cnt_r[1]_i_1_n_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_cnt_r[1]_i_1_n_0 ),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
D,
wrap_second_len,
axaddr_incr,
Q,
\axaddr_incr_reg[3] ,
\s_arid_r_reg[11] ,
\axaddr_incr_reg[7] ,
O,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
shandshake,
\wrap_second_len_r_reg[2] ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
next_pending_r_reg_0,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3]_0 ,
\cnt_read_reg[0]_rep__1 ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
m_valid_i0,
aresetn,
\cnt_read_reg[3]_rep__0 ,
s_axi_rready,
S,
\m_payload_i_reg[3] ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1] ,
\axaddr_offset_r_reg[3]_0 ,
s_axi_awvalid,
b_push,
si_rs_bvalid,
axaddr_offset_0,
\state_reg[1]_rep_0 ,
\wrap_second_len_r_reg[2]_0 ,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[1]_rep_1 ,
\state_reg[0]_rep ,
s_axi_bready,
s_axi_arvalid,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
E,
\state_reg[1]_rep_2 );
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output [3:0]D;
output [3:0]wrap_second_len;
output [11:0]axaddr_incr;
output [54:0]Q;
output [3:0]\axaddr_incr_reg[3] ;
output [53:0]\s_arid_r_reg[11] ;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [3:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output shandshake;
output [1:0]\wrap_second_len_r_reg[2] ;
output [2:0]\axaddr_offset_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output next_pending_r_reg_0;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3]_0 ;
output \cnt_read_reg[0]_rep__1 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input m_valid_i0;
input aresetn;
input \cnt_read_reg[3]_rep__0 ;
input s_axi_rready;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input \state_reg[1]_rep ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [1:0]\state_reg[1] ;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input s_axi_awvalid;
input b_push;
input si_rs_bvalid;
input [0:0]axaddr_offset_0;
input \state_reg[1]_rep_0 ;
input [1:0]\wrap_second_len_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[1]_rep_1 ;
input \state_reg[0]_rep ;
input s_axi_bready;
input s_axi_arvalid;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [0:0]E;
input [0:0]\state_reg[1]_rep_2 ;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [3:0]axaddr_offset;
wire [0:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [2:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[0]_rep__1 ;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \gen_simple_ar.ar_pipe_n_2 ;
wire \gen_simple_aw.aw_pipe_n_1 ;
wire \gen_simple_aw.aw_pipe_n_91 ;
wire [3:0]\m_payload_i_reg[3] ;
wire m_valid_i0;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [53:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire shandshake;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire [0:0]\state_reg[1]_rep_2 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire [3:0]wrap_second_len;
wire [1:0]\wrap_second_len_r_reg[2] ;
wire [1:0]\wrap_second_len_r_reg[2]_0 ;
wire \wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice \gen_simple_ar.ar_pipe
(.O(O),
.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (\gen_simple_aw.aw_pipe_n_1 ),
.\aresetn_d_reg[0]_0 (\gen_simple_aw.aw_pipe_n_91 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.axaddr_offset_0(axaddr_offset_0),
.\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0] ),
.\axaddr_offset_r_reg[1] (\axaddr_offset_r_reg[1] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i0(m_valid_i0),
.m_valid_i_reg_0(\gen_simple_ar.ar_pipe_n_2 ),
.next_pending_r_reg(next_pending_r_reg_0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1]_rep (\state_reg[1]_rep_0 ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_1 ),
.\state_reg[1]_rep_1 (\state_reg[1]_rep_2 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_second_len_r_reg[2] (\wrap_second_len_r_reg[2] ),
.\wrap_second_len_r_reg[2]_0 (\wrap_second_len_r_reg[2]_0 ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0 \gen_simple_aw.aw_pipe
(.D(D),
.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (\gen_simple_aw.aw_pipe_n_91 ),
.\aresetn_d_reg[1]_inv_0 (\gen_simple_ar.ar_pipe_n_2 ),
.axaddr_incr(axaddr_incr),
.axaddr_offset({axaddr_offset[2],axaddr_offset[0]}),
.\axaddr_offset_r_reg[1] (axaddr_offset[1]),
.\axaddr_offset_r_reg[3] (axaddr_offset[3]),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(\gen_simple_aw.aw_pipe_n_1 ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.wrap_second_len({wrap_second_len[3:2],wrap_second_len[0]}),
.\wrap_second_len_r_reg[1] (wrap_second_len[1]),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1 \gen_simple_b.b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\gen_simple_aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\gen_simple_ar.ar_pipe_n_2 ),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.shandshake(shandshake),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2 \gen_simple_r.r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\gen_simple_aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\gen_simple_ar.ar_pipe_n_2 ),
.\cnt_read_reg[0]_rep__1 (\cnt_read_reg[0]_rep__1 ),
.\cnt_read_reg[3]_rep__0 (\cnt_read_reg[3]_rep__0 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice
(s_axi_arready,
s_ready_i_reg_0,
m_valid_i_reg_0,
\axaddr_incr_reg[3] ,
Q,
\axaddr_incr_reg[7] ,
O,
\wrap_second_len_r_reg[2] ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
next_pending_r_reg,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\aresetn_d_reg[0] ,
aclk,
m_valid_i0,
\aresetn_d_reg[0]_0 ,
\m_payload_i_reg[3]_0 ,
axaddr_offset_0,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[2]_0 ,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep_0 ,
\state_reg[0]_rep ,
s_axi_arvalid,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
\state_reg[1]_rep_1 );
output s_axi_arready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output [53:0]Q;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]\wrap_second_len_r_reg[2] ;
output [2:0]\axaddr_offset_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output next_pending_r_reg;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
input \aresetn_d_reg[0] ;
input aclk;
input m_valid_i0;
input \aresetn_d_reg[0]_0 ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [0:0]axaddr_offset_0;
input \state_reg[1]_rep ;
input [1:0]\wrap_second_len_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep_0 ;
input \state_reg[0]_rep ;
input s_axi_arvalid;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [0:0]\state_reg[1]_rep_1 ;
wire [3:0]O;
wire [53:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[3]_i_4__0_n_0 ;
wire \axaddr_incr[3]_i_5__0_n_0 ;
wire \axaddr_incr[3]_i_6__0_n_0 ;
wire \axaddr_incr_reg[11]_i_3__0_n_1 ;
wire \axaddr_incr_reg[11]_i_3__0_n_2 ;
wire \axaddr_incr_reg[11]_i_3__0_n_3 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire \axaddr_incr_reg[3]_i_2__0_n_0 ;
wire \axaddr_incr_reg[3]_i_2__0_n_1 ;
wire \axaddr_incr_reg[3]_i_2__0_n_2 ;
wire \axaddr_incr_reg[3]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire \axaddr_incr_reg[7]_i_2__0_n_0 ;
wire \axaddr_incr_reg[7]_i_2__0_n_1 ;
wire \axaddr_incr_reg[7]_i_2__0_n_2 ;
wire \axaddr_incr_reg[7]_i_2__0_n_3 ;
wire [0:0]axaddr_offset_0;
wire \axaddr_offset_r[1]_i_3_n_0 ;
wire \axaddr_offset_r[2]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_3__0_n_0 ;
wire \axaddr_offset_r[3]_i_2__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire [2:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[52]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [3:3]si_rs_arlen;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [0:0]\state_reg[1]_rep_1 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [1:0]\wrap_second_len_r_reg[2] ;
wire [1:0]\wrap_second_len_r_reg[2]_0 ;
wire \wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4__0
(.I0(Q[2]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[3]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[3]_i_6__0_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3__0
(.CI(\axaddr_incr_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3__0_n_1 ,\axaddr_incr_reg[11]_i_3__0_n_2 ,\axaddr_incr_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2__0_n_0 ,\axaddr_incr_reg[3]_i_2__0_n_1 ,\axaddr_incr_reg[3]_i_2__0_n_2 ,\axaddr_incr_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4__0_n_0 ,\axaddr_incr[3]_i_5__0_n_0 ,\axaddr_incr[3]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[7]_i_2__0
(.CI(\axaddr_incr_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2__0_n_0 ,\axaddr_incr_reg[7]_i_2__0_n_1 ,\axaddr_incr_reg[7]_i_2__0_n_2 ,\axaddr_incr_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r_reg[0] ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.O(\axaddr_offset_r_reg[3] [0]));
LUT6 #(
.INIT(64'h1FDF00001FDFFFFF))
\axaddr_offset_r[1]_i_2
(.I0(\axaddr_offset_r[1]_i_3_n_0 ),
.I1(Q[35]),
.I2(Q[40]),
.I3(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [0]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_3
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [1]),
.O(\axaddr_offset_r_reg[3] [1]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3__0
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1__0
(.I0(si_rs_arlen),
.I1(\axaddr_offset_r[3]_i_2__0_n_0 ),
.I2(\state_reg[1]_rep_0 ),
.I3(s_ready_i_reg_0),
.I4(\state_reg[0]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [2]),
.O(\axaddr_offset_r_reg[3] [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_4
(.I0(si_rs_arlen),
.I1(\state_reg[0]_rep ),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\axlen_cnt_reg[3] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(\m_payload_i[52]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(si_rs_arlen),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[52]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_3__0
(.I0(\state_reg[1]_rep ),
.I1(Q[39]),
.I2(si_rs_arlen),
.I3(Q[40]),
.I4(Q[41]),
.O(next_pending_r_reg));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[0]_rep ),
.I4(s_ready_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'h8888082AAAAA082A))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[40]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(si_rs_arlen),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h002AA02A0A2AAA2A))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[4]),
.I1(si_rs_arlen),
.I2(Q[35]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(si_rs_arlen),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[35]),
.I3(si_rs_arlen),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'h0EF0FFFF0EF00000))
\wrap_second_len_r[1]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [1]),
.I1(\axaddr_offset_r_reg[3] [2]),
.I2(axaddr_offset_0),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[2]_0 [0]),
.O(\wrap_second_len_r_reg[2] [0]));
LUT6 #(
.INIT(64'hAA4AFFFFAA4A0000))
\wrap_second_len_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [1]),
.I1(\axaddr_offset_r_reg[3] [2]),
.I2(\axaddr_offset_r_reg[1] ),
.I3(axaddr_offset_0),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[2]_0 [1]),
.O(\wrap_second_len_r_reg[2] [1]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r_reg[3] ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_14_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
D,
\wrap_second_len_r_reg[1] ,
axaddr_incr,
Q,
wrap_second_len,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[3] ,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
\wrap_boundary_axaddr_r_reg[6] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
S,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[3] ,
\state_reg[1] ,
\axaddr_offset_r_reg[3]_0 ,
s_axi_awvalid,
b_push,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [3:0]D;
output \wrap_second_len_r_reg[1] ;
output [11:0]axaddr_incr;
output [54:0]Q;
output [2:0]wrap_second_len;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[3] ;
output [1:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input [3:0]S;
input \state_reg[1]_rep ;
input [3:0]\wrap_second_len_r_reg[3] ;
input [1:0]\state_reg[1] ;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input s_axi_awvalid;
input b_push;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [0:0]E;
wire [3:0]D;
wire [0:0]E;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire [11:0]axaddr_incr;
wire \axaddr_incr[3]_i_4_n_0 ;
wire \axaddr_incr[3]_i_5_n_0 ;
wire \axaddr_incr[3]_i_6_n_0 ;
wire \axaddr_incr_reg[11]_i_3_n_1 ;
wire \axaddr_incr_reg[11]_i_3_n_2 ;
wire \axaddr_incr_reg[11]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_2_n_0 ;
wire \axaddr_incr_reg[3]_i_2_n_1 ;
wire \axaddr_incr_reg[3]_i_2_n_2 ;
wire \axaddr_incr_reg[3]_i_2_n_3 ;
wire \axaddr_incr_reg[7]_i_2_n_0 ;
wire \axaddr_incr_reg[7]_i_2_n_1 ;
wire \axaddr_incr_reg[7]_i_2_n_2 ;
wire \axaddr_incr_reg[7]_i_2_n_3 ;
wire [1:0]axaddr_offset;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[0]_i_3_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_3_n_0 ;
wire \axaddr_offset_r[2]_i_4_n_0 ;
wire \axaddr_offset_r[3]_i_2_n_0 ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [61:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_2_n_0 ;
wire \wrap_cnt_r[3]_i_3_n_0 ;
wire [2:0]wrap_second_len;
wire \wrap_second_len_r[0]_i_2_n_0 ;
wire \wrap_second_len_r[0]_i_3_n_0 ;
wire \wrap_second_len_r[0]_i_4_n_0 ;
wire \wrap_second_len_r[0]_i_5_n_0 ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire \wrap_second_len_r_reg[1] ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4
(.I0(Q[2]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[3]_i_6_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3
(.CI(\axaddr_incr_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3_n_1 ,\axaddr_incr_reg[11]_i_3_n_2 ,\axaddr_incr_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[11:8]),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2_n_0 ,\axaddr_incr_reg[3]_i_2_n_1 ,\axaddr_incr_reg[3]_i_2_n_2 ,\axaddr_incr_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4_n_0 ,\axaddr_incr[3]_i_5_n_0 ,\axaddr_incr[3]_i_6_n_0 }),
.O(axaddr_incr[3:0]),
.S(S));
CARRY4 \axaddr_incr_reg[7]_i_2
(.CI(\axaddr_incr_reg[3]_i_2_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2_n_0 ,\axaddr_incr_reg[7]_i_2_n_1 ,\axaddr_incr_reg[7]_i_2_n_2 ,\axaddr_incr_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[7:4]),
.S(Q[7:4]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'h00000700FFFFF7FF))
\axaddr_offset_r[0]_i_2
(.I0(Q[39]),
.I1(\axaddr_offset_r[0]_i_3_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_3
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[1]_i_1
(.I0(Q[40]),
.I1(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [1]),
.O(\axaddr_offset_r_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[35]),
.I3(Q[3]),
.I4(Q[36]),
.I5(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.O(axaddr_offset[1]));
LUT6 #(
.INIT(64'h03FFF3FF55555555))
\axaddr_offset_r[2]_i_2
(.I0(\axaddr_offset_r_reg[3]_0 [2]),
.I1(\axaddr_offset_r[2]_i_3_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\axaddr_offset_r[2]_i_4_n_0 ),
.I5(\state_reg[1]_rep ),
.O(\axaddr_offset_r[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_4
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1
(.I0(Q[42]),
.I1(\axaddr_offset_r[3]_i_2_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [3]),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_3
(.I0(Q[42]),
.I1(\state_reg[1] [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\axlen_cnt_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(skid_buffer[52]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(E),
.D(skid_buffer[52]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_2
(.I0(Q[41]),
.I1(Q[40]),
.I2(Q[42]),
.I3(Q[39]),
.O(next_pending_r_reg));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_awready),
.I2(b_push),
.I3(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A002A2AAAA02A2))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[2]),
.I1(Q[41]),
.I2(Q[35]),
.I3(Q[40]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h002A0A2AA02AAA2A))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[4]),
.I1(Q[42]),
.I2(Q[35]),
.I3(Q[36]),
.I4(Q[41]),
.I5(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[35]),
.I3(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hDDDDD8DDAAAAA8AA))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r[0]_i_3_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(D[0]));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[1] ),
.I1(\wrap_cnt_r[3]_i_2_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1
(.I0(wrap_second_len[1]),
.I1(\wrap_cnt_r[3]_i_2_n_0 ),
.I2(\wrap_second_len_r_reg[1] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1
(.I0(wrap_second_len[2]),
.I1(\wrap_second_len_r_reg[1] ),
.I2(\wrap_cnt_r[3]_i_2_n_0 ),
.I3(wrap_second_len[1]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'hAAAABAAA))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_cnt_r[3]_i_3_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r[0]_i_2_n_0 ),
.I3(\axaddr_offset_r[2]_i_2_n_0 ),
.I4(\axaddr_offset_r_reg[3] ),
.O(\wrap_cnt_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000800FFFFF8FF))
\wrap_cnt_r[3]_i_3
(.I0(Q[39]),
.I1(\axaddr_offset_r[0]_i_3_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(\wrap_cnt_r[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00000000CCCCCACC))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3] [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(wrap_second_len[0]));
LUT6 #(
.INIT(64'hFFFFFFFFF2FFFFFF))
\wrap_second_len_r[0]_i_2
(.I0(\axaddr_offset_r_reg[3]_0 [3]),
.I1(\state_reg[1]_rep ),
.I2(\wrap_second_len_r[3]_i_2_n_0 ),
.I3(\axaddr_offset_r[2]_i_2_n_0 ),
.I4(\axaddr_offset_r[0]_i_2_n_0 ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000FFE200E2))
\wrap_second_len_r[0]_i_3
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[2]),
.I3(Q[35]),
.I4(\wrap_second_len_r[0]_i_4_n_0 ),
.I5(\wrap_second_len_r[0]_i_5_n_0 ),
.O(\wrap_second_len_r[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_second_len_r[0]_i_4
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\wrap_second_len_r[0]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT4 #(
.INIT(16'hFFDF))
\wrap_second_len_r[0]_i_5
(.I0(Q[39]),
.I1(\state_reg[1] [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\wrap_second_len_r[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'h2EE22E222EE22EE2))
\wrap_second_len_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\state_reg[1]_rep ),
.I2(\axaddr_offset_r[0]_i_2_n_0 ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[3] ),
.I5(\axaddr_offset_r[2]_i_2_n_0 ),
.O(\wrap_second_len_r_reg[1] ));
LUT6 #(
.INIT(64'h08F3FFFF08F30000))
\wrap_second_len_r[2]_i_1
(.I0(\axaddr_offset_r_reg[3] ),
.I1(\axaddr_offset_r[0]_i_2_n_0 ),
.I2(\axaddr_offset_r_reg[1] ),
.I3(\axaddr_offset_r[2]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3] [2]),
.O(wrap_second_len[1]));
LUT6 #(
.INIT(64'hBF00FFFFBF00BF00))
\wrap_second_len_r[3]_i_1
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r[0]_i_2_n_0 ),
.I2(\axaddr_offset_r[2]_i_2_n_0 ),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3] [3]),
.O(wrap_second_len[2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2
(.I0(\axaddr_offset_r[2]_i_4_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_14_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
shandshake,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output shandshake;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire shandshake;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__0
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(\skid_buffer_reg[0]_0 ),
.I1(si_rs_bvalid),
.O(shandshake));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_14_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_14_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[0]_rep__1 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[3]_rep__0 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[0]_rep__1 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[3]_rep__0 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[0]_rep__1 ;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__2_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[3]_i_2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[3]_rep__0 ),
.O(\cnt_read_reg[0]_rep__1 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\skid_buffer_reg[0]_0 ),
.I3(\cnt_read_reg[3]_rep__0 ),
.O(m_valid_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__2_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[3]_rep__0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "ip_design_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [11:0]s_axi_wid;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_14_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(s_axi_wid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 14.1 cbx_altiobuf_out 2015:01:15:17:21:49:SJ cbx_mgl 2015:01:19:18:40:00:SJ cbx_stratixiii 2015:01:15:17:21:50:SJ cbx_stratixv 2015:01:15:17:21:50:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__INV_BEHAVIORAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_BEHAVIORAL_PP_V |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_config_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_config_pll (
areset,
configupdate,
inclk0,
scanclk,
scanclkena,
scandata,
c0,
locked,
scandataout,
scandone);
input areset;
input configupdate;
input inclk0;
input scanclk;
input scanclkena;
input scandata;
output c0;
output locked;
output scandataout;
output scandone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 configupdate;
tri0 scanclkena;
tri0 scandata;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] sub_wire0;
wire sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire [0:0] sub_wire7 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire scandataout = sub_wire2;
wire scandone = sub_wire3;
wire locked = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.areset (areset),
.configupdate (configupdate),
.inclk (sub_wire6),
.scanclk (scanclk),
.scanclkena (scanclkena),
.scandata (scandata),
.clk (sub_wire0),
.scandataout (sub_wire2),
.scandone (sub_wire3),
.locked (sub_wire4),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "LOW",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 33898,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_config_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_USED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_USED",
altpll_component.port_scandata = "PORT_USED",
altpll_component.port_scandataout = "PORT_USED",
altpll_component.port_scandone = "PORT_USED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 7,
altpll_component.scan_chain_mif_file = "pll_config_pll.mif";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "3"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "15"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "29.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "29.500"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "17"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "29.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_config_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "33898"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_config_pll.mif"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_pll_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_pll.mif TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 256 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Complex Multiplier by 0.7071
// FUNCTION: Constant multiplier to cos(PI/8)+cos(3*PI/8) =1.307
// FILES: MPU�1307.v
// PROPERTIES: 1) Is based on shifts right and add
// 2) for short input bit width 1.307 is approximated as 1_0100_111 = 1_0101_00T
// 3) for medium bit width 1.3066 is approximated as 1_0100_1110_0111_11= 1_0101_00T0_1000_0T
// 4) for long bit width 1.30656 is approximated as 1_0100_1110_0111_1011=1_0101_00T0_1000_0T0T
// 5) hardware is 3 or 5, or 6 adders +1
// 6) MPYJ switches multiply by j
// 6) A complex data is multiplied for 2 cycles, latent delay=4
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "FFT256_CONFIG.inc"
module MPUC1307 ( CLK,EI ,ED, MPYJ,DR,DI ,DOR ,DOI );
`FFT256paramnb
input CLK ;
wire CLK ;
input EI ;
wire EI ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [nb-1:0] DR ;
wire signed [nb-1:0] DR ;
input [nb-1:0] DI ;
wire signed [nb-1:0] DI ;
output [nb:0] DOR ;
reg [nb:0] DOR ;
output [nb:0] DOI ;
reg [nb:0] DOI ;
reg signed [nb+2 :0] dx5;
reg signed [nb-1 :0] dx7;
reg signed [nb-1 :0] dii;
reg signed [nb : 0] dt;
wire signed [nb+3 : 0] dx5p;
wire signed [nb+3 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [nb:0] doo ;
reg [nb:0] droo ;
always @(posedge CLK)
begin
if (EI) begin
edd<=ED;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2; //1_0100_1110_0111_1011
if (ED) begin // 1_0101_00T0_1000_0T0T
dx5<=DR+(DR <<2); //multiply by 5
dx7<=DR-(DR>>>3); //multiply by 7, shifted right to 2
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii <<2); //multiply by 5
dx7<=dii-(dii>>>3); //multiply by 7, shifted right to 3
dt<=dii;
end
doo<=dot >>>3;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dx5<<1)+(dx7>>>1); // multiply by 1_0101_00T
`ifdef FFT256bitwidth_coef_high
assign dot= (dx5p+(dt>>>6) -(dx5>>>13));// multiply by 1_0101_00T0_1000_0T0T
`else
assign dot= dx5p+(dt>>>6);
`endif
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_lin2exp(
input [15:0] lin,
output reg [9:0] man,
output reg [2:0] exp
);
always @(*) begin
casex( lin[15:9] )
// negative numbers
7'b10XXXXX: begin
man = lin[15:6];
exp = 3'd7;
end
7'b110XXXX: begin
man = lin[14:5];
exp = 3'd6;
end
7'b1110XXX: begin
man = lin[13:4];
exp = 3'd5;
end
7'b11110XX: begin
man = lin[12:3];
exp = 3'd4;
end
7'b111110X: begin
man = lin[11:2];
exp = 3'd3;
end
7'b1111110: begin
man = lin[10:1];
exp = 3'd2;
end
7'b1111111: begin
man = lin[ 9:0];
exp = 3'd1;
end
// positive numbers
7'b01XXXXX: begin
man = lin[15:6];
exp = 3'd7;
end
7'b001XXXX: begin
man = lin[14:5];
exp = 3'd6;
end
7'b0001XXX: begin
man = lin[13:4];
exp = 3'd5;
end
7'b00001XX: begin
man = lin[12:3];
exp = 3'd4;
end
7'b000001X: begin
man = lin[11:2];
exp = 3'd3;
end
7'b0000001: begin
man = lin[10:1];
exp = 3'd2;
end
7'b0000000: begin
man = lin[ 9:0];
exp = 3'd1;
end
default: begin
man = lin[9:0];
exp = 3'd1;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_SYMBOL_V
`define SKY130_FD_SC_LS__A221OI_SYMBOL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a221oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_SYMBOL_V
|
// hps_design_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
hps_design_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41O_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A41O_PP_SYMBOL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a41o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41O_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2B_1_V
`define SKY130_FD_SC_HDLL__NAND2B_1_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2b_1 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2b_1 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2B_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_BEHAVIORAL_PP_V |
/*
* Copyright (c) 2015 Instrumentation Technologies
* All Rights Reserved.
*
* $Id: $
*/
// synopsys translate_off
`timescale 1ns / 1ps
// synopsys translate_on
module axi_master #(
parameter DW = 64 , // data width (8,16,...,1024)
parameter AW = 32 , // address width
parameter ID = 0 , // master ID
parameter IW = 4 , // master ID width
parameter LW = 4 , // length width
parameter SW = DW >> 3 // strobe width - 1 bit for every data byte
)
(
// global signals
input axi_clk_i , // global clock
input axi_rstn_i , // global reset
// axi write address channel
output [ IW-1: 0] axi_awid_o , // write address ID
output reg [ AW-1: 0] axi_awaddr_o , // write address
output reg [ 4-1: 0] axi_awlen_o , // write burst length
output [ 3-1: 0] axi_awsize_o , // write burst size
output reg [ 2-1: 0] axi_awburst_o , // write burst type
output [ 2-1: 0] axi_awlock_o , // write lock type
output [ 4-1: 0] axi_awcache_o , // write cache type
output [ 3-1: 0] axi_awprot_o , // write protection type
output reg axi_awvalid_o , // write address valid
input axi_awready_i , // write ready
// axi write data channel
output [ IW-1: 0] axi_wid_o , // write data ID
output reg [ DW-1: 0] axi_wdata_o , // write data
output reg [ SW-1: 0] axi_wstrb_o , // write strobes
output reg axi_wlast_o , // write last
output reg axi_wvalid_o , // write valid
input axi_wready_i , // write ready
// axi write response channel
input [ IW-1: 0] axi_bid_i , // write response ID
input [ 2-1: 0] axi_bresp_i , // write response
input axi_bvalid_i , // write response valid
output axi_bready_o , // write response ready
// axi read address channel
output [ IW-1: 0] axi_arid_o , // read address ID
output reg [ AW-1: 0] axi_araddr_o , // read address
output reg [ 4-1: 0] axi_arlen_o , // read burst length
output [ 3-1: 0] axi_arsize_o , // read burst size
output reg [ 2-1: 0] axi_arburst_o , // read burst type
output [ 2-1: 0] axi_arlock_o , // read lock type
output [ 4-1: 0] axi_arcache_o , // read cache type
output [ 3-1: 0] axi_arprot_o , // read protection type
output reg axi_arvalid_o , // read address valid
input axi_arready_i , // read address ready
// axi read data channel
input [ IW-1: 0] axi_rid_i , // read response ID
input [ DW-1: 0] axi_rdata_i , // read data
input [ 2-1: 0] axi_rresp_i , // read response
input axi_rlast_i , // read last
input axi_rvalid_i , // read response valid
output reg axi_rready_o , // read response ready
// system write channel
input [ AW-1: 0] sys_waddr_i , // system write address
input [ DW-1: 0] sys_wdata_i , // system write data
input [ SW-1: 0] sys_wsel_i , // system write byte select
input sys_wvalid_i , // system write data valid
input [ 4-1: 0] sys_wlen_i , // system write burst length
input sys_wfixed_i , // system write burst type (fixed / incremental)
output reg sys_werr_o , // system write error
output reg sys_wrdy_o , // system write ready
// system read channel
input [ AW-1: 0] sys_raddr_i , // system read address
input sys_rvalid_i , // system read address valid
input [ SW-1: 0] sys_rsel_i , // system read byte select
input [ 4-1: 0] sys_rlen_i , // system read burst length
input sys_rfixed_i , // system read burst type (fixed / incremental)
output reg [ DW-1: 0] sys_rdata_o , // system read data
output reg sys_rrdy_o , // system read data is ready
output reg sys_rerr_o // system read error
);
//---------------------------------------------------------------------------------
//
// Write address channel
assign axi_awid_o = ID ;
assign axi_awsize_o = {2'b01,(DW==64)} ; // 4 or 8 byte transfer ; // write burst size
assign axi_awlock_o = 2'h0 ; // normal
assign axi_awcache_o = 4'b0001; // bufferable, non-cacheable
assign axi_awprot_o = 3'b000 ; // data, non-secured, unprivileged
reg [ 4-1: 0] wr_cnt ;
reg [ 4-1: 0] axi_awwr_pt ;
reg [ 4-1: 0] axi_awrd_pt ;
reg [ 4-1: 0] axi_awfill_lvl ;
reg [ 5+AW-1: 0] axi_awfifo[15:0] ; //synthesis attribute ram_style of axi_awfifo is "distributed";
reg awdata_in_reg ;
wire axi_wlast ;
wire axi_wpush ;
wire axi_awpop = (!awdata_in_reg || axi_awready_i) && |axi_awfill_lvl ;
wire axi_awpush = sys_wvalid_i && sys_wrdy_o && !wr_cnt ;
always @ (posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
axi_awwr_pt <= 4'h0 ;
end
else if (axi_awpush) begin
axi_awfifo[axi_awwr_pt] <= {!sys_wfixed_i,sys_wlen_i,sys_waddr_i} ;
axi_awwr_pt <= axi_awwr_pt + 4'h1 ;
end
end
always @ (posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
axi_awrd_pt <= 'h0 ;
axi_awburst_o <= 'h0 ;
end
else begin
if (axi_awpop) begin
{axi_awburst_o[0],axi_awlen_o,axi_awaddr_o} <= axi_awfifo[axi_awrd_pt] ;
axi_awrd_pt <= axi_awrd_pt + 4'h1 ;
end
else if (axi_awready_i && axi_awvalid_o) begin
{axi_awburst_o[0],axi_awlen_o,axi_awaddr_o} <= {1 + 4 + AW{1'h0}} ;
end
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
axi_awvalid_o <= 1'b0 ;
axi_awfill_lvl <= 4'h0 ;
awdata_in_reg <= 1'b0 ;
end
else begin
if (axi_awpop)
axi_awvalid_o <= 1'b1 ;
else if (axi_awready_i && axi_awvalid_o)
axi_awvalid_o <= 1'b0 ;
if (axi_awpush && !axi_awpop)
axi_awfill_lvl <= axi_awfill_lvl + 4'h1 ;
else if (!axi_awpush && axi_awpop)
axi_awfill_lvl <= axi_awfill_lvl - 4'h1 ;
if (axi_awpop)
awdata_in_reg <= 1'b1 ;
else if (axi_awready_i && axi_awvalid_o)
awdata_in_reg <= 1'b0 ;
end
end
//---------------------------------------------------------------------------------
//
// Write data channel
assign axi_wid_o = ID ;
reg [ 4-1: 0] axi_wwr_pt ;
reg [ 4-1: 0] axi_wrd_pt ;
reg [ 4-1: 0] axi_wfill_lvl ;
reg [SW + DW: 0] axi_wfifo[15:0] ; //synthesis attribute ram_style of axi_wfifo is "distributed";
// stores last data, data select and data signals
reg wdata_in_reg ;
wire axi_wpop = (!wdata_in_reg || axi_wready_i) && |axi_wfill_lvl ;
assign axi_wpush = sys_wvalid_i && sys_wrdy_o ;
assign axi_wlast = ((!sys_wlen_i && sys_wvalid_i) || (wr_cnt == 4'h1)) ;
always @ (posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
axi_wwr_pt <= 4'h0 ;
axi_wrd_pt <= 4'h0 ;
end
else begin
if (axi_wpush) begin
axi_wfifo[axi_wwr_pt] <= {axi_wlast,sys_wsel_i,sys_wdata_i} ;
axi_wwr_pt <= axi_wwr_pt + 4'h1 ;
end
if (axi_wpop) begin
{axi_wlast_o,axi_wstrb_o,axi_wdata_o} <= axi_wfifo[axi_wrd_pt] ;
axi_wrd_pt <= axi_wrd_pt + 4'h1 ;
end
else if (axi_wready_i && axi_wvalid_o) begin
{axi_wlast_o,axi_wstrb_o,axi_wdata_o} <= {1 + SW + DW{1'h0}} ;
end
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
axi_wvalid_o <= 1'b0 ;
sys_wrdy_o <= 1'b0 ;
axi_wfill_lvl <= 4'h0 ;
end
else begin
if (axi_wpop)
axi_wvalid_o <= 1'b1 ;
else if (axi_wready_i && axi_wvalid_o)
axi_wvalid_o <= 1'b0 ;
if (axi_wpush && !axi_wpop)
axi_wfill_lvl <= axi_wfill_lvl + 4'h1 ;
else if (!axi_wpush && axi_wpop)
axi_wfill_lvl <= axi_wfill_lvl - 4'h1 ;
// stop pushing, when either data or address FIFO is almost full
sys_wrdy_o <= ~&axi_wfill_lvl[3:1] && ~&axi_awfill_lvl[3:1];
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
wdata_in_reg <= 'h0 ;
wr_cnt <= 'h0 ;
end
else begin
if (axi_wpop)
wdata_in_reg <= 1'b1 ;
else if (axi_wready_i && axi_wvalid_o)
wdata_in_reg <= 1'b0 ;
if (sys_wvalid_i && sys_wrdy_o && !wr_cnt)
wr_cnt <= sys_wlen_i ;
else if (axi_wpush && wr_cnt)
wr_cnt <= wr_cnt - 4'h1 ;
end
end
//---------------------------------------------------------------------------------
//
// Write response channel
assign axi_bready_o = 'h1 ;
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i)
sys_werr_o <= 1'b0 ;
else
sys_werr_o <= axi_bvalid_i && (axi_bresp_i == 2'h2) ;
end
//---------------------------------------------------------------------------------
//
// Read address channel
assign axi_arid_o = ID ;
assign axi_arsize_o = {2'b01,(DW==64)} ; // 4 or 8 byte transfer
assign axi_arlock_o = 2'h0 ; // normal
assign axi_arcache_o = 4'b0001; // bufferable, non-cacheable
assign axi_arprot_o = 3'b000 ; // data, non-secured, unprivileged
reg [4-1: 0] rd_cnt ; // counts data received by system port
reg nxt_burst_rdy;
// system bus provides next address only
// after the current read burst has finished
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
nxt_burst_rdy <= 1'b1 ;
rd_cnt <= 4'h0 ;
end
else begin
if (sys_rvalid_i)
nxt_burst_rdy <= 1'b0 ;
else if (!rd_cnt && sys_rrdy_o && sys_rvalid_i)
nxt_burst_rdy <= 1'b1 ;
if (sys_rvalid_i && nxt_burst_rdy)
rd_cnt <= sys_rlen_i ;
else if (sys_rvalid_i && sys_rrdy_o && rd_cnt)
rd_cnt <= rd_cnt - 4'h1 ;
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
axi_arvalid_o <= 'h0 ;
axi_arburst_o <= 'h0 ;
end
else begin
if (sys_rvalid_i && nxt_burst_rdy) begin
axi_arvalid_o <= 'h1 ;
axi_arlen_o <= sys_rlen_i ;
axi_araddr_o <= sys_raddr_i ;
axi_arburst_o <= !sys_rfixed_i ;
end
else if (axi_arready_i) begin
axi_arvalid_o <= 'h0 ;
end
end
end
//---------------------------------------------------------------------------------
//
// Read data channel
reg [ 4-1: 0] axi_rwr_pt ,
axi_rrd_pt ;
reg [ 4-1: 0] axi_rfill_lvl ;
reg [DW-1: 0] axi_rfifo[15:0] ; //synthesis attribute ram_style of axi_rfifo is "distributed";
reg rdata_in_reg ;
wire axi_rpush = axi_rvalid_i && axi_rready_o ;
wire axi_rpop = (!rdata_in_reg || sys_rvalid_i) && |axi_rfill_lvl ;
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
axi_rwr_pt <= 4'h0 ;
axi_rrd_pt <= 4'h0 ;
end
else begin
if (axi_rpush) begin
axi_rfifo[axi_rwr_pt] <= axi_rdata_i ;
axi_rwr_pt <= axi_rwr_pt + 4'h1 ;
end
if (axi_rpop) begin
sys_rdata_o <= axi_rfifo[axi_rrd_pt] ;
axi_rrd_pt <= axi_rrd_pt + 4'h1 ;
end
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
sys_rrdy_o <= 1'b0 ;
sys_rerr_o <= 1'b0 ;
end
else begin
if (axi_rpop)
sys_rrdy_o <= 1'b1 ;
else if (sys_rrdy_o && sys_rvalid_i)
sys_rrdy_o <= 1'b0 ;
sys_rerr_o <= axi_rvalid_i && (axi_rresp_i == 2'h2) ;
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
axi_rfill_lvl <= 4'h0 ;
axi_rready_o <= 1'h1 ;
end
else begin
if (axi_rpush && !axi_rpop)
axi_rfill_lvl <= axi_rfill_lvl + 4'h1 ;
else if (!axi_rpush && axi_rpop)
axi_rfill_lvl <= axi_rfill_lvl - 4'h1 ;
axi_rready_o <= ~&axi_rfill_lvl[3:1] ;
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
rdata_in_reg <= 'h0 ;
end
else begin
if (axi_rpop) begin
rdata_in_reg <= 1'b1 ;
end
else if (sys_rrdy_o && sys_rvalid_i) begin
rdata_in_reg <= 1'b0 ;
end
end
end
endmodule // amba_axi_master
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 14:49:03 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_transform_0_1 -prefix
// system_vga_transform_0_1_ system_vga_transform_0_1_stub.v
// Design : system_vga_transform_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_transform,Vivado 2016.4" *)
module system_vga_transform_0_1(clk, enable, x_addr_in, y_addr_in, rot_m00,
rot_m01, rot_m10, rot_m11, t_x, t_y, x_addr_out, y_addr_out)
/* synthesis syn_black_box black_box_pad_pin="clk,enable,x_addr_in[9:0],y_addr_in[9:0],rot_m00[15:0],rot_m01[15:0],rot_m10[15:0],rot_m11[15:0],t_x[9:0],t_y[9:0],x_addr_out[9:0],y_addr_out[9:0]" */;
input clk;
input enable;
input [9:0]x_addr_in;
input [9:0]y_addr_in;
input [15:0]rot_m00;
input [15:0]rot_m01;
input [15:0]rot_m10;
input [15:0]rot_m11;
input [9:0]t_x;
input [9:0]t_y;
output [9:0]x_addr_out;
output [9:0]y_addr_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_4_V
`define SKY130_FD_SC_LS__SDFSTP_4_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_4_V
|
module avconf ( // Host Side
CLOCK_50,
reset,
// I2C Side
I2C_SCLK,
I2C_SDAT );
// Host Side
input CLOCK_50;
input reset;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
wire iRST_N = !reset;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
parameter USE_MIC_INPUT = 1'b0;
parameter AUD_LINE_IN_LC = 9'd24;
parameter AUD_LINE_IN_RC = 9'd24;
parameter AUD_LINE_OUT_LC = 9'd119;
parameter AUD_LINE_OUT_RC = 9'd119;
parameter AUD_ADC_PATH = 9'd17;
parameter AUD_DAC_PATH = 9'd6;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'd77;
parameter AUD_SAMPLE_CTRL = 9'd0;
parameter AUD_SET_ACTIVE = 9'h001;
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 50;
// Audio Data Index
parameter SET_LIN_L = 0;
parameter SET_LIN_R = 1;
parameter SET_HEAD_L = 2;
parameter SET_HEAD_R = 3;
parameter A_PATH_CTRL = 4;
parameter D_PATH_CTRL = 5;
parameter POWER_ON = 6;
parameter SET_FORMAT = 7;
parameter SAMPLE_CTRL = 8;
parameter SET_ACTIVE = 9;
// Video Data Index
parameter SET_VIDEO = 10;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge CLOCK_50 or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N) );
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
if(LUT_INDEX<SET_VIDEO)
mI2C_DATA <= {8'h34,LUT_DATA};
else
mI2C_DATA <= {8'h40,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Audio Config Data
SET_LIN_L : LUT_DATA <= {7'h0, AUD_LINE_IN_LC};
SET_LIN_R : LUT_DATA <= {7'h1, AUD_LINE_IN_RC};
SET_HEAD_L : LUT_DATA <= {7'h2, AUD_LINE_OUT_LC};
SET_HEAD_R : LUT_DATA <= {7'h3, AUD_LINE_OUT_RC};
A_PATH_CTRL : LUT_DATA <= {7'h4, AUD_ADC_PATH} + (16'h0004 * USE_MIC_INPUT);
D_PATH_CTRL : LUT_DATA <= {7'h5, AUD_DAC_PATH};
POWER_ON : LUT_DATA <= {7'h6, AUD_POWER};
SET_FORMAT : LUT_DATA <= {7'h7, AUD_DATA_FORMAT};
SAMPLE_CTRL : LUT_DATA <= {7'h8, AUD_SAMPLE_CTRL};
SET_ACTIVE : LUT_DATA <= {7'h9, AUD_SET_ACTIVE};
// Video Config Data
SET_VIDEO+0 : LUT_DATA <= 16'h1500;
SET_VIDEO+1 : LUT_DATA <= 16'h1741;
SET_VIDEO+2 : LUT_DATA <= 16'h3a16;
SET_VIDEO+3 : LUT_DATA <= 16'h503f; // 16'h5004;
SET_VIDEO+4 : LUT_DATA <= 16'hc305;
SET_VIDEO+5 : LUT_DATA <= 16'hc480;
SET_VIDEO+6 : LUT_DATA <= 16'h0e80;
SET_VIDEO+7 : LUT_DATA <= 16'h503f; // 16'h5020;
SET_VIDEO+8 : LUT_DATA <= 16'h5218;
SET_VIDEO+9 : LUT_DATA <= 16'h58ed;
SET_VIDEO+10: LUT_DATA <= 16'h77c5;
SET_VIDEO+11: LUT_DATA <= 16'h7c93;
SET_VIDEO+12: LUT_DATA <= 16'h7d00;
SET_VIDEO+13: LUT_DATA <= 16'hd048;
SET_VIDEO+14: LUT_DATA <= 16'hd5a0;
SET_VIDEO+15: LUT_DATA <= 16'hd7ea;
SET_VIDEO+16: LUT_DATA <= 16'he43e;
SET_VIDEO+17: LUT_DATA <= 16'hea0f;
SET_VIDEO+18: LUT_DATA <= 16'h3112;
SET_VIDEO+19: LUT_DATA <= 16'h3281;
SET_VIDEO+20: LUT_DATA <= 16'h3384;
SET_VIDEO+21: LUT_DATA <= 16'h37A0;
SET_VIDEO+22: LUT_DATA <= 16'he580;
SET_VIDEO+23: LUT_DATA <= 16'he603;
SET_VIDEO+24: LUT_DATA <= 16'he785;
SET_VIDEO+25: LUT_DATA <= 16'h2778; // 16'h503f; // 16'h5000;
SET_VIDEO+26: LUT_DATA <= 16'h5100;
SET_VIDEO+27: LUT_DATA <= 16'h0050;
SET_VIDEO+28: LUT_DATA <= 16'h1000;
SET_VIDEO+29: LUT_DATA <= 16'h0402;
SET_VIDEO+30: LUT_DATA <= 16'h0860;
SET_VIDEO+31: LUT_DATA <= 16'h0a18;
SET_VIDEO+32: LUT_DATA <= 16'h1100;
SET_VIDEO+33: LUT_DATA <= 16'h2b00;
SET_VIDEO+34: LUT_DATA <= 16'h2c8c;
SET_VIDEO+35: LUT_DATA <= 16'h2df8;
SET_VIDEO+36: LUT_DATA <= 16'h2eee;
SET_VIDEO+37: LUT_DATA <= 16'h2ff4;
SET_VIDEO+38: LUT_DATA <= 16'h30d2;
SET_VIDEO+39: LUT_DATA <= 16'h0e05;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
module main;
string foo;
int error_count;
task check_char(input int idx, input [7:0] val);
if (foo[idx] !== val) begin
$display("FAILED: foo[%0d]==%02h, expecting %02h",
idx, foo[idx], val);
error_count = error_count+1;
end
endtask // check_char
initial begin
// These are the special charasters in strings as defined by
// IEEE Std 1800-2017: 5.9.1 Special characters in strings.
// The string assignment is governed by:
// IEEE Std 1800-2017: 6.16 String data type
foo = "abc\n\t\\\"\v\f\a\001\002\x03\x04";
error_count = 0;
check_char(0, 8'h61); // 'a'
check_char(1, 8'h62); // 'b'
check_char(2, 8'h63); // 'c'
check_char(3, 8'h0a); // '\n'
check_char(4, 8'h09); // '\t'
check_char(5, 8'h5c); // '\\'
check_char(6, 8'h22); // '\"'
check_char(7, 8'h0b); // '\v'
check_char(8, 8'h0c); // '\f'
check_char(9, 8'h07); // '\a'
check_char(10, 8'h01); // '\001'
check_char(11, 8'h02); // '\002'
check_char(12, 8'h03); // '\x03'
check_char(13, 8'h04); // '\x04'
if (foo.len() !== 14) begin
$display("FAILED: foo.len() == %0d, should be 14", foo.len());
error_count = error_count+1;
end
if (error_count == 0) $display("PASSED");
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_2_V
`define SKY130_FD_SC_LP__AND2B_2_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2b_2 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2b_2 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_2_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: sum_31_36.v
// /___/ /\ Timestamp: Tue Mar 31 01:52:02 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/sum_31_36/tmp/_cg/sum_31_36.ngc C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/sum_31_36/tmp/_cg/sum_31_36.v
// Device : 6slx45csg324-2
// Input file : C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/sum_31_36/tmp/_cg/sum_31_36.ngc
// Output file : C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/ipcore_dir/sum_31_36/tmp/_cg/sum_31_36.v
// # of Modules : 1
// Design Name : sum_31_36
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module sum_31_36 (
clk, ce, a, b, s
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input [30 : 0] a;
input [35 : 0] b;
output [36 : 0] s;
// synthesis translate_off
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \NLW_blk00000001/blk0000015f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000159_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000157_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000155_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000153_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000151_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000149_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000147_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000145_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000143_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000141_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000013f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000013d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000013b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000129_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000127_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000125_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000123_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000121_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000011f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000011d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000011b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000119_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000117_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000115_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000113_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000111_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000010f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000010d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000010b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000109_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000107_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000105_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000103_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000000b2_O_UNCONNECTED ;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000160 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000001a3 ),
.Q(s[14])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000015f (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000008b ),
.Q(\blk00000001/sig000001a3 ),
.Q15(\NLW_blk00000001/blk0000015f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000001a2 ),
.Q(s[15])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000015d (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000008c ),
.Q(\blk00000001/sig000001a2 ),
.Q15(\NLW_blk00000001/blk0000015d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000001a1 ),
.Q(s[17])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000015b (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000008e ),
.Q(\blk00000001/sig000001a1 ),
.Q15(\NLW_blk00000001/blk0000015b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000001a0 ),
.Q(s[18])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000159 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000008f ),
.Q(\blk00000001/sig000001a0 ),
.Q15(\NLW_blk00000001/blk00000159_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000158 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000019f ),
.Q(s[16])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000157 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000008d ),
.Q(\blk00000001/sig0000019f ),
.Q15(\NLW_blk00000001/blk00000157_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000156 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000019e ),
.Q(s[20])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000155 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000091 ),
.Q(\blk00000001/sig0000019e ),
.Q15(\NLW_blk00000001/blk00000155_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000154 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000019d ),
.Q(s[21])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000153 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000092 ),
.Q(\blk00000001/sig0000019d ),
.Q15(\NLW_blk00000001/blk00000153_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000152 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000019c ),
.Q(s[19])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000151 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000090 ),
.Q(\blk00000001/sig0000019c ),
.Q15(\NLW_blk00000001/blk00000151_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000150 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000019b ),
.Q(\blk00000001/sig00000071 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000014f (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000010c ),
.Q(\blk00000001/sig0000019b ),
.Q15(\NLW_blk00000001/blk0000014f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000019a ),
.Q(\blk00000001/sig00000072 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000014d (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000010b ),
.Q(\blk00000001/sig0000019a ),
.Q15(\NLW_blk00000001/blk0000014d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000199 ),
.Q(\blk00000001/sig00000070 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000014b (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000105 ),
.Q(\blk00000001/sig00000199 ),
.Q15(\NLW_blk00000001/blk0000014b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000198 ),
.Q(\blk00000001/sig00000074 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000149 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000109 ),
.Q(\blk00000001/sig00000198 ),
.Q15(\NLW_blk00000001/blk00000149_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000148 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000197 ),
.Q(\blk00000001/sig00000075 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000147 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000108 ),
.Q(\blk00000001/sig00000197 ),
.Q15(\NLW_blk00000001/blk00000147_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000146 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000196 ),
.Q(\blk00000001/sig00000073 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000145 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000010a ),
.Q(\blk00000001/sig00000196 ),
.Q15(\NLW_blk00000001/blk00000145_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000144 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000195 ),
.Q(\blk00000001/sig00000077 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000143 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000106 ),
.Q(\blk00000001/sig00000195 ),
.Q15(\NLW_blk00000001/blk00000143_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000142 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000194 ),
.Q(\blk00000001/sig00000094 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000141 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000d8 ),
.Q(\blk00000001/sig00000194 ),
.Q15(\NLW_blk00000001/blk00000141_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000140 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000193 ),
.Q(\blk00000001/sig00000076 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000013f (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000107 ),
.Q(\blk00000001/sig00000193 ),
.Q15(\NLW_blk00000001/blk0000013f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000192 ),
.Q(\blk00000001/sig00000096 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000013d (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000de ),
.Q(\blk00000001/sig00000192 ),
.Q15(\NLW_blk00000001/blk0000013d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000191 ),
.Q(\blk00000001/sig00000097 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000013b (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000dd ),
.Q(\blk00000001/sig00000191 ),
.Q15(\NLW_blk00000001/blk0000013b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000190 ),
.Q(\blk00000001/sig00000095 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000139 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000df ),
.Q(\blk00000001/sig00000190 ),
.Q15(\NLW_blk00000001/blk00000139_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000138 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000018f ),
.Q(\blk00000001/sig00000099 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000137 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000db ),
.Q(\blk00000001/sig0000018f ),
.Q15(\NLW_blk00000001/blk00000137_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000136 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000018e ),
.Q(\blk00000001/sig0000009a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000135 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000da ),
.Q(\blk00000001/sig0000018e ),
.Q15(\NLW_blk00000001/blk00000135_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000134 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000018d ),
.Q(\blk00000001/sig00000098 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000133 (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000dc ),
.Q(\blk00000001/sig0000018d ),
.Q15(\NLW_blk00000001/blk00000133_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000132 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000018c ),
.Q(\blk00000001/sig00000081 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000131 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000103 ),
.Q(\blk00000001/sig0000018c ),
.Q15(\NLW_blk00000001/blk00000131_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000130 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000018b ),
.Q(\blk00000001/sig00000093 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000012f (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000ee ),
.Q(\blk00000001/sig0000018b ),
.Q15(\NLW_blk00000001/blk0000012f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000018a ),
.Q(\blk00000001/sig0000009b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000012d (
.A0(\blk00000001/sig0000006c ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000d9 ),
.Q(\blk00000001/sig0000018a ),
.Q15(\NLW_blk00000001/blk0000012d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000189 ),
.Q(s[8])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000012b (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000009f ),
.Q(\blk00000001/sig00000189 ),
.Q15(\NLW_blk00000001/blk0000012b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000188 ),
.Q(s[9])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000129 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000a0 ),
.Q(\blk00000001/sig00000188 ),
.Q15(\NLW_blk00000001/blk00000129_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000128 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000187 ),
.Q(s[7])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000127 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000009e ),
.Q(\blk00000001/sig00000187 ),
.Q15(\NLW_blk00000001/blk00000127_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000126 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000186 ),
.Q(s[11])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000125 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000a2 ),
.Q(\blk00000001/sig00000186 ),
.Q15(\NLW_blk00000001/blk00000125_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000124 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000185 ),
.Q(s[12])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000123 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000a3 ),
.Q(\blk00000001/sig00000185 ),
.Q15(\NLW_blk00000001/blk00000123_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000122 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000184 ),
.Q(s[10])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000121 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000a1 ),
.Q(\blk00000001/sig00000184 ),
.Q15(\NLW_blk00000001/blk00000121_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000120 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000183 ),
.Q(s[0])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000011f (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000ae ),
.Q(\blk00000001/sig00000183 ),
.Q15(\NLW_blk00000001/blk0000011f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000182 ),
.Q(s[1])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000011d (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000b4 ),
.Q(\blk00000001/sig00000182 ),
.Q15(\NLW_blk00000001/blk0000011d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000181 ),
.Q(s[13])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000011b (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000a4 ),
.Q(\blk00000001/sig00000181 ),
.Q15(\NLW_blk00000001/blk0000011b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000180 ),
.Q(s[3])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000119 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000b2 ),
.Q(\blk00000001/sig00000180 ),
.Q15(\NLW_blk00000001/blk00000119_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000118 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000017f ),
.Q(s[4])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000117 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000b1 ),
.Q(\blk00000001/sig0000017f ),
.Q15(\NLW_blk00000001/blk00000117_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000116 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000017e ),
.Q(s[2])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000115 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000b3 ),
.Q(\blk00000001/sig0000017e ),
.Q15(\NLW_blk00000001/blk00000115_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000114 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000017d ),
.Q(s[6])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000113 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000af ),
.Q(\blk00000001/sig0000017d ),
.Q15(\NLW_blk00000001/blk00000113_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000112 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000017c ),
.Q(\blk00000001/sig00000082 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000111 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000f0 ),
.Q(\blk00000001/sig0000017c ),
.Q15(\NLW_blk00000001/blk00000111_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000110 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000017b ),
.Q(s[5])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000010f (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006b ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000b0 ),
.Q(\blk00000001/sig0000017b ),
.Q15(\NLW_blk00000001/blk0000010f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000017a ),
.Q(\blk00000001/sig00000084 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000010d (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000f5 ),
.Q(\blk00000001/sig0000017a ),
.Q15(\NLW_blk00000001/blk0000010d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000179 ),
.Q(\blk00000001/sig00000085 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000010b (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000f4 ),
.Q(\blk00000001/sig00000179 ),
.Q15(\NLW_blk00000001/blk0000010b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000178 ),
.Q(\blk00000001/sig00000083 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000109 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000f6 ),
.Q(\blk00000001/sig00000178 ),
.Q15(\NLW_blk00000001/blk00000109_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000108 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000177 ),
.Q(\blk00000001/sig00000087 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000107 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000f2 ),
.Q(\blk00000001/sig00000177 ),
.Q15(\NLW_blk00000001/blk00000107_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000106 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000176 ),
.Q(\blk00000001/sig00000088 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000105 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000f1 ),
.Q(\blk00000001/sig00000176 ),
.Q15(\NLW_blk00000001/blk00000105_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000104 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000175 ),
.Q(\blk00000001/sig00000086 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000103 (
.A0(\blk00000001/sig0000006b ),
.A1(\blk00000001/sig0000006c ),
.A2(\blk00000001/sig0000006c ),
.A3(\blk00000001/sig0000006c ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000000f3 ),
.Q(\blk00000001/sig00000175 ),
.Q15(\NLW_blk00000001/blk00000103_Q15_UNCONNECTED )
);
INV \blk00000001/blk00000102 (
.I(\blk00000001/sig00000093 ),
.O(\blk00000001/sig00000174 )
);
INV \blk00000001/blk00000101 (
.I(\blk00000001/sig00000081 ),
.O(\blk00000001/sig00000173 )
);
INV \blk00000001/blk00000100 (
.I(\blk00000001/sig000000a5 ),
.O(\blk00000001/sig00000172 )
);
MUXCY \blk00000001/blk000000ff (
.CI(\blk00000001/sig0000008a ),
.DI(\blk00000001/sig0000006b ),
.S(\blk00000001/sig00000174 ),
.O(\blk00000001/sig0000006e )
);
MUXCY \blk00000001/blk000000fe (
.CI(\blk00000001/sig00000079 ),
.DI(\blk00000001/sig0000006b ),
.S(\blk00000001/sig00000173 ),
.O(\blk00000001/sig0000006d )
);
MUXCY \blk00000001/blk000000fd (
.CI(\blk00000001/sig0000009d ),
.DI(\blk00000001/sig0000006b ),
.S(\blk00000001/sig00000172 ),
.O(\blk00000001/sig0000006f )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000fc (
.I0(\blk00000001/sig00000070 ),
.O(\blk00000001/sig00000171 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000fb (
.I0(\blk00000001/sig00000071 ),
.O(\blk00000001/sig00000170 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000fa (
.I0(\blk00000001/sig00000072 ),
.O(\blk00000001/sig0000016f )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f9 (
.I0(\blk00000001/sig00000077 ),
.O(\blk00000001/sig0000016e )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f8 (
.I0(\blk00000001/sig00000073 ),
.O(\blk00000001/sig0000016d )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f7 (
.I0(\blk00000001/sig00000074 ),
.O(\blk00000001/sig0000016c )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f6 (
.I0(\blk00000001/sig00000075 ),
.O(\blk00000001/sig0000016b )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f5 (
.I0(\blk00000001/sig00000076 ),
.O(\blk00000001/sig0000016a )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f4 (
.I0(\blk00000001/sig00000094 ),
.O(\blk00000001/sig00000169 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f3 (
.I0(\blk00000001/sig00000095 ),
.O(\blk00000001/sig00000168 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f2 (
.I0(\blk00000001/sig00000096 ),
.O(\blk00000001/sig00000167 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f1 (
.I0(\blk00000001/sig0000009b ),
.O(\blk00000001/sig00000166 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000f0 (
.I0(\blk00000001/sig00000097 ),
.O(\blk00000001/sig00000165 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000ef (
.I0(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000164 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000ee (
.I0(\blk00000001/sig00000099 ),
.O(\blk00000001/sig00000163 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000ed (
.I0(\blk00000001/sig0000009a ),
.O(\blk00000001/sig00000162 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000ec (
.I0(\blk00000001/sig00000082 ),
.O(\blk00000001/sig00000161 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000eb (
.I0(\blk00000001/sig00000083 ),
.O(\blk00000001/sig00000160 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000ea (
.I0(\blk00000001/sig00000084 ),
.O(\blk00000001/sig0000015f )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e9 (
.I0(\blk00000001/sig00000088 ),
.O(\blk00000001/sig0000015e )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e8 (
.I0(\blk00000001/sig00000085 ),
.O(\blk00000001/sig0000015d )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e7 (
.I0(\blk00000001/sig00000086 ),
.O(\blk00000001/sig0000015c )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e6 (
.I0(\blk00000001/sig00000087 ),
.O(\blk00000001/sig0000015b )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e5 (
.I0(\blk00000001/sig000000a6 ),
.O(\blk00000001/sig0000015a )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e4 (
.I0(\blk00000001/sig000000a7 ),
.O(\blk00000001/sig00000159 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e3 (
.I0(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig00000158 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e2 (
.I0(\blk00000001/sig000000ac ),
.O(\blk00000001/sig00000157 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e1 (
.I0(\blk00000001/sig000000a9 ),
.O(\blk00000001/sig00000156 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000e0 (
.I0(\blk00000001/sig000000aa ),
.O(\blk00000001/sig00000155 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk000000df (
.I0(\blk00000001/sig000000ab ),
.O(\blk00000001/sig00000154 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000de (
.I0(a[30]),
.I1(b[35]),
.O(\blk00000001/sig00000153 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000dd (
.I0(a[30]),
.I1(b[35]),
.O(\blk00000001/sig0000010d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000dc (
.I0(a[30]),
.I1(b[34]),
.O(\blk00000001/sig0000010e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000db (
.I0(a[30]),
.I1(b[33]),
.O(\blk00000001/sig0000010f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000da (
.I0(a[30]),
.I1(b[32]),
.O(\blk00000001/sig00000110 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d9 (
.I0(a[30]),
.I1(b[31]),
.O(\blk00000001/sig00000111 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d8 (
.I0(a[30]),
.I1(b[30]),
.O(\blk00000001/sig00000112 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d7 (
.I0(a[29]),
.I1(b[29]),
.O(\blk00000001/sig00000113 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d6 (
.I0(a[28]),
.I1(b[28]),
.O(\blk00000001/sig000000fc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d5 (
.I0(a[27]),
.I1(b[27]),
.O(\blk00000001/sig000000f7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d4 (
.I0(a[26]),
.I1(b[26]),
.O(\blk00000001/sig000000f8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d3 (
.I0(a[25]),
.I1(b[25]),
.O(\blk00000001/sig000000f9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d2 (
.I0(a[24]),
.I1(b[24]),
.O(\blk00000001/sig000000fa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d1 (
.I0(a[23]),
.I1(b[23]),
.O(\blk00000001/sig000000fb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d0 (
.I0(a[22]),
.I1(b[22]),
.O(\blk00000001/sig000000fd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000cf (
.I0(a[21]),
.I1(b[21]),
.O(\blk00000001/sig000000e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ce (
.I0(a[20]),
.I1(b[20]),
.O(\blk00000001/sig000000e0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000cd (
.I0(a[19]),
.I1(b[19]),
.O(\blk00000001/sig000000e1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000cc (
.I0(a[18]),
.I1(b[18]),
.O(\blk00000001/sig000000e2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000cb (
.I0(a[17]),
.I1(b[17]),
.O(\blk00000001/sig000000e3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ca (
.I0(a[16]),
.I1(b[16]),
.O(\blk00000001/sig000000e4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c9 (
.I0(a[15]),
.I1(b[15]),
.O(\blk00000001/sig000000e5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c8 (
.I0(a[14]),
.I1(b[14]),
.O(\blk00000001/sig000000e7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c7 (
.I0(a[13]),
.I1(b[13]),
.O(\blk00000001/sig000000cf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c6 (
.I0(a[12]),
.I1(b[12]),
.O(\blk00000001/sig000000ca )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c5 (
.I0(a[11]),
.I1(b[11]),
.O(\blk00000001/sig000000cb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c4 (
.I0(a[10]),
.I1(b[10]),
.O(\blk00000001/sig000000cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c3 (
.I0(a[9]),
.I1(b[9]),
.O(\blk00000001/sig000000cd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c2 (
.I0(a[8]),
.I1(b[8]),
.O(\blk00000001/sig000000ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c1 (
.I0(a[7]),
.I1(b[7]),
.O(\blk00000001/sig000000d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c0 (
.I0(a[6]),
.I1(b[6]),
.O(\blk00000001/sig000000ba )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bf (
.I0(a[5]),
.I1(b[5]),
.O(\blk00000001/sig000000b5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000be (
.I0(a[4]),
.I1(b[4]),
.O(\blk00000001/sig000000b6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bd (
.I0(a[3]),
.I1(b[3]),
.O(\blk00000001/sig000000b7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bc (
.I0(a[2]),
.I1(b[2]),
.O(\blk00000001/sig000000b8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bb (
.I0(a[1]),
.I1(b[1]),
.O(\blk00000001/sig000000b9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ba (
.I0(a[0]),
.I1(b[0]),
.O(\blk00000001/sig000000bb )
);
MUXCY \blk00000001/blk000000b9 (
.CI(\blk00000001/sig00000078 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000171 ),
.O(\blk00000001/sig00000152 )
);
XORCY \blk00000001/blk000000b8 (
.CI(\blk00000001/sig00000078 ),
.LI(\blk00000001/sig00000171 ),
.O(\blk00000001/sig00000151 )
);
MUXCY \blk00000001/blk000000b7 (
.CI(\blk00000001/sig00000152 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000170 ),
.O(\blk00000001/sig00000150 )
);
XORCY \blk00000001/blk000000b6 (
.CI(\blk00000001/sig00000152 ),
.LI(\blk00000001/sig00000170 ),
.O(\blk00000001/sig0000014f )
);
MUXCY \blk00000001/blk000000b5 (
.CI(\blk00000001/sig00000150 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000016f ),
.O(\blk00000001/sig0000014e )
);
XORCY \blk00000001/blk000000b4 (
.CI(\blk00000001/sig00000150 ),
.LI(\blk00000001/sig0000016f ),
.O(\blk00000001/sig0000014d )
);
XORCY \blk00000001/blk000000b3 (
.CI(\blk00000001/sig00000145 ),
.LI(\blk00000001/sig0000016e ),
.O(\blk00000001/sig0000014c )
);
MUXCY \blk00000001/blk000000b2 (
.CI(\blk00000001/sig00000145 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000016e ),
.O(\NLW_blk00000001/blk000000b2_O_UNCONNECTED )
);
MUXCY \blk00000001/blk000000b1 (
.CI(\blk00000001/sig0000014e ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000016d ),
.O(\blk00000001/sig0000014b )
);
XORCY \blk00000001/blk000000b0 (
.CI(\blk00000001/sig0000014e ),
.LI(\blk00000001/sig0000016d ),
.O(\blk00000001/sig0000014a )
);
MUXCY \blk00000001/blk000000af (
.CI(\blk00000001/sig0000014b ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000016c ),
.O(\blk00000001/sig00000149 )
);
XORCY \blk00000001/blk000000ae (
.CI(\blk00000001/sig0000014b ),
.LI(\blk00000001/sig0000016c ),
.O(\blk00000001/sig00000148 )
);
MUXCY \blk00000001/blk000000ad (
.CI(\blk00000001/sig00000149 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000016b ),
.O(\blk00000001/sig00000147 )
);
XORCY \blk00000001/blk000000ac (
.CI(\blk00000001/sig00000149 ),
.LI(\blk00000001/sig0000016b ),
.O(\blk00000001/sig00000146 )
);
MUXCY \blk00000001/blk000000ab (
.CI(\blk00000001/sig00000147 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000016a ),
.O(\blk00000001/sig00000145 )
);
XORCY \blk00000001/blk000000aa (
.CI(\blk00000001/sig00000147 ),
.LI(\blk00000001/sig0000016a ),
.O(\blk00000001/sig00000144 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000014c ),
.Q(s[36])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000144 ),
.Q(s[35])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000146 ),
.Q(s[34])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000148 ),
.Q(s[33])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000014a ),
.Q(s[32])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000014d ),
.Q(s[31])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000014f ),
.Q(s[30])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000151 ),
.Q(s[29])
);
MUXCY \blk00000001/blk000000a1 (
.CI(\blk00000001/sig0000009c ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000169 ),
.O(\blk00000001/sig00000143 )
);
XORCY \blk00000001/blk000000a0 (
.CI(\blk00000001/sig0000009c ),
.LI(\blk00000001/sig00000169 ),
.O(\blk00000001/sig00000142 )
);
MUXCY \blk00000001/blk0000009f (
.CI(\blk00000001/sig00000143 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000168 ),
.O(\blk00000001/sig00000141 )
);
XORCY \blk00000001/blk0000009e (
.CI(\blk00000001/sig00000143 ),
.LI(\blk00000001/sig00000168 ),
.O(\blk00000001/sig00000140 )
);
MUXCY \blk00000001/blk0000009d (
.CI(\blk00000001/sig00000141 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000167 ),
.O(\blk00000001/sig0000013f )
);
XORCY \blk00000001/blk0000009c (
.CI(\blk00000001/sig00000141 ),
.LI(\blk00000001/sig00000167 ),
.O(\blk00000001/sig0000013e )
);
XORCY \blk00000001/blk0000009b (
.CI(\blk00000001/sig00000136 ),
.LI(\blk00000001/sig00000166 ),
.O(\blk00000001/sig0000013d )
);
MUXCY \blk00000001/blk0000009a (
.CI(\blk00000001/sig00000136 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000166 ),
.O(\blk00000001/sig0000008a )
);
MUXCY \blk00000001/blk00000099 (
.CI(\blk00000001/sig0000013f ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000165 ),
.O(\blk00000001/sig0000013c )
);
XORCY \blk00000001/blk00000098 (
.CI(\blk00000001/sig0000013f ),
.LI(\blk00000001/sig00000165 ),
.O(\blk00000001/sig0000013b )
);
MUXCY \blk00000001/blk00000097 (
.CI(\blk00000001/sig0000013c ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000164 ),
.O(\blk00000001/sig0000013a )
);
XORCY \blk00000001/blk00000096 (
.CI(\blk00000001/sig0000013c ),
.LI(\blk00000001/sig00000164 ),
.O(\blk00000001/sig00000139 )
);
MUXCY \blk00000001/blk00000095 (
.CI(\blk00000001/sig0000013a ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000163 ),
.O(\blk00000001/sig00000138 )
);
XORCY \blk00000001/blk00000094 (
.CI(\blk00000001/sig0000013a ),
.LI(\blk00000001/sig00000163 ),
.O(\blk00000001/sig00000137 )
);
MUXCY \blk00000001/blk00000093 (
.CI(\blk00000001/sig00000138 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000162 ),
.O(\blk00000001/sig00000136 )
);
XORCY \blk00000001/blk00000092 (
.CI(\blk00000001/sig00000138 ),
.LI(\blk00000001/sig00000162 ),
.O(\blk00000001/sig00000135 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000091 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000013d ),
.Q(\blk00000001/sig00000092 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000090 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000135 ),
.Q(\blk00000001/sig00000091 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000137 ),
.Q(\blk00000001/sig00000090 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000139 ),
.Q(\blk00000001/sig0000008f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000013b ),
.Q(\blk00000001/sig0000008e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000013e ),
.Q(\blk00000001/sig0000008d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000140 ),
.Q(\blk00000001/sig0000008c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000142 ),
.Q(\blk00000001/sig0000008b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000089 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006d ),
.Q(\blk00000001/sig00000078 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000088 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006e ),
.Q(\blk00000001/sig00000089 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000087 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006f ),
.Q(\blk00000001/sig0000009c )
);
MUXCY \blk00000001/blk00000086 (
.CI(\blk00000001/sig00000089 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000161 ),
.O(\blk00000001/sig00000134 )
);
XORCY \blk00000001/blk00000085 (
.CI(\blk00000001/sig00000089 ),
.LI(\blk00000001/sig00000161 ),
.O(\blk00000001/sig00000133 )
);
MUXCY \blk00000001/blk00000084 (
.CI(\blk00000001/sig00000134 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000160 ),
.O(\blk00000001/sig00000132 )
);
XORCY \blk00000001/blk00000083 (
.CI(\blk00000001/sig00000134 ),
.LI(\blk00000001/sig00000160 ),
.O(\blk00000001/sig00000131 )
);
MUXCY \blk00000001/blk00000082 (
.CI(\blk00000001/sig00000132 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000015f ),
.O(\blk00000001/sig00000130 )
);
XORCY \blk00000001/blk00000081 (
.CI(\blk00000001/sig00000132 ),
.LI(\blk00000001/sig0000015f ),
.O(\blk00000001/sig0000012f )
);
XORCY \blk00000001/blk00000080 (
.CI(\blk00000001/sig00000129 ),
.LI(\blk00000001/sig0000015e ),
.O(\blk00000001/sig0000012e )
);
MUXCY \blk00000001/blk0000007f (
.CI(\blk00000001/sig00000129 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000015e ),
.O(\blk00000001/sig00000079 )
);
MUXCY \blk00000001/blk0000007e (
.CI(\blk00000001/sig00000130 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000015d ),
.O(\blk00000001/sig0000012d )
);
XORCY \blk00000001/blk0000007d (
.CI(\blk00000001/sig00000130 ),
.LI(\blk00000001/sig0000015d ),
.O(\blk00000001/sig0000012c )
);
MUXCY \blk00000001/blk0000007c (
.CI(\blk00000001/sig0000012d ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000015c ),
.O(\blk00000001/sig0000012b )
);
XORCY \blk00000001/blk0000007b (
.CI(\blk00000001/sig0000012d ),
.LI(\blk00000001/sig0000015c ),
.O(\blk00000001/sig0000012a )
);
MUXCY \blk00000001/blk0000007a (
.CI(\blk00000001/sig0000012b ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000015b ),
.O(\blk00000001/sig00000129 )
);
XORCY \blk00000001/blk00000079 (
.CI(\blk00000001/sig0000012b ),
.LI(\blk00000001/sig0000015b ),
.O(\blk00000001/sig00000128 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000078 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000012e ),
.Q(\blk00000001/sig00000080 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000077 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000128 ),
.Q(\blk00000001/sig0000007f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000076 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000012a ),
.Q(\blk00000001/sig0000007e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000075 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000012c ),
.Q(\blk00000001/sig0000007d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000074 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000012f ),
.Q(\blk00000001/sig0000007c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000073 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000131 ),
.Q(\blk00000001/sig0000007b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000072 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000133 ),
.Q(\blk00000001/sig0000007a )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig000000ad ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig0000015a ),
.O(\blk00000001/sig00000127 )
);
XORCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig000000ad ),
.LI(\blk00000001/sig0000015a ),
.O(\blk00000001/sig00000126 )
);
MUXCY \blk00000001/blk0000006f (
.CI(\blk00000001/sig00000127 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000159 ),
.O(\blk00000001/sig00000125 )
);
XORCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig00000127 ),
.LI(\blk00000001/sig00000159 ),
.O(\blk00000001/sig00000124 )
);
MUXCY \blk00000001/blk0000006d (
.CI(\blk00000001/sig00000125 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000158 ),
.O(\blk00000001/sig00000123 )
);
XORCY \blk00000001/blk0000006c (
.CI(\blk00000001/sig00000125 ),
.LI(\blk00000001/sig00000158 ),
.O(\blk00000001/sig00000122 )
);
XORCY \blk00000001/blk0000006b (
.CI(\blk00000001/sig0000011c ),
.LI(\blk00000001/sig00000157 ),
.O(\blk00000001/sig00000121 )
);
MUXCY \blk00000001/blk0000006a (
.CI(\blk00000001/sig0000011c ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000157 ),
.O(\blk00000001/sig0000009d )
);
MUXCY \blk00000001/blk00000069 (
.CI(\blk00000001/sig00000123 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000156 ),
.O(\blk00000001/sig00000120 )
);
XORCY \blk00000001/blk00000068 (
.CI(\blk00000001/sig00000123 ),
.LI(\blk00000001/sig00000156 ),
.O(\blk00000001/sig0000011f )
);
MUXCY \blk00000001/blk00000067 (
.CI(\blk00000001/sig00000120 ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000155 ),
.O(\blk00000001/sig0000011e )
);
XORCY \blk00000001/blk00000066 (
.CI(\blk00000001/sig00000120 ),
.LI(\blk00000001/sig00000155 ),
.O(\blk00000001/sig0000011d )
);
MUXCY \blk00000001/blk00000065 (
.CI(\blk00000001/sig0000011e ),
.DI(\blk00000001/sig0000006c ),
.S(\blk00000001/sig00000154 ),
.O(\blk00000001/sig0000011c )
);
XORCY \blk00000001/blk00000064 (
.CI(\blk00000001/sig0000011e ),
.LI(\blk00000001/sig00000154 ),
.O(\blk00000001/sig0000011b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000063 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000121 ),
.Q(\blk00000001/sig000000a4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000062 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000011b ),
.Q(\blk00000001/sig000000a3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000061 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000011d ),
.Q(\blk00000001/sig000000a2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000060 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000011f ),
.Q(\blk00000001/sig000000a1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000122 ),
.Q(\blk00000001/sig000000a0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000124 ),
.Q(\blk00000001/sig0000009f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000126 ),
.Q(\blk00000001/sig0000009e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000007a ),
.Q(s[22])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000007b ),
.Q(s[23])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000005a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000007c ),
.Q(s[24])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000059 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000007d ),
.Q(s[25])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000058 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000007e ),
.Q(s[26])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000057 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000007f ),
.Q(s[27])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000056 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000080 ),
.Q(s[28])
);
MUXCY \blk00000001/blk00000055 (
.CI(\blk00000001/sig0000006c ),
.DI(a[29]),
.S(\blk00000001/sig00000113 ),
.O(\blk00000001/sig0000011a )
);
MUXCY \blk00000001/blk00000054 (
.CI(\blk00000001/sig0000011a ),
.DI(a[30]),
.S(\blk00000001/sig00000112 ),
.O(\blk00000001/sig00000119 )
);
MUXCY \blk00000001/blk00000053 (
.CI(\blk00000001/sig00000119 ),
.DI(a[30]),
.S(\blk00000001/sig00000111 ),
.O(\blk00000001/sig00000118 )
);
MUXCY \blk00000001/blk00000052 (
.CI(\blk00000001/sig00000118 ),
.DI(a[30]),
.S(\blk00000001/sig00000110 ),
.O(\blk00000001/sig00000117 )
);
MUXCY \blk00000001/blk00000051 (
.CI(\blk00000001/sig00000117 ),
.DI(a[30]),
.S(\blk00000001/sig0000010f ),
.O(\blk00000001/sig00000116 )
);
MUXCY \blk00000001/blk00000050 (
.CI(\blk00000001/sig00000116 ),
.DI(a[30]),
.S(\blk00000001/sig0000010e ),
.O(\blk00000001/sig00000115 )
);
MUXCY \blk00000001/blk0000004f (
.CI(\blk00000001/sig00000115 ),
.DI(a[30]),
.S(\blk00000001/sig00000153 ),
.O(\blk00000001/sig00000114 )
);
XORCY \blk00000001/blk0000004e (
.CI(\blk00000001/sig0000011a ),
.LI(\blk00000001/sig00000112 ),
.O(\blk00000001/sig0000010c )
);
XORCY \blk00000001/blk0000004d (
.CI(\blk00000001/sig00000119 ),
.LI(\blk00000001/sig00000111 ),
.O(\blk00000001/sig0000010b )
);
XORCY \blk00000001/blk0000004c (
.CI(\blk00000001/sig00000118 ),
.LI(\blk00000001/sig00000110 ),
.O(\blk00000001/sig0000010a )
);
XORCY \blk00000001/blk0000004b (
.CI(\blk00000001/sig00000117 ),
.LI(\blk00000001/sig0000010f ),
.O(\blk00000001/sig00000109 )
);
XORCY \blk00000001/blk0000004a (
.CI(\blk00000001/sig00000116 ),
.LI(\blk00000001/sig0000010e ),
.O(\blk00000001/sig00000108 )
);
XORCY \blk00000001/blk00000049 (
.CI(\blk00000001/sig00000115 ),
.LI(\blk00000001/sig00000153 ),
.O(\blk00000001/sig00000107 )
);
XORCY \blk00000001/blk00000048 (
.CI(\blk00000001/sig00000114 ),
.LI(\blk00000001/sig0000010d ),
.O(\blk00000001/sig00000106 )
);
XORCY \blk00000001/blk00000047 (
.CI(\blk00000001/sig0000006c ),
.LI(\blk00000001/sig00000113 ),
.O(\blk00000001/sig00000105 )
);
MUXCY \blk00000001/blk00000046 (
.CI(\blk00000001/sig0000006c ),
.DI(a[22]),
.S(\blk00000001/sig000000fd ),
.O(\blk00000001/sig00000104 )
);
MUXCY \blk00000001/blk00000045 (
.CI(\blk00000001/sig000000fe ),
.DI(a[28]),
.S(\blk00000001/sig000000fc ),
.O(\blk00000001/sig00000103 )
);
MUXCY \blk00000001/blk00000044 (
.CI(\blk00000001/sig00000104 ),
.DI(a[23]),
.S(\blk00000001/sig000000fb ),
.O(\blk00000001/sig00000102 )
);
MUXCY \blk00000001/blk00000043 (
.CI(\blk00000001/sig00000102 ),
.DI(a[24]),
.S(\blk00000001/sig000000fa ),
.O(\blk00000001/sig00000101 )
);
MUXCY \blk00000001/blk00000042 (
.CI(\blk00000001/sig00000101 ),
.DI(a[25]),
.S(\blk00000001/sig000000f9 ),
.O(\blk00000001/sig00000100 )
);
MUXCY \blk00000001/blk00000041 (
.CI(\blk00000001/sig00000100 ),
.DI(a[26]),
.S(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig000000ff )
);
MUXCY \blk00000001/blk00000040 (
.CI(\blk00000001/sig000000ff ),
.DI(a[27]),
.S(\blk00000001/sig000000f7 ),
.O(\blk00000001/sig000000fe )
);
XORCY \blk00000001/blk0000003f (
.CI(\blk00000001/sig00000104 ),
.LI(\blk00000001/sig000000fb ),
.O(\blk00000001/sig000000f6 )
);
XORCY \blk00000001/blk0000003e (
.CI(\blk00000001/sig00000102 ),
.LI(\blk00000001/sig000000fa ),
.O(\blk00000001/sig000000f5 )
);
XORCY \blk00000001/blk0000003d (
.CI(\blk00000001/sig00000101 ),
.LI(\blk00000001/sig000000f9 ),
.O(\blk00000001/sig000000f4 )
);
XORCY \blk00000001/blk0000003c (
.CI(\blk00000001/sig00000100 ),
.LI(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig000000f3 )
);
XORCY \blk00000001/blk0000003b (
.CI(\blk00000001/sig000000ff ),
.LI(\blk00000001/sig000000f7 ),
.O(\blk00000001/sig000000f2 )
);
XORCY \blk00000001/blk0000003a (
.CI(\blk00000001/sig000000fe ),
.LI(\blk00000001/sig000000fc ),
.O(\blk00000001/sig000000f1 )
);
XORCY \blk00000001/blk00000039 (
.CI(\blk00000001/sig0000006c ),
.LI(\blk00000001/sig000000fd ),
.O(\blk00000001/sig000000f0 )
);
MUXCY \blk00000001/blk00000038 (
.CI(\blk00000001/sig0000006c ),
.DI(a[14]),
.S(\blk00000001/sig000000e7 ),
.O(\blk00000001/sig000000ef )
);
MUXCY \blk00000001/blk00000037 (
.CI(\blk00000001/sig000000e8 ),
.DI(a[21]),
.S(\blk00000001/sig000000e6 ),
.O(\blk00000001/sig000000ee )
);
MUXCY \blk00000001/blk00000036 (
.CI(\blk00000001/sig000000ef ),
.DI(a[15]),
.S(\blk00000001/sig000000e5 ),
.O(\blk00000001/sig000000ed )
);
MUXCY \blk00000001/blk00000035 (
.CI(\blk00000001/sig000000ed ),
.DI(a[16]),
.S(\blk00000001/sig000000e4 ),
.O(\blk00000001/sig000000ec )
);
MUXCY \blk00000001/blk00000034 (
.CI(\blk00000001/sig000000ec ),
.DI(a[17]),
.S(\blk00000001/sig000000e3 ),
.O(\blk00000001/sig000000eb )
);
MUXCY \blk00000001/blk00000033 (
.CI(\blk00000001/sig000000eb ),
.DI(a[18]),
.S(\blk00000001/sig000000e2 ),
.O(\blk00000001/sig000000ea )
);
MUXCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig000000ea ),
.DI(a[19]),
.S(\blk00000001/sig000000e1 ),
.O(\blk00000001/sig000000e9 )
);
MUXCY \blk00000001/blk00000031 (
.CI(\blk00000001/sig000000e9 ),
.DI(a[20]),
.S(\blk00000001/sig000000e0 ),
.O(\blk00000001/sig000000e8 )
);
XORCY \blk00000001/blk00000030 (
.CI(\blk00000001/sig000000ef ),
.LI(\blk00000001/sig000000e5 ),
.O(\blk00000001/sig000000df )
);
XORCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig000000ed ),
.LI(\blk00000001/sig000000e4 ),
.O(\blk00000001/sig000000de )
);
XORCY \blk00000001/blk0000002e (
.CI(\blk00000001/sig000000ec ),
.LI(\blk00000001/sig000000e3 ),
.O(\blk00000001/sig000000dd )
);
XORCY \blk00000001/blk0000002d (
.CI(\blk00000001/sig000000eb ),
.LI(\blk00000001/sig000000e2 ),
.O(\blk00000001/sig000000dc )
);
XORCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig000000ea ),
.LI(\blk00000001/sig000000e1 ),
.O(\blk00000001/sig000000db )
);
XORCY \blk00000001/blk0000002b (
.CI(\blk00000001/sig000000e9 ),
.LI(\blk00000001/sig000000e0 ),
.O(\blk00000001/sig000000da )
);
XORCY \blk00000001/blk0000002a (
.CI(\blk00000001/sig000000e8 ),
.LI(\blk00000001/sig000000e6 ),
.O(\blk00000001/sig000000d9 )
);
XORCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig0000006c ),
.LI(\blk00000001/sig000000e7 ),
.O(\blk00000001/sig000000d8 )
);
MUXCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig0000006c ),
.DI(a[7]),
.S(\blk00000001/sig000000d0 ),
.O(\blk00000001/sig000000d7 )
);
MUXCY \blk00000001/blk00000027 (
.CI(\blk00000001/sig000000d1 ),
.DI(a[13]),
.S(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000000d6 )
);
MUXCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig000000d7 ),
.DI(a[8]),
.S(\blk00000001/sig000000ce ),
.O(\blk00000001/sig000000d5 )
);
MUXCY \blk00000001/blk00000025 (
.CI(\blk00000001/sig000000d5 ),
.DI(a[9]),
.S(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000000d4 )
);
MUXCY \blk00000001/blk00000024 (
.CI(\blk00000001/sig000000d4 ),
.DI(a[10]),
.S(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000000d3 )
);
MUXCY \blk00000001/blk00000023 (
.CI(\blk00000001/sig000000d3 ),
.DI(a[11]),
.S(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000000d2 )
);
MUXCY \blk00000001/blk00000022 (
.CI(\blk00000001/sig000000d2 ),
.DI(a[12]),
.S(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000000d1 )
);
XORCY \blk00000001/blk00000021 (
.CI(\blk00000001/sig000000d7 ),
.LI(\blk00000001/sig000000ce ),
.O(\blk00000001/sig000000c9 )
);
XORCY \blk00000001/blk00000020 (
.CI(\blk00000001/sig000000d5 ),
.LI(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000000c8 )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig000000d4 ),
.LI(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000000c7 )
);
XORCY \blk00000001/blk0000001e (
.CI(\blk00000001/sig000000d3 ),
.LI(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000000c6 )
);
XORCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig000000d2 ),
.LI(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000000c5 )
);
XORCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig000000d1 ),
.LI(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000000c4 )
);
XORCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig0000006c ),
.LI(\blk00000001/sig000000d0 ),
.O(\blk00000001/sig000000c3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000d6 ),
.Q(\blk00000001/sig000000a5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c4 ),
.Q(\blk00000001/sig000000ac )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000018 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c5 ),
.Q(\blk00000001/sig000000ab )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000017 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c6 ),
.Q(\blk00000001/sig000000aa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000016 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c7 ),
.Q(\blk00000001/sig000000a9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000015 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c8 ),
.Q(\blk00000001/sig000000a8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000014 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c9 ),
.Q(\blk00000001/sig000000a7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000013 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c3 ),
.Q(\blk00000001/sig000000a6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000012 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000000c1 ),
.Q(\blk00000001/sig000000ad )
);
MUXCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig0000006c ),
.DI(a[0]),
.S(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000c2 )
);
MUXCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig000000bc ),
.DI(a[6]),
.S(\blk00000001/sig000000ba ),
.O(\blk00000001/sig000000c1 )
);
MUXCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig000000c2 ),
.DI(a[1]),
.S(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000000c0 )
);
MUXCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig000000c0 ),
.DI(a[2]),
.S(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig000000bf )
);
MUXCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig000000bf ),
.DI(a[3]),
.S(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000000be )
);
MUXCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig000000be ),
.DI(a[4]),
.S(\blk00000001/sig000000b6 ),
.O(\blk00000001/sig000000bd )
);
MUXCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig000000bd ),
.DI(a[5]),
.S(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000000bc )
);
XORCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig000000c2 ),
.LI(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000000b4 )
);
XORCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig000000c0 ),
.LI(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig000000b3 )
);
XORCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig000000bf ),
.LI(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000000b2 )
);
XORCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig000000be ),
.LI(\blk00000001/sig000000b6 ),
.O(\blk00000001/sig000000b1 )
);
XORCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig000000bd ),
.LI(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000000b0 )
);
XORCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig000000bc ),
.LI(\blk00000001/sig000000ba ),
.O(\blk00000001/sig000000af )
);
XORCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig0000006c ),
.LI(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000ae )
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig0000006c )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig0000006b )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBN_1_V
`define SKY130_FD_SC_HD__DFBBN_1_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfbbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBN_1_V
|
module heap_simulation;
// Inputs
reg mclk = 0;
reg core_stall = 0;
reg [31:0] memory_dout = 31'b0;
reg [7:0] switch = 7'b0;
reg [3:0] button = 4'b0;
// Outputs
wire memory_read;
wire memory_write;
wire [31:0] memory_address;
wire [31:0] memory_din;
wire [7:0] seg;
wire [3:0] digit;
wire hsync;
wire vsync;
wire [7:0] color;
reg[31:0] heap[0:16777216];
// Instantiate the Unit Under Test (UUT)
processor uut (
.mclk(mclk),
.core_stall(core_stall),
.memory_read(memory_read),
.memory_write(memory_write),
.memory_address(memory_address),
.memory_din(memory_din),
.memory_dout(memory_dout),
.switch(switch),
.button(button),
.seg(seg),
.digit(digit),
.hsync(hsync),
.vsync(vsync),
.color(color)
);
parameter state_idle = 2'b00;
parameter state_read = 2'b01;
parameter state_write = 2'b10;
reg[1:0] state = state_idle;
reg[31:0] address;
initial begin
// Initialize Inputs
mclk = 0;
core_stall = 0;
memory_dout = 0;
switch = 0;
button = 0;
address = 0;
$readmemh("HelloApp_heap.txt", heap);
#100;
end
always begin
#10 mclk = !mclk;
end
always @ (posedge mclk) begin
case(state)
/*state_read: begin
core_stall <= 0;
memory_dout <= heap[address];
state <= state_idle;
end
state_write: begin
core_stall <= 0;
heap[address] <= memory_din;
state <= state_idle;
end*/
default: begin
if(memory_read) begin
//core_stall <= 1;
//address <= memory_address;
//state <= state_read;
core_stall <= 0;
memory_dout <= heap[memory_address];
state <= state_idle;
end else if(memory_write) begin
//core_stall <= 1;
//address <= memory_address;
//state <= state_write;
core_stall <= 0;
heap[memory_address] <= memory_din;
state <= state_idle;
end
end
endcase
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : sonic_single_port.sv
// Description : basic PHY with gearbox and blocksync
// Author : Han Wang
// Created On : Fri Apr 25 21:17:48 2014
// Last Modified By: Han Wang
// Last Modified On: Fri Apr 25 21:17:48 2014
// Update Count : 0
// Status : initial design for OSDI
module sonic_single_port (/*AUTOARG*/
// Outputs
xcvr_tx_dataout,
cntr_local_state,
xgmii_rx_data,
log_data,
log_valid,
log_delay,
// Inputs
xcvr_rx_datain,
xcvr_tx_clkout,
xcvr_rx_clkout,
xcvr_tx_ready,
xcvr_rx_ready,
ctrl_bypass_clksync,
ctrl_disable_clksync,
ctrl_clear_local_state,
ctrl_mode,
ctrl_disable_ecc,
ctrl_error_bound,
cntr_global_state,
xgmii_tx_data,
clk_in,
rst_in,
lpbk_endec,
timeout_init,
timeout_sync
);
// lower layer xcvr interface
output wire [39:0] xcvr_tx_dataout;
input wire [39:0] xcvr_rx_datain;
input wire xcvr_tx_clkout;
input wire xcvr_rx_clkout;
input wire xcvr_tx_ready;
input wire xcvr_rx_ready;
input wire ctrl_bypass_clksync; //ctrl_bypass clocksync
input wire ctrl_disable_clksync; //disable clocksync
input wire ctrl_clear_local_state; //ctrl_clear_local_state c_local counters
input wire ctrl_mode; //0 for NIC mode, 1 for switch mode
input wire ctrl_disable_ecc;
input wire [31:0] ctrl_error_bound;
input wire [52:0] cntr_global_state;
output wire [52:0] cntr_local_state;
// upper layer xgmii interface
input wire [71:0] xgmii_tx_data;
output wire [71:0] xgmii_rx_data;
input wire clk_in;
output wire [511:0] log_data;
output wire log_valid;
output wire [15:0] log_delay;
// system interface
input wire rst_in;
input wire lpbk_endec;
input wire [31:0] timeout_init;
input wire [31:0] timeout_sync;
wire [63:0] xgmii_txd;
wire [7:0] xgmii_txc;
wire [63:0] xgmii_rxd;
wire [7:0] xgmii_rxc;
wire lock;
wire [65:0] encoded_datain, decoded_dataout, clksync_dataout, loopback_dataout;
parameter INIT_TYPE=2'b01, ACK_TYPE=2'b10, BEACON_TYPE=2'b11;
// xgmii data conversion
assign xgmii_txc[7] = xgmii_tx_data[71];
assign xgmii_txc[6] = xgmii_tx_data[62];
assign xgmii_txc[5] = xgmii_tx_data[53];
assign xgmii_txc[4] = xgmii_tx_data[44];
assign xgmii_txc[3] = xgmii_tx_data[35];
assign xgmii_txc[2] = xgmii_tx_data[26];
assign xgmii_txc[1] = xgmii_tx_data[17];
assign xgmii_txc[0] = xgmii_tx_data[8];
assign xgmii_txd[63:56] = xgmii_tx_data[70:63];
assign xgmii_txd[55:48] = xgmii_tx_data[61:54];
assign xgmii_txd[47:40] = xgmii_tx_data[52:45];
assign xgmii_txd[39:32] = xgmii_tx_data[43:36];
assign xgmii_txd[31:24] = xgmii_tx_data[34:27];
assign xgmii_txd[23:16] = xgmii_tx_data[25:18];
assign xgmii_txd[15:8] = xgmii_tx_data[16:9];
assign xgmii_txd[7:0] = xgmii_tx_data[7:0];
assign xgmii_rx_data = {xgmii_rxc[7], xgmii_rxd[63:56],
xgmii_rxc[6], xgmii_rxd[55:48],
xgmii_rxc[5], xgmii_rxd[47:40],
xgmii_rxc[4], xgmii_rxd[39:32],
xgmii_rxc[3], xgmii_rxd[31:24],
xgmii_rxc[2], xgmii_rxd[23:16],
xgmii_rxc[1], xgmii_rxd[15:8],
xgmii_rxc[0], xgmii_rxd[7:0]};
// Clock synchronisation layer
// Use the link_fault_status, 00=No link fault, 01=Local Fault, 10=Remote Fault
// if transceiver ready, assume link ok.
// NOTE: this is not entirely safe, because we also need to make sure data in
// phy is valid (fifos, gearbox, etc). For testing purpose, we ignore the
// corner cases.
clocksync_sm clocksync_sm (
.reset(rst_in || ctrl_disable_clksync),
.clear(ctrl_clear_local_state),
.mode(ctrl_mode),
.disable_filter(ctrl_disable_ecc),
.thres(ctrl_error_bound),
.clock(clk_in),
.link_ok(xcvr_rx_ready && lock),
// axillary data saved to DDR3 ram
.export_data(log_data),
.export_valid(log_valid),
.export_delay(log_delay),
.c_global(cntr_global_state),
.c_local_o(cntr_local_state),
.encoded_datain(encoded_datain), // data from encoder
.clksync_dataout(clksync_dataout), // data from clksync to txchan
.decoded_dataout(decoded_dataout), // data from decoder
.init_timeout(timeout_init),
.sync_timeout(timeout_sync)
);
wire [65:0] bypass_dataout;
xgmii_mux mux_bypass (
.data0x(clksync_dataout),
.data1x(encoded_datain),
.data2x(),
.data3x(),
.sel({1'b0, ctrl_bypass_clksync}),
.clock(clk_in),
.result(bypass_dataout)
);
// XGMII encoder
encoder encoder_block (
.clk(clk_in),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.data_out(encoded_datain),
.t_type(),
.init(rst_in),
.enable(xcvr_tx_ready)
);
// TX channel
sonic_tx_chan_66 tx_chan (
.data_in(bypass_dataout),
.wr_clock(clk_in),
.data_out(xcvr_tx_dataout),
.rd_clock(xcvr_tx_clkout),
.reset(rst_in),
.xcvr_tx_ready(xcvr_tx_ready)
);
// XGMII decoder
decoder decoder_block (
.clk(clk_in),
.data_in(loopback_dataout),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.r_type(),
.sync_lock(lock),
.init(rst_in),
.idle_bus()
);
// RX channel
sonic_rx_chan_66 rx_chan (
.data_in(xcvr_rx_datain),
.wr_clock(xcvr_rx_clkout),
.data_out(decoded_dataout),
.rd_clock(clk_in),
.reset(rst_in),
.lock(lock),
.xcvr_rx_ready(xcvr_rx_ready)
);
// encoder to decoder loopback
xgmii_loopback lpbk (
.data0x(decoded_dataout),
.data1x(bypass_dataout),
.sel(lpbk_endec),
.result(loopback_dataout)
);
endmodule // sonic_single_port
|
module ARM_CU_ALU_TestBench2;
parameter sim_time = 750*2; // Num of Cycles * 2
wire IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode;
wire [3:0] CU;
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;
//ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output[3:0] CU, input MFC, Reset,Clk);
ControlUnit cu(IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);
always@(IR or CU)
begin
RSLCT = {CU,IR[15:8],IR[3:1], IR[19:16]};
end
reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout,Out;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);
reg S;
wire [3:0] FLAGS_OUT;
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(Rn,Rm, opcode, SR, Out,FLAGS_OUT,S,ALUSTORE);
initial fork
MFC = 0; Reset=1 ; Clk=0 ; SR =0; IR = 0 ;
#1 MFC = 1;#1 Reset=0 ;#1 #1 SR=FLAGS_OUT;#1 S=1; ; #1 IR[19:16] = 0 /* Rn */ ; #1 IR[3:0] = 0 /* Rm */; #1 IR[11:8] = 0 /* Rs */; #1 IR[15:12] = 0 /* Rd */;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench2.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench2);
$display(" Test Results" );
$monitor("Rn=%4h,Rm=%4h,opcode=%3d,Out=%3h,FLAGS_OUT=%3d,SR=%3d,S=%3d,ALUSTORE=%3d",Rn,Rm,opcode,Out,FLAGS_OUT,SR,S,ALUSTORE);
end
endmodule
//iverilog ARM_ALU.v controlunit2.v Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v ARM_CU_ALU_TestBench2.v |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 18:12:16
// Design Name:
// Module Name: ARINC429txtestbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ARINC429_tx_testbench ();
reg clk;
reg ce;
AR_TXD TX(
.clk(clk),
.Nvel(2'd2),
.ADR(8'h8D),
.DAT(23'h702D00),
.st(ce),
.TXD0(TXD0), // 0
.TXD1(TXD1) // 1
/* output wire ce, // (Tce=1/Vel)
output wire SLP, //
output reg en_tx =0, //
output wire T_cp, //
output reg FT_cp=0, //
output wire SDAT, //
output reg QM=0, //
output reg[5:0]cb_bit=0, //
output reg en_tx_word=0 // */
);
always
begin
clk = 0;
#10;
clk = 1;
#10;
end
initial
begin
ce = 0;
#95;
ce = 1;
# 30;
ce=0;
end
endmodule |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of lp_stdby
//
// Generated
// by: lutscher
// on: Fri Jun 26 13:24:43 2009
// cmd: /tools/mix/1.9//mix_1.pl -vinc global_project.i -nodelta LP-blue-pin-list.xls LP-paris-pin-list.xls LP-reallity-pin-list.xls LP-HIER.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author$
// $Id$
// $Date$
// $Log$
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
//
// Generator: mix_1.pl Revision: 1.3 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
`include "global_project.i"
//
//
// Start of Generated Module rtl of lp_stdby
//
// No user `defines in this module
module lp_stdby
//
// Generated Module lp_stdby_i1
//
(
reallity_in2_s,
blue_out2_s,
tes_s,
test5_s,
reallity_test_s,
reallity_gimick_s,
ext1_pad_do,
ext2_pad_do
);
// Generated Module Inputs:
input blue_out2_s;
input tes_s;
input test5_s;
input ext1_pad_do;
input ext2_pad_do;
// Generated Module Outputs:
output [31:0] reallity_in2_s;
output reallity_test_s;
output reallity_gimick_s;
// Generated Wires:
wire [31:0] reallity_in2_s;
wire blue_out2_s;
wire tes_s;
wire test5_s;
wire reallity_test_s;
wire reallity_gimick_s;
wire ext1_pad_do;
wire ext2_pad_do;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for reallity_i1
reallity reallity_i1 ( // LP reallity
.extout1_i(ext1_pad_do), // from bluePAD <-> Iocell connect (IO)
.extout2_i(ext2_pad_do), // from bluePAD <-> Iocell connect (IO)
.gimick_o(reallity_gimick_s), // from reallityto blue
.in2_o(reallity_in2_s), // from reallity (X4)to blue
.out2_i(blue_out2_s), // to reallityfrom blue
.sig_o(), // to blue
.tes_i(tes_s), // to reallityfrom blue
.test5_i(test5_s), // to reallityfrom blue
.test_o(reallity_test_s) // from reallityto blue
);
// End of Generated Instance Port Map for reallity_i1
endmodule
//
// End of Generated Module rtl of lp_stdby
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR4BB_PP_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_S_BLACKBOX_V
/**
* udp_dlatch$PR_pp$PKG$s: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$s (
Q ,
D ,
GATE ,
RESET ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input GATE ;
input RESET ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PR_PP_PKG_S_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND3B_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_BLACKBOX_V
|
/*
RC4 PRGA module implementation
Copyright Groundworks Technologies 2012-2013
Author: Alfredo Ortega [email protected]
[email protected]
This library is free software: you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation, either
version 3 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
`include "/home/guest/docto/FPGADesign/rc4-prbs/trunk/rc4.inc"
module rc4(clk,rst,output_ready,password_input,K);
input clk; // Clock
input rst; // Reset
input [7:0] password_input; // Password input
output output_ready; // Output valid
output [7:0] K; // Output port
wire clk, rst; // clock, reset
reg output_ready;
wire [7:0] password_input;
/* RC4 PRGA */
// Key
reg [7:0] key[0:`KEY_SIZE-1];
// S array
reg [7:0] S[0:256];
reg [9:0] discardCount;
// Key-scheduling state
`define KSS_KEYREAD 4'h0
`define KSS_KEYSCHED1 4'h1
`define KSS_KEYSCHED2 4'h2
`define KSS_KEYSCHED3 4'h3
`define KSS_CRYPTO 4'h4
`define KSS_CRYPTO2 4'h5
// Variable names from http://en.wikipedia.org/wiki/RC4
reg [3:0] KSState;
reg [7:0] i; // Counter
reg [7:0] j;
reg [7:0] K;
reg [7:0] tmp;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
i <= 8'h0;
KSState <= `KSS_KEYREAD;
output_ready <= 0;
j <= 0;
end
else
case (KSState)
`KSS_KEYREAD: begin // KSS_KEYREAD state: Read key from input
if (i == `KEY_SIZE)
begin
KSState <= `KSS_KEYSCHED1;
i<=8'h00;
end
else begin
i <= i+1;
key[i] <= password_input;
$display ("rc4: key[%d] = %08X",i,password_input);
end
end
/*
for i from 0 to 255
S[i] := i
endfor
*/
`KSS_KEYSCHED1: begin // KSS_KEYSCHED1: Increment counter for S initialization
S[i] <= i;
if (i == 8'hFF)
begin
KSState <= `KSS_KEYSCHED2;
i <= 8'h00;
end
else i <= i +1;
end
/*
j := 0
for i from 0 to 255
j := (j + S[i] + key[i mod keylength]) mod 256
swap values of S[i] and S[j]
endfor
*/
`KSS_KEYSCHED2: begin // KSS_KEYSCHED2: Initialize S array
j <= (j + S[i] + key[i % `KEY_SIZE]);
KSState <= `KSS_KEYSCHED3;
end
`KSS_KEYSCHED3: begin // KSS_KEYSCHED3: S array permutation
S[i]<=S[j];
S[j]<=S[i];
if (i == 8'hFF)
begin
KSState <= `KSS_CRYPTO;
i <= 8'h01;
j <= S[1];
discardCount <= 10'h0;
output_ready <= 0; // K not valid yet
end
else begin
i <= i + 1;
KSState <= `KSS_KEYSCHED2;
end
end
/*
i := 0
j := 0
while GeneratingOutput:
i := (i + 1) mod 256
j := (j + S[i]) mod 256
swap values of S[i] and S[j]
K := S[(S[i] + S[j]) mod 256]
output K
endwhile
*/
`KSS_CRYPTO: begin
S[i] <= S[j];
S[j] <= S[i]; // We can do this because of verilog.
tmp<=S[i]+S[j];
KSState <= `KSS_CRYPTO2;
output_ready <= 0;
end
`KSS_CRYPTO2: begin
K <= S[tmp];//S[ S[i]+S[j] ];
if (discardCount<10'h600) // discard first 1536 values - SSH RC4 compliant
discardCount<=discardCount+1;
else output_ready <= 1; // Valid K at output
i <= i+1;
// Here is the secret of 1-clock: we develop all possible values of j in the future
if (j==i+1)
j <= (j + S[i]);
else
if (i==255) j <= (j + S[0]);
else j <= (j + S[i+1]);
$display ("rc4: output = %08X",K);
KSState <= `KSS_CRYPTO;
end
default: begin
end
endcase
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: rep_jbi_sc0_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module rep_jbi_sc0_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_buf, scbuf_jbi_data_buf, jbi_scbuf_ecc_buf,
jbi_sctag_req_vld_buf, scbuf_jbi_ctag_vld_buf,
scbuf_jbi_ue_err_buf, sctag_jbi_iq_dequeue_buf,
sctag_jbi_wib_dequeue_buf, sctag_jbi_por_req_buf,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req
);
output [31:0] jbi_sctag_req_buf;
output [31:0] scbuf_jbi_data_buf;
output [6:0] jbi_scbuf_ecc_buf;
output jbi_sctag_req_vld_buf;
output scbuf_jbi_ctag_vld_buf;
output scbuf_jbi_ue_err_buf;
output sctag_jbi_iq_dequeue_buf;
output sctag_jbi_wib_dequeue_buf;
output sctag_jbi_por_req_buf;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
// This repeater bank is a row of flops
// There are a maximum of 10 flops per row.
assign jbi_sctag_req_buf = jbi_sctag_req ;
assign scbuf_jbi_data_buf = scbuf_jbi_data ;
assign jbi_scbuf_ecc_buf[6:0] = jbi_scbuf_ecc[6:0] ;
assign jbi_sctag_req_vld_buf = jbi_sctag_req_vld ;
assign scbuf_jbi_ctag_vld_buf = scbuf_jbi_ctag_vld ;
assign scbuf_jbi_ue_err_buf = scbuf_jbi_ue_err ;
assign sctag_jbi_iq_dequeue_buf = sctag_jbi_iq_dequeue ;
assign sctag_jbi_wib_dequeue_buf = sctag_jbi_wib_dequeue;
assign sctag_jbi_por_req_buf = sctag_jbi_por_req ;
endmodule
|
// --------------------------------------------------------------------
// Module: Sound.v
// Description: Sound module. This is NOT a sound blaster emulator.
// This module produces simple sounds by implementing a simple interface,
// The user simply writes a byte of data to the left and/or right channels.
// Then poll the status register which will raise a flag when ready for the
// next byte of data. Alternatively, it can generate an interupt to request
// the next byte.
//
// Sound uses 16 I/O addresses 0x0nn0 to 0x0nnF, nn can be anything
//
// I/O Address Description
// ----------- ------------------
// 0x0210 Left Channel
// 0x0211 Right Channel
// 0x0212 High byte of timing increment
// 0x0213 Low byte of timing increment
// 0x0215 Control, 0x01 to enable interupt, 0x00 for polled mode
// 0x0217 Status, 0x80 when ready for next data, else 0x00
//
// --------------------------------------------------------------------
module sound (
input wb_clk_i,
input wb_rst_i,
input [ 2:0] wb_adr_i,
input [ 1:0] wb_sel_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
input dac_clk,
output audio_L,
output audio_R
);
// --------------------------------------------------------------------
// Wishbone Handling
// --------------------------------------------------------------------
reg [7:0] sb_dat_o;
wire [3:0] sb_adr_i = {wb_adr_i, wb_sel_i[1]};
wire [7:0] sb_dat_i = wb_sel_i[0] ? wb_dat_i[7:0] : wb_dat_i[15:8]; // 16 to 8 bit
assign wb_dat_o = {sb_dat_o, sb_dat_o};
wire wb_ack_i = wb_stb_i & wb_cyc_i; // Immediate ack
wire wr_command = wb_ack_i & wb_we_i; // Wishbone write access, Singal to send
wire rd_command = wb_ack_i & ~wb_we_i; // Wishbone write access, Singal to send
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) wb_ack_o <= 1'b0;
else wb_ack_o <= wb_ack_i & ~wb_ack_o; // one clock delay on acknowledge output
end
// --------------------------------------------------------------------
// The following table lists the functions of the I/O ports:
// I/O Address Description Access
// ----------- -------------------
// Base + 0 Left channel data, write only
// Base + 1 Right channel data, write only
// Base + 2 High byte for timer, write only
// Base + 3 Low byte for timer, write only
// Base + 5 Control, write only
// Base + 7 Status, read only
// --------------------------------------------------------------------
`define REG_CHAN01 4'h0 // W - Channel 1
`define REG_CHAN02 4'h1 // W - Channel 1
`define REG_TIMERH 4'h2 // W - Timer increment high byte
`define REG_TIMERL 4'h3 // W - Timer increment low byte
`define REG_CONTRL 4'h5 // W - Control
`define REG_STATUS 4'h7 // R - Status
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// DefaultTime Constant
// --------------------------------------------------------------------
`define DSP_DEFAULT_RATE 16'd671 // Default sampling rate is 8Khz
// --------------------------------------------------------------------
// Sound Blaster Register behavior
// --------------------------------------------------------------------
reg start; // Start the timer
reg timeout; // Timer has timed out
reg [19:0] timer; // DAC output timer register
reg [15:0] time_inc; // DAC output time increment
wire [7:0] TMR_STATUS = {timeout, 7'h00};
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous Logic
if(wb_rst_i) begin
sb_dat_o <= 8'h00; // Default value
end
else begin
if(rd_command) begin
case(sb_adr_i) // Determine which register was read
`REG_STATUS: sb_dat_o <= TMR_STATUS; // DSP Read status
`REG_TIMERH: sb_dat_o <= time_inc[15:8]; // Read back the timing register
`REG_TIMERL: sb_dat_o <= time_inc[ 7:0]; // Read back the timing register
default: sb_dat_o <= 8'h00; // Default
endcase // End of case
end
end // End of Reset if
end // End Synchrounous always
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous Logic
if(wb_rst_i) begin
dsp_audio_l <= 8'h80; // default is equivalent to 1/2
dsp_audio_r <= 8'h80; // default is equivalent to 1/2
start <= 1'b0; // Timer not on
timeout <= 1'b0; // Not timed out
time_inc <= `DSP_DEFAULT_RATE; // Default value
end
else begin
if(wr_command) begin // If a write was requested
case(sb_adr_i) // Determine which register was writen to
`REG_CHAN01: begin
dsp_audio_l <= sb_dat_i; // Get the user data or data
start <= 1'b1;
timeout <= 1'b0;
end
`REG_CHAN02: begin
dsp_audio_r <= sb_dat_i; // Get the user data or data
start <= 1'b1;
timeout <= 1'b0;
end
`REG_TIMERH: time_inc[15:8] <= sb_dat_i; // Get the user data or data
`REG_TIMERL: time_inc[ 7:0] <= sb_dat_i; // Get the user data or data
default: ; // Default value
endcase // End of case
end // End of Write Command if
if(timed_out) begin
start <= 1'b0;
timeout <= 1'b1;
end
end // End of Reset if
end // End Synchrounous always
// --------------------------------------------------------------------
// Audio Timer interrupt Generation Section
// DAC Clock set to system clock which is 12,500,000Hz
// Interval = DAC_ClK / Incr = 12,500,000 / (1048576 / X ) = 8000Hz
// X = 1048576 / (12,500,000 / 8000) = 1048576 / 1562.5
// X = 671
// --------------------------------------------------------------------
wire timed_out = timer[19];
always @(posedge dac_clk) begin
if(wb_rst_i) begin
timer <= 20'd0;
end
else begin
if(start) timer <= timer + time_inc;
else timer <= 20'd0;
end
end
// --------------------------------------------------------------------
// PWM CLock Generation Section:
// We need to divide down the clock for PWM, dac_clk = 12.5Mhz
// then 12,500,000 / 512 = 24,414Hz which is a good sampling rate for audio
// 0 = 2
// 1 = 4
// 2 = 8 1,562,500Hz
// 3 = 16
// 4 = 32
// 5 = 64
// 6 = 128
// 7 = 256
// 8 = 512 24,414Hz
// --------------------------------------------------------------------
wire pwm_clk = clkdiv[2];
reg [8:0] clkdiv;
always @(posedge dac_clk) clkdiv <= clkdiv + 9'd1;
// --------------------------------------------------------------------
// Audio Generation Section
// --------------------------------------------------------------------
reg [7:0] dsp_audio_l;
reg [7:0] dsp_audio_r;
dac8 left (pwm_clk, dsp_audio_l, audio_L); // 8 bit pwm DAC
dac8 right(pwm_clk, dsp_audio_r, audio_R); // 8 bit pwm DAC
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: DAC8.v
// Description: 8 bit pwm DAC
// --------------------------------------------------------------------
module dac8(
input clk,
input [7:0] DAC_in,
output Audio_out
);
reg [8:0] DAC_Register;
always @(posedge clk) DAC_Register <= DAC_Register[7:0] + DAC_in;
assign Audio_out = DAC_Register[8];
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:12.0
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dcfifo_32in_32out_16kb (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
wr_data_count
);
input wire rst;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
input wire wr_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [31 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [31 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire [0 : 0] wr_data_count;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_FAMILY("artix7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(509),
.C_PROG_FULL_THRESH_NEGATE_VAL(508),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(1),
.C_WR_DEPTH(512),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(9'B0),
.prog_empty_thresh_assert(9'B0),
.prog_empty_thresh_negate(9'B0),
.prog_full_thresh(9'B0),
.prog_full_thresh_assert(9'B0),
.prog_full_thresh_negate(9'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(wr_data_count),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_1_V
`define SKY130_FD_SC_HVL__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLCLKP_BEHAVIORAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_BEHAVIORAL_V |
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
Eval compute in (next_weekday (next_weekday friday)).
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
Example test_next_friday:
(next_weekday thursday) = friday.
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
Check bool.
Check bool_ind.
Check bool_rec.
Check bool_rect.
Lemma duality : forall b:bool, b = true \/ b = false.
intro b.
elim b.
left. trivial.
right. trivial.
Qed.
Lemma duality_ind : forall b:bool, b = true \/ b = false.
induction b.
left.
reflexivity.
right.
reflexivity.
Qed.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match b1 with
| false => true
| true => negb b2
end.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match b1, b2, b3 with
| true, true, true => true
| _, _, _ => false
end.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => 1
| S n' => S n' * factorial n'
end.
Example test_factorial1: (factorial 3) = 6.
Proof. simpl. trivial. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. simpl. trivial. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool :=
match (beq_nat n m) with
| true => false
| false => (ble_nat n m)
end.
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H1 H2.
rewrite H1.
rewrite <- H2.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
SearchAbout plus.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m H.
rewrite -> plus_1_l.
rewrite <- H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
SearchAbout nat.
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Eval compute in negb true = true.
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n as [|n'].
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite H, H.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite H, H.
destruct b.
reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
(**
Lemma nandb_eq_orb_t_t :
andb false false <> orb false false.
Proof.
reflexivity.
Qed.
Lemma andb_eq_orb_f_f :
andb true true = orb true true.
Proof.
reflexivity.
Qed.
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c H.
destruct b, c.
apply
**)
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
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