text
stringlengths 938
1.05M
|
|---|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_TB_V
`define SKY130_FD_SC_HS__NAND2_TB_V
/**
* nand2: 2-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__nand2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_TB_V
|
module c1908 (
n227,
n902,
n217,
n237,
n143,
n131,
n110,
n134,
n952,
n221,
n900,
n140,
n113,
n234,
n146,
n122,
n472,
n104,
n107,
n128,
n953,
n101,
n125,
n224,
n116,
n210,
n475,
n119,
n478,
n898,
n214,
n137,
n469,
n66,
n72,
n69,
n54,
n18,
n24,
n75,
n60,
n39,
n45,
n42,
n30,
n63,
n57,
n9,
n21,
n51,
n33,
n6,
n15,
n12,
n3,
n27,
n48,
n36);
// Start PIs
input n227;
input n902;
input n217;
input n237;
input n143;
input n131;
input n110;
input n134;
input n952;
input n221;
input n900;
input n140;
input n113;
input n234;
input n146;
input n122;
input n472;
input n104;
input n107;
input n128;
input n953;
input n101;
input n125;
input n224;
input n116;
input n210;
input n475;
input n119;
input n478;
input n898;
input n214;
input n137;
input n469;
// Start POs
output n66;
output n72;
output n69;
output n54;
output n18;
output n24;
output n75;
output n60;
output n39;
output n45;
output n42;
output n30;
output n63;
output n57;
output n9;
output n21;
output n51;
output n33;
output n6;
output n15;
output n12;
output n3;
output n27;
output n48;
output n36;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_179;
wire net_176;
wire net_159;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire n18;
wire net_105;
wire net_62;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire net_117;
wire net_12;
wire net_151;
wire net_74;
wire net_53;
wire net_93;
wire n63;
wire net_168;
wire net_135;
wire n27;
wire net_130;
wire n113;
wire net_147;
wire net_127;
wire net_14;
wire n146;
wire net_113;
wire net_26;
wire net_76;
wire n128;
wire n101;
wire net_101;
wire net_32;
wire net_187;
wire net_111;
wire net_90;
wire net_40;
wire n116;
wire net_100;
wire n210;
wire n475;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire n119;
wire net_141;
wire net_160;
wire net_83;
wire n21;
wire net_115;
wire net_4;
wire n36;
wire net_95;
wire net_17;
wire net_173;
wire net_78;
wire net_27;
wire net_164;
wire n69;
wire net_56;
wire net_87;
wire net_0;
wire net_155;
wire net_35;
wire net_191;
wire n143;
wire net_22;
wire net_16;
wire net_181;
wire n131;
wire net_193;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire n952;
wire n57;
wire net_42;
wire n9;
wire net_120;
wire net_109;
wire n12;
wire net_80;
wire net_65;
wire net_50;
wire net_162;
wire n234;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire n122;
wire net_136;
wire net_134;
wire n107;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire n45;
wire net_185;
wire net_34;
wire net_108;
wire n478;
wire net_183;
wire net_178;
wire net_150;
wire net_63;
wire n137;
wire n227;
wire n902;
wire n72;
wire net_152;
wire net_116;
wire net_30;
wire net_189;
wire n54;
wire net_175;
wire net_91;
wire n237;
wire n75;
wire net_106;
wire net_99;
wire net_24;
wire net_55;
wire net_186;
wire n39;
wire n60;
wire net_46;
wire net_140;
wire net_118;
wire net_148;
wire net_104;
wire n42;
wire net_146;
wire n134;
wire net_72;
wire net_122;
wire n221;
wire net_25;
wire net_70;
wire n900;
wire n51;
wire net_7;
wire n140;
wire n48;
wire net_194;
wire net_172;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire n472;
wire n104;
wire net_138;
wire net_13;
wire net_184;
wire net_94;
wire net_11;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire n30;
wire net_196;
wire net_170;
wire net_29;
wire net_68;
wire net_149;
wire net_142;
wire net_77;
wire n898;
wire n214;
wire net_20;
wire net_31;
wire n3;
wire n469;
wire net_36;
wire net_49;
wire net_158;
wire net_15;
wire net_41;
wire net_57;
wire n217;
wire net_71;
wire net_153;
wire net_156;
wire net_3;
wire net_84;
wire net_174;
wire net_154;
wire net_112;
wire net_92;
wire net_1;
wire net_103;
wire net_139;
wire n110;
wire net_43;
wire net_10;
wire net_180;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_171;
wire net_79;
wire n15;
wire net_143;
wire net_97;
wire net_190;
wire n66;
wire net_88;
wire net_182;
wire net_192;
wire net_145;
wire net_60;
wire n953;
wire net_81;
wire n24;
wire net_163;
wire net_58;
wire n125;
wire net_82;
wire net_67;
wire n224;
wire net_64;
wire net_37;
wire net_188;
wire net_110;
wire net_121;
wire net_73;
wire net_33;
wire net_48;
wire net_177;
wire net_86;
wire net_75;
wire net_8;
wire net_133;
wire n6;
wire n33;
wire net_195;
wire net_125;
// Start cells
NAND3_X1 inst_145 ( .A3(net_142), .A2(net_121), .ZN(net_120), .A1(net_119) );
NOR2_X1 inst_103 ( .ZN(net_60), .A1(net_59), .A2(net_58) );
NOR2_X1 inst_125 ( .ZN(net_162), .A2(net_153), .A1(net_152) );
AND4_X1 inst_207 ( .A1(net_121), .ZN(net_115), .A3(net_114), .A4(net_113), .A2(net_94) );
NAND4_X1 inst_138 ( .ZN(net_149), .A2(net_121), .A3(net_114), .A1(net_111), .A4(net_100) );
NAND2_X1 inst_159 ( .ZN(net_101), .A2(net_21), .A1(n214) );
AND2_X4 inst_218 ( .A1(net_114), .ZN(net_107), .A2(net_94) );
XOR2_X1 inst_15 ( .Z(net_82), .A(net_75), .B(n469) );
INV_X1 inst_197 ( .ZN(net_143), .A(net_88) );
NOR2_X1 inst_134 ( .A2(net_195), .A1(net_194), .ZN(n57) );
NAND2_X1 inst_179 ( .ZN(net_157), .A2(net_144), .A1(net_143) );
XOR2_X1 inst_24 ( .A(net_156), .Z(n12), .B(n110) );
NOR2_X1 inst_114 ( .A2(net_130), .ZN(net_118), .A1(net_88) );
XOR2_X1 inst_6 ( .Z(net_13), .A(n137), .B(n134) );
INV_X1 inst_194 ( .ZN(net_85), .A(net_80) );
NOR2_X1 inst_131 ( .A1(net_194), .A2(net_187), .ZN(n54) );
OR2_X4 inst_76 ( .A1(net_121), .ZN(net_110), .A2(net_31) );
AND2_X4 inst_214 ( .A1(net_59), .A2(net_58), .ZN(net_57) );
NAND2_X1 inst_180 ( .ZN(net_160), .A2(net_144), .A1(net_142) );
NAND2_X1 inst_160 ( .ZN(net_22), .A2(net_2), .A1(n953) );
NAND3_X1 inst_150 ( .ZN(net_181), .A3(net_180), .A1(n902), .A2(n472) );
XNOR2_X1 inst_33 ( .ZN(net_36), .A(net_7), .B(n110) );
NAND2_X1 inst_172 ( .ZN(net_126), .A1(net_108), .A2(net_107) );
NOR4_X1 inst_83 ( .ZN(net_183), .A4(net_175), .A2(net_170), .A1(net_115), .A3(net_112) );
XNOR2_X1 inst_47 ( .ZN(net_65), .B(net_43), .A(net_10) );
XOR2_X1 inst_19 ( .A(net_145), .Z(n18), .B(n116) );
NOR2_X1 inst_123 ( .ZN(net_144), .A2(net_128), .A1(net_89) );
NOR2_X1 inst_121 ( .ZN(net_146), .A1(net_126), .A2(net_103) );
XOR2_X1 inst_2 ( .Z(net_7), .A(n128), .B(n119) );
XOR2_X1 inst_8 ( .Z(net_16), .A(n143), .B(n128) );
NOR2_X1 inst_118 ( .ZN(net_111), .A1(net_101), .A2(net_99) );
NOR3_X1 inst_86 ( .ZN(net_56), .A3(net_52), .A1(net_51), .A2(net_11) );
NAND2_X1 inst_153 ( .ZN(net_3), .A2(n898), .A1(n224) );
XOR2_X1 inst_20 ( .A(net_146), .Z(n15), .B(n113) );
XOR2_X1 inst_27 ( .Z(net_176), .A(net_171), .B(net_56) );
XNOR2_X1 inst_38 ( .ZN(net_59), .A(net_26), .B(n101) );
NOR2_X1 inst_100 ( .ZN(net_31), .A2(net_30), .A1(n900) );
XNOR2_X1 inst_52 ( .ZN(net_71), .A(net_69), .B(net_65) );
NOR3_X1 inst_90 ( .ZN(net_155), .A1(net_134), .A2(net_133), .A3(net_132) );
NAND4_X1 inst_140 ( .ZN(net_175), .A4(net_174), .A2(net_172), .A3(net_137), .A1(n952) );
AND4_X1 inst_209 ( .ZN(net_196), .A1(net_191), .A2(net_131), .A3(net_125), .A4(net_122) );
AND3_X4 inst_211 ( .ZN(net_129), .A2(net_110), .A1(net_106), .A3(net_105) );
AND2_X4 inst_221 ( .ZN(net_159), .A1(net_143), .A2(net_141) );
XNOR2_X1 inst_40 ( .ZN(net_47), .A(net_46), .B(net_36) );
NAND2_X1 inst_162 ( .ZN(net_29), .A2(net_27), .A1(n221) );
NAND2_X1 inst_167 ( .ZN(net_130), .A1(net_86), .A2(net_85) );
NOR3_X1 inst_93 ( .ZN(net_156), .A1(net_134), .A3(net_132), .A2(net_130) );
NOR4_X1 inst_81 ( .ZN(net_136), .A1(net_116), .A4(net_102), .A2(net_87), .A3(net_86) );
NOR3_X1 inst_95 ( .ZN(net_169), .A1(net_166), .A2(net_165), .A3(net_164) );
XOR2_X1 inst_1 ( .Z(net_6), .A(n119), .B(n116) );
XNOR2_X1 inst_72 ( .ZN(net_195), .B(net_190), .A(net_59) );
NAND4_X1 inst_139 ( .ZN(net_164), .A1(net_160), .A3(net_151), .A4(net_150), .A2(net_138) );
NAND2_X1 inst_155 ( .A2(net_172), .ZN(net_9), .A1(n227) );
XNOR2_X1 inst_59 ( .B(net_150), .ZN(n36), .A(n134) );
NOR2_X1 inst_135 ( .A2(net_196), .A1(net_154), .ZN(n75) );
INV_X1 inst_196 ( .ZN(net_133), .A(net_90) );
XNOR2_X1 inst_44 ( .ZN(net_61), .B(net_47), .A(net_39) );
XNOR2_X1 inst_55 ( .ZN(net_86), .A(net_73), .B(net_62) );
NAND2_X1 inst_174 ( .ZN(net_128), .A1(net_110), .A2(net_109) );
NOR2_X1 inst_115 ( .A1(net_134), .ZN(net_95), .A2(net_89) );
XNOR2_X1 inst_37 ( .ZN(net_38), .A(net_13), .B(n131) );
AND3_X4 inst_210 ( .A2(net_172), .ZN(net_121), .A3(net_24), .A1(n952) );
NAND3_X1 inst_148 ( .A3(net_180), .ZN(net_178), .A1(n902), .A2(n478) );
NAND2_X1 inst_164 ( .ZN(net_89), .A1(net_86), .A2(net_80) );
INV_X1 inst_191 ( .ZN(net_116), .A(net_29) );
XOR2_X1 inst_5 ( .Z(net_12), .A(n122), .B(n113) );
NAND2_X1 inst_157 ( .A2(net_172), .ZN(net_18), .A1(n224) );
NOR3_X1 inst_84 ( .ZN(net_19), .A2(net_1), .A3(n953), .A1(n237) );
XNOR2_X1 inst_51 ( .ZN(net_74), .A(net_54), .B(net_37) );
NAND3_X1 inst_142 ( .ZN(net_30), .A1(net_24), .A3(n953), .A2(n902) );
OR2_X4 inst_80 ( .A1(net_134), .ZN(net_123), .A2(net_93) );
NAND2_X1 inst_173 ( .ZN(net_132), .A2(net_109), .A1(net_108) );
NOR2_X1 inst_105 ( .ZN(net_66), .A2(net_65), .A1(net_8) );
AND2_X4 inst_213 ( .A2(net_53), .ZN(net_51), .A1(net_50) );
XNOR2_X1 inst_68 ( .ZN(net_189), .A(net_179), .B(net_77) );
AND2_X4 inst_216 ( .A1(net_69), .ZN(net_68), .A2(net_67) );
OR2_X4 inst_78 ( .ZN(net_127), .A1(net_86), .A2(net_80) );
XNOR2_X1 inst_42 ( .ZN(net_53), .A(net_44), .B(net_38) );
NAND2_X1 inst_175 ( .ZN(net_147), .A1(net_129), .A2(net_118) );
XNOR2_X1 inst_53 ( .ZN(net_77), .A(net_55), .B(net_35) );
INV_X1 inst_205 ( .ZN(net_170), .A(net_169) );
NAND2_X1 inst_177 ( .ZN(net_151), .A1(net_129), .A2(net_104) );
NAND2_X1 inst_183 ( .ZN(net_173), .A1(net_172), .A2(net_168) );
NOR2_X1 inst_133 ( .A1(net_194), .A2(net_193), .ZN(n51) );
XOR2_X1 inst_26 ( .A(net_159), .Z(n6), .B(n104) );
NAND3_X1 inst_151 ( .ZN(net_182), .A3(net_180), .A1(n902), .A2(n469) );
NOR2_X1 inst_112 ( .ZN(net_84), .A1(net_83), .A2(net_82) );
XNOR2_X1 inst_64 ( .B(net_176), .A(net_22), .ZN(n72) );
NOR2_X1 inst_107 ( .ZN(net_75), .A2(net_74), .A1(n902) );
XNOR2_X1 inst_67 ( .ZN(net_188), .A(net_178), .B(net_63) );
NAND2_X1 inst_181 ( .ZN(net_166), .A1(net_148), .A2(net_147) );
NOR2_X1 inst_127 ( .ZN(net_185), .A2(net_184), .A1(net_73) );
XNOR2_X1 inst_70 ( .ZN(net_192), .A(net_185), .B(net_61) );
INV_X1 inst_186 ( .ZN(net_172), .A(n953) );
NOR2_X1 inst_129 ( .A1(net_194), .A2(net_189), .ZN(n60) );
NOR3_X1 inst_92 ( .ZN(net_139), .A1(net_135), .A2(net_133), .A3(net_128) );
XNOR2_X1 inst_29 ( .ZN(net_42), .A(net_6), .B(n113) );
INV_X1 inst_189 ( .ZN(net_1), .A(n214) );
XOR2_X1 inst_17 ( .Z(net_100), .A(net_79), .B(net_76) );
XOR2_X1 inst_11 ( .Z(net_39), .B(net_25), .A(n137) );
NAND3_X1 inst_146 ( .A3(net_143), .ZN(net_122), .A2(net_121), .A1(net_119) );
INV_X1 inst_188 ( .ZN(net_14), .A(n902) );
XOR2_X1 inst_14 ( .Z(net_80), .B(net_72), .A(n472) );
INV_X1 inst_202 ( .ZN(net_104), .A(net_103) );
AND4_X1 inst_206 ( .A1(net_121), .A4(net_113), .ZN(net_112), .A2(net_106), .A3(net_105) );
INV_X1 inst_187 ( .ZN(net_0), .A(n210) );
NOR2_X1 inst_122 ( .ZN(net_141), .A2(net_132), .A1(net_127) );
XNOR2_X1 inst_31 ( .ZN(net_34), .A(net_5), .B(n107) );
XOR2_X1 inst_25 ( .A(net_158), .Z(n9), .B(n107) );
NOR2_X1 inst_126 ( .ZN(net_171), .A2(net_167), .A1(n953) );
NAND2_X1 inst_158 ( .ZN(net_20), .A2(net_3), .A1(n953) );
NAND3_X1 inst_141 ( .A3(net_172), .ZN(net_23), .A1(n234), .A2(n217) );
XNOR2_X1 inst_62 ( .B(net_160), .ZN(n30), .A(n128) );
INV_X1 inst_200 ( .ZN(net_98), .A(net_97) );
NOR2_X1 inst_110 ( .ZN(net_142), .A2(net_83), .A1(net_81) );
OR3_X2 inst_74 ( .ZN(net_131), .A3(net_130), .A2(net_124), .A1(net_123) );
XNOR2_X1 inst_57 ( .B(net_147), .ZN(n42), .A(n140) );
XNOR2_X1 inst_35 ( .ZN(net_37), .A(net_15), .B(net_9) );
NOR2_X1 inst_99 ( .ZN(net_194), .A1(net_172), .A2(n952) );
XNOR2_X1 inst_48 ( .ZN(net_63), .A(net_48), .B(net_23) );
XNOR2_X1 inst_69 ( .ZN(net_190), .B(net_181), .A(net_58) );
XNOR2_X1 inst_46 ( .ZN(net_58), .B(net_53), .A(net_42) );
NOR4_X1 inst_82 ( .ZN(net_161), .A2(net_159), .A4(net_158), .A3(net_156), .A1(net_155) );
NAND4_X1 inst_136 ( .ZN(net_102), .A1(net_101), .A4(net_100), .A3(net_85), .A2(net_84) );
XNOR2_X1 inst_30 ( .ZN(net_33), .A(net_16), .B(n134) );
NOR2_X1 inst_102 ( .A2(net_53), .ZN(net_52), .A1(net_50) );
NOR2_X1 inst_108 ( .ZN(net_78), .A2(net_77), .A1(n902) );
NAND2_X1 inst_165 ( .ZN(net_135), .A1(net_87), .A2(net_83) );
XNOR2_X1 inst_32 ( .ZN(net_35), .A(net_12), .B(n104) );
XOR2_X1 inst_22 ( .A(net_155), .Z(n3), .B(n101) );
NAND3_X1 inst_144 ( .ZN(net_138), .A3(net_118), .A1(net_110), .A2(net_107) );
XNOR2_X1 inst_34 ( .ZN(net_41), .A(net_4), .B(n101) );
XOR2_X1 inst_12 ( .Z(net_43), .A(net_42), .B(net_41) );
INV_X1 inst_195 ( .A(net_114), .ZN(net_93) );
XNOR2_X1 inst_56 ( .B(net_138), .ZN(n27), .A(n125) );
XNOR2_X1 inst_71 ( .ZN(net_193), .A(net_186), .B(net_71) );
XOR2_X1 inst_21 ( .A(net_139), .Z(n45), .B(n143) );
NOR2_X1 inst_104 ( .ZN(net_64), .A2(net_63), .A1(n902) );
XNOR2_X1 inst_60 ( .B(net_151), .ZN(n33), .A(n131) );
AND2_X4 inst_215 ( .ZN(net_62), .A2(net_61), .A1(net_14) );
NAND2_X1 inst_169 ( .A1(net_142), .ZN(net_97), .A2(net_90) );
NAND2_X1 inst_168 ( .A1(net_101), .A2(net_100), .ZN(net_91) );
NOR2_X1 inst_97 ( .A1(net_172), .ZN(net_8), .A2(n898) );
NAND2_X1 inst_161 ( .ZN(net_79), .A2(net_21), .A1(n210) );
NOR2_X1 inst_124 ( .ZN(net_163), .A1(net_146), .A2(net_145) );
XOR2_X1 inst_18 ( .A(net_152), .Z(n21), .B(n119) );
XOR2_X1 inst_16 ( .Z(net_83), .A(net_78), .B(n475) );
AND4_X1 inst_208 ( .ZN(net_191), .A2(net_183), .A4(net_149), .A1(net_120), .A3(net_117) );
NOR3_X1 inst_88 ( .ZN(net_76), .A1(net_70), .A3(net_68), .A2(n902) );
AND2_X4 inst_220 ( .ZN(net_158), .A1(net_142), .A2(net_141) );
XOR2_X1 inst_3 ( .Z(net_10), .A(n122), .B(n110) );
NAND2_X1 inst_156 ( .ZN(net_27), .A2(net_14), .A1(n234) );
XOR2_X1 inst_9 ( .Z(net_17), .A(n146), .B(n143) );
NOR2_X1 inst_113 ( .A2(net_100), .ZN(net_94), .A1(net_28) );
NAND2_X1 inst_170 ( .A1(net_143), .ZN(net_103), .A2(net_90) );
INV_X1 inst_198 ( .ZN(net_105), .A(net_91) );
XNOR2_X1 inst_50 ( .ZN(net_55), .B(net_49), .A(net_46) );
NAND4_X1 inst_137 ( .A1(net_121), .ZN(net_117), .A3(net_116), .A4(net_113), .A2(net_92) );
INV_X1 inst_199 ( .ZN(net_96), .A(net_95) );
XNOR2_X1 inst_41 ( .ZN(net_48), .B(net_34), .A(net_33) );
NOR2_X1 inst_130 ( .A1(net_194), .A2(net_188), .ZN(n63) );
NOR3_X1 inst_91 ( .ZN(net_153), .A1(net_135), .A2(net_127), .A3(net_126) );
NOR2_X1 inst_132 ( .A1(net_194), .A2(net_192), .ZN(n66) );
NAND3_X1 inst_143 ( .A3(net_172), .ZN(net_25), .A1(n234), .A2(n221) );
NAND2_X1 inst_176 ( .ZN(net_148), .A1(net_129), .A2(net_95) );
NAND2_X1 inst_152 ( .ZN(net_2), .A2(n900), .A1(n227) );
XNOR2_X1 inst_58 ( .B(net_148), .ZN(n39), .A(n137) );
XNOR2_X1 inst_36 ( .ZN(net_44), .A(net_17), .B(n128) );
NAND3_X1 inst_147 ( .ZN(net_168), .A2(net_163), .A1(net_162), .A3(net_161) );
NOR3_X1 inst_87 ( .ZN(net_72), .A3(net_60), .A1(net_57), .A2(n902) );
XNOR2_X1 inst_61 ( .B(net_157), .ZN(n48), .A(n146) );
INV_X1 inst_203 ( .ZN(net_137), .A(net_136) );
XNOR2_X1 inst_45 ( .ZN(net_54), .B(net_53), .A(net_41) );
NOR3_X1 inst_96 ( .ZN(net_167), .A2(net_166), .A1(net_165), .A3(net_164) );
AND3_X4 inst_212 ( .ZN(net_174), .A1(net_163), .A2(net_162), .A3(net_161) );
NOR2_X1 inst_101 ( .ZN(net_32), .A2(net_30), .A1(n898) );
XOR2_X1 inst_0 ( .Z(net_5), .A(n122), .B(n116) );
NAND2_X1 inst_184 ( .ZN(net_180), .A2(net_174), .A1(net_169) );
XOR2_X1 inst_10 ( .B(net_50), .Z(net_46), .A(n146) );
XOR2_X1 inst_4 ( .Z(net_50), .A(n140), .B(n125) );
XNOR2_X1 inst_65 ( .B(net_177), .A(net_20), .ZN(n69) );
NAND2_X1 inst_178 ( .ZN(net_150), .A1(net_129), .A2(net_98) );
NOR3_X1 inst_89 ( .A3(net_127), .ZN(net_119), .A2(net_93), .A1(net_91) );
XNOR2_X1 inst_28 ( .ZN(net_4), .A(n107), .B(n104) );
NOR2_X1 inst_111 ( .ZN(net_90), .A1(net_86), .A2(net_85) );
XNOR2_X1 inst_66 ( .ZN(net_187), .A(net_182), .B(net_74) );
NOR2_X1 inst_117 ( .ZN(net_92), .A2(net_91), .A1(net_82) );
NOR2_X1 inst_98 ( .A1(net_172), .ZN(net_11), .A2(n900) );
INV_X1 inst_190 ( .A(net_101), .ZN(net_28) );
XNOR2_X1 inst_63 ( .ZN(net_177), .B(net_173), .A(net_66) );
XOR2_X1 inst_7 ( .Z(net_15), .A(n140), .B(n110) );
INV_X1 inst_204 ( .ZN(net_140), .A(net_139) );
NAND2_X1 inst_185 ( .ZN(net_184), .A2(net_180), .A1(n902) );
NAND2_X1 inst_182 ( .ZN(net_165), .A1(net_157), .A2(net_140) );
XNOR2_X1 inst_49 ( .ZN(net_69), .A(net_45), .B(net_18) );
NOR2_X1 inst_120 ( .ZN(net_145), .A1(net_126), .A2(net_97) );
NAND2_X1 inst_154 ( .ZN(net_24), .A2(n237), .A1(n234) );
XOR2_X1 inst_13 ( .Z(net_45), .B(net_44), .A(n125) );
NOR2_X1 inst_119 ( .ZN(net_152), .A1(net_126), .A2(net_96) );
OR2_X4 inst_75 ( .ZN(net_21), .A2(n902), .A1(n237) );
INV_X1 inst_192 ( .ZN(net_67), .A(net_65) );
NAND2_X1 inst_166 ( .ZN(net_88), .A2(net_83), .A1(net_81) );
NOR2_X1 inst_116 ( .A1(net_134), .A2(net_127), .ZN(net_113) );
NAND2_X1 inst_163 ( .ZN(net_73), .A2(net_27), .A1(n217) );
NOR3_X1 inst_85 ( .ZN(net_26), .A2(net_0), .A3(n953), .A1(n237) );
XNOR2_X1 inst_54 ( .ZN(net_81), .A(net_64), .B(n478) );
OR2_X4 inst_79 ( .ZN(net_134), .A1(net_87), .A2(net_83) );
NOR2_X1 inst_109 ( .A1(net_116), .ZN(net_114), .A2(net_82) );
NOR2_X1 inst_106 ( .ZN(net_70), .A1(net_69), .A2(net_67) );
AND2_X4 inst_219 ( .ZN(net_109), .A1(net_106), .A2(net_94) );
INV_X1 inst_201 ( .A(net_113), .ZN(net_99) );
INV_X1 inst_193 ( .ZN(net_87), .A(net_81) );
NAND3_X1 inst_149 ( .A3(net_180), .ZN(net_179), .A1(n902), .A2(n475) );
XNOR2_X1 inst_43 ( .ZN(net_49), .A(net_40), .B(n131) );
XNOR2_X1 inst_39 ( .ZN(net_40), .A(net_19), .B(n143) );
NOR2_X1 inst_128 ( .ZN(net_186), .A2(net_184), .A1(net_79) );
OR3_X2 inst_73 ( .A2(net_133), .ZN(net_125), .A1(net_124), .A3(net_123) );
AND2_X4 inst_217 ( .ZN(net_106), .A2(net_82), .A1(net_29) );
XOR2_X1 inst_23 ( .A(net_153), .Z(n24), .B(n122) );
NAND2_X1 inst_171 ( .ZN(net_124), .A1(net_121), .A2(net_105) );
OR2_X4 inst_77 ( .A1(net_121), .ZN(net_108), .A2(net_32) );
NOR3_X1 inst_94 ( .ZN(net_154), .A3(net_136), .A2(n953), .A1(n952) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_2_V
`define SKY130_FD_SC_LP__AND3B_2_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_2_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module replicates pixels in video data to enlarge the image. *
* *
******************************************************************************/
module altera_up_video_scaler_multiply_width (
// Inputs
clk,
reset,
stream_in_channel,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_channel,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 15; // Image's Channel Width
parameter DW = 15; // Image's data width
parameter MCW = 0; // Multiply width's counter width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [CW: 0] stream_in_channel;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output reg [CW: 0] stream_out_channel;
output reg [DW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [CW: 0] channel;
reg [DW: 0] data;
reg startofpacket;
reg endofpacket;
reg valid;
reg [MCW:0] enlarge_width_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_channel <= 'h0;
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_channel <= {channel, enlarge_width_counter};
stream_out_data <= data;
if (|(enlarge_width_counter))
stream_out_startofpacket <= 1'b0;
else
stream_out_startofpacket <= startofpacket;
if (&(enlarge_width_counter))
stream_out_endofpacket <= endofpacket;
else
stream_out_endofpacket <= 1'b0;
stream_out_valid <= valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
channel <= 'h0;
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
channel <= stream_in_channel;
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
valid <= stream_in_valid;
end
end
always @(posedge clk)
begin
if (reset)
enlarge_width_counter <= 'h0;
else if ((stream_out_ready | ~stream_out_valid) & valid)
enlarge_width_counter <= enlarge_width_counter + 1;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = (~valid) |
((&(enlarge_width_counter)) & (stream_out_ready | ~stream_out_valid));
// Internal assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_s_r_channel.v
// Version : v1.0
// Description: slave interface read channel.Read requests are processed to
// output the desired read data.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
//Specific WARNINGs moved to INFO by Vivado Synthesis Tool
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_s_r_channel
# (
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter C_ZERO_INVALID = 1 ,
parameter C_NO_EXCL = 0 ,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_S_AXI_ARUSER_WIDTH = 8 ,
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_ATG_AXI4LITE = 0
) (
// system
input Clk ,
input rst_l ,
//AR
input [C_S_AXI_ID_WIDTH-1:0] arid_s ,
input [31:0] araddr_s ,
input [7:0] arlen_s ,
input [2:0] arsize_s ,
input [1:0] arburst_s ,
input [0:0] arlock_s ,
input [3:0] arcache_s ,
input [2:0] arprot_s ,
input [3:0] arqos_s ,
input [C_S_AXI_ARUSER_WIDTH-1:0] aruser_s ,
input arvalid_s ,
output arready_s ,
//R
output [C_S_AXI_ID_WIDTH-1:0] rid_s ,
output rlast_s ,
output [C_S_AXI_DATA_WIDTH-1:0] rdata_s ,
output [1:0] rresp_s ,
output rvalid_s ,
input rready_s ,
// Register block
input reg1_sgl_slv_rd ,
output [15:0] rd_reg_decode ,
input [31:0] rd_reg_data_raw ,
input reg1_disallow_excl ,
output reg rddec6_valid_ff ,
//sw channel
output reg [71:0] slv_ex_info0_ff ,
input slv_ex_valid0_ff ,
output reg [71:0] slv_ex_info1_ff ,
output[71:0] slv_ex_info1 ,
input slv_ex_valid1_ff ,
output reg slv_ex_toggle_ff ,
output slv_ex_new_valid0 ,
output slv_ex_new_valid1 ,
output [15:0] ar_agen_addr ,
input [C_S_AXI_DATA_WIDTH-1:0] slvram_rd_out ,
//axi_traffic_gen_v2_0_cmdram input
output [15:0] ar_agen0_addr ,
output arfifo_valid ,
output [71:0] arfifo_out ,
input [127:0] cmd_out_mr_i
);
wire [31:0] base_addr = C_BASEADDR;
wire [31:0] high_addr = C_HIGHADDR;
wire [31:0] addr_mask = base_addr[31:0] ^ high_addr[31:0];
//wire [7:0] arlen8_s = arlen_s[7:0] | { 4'h0, arlen3_s[3:0] };
wire [7:0] arlen8_s = arlen_s[7:0] ;
wire [31:0] ar_addr_masked = araddr_s[31:0] & addr_mask[31:0];
//Address re-mapped
//wire ar_isslvram = (ar_addr_masked[22:16] != 'h0);
wire ar_isslvram = (ar_addr_masked[15:14] == 2'b11);
wire ar_iscmd = ~ar_isslvram && araddr_s[15];
wire [15:0] arbuf_id = arid_s[C_S_AXI_ID_WIDTH-1:0];
wire [71:0] arbuf_data = {
arbuf_id[15:0], //71:56
ar_isslvram, ar_iscmd, arprot_s[2:0], arsize_s[2:0], //55:48
arburst_s[1:0], 1'b0,arlock_s[0:0], arcache_s[3:0], //47:40 //arlock made 1-bit
arlen8_s[7:0], //39:32
araddr_s[31:0] }; //31:0
wire ar_agen0_valid, ar_agen1_valid, ar_agen2_valid, ar_agen3_valid;
wire arfifo_notfull;
wire arfifo_push = arvalid_s && arready_s;
wire arfifo_pop;
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (72),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Arfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (arbuf_data[71:0] ),
.in_push (arfifo_push ),
.in_pop (arfifo_pop ),
.out_data (arfifo_out[71:0] ),
.is_full ( ),
.is_notfull (arfifo_notfull ),
.is_empty ( ),
.out_valid (arfifo_valid ),
.ex_fifo_dbgout ( )
);
assign arready_s = arfifo_notfull;
wire [1:0] arfifo_out_lock = arfifo_out[45:44];
wire [71:0] slv_new_ex_info = arfifo_out[71:0];
wire slv_ex_new_valid ;
wire slv_ex_must_wr0 ;
wire slv_ex_must_wr1 ;
wire slv_ex_use_toggle ;
wire slv_ex_choose1 ;
wire slv_ex_toggle ;
wire [71:0] slv_ex_info0 ;
wire [1:0] ar_calc_resp ;
generate if(C_NO_EXCL == 0) begin : S_R_EXCL_0
assign slv_ex_new_valid = arfifo_valid && (arfifo_out_lock[1:0] == 2'b01) &&
(C_NO_EXCL == 0);
assign slv_ex_must_wr0 = ~slv_ex_valid0_ff ||
(slv_ex_info0_ff[71:56] == slv_new_ex_info[71:56]);
assign slv_ex_must_wr1 = ~slv_ex_valid1_ff ||
(slv_ex_info1_ff[71:56] == slv_new_ex_info[71:56]);
assign slv_ex_use_toggle = ~slv_ex_must_wr0 && ~slv_ex_must_wr1;
assign slv_ex_choose1 = (slv_ex_use_toggle) ? slv_ex_toggle_ff :
slv_ex_must_wr1;
assign slv_ex_new_valid0 = slv_ex_new_valid && ~slv_ex_choose1;
assign slv_ex_new_valid1 = slv_ex_new_valid && slv_ex_choose1;
assign slv_ex_toggle = (slv_ex_use_toggle && slv_ex_new_valid) ?
~slv_ex_toggle_ff : slv_ex_toggle_ff;
assign slv_ex_info0 = (slv_ex_new_valid0) ? slv_new_ex_info[71:0] :
slv_ex_info0_ff[71:0];
assign slv_ex_info1 = (slv_ex_new_valid1) ? slv_new_ex_info[71:0] :
slv_ex_info1_ff[71:0];
assign ar_calc_resp = (arfifo_out_lock[1:0] == 2'b01) ? 2'b01 : 2'b00;
end
endgenerate
generate if(C_NO_EXCL == 1) begin : S_R_EXCL_1
assign slv_ex_info0 = 72'h0;
assign slv_ex_info1 = 72'h0;
assign slv_ex_toggle = 1'b0;
assign slv_ex_new_valid0 = 1'b0;
assign slv_ex_new_valid1 = 1'b0;
assign ar_calc_resp = 2'b00;
end
endgenerate
wire ar_agen0_pop, ar_agen1_pop, ar_agen2_pop, ar_agen3_pop;
wire ar_agen0_done, ar_agen1_done, ar_agen2_done, ar_agen3_done;
wire [3:0] artrk_fifo_num;
wire [C_S_AXI_ID_WIDTH-1:0] artrk_in_push_id = arfifo_out[71:56];
wire ar_agen0_eff_valid = ar_agen0_valid && ~(ar_agen0_done && ar_agen0_pop);
wire ar_agen1_eff_valid = ar_agen1_valid && ~(ar_agen1_done && ar_agen1_pop);
wire ar_agen2_eff_valid = ar_agen2_valid && ~(ar_agen2_done && ar_agen2_pop);
wire ar_agen3_eff_valid = ar_agen3_valid && ~(ar_agen3_done && ar_agen3_pop);
wire [3:0] ar_agen_eff_valid = { ar_agen3_eff_valid, ar_agen2_eff_valid,
ar_agen1_eff_valid, ar_agen0_eff_valid };
wire [3:0] ar_agen_push = ~ar_agen_eff_valid[3:0] & artrk_fifo_num[3:0];
wire [3:0] artrk_clear_pos = ~ar_agen_eff_valid[3:0];
assign arfifo_pop = arfifo_valid && (ar_agen_push[3:0] != 4'h0);
wire dis_dis_out_of_order;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_R_OOO_YES
assign dis_dis_out_of_order = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_R_OOO_NO
assign dis_dis_out_of_order = 1'b1;
end
endgenerate
axi_traffic_gen_v2_0_id_track #(
.ID_WIDTH(C_S_AXI_ID_WIDTH)
) Ar_track (
.Clk (Clk ),
.rst_l (rst_l ),
.in_push_id (artrk_in_push_id[C_S_AXI_ID_WIDTH-1:0]),
.in_push (arfifo_valid ),
.in_search_id ({ C_S_AXI_ID_WIDTH { 1'b0 } } ),
.in_clear_pos (artrk_clear_pos[3:0] ),
.in_only_entry0(dis_dis_out_of_order ),
.out_push_pos (artrk_fifo_num[3:0] ),
.out_search_hit( ),
.out_free ( )
);
wire [3:0] arbuf_wrsel = (arfifo_pop) ? ar_agen_push[3:0] : 4'h0;
wire [15:0] ar_agen0_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen0_be;
axi_traffic_gen_v2_0_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Ar_agen0 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({arfifo_out[55:54], arfifo_out[13:0]} ),
.in_addr_offset({1'b0,arfifo_out[7:0] } ),
.in_id ({ ar_calc_resp[1:0], arfifo_out[69:56] }),
.in_len (arfifo_out[39:32] ),
.in_size (arfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (arfifo_out[47:46] ),
.in_push (arbuf_wrsel[0] ),
.in_pop (ar_agen0_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (ar_agen0_addr[15:0] ),
.out_be (ar_agen0_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_id (ar_agen0_id[15:0] ),
.out_done (ar_agen0_done ),
.out_valid (ar_agen0_valid )
);
wire [15:0] ar_agen1_addr, ar_agen1_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen1_be;
wire [15:0] ar_agen2_addr, ar_agen2_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen2_be;
wire [15:0] ar_agen3_addr, ar_agen3_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen3_be;
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_R_OOO_F_NO
assign ar_agen1_done = 1'b0;
assign ar_agen2_done = 1'b0;
assign ar_agen3_done = 1'b0;
assign ar_agen1_valid = 1'b0;
assign ar_agen2_valid = 1'b0;
assign ar_agen3_valid = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_R_OOO_F_YES
axi_traffic_gen_v2_0_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Ar_agen1 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({arfifo_out[55:54], arfifo_out[13:0]} ),
.in_addr_offset({1'b0,arfifo_out[7:0] } ),
.in_id ({ ar_calc_resp[1:0], arfifo_out[69:56] }),
.in_len (arfifo_out[39:32] ),
.in_size (arfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (arfifo_out[47:46] ),
.in_push (arbuf_wrsel[1] ),
.in_pop (ar_agen1_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (ar_agen1_addr[15:0] ),
.out_be (ar_agen1_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_id (ar_agen1_id[15:0] ),
.out_done (ar_agen1_done ),
.out_valid (ar_agen1_valid )
);
axi_traffic_gen_v2_0_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Ar_agen2 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({arfifo_out[55:54], arfifo_out[13:0]} ),
.in_addr_offset({1'b0,arfifo_out[7:0] } ),
.in_id ({ ar_calc_resp[1:0], arfifo_out[69:56] }),
.in_len (arfifo_out[39:32] ),
.in_size (arfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (arfifo_out[47:46] ),
.in_push (arbuf_wrsel[2] ),
.in_pop (ar_agen2_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (ar_agen2_addr[15:0] ),
.out_be (ar_agen2_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_id (ar_agen2_id[15:0] ),
.out_done (ar_agen2_done ),
.out_valid (ar_agen2_valid )
);
axi_traffic_gen_v2_0_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Ar_agen3 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({arfifo_out[55:54], arfifo_out[13:0]} ),
.in_addr_offset({1'b0,arfifo_out[7:0] } ),
.in_id ({ ar_calc_resp[1:0], arfifo_out[69:56] }),
.in_len (arfifo_out[39:32] ),
.in_size (arfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (arfifo_out[47:46] ),
.in_push (arbuf_wrsel[3] ),
.in_pop (ar_agen3_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (ar_agen3_addr[15:0] ),
.out_be (ar_agen3_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_id (ar_agen3_id[15:0] ),
.out_done (ar_agen3_done ),
.out_valid (ar_agen3_valid )
);
end
endgenerate
wire [3:0] ar_agen_sel ;
wire [15:0] ar_agen_id ;
wire [C_S_AXI_DATA_WIDTH/8-1:0] ar_agen_be ;
wire ar_agen_done ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_R1_OOO_F_YES
assign ar_agen_sel = (ar_agen3_valid) ? 4'h8 :
(ar_agen2_valid) ? 4'h4 :
(ar_agen1_valid) ? 4'h2 :
(ar_agen0_valid) ? 4'h1 : 4'h0;
assign ar_agen_addr = ((ar_agen_sel[0]) ? ar_agen0_addr[15:0] : 16'h0) |
((ar_agen_sel[1]) ? ar_agen1_addr[15:0] : 16'h0) |
((ar_agen_sel[2]) ? ar_agen2_addr[15:0] : 16'h0) |
((ar_agen_sel[3]) ? ar_agen3_addr[15:0] : 16'h0);
assign ar_agen_id = ((ar_agen_sel[0]) ? ar_agen0_id[15:0] : 16'h0) |
((ar_agen_sel[1]) ? ar_agen1_id[15:0] : 16'h0) |
((ar_agen_sel[2]) ? ar_agen2_id[15:0] : 16'h0) |
((ar_agen_sel[3]) ? ar_agen3_id[15:0] : 16'h0);
assign ar_agen_be =
((ar_agen_sel[0]) ? ar_agen0_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) |
((ar_agen_sel[1]) ? ar_agen1_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) |
((ar_agen_sel[2]) ? ar_agen2_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) |
((ar_agen_sel[3]) ? ar_agen3_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) ;
assign ar_agen_done = ((ar_agen_sel[0]) ? ar_agen0_done : 1'b0) |
((ar_agen_sel[1]) ? ar_agen1_done : 1'b0) |
((ar_agen_sel[2]) ? ar_agen2_done : 1'b0) |
((ar_agen_sel[3]) ? ar_agen3_done : 1'b0);
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_R1_OOO_F_NO
assign ar_agen_sel = (ar_agen0_valid) ? 4'h1 : 4'h0;
assign ar_agen_addr = ((ar_agen_sel[0]) ? ar_agen0_addr[15:0] : 16'h0) ;
assign ar_agen_id = ((ar_agen_sel[0]) ? ar_agen0_id[15:0] : 16'h0) ;
assign ar_agen_be =
((ar_agen_sel[0]) ? ar_agen0_be[C_S_AXI_DATA_WIDTH/8-1:0] : {(C_S_AXI_DATA_WIDTH/8-1){1'b0}}) ;
assign ar_agen_done = ((ar_agen_sel[0]) ? ar_agen0_done : 1'b0) ;
end
endgenerate
assign rd_reg_decode = 16'h1 << ar_agen_addr[5:2];
wire rd_reg_err = (ar_agen_addr[15:14] == 2'b00) && rd_reg_decode[13] &&
ar_agen_addr[7];
wire [1:0] rd_reg_rresp = (reg1_disallow_excl) ? 2'b00 :
(rd_reg_err) ? 2'b10 : ar_agen_id[15:14];
wire [56+C_S_AXI_DATA_WIDTH/8-1:0] rd_reg_data = { ar_agen_be[C_S_AXI_DATA_WIDTH/8-1:0], //63:56
ar_agen_id[15:0], //55:40
ar_agen_addr[15:14], ar_agen_addr[3:2], //39:36
1'b0, ar_agen_done, rd_reg_rresp[1:0], //35:32
rd_reg_data_raw[31:0] }; //31:0
wire rdataout_full;
wire [C_S_AXI_DATA_WIDTH+24-1:0] rdata_pre;
reg rd_reg_valid_ff;
assign ar_agen0_pop = ar_agen_sel[0] && ~rdataout_full ;
assign ar_agen1_pop = ar_agen_sel[1] && ~rdataout_full ;
assign ar_agen2_pop = ar_agen_sel[2] && ~rdataout_full ;
assign ar_agen3_pop = ar_agen_sel[3] && ~rdataout_full ;
wire rd_reg_valid = ar_agen0_pop || ar_agen1_pop || ar_agen2_pop || ar_agen3_pop;
wire rddec6_valid = rd_reg_valid && rd_reg_decode[6] &&
(rd_reg_data[39:38] == 2'b00);
reg [56+C_S_AXI_DATA_WIDTH/8-1:0] rd_reg_data_ff;
always @(posedge Clk) begin
rd_reg_data_ff <= (rst_l) ? rd_reg_data : 'h0;
rd_reg_valid_ff <= (rst_l) ? rd_reg_valid : 1'b0;
rddec6_valid_ff <= (rst_l) ? rddec6_valid : 1'b0;
slv_ex_info0_ff[71:0] <= (rst_l) ? slv_ex_info0[71:0] : 72'h0;
slv_ex_info1_ff[71:0] <= (rst_l) ? slv_ex_info1[71:0] : 72'h0;
slv_ex_toggle_ff <= (rst_l) ? slv_ex_toggle : 1'b0;
end
wire [31:0] cmdram_rd_out =
((rd_reg_data_ff[37:36] == 2'b00) ? cmd_out_mr_i[31:0] : 32'h0) |
((rd_reg_data_ff[37:36] == 2'b01) ? cmd_out_mr_i[63:32] : 32'h0) |
((rd_reg_data_ff[37:36] == 2'b10) ? cmd_out_mr_i[95:64] : 32'h0) |
((rd_reg_data_ff[37:36] == 2'b11) ? cmd_out_mr_i[127:96] : 32'h0);
wire [C_S_AXI_DATA_WIDTH-1:0] rd_data_muxed ;
assign rd_data_muxed =
(rd_reg_data_ff[39]) ? slvram_rd_out[C_S_AXI_DATA_WIDTH-1:0] :
(rd_reg_data_ff[38]) ? { 2 { cmdram_rd_out[31:0] } } :
{ 2 { rd_reg_data_ff[31:0] } };
wire [C_S_AXI_DATA_WIDTH/8-1:0] rd_data_be = rd_reg_data_ff[56+C_S_AXI_DATA_WIDTH/8-1:
56];
wire [C_S_AXI_DATA_WIDTH-1:0] rd_data_mask ;
generate if(C_S_AXI_DATA_WIDTH == 32) begin : S_R_BE_32
assign rd_data_mask = {
{ 8 { rd_data_be[3] } }, { 8 { rd_data_be[2] } },
{ 8 { rd_data_be[1] } }, { 8 { rd_data_be[0] } }
};
end
endgenerate
generate if(C_S_AXI_DATA_WIDTH == 64) begin : S_R_BE_64
assign rd_data_mask = {
{ 8 { rd_data_be[7] } }, { 8 { rd_data_be[6] } },
{ 8 { rd_data_be[5] } }, { 8 { rd_data_be[4] } },
{ 8 { rd_data_be[3] } }, { 8 { rd_data_be[2] } },
{ 8 { rd_data_be[1] } }, { 8 { rd_data_be[0] } }
};
end
endgenerate
wire [C_S_AXI_DATA_WIDTH-1:0] rd_data_masked =
rd_data_muxed[C_S_AXI_DATA_WIDTH-1:0] ;
//
//Timing improvement
//
reg [C_S_AXI_DATA_WIDTH+24-1:0] Rdataout_in_data_ff;
reg Rdataout_in_push_ff;
always @ (posedge Clk) begin
Rdataout_in_data_ff <= (rst_l) ? ({ rd_reg_data_ff[55:32], rd_data_masked[C_S_AXI_DATA_WIDTH-1:0] }) : {(C_S_AXI_DATA_WIDTH+24){1'b0}};
Rdataout_in_push_ff <= (rst_l) ? rd_reg_valid_ff : 1'b0;
end
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (C_S_AXI_DATA_WIDTH+24 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.ZERO_INVALID(C_ZERO_INVALID ),
.HEADREG (1 ),
.FULL_LEVEL (6 )
) Rdataout (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (Rdataout_in_data_ff ),
.in_push (Rdataout_in_push_ff ),
.in_pop ((rvalid_s && rready_s )),
.out_data (rdata_pre[C_S_AXI_DATA_WIDTH+24-1:0] ),
.is_full (rdataout_full ),
.is_notfull ( ),
.is_empty ( ),
.out_valid (rvalid_s ),
.ex_fifo_dbgout ( )
);
assign rdata_s[C_S_AXI_DATA_WIDTH-1:0] = rdata_pre[C_S_AXI_DATA_WIDTH-1:0];
assign rresp_s[1:0] = rdata_pre[C_S_AXI_DATA_WIDTH+2-1:C_S_AXI_DATA_WIDTH];
assign rlast_s = rdata_pre[C_S_AXI_DATA_WIDTH+2];
assign rid_s[C_S_AXI_ID_WIDTH-1:0] =
rdata_pre[C_S_AXI_DATA_WIDTH+23:C_S_AXI_DATA_WIDTH+8];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2010-2012 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may be reproduced or transmitted in any form or by any
// means, electronic or mechanical, including photocopying, recording, or any
// information storage and retrieval system in violation of the license under
// which the source code is released.
//
// The souce code contained herein is free; it may be redistributed and/or
// modified in accordance with the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either version 2.1 of
// the GNU Lesser General Public License, or any later version.
//
// The souce code contained herein is freely released WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
// more details.)
//
// A copy of the GNU Lesser General Public License should have been received
// along with the source code contained herein; if not, a copy can be obtained
// by writing to:
//
// Free Software Foundation, Inc.
// 51 Franklin Street, Fifth Floor
// Boston, MA 02110-1301 USA
//
// Further, no use of this source code is permitted in any form or means
// without inclusion of this banner prominently in any derived works.
//
// Michael A. Morris
// Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
// Company: M. A. Morris & Associates
// Engineer: Michael A. Morris
//
// Create Date: 21:00:57 02/17/2011
// Design Name: Booth_Multiplier_4x
// Module Name: C:/XProjects/ISE10.1i/F9408/tb_Booth_Multiplier_4x.v
// Project Name: Booth_Multiplier
// Target Devices: Spartan-3AN
// Tool versions: Xilinx ISE 10.1 SP3
//
// Description:
//
// Verilog Test Fixture created by ISE for module: Booth_Multiplier_4x
//
// Dependencies:
//
// Revision:
//
// 0.01 11B17 MAM File Created
//
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////
module tb_Booth_Multiplier_4x;
parameter N = 8;
// UUT Signals
reg Rst;
reg Clk;
reg Ld;
reg [(N - 1):0] M;
reg [(N - 1):0] R;
wire Valid;
wire [((2*N) - 1):0] P;
// Simulation Variables
reg [(2*N):0] i;
// Instantiate the Unit Under Test (UUT)
Booth_Multiplier_4x #(
.N(N)
) uut (
.Rst(Rst),
.Clk(Clk),
.Ld(Ld),
.M(M),
.R(R),
.Valid(Valid),
.P(P)
);
initial begin
// Initialize Inputs
Rst = 1;
Clk = 1;
Ld = 0;
M = 0;
R = 0;
i = 0;
// Wait 100 ns for global reset to finish
#101 Rst = 0;
// Add stimulus here
@(posedge Clk) #1;
for(i = (2**N); i < (2**(2*N)) + 1; i = i + 1) begin
Ld = 1; M = i[((2*N) - 1):N]; R = i[(N - 1):0];
@(posedge Clk) #1 Ld = 0;
@(posedge Valid);
end
// @(posedge Clk) #1 M = 4'h8; R = 4'h2; Ld = 1;
// @(posedge Clk) #1 Ld = 0;
//
// @(posedge Valid); M = 4'h2; R = 4'h8; Ld = 1;
// @(posedge Clk) #1 Ld = 0;
//
// @(posedge Valid); M = 4'h8; R = 4'h6; Ld = 1;
// @(posedge Clk) #1 Ld = 0;
//
// @(posedge Valid); M = 4'h6; R = 4'h8; Ld = 1;
// @(posedge Clk) #1 Ld = 0;
//
// @(posedge Valid); M = 4'h0; R = 4'h0; Ld = 1;
// @(posedge Clk) #1 Ld = 0;
end
///////////////////////////////////////////////////////////////////////////////
always #5 Clk = ~Clk;
///////////////////////////////////////////////////////////////////////////////
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler, Nick Desaulniers
//
// Create Date: 10:58:44 04/07/2011
// Design Name: data_path
// Module Name: data_path
// Project Name: Data Path for the Pipelined CPU
// Target Devices: Xilinx Spartan-3E
// Tool versions: Xilinx ISE Project Navigator
// Description: This is a pipelined data_path with five stages: IF, ID, EX, M, WB
//
// Dependencies: n/a
//
// Revision:
// Revision 0.01 - File Created
// Revision 1.00 - Removed v, c from execute block
// Revision 2.00 - Added clk_n, rst_n to memory module
// Revision 3.00 - Fixed some inputs (clk_n, rst_n) to modules (CRC)
// Revision 4.00 - Temporarily wired stages together, no pipeline; addec cu_branch (CRC)
// Revision 5.00 - Added FFs between stages, untested (CRC)
// Revision 6.00 - Modified cu_branch width, cu_alu_opcode width
// Revision 7.00 - Changed width of cu_branch input, removed m_branch_en_ff (CRC)
// Revision 8.00 - Added assign for id_opcode_out, fixes to pipeline (CRC)
//
//////////////////////////////////////////////////////////////////////////////////
module data_path(
input wire clk,
input wire clk_n,
input wire rst_n,
input wire cu_reg_load,
input wire cu_alu_sel_b,
input wire [10:0] cu_alu_opcode,
input wire cu_dm_wea,
input wire cu_reg_data_loc,
input wire[1:0] cu_branch,
output wire [3:0] id_opcode_out,
output wire [7:0] leds
);
wire [6:0] if_next_addr;
wire [15:0] if_curr_inst;
reg [6:0] if_next_addr_ff;
reg [15:0] if_curr_inst_ff;
wire [3:0] id_opcode;
wire [6:0] id_next_addr;
wire [15:0] id_register1_data;
wire [15:0] id_register2_data;
wire [6:0] id_sign_ext_addr;
wire [2:0] id_dest_reg_addr;
reg [3:0] id_opcode_ff;
reg [6:0] id_next_addr_ff;
reg [15:0] id_register1_data_ff;
reg [15:0] id_register2_data_ff;
reg [6:0] id_sign_ext_addr_ff;
reg [2:0] id_dest_reg_addr_ff;
wire [6:0] ex_sign_ext_next_addr;
wire ex_alu_z;
wire [15:0] ex_alu_result;
wire [15:0] ex_register2_data;
wire [2:0] ex_reg_waddr;
reg [6:0] ex_sign_ext_next_addr_ff;
reg ex_alu_z_ff;
reg [15:0] ex_alu_result_ff;
reg [15:0] ex_register2_data_ff;
reg [2:0] ex_reg_waddr_ff;
wire [15:0] m_alu_result;
wire [15:0] m_dm_dout;
wire [2:0] m_reg_waddr;
wire m_branch_en;
reg [15:0] m_alu_result_ff;
reg [15:0] m_dm_dout_ff;
reg [2:0] m_reg_waddr_ff;
wire [15:0] wb_reg_wdata;
wire [2:0] wb_reg_waddr;
// Control signals through ffs
reg cu_reg_load_ff1;
reg cu_reg_data_loc_ff1;
reg [1:0] cu_branch_ff1;
reg cu_dm_wea_ff1;
reg [10:0] cu_alu_opcode_ff1;
reg cu_alu_sel_b_ff1;
reg cu_reg_load_ff2;
reg cu_reg_data_loc_ff2;
reg [1:0] cu_branch_ff2;
reg cu_dm_wea_ff2;
reg cu_reg_load_ff3;
reg cu_reg_data_loc_ff3;
assign id_opcode_out = id_opcode_ff;
assign leds = 8'hAA;
instruction_fetch i_instruction_fetch(
.clk_n(clk_n),
.rst_n(rst_n),
.m_branch_addr(ex_sign_ext_next_addr_ff),
.m_branch_en(m_branch_en),
.if_next_addr(if_next_addr),
.if_curr_inst(if_curr_inst)
);
instruction_decode i_instruction_decode(
.clk_n(clk_n),
.if_next_addr(if_next_addr_ff),
.if_curr_inst(if_curr_inst_ff),
.wb_reg_wea(wb_reg_wea),
.wb_reg_wdata(wb_reg_wdata),
.wb_reg_waddr(wb_reg_waddr),
.id_opcode(id_opcode),
.id_next_addr(id_next_addr),
.id_register1_data(id_register1_data),
.id_register2_data(id_register2_data),
.id_sign_ext_addr(id_sign_ext_addr),
.id_dest_reg_addr(id_dest_reg_addr)
);
execute i_execute(
.clk_n(clk_n),
.rst_n(rst_n),
.id_next_addr(id_next_addr_ff),
.id_register1_data(id_register1_data_ff),
.id_register2_data(id_register2_data_ff),
.id_sign_ext_addr(id_sign_ext_addr_ff),
.id_dest_reg_addr(id_dest_reg_addr_ff),
.cu_alu_opcode(cu_alu_opcode_ff1),
.cu_alu_sel_b(cu_alu_sel_b_ff1),
.ex_sign_ext_next_addr(ex_sign_ext_next_addr),
.ex_alu_z(ex_alu_z),
.ex_alu_result(ex_alu_result),
.ex_register2_data(ex_register2_data),
.ex_reg_waddr(ex_reg_waddr)
);
memory i_memory(
.clk_n(clk_n),
.rst_n(rst_n),
.ex_alu_result(ex_alu_result_ff),
.ex_register2_data(ex_register2_data_ff),
.ex_reg_waddr(ex_reg_waddr_ff),
.cu_dm_wea(cu_dm_wea_ff2),
.cu_branch(cu_branch_ff2),
.ex_alu_z(ex_alu_z_ff),
.m_alu_result(m_alu_result),
.m_dm_dout(m_dm_dout),
.m_reg_waddr(m_reg_waddr),
.m_branch_en(m_branch_en)
);
write_back i_write_back(
.m_alu_result(m_alu_result_ff),
.m_dm_dout(m_dm_dout_ff),
.m_reg_waddr(m_reg_waddr_ff),
.cu_reg_data_loc(cu_reg_data_loc_ff3),
.cu_reg_load(cu_reg_load_ff3),
.wb_reg_wdata(wb_reg_wdata),
.wb_reg_wea(wb_reg_wea),
.wb_reg_waddr(wb_reg_waddr)
);
// IF -> ID
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
if_next_addr_ff <= 7'b0;
if_curr_inst_ff <= 16'b0;
end else begin
if_next_addr_ff <= if_next_addr;
if_curr_inst_ff <= if_curr_inst;
end
end
// ID -> EX
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
id_opcode_ff <= 4'b0;
id_next_addr_ff <= 7'b0;
id_register1_data_ff <= 16'b0;
id_register2_data_ff <= 16'b0;
id_sign_ext_addr_ff <= 7'b0;
id_dest_reg_addr_ff <= 3'b0;
cu_reg_load_ff1 <= 1'b0;
cu_reg_data_loc_ff1 <= 1'b0;
cu_branch_ff1 <= 2'b0;
cu_dm_wea_ff1 <= 1'b0;
cu_alu_opcode_ff1 <= 11'b0;
cu_alu_sel_b_ff1 <= 1'b0;
end else begin
id_opcode_ff <= id_opcode;
id_next_addr_ff <= id_next_addr;
id_register1_data_ff <= id_register1_data;
id_register2_data_ff <= id_register2_data;
id_sign_ext_addr_ff <= id_sign_ext_addr;
id_dest_reg_addr_ff <= id_dest_reg_addr;
cu_reg_load_ff1 <= cu_reg_load;
cu_reg_data_loc_ff1 <= cu_reg_data_loc;
cu_branch_ff1 <= cu_branch;
cu_dm_wea_ff1 <= cu_dm_wea;
cu_alu_opcode_ff1 <= cu_alu_opcode;
cu_alu_sel_b_ff1 <= cu_alu_sel_b;
end
end
// EX -> M
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ex_sign_ext_next_addr_ff <= 7'b0;
ex_alu_z_ff <= 1'b0;
ex_alu_result_ff <= 16'b0;
ex_register2_data_ff <= 16'b0;
ex_reg_waddr_ff <= 3'b0;
cu_reg_load_ff2 <= 1'b0;
cu_reg_data_loc_ff2 <= 1'b0;
cu_branch_ff2 <= 2'b0;
cu_dm_wea_ff2 <= 1'b0;
end else begin
ex_sign_ext_next_addr_ff <= ex_sign_ext_next_addr;
ex_alu_z_ff <= ex_alu_z;
ex_alu_result_ff <= ex_alu_result;
ex_register2_data_ff <= ex_register2_data;
ex_reg_waddr_ff <= ex_reg_waddr;
cu_reg_load_ff2 <= cu_reg_load_ff1;
cu_reg_data_loc_ff2 <= cu_reg_data_loc_ff1;
cu_branch_ff2 <= cu_branch_ff1;
cu_dm_wea_ff2 <= cu_dm_wea_ff1;
end
end
// M -> WB
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
m_alu_result_ff <= 16'b0;
m_dm_dout_ff <= 16'b0;
m_reg_waddr_ff <= 16'b0;
cu_reg_load_ff3 <= 1'b0;
cu_reg_data_loc_ff3 <= 1'b0;
end else begin
m_alu_result_ff <= m_alu_result;
m_dm_dout_ff <= m_dm_dout;
m_reg_waddr_ff <= m_reg_waddr;
cu_reg_load_ff3 <= cu_reg_load_ff2;
cu_reg_data_loc_ff3 <= cu_reg_data_loc_ff2;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXBP_1_V
`define SKY130_FD_SC_HD__EDFXBP_1_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for edfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__edfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__edfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__edfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__edfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXBP_1_V
|
module single_step_motor #(
parameter integer C_OPT_BR_TIME = 0,
parameter integer C_STEP_NUMBER_WIDTH = 16,
parameter integer C_SPEED_DATA_WIDTH = 16,
parameter integer C_SPEED_ADDRESS_WIDTH = 9,
parameter integer C_MICROSTEP_WIDTH = 3,
parameter integer C_ZPD = 0,
parameter integer C_MICROSTEP_PASSTHOUGH = 0,
parameter integer C_REVERSE_DELAY = 4 /// >= 2
)(
input wire clk,
input wire resetn,
input wire clk_en,
input wire [C_SPEED_ADDRESS_WIDTH-1:0] acce_addr_max,
input wire [C_SPEED_ADDRESS_WIDTH-1:0] deac_addr_max,
output wire acce_en,
output wire [C_SPEED_ADDRESS_WIDTH-1:0] acce_addr,
input wire [C_SPEED_DATA_WIDTH-1:0] acce_data,
output wire deac_en,
output wire [C_SPEED_ADDRESS_WIDTH-1:0] deac_addr,
input wire [C_SPEED_DATA_WIDTH-1:0] deac_data,
/// valid when C_ZPD == 1
input wire zpd, /// zero position detection
output reg o_drive,
output reg o_dir,
output wire [C_MICROSTEP_WIDTH-1:0] o_ms,
output wire o_xen,
output wire o_xrst,
input wire i_xen ,
input wire i_xrst ,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] i_min_pos,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] i_max_pos,
input wire [C_MICROSTEP_WIDTH-1:0] i_ms ,
/// valid when C_ZPD == 1
output wire pri_zpsign , /// zero position sign
output wire pri_ntsign , /// negative terminal sign
output wire pri_ptsign , /// positive terminal sign
output wire pri_state ,
output wire [C_SPEED_DATA_WIDTH-1:0] pri_rt_speed,
output wire signed [C_STEP_NUMBER_WIDTH-1:0] pri_position,
input wire pri_start, /// pulse sync to clk
input wire pri_stop , /// pulse sync to clk
input wire [C_SPEED_DATA_WIDTH-1:0] pri_speed,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] pri_step ,
input wire pri_abs ,
input wire ext_sel ,
output wire ext_zpsign , /// zero position sign
output wire ext_ntsign , /// negative terminal sign
output wire ext_ptsign , /// positive terminal sign
output wire ext_state ,
output wire [C_SPEED_DATA_WIDTH-1:0] ext_rt_speed,
output wire signed [C_STEP_NUMBER_WIDTH-1:0] ext_position, /// signed integer
input wire ext_start, /// pulse sync to clk
input wire ext_stop , /// pulse sync to clk
input wire [C_SPEED_DATA_WIDTH-1:0] ext_speed,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] ext_step , /// signed intger (sign -> direction)
input wire ext_abs,
input wire ext_mod_remain,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] ext_new_remain,
output reg [31:0] test0,
output reg [31:0] test1,
output reg [31:0] test2,
output reg [31:0] test3
);
/// state macro
localparam integer IDLE = 2'b00;
localparam integer PREPARE = 2'b10;
localparam integer RUNNING = 2'b11;
/// motor logic
reg [C_SPEED_DATA_WIDTH-1:0] speed_max;
reg [C_SPEED_DATA_WIDTH-1:0] speed_cur;
reg [C_SPEED_DATA_WIDTH-1:0] speed_cnt;
reg [C_STEP_NUMBER_WIDTH-1:0] step_cnt;
reg signed [C_STEP_NUMBER_WIDTH-1:0] step_remain;
reg step_done; /// keep one between final half step
reg[1:0] motor_state;
assign pri_state = motor_state[1];
wire is_idle; assign is_idle = (pri_state == 0);
wire is_running; assign is_running = (pri_state);
reg rd_en;
/// posedge of out drive
reg o_drive_d1;
always @ (posedge clk) begin
o_drive_d1 <= o_drive;
end
wire posedge_drive;
assign posedge_drive = o_drive_d1 && ~o_drive;
/// backwarding
wire backwarding;
assign backwarding = o_dir;
/// for zpd
reg signed [C_STEP_NUMBER_WIDTH-1:0] cur_position;
wire reach_neg_term;
wire reach_pos_term;
wire reach_zero_position;
wire shouldStop;
/// control selection
reg [C_SPEED_DATA_WIDTH-1:0] req_speed;
reg signed [C_STEP_NUMBER_WIDTH-1:0] req_step ;
reg req_dir ;
reg req_abs ;
/// @note only for C_ZPD
reg req_reset2zero;
/// start_pulse
reg start_pulse;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
start_pulse <= 0;
req_reset2zero <= 0;
end
else if (start_pulse) begin
if (clk_en)
start_pulse <= 0;
end
else begin
if (is_idle) begin
if (ext_sel == 1'b0) begin
if (pri_start) begin
start_pulse <= 1'b1;
req_speed <= pri_speed;
req_step <= pri_step;
req_abs <= pri_abs;
if ((pri_abs == 1'b1) && (pri_step == 0) && C_ZPD) begin
req_dir <= 1'b1; /// backward
req_reset2zero <= 1'b1;
end
else begin
req_dir <= pri_abs
? (pri_step > cur_position ? 0 : 1)
: pri_step[C_STEP_NUMBER_WIDTH-1];
req_reset2zero <= 1'b0;
end
end
end
else begin
if (ext_start) begin
start_pulse <= 1'b1;
req_speed <= ext_speed;
req_step <= ext_step;
req_abs <= ext_abs;
if ((ext_abs == 1'b1) && (ext_step == 0) && C_ZPD) begin
req_dir <= 1'b1; /// backward
req_reset2zero <= 1'b1;
end
else begin
req_dir <= ext_abs
? (ext_step > cur_position ? 0 : 1)
: ext_step[C_STEP_NUMBER_WIDTH-1];
req_reset2zero <= 1'b0;
end
end
end
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
test0 <= 32'b1;
test1 <= 32'b1;
test2 <= 32'b1;
test3 <= 32'b1;
end
else begin
if (clk_en) begin
case (motor_state)
RUNNING: begin
if (shouldStop) begin
test3 <= cur_position;
test2 <= reach_neg_term;
test1 <= reach_pos_term;
test0 <= backwarding;
end
end
endcase
end
end
end
/// stop
reg last_ext_sel;
always @ (posedge clk) begin
if (resetn == 1'b0)
last_ext_sel <= 0;
else
last_ext_sel <= ext_sel;
end
reg stop_pulse;
always @ (posedge clk) begin
if (resetn == 1'b0)
stop_pulse <= 0;
else if (stop_pulse) begin
if (clk_en)
stop_pulse <= 0;
end
else begin
if (is_running) begin
/**
* auto stop when swith control interface
*/
if (last_ext_sel != ext_sel) begin
stop_pulse <= 1'b1;
end
else if (ext_sel == 1'b0) begin
if (pri_stop)
stop_pulse <= 1'b1;
end
else begin
if (ext_stop)
stop_pulse <= 1'b1;
end
end
end
end
/// rd_en
always @ (posedge clk) begin
if (resetn == 1'b0)
rd_en <= 0;
else if (rd_en)
rd_en <= 0;
else if (clk_en) begin
case (motor_state)
IDLE: rd_en <= start_pulse;
PREPARE: rd_en <= 0;
RUNNING: rd_en <= ((speed_cnt == 0) && o_drive);
endcase
end
end
reg [31:0] reverse_delay_cnt;
always @ (posedge clk) begin
if (resetn == 1'b0)
reverse_delay_cnt <= 0;
else if (clk_en) begin
case (motor_state)
IDLE: reverse_delay_cnt <= 0;
PREPARE: reverse_delay_cnt <= reverse_delay_cnt + 1;
endcase
end
end
/// should start
wire should_start;
assign should_start = (clk_en && start_pulse && is_idle);
generate
if (C_MICROSTEP_PASSTHOUGH) begin
assign o_ms = i_ms;
end
else begin
reg [C_MICROSTEP_WIDTH-1:0] r_ms;
assign o_ms = r_ms;
always @ (posedge clk) begin
if (should_start) begin
r_ms <= i_ms;
end
end
end
endgenerate
/// store instruction
always @ (posedge clk) begin
if (should_start) begin
speed_max <= req_speed;
o_dir <= req_dir;
end
end
/// motor_state
always @ (posedge clk) begin
if (resetn == 1'b0)
motor_state <= IDLE;
else if (clk_en) begin
case (motor_state)
IDLE: begin
if (start_pulse) begin
if (o_dir == req_dir)
motor_state <= RUNNING;
else
motor_state <= PREPARE;
end
end
PREPARE: begin
if (stop_pulse)
motor_state <= IDLE;
else if (reverse_delay_cnt == C_REVERSE_DELAY - 2)
motor_state <= RUNNING;
end
RUNNING: begin
if (stop_pulse)
motor_state <= IDLE;
else if (shouldStop)
motor_state <= IDLE;
end
endcase
end
end
assign o_xen = i_xen;
assign o_xrst = i_xrst;
/// step_done
always @ (posedge clk) begin
if (resetn == 1'b0)
step_done <= 0;
else if (clk_en) begin
case (motor_state)
IDLE, PREPARE: begin
step_done <= 0;
end
RUNNING: begin
if (o_drive == 1 && speed_cnt == 0) begin
/// @note not simplify it, the cur_position is not stable
if (req_abs) begin
if (req_step == 0) begin
if (reach_zero_position)
step_done <= 1;
end
else begin
if (cur_position == req_step)
step_done <= 1;
end
end
else begin
if (step_remain == 0)
step_done <= 1;
end
end
end
endcase
end
end
/// step counter (i.e. block ram address)
always @ (posedge clk) begin
if (resetn == 1'b0)
step_cnt <= 0;
else if (clk_en) begin
case (motor_state)
IDLE: begin
if (start_pulse)
step_cnt <= 0;
end
RUNNING: begin
if (speed_cnt == 0 && o_drive == 1)
step_cnt <= step_cnt + 1;
end
endcase
end
end
wire [C_STEP_NUMBER_WIDTH-1:0] abs_remain;
abs #(
.C_WIDTH(C_STEP_NUMBER_WIDTH)
) abs_inst (
.din(step_remain),
.dout(abs_remain)
);
always @ (posedge clk) begin
if (resetn == 1'b0)
step_remain <= 0;
else if (ext_mod_remain)
step_remain <= ext_new_remain;
else if (clk_en) begin
case (motor_state)
IDLE: begin
if (start_pulse) begin
if (req_dir)
step_remain <= req_step + 1;
else
step_remain <= req_step - 1;
end
end
RUNNING: begin
if (speed_cnt == 0 && o_drive == 1) begin
if (req_dir)
step_remain <= step_remain + 1;
else
step_remain <= step_remain - 1;
end
end
endcase
end
end
////////////////////////////// read block ram logic ////////////////////////////
reg rd_en_d1;
reg rd_en_d2;
reg rd_en_d3;
reg rd_en_d4;
reg rd_en_d5;
reg [C_SPEED_DATA_WIDTH-1:0] speed_var;
always @ (posedge clk) begin
rd_en_d1 <= rd_en;
rd_en_d2 <= rd_en_d1;
rd_en_d3 <= rd_en_d2;
rd_en_d4 <= rd_en_d3;
rd_en_d5 <= rd_en_d4;
end
reg acce_ing;
reg deac_ing;
always @ (posedge clk) begin
if (rd_en) begin
acce_ing <= (step_cnt < acce_addr_max);
deac_ing <= (abs_remain < deac_addr_max);
end
end
/// rd_en_d2: read address for block ram
reg [C_SPEED_ADDRESS_WIDTH-1:0] r_acce_addr;
reg [C_SPEED_ADDRESS_WIDTH-1:0] r_deac_addr;
assign acce_en = rd_en_d2;
assign acce_addr = r_acce_addr;
assign deac_en = rd_en_d2;
assign deac_addr = r_deac_addr;
always @ (posedge clk) begin
if (rd_en_d1) begin
r_acce_addr <= (acce_ing ? step_cnt : acce_addr_max);
r_deac_addr <= (deac_ing ? abs_remain : deac_addr_max);
end
end
/// minimum of acce_data_final / deac_data_final / speed_max
generate
if (C_OPT_BR_TIME == 0) begin
always @ (posedge clk) begin
if (rd_en_d4) begin
if (acce_data > deac_data)
speed_var <= acce_data;
else
speed_var <= deac_data;
end
end
assign pri_rt_speed = speed_cur;
always @ (posedge clk) begin
if (rd_en_d5) begin
if (speed_var > speed_max)
speed_cur <= speed_var;
else
speed_cur <= speed_max;
end
end
end
else begin
reg [C_SPEED_DATA_WIDTH-1:0] acce_data_d1;
reg [C_SPEED_DATA_WIDTH-1:0] deac_data_d1;
reg acceBdeac;
always @ (posedge clk) begin
if (rd_en_d4) begin
acceBdeac <= (acce_data > deac_data);
acce_data_d1 <= acce_data;
deac_data_d1 <= deac_data;
end
end
always @ (posedge clk) begin
if (rd_en_d5) begin
speed_var <= (acceBdeac ? acce_data_d1 : deac_data_d1);
end
end
reg rd_en_d6;
always @ (posedge clk) rd_en_d6 <= rd_en_d5;
reg varBmax;
reg [C_SPEED_DATA_WIDTH-1:0] speed_var_d1;
always @ (posedge clk) begin
if (rd_en_d6) begin
speed_var_d1 <= speed_var;
varBmax <= (speed_var > speed_max);
end
end
reg rd_en_d7;
always @ (posedge clk) rd_en_d7 <= rd_en_d6;
assign pri_rt_speed = speed_cur;
always @ (posedge clk) begin
if (rd_en_d7) begin
speed_cur <= (varBmax ? speed_var_d1 : speed_max);
end
end
end
endgenerate
//////////////////////////////////// read block ram end ////////////////////////
/// speed counter result in output driver
always @ (posedge clk) begin
if (resetn == 1'b0)
speed_cnt <= 0;
else if (clk_en) begin
case (motor_state)
IDLE: begin
speed_cnt <= 0;
end
RUNNING: begin
if (speed_cnt == 0)
speed_cnt <= speed_cur;
else
speed_cnt <= speed_cnt - 1;
end
endcase
end
end
always @ (posedge clk) begin
if (resetn == 1'b0)
o_drive <= 0;
else if (clk_en) begin
case (motor_state)
IDLE, PREPARE: o_drive <= 0;
RUNNING: begin
if (speed_cnt == 0 && ~step_done)
o_drive <= ~o_drive;
end
endcase
end
end
/// zero position process
generate
if (C_ZPD) begin
//reg internal_zpd;
//reg internal_ptd;
//reg internal_ntd;
//always @ (posedge clk) begin
// if (resetn == 1'b0) begin
// internal_zpd <= 0;
// internal_ptd <= 0;
// internal_ntd <= 0;
// end
// else begin
// internal_zpd <= zpd;
// internal_ptd <= (cur_position >= i_max_pos);
// internal_ntd <= (cur_position <= i_min_pos);
// end
//end
/// for shouldStop
assign shouldStop = (req_reset2zero
? reach_zero_position
: (((step_done && (speed_cnt == 0))
|| (backwarding ? reach_neg_term : reach_pos_term))));
/// current position
always @ (posedge clk) begin
if (resetn == 1'b0)
cur_position <= 0;
else if (reach_zero_position)
cur_position <= 0;
else if (posedge_drive) begin
if (backwarding) begin
if (cur_position > i_min_pos)
cur_position <= cur_position - 1;
end
else begin
if (cur_position < i_max_pos)
cur_position <= cur_position + 1;
end
end
end
assign reach_neg_term = cur_position <= i_min_pos;
assign reach_pos_term = cur_position >= i_max_pos;
assign reach_zero_position = (zpd == 1'b1);
assign pri_zpsign = reach_zero_position;
assign pri_ptsign = reach_pos_term;
assign pri_ntsign = reach_neg_term;
assign pri_position = cur_position;
end
else begin
assign reach_neg_term = cur_position <= i_min_pos;
assign reach_pos_term = cur_position >= i_max_pos;
assign reach_zero_position = (cur_position == 0);
/// current position
always @ (posedge clk) begin
if (resetn == 1'b0)
cur_position <= 0;
else if (posedge_drive) begin
if (backwarding) begin
if (cur_position > i_min_pos)
cur_position <= cur_position - 1;
end
else begin
if (cur_position < i_max_pos)
cur_position <= cur_position + 1;
end
end
end
assign pri_zpsign = 0;
assign pri_ptsign = 0;
assign pri_ntsign = 0;
assign pri_position = 0;
assign shouldStop = (step_done && (speed_cnt == 0));
end
endgenerate
assign ext_zpsign = pri_zpsign ;
assign ext_ntsign = pri_ntsign ;
assign ext_ptsign = pri_ptsign ;
assign ext_state = pri_state ;
assign ext_rt_speed = pri_rt_speed;
assign ext_position = pri_position;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O41AI_BLACKBOX_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ddr_ch_b.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ddr_ch_b(afo ,serial_in ,afi ,serial_out ,pad_clk_si ,testmode_l
,test_mode ,bypass_enable_out ,ps_select_out ,rclk ,se ,pad_clk_so
,update_dr_in ,dram_io_data_out ,spare_ddr_pin ,spare_ddr_data ,
dram_io_ptr_clk_inv ,bso ,bsi ,bypass_enable_in ,mode_ctrl_out ,
update_dr_out ,shift_dr_out ,clock_dr_out ,hiz_n_out ,ps_select_in
,mode_ctrl_in ,shift_dr_in ,clock_dr_in ,hiz_n_in ,strobe , arst_l_out,
io_dram_data_in ,io_dram_ecc_in ,dram_io_addr ,dram_io_clk_enable ,
dram_io_cke ,dram_io_bank ,dram_io_ras_l ,dram_io_write_en_l ,
dram_io_cas_l ,dram_io_cs_l ,dram_dq ,dram_addr ,dram_cb ,dram_dqs
,dram_cke ,dram_ba ,dram_ck_n ,dram_ck_p ,io_dram_data_valid ,
dram_ras_l ,dram_we_l ,dram_cas_l ,dram_cs_l ,burst_length_four ,
dram_io_pad_clk_inv ,dram_io_pad_enable ,dram_io_drive_enable ,
rst_l ,lpf_code ,dram_io_channel_disabled ,dram_io_drive_data ,cbu
,vdd_h ,cbd, dram_arst_l );
output [143:0] afi ;
output [143:0] serial_out ;
output [255:0] io_dram_data_in ;
output [31:0] io_dram_ecc_in ;
input [143:0] afo ;
input [143:0] serial_in ;
input [287:0] dram_io_data_out ;
input [9:0] spare_ddr_data ;
input [4:0] dram_io_ptr_clk_inv ;
input [14:0] dram_io_addr ;
input [2:0] dram_io_bank ;
input [3:0] dram_io_cs_l ;
input [4:0] lpf_code ;
input [8:1] cbu ;
input [8:1] cbd ;
inout [9:0] spare_ddr_pin ;
inout [127:0] dram_dq ;
inout [14:0] dram_addr ;
inout [15:0] dram_cb ;
inout [35:0] dram_dqs ;
inout [2:0] dram_ba ;
inout [3:0] dram_ck_n ;
inout [3:0] dram_ck_p ;
inout [3:0] dram_cs_l ;
output arst_l_out ;
output bypass_enable_out ;
output ps_select_out ;
output pad_clk_so ;
output bso ;
output mode_ctrl_out ;
output update_dr_out ;
output shift_dr_out ;
output clock_dr_out ;
output hiz_n_out ;
output io_dram_data_valid ;
input pad_clk_si ;
input testmode_l ;
input test_mode ;
input rclk ;
input se ;
input update_dr_in ;
input bsi ;
input bypass_enable_in ;
input ps_select_in ;
input mode_ctrl_in ;
input shift_dr_in ;
input clock_dr_in ;
input hiz_n_in ;
input strobe ;
input dram_io_clk_enable ;
input dram_io_cke ;
input dram_io_ras_l ;
input dram_io_write_en_l ;
input dram_io_cas_l ;
input burst_length_four ;
input dram_io_pad_clk_inv ;
input dram_io_pad_enable ;
input dram_io_drive_enable ;
input rst_l ;
input dram_arst_l ;
input dram_io_channel_disabled ;
input dram_io_drive_data ;
input vdd_h ;
inout dram_cke ;
inout dram_ras_l ;
inout dram_we_l ;
inout dram_cas_l ;
wire [8:1] cbd_l ;
wire [7:0] net0187 ;
wire [7:0] net0182 ;
wire [7:0] net0186 ;
wire [7:0] net0412 ;
wire [7:0] net0413 ;
wire [8:1] cbu_l ;
wire [1:0] pad_pos_cnt ;
wire [1:0] pad_neg_cnt ;
wire net0173 ;
wire net0200 ;
wire net0201 ;
wire net0202 ;
wire net0300 ;
wire net0203 ;
wire net0301 ;
wire net0302 ;
wire net0204 ;
wire net0303 ;
wire net0205 ;
wire net0304 ;
wire net0305 ;
wire net0306 ;
wire net0253 ;
wire net0254 ;
wire bso0_bsi1 ;
wire pad_clk_so0_plogic_si1 ;
wire se_out ;
wire net0241 ;
wire net0247 ;
wire net0249 ;
wire net0191 ;
wire net0192 ;
wire net0193 ;
wire net0212 ;
wire net0194 ;
wire net0213 ;
wire net0195 ;
wire net0196 ;
wire net0197 ;
wire net0198 ;
wire net0316 ;
wire net0199 ;
wire pvt_so_top_si ;
wire plogic_clk_so1_pad_si2 ;
bw_io_ddr_sig_top_b I0 (
.vrefcode_i_l ({net0182[0] ,net0182[1] ,net0182[2] ,net0182[3] ,
net0182[4] ,net0182[5] ,net0182[6] ,net0182[7] } ),
.vrefcode_i_r ({net0182[0] ,net0182[1] ,net0182[2] ,net0182[3] ,
net0182[4] ,net0182[5] ,net0182[6] ,net0182[7] } ),
.afo ({afo[71:0] } ),
.serial_in ({serial_in[71:0] } ),
.serial_out ({serial_out[71:0] } ),
.afi ({afi[71:0] } ),
.cbu_o_l ({cbu_l } ),
.cbd_o_l ({cbd_l } ),
.lpf_code_i_r ({lpf_code } ),
.dram_io_ptr_clk_inv_i_r ({dram_io_ptr_clk_inv[1:0] } ),
.pad_pos_cnt_i_r ({pad_pos_cnt } ),
.pad_neg_cnt_i_r ({pad_neg_cnt } ),
.cbu_i_r ({net0412[0] ,net0412[1] ,net0412[2] ,net0412[3] ,
net0412[4] ,net0412[5] ,net0412[6] ,net0412[7] } ),
.cbd_i_r ({net0413[0] ,net0413[1] ,net0413[2] ,net0413[3] ,
net0413[4] ,net0413[5] ,net0413[6] ,net0413[7] } ),
.cbu_o_r ({net0186[0] ,net0186[1] ,net0186[2] ,net0186[3] ,
net0186[4] ,net0186[5] ,net0186[6] ,net0186[7] } ),
.cbd_o_r ({net0187[0] ,net0187[1] ,net0187[2] ,net0187[3] ,
net0187[4] ,net0187[5] ,net0187[6] ,net0187[7] } ),
.spare_ddr_data ({spare_ddr_data[9:8] } ),
.lpf_code_i_l ({lpf_code } ),
.dram_io_ptr_clk_inv_i_l ({dram_io_ptr_clk_inv[1:0] } ),
.cbd_i_l ({net0413[0] ,net0413[1] ,net0413[2] ,net0413[3] ,
net0413[4] ,net0413[5] ,net0413[6] ,net0413[7] } ),
.spare_ddr_pin ({spare_ddr_pin[9:8] } ),
.dram_ck_n ({dram_ck_n } ),
.dram_ck_p ({dram_ck_p } ),
.dram_io_bank ({dram_io_bank[2] } ),
.dram_ba ({dram_ba[2] } ),
.pad_neg_cnt_i_l ({pad_neg_cnt } ),
.cbu_i_l ({net0412[0] ,net0412[1] ,net0412[2] ,net0412[3] ,
net0412[4] ,net0412[5] ,net0412[6] ,net0412[7] } ),
.dram_cb ({dram_cb[7:0] } ),
.pad_pos_cnt_i_l ({pad_pos_cnt } ),
.se_o_l (se_out ),
.dram_io_drive_enable_o_l (net0316 ),
.mode_ctrl_out (net0306 ),
.update_dr_out (net0305 ),
.shift_dr_out (net0304 ),
.clock_dr_out (net0303 ),
.hiz_n_out (net0302 ),
.bypass_enable_out (net0301 ),
.ps_select_out (net0300 ),
.test_mode_i_r (test_mode ),
.strobe_i_r (strobe ),
.testmode_l_i_l (testmode_l ),
.burst_length_four_i_r (burst_length_four ),
.dram_io_pad_enable_i_r (dram_io_pad_enable ),
.dram_io_drive_enable_i_r (dram_io_drive_enable ),
.rst_l_i_r (rst_l ),
.arst_l_i_r (dram_arst_l ),
.dram_io_channel_disabled_i_r (dram_io_channel_disabled ),
.dram_io_drive_data_i_r (dram_io_drive_data ),
.se_i_r (se ),
.mode_ctrl_i_r (net0191 ),
.shift_dr_i_r (net0193 ),
.clock_dr_i_r (net0194 ),
.hiz_n_i_r (net0195 ),
.update_dr_i_r (net0192 ),
.vdd_h (vdd_h ),
.strobe_i_l (strobe ),
.bypass_enable_i_l (net0203 ),
.ps_select_i_r (net0197 ),
.ps_select_i_l (net0204 ),
.test_mode_i_l (test_mode ),
.testmode_l_i_r (testmode_l ),
.dram_io_pad_enable_i_l (dram_io_pad_enable ),
.burst_length_four_i_l (burst_length_four ),
.\dram_io_data_out[95] (dram_io_data_out[95] ),
.\dram_io_data_out[94] (dram_io_data_out[94] ),
.\dram_io_data_out[93] (dram_io_data_out[93] ),
.\dram_io_data_out[92] (dram_io_data_out[92] ),
.\dram_io_data_out[91] (dram_io_data_out[91] ),
.\dram_io_data_out[90] (dram_io_data_out[90] ),
.\dram_io_data_out[89] (dram_io_data_out[89] ),
.\dram_io_data_out[88] (dram_io_data_out[88] ),
.\dram_io_data_out[87] (dram_io_data_out[87] ),
.\dram_io_data_out[86] (dram_io_data_out[86] ),
.\dram_io_data_out[85] (dram_io_data_out[85] ),
.\dram_io_data_out[84] (dram_io_data_out[84] ),
.\dram_io_data_out[83] (dram_io_data_out[83] ),
.\dram_io_data_out[82] (dram_io_data_out[82] ),
.\dram_io_data_out[81] (dram_io_data_out[81] ),
.\dram_io_data_out[80] (dram_io_data_out[80] ),
.\dram_io_data_out[79] (dram_io_data_out[79] ),
.\dram_io_data_out[78] (dram_io_data_out[78] ),
.\dram_io_data_out[77] (dram_io_data_out[77] ),
.\dram_io_data_out[76] (dram_io_data_out[76] ),
.\dram_io_data_out[75] (dram_io_data_out[75] ),
.\dram_io_data_out[74] (dram_io_data_out[74] ),
.\dram_io_data_out[73] (dram_io_data_out[73] ),
.\dram_io_data_out[72] (dram_io_data_out[72] ),
.\dram_io_data_out[71] (dram_io_data_out[71] ),
.\dram_io_data_out[70] (dram_io_data_out[70] ),
.\dram_io_data_out[69] (dram_io_data_out[69] ),
.\dram_io_data_out[68] (dram_io_data_out[68] ),
.\dram_io_data_out[67] (dram_io_data_out[67] ),
.\dram_io_data_out[66] (dram_io_data_out[66] ),
.\dram_io_data_out[65] (dram_io_data_out[65] ),
.\dram_io_data_out[64] (dram_io_data_out[64] ),
.\dram_io_data_out[31] (dram_io_data_out[31] ),
.\dram_io_data_out[30] (dram_io_data_out[30] ),
.\dram_io_data_out[29] (dram_io_data_out[29] ),
.\dram_io_data_out[28] (dram_io_data_out[28] ),
.\dram_io_data_out[27] (dram_io_data_out[27] ),
.\dram_io_data_out[26] (dram_io_data_out[26] ),
.\dram_io_data_out[25] (dram_io_data_out[25] ),
.\dram_io_data_out[24] (dram_io_data_out[24] ),
.\dram_io_data_out[23] (dram_io_data_out[23] ),
.\dram_io_data_out[22] (dram_io_data_out[22] ),
.\dram_io_data_out[21] (dram_io_data_out[21] ),
.\dram_io_data_out[20] (dram_io_data_out[20] ),
.\dram_io_data_out[19] (dram_io_data_out[19] ),
.\dram_io_data_out[18] (dram_io_data_out[18] ),
.\dram_io_data_out[17] (dram_io_data_out[17] ),
.\dram_io_data_out[16] (dram_io_data_out[16] ),
.\dram_io_data_out[15] (dram_io_data_out[15] ),
.\dram_io_data_out[14] (dram_io_data_out[14] ),
.\dram_io_data_out[13] (dram_io_data_out[13] ),
.\dram_io_data_out[12] (dram_io_data_out[12] ),
.\dram_io_data_out[11] (dram_io_data_out[11] ),
.\dram_io_data_out[10] (dram_io_data_out[10] ),
.\dram_io_data_out[9] (dram_io_data_out[9] ),
.\dram_io_data_out[8] (dram_io_data_out[8] ),
.\dram_io_data_out[7] (dram_io_data_out[7] ),
.\dram_io_data_out[6] (dram_io_data_out[6] ),
.\dram_io_data_out[5] (dram_io_data_out[5] ),
.\dram_io_data_out[4] (dram_io_data_out[4] ),
.\dram_io_data_out[3] (dram_io_data_out[3] ),
.\dram_io_data_out[2] (dram_io_data_out[2] ),
.\dram_io_data_out[1] (dram_io_data_out[1] ),
.\dram_io_data_out[0] (dram_io_data_out[0] ),
.dram_io_channel_disabled_i_l (dram_io_channel_disabled ),
.dram_io_drive_enable_i_l (dram_io_drive_enable ),
.rclk (rclk ),
.\dram_io_data_out[175] (dram_io_data_out[175] ),
.\dram_io_data_out[174] (dram_io_data_out[174] ),
.\dram_io_data_out[173] (dram_io_data_out[173] ),
.\dram_io_data_out[172] (dram_io_data_out[172] ),
.\dram_io_data_out[171] (dram_io_data_out[171] ),
.\dram_io_data_out[170] (dram_io_data_out[170] ),
.\dram_io_data_out[169] (dram_io_data_out[169] ),
.\dram_io_data_out[168] (dram_io_data_out[168] ),
.\dram_io_data_out[167] (dram_io_data_out[167] ),
.\dram_io_data_out[166] (dram_io_data_out[166] ),
.\dram_io_data_out[165] (dram_io_data_out[165] ),
.\dram_io_data_out[164] (dram_io_data_out[164] ),
.\dram_io_data_out[163] (dram_io_data_out[163] ),
.\dram_io_data_out[162] (dram_io_data_out[162] ),
.\dram_io_data_out[161] (dram_io_data_out[161] ),
.\dram_io_data_out[160] (dram_io_data_out[160] ),
.\dram_io_data_out[159] (dram_io_data_out[159] ),
.\dram_io_data_out[158] (dram_io_data_out[158] ),
.\dram_io_data_out[157] (dram_io_data_out[157] ),
.\dram_io_data_out[156] (dram_io_data_out[156] ),
.\dram_io_data_out[155] (dram_io_data_out[155] ),
.\dram_io_data_out[154] (dram_io_data_out[154] ),
.\dram_io_data_out[153] (dram_io_data_out[153] ),
.\dram_io_data_out[152] (dram_io_data_out[152] ),
.\dram_io_data_out[151] (dram_io_data_out[151] ),
.\dram_io_data_out[150] (dram_io_data_out[150] ),
.\dram_io_data_out[149] (dram_io_data_out[149] ),
.\dram_io_data_out[148] (dram_io_data_out[148] ),
.\dram_io_data_out[147] (dram_io_data_out[147] ),
.\dram_io_data_out[146] (dram_io_data_out[146] ),
.\dram_io_data_out[145] (dram_io_data_out[145] ),
.\dram_io_data_out[144] (dram_io_data_out[144] ),
.\dram_io_data_out[279] (dram_io_data_out[279] ),
.\dram_io_data_out[278] (dram_io_data_out[278] ),
.\dram_io_data_out[277] (dram_io_data_out[277] ),
.\dram_io_data_out[276] (dram_io_data_out[276] ),
.\dram_io_data_out[275] (dram_io_data_out[275] ),
.\dram_io_data_out[274] (dram_io_data_out[274] ),
.\dram_io_data_out[273] (dram_io_data_out[273] ),
.\dram_io_data_out[272] (dram_io_data_out[272] ),
.\io_dram_data_in[223] (io_dram_data_in[223] ),
.\io_dram_data_in[222] (io_dram_data_in[222] ),
.\io_dram_data_in[221] (io_dram_data_in[221] ),
.\io_dram_data_in[220] (io_dram_data_in[220] ),
.\io_dram_data_in[219] (io_dram_data_in[219] ),
.\io_dram_data_in[218] (io_dram_data_in[218] ),
.\io_dram_data_in[217] (io_dram_data_in[217] ),
.\io_dram_data_in[216] (io_dram_data_in[216] ),
.\io_dram_data_in[215] (io_dram_data_in[215] ),
.\io_dram_data_in[214] (io_dram_data_in[214] ),
.\io_dram_data_in[213] (io_dram_data_in[213] ),
.\io_dram_data_in[212] (io_dram_data_in[212] ),
.\io_dram_data_in[211] (io_dram_data_in[211] ),
.\io_dram_data_in[210] (io_dram_data_in[210] ),
.\io_dram_data_in[209] (io_dram_data_in[209] ),
.\io_dram_data_in[208] (io_dram_data_in[208] ),
.\io_dram_data_in[207] (io_dram_data_in[207] ),
.\io_dram_data_in[206] (io_dram_data_in[206] ),
.\io_dram_data_in[205] (io_dram_data_in[205] ),
.\io_dram_data_in[204] (io_dram_data_in[204] ),
.\io_dram_data_in[203] (io_dram_data_in[203] ),
.\io_dram_data_in[202] (io_dram_data_in[202] ),
.\io_dram_data_in[201] (io_dram_data_in[201] ),
.\io_dram_data_in[200] (io_dram_data_in[200] ),
.\io_dram_data_in[199] (io_dram_data_in[199] ),
.\io_dram_data_in[198] (io_dram_data_in[198] ),
.\io_dram_data_in[197] (io_dram_data_in[197] ),
.\io_dram_data_in[196] (io_dram_data_in[196] ),
.\io_dram_data_in[195] (io_dram_data_in[195] ),
.\io_dram_data_in[194] (io_dram_data_in[194] ),
.\io_dram_data_in[193] (io_dram_data_in[193] ),
.\io_dram_data_in[192] (io_dram_data_in[192] ),
.\dram_io_data_out[135] (dram_io_data_out[135] ),
.\dram_io_data_out[134] (dram_io_data_out[134] ),
.\dram_io_data_out[133] (dram_io_data_out[133] ),
.\dram_io_data_out[132] (dram_io_data_out[132] ),
.\dram_io_data_out[131] (dram_io_data_out[131] ),
.\dram_io_data_out[130] (dram_io_data_out[130] ),
.\dram_io_data_out[129] (dram_io_data_out[129] ),
.\dram_io_data_out[128] (dram_io_data_out[128] ),
.\io_dram_ecc_in[23] (io_dram_ecc_in[23] ),
.\io_dram_ecc_in[22] (io_dram_ecc_in[22] ),
.\io_dram_ecc_in[21] (io_dram_ecc_in[21] ),
.\io_dram_ecc_in[20] (io_dram_ecc_in[20] ),
.\io_dram_ecc_in[19] (io_dram_ecc_in[19] ),
.\io_dram_ecc_in[18] (io_dram_ecc_in[18] ),
.\io_dram_ecc_in[17] (io_dram_ecc_in[17] ),
.\io_dram_ecc_in[16] (io_dram_ecc_in[16] ),
.\io_dram_ecc_in[7] (io_dram_ecc_in[7] ),
.\io_dram_ecc_in[6] (io_dram_ecc_in[6] ),
.\io_dram_ecc_in[5] (io_dram_ecc_in[5] ),
.\io_dram_ecc_in[4] (io_dram_ecc_in[4] ),
.\io_dram_ecc_in[3] (io_dram_ecc_in[3] ),
.\io_dram_ecc_in[2] (io_dram_ecc_in[2] ),
.\io_dram_ecc_in[1] (io_dram_ecc_in[1] ),
.\io_dram_ecc_in[0] (io_dram_ecc_in[0] ),
.\io_dram_data_in[159] (io_dram_data_in[159] ),
.\io_dram_data_in[158] (io_dram_data_in[158] ),
.\io_dram_data_in[157] (io_dram_data_in[157] ),
.\io_dram_data_in[156] (io_dram_data_in[156] ),
.\io_dram_data_in[155] (io_dram_data_in[155] ),
.\io_dram_data_in[154] (io_dram_data_in[154] ),
.\io_dram_data_in[153] (io_dram_data_in[153] ),
.\io_dram_data_in[152] (io_dram_data_in[152] ),
.\io_dram_data_in[151] (io_dram_data_in[151] ),
.\io_dram_data_in[150] (io_dram_data_in[150] ),
.\io_dram_data_in[149] (io_dram_data_in[149] ),
.\io_dram_data_in[148] (io_dram_data_in[148] ),
.\io_dram_data_in[147] (io_dram_data_in[147] ),
.\io_dram_data_in[146] (io_dram_data_in[146] ),
.\io_dram_data_in[145] (io_dram_data_in[145] ),
.\io_dram_data_in[144] (io_dram_data_in[144] ),
.\io_dram_data_in[143] (io_dram_data_in[143] ),
.\io_dram_data_in[142] (io_dram_data_in[142] ),
.\io_dram_data_in[141] (io_dram_data_in[141] ),
.\io_dram_data_in[140] (io_dram_data_in[140] ),
.\io_dram_data_in[139] (io_dram_data_in[139] ),
.\io_dram_data_in[138] (io_dram_data_in[138] ),
.\io_dram_data_in[137] (io_dram_data_in[137] ),
.\io_dram_data_in[136] (io_dram_data_in[136] ),
.\io_dram_data_in[135] (io_dram_data_in[135] ),
.\io_dram_data_in[134] (io_dram_data_in[134] ),
.\io_dram_data_in[133] (io_dram_data_in[133] ),
.\io_dram_data_in[132] (io_dram_data_in[132] ),
.\io_dram_data_in[131] (io_dram_data_in[131] ),
.\io_dram_data_in[130] (io_dram_data_in[130] ),
.\io_dram_data_in[129] (io_dram_data_in[129] ),
.\io_dram_data_in[128] (io_dram_data_in[128] ),
.\io_dram_data_in[31] (io_dram_data_in[31] ),
.\io_dram_data_in[30] (io_dram_data_in[30] ),
.\io_dram_data_in[29] (io_dram_data_in[29] ),
.\io_dram_data_in[28] (io_dram_data_in[28] ),
.\io_dram_data_in[27] (io_dram_data_in[27] ),
.\io_dram_data_in[26] (io_dram_data_in[26] ),
.\io_dram_data_in[25] (io_dram_data_in[25] ),
.\io_dram_data_in[24] (io_dram_data_in[24] ),
.\io_dram_data_in[23] (io_dram_data_in[23] ),
.\io_dram_data_in[22] (io_dram_data_in[22] ),
.\io_dram_data_in[21] (io_dram_data_in[21] ),
.\io_dram_data_in[20] (io_dram_data_in[20] ),
.\io_dram_data_in[19] (io_dram_data_in[19] ),
.\io_dram_data_in[18] (io_dram_data_in[18] ),
.\io_dram_data_in[17] (io_dram_data_in[17] ),
.\io_dram_data_in[16] (io_dram_data_in[16] ),
.\io_dram_data_in[15] (io_dram_data_in[15] ),
.\io_dram_data_in[14] (io_dram_data_in[14] ),
.\io_dram_data_in[13] (io_dram_data_in[13] ),
.\io_dram_data_in[12] (io_dram_data_in[12] ),
.\io_dram_data_in[11] (io_dram_data_in[11] ),
.\io_dram_data_in[10] (io_dram_data_in[10] ),
.\io_dram_data_in[9] (io_dram_data_in[9] ),
.\io_dram_data_in[8] (io_dram_data_in[8] ),
.\io_dram_data_in[7] (io_dram_data_in[7] ),
.\io_dram_data_in[6] (io_dram_data_in[6] ),
.\io_dram_data_in[5] (io_dram_data_in[5] ),
.\io_dram_data_in[4] (io_dram_data_in[4] ),
.\io_dram_data_in[3] (io_dram_data_in[3] ),
.\io_dram_data_in[2] (io_dram_data_in[2] ),
.\io_dram_data_in[1] (io_dram_data_in[1] ),
.\io_dram_data_in[0] (io_dram_data_in[0] ),
.pad_clk_so (pad_clk_so0_plogic_si1 ),
.pad_clk_si (pvt_so_top_si ),
.\dram_addr[9] (dram_addr[9] ),
.\dram_addr[8] (dram_addr[8] ),
.\dram_addr[7] (dram_addr[7] ),
.\dram_addr[6] (dram_addr[6] ),
.\dram_addr[5] (dram_addr[5] ),
.\dram_addr[4] (dram_addr[4] ),
.\dram_addr[3] (dram_addr[3] ),
.\dram_addr[2] (dram_addr[2] ),
.\dram_addr[1] (dram_addr[1] ),
.\dram_addr[0] (dram_addr[0] ),
.\dram_io_addr[9] (dram_io_addr[9] ),
.\dram_io_addr[8] (dram_io_addr[8] ),
.\dram_io_addr[7] (dram_io_addr[7] ),
.\dram_io_addr[6] (dram_io_addr[6] ),
.\dram_io_addr[5] (dram_io_addr[5] ),
.\dram_io_addr[4] (dram_io_addr[4] ),
.\dram_io_addr[3] (dram_io_addr[3] ),
.\dram_io_addr[2] (dram_io_addr[2] ),
.\dram_io_addr[1] (dram_io_addr[1] ),
.\dram_io_addr[0] (dram_io_addr[0] ),
.\dram_dqs[12] (dram_dqs[12] ),
.\dram_dqs[11] (dram_dqs[11] ),
.\dram_dqs[10] (dram_dqs[10] ),
.\dram_dqs[9] (dram_dqs[9] ),
.\dram_dqs[8] (dram_dqs[8] ),
.bso (bso0_bsi1 ),
.bsi (bsi ),
.dram_io_clk_enable (dram_io_clk_enable ),
.\dram_addr[14] (dram_addr[14] ),
.\dram_addr[13] (dram_addr[13] ),
.\dram_addr[12] (dram_addr[12] ),
.\dram_addr[11] (dram_addr[11] ),
.dram_cke (dram_cke ),
.dram_io_cke (dram_io_cke ),
.\dram_io_addr[14] (dram_io_addr[14] ),
.\dram_io_addr[13] (dram_io_addr[13] ),
.\dram_io_addr[12] (dram_io_addr[12] ),
.\dram_io_addr[11] (dram_io_addr[11] ),
.\dram_dq[95] (dram_dq[95] ),
.\dram_dq[94] (dram_dq[94] ),
.\dram_dq[93] (dram_dq[93] ),
.\dram_dq[92] (dram_dq[92] ),
.\dram_dq[91] (dram_dq[91] ),
.\dram_dq[90] (dram_dq[90] ),
.\dram_dq[89] (dram_dq[89] ),
.\dram_dq[88] (dram_dq[88] ),
.\dram_dq[87] (dram_dq[87] ),
.\dram_dq[86] (dram_dq[86] ),
.\dram_dq[85] (dram_dq[85] ),
.\dram_dq[84] (dram_dq[84] ),
.\dram_dq[83] (dram_dq[83] ),
.\dram_dq[82] (dram_dq[82] ),
.\dram_dq[81] (dram_dq[81] ),
.\dram_dq[80] (dram_dq[80] ),
.\dram_dq[79] (dram_dq[79] ),
.\dram_dq[78] (dram_dq[78] ),
.\dram_dq[77] (dram_dq[77] ),
.\dram_dq[76] (dram_dq[76] ),
.\dram_dq[75] (dram_dq[75] ),
.\dram_dq[74] (dram_dq[74] ),
.\dram_dq[73] (dram_dq[73] ),
.\dram_dq[72] (dram_dq[72] ),
.\dram_dq[71] (dram_dq[71] ),
.\dram_dq[70] (dram_dq[70] ),
.\dram_dq[69] (dram_dq[69] ),
.\dram_dq[68] (dram_dq[68] ),
.\dram_dq[67] (dram_dq[67] ),
.\dram_dq[66] (dram_dq[66] ),
.\dram_dq[65] (dram_dq[65] ),
.\dram_dq[64] (dram_dq[64] ),
.\dram_dq[31] (dram_dq[31] ),
.\dram_dq[30] (dram_dq[30] ),
.\dram_dq[29] (dram_dq[29] ),
.\dram_dq[28] (dram_dq[28] ),
.\dram_dq[27] (dram_dq[27] ),
.\dram_dq[26] (dram_dq[26] ),
.\dram_dq[25] (dram_dq[25] ),
.\dram_dq[24] (dram_dq[24] ),
.\dram_dq[23] (dram_dq[23] ),
.\dram_dq[22] (dram_dq[22] ),
.\dram_dq[21] (dram_dq[21] ),
.\dram_dq[20] (dram_dq[20] ),
.\dram_dq[19] (dram_dq[19] ),
.\dram_dq[18] (dram_dq[18] ),
.\dram_dq[17] (dram_dq[17] ),
.\dram_dq[16] (dram_dq[16] ),
.\dram_dq[15] (dram_dq[15] ),
.\dram_dq[14] (dram_dq[14] ),
.\dram_dq[13] (dram_dq[13] ),
.\dram_dq[12] (dram_dq[12] ),
.\dram_dq[11] (dram_dq[11] ),
.\dram_dq[10] (dram_dq[10] ),
.\dram_dq[9] (dram_dq[9] ),
.\dram_dq[8] (dram_dq[8] ),
.\dram_dq[7] (dram_dq[7] ),
.\dram_dq[6] (dram_dq[6] ),
.\dram_dq[5] (dram_dq[5] ),
.\dram_dq[4] (dram_dq[4] ),
.\dram_dq[3] (dram_dq[3] ),
.\dram_dq[2] (dram_dq[2] ),
.\dram_dq[1] (dram_dq[1] ),
.\dram_dq[0] (dram_dq[0] ),
.\dram_dqs[3] (dram_dqs[3] ),
.\dram_dqs[2] (dram_dqs[2] ),
.\dram_dqs[1] (dram_dqs[1] ),
.\dram_dqs[0] (dram_dqs[0] ),
.\dram_dqs[21] (dram_dqs[21] ),
.\dram_dqs[20] (dram_dqs[20] ),
.\dram_dqs[19] (dram_dqs[19] ),
.\dram_dqs[18] (dram_dqs[18] ),
.\dram_dqs[17] (dram_dqs[17] ),
.\dram_dqs[30] (dram_dqs[30] ),
.\dram_dqs[29] (dram_dqs[29] ),
.\dram_dqs[28] (dram_dqs[28] ),
.\dram_dqs[27] (dram_dqs[27] ),
.rst_l_i_l (rst_l ),
.arst_l_i_l (dram_arst_l ),
.bypass_enable_i_r (net0196 ),
.hiz_n_i_l (net0202 ),
.shift_dr_i_l (net0200 ),
.mode_ctrl_i_l (net0198 ),
.dram_io_drive_data_i_l (dram_io_drive_data ),
.se_i_l (se ),
.update_dr_i_l (net0199 ),
.clock_dr_i_l (net0201 ),
.\io_dram_data_in[95] (io_dram_data_in[95] ),
.\io_dram_data_in[94] (io_dram_data_in[94] ),
.\io_dram_data_in[93] (io_dram_data_in[93] ),
.\io_dram_data_in[92] (io_dram_data_in[92] ),
.\io_dram_data_in[91] (io_dram_data_in[91] ),
.\io_dram_data_in[90] (io_dram_data_in[90] ),
.\io_dram_data_in[89] (io_dram_data_in[89] ),
.\io_dram_data_in[88] (io_dram_data_in[88] ),
.\io_dram_data_in[87] (io_dram_data_in[87] ),
.\io_dram_data_in[86] (io_dram_data_in[86] ),
.\io_dram_data_in[85] (io_dram_data_in[85] ),
.\io_dram_data_in[84] (io_dram_data_in[84] ),
.\io_dram_data_in[83] (io_dram_data_in[83] ),
.\io_dram_data_in[82] (io_dram_data_in[82] ),
.\io_dram_data_in[81] (io_dram_data_in[81] ),
.\io_dram_data_in[80] (io_dram_data_in[80] ),
.\io_dram_data_in[79] (io_dram_data_in[79] ),
.\io_dram_data_in[78] (io_dram_data_in[78] ),
.\io_dram_data_in[77] (io_dram_data_in[77] ),
.\io_dram_data_in[76] (io_dram_data_in[76] ),
.\io_dram_data_in[75] (io_dram_data_in[75] ),
.\io_dram_data_in[74] (io_dram_data_in[74] ),
.\io_dram_data_in[73] (io_dram_data_in[73] ),
.\io_dram_data_in[72] (io_dram_data_in[72] ),
.\io_dram_data_in[71] (io_dram_data_in[71] ),
.\io_dram_data_in[70] (io_dram_data_in[70] ),
.\io_dram_data_in[69] (io_dram_data_in[69] ),
.\io_dram_data_in[68] (io_dram_data_in[68] ),
.\io_dram_data_in[67] (io_dram_data_in[67] ),
.\io_dram_data_in[66] (io_dram_data_in[66] ),
.\io_dram_data_in[65] (io_dram_data_in[65] ),
.\io_dram_data_in[64] (io_dram_data_in[64] ),
.\dram_io_data_out[239] (dram_io_data_out[239] ),
.\dram_io_data_out[238] (dram_io_data_out[238] ),
.\dram_io_data_out[237] (dram_io_data_out[237] ),
.\dram_io_data_out[236] (dram_io_data_out[236] ),
.\dram_io_data_out[235] (dram_io_data_out[235] ),
.\dram_io_data_out[234] (dram_io_data_out[234] ),
.\dram_io_data_out[233] (dram_io_data_out[233] ),
.\dram_io_data_out[232] (dram_io_data_out[232] ),
.\dram_io_data_out[231] (dram_io_data_out[231] ),
.\dram_io_data_out[230] (dram_io_data_out[230] ),
.\dram_io_data_out[229] (dram_io_data_out[229] ),
.\dram_io_data_out[228] (dram_io_data_out[228] ),
.\dram_io_data_out[227] (dram_io_data_out[227] ),
.\dram_io_data_out[226] (dram_io_data_out[226] ),
.\dram_io_data_out[225] (dram_io_data_out[225] ),
.\dram_io_data_out[224] (dram_io_data_out[224] ),
.\dram_io_data_out[223] (dram_io_data_out[223] ),
.\dram_io_data_out[222] (dram_io_data_out[222] ),
.\dram_io_data_out[221] (dram_io_data_out[221] ),
.\dram_io_data_out[220] (dram_io_data_out[220] ),
.\dram_io_data_out[219] (dram_io_data_out[219] ),
.\dram_io_data_out[218] (dram_io_data_out[218] ),
.\dram_io_data_out[217] (dram_io_data_out[217] ),
.\dram_io_data_out[216] (dram_io_data_out[216] ),
.\dram_io_data_out[215] (dram_io_data_out[215] ),
.\dram_io_data_out[214] (dram_io_data_out[214] ),
.\dram_io_data_out[213] (dram_io_data_out[213] ),
.\dram_io_data_out[212] (dram_io_data_out[212] ),
.\dram_io_data_out[211] (dram_io_data_out[211] ),
.\dram_io_data_out[210] (dram_io_data_out[210] ),
.\dram_io_data_out[209] (dram_io_data_out[209] ),
.\dram_io_data_out[208] (dram_io_data_out[208] ) );
bw_io_ddr_sig_bot_b I1 (
.vrefcode_i_l ({net0182[0] ,net0182[1] ,net0182[2] ,net0182[3] ,
net0182[4] ,net0182[5] ,net0182[6] ,net0182[7] } ),
.vrefcode_i_r ({net0182[0] ,net0182[1] ,net0182[2] ,net0182[3] ,
net0182[4] ,net0182[5] ,net0182[6] ,net0182[7] } ),
.serial_in ({serial_in[143:72] } ),
.afo ({afo[143:72] } ),
.serial_out ({serial_out[143:72] } ),
.afi ({afi[143:72] } ),
.spare_ddr_data ({spare_ddr_data[7:0] } ),
.spare_ddr_pin ({spare_ddr_pin[7:0] } ),
.cbu_i_r ({net0186[0] ,net0186[1] ,net0186[2] ,net0186[3] ,
net0186[4] ,net0186[5] ,net0186[6] ,net0186[7] } ),
.cbd_i_r ({net0187[0] ,net0187[1] ,net0187[2] ,net0187[3] ,
net0187[4] ,net0187[5] ,net0187[6] ,net0187[7] } ),
.dram_io_ptr_clk_inv_i_l ({dram_io_ptr_clk_inv[1:0] } ),
.arst_l_out (arst_l_out ),
.lpf_code_i_l ({lpf_code } ),
.pad_pos_cnt_i_l ({pad_pos_cnt } ),
.pad_neg_cnt_i_l ({pad_neg_cnt } ),
.dram_cs_l ({dram_cs_l } ),
.cbu_i_l ({cbu_l } ),
.dram_cb ({dram_cb[15:8] } ),
.pad_neg_cnt_i_r ({pad_neg_cnt } ),
.dram_io_bank ({dram_io_bank[1:0] } ),
.dram_addr ({dram_addr[10] } ),
.lpf_code_i_r ({lpf_code } ),
.cbd_i_l ({cbd_l } ),
.dram_io_ptr_clk_inv_i_r ({dram_io_ptr_clk_inv[1:0] } ),
.dram_io_cs_l ({dram_io_cs_l } ),
.dram_ba ({dram_ba[1:0] } ),
.dram_io_addr ({dram_io_addr[10] } ),
.pad_pos_cnt_i_r ({pad_pos_cnt } ),
.ps_select_i_r (net0212 ),
.test_mode_i_l (test_mode ),
.testmode_l_i_r (testmode_l ),
.test_mode_i_r (test_mode ),
.bypass_enable_i_l (net0213 ),
.bypass_enable_i_r (net0213 ),
.ps_select_i_l (net0212 ),
.update_dr_o_l (net0199 ),
.shift_dr_o_l (net0200 ),
.clock_dr_o_l (net0201 ),
.hiz_n_o_l (net0202 ),
.bypass_enable_o_l (net0203 ),
.ps_select_o_r (net0197 ),
.mode_ctrl_o_r (net0191 ),
.update_dr_o_r (net0192 ),
.se_i_r (se ),
.mode_ctrl_i_r (net0249 ),
.clock_dr_i_r (net0241 ),
.mode_ctrl_o_l (net0198 ),
.hiz_n_i_r (net0247 ),
.update_dr_i_r (net0254 ),
.shift_dr_o_r (net0193 ),
.dram_io_drive_enable_i_r (dram_io_drive_enable ),
.clock_dr_o_r (net0194 ),
.hiz_n_o_r (net0195 ),
.ps_select_o_l (net0204 ),
.rclk (rclk ),
.testmode_l_i_l (testmode_l ),
.burst_length_four_i_l (burst_length_four ),
.dram_io_pad_enable_i_l (dram_io_pad_enable ),
.dram_io_drive_enable_i_l (dram_io_drive_enable ),
.rst_l_i_l (rst_l ),
.arst_l_i_l (dram_arst_l ),
.strobe_i_l (strobe ),
.dram_io_channel_disabled_i_l (dram_io_channel_disabled ),
.dram_io_drive_data_i_l (dram_io_drive_data ),
.dram_io_channel_disabled_i_r (dram_io_channel_disabled ),
.dram_io_write_en_l (dram_io_write_en_l ),
.\dram_io_data_out[63] (dram_io_data_out[63] ),
.\dram_io_data_out[62] (dram_io_data_out[62] ),
.\dram_io_data_out[61] (dram_io_data_out[61] ),
.\dram_io_data_out[60] (dram_io_data_out[60] ),
.\dram_io_data_out[59] (dram_io_data_out[59] ),
.\dram_io_data_out[58] (dram_io_data_out[58] ),
.\dram_io_data_out[57] (dram_io_data_out[57] ),
.\dram_io_data_out[56] (dram_io_data_out[56] ),
.\dram_io_data_out[55] (dram_io_data_out[55] ),
.\dram_io_data_out[54] (dram_io_data_out[54] ),
.\dram_io_data_out[53] (dram_io_data_out[53] ),
.\dram_io_data_out[52] (dram_io_data_out[52] ),
.\dram_io_data_out[51] (dram_io_data_out[51] ),
.\dram_io_data_out[50] (dram_io_data_out[50] ),
.\dram_io_data_out[49] (dram_io_data_out[49] ),
.\dram_io_data_out[48] (dram_io_data_out[48] ),
.\dram_io_data_out[47] (dram_io_data_out[47] ),
.\dram_io_data_out[46] (dram_io_data_out[46] ),
.\dram_io_data_out[45] (dram_io_data_out[45] ),
.\dram_io_data_out[44] (dram_io_data_out[44] ),
.\dram_io_data_out[43] (dram_io_data_out[43] ),
.\dram_io_data_out[42] (dram_io_data_out[42] ),
.\dram_io_data_out[41] (dram_io_data_out[41] ),
.\dram_io_data_out[40] (dram_io_data_out[40] ),
.\dram_io_data_out[39] (dram_io_data_out[39] ),
.\dram_io_data_out[38] (dram_io_data_out[38] ),
.\dram_io_data_out[37] (dram_io_data_out[37] ),
.\dram_io_data_out[36] (dram_io_data_out[36] ),
.\dram_io_data_out[35] (dram_io_data_out[35] ),
.\dram_io_data_out[34] (dram_io_data_out[34] ),
.\dram_io_data_out[33] (dram_io_data_out[33] ),
.\dram_io_data_out[32] (dram_io_data_out[32] ),
.\io_dram_data_in[255] (io_dram_data_in[255] ),
.\io_dram_data_in[254] (io_dram_data_in[254] ),
.\io_dram_data_in[253] (io_dram_data_in[253] ),
.\io_dram_data_in[252] (io_dram_data_in[252] ),
.\io_dram_data_in[251] (io_dram_data_in[251] ),
.\io_dram_data_in[250] (io_dram_data_in[250] ),
.\io_dram_data_in[249] (io_dram_data_in[249] ),
.\io_dram_data_in[248] (io_dram_data_in[248] ),
.\io_dram_data_in[247] (io_dram_data_in[247] ),
.\io_dram_data_in[246] (io_dram_data_in[246] ),
.\io_dram_data_in[245] (io_dram_data_in[245] ),
.\io_dram_data_in[244] (io_dram_data_in[244] ),
.\io_dram_data_in[243] (io_dram_data_in[243] ),
.\io_dram_data_in[242] (io_dram_data_in[242] ),
.\io_dram_data_in[241] (io_dram_data_in[241] ),
.\io_dram_data_in[240] (io_dram_data_in[240] ),
.\io_dram_data_in[239] (io_dram_data_in[239] ),
.\io_dram_data_in[238] (io_dram_data_in[238] ),
.\io_dram_data_in[237] (io_dram_data_in[237] ),
.\io_dram_data_in[236] (io_dram_data_in[236] ),
.\io_dram_data_in[235] (io_dram_data_in[235] ),
.\io_dram_data_in[234] (io_dram_data_in[234] ),
.\io_dram_data_in[233] (io_dram_data_in[233] ),
.\io_dram_data_in[232] (io_dram_data_in[232] ),
.\io_dram_data_in[231] (io_dram_data_in[231] ),
.\io_dram_data_in[230] (io_dram_data_in[230] ),
.\io_dram_data_in[229] (io_dram_data_in[229] ),
.\io_dram_data_in[228] (io_dram_data_in[228] ),
.\io_dram_data_in[227] (io_dram_data_in[227] ),
.\io_dram_data_in[226] (io_dram_data_in[226] ),
.\io_dram_data_in[225] (io_dram_data_in[225] ),
.\io_dram_data_in[224] (io_dram_data_in[224] ),
.dram_io_cas_l (dram_io_cas_l ),
.dram_we_l (dram_we_l ),
.dram_cas_l (dram_cas_l ),
.\dram_dq[127] (dram_dq[127] ),
.\dram_dq[126] (dram_dq[126] ),
.\dram_dq[125] (dram_dq[125] ),
.\dram_dq[124] (dram_dq[124] ),
.\dram_dq[123] (dram_dq[123] ),
.\dram_dq[122] (dram_dq[122] ),
.\dram_dq[121] (dram_dq[121] ),
.\dram_dq[120] (dram_dq[120] ),
.\dram_dq[119] (dram_dq[119] ),
.\dram_dq[118] (dram_dq[118] ),
.\dram_dq[117] (dram_dq[117] ),
.\dram_dq[116] (dram_dq[116] ),
.\dram_dq[115] (dram_dq[115] ),
.\dram_dq[114] (dram_dq[114] ),
.\dram_dq[113] (dram_dq[113] ),
.\dram_dq[112] (dram_dq[112] ),
.\dram_dq[111] (dram_dq[111] ),
.\dram_dq[110] (dram_dq[110] ),
.\dram_dq[109] (dram_dq[109] ),
.\dram_dq[108] (dram_dq[108] ),
.\dram_dq[107] (dram_dq[107] ),
.\dram_dq[106] (dram_dq[106] ),
.\dram_dq[105] (dram_dq[105] ),
.\dram_dq[104] (dram_dq[104] ),
.\dram_dq[103] (dram_dq[103] ),
.\dram_dq[102] (dram_dq[102] ),
.\dram_dq[101] (dram_dq[101] ),
.\dram_dq[100] (dram_dq[100] ),
.\dram_dq[99] (dram_dq[99] ),
.\dram_dq[98] (dram_dq[98] ),
.\dram_dq[97] (dram_dq[97] ),
.\dram_dq[96] (dram_dq[96] ),
.\dram_io_data_out[287] (dram_io_data_out[287] ),
.\dram_io_data_out[286] (dram_io_data_out[286] ),
.\dram_io_data_out[285] (dram_io_data_out[285] ),
.\dram_io_data_out[284] (dram_io_data_out[284] ),
.\dram_io_data_out[283] (dram_io_data_out[283] ),
.\dram_io_data_out[282] (dram_io_data_out[282] ),
.\dram_io_data_out[281] (dram_io_data_out[281] ),
.\dram_io_data_out[280] (dram_io_data_out[280] ),
.\dram_io_data_out[143] (dram_io_data_out[143] ),
.\dram_io_data_out[142] (dram_io_data_out[142] ),
.\dram_io_data_out[141] (dram_io_data_out[141] ),
.\dram_io_data_out[140] (dram_io_data_out[140] ),
.\dram_io_data_out[139] (dram_io_data_out[139] ),
.\dram_io_data_out[138] (dram_io_data_out[138] ),
.\dram_io_data_out[137] (dram_io_data_out[137] ),
.\dram_io_data_out[136] (dram_io_data_out[136] ),
.\io_dram_ecc_in[31] (io_dram_ecc_in[31] ),
.\io_dram_ecc_in[30] (io_dram_ecc_in[30] ),
.\io_dram_ecc_in[29] (io_dram_ecc_in[29] ),
.\io_dram_ecc_in[28] (io_dram_ecc_in[28] ),
.\io_dram_ecc_in[27] (io_dram_ecc_in[27] ),
.\io_dram_ecc_in[26] (io_dram_ecc_in[26] ),
.\io_dram_ecc_in[25] (io_dram_ecc_in[25] ),
.\io_dram_ecc_in[24] (io_dram_ecc_in[24] ),
.\io_dram_ecc_in[15] (io_dram_ecc_in[15] ),
.\io_dram_ecc_in[14] (io_dram_ecc_in[14] ),
.\io_dram_ecc_in[13] (io_dram_ecc_in[13] ),
.\io_dram_ecc_in[12] (io_dram_ecc_in[12] ),
.\io_dram_ecc_in[11] (io_dram_ecc_in[11] ),
.\io_dram_ecc_in[10] (io_dram_ecc_in[10] ),
.\io_dram_ecc_in[9] (io_dram_ecc_in[9] ),
.\io_dram_ecc_in[8] (io_dram_ecc_in[8] ),
.\dram_io_data_out[127] (dram_io_data_out[127] ),
.\dram_io_data_out[126] (dram_io_data_out[126] ),
.\dram_io_data_out[125] (dram_io_data_out[125] ),
.\dram_io_data_out[124] (dram_io_data_out[124] ),
.\dram_io_data_out[123] (dram_io_data_out[123] ),
.\dram_io_data_out[122] (dram_io_data_out[122] ),
.\dram_io_data_out[121] (dram_io_data_out[121] ),
.\dram_io_data_out[120] (dram_io_data_out[120] ),
.\dram_io_data_out[119] (dram_io_data_out[119] ),
.\dram_io_data_out[118] (dram_io_data_out[118] ),
.\dram_io_data_out[117] (dram_io_data_out[117] ),
.\dram_io_data_out[116] (dram_io_data_out[116] ),
.\dram_io_data_out[115] (dram_io_data_out[115] ),
.\dram_io_data_out[114] (dram_io_data_out[114] ),
.\dram_io_data_out[113] (dram_io_data_out[113] ),
.\dram_io_data_out[112] (dram_io_data_out[112] ),
.\dram_io_data_out[111] (dram_io_data_out[111] ),
.\dram_io_data_out[110] (dram_io_data_out[110] ),
.\dram_io_data_out[109] (dram_io_data_out[109] ),
.\dram_io_data_out[108] (dram_io_data_out[108] ),
.\dram_io_data_out[107] (dram_io_data_out[107] ),
.\dram_io_data_out[106] (dram_io_data_out[106] ),
.\dram_io_data_out[105] (dram_io_data_out[105] ),
.\dram_io_data_out[104] (dram_io_data_out[104] ),
.\dram_io_data_out[103] (dram_io_data_out[103] ),
.\dram_io_data_out[102] (dram_io_data_out[102] ),
.\dram_io_data_out[101] (dram_io_data_out[101] ),
.\dram_io_data_out[100] (dram_io_data_out[100] ),
.\dram_io_data_out[99] (dram_io_data_out[99] ),
.\dram_io_data_out[98] (dram_io_data_out[98] ),
.\dram_io_data_out[97] (dram_io_data_out[97] ),
.\dram_io_data_out[96] (dram_io_data_out[96] ),
.\io_dram_data_in[191] (io_dram_data_in[191] ),
.\io_dram_data_in[190] (io_dram_data_in[190] ),
.\io_dram_data_in[189] (io_dram_data_in[189] ),
.\io_dram_data_in[188] (io_dram_data_in[188] ),
.\io_dram_data_in[187] (io_dram_data_in[187] ),
.\io_dram_data_in[186] (io_dram_data_in[186] ),
.\io_dram_data_in[185] (io_dram_data_in[185] ),
.\io_dram_data_in[184] (io_dram_data_in[184] ),
.\io_dram_data_in[183] (io_dram_data_in[183] ),
.\io_dram_data_in[182] (io_dram_data_in[182] ),
.\io_dram_data_in[181] (io_dram_data_in[181] ),
.\io_dram_data_in[180] (io_dram_data_in[180] ),
.\io_dram_data_in[179] (io_dram_data_in[179] ),
.\io_dram_data_in[178] (io_dram_data_in[178] ),
.\io_dram_data_in[177] (io_dram_data_in[177] ),
.\io_dram_data_in[176] (io_dram_data_in[176] ),
.\io_dram_data_in[175] (io_dram_data_in[175] ),
.\io_dram_data_in[174] (io_dram_data_in[174] ),
.\io_dram_data_in[173] (io_dram_data_in[173] ),
.\io_dram_data_in[172] (io_dram_data_in[172] ),
.\io_dram_data_in[171] (io_dram_data_in[171] ),
.\io_dram_data_in[170] (io_dram_data_in[170] ),
.\io_dram_data_in[169] (io_dram_data_in[169] ),
.\io_dram_data_in[168] (io_dram_data_in[168] ),
.\io_dram_data_in[167] (io_dram_data_in[167] ),
.\io_dram_data_in[166] (io_dram_data_in[166] ),
.\io_dram_data_in[165] (io_dram_data_in[165] ),
.\io_dram_data_in[164] (io_dram_data_in[164] ),
.\io_dram_data_in[163] (io_dram_data_in[163] ),
.\io_dram_data_in[162] (io_dram_data_in[162] ),
.\io_dram_data_in[161] (io_dram_data_in[161] ),
.\io_dram_data_in[160] (io_dram_data_in[160] ),
.rst_l_i_r (rst_l ),
.arst_l_i_r (dram_arst_l ),
.\io_dram_data_in[127] (io_dram_data_in[127] ),
.\io_dram_data_in[126] (io_dram_data_in[126] ),
.\io_dram_data_in[125] (io_dram_data_in[125] ),
.\io_dram_data_in[124] (io_dram_data_in[124] ),
.\io_dram_data_in[123] (io_dram_data_in[123] ),
.\io_dram_data_in[122] (io_dram_data_in[122] ),
.\io_dram_data_in[121] (io_dram_data_in[121] ),
.\io_dram_data_in[120] (io_dram_data_in[120] ),
.\io_dram_data_in[119] (io_dram_data_in[119] ),
.\io_dram_data_in[118] (io_dram_data_in[118] ),
.\io_dram_data_in[117] (io_dram_data_in[117] ),
.\io_dram_data_in[116] (io_dram_data_in[116] ),
.\io_dram_data_in[115] (io_dram_data_in[115] ),
.\io_dram_data_in[114] (io_dram_data_in[114] ),
.\io_dram_data_in[113] (io_dram_data_in[113] ),
.\io_dram_data_in[112] (io_dram_data_in[112] ),
.\io_dram_data_in[111] (io_dram_data_in[111] ),
.\io_dram_data_in[110] (io_dram_data_in[110] ),
.\io_dram_data_in[109] (io_dram_data_in[109] ),
.\io_dram_data_in[108] (io_dram_data_in[108] ),
.\io_dram_data_in[107] (io_dram_data_in[107] ),
.\io_dram_data_in[106] (io_dram_data_in[106] ),
.\io_dram_data_in[105] (io_dram_data_in[105] ),
.\io_dram_data_in[104] (io_dram_data_in[104] ),
.\io_dram_data_in[103] (io_dram_data_in[103] ),
.\io_dram_data_in[102] (io_dram_data_in[102] ),
.\io_dram_data_in[101] (io_dram_data_in[101] ),
.\io_dram_data_in[100] (io_dram_data_in[100] ),
.\io_dram_data_in[99] (io_dram_data_in[99] ),
.\io_dram_data_in[98] (io_dram_data_in[98] ),
.\io_dram_data_in[97] (io_dram_data_in[97] ),
.\io_dram_data_in[96] (io_dram_data_in[96] ),
.pad_clk_si (plogic_clk_so1_pad_si2 ),
.dram_ras_l (dram_ras_l ),
.dram_io_pad_enable_i_r (dram_io_pad_enable ),
.\dram_io_data_out[271] (dram_io_data_out[271] ),
.\dram_io_data_out[270] (dram_io_data_out[270] ),
.\dram_io_data_out[269] (dram_io_data_out[269] ),
.\dram_io_data_out[268] (dram_io_data_out[268] ),
.\dram_io_data_out[267] (dram_io_data_out[267] ),
.\dram_io_data_out[266] (dram_io_data_out[266] ),
.\dram_io_data_out[265] (dram_io_data_out[265] ),
.\dram_io_data_out[264] (dram_io_data_out[264] ),
.\dram_io_data_out[263] (dram_io_data_out[263] ),
.\dram_io_data_out[262] (dram_io_data_out[262] ),
.\dram_io_data_out[261] (dram_io_data_out[261] ),
.\dram_io_data_out[260] (dram_io_data_out[260] ),
.\dram_io_data_out[259] (dram_io_data_out[259] ),
.\dram_io_data_out[258] (dram_io_data_out[258] ),
.\dram_io_data_out[257] (dram_io_data_out[257] ),
.\dram_io_data_out[256] (dram_io_data_out[256] ),
.\dram_io_data_out[255] (dram_io_data_out[255] ),
.\dram_io_data_out[254] (dram_io_data_out[254] ),
.\dram_io_data_out[253] (dram_io_data_out[253] ),
.\dram_io_data_out[252] (dram_io_data_out[252] ),
.\dram_io_data_out[251] (dram_io_data_out[251] ),
.\dram_io_data_out[250] (dram_io_data_out[250] ),
.\dram_io_data_out[249] (dram_io_data_out[249] ),
.\dram_io_data_out[248] (dram_io_data_out[248] ),
.\dram_io_data_out[247] (dram_io_data_out[247] ),
.\dram_io_data_out[246] (dram_io_data_out[246] ),
.\dram_io_data_out[245] (dram_io_data_out[245] ),
.\dram_io_data_out[244] (dram_io_data_out[244] ),
.\dram_io_data_out[243] (dram_io_data_out[243] ),
.\dram_io_data_out[242] (dram_io_data_out[242] ),
.\dram_io_data_out[241] (dram_io_data_out[241] ),
.\dram_io_data_out[240] (dram_io_data_out[240] ),
.mode_ctrl_i_l (net0249 ),
.\dram_dqs[7] (dram_dqs[7] ),
.\dram_dqs[6] (dram_dqs[6] ),
.\dram_dqs[5] (dram_dqs[5] ),
.\dram_dqs[4] (dram_dqs[4] ),
.bsi (bso0_bsi1 ),
.bso (bso_pre_latch ),
.burst_length_four_i_r (burst_length_four ),
.strobe_i_r (strobe ),
.update_dr_i_l (net0254 ),
.hiz_n_i_l (net0247 ),
.clock_dr_i_l (net0241 ),
.shift_dr_i_l (net0253 ),
.se_i_l (se ),
.pad_clk_so (pad_clk_so ),
.dram_io_ras_l (dram_io_ras_l ),
.\dram_dq[63] (dram_dq[63] ),
.\dram_dq[62] (dram_dq[62] ),
.\dram_dq[61] (dram_dq[61] ),
.\dram_dq[60] (dram_dq[60] ),
.\dram_dq[59] (dram_dq[59] ),
.\dram_dq[58] (dram_dq[58] ),
.\dram_dq[57] (dram_dq[57] ),
.\dram_dq[56] (dram_dq[56] ),
.\dram_dq[55] (dram_dq[55] ),
.\dram_dq[54] (dram_dq[54] ),
.\dram_dq[53] (dram_dq[53] ),
.\dram_dq[52] (dram_dq[52] ),
.\dram_dq[51] (dram_dq[51] ),
.\dram_dq[50] (dram_dq[50] ),
.\dram_dq[49] (dram_dq[49] ),
.\dram_dq[48] (dram_dq[48] ),
.\dram_dq[47] (dram_dq[47] ),
.\dram_dq[46] (dram_dq[46] ),
.\dram_dq[45] (dram_dq[45] ),
.\dram_dq[44] (dram_dq[44] ),
.\dram_dq[43] (dram_dq[43] ),
.\dram_dq[42] (dram_dq[42] ),
.\dram_dq[41] (dram_dq[41] ),
.\dram_dq[40] (dram_dq[40] ),
.\dram_dq[39] (dram_dq[39] ),
.\dram_dq[38] (dram_dq[38] ),
.\dram_dq[37] (dram_dq[37] ),
.\dram_dq[36] (dram_dq[36] ),
.\dram_dq[35] (dram_dq[35] ),
.\dram_dq[34] (dram_dq[34] ),
.\dram_dq[33] (dram_dq[33] ),
.\dram_dq[32] (dram_dq[32] ),
.\dram_dqs[35] (dram_dqs[35] ),
.\dram_dqs[34] (dram_dqs[34] ),
.\dram_dqs[33] (dram_dqs[33] ),
.\dram_dqs[32] (dram_dqs[32] ),
.\dram_dqs[31] (dram_dqs[31] ),
.\dram_dqs[16] (dram_dqs[16] ),
.\dram_dqs[15] (dram_dqs[15] ),
.\dram_dqs[14] (dram_dqs[14] ),
.\dram_dqs[13] (dram_dqs[13] ),
.\dram_dqs[26] (dram_dqs[26] ),
.\dram_dqs[25] (dram_dqs[25] ),
.\dram_dqs[24] (dram_dqs[24] ),
.\dram_dqs[23] (dram_dqs[23] ),
.\dram_dqs[22] (dram_dqs[22] ),
.dram_io_drive_data_i_r (dram_io_drive_data ),
.shift_dr_i_r (net0253 ),
.bypass_enable_o_r (net0196 ),
.vdd_h (vdd_h ),
.\io_dram_data_in[63] (io_dram_data_in[63] ),
.\io_dram_data_in[62] (io_dram_data_in[62] ),
.\io_dram_data_in[61] (io_dram_data_in[61] ),
.\io_dram_data_in[60] (io_dram_data_in[60] ),
.\io_dram_data_in[59] (io_dram_data_in[59] ),
.\io_dram_data_in[58] (io_dram_data_in[58] ),
.\io_dram_data_in[57] (io_dram_data_in[57] ),
.\io_dram_data_in[56] (io_dram_data_in[56] ),
.\io_dram_data_in[55] (io_dram_data_in[55] ),
.\io_dram_data_in[54] (io_dram_data_in[54] ),
.\io_dram_data_in[53] (io_dram_data_in[53] ),
.\io_dram_data_in[52] (io_dram_data_in[52] ),
.\io_dram_data_in[51] (io_dram_data_in[51] ),
.\io_dram_data_in[50] (io_dram_data_in[50] ),
.\io_dram_data_in[49] (io_dram_data_in[49] ),
.\io_dram_data_in[48] (io_dram_data_in[48] ),
.\io_dram_data_in[47] (io_dram_data_in[47] ),
.\io_dram_data_in[46] (io_dram_data_in[46] ),
.\io_dram_data_in[45] (io_dram_data_in[45] ),
.\io_dram_data_in[44] (io_dram_data_in[44] ),
.\io_dram_data_in[43] (io_dram_data_in[43] ),
.\io_dram_data_in[42] (io_dram_data_in[42] ),
.\io_dram_data_in[41] (io_dram_data_in[41] ),
.\io_dram_data_in[40] (io_dram_data_in[40] ),
.\io_dram_data_in[39] (io_dram_data_in[39] ),
.\io_dram_data_in[38] (io_dram_data_in[38] ),
.\io_dram_data_in[37] (io_dram_data_in[37] ),
.\io_dram_data_in[36] (io_dram_data_in[36] ),
.\io_dram_data_in[35] (io_dram_data_in[35] ),
.\io_dram_data_in[34] (io_dram_data_in[34] ),
.\io_dram_data_in[33] (io_dram_data_in[33] ),
.\io_dram_data_in[32] (io_dram_data_in[32] ),
.\dram_io_data_out[207] (dram_io_data_out[207] ),
.\dram_io_data_out[206] (dram_io_data_out[206] ),
.\dram_io_data_out[205] (dram_io_data_out[205] ),
.\dram_io_data_out[204] (dram_io_data_out[204] ),
.\dram_io_data_out[203] (dram_io_data_out[203] ),
.\dram_io_data_out[202] (dram_io_data_out[202] ),
.\dram_io_data_out[201] (dram_io_data_out[201] ),
.\dram_io_data_out[200] (dram_io_data_out[200] ),
.\dram_io_data_out[199] (dram_io_data_out[199] ),
.\dram_io_data_out[198] (dram_io_data_out[198] ),
.\dram_io_data_out[197] (dram_io_data_out[197] ),
.\dram_io_data_out[196] (dram_io_data_out[196] ),
.\dram_io_data_out[195] (dram_io_data_out[195] ),
.\dram_io_data_out[194] (dram_io_data_out[194] ),
.\dram_io_data_out[193] (dram_io_data_out[193] ),
.\dram_io_data_out[192] (dram_io_data_out[192] ),
.\dram_io_data_out[191] (dram_io_data_out[191] ),
.\dram_io_data_out[190] (dram_io_data_out[190] ),
.\dram_io_data_out[189] (dram_io_data_out[189] ),
.\dram_io_data_out[188] (dram_io_data_out[188] ),
.\dram_io_data_out[187] (dram_io_data_out[187] ),
.\dram_io_data_out[186] (dram_io_data_out[186] ),
.\dram_io_data_out[185] (dram_io_data_out[185] ),
.\dram_io_data_out[184] (dram_io_data_out[184] ),
.\dram_io_data_out[183] (dram_io_data_out[183] ),
.\dram_io_data_out[182] (dram_io_data_out[182] ),
.\dram_io_data_out[181] (dram_io_data_out[181] ),
.\dram_io_data_out[180] (dram_io_data_out[180] ),
.\dram_io_data_out[179] (dram_io_data_out[179] ),
.\dram_io_data_out[178] (dram_io_data_out[178] ),
.\dram_io_data_out[177] (dram_io_data_out[177] ),
.\dram_io_data_out[176] (dram_io_data_out[176] ) );
dram_pad_logic I9 (
.pad_neg_cnt ({pad_neg_cnt } ),
.pad_pos_cnt ({pad_pos_cnt } ),
.testmode_l (testmode_l ),
.pad_logic_clk_se (se ),
.pad_logic_clk_si (pad_clk_so0_plogic_si1 ),
.dram_io_pad_clk_inv (dram_io_pad_clk_inv ),
.dram_io_pad_enable (dram_io_pad_enable ),
.burst_length_four (burst_length_four ),
.clk (net0173 ),
.io_dram_data_valid (io_dram_data_valid ),
.arst_l (dram_arst_l ),
.rst_l (rst_l ),
.pad_logic_clk_so (plogic_clk_so1_pad_si2 ) );
bw_u1_buf_15x I140 (
.z (net0249 ),
.a (mode_ctrl_in ) );
bw_u1_buf_15x I141 (
.z (net0254 ),
.a (update_dr_in ) );
bw_u1_buf_15x I142 (
.z (net0253 ),
.a (shift_dr_in ) );
bw_u1_buf_15x I143 (
.z (net0241 ),
.a (clock_dr_in ) );
bw_u1_buf_15x I144 (
.z (net0247 ),
.a (hiz_n_in ) );
bw_u1_buf_15x I145 (
.z (net0213 ),
.a (bypass_enable_in ) );
bw_u1_buf_15x I146 (
.z (net0212 ),
.a (ps_select_in ) );
bw_u1_buf_15x I155 (
.z (shift_dr_out ),
.a (net0304 ) );
bw_u1_buf_15x I156 (
.z (mode_ctrl_out ),
.a (net0306 ) );
bw_u1_buf_15x I157 (
.z (bypass_enable_out ),
.a (net0301 ) );
bw_u1_buf_15x I158 (
.z (clock_dr_out ),
.a (net0303 ) );
bw_u1_buf_15x I159 (
.z (update_dr_out ),
.a (net0305 ) );
bw_u1_buf_15x I160 (
.z (hiz_n_out ),
.a (net0302 ) );
bw_u1_buf_15x I161 (
.z (ps_select_out ),
.a (net0300 ) );
bw_u1_buf_5x I172 (
.z (net0205 ),
.a (net0316 ) );
bw_io_ddr_pvt_enable I176 (
.cbd_in ({cbd } ),
.cbu_in ({cbu } ),
.cbu_out ({net0412[0] ,net0412[1] ,net0412[2] ,net0412[3] ,
net0412[4] ,net0412[5] ,net0412[6] ,net0412[7] } ),
.cbd_out ({net0413[0] ,net0413[1] ,net0413[2] ,net0413[3] ,
net0413[4] ,net0413[5] ,net0413[6] ,net0413[7] } ),
.si (pad_clk_si ),
.en (net0205 ),
.rclk (rclk ),
.se (se_out ),
.so (pvt_so_top_si ) );
bw_io_ddr_vref_logic I177 (
.vrefcode ({net0182[0] ,net0182[1] ,net0182[2] ,net0182[3] ,
net0182[4] ,net0182[5] ,net0182[6] ,net0182[7] } ),
.a (dram_io_ptr_clk_inv[2] ),
.c (dram_io_ptr_clk_inv[4] ),
.b (dram_io_ptr_clk_inv[3] ),
.vdd18 (vdd_h ) );
bw_u1_ckbuf_6x I124 (
.clk (net0173 ),
.rclk (rclk ) );
bw_u1_scanl_2x lockup_latch(
.so(bso),
.sd(bso_pre_latch),
.ck(clock_dr_in));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_PP_SYMBOL_V
`define SKY130_FD_SC_MS__AND4BB_PP_SYMBOL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_PP_SYMBOL_V
|
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`timescale 1ps / 1ps
`define MAJOR_VERSION 1
`define MINOR_VERSION 0
`define REVISION 0
`define MAJOR_RANGE 31:28
`define MINOR_RANGE 27:20
`define REVISION_RANGE 19:16
module axi_lite_demo #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8),
parameter INVERT_AXI_RESET = 1
)(
input clk,
input rst,
//AXI Lite Interface
//Write Address Channel
input i_awvalid,
input [ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
//Write Data Channel
input i_wvalid,
output o_wready,
input [DATA_WIDTH - 1: 0] i_wdata,
//Write Response Channel
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
//Read Address Channel
input i_arvalid,
output o_arready,
input [ADDR_WIDTH - 1: 0] i_araddr,
//Read Data Channel
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [DATA_WIDTH - 1: 0] o_rdata
);
//local parameters
//Address Map
localparam REG_CONTROL = 0;
localparam REG_STATUS = 1;
localparam REG_VERSION = 2;
//Register/Wire
//AXI Signals
reg [31:0] control;
wire [31:0] status;
//Simple User Interface
wire [ADDR_WIDTH - 1: 0] w_reg_address;
wire [((ADDR_WIDTH - 1) - 2): 0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
//Submodules
//Convert AXI Slave signals to a simple register/address strobe
axi_lite_slave #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
) axi_lite_reg_interface (
.clk (clk ),
.rst (w_axi_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
//Asynchronous Logic
assign w_axi_rst = (INVERT_AXI_RESET) ? ~rst : rst;
assign w_reg_32bit_address = w_reg_address[(ADDR_WIDTH - 1): 2];
//blocks
always @ (posedge clk) begin
//De-assert Strobes
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
if (w_axi_rst) begin
control <= 0;
r_reg_out_data <= 0;
end
else begin
if (w_reg_in_rdy && !r_reg_in_ack_stb) begin
//From master
case (w_reg_32bit_address)
REG_CONTROL: begin
control <= w_reg_in_data;
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_in_ack_stb <= 1;
end
else if (w_reg_out_req && !r_reg_out_rdy_stb) begin
//To master
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data <= control;
end
REG_STATUS: begin
r_reg_out_data <= status;
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : if_stage.v
-- DESCRIPTION : IFXe[W
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "cpu.h"
/********** W
[ **********/
module if_stage (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** SPMC^tF[X **********/
input wire [`WordDataBus] spm_rd_data, // ÇÝoµf[^
output wire [`WordAddrBus] spm_addr, // AhX
output wire spm_as_, // AhXXg[u
output wire spm_rw, // ÇÝ^«
output wire [`WordDataBus] spm_wr_data, // «Ýf[^
/********** oXC^tF[X **********/
input wire [`WordDataBus] bus_rd_data, // ÇÝoµf[^
input wire bus_rdy_, // fB
input wire bus_grnt_, // oXOg
output wire bus_req_, // oXNGXg
output wire [`WordAddrBus] bus_addr, // AhX
output wire bus_as_, // AhXXg[u
output wire bus_rw, // ÇÝ^«
output wire [`WordDataBus] bus_wr_data, // «Ýf[^
/********** pCvC§äM **********/
input wire stall, // Xg[
input wire flush, // tbV
input wire [`WordAddrBus] new_pc, // Vµ¢vOJE^
input wire br_taken, // ªò̬§
input wire [`WordAddrBus] br_addr, // ªòæAhX
output wire busy, // rW[M
/********** IF/IDpCvCWX^ **********/
output wire [`WordAddrBus] if_pc, // vOJE^
output wire [`WordDataBus] if_insn, // ½ß
output wire if_en // pCvCf[^ÌLø
);
/********** àÚ±M **********/
wire [`WordDataBus] insn; // tFb`µ½½ß
/********** oXC^tF[X **********/
bus_if bus_if (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.reset (reset), // ñ¯úZbg
/********** pCvC§äM **********/
.stall (stall), // Xg[
.flush (flush), // tbV
M
.busy (busy), // rW[M
/********** CPUC^tF[X **********/
.addr (if_pc), // AhX
.as_ (`ENABLE_), // AhXLø
.rw (`READ), // ÇÝ^«
.wr_data (`WORD_DATA_W'h0), // «Ýf[^
.rd_data (insn), // ÇÝoµf[^
/********** XNb`pbhC^tF[X **********/
.spm_rd_data (spm_rd_data), // ÇÝoµf[^
.spm_addr (spm_addr), // AhX
.spm_as_ (spm_as_), // AhXXg[u
.spm_rw (spm_rw), // ÇÝ^«
.spm_wr_data (spm_wr_data), // «Ýf[^
/********** oXC^tF[X **********/
.bus_rd_data (bus_rd_data), // ÇÝoµf[^
.bus_rdy_ (bus_rdy_), // fB
.bus_grnt_ (bus_grnt_), // oXOg
.bus_req_ (bus_req_), // oXNGXg
.bus_addr (bus_addr), // AhX
.bus_as_ (bus_as_), // AhXXg[u
.bus_rw (bus_rw), // ÇÝ^«
.bus_wr_data (bus_wr_data) // «Ýf[^
);
/********** IFXe[WpCvCWX^ **********/
if_reg if_reg (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.reset (reset), // ñ¯úZbg
/********** tFb`f[^ **********/
.insn (insn), // tFb`µ½½ß
/********** pCvC§äM **********/
.stall (stall), // Xg[
.flush (flush), // tbV
.new_pc (new_pc), // Vµ¢vOJE^
.br_taken (br_taken), // ªò̬§
.br_addr (br_addr), // ªòæAhX
/********** IF/IDpCvCWX^ **********/
.if_pc (if_pc), // vOJE^
.if_insn (if_insn), // ½ß
.if_en (if_en) // pCvCf[^ÌLø
);
endmodule
|
`include "setseed.vh"
`define N 500
module top(input clk, stb, di, output do);
localparam integer DIN_N = 6;
localparam integer DOUT_N = `N;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [5:0] din, output [`N-1:0] dout);
function [31:0] xorshift32(input [31:0] v);
begin
xorshift32 = v;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [31:0] hash32(input [31:0] v);
begin
hash32 = v ^ `SEED;
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
end
endfunction
function [63:0] hash64(input [31:0] v);
begin
hash64[63:32] = hash32(v);
hash64[31: 0] = hash32(~v);
end
endfunction
genvar i;
generate
for (i = 0; i < `N; i = i+1) begin:is
wire o6;
//Randomly take out 1/4 iterations
wire [3:0] hash = hash32(i);
wire opt_out = |hash;
assign dout[i] = o6 & opt_out;
LUT6 #(
.INIT(hash64(i))
) lut6 (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6)
);
end
endgenerate
endmodule
|
// $File: //acds/rel/15.1/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
//-------------------------------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_dcfifo_synchronizer_bundle(
clk,
reset_n,
din,
dout
);
parameter WIDTH = 1;
parameter DEPTH = 3;
input clk;
input reset_n;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
genvar i;
generate
for (i=0; i<WIDTH; i=i+1)
begin : sync
altera_std_synchronizer_nocut #(.depth(DEPTH))
u (
.clk(clk),
.reset_n(reset_n),
.din(din[i]),
.dout(dout[i])
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A31O_BEHAVIORAL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a31o (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_BEHAVIORAL_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:30:26 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, enab_cont_iter, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_fmtted_Result_31_, FPSENCOS_enab_d_ff4_Xn,
FPSENCOS_enab_d_ff4_Yn, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_shift_region_flag_out_0_, FPSENCOS_d_ff1_operation_out,
FPSENCOS_enab_d_ff5_data_out, FPSENCOS_enab_RB3,
FPSENCOS_enab_d_ff_RB1, FPSENCOS_enab_d_ff4_Zn, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_barrel_shifter_load,
FPMULT_FSM_final_result_load, FPMULT_FSM_adder_round_norm_load,
FPMULT_FSM_load_second_step, FPMULT_FSM_exp_operation_load_result,
FPMULT_FSM_first_phase_load, FPMULT_FSM_add_overflow_flag,
FPADDSUB_N60, FPADDSUB_N59, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB__19_net_,
FPADDSUB_SIGN_FLAG_NRM, FPADDSUB_SIGN_FLAG_SHT1SHT2,
FPADDSUB_ADD_OVRFLW_NRM2, FPADDSUB_OP_FLAG_SHT2,
FPADDSUB_SIGN_FLAG_SHT2, FPADDSUB_left_right_SHT2, FPADDSUB__6_net_,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_Shift_reg_FLAGS_7_5, FPADDSUB_Shift_reg_FLAGS_7_6,
FPADDSUB_enable_Pipeline_input, FPSENCOS_ITER_CONT_net8130676,
FPSENCOS_ITER_CONT_N5, FPSENCOS_ITER_CONT_N4, FPSENCOS_ITER_CONT_N3,
FPMULT_FS_Module_net8130622, FPMULT_Exp_module_Overflow_flag_A,
FPMULT_Exp_module_Overflow_A,
FPMULT_final_result_ieee_Module_Sign_S_mux,
FPADDSUB_inst_ShiftRegister_net8130514,
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424,
FPSENCOS_d_ff5_data_out_net8130640,
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352,
FPADDSUB_SGF_STAGE_DMP_net8130406,
FPADDSUB_NRM_STAGE_Raw_mant_net8130388, FPSENCOS_reg_Z0_net8130640,
FPSENCOS_reg_val_muxZ_2stage_net8130640,
FPSENCOS_reg_shift_y_net8130640, FPSENCOS_d_ff4_Xn_net8130640,
FPSENCOS_d_ff4_Yn_net8130640, FPSENCOS_d_ff4_Zn_net8130640,
FPADDSUB_INPUT_STAGE_OPERANDY_net8130352,
FPADDSUB_EXP_STAGE_DMP_net8130406, FPADDSUB_SHT1_STAGE_DMP_net8130406,
FPADDSUB_SHT2_STAGE_DMP_net8130406,
FPADDSUB_SHT2_SHIFT_DATA_net8130388,
FPMULT_Exp_module_exp_result_m_net8130586,
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568,
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550,
FPMULT_Adder_M_Add_Subt_Result_net8130532,
FPMULT_Operands_load_reg_XMRegister_net8130604,
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352, n30,
n106, n107, n810, n813, n816, n819, n824, n829, n830, n834, n842,
n843, n844, n846, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n859, n860, n861, n862, n863, n864, n865, n874, n875,
DP_OP_26J312_126_1325_n18, DP_OP_26J312_126_1325_n17,
DP_OP_26J312_126_1325_n16, DP_OP_26J312_126_1325_n15,
DP_OP_26J312_126_1325_n14, DP_OP_26J312_126_1325_n8,
DP_OP_26J312_126_1325_n7, DP_OP_26J312_126_1325_n6,
DP_OP_26J312_126_1325_n5, DP_OP_26J312_126_1325_n4,
DP_OP_26J312_126_1325_n3, DP_OP_26J312_126_1325_n2,
DP_OP_26J312_126_1325_n1, DP_OP_234J312_129_4955_n22,
DP_OP_234J312_129_4955_n21, DP_OP_234J312_129_4955_n20,
DP_OP_234J312_129_4955_n19, DP_OP_234J312_129_4955_n18,
DP_OP_234J312_129_4955_n17, DP_OP_234J312_129_4955_n16,
DP_OP_234J312_129_4955_n15, DP_OP_234J312_129_4955_n9,
DP_OP_234J312_129_4955_n8, DP_OP_234J312_129_4955_n7,
DP_OP_234J312_129_4955_n6, DP_OP_234J312_129_4955_n5,
DP_OP_234J312_129_4955_n4, DP_OP_234J312_129_4955_n3,
DP_OP_234J312_129_4955_n2, DP_OP_234J312_129_4955_n1, intadd_1048_CI,
intadd_1048_n3, intadd_1048_n2, intadd_1048_n1, intadd_1049_CI,
intadd_1049_n3, intadd_1049_n2, intadd_1049_n1, intadd_1050_CI,
intadd_1050_SUM_2_, intadd_1050_SUM_1_, intadd_1050_SUM_0_,
intadd_1050_n3, intadd_1050_n2, intadd_1050_n1,
DP_OP_497J312_123_1725_n369, DP_OP_497J312_123_1725_n364,
DP_OP_497J312_123_1725_n359, DP_OP_497J312_123_1725_n358,
DP_OP_497J312_123_1725_n351, DP_OP_497J312_123_1725_n345,
DP_OP_497J312_123_1725_n335, DP_OP_497J312_123_1725_n332,
DP_OP_497J312_123_1725_n331, DP_OP_497J312_123_1725_n330,
DP_OP_497J312_123_1725_n329, DP_OP_497J312_123_1725_n328,
DP_OP_497J312_123_1725_n327, DP_OP_497J312_123_1725_n326,
DP_OP_497J312_123_1725_n325, DP_OP_497J312_123_1725_n324,
DP_OP_497J312_123_1725_n323, DP_OP_497J312_123_1725_n322,
DP_OP_497J312_123_1725_n321, DP_OP_497J312_123_1725_n320,
DP_OP_497J312_123_1725_n319, DP_OP_497J312_123_1725_n318,
DP_OP_497J312_123_1725_n317, DP_OP_497J312_123_1725_n316,
DP_OP_497J312_123_1725_n315, DP_OP_497J312_123_1725_n314,
DP_OP_497J312_123_1725_n313, DP_OP_497J312_123_1725_n312,
DP_OP_497J312_123_1725_n311, DP_OP_497J312_123_1725_n310,
DP_OP_497J312_123_1725_n309, DP_OP_497J312_123_1725_n308,
DP_OP_497J312_123_1725_n307, DP_OP_497J312_123_1725_n306,
DP_OP_497J312_123_1725_n279, DP_OP_497J312_123_1725_n274,
DP_OP_497J312_123_1725_n273, DP_OP_497J312_123_1725_n269,
DP_OP_497J312_123_1725_n261, DP_OP_497J312_123_1725_n260,
DP_OP_497J312_123_1725_n255, DP_OP_497J312_123_1725_n250,
DP_OP_497J312_123_1725_n244, DP_OP_497J312_123_1725_n241,
DP_OP_497J312_123_1725_n240, DP_OP_497J312_123_1725_n239,
DP_OP_497J312_123_1725_n238, DP_OP_497J312_123_1725_n237,
DP_OP_497J312_123_1725_n236, DP_OP_497J312_123_1725_n235,
DP_OP_497J312_123_1725_n234, DP_OP_497J312_123_1725_n233,
DP_OP_497J312_123_1725_n232, DP_OP_497J312_123_1725_n231,
DP_OP_497J312_123_1725_n230, DP_OP_497J312_123_1725_n229,
DP_OP_497J312_123_1725_n228, DP_OP_497J312_123_1725_n227,
DP_OP_497J312_123_1725_n226, DP_OP_497J312_123_1725_n225,
DP_OP_497J312_123_1725_n224, DP_OP_497J312_123_1725_n223,
DP_OP_497J312_123_1725_n222, DP_OP_497J312_123_1725_n221,
DP_OP_497J312_123_1725_n220, DP_OP_497J312_123_1725_n219,
DP_OP_497J312_123_1725_n218, DP_OP_497J312_123_1725_n217,
DP_OP_497J312_123_1725_n216, DP_OP_497J312_123_1725_n215,
DP_OP_497J312_123_1725_n202, DP_OP_497J312_123_1725_n201,
DP_OP_497J312_123_1725_n197, DP_OP_497J312_123_1725_n196,
DP_OP_497J312_123_1725_n195, DP_OP_497J312_123_1725_n194,
DP_OP_497J312_123_1725_n193, DP_OP_497J312_123_1725_n192,
DP_OP_497J312_123_1725_n125, DP_OP_497J312_123_1725_n124,
DP_OP_497J312_123_1725_n123, DP_OP_497J312_123_1725_n122,
DP_OP_497J312_123_1725_n121, DP_OP_497J312_123_1725_n120,
DP_OP_497J312_123_1725_n119, DP_OP_497J312_123_1725_n118,
DP_OP_497J312_123_1725_n117, DP_OP_497J312_123_1725_n116,
DP_OP_497J312_123_1725_n114, DP_OP_497J312_123_1725_n113,
DP_OP_497J312_123_1725_n112, DP_OP_497J312_123_1725_n111,
DP_OP_497J312_123_1725_n110, DP_OP_497J312_123_1725_n109,
DP_OP_497J312_123_1725_n108, DP_OP_497J312_123_1725_n107,
DP_OP_497J312_123_1725_n106, DP_OP_497J312_123_1725_n105,
DP_OP_497J312_123_1725_n104, DP_OP_497J312_123_1725_n103,
DP_OP_497J312_123_1725_n101, DP_OP_497J312_123_1725_n100,
DP_OP_497J312_123_1725_n99, DP_OP_497J312_123_1725_n98,
DP_OP_497J312_123_1725_n97, DP_OP_497J312_123_1725_n96,
DP_OP_497J312_123_1725_n94, DP_OP_497J312_123_1725_n91,
DP_OP_497J312_123_1725_n86, DP_OP_497J312_123_1725_n83,
DP_OP_497J312_123_1725_n82, DP_OP_497J312_123_1725_n81,
DP_OP_497J312_123_1725_n80, DP_OP_497J312_123_1725_n79,
DP_OP_497J312_123_1725_n78, DP_OP_497J312_123_1725_n75,
DP_OP_497J312_123_1725_n74, DP_OP_497J312_123_1725_n73,
DP_OP_497J312_123_1725_n72, DP_OP_497J312_123_1725_n70,
DP_OP_497J312_123_1725_n69, DP_OP_497J312_123_1725_n68,
DP_OP_497J312_123_1725_n67, DP_OP_497J312_123_1725_n65,
DP_OP_497J312_123_1725_n64, DP_OP_497J312_123_1725_n63,
DP_OP_497J312_123_1725_n62, DP_OP_497J312_123_1725_n61,
DP_OP_497J312_123_1725_n60, DP_OP_497J312_123_1725_n59,
DP_OP_497J312_123_1725_n58, DP_OP_497J312_123_1725_n57,
DP_OP_497J312_123_1725_n56, DP_OP_497J312_123_1725_n55,
DP_OP_497J312_123_1725_n54, DP_OP_497J312_123_1725_n53,
DP_OP_497J312_123_1725_n52, DP_OP_497J312_123_1725_n51,
DP_OP_497J312_123_1725_n50, DP_OP_497J312_123_1725_n49,
DP_OP_497J312_123_1725_n48, DP_OP_497J312_123_1725_n47,
DP_OP_497J312_123_1725_n46, DP_OP_497J312_123_1725_n45,
DP_OP_497J312_123_1725_n44, DP_OP_497J312_123_1725_n43,
DP_OP_497J312_123_1725_n42, DP_OP_497J312_123_1725_n41,
DP_OP_497J312_123_1725_n40, DP_OP_497J312_123_1725_n39,
DP_OP_497J312_123_1725_n38, DP_OP_497J312_123_1725_n37,
DP_OP_497J312_123_1725_n36, DP_OP_497J312_123_1725_n35,
DP_OP_497J312_123_1725_n34, DP_OP_497J312_123_1725_n33,
DP_OP_497J312_123_1725_n32, DP_OP_497J312_123_1725_n31,
DP_OP_497J312_123_1725_n30, DP_OP_497J312_123_1725_n29,
DP_OP_497J312_123_1725_n28, DP_OP_497J312_123_1725_n27,
DP_OP_497J312_123_1725_n26, DP_OP_497J312_123_1725_n25,
DP_OP_497J312_123_1725_n24, DP_OP_497J312_123_1725_n23,
DP_OP_497J312_123_1725_n22, DP_OP_497J312_123_1725_n21,
DP_OP_497J312_123_1725_n20, DP_OP_497J312_123_1725_n19,
DP_OP_497J312_123_1725_n18, DP_OP_498J312_124_1725_n382,
DP_OP_498J312_124_1725_n381, DP_OP_498J312_124_1725_n379,
DP_OP_498J312_124_1725_n378, DP_OP_498J312_124_1725_n377,
DP_OP_498J312_124_1725_n376, DP_OP_498J312_124_1725_n370,
DP_OP_498J312_124_1725_n364, DP_OP_498J312_124_1725_n360,
DP_OP_498J312_124_1725_n355, DP_OP_498J312_124_1725_n352,
DP_OP_498J312_124_1725_n351, DP_OP_498J312_124_1725_n346,
DP_OP_498J312_124_1725_n341, DP_OP_498J312_124_1725_n335,
DP_OP_498J312_124_1725_n332, DP_OP_498J312_124_1725_n331,
DP_OP_498J312_124_1725_n330, DP_OP_498J312_124_1725_n329,
DP_OP_498J312_124_1725_n328, DP_OP_498J312_124_1725_n327,
DP_OP_498J312_124_1725_n326, DP_OP_498J312_124_1725_n325,
DP_OP_498J312_124_1725_n324, DP_OP_498J312_124_1725_n323,
DP_OP_498J312_124_1725_n322, DP_OP_498J312_124_1725_n321,
DP_OP_498J312_124_1725_n320, DP_OP_498J312_124_1725_n319,
DP_OP_498J312_124_1725_n318, DP_OP_498J312_124_1725_n317,
DP_OP_498J312_124_1725_n316, DP_OP_498J312_124_1725_n315,
DP_OP_498J312_124_1725_n314, DP_OP_498J312_124_1725_n313,
DP_OP_498J312_124_1725_n312, DP_OP_498J312_124_1725_n311,
DP_OP_498J312_124_1725_n310, DP_OP_498J312_124_1725_n309,
DP_OP_498J312_124_1725_n308, DP_OP_498J312_124_1725_n307,
DP_OP_498J312_124_1725_n306, DP_OP_498J312_124_1725_n289,
DP_OP_498J312_124_1725_n283, DP_OP_498J312_124_1725_n279,
DP_OP_498J312_124_1725_n274, DP_OP_498J312_124_1725_n273,
DP_OP_498J312_124_1725_n269, DP_OP_498J312_124_1725_n261,
DP_OP_498J312_124_1725_n260, DP_OP_498J312_124_1725_n255,
DP_OP_498J312_124_1725_n250, DP_OP_498J312_124_1725_n244,
DP_OP_498J312_124_1725_n241, DP_OP_498J312_124_1725_n240,
DP_OP_498J312_124_1725_n239, DP_OP_498J312_124_1725_n238,
DP_OP_498J312_124_1725_n237, DP_OP_498J312_124_1725_n236,
DP_OP_498J312_124_1725_n235, DP_OP_498J312_124_1725_n234,
DP_OP_498J312_124_1725_n233, DP_OP_498J312_124_1725_n232,
DP_OP_498J312_124_1725_n231, DP_OP_498J312_124_1725_n230,
DP_OP_498J312_124_1725_n229, DP_OP_498J312_124_1725_n228,
DP_OP_498J312_124_1725_n227, DP_OP_498J312_124_1725_n226,
DP_OP_498J312_124_1725_n225, DP_OP_498J312_124_1725_n224,
DP_OP_498J312_124_1725_n223, DP_OP_498J312_124_1725_n222,
DP_OP_498J312_124_1725_n221, DP_OP_498J312_124_1725_n220,
DP_OP_498J312_124_1725_n219, DP_OP_498J312_124_1725_n218,
DP_OP_498J312_124_1725_n217, DP_OP_498J312_124_1725_n216,
DP_OP_498J312_124_1725_n215, DP_OP_498J312_124_1725_n202,
DP_OP_498J312_124_1725_n201, DP_OP_498J312_124_1725_n197,
DP_OP_498J312_124_1725_n196, DP_OP_498J312_124_1725_n195,
DP_OP_498J312_124_1725_n194, DP_OP_498J312_124_1725_n193,
DP_OP_498J312_124_1725_n192, DP_OP_498J312_124_1725_n125,
DP_OP_498J312_124_1725_n124, DP_OP_498J312_124_1725_n123,
DP_OP_498J312_124_1725_n122, DP_OP_498J312_124_1725_n121,
DP_OP_498J312_124_1725_n120, DP_OP_498J312_124_1725_n119,
DP_OP_498J312_124_1725_n118, DP_OP_498J312_124_1725_n117,
DP_OP_498J312_124_1725_n116, DP_OP_498J312_124_1725_n114,
DP_OP_498J312_124_1725_n113, DP_OP_498J312_124_1725_n112,
DP_OP_498J312_124_1725_n111, DP_OP_498J312_124_1725_n110,
DP_OP_498J312_124_1725_n109, DP_OP_498J312_124_1725_n108,
DP_OP_498J312_124_1725_n107, DP_OP_498J312_124_1725_n106,
DP_OP_498J312_124_1725_n105, DP_OP_498J312_124_1725_n104,
DP_OP_498J312_124_1725_n103, DP_OP_498J312_124_1725_n101,
DP_OP_498J312_124_1725_n100, DP_OP_498J312_124_1725_n99,
DP_OP_498J312_124_1725_n98, DP_OP_498J312_124_1725_n97,
DP_OP_498J312_124_1725_n96, DP_OP_498J312_124_1725_n94,
DP_OP_498J312_124_1725_n91, DP_OP_498J312_124_1725_n90,
DP_OP_498J312_124_1725_n86, DP_OP_498J312_124_1725_n83,
DP_OP_498J312_124_1725_n82, DP_OP_498J312_124_1725_n81,
DP_OP_498J312_124_1725_n80, DP_OP_498J312_124_1725_n79,
DP_OP_498J312_124_1725_n78, DP_OP_498J312_124_1725_n75,
DP_OP_498J312_124_1725_n74, DP_OP_498J312_124_1725_n73,
DP_OP_498J312_124_1725_n72, DP_OP_498J312_124_1725_n70,
DP_OP_498J312_124_1725_n69, DP_OP_498J312_124_1725_n68,
DP_OP_498J312_124_1725_n67, DP_OP_498J312_124_1725_n65,
DP_OP_498J312_124_1725_n64, DP_OP_498J312_124_1725_n63,
DP_OP_498J312_124_1725_n62, DP_OP_498J312_124_1725_n61,
DP_OP_498J312_124_1725_n60, DP_OP_498J312_124_1725_n59,
DP_OP_498J312_124_1725_n58, DP_OP_498J312_124_1725_n57,
DP_OP_498J312_124_1725_n56, DP_OP_498J312_124_1725_n55,
DP_OP_498J312_124_1725_n54, DP_OP_498J312_124_1725_n53,
DP_OP_498J312_124_1725_n52, DP_OP_498J312_124_1725_n51,
DP_OP_498J312_124_1725_n50, DP_OP_498J312_124_1725_n49,
DP_OP_498J312_124_1725_n48, DP_OP_498J312_124_1725_n47,
DP_OP_498J312_124_1725_n46, DP_OP_498J312_124_1725_n45,
DP_OP_498J312_124_1725_n44, DP_OP_498J312_124_1725_n43,
DP_OP_498J312_124_1725_n42, DP_OP_498J312_124_1725_n41,
DP_OP_498J312_124_1725_n40, DP_OP_498J312_124_1725_n39,
DP_OP_498J312_124_1725_n38, DP_OP_498J312_124_1725_n37,
DP_OP_498J312_124_1725_n36, DP_OP_498J312_124_1725_n35,
DP_OP_498J312_124_1725_n34, DP_OP_498J312_124_1725_n33,
DP_OP_498J312_124_1725_n32, DP_OP_498J312_124_1725_n31,
DP_OP_498J312_124_1725_n30, DP_OP_498J312_124_1725_n29,
DP_OP_498J312_124_1725_n28, DP_OP_498J312_124_1725_n27,
DP_OP_498J312_124_1725_n26, DP_OP_498J312_124_1725_n25,
DP_OP_498J312_124_1725_n24, DP_OP_498J312_124_1725_n23,
DP_OP_498J312_124_1725_n22, DP_OP_498J312_124_1725_n21,
DP_OP_498J312_124_1725_n20, DP_OP_498J312_124_1725_n19,
DP_OP_498J312_124_1725_n18, DP_OP_499J312_125_1651_n109,
DP_OP_499J312_125_1651_n108, DP_OP_499J312_125_1651_n107,
DP_OP_499J312_125_1651_n106, DP_OP_499J312_125_1651_n105,
DP_OP_499J312_125_1651_n104, DP_OP_499J312_125_1651_n103,
DP_OP_499J312_125_1651_n102, DP_OP_499J312_125_1651_n101,
DP_OP_499J312_125_1651_n100, DP_OP_499J312_125_1651_n99,
DP_OP_499J312_125_1651_n98, DP_OP_499J312_125_1651_n97,
DP_OP_499J312_125_1651_n96, DP_OP_499J312_125_1651_n95,
DP_OP_499J312_125_1651_n94, DP_OP_499J312_125_1651_n80,
DP_OP_499J312_125_1651_n78, DP_OP_499J312_125_1651_n77,
DP_OP_499J312_125_1651_n76, DP_OP_499J312_125_1651_n75,
DP_OP_499J312_125_1651_n74, DP_OP_499J312_125_1651_n73,
DP_OP_499J312_125_1651_n72, DP_OP_499J312_125_1651_n71,
DP_OP_499J312_125_1651_n70, DP_OP_499J312_125_1651_n69,
DP_OP_499J312_125_1651_n68, DP_OP_499J312_125_1651_n67,
DP_OP_499J312_125_1651_n66, DP_OP_499J312_125_1651_n65,
DP_OP_499J312_125_1651_n64, DP_OP_499J312_125_1651_n63,
DP_OP_499J312_125_1651_n62, DP_OP_499J312_125_1651_n61,
DP_OP_499J312_125_1651_n60, DP_OP_499J312_125_1651_n59,
DP_OP_499J312_125_1651_n58, DP_OP_499J312_125_1651_n57,
DP_OP_499J312_125_1651_n56, DP_OP_499J312_125_1651_n55,
DP_OP_499J312_125_1651_n54, DP_OP_499J312_125_1651_n53,
DP_OP_499J312_125_1651_n52, DP_OP_499J312_125_1651_n51,
DP_OP_499J312_125_1651_n50, DP_OP_499J312_125_1651_n49,
DP_OP_499J312_125_1651_n48, DP_OP_499J312_125_1651_n47,
DP_OP_499J312_125_1651_n46, DP_OP_499J312_125_1651_n45,
DP_OP_499J312_125_1651_n44, DP_OP_499J312_125_1651_n43,
DP_OP_499J312_125_1651_n42, DP_OP_499J312_125_1651_n41,
DP_OP_499J312_125_1651_n40, DP_OP_499J312_125_1651_n39,
DP_OP_499J312_125_1651_n38, DP_OP_499J312_125_1651_n37,
DP_OP_499J312_125_1651_n36, DP_OP_499J312_125_1651_n35,
DP_OP_499J312_125_1651_n34, DP_OP_499J312_125_1651_n33,
DP_OP_499J312_125_1651_n32, DP_OP_499J312_125_1651_n31,
DP_OP_499J312_125_1651_n30, DP_OP_496J312_122_3540_n1017,
DP_OP_496J312_122_3540_n1016, DP_OP_496J312_122_3540_n1015,
DP_OP_496J312_122_3540_n1014, DP_OP_496J312_122_3540_n1013,
DP_OP_496J312_122_3540_n1012, DP_OP_496J312_122_3540_n1011,
DP_OP_496J312_122_3540_n1010, DP_OP_496J312_122_3540_n1009,
DP_OP_496J312_122_3540_n1008, DP_OP_496J312_122_3540_n1007,
DP_OP_496J312_122_3540_n1006, DP_OP_496J312_122_3540_n1004,
DP_OP_496J312_122_3540_n833, DP_OP_496J312_122_3540_n832,
DP_OP_496J312_122_3540_n831, DP_OP_496J312_122_3540_n830,
DP_OP_496J312_122_3540_n829, DP_OP_496J312_122_3540_n828,
DP_OP_496J312_122_3540_n827, DP_OP_496J312_122_3540_n826,
DP_OP_496J312_122_3540_n825, DP_OP_496J312_122_3540_n824,
DP_OP_496J312_122_3540_n823, DP_OP_496J312_122_3540_n822,
DP_OP_496J312_122_3540_n821, DP_OP_496J312_122_3540_n820,
DP_OP_496J312_122_3540_n819, DP_OP_496J312_122_3540_n686,
DP_OP_496J312_122_3540_n683, DP_OP_496J312_122_3540_n575,
DP_OP_496J312_122_3540_n574, DP_OP_496J312_122_3540_n573,
DP_OP_496J312_122_3540_n572, DP_OP_496J312_122_3540_n571,
DP_OP_496J312_122_3540_n570, DP_OP_496J312_122_3540_n569,
DP_OP_496J312_122_3540_n568, DP_OP_496J312_122_3540_n567,
DP_OP_496J312_122_3540_n566, DP_OP_496J312_122_3540_n565,
DP_OP_496J312_122_3540_n564, DP_OP_496J312_122_3540_n563,
DP_OP_496J312_122_3540_n562, DP_OP_496J312_122_3540_n557,
DP_OP_496J312_122_3540_n556, DP_OP_496J312_122_3540_n555,
DP_OP_496J312_122_3540_n554, DP_OP_496J312_122_3540_n553,
DP_OP_496J312_122_3540_n552, DP_OP_496J312_122_3540_n551,
DP_OP_496J312_122_3540_n550, DP_OP_496J312_122_3540_n549,
DP_OP_496J312_122_3540_n548, DP_OP_496J312_122_3540_n547,
DP_OP_496J312_122_3540_n546, DP_OP_496J312_122_3540_n545,
DP_OP_496J312_122_3540_n544, DP_OP_496J312_122_3540_n543,
DP_OP_496J312_122_3540_n272, n910, n911, n912, n913, n914, n915, n916,
n917, n918, n919, n921, n922, n923, n925, n926, n927, n928, n929,
n930, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n968, n969, n970, n972, n975, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430,
n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440,
n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450,
n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460,
n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470,
n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480,
n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490,
n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500,
n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510,
n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520,
n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530,
n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540,
n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550,
n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560,
n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570,
n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580,
n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590,
n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600,
n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610,
n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620,
n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630,
n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640,
n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650,
n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660,
n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670,
n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680,
n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690,
n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700,
n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710,
n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720,
n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730,
n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740,
n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2751,
n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842,
n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852,
n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862,
n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872,
n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882,
n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892,
n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902,
n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912,
n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952,
n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212,
n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222,
n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232,
n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242,
n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252,
n3253, n3254, n3255, n3257, n3258, n3259, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3752, n3753, n3755, n3756,
n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765, n3766,
n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775, n3776,
n3777, n3778, n3779, n3780;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] add_subt_data1;
wire [30:0] add_subt_data2;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_mux_sal;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [25:4] FPSENCOS_data_out_LUT;
wire [7:0] FPSENCOS_sh_exp_y;
wire [7:0] FPSENCOS_sh_exp_x;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_first_mux_Z;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_first_mux_Y;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_first_mux_X;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [30:0] FPMULT_Op_MY;
wire [30:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:23] FPMULT_P_Sgf;
wire [31:0] FPADDSUB_formatted_number_W;
wire [25:1] FPADDSUB_Raw_mant_SGF;
wire [25:2] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [51:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] FPADDSUB_LZD_raw_out_EWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [27:0] FPADDSUB_DmP_INIT_EWSW;
wire [30:0] FPADDSUB_DMP_INIT_EWSW;
wire [28:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_next;
wire [3:1] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:23] FPMULT_Sgf_operation_Result;
wire [24:1] FPMULT_Adder_M_result_A_adder;
wire [22:0] FPMULT_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] FPMULT_final_result_ieee_Module_Exp_S_mux;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
wire [11:8] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [13:7] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [11:8] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 FPSENCOS_ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(FPSENCOS_ITER_CONT_net8130676),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function FPMULT_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n846), .ENCLK(FPMULT_FS_Module_net8130622), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n875), .ENCLK(FPADDSUB_inst_ShiftRegister_net8130514),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[1]), .ENCLK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 FPSENCOS_d_ff5_data_out_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff5_data_out), .ENCLK(
FPSENCOS_d_ff5_data_out_net8130640), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[0]), .ENCLK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__19_net_), .ENCLK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[2]), .ENCLK(
FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 FPSENCOS_reg_Z0_clk_gate_Q_reg ( .CLK(
clk), .EN(FPSENCOS_enab_d_ff_RB1), .ENCLK(FPSENCOS_reg_Z0_net8130640),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 FPSENCOS_reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
FPSENCOS_reg_val_muxZ_2stage_net8130640), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 FPSENCOS_reg_shift_y_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_RB3), .ENCLK(
FPSENCOS_reg_shift_y_net8130640), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 FPSENCOS_d_ff4_Xn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Xn), .ENCLK(
FPSENCOS_d_ff4_Xn_net8130640), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 FPSENCOS_d_ff4_Yn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Yn), .ENCLK(
FPSENCOS_d_ff4_Yn_net8130640), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 FPSENCOS_d_ff4_Zn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Zn), .ENCLK(
FPSENCOS_d_ff4_Zn_net8130640), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_enable_Pipeline_input), .ENCLK(
FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_6), .ENCLK(
FPADDSUB_EXP_STAGE_DMP_net8130406), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_5), .ENCLK(
FPADDSUB_SHT1_STAGE_DMP_net8130406), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__6_net_), .ENCLK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 FPMULT_Exp_module_exp_result_m_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_exp_operation_load_result), .ENCLK(
FPMULT_Exp_module_exp_result_m_net8130586), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 FPMULT_Sgf_operation_EVEN1_finalreg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_load_second_step), .ENCLK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 FPMULT_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_barrel_shifter_load), .ENCLK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 FPMULT_Adder_M_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_adder_round_norm_load), .ENCLK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 FPMULT_Operands_load_reg_XMRegister_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_first_phase_load), .ENCLK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 FPMULT_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_final_result_load), .ENCLK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .TE(
1'b0) );
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n917), .Q(
dataA[25]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n2572), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n3711), .Q(
dataA[27]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n3712), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n3733), .Q(
dataB[23]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n3733), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n3733), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n3733), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n3733), .Q(
dataB[28]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n3733), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n3733), .Q(
dataB[31]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n3756), .CK(
FPADDSUB_inst_ShiftRegister_net8130514), .RN(n3673), .Q(
FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
FPADDSUB_inst_ShiftRegister_net8130514), .RN(n3678), .Q(
FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
FPADDSUB_inst_ShiftRegister_net8130514), .RN(n3687), .Q(
FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
FPADDSUB_inst_ShiftRegister_net8130514), .RN(n3661), .Q(
FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3673), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3678), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3687), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3687), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3678), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(region_flag[1]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3731), .QN(n936) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n852), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3731), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n862), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3731), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n856), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3731), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n864), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3731), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(FPSENCOS_data_out_LUT[4]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3731), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n853), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3731), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n855), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3731), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n859), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3731), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n3511), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3731), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n861), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3708), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n854), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3708), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n860), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n851), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n863), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n865), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n850), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n849), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n848), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(FPSENCOS_data_out_LUT[25]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n857), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3733), .Q(FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3733), .Q(FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3727), .Q(FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n824), .Q(FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3721), .Q(FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n824), .Q(FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n824), .Q(FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n824), .Q(FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n824), .Q(FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(Data_1[10]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n917), .Q(FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(Data_1[11]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3712), .Q(FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(Data_1[12]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3718), .Q(FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(Data_1[13]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3714), .Q(FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(Data_1[14]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(Data_1[15]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(Data_1[16]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(Data_1[17]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(Data_1[18]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(Data_1[19]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(Data_1[20]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(Data_1[21]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(Data_1[22]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(Data_1[23]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(Data_1[24]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(Data_1[25]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(Data_1[26]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3728), .Q(FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(Data_1[27]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3728), .Q(FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(Data_1[28]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3728), .Q(FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(Data_1[29]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3728), .Q(FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(Data_1[30]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3728), .Q(FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(Data_1[31]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3728), .Q(FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(FPSENCOS_sh_exp_x[0]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3728), .Q(
FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(FPSENCOS_sh_exp_x[1]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3728), .Q(
FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(FPSENCOS_sh_exp_x[2]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3728), .Q(
FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(FPSENCOS_sh_exp_x[3]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3707), .Q(
FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(FPSENCOS_sh_exp_x[4]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3706), .Q(
FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(FPSENCOS_sh_exp_x[5]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3707), .Q(
FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(FPSENCOS_sh_exp_x[6]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3727), .Q(
FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(FPSENCOS_sh_exp_x[7]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3727), .Q(
FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(FPSENCOS_sh_exp_y[0]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3727), .Q(
FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(FPSENCOS_sh_exp_y[1]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3727), .Q(
FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(FPSENCOS_sh_exp_y[2]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3727), .Q(
FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(FPSENCOS_sh_exp_y[3]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3727), .Q(
FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(FPSENCOS_sh_exp_y[4]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3727), .Q(
FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(FPSENCOS_sh_exp_y[5]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3727), .Q(
FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(FPSENCOS_sh_exp_y[6]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3727), .Q(
FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(FPSENCOS_sh_exp_y[7]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3705), .Q(
FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3705), .Q(FPSENCOS_d_ff_Xn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff_Xn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff_Xn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3720), .Q(FPSENCOS_d_ff_Xn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_X[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3725), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3735), .Q(FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(FPSENCOS_mux_sal[23]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3720), .Q(cordic_result[23])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3725), .Q(FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(FPSENCOS_mux_sal[24]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3735), .Q(cordic_result[24])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3720), .Q(FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(FPSENCOS_mux_sal[25]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3725), .Q(cordic_result[25])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3735), .Q(FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(FPSENCOS_mux_sal[26]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3724), .Q(cordic_result[26])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3724), .Q(FPSENCOS_d_ff_Yn[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(FPSENCOS_mux_sal[27]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3724), .Q(cordic_result[27])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3724), .Q(FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(FPSENCOS_mux_sal[28]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3724), .Q(cordic_result[28])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3724), .Q(FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(FPSENCOS_mux_sal[29]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3724), .Q(cordic_result[29])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3735), .Q(FPSENCOS_d_ff_Yn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Y[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3707), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(FPSENCOS_mux_sal[30]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3723), .Q(cordic_result[30])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3706), .Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Z[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3707), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3723), .Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Z[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3706), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3707), .Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Z[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3723), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3706), .Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Z[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3707), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3723), .Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Z[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3706), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3722), .Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Z[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3705), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3722), .Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Z[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3705), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3722), .Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Z[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3705), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(FPADDSUB_DmP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3675), .Q(
FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(FPADDSUB_DmP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3689), .Q(
FPADDSUB_DmP_EXP_EWSW[24]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(FPADDSUB_DmP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3691), .Q(
FPADDSUB_DmP_EXP_EWSW[25]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(FPADDSUB_DmP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3663), .Q(
FPADDSUB_DmP_EXP_EWSW[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(FPADDSUB_DmP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3675), .Q(
FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3674), .Q(
FPADDSUB_DMP_EXP_EWSW[23]), .QN(n989) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3674), .Q(
FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_INIT_EWSW[28]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3661), .Q(
FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_INIT_EWSW[29]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3675), .Q(
FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_INIT_EWSW[30]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_EXP_EWSW[23]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_EXP_EWSW[24]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3674), .Q(
FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_EXP_EWSW[25]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3690), .Q(
FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_EXP_EWSW[26]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3662), .Q(
FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_EXP_EWSW[27]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_EXP_EWSW[28]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3674), .Q(
FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_EXP_EWSW[29]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3665), .Q(
FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_EXP_EWSW[30]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3677), .Q(
FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT1_EWSW[23]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT2_EWSW[23]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3663), .Q(
FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(FPADDSUB_DMP_SFG[23]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3691), .Q(
FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3675), .Q(
FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT1_EWSW[24]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3674), .Q(
FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT2_EWSW[24]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3664), .Q(
FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(FPADDSUB_DMP_SFG[24]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3690), .Q(
FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3664), .Q(
FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT1_EWSW[25]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3665), .Q(
FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT2_EWSW[25]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3690), .Q(
FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(FPADDSUB_DMP_SFG[25]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3664), .Q(
FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3690), .Q(
FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT1_EWSW[26]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3677), .Q(
FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT2_EWSW[26]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3664), .Q(
FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(FPADDSUB_DMP_SFG[26]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3690), .Q(
FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3664), .Q(
FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT1_EWSW[27]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT2_EWSW[27]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3690), .Q(
FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(FPADDSUB_DMP_SFG[27]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3664), .Q(
FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3690), .Q(
FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT1_EWSW[28]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3674), .Q(
FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT2_EWSW[28]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3691), .Q(
FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(FPADDSUB_DMP_SFG[28]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3675), .Q(
FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3689), .Q(
FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT1_EWSW[29]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3665), .Q(
FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT2_EWSW[29]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3675), .Q(
FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(FPADDSUB_DMP_SFG[29]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3689), .Q(
FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3663), .Q(
FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT1_EWSW[30]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3677), .Q(
FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT2_EWSW[30]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3663), .Q(
FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(FPADDSUB_DMP_SFG[30]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3691), .Q(
FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3689), .Q(
FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3722), .Q(FPSENCOS_d_ff_Xn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_X[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3705), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(FPSENCOS_d_ff2_X[22]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3722), .Q(
FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3705), .Q(FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Y[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3722), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(FPSENCOS_d_ff2_Y[22]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3705), .Q(
FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(FPSENCOS_mux_sal[22]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3721), .Q(cordic_result[22])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3721), .Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Z[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3721), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(FPADDSUB_DmP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3687), .Q(
FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_DmP_EXP_EWSW[22]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n3683), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3721), .Q(FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_X[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3721), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(FPSENCOS_d_ff2_X[19]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3721), .Q(
FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3721), .Q(FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Y[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3721), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(FPSENCOS_d_ff2_Y[19]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3721), .Q(
FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(FPSENCOS_mux_sal[19]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3721), .Q(cordic_result[19])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3721), .Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Z[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3721), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(FPADDSUB_DmP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3678), .Q(
FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_DmP_EXP_EWSW[19]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n3674), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(FPADDSUB_Data_array_SWR[2]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3670), .Q(
FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3720), .Q(FPSENCOS_d_ff_Xn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_X[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3725), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(FPSENCOS_d_ff2_X[21]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3735), .Q(
FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3720), .Q(FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Y[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3725), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(FPSENCOS_d_ff2_Y[21]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3735), .Q(
FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(FPSENCOS_mux_sal[21]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3720), .Q(cordic_result[21])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3725), .Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Z[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3735), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(FPADDSUB_DmP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n2571), .Q(
FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_DmP_EXP_EWSW[21]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n2570), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3720), .Q(FPSENCOS_d_ff_Xn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_X[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3725), .Q(
FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(FPSENCOS_d_ff2_X[2]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3735), .Q(
FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n2567), .Q(FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Y[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n2567), .Q(
FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(FPSENCOS_d_ff2_Y[2]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n2567), .Q(
FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(FPSENCOS_mux_sal[2]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n2572), .Q(cordic_result[2])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n2572), .Q(FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Z[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3719), .Q(
FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(FPADDSUB_DmP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3671), .Q(
FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(FPADDSUB_DmP_EXP_EWSW[2]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3672), .Q(
FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3717), .Q(FPSENCOS_d_ff_Xn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_X[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3719), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(FPSENCOS_d_ff2_X[16]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3717), .Q(
FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3719), .Q(FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Y[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3717), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(FPSENCOS_d_ff2_Y[16]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3719), .Q(
FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(FPSENCOS_mux_sal[16]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3718), .Q(cordic_result[16])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3718), .Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Z[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3718), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(FPADDSUB_DmP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3667), .Q(
FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_DmP_EXP_EWSW[16]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n2569), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3718), .Q(FPSENCOS_d_ff_Xn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_X[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3718), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(FPSENCOS_d_ff2_X[18]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3718), .Q(
FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3718), .Q(FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Y[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3718), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(FPSENCOS_d_ff2_Y[18]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3718), .Q(
FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(FPSENCOS_mux_sal[18]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3718), .Q(cordic_result[18])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3718), .Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Z[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3718), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(FPADDSUB_DmP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3668), .Q(
FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_DmP_EXP_EWSW[18]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n3670), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(FPADDSUB_Data_array_SWR[3]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3672), .Q(
FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3717), .Q(FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_X[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3719), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(FPSENCOS_d_ff2_X[20]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3717), .Q(
FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3719), .Q(FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Y[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3717), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(FPSENCOS_d_ff2_Y[20]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3719), .Q(
FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(FPSENCOS_mux_sal[20]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3717), .Q(cordic_result[20])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n2572), .Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Z[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3719), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(FPADDSUB_DmP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3671), .Q(
FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_DmP_EXP_EWSW[20]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n3667), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3717), .Q(FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_X[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n2572), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(FPSENCOS_d_ff2_X[17]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3719), .Q(
FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3716), .Q(FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Y[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3716), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(FPSENCOS_d_ff2_Y[17]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3716), .Q(
FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(FPSENCOS_mux_sal[17]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3716), .Q(cordic_result[17])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3716), .Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Z[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3716), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(FPADDSUB_DmP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n2571), .Q(
FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_DmP_EXP_EWSW[17]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n2570), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3716), .Q(FPSENCOS_d_ff_Xn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_X[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3716), .Q(
FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(FPSENCOS_d_ff2_X[4]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3716), .Q(
FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3716), .Q(FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Y[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3709), .Q(
FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(FPSENCOS_d_ff2_Y[4]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3709), .Q(
FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(FPSENCOS_mux_sal[4]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3715), .Q(cordic_result[4])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3715), .Q(FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Z[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3715), .Q(
FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(FPADDSUB_DmP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3667), .Q(
FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(FPADDSUB_DmP_EXP_EWSW[4]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3671), .Q(
FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3715), .Q(FPSENCOS_d_ff_Xn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_X[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3715), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(FPSENCOS_d_ff2_X[15]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3715), .Q(
FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3715), .Q(FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Y[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3715), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(FPSENCOS_d_ff2_Y[15]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3715), .Q(
FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(FPSENCOS_mux_sal[15]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3715), .Q(cordic_result[15])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3712), .Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Z[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3712), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(FPADDSUB_DmP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n2571), .Q(
FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_DmP_EXP_EWSW[15]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n2570), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3730), .Q(FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_X[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n824), .Q(
FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(FPSENCOS_d_ff2_X[5]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n2567), .Q(
FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n2567), .Q(FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Y[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n2567), .Q(
FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(FPSENCOS_d_ff2_Y[5]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n2567), .Q(
FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(FPSENCOS_mux_sal[5]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3715), .Q(cordic_result[5])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n824), .Q(FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Z[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3728), .Q(
FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(FPADDSUB_DmP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n2571), .Q(
FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(FPADDSUB_DmP_EXP_EWSW[5]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n2570), .Q(
FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3729), .Q(FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_X[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n2572), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(FPSENCOS_d_ff2_X[13]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3719), .Q(
FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3714), .Q(FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Y[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3714), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(FPSENCOS_d_ff2_Y[13]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3714), .Q(
FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(FPSENCOS_mux_sal[13]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3714), .Q(cordic_result[13])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3714), .Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Z[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3714), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(FPADDSUB_DmP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3672), .Q(
FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_DmP_EXP_EWSW[13]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n3671), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3714), .Q(FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_X[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3714), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(FPSENCOS_d_ff2_X[14]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3714), .Q(
FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3714), .Q(FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Y[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3711), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(FPSENCOS_d_ff2_Y[14]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3711), .Q(
FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(FPSENCOS_mux_sal[14]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3713), .Q(cordic_result[14])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3713), .Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Z[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3713), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(FPADDSUB_DmP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3667), .Q(
FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_DmP_EXP_EWSW[14]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n2569), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3713), .Q(FPSENCOS_d_ff_Xn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_X[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3713), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(FPSENCOS_d_ff2_X[11]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3713), .Q(
FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3713), .Q(FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Y[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3713), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(FPSENCOS_d_ff2_Y[11]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3713), .Q(
FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(FPSENCOS_mux_sal[11]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3713), .Q(cordic_result[11])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3710), .Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Z[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3710), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(FPADDSUB_DmP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3669), .Q(
FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_DmP_EXP_EWSW[11]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n3668), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3712), .Q(FPSENCOS_d_ff_Xn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_X[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3712), .Q(
FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(FPSENCOS_d_ff2_X[8]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3712), .Q(
FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3712), .Q(FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Y[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3712), .Q(
FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(FPSENCOS_d_ff2_Y[8]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3712), .Q(
FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(FPSENCOS_mux_sal[8]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3712), .Q(cordic_result[8])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n2567), .Q(FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Z[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3712), .Q(
FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(FPADDSUB_DmP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3665), .Q(
FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(FPADDSUB_DmP_EXP_EWSW[8]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3665), .Q(
FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3717), .Q(FPSENCOS_d_ff_Xn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_X[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3712), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(FPSENCOS_d_ff2_X[10]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3718), .Q(
FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3711), .Q(FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Y[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3711), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(FPSENCOS_d_ff2_Y[10]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3711), .Q(
FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(FPSENCOS_mux_sal[10]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3711), .Q(cordic_result[10])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3711), .Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Z[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3711), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(FPADDSUB_DmP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3673), .Q(
FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_DmP_EXP_EWSW[10]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n3691), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3711), .Q(FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_X[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n917), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(FPSENCOS_d_ff2_X[12]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3711), .Q(
FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n917), .Q(FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Y[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3711), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(FPSENCOS_d_ff2_Y[12]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n917), .Q(
FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(FPSENCOS_mux_sal[12]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3710), .Q(cordic_result[12])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3710), .Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Z[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3710), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(FPADDSUB_DmP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3677), .Q(
FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_DmP_EXP_EWSW[12]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406),
.RN(n3678), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3710), .Q(FPSENCOS_d_ff_Xn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_X[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n917), .Q(
FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(FPSENCOS_d_ff2_X[9]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3710), .Q(
FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n917), .Q(FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Y[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3710), .Q(
FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(FPSENCOS_d_ff2_Y[9]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n917), .Q(
FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(FPSENCOS_mux_sal[9]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3710), .Q(cordic_result[9])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n917), .Q(FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Z[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3710), .Q(
FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3709), .Q(FPSENCOS_d_ff_Xn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_X[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3709), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(FPSENCOS_d_ff2_X[31]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3709), .Q(
FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3709), .Q(FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(FPSENCOS_fmtted_Result_31_),
.CK(FPSENCOS_d_ff5_data_out_net8130640), .RN(n3709), .Q(
cordic_result[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Y[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3709), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(FPSENCOS_d_ff2_Y[31]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3709), .Q(
FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3709), .Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Z[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3709), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(add_subt_data1[31]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3661), .Q(
FPADDSUB_intDX_EWSW[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Z[31]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3709), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n951), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3687), .QN(n937) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(FPADDSUB_Raw_mant_SGF[4]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3677), .QN(n934) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
FPADDSUB_LZD_raw_out_EWR[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3663), .Q(
FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
FPADDSUB_LZD_raw_out_EWR[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3689), .Q(
FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
FPADDSUB_LZD_raw_out_EWR[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3691), .Q(
FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
FPADDSUB_LZD_raw_out_EWR[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3675), .Q(
FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
FPADDSUB_LZD_raw_out_EWR[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8130424), .RN(n3689), .Q(
FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3709), .Q(FPSENCOS_d_ff_Xn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_X[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3709), .Q(
FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(FPSENCOS_d_ff2_X[0]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3708), .Q(
FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3708), .Q(FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Y[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3708), .Q(
FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Y[0]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3708), .Q(
FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(FPSENCOS_mux_sal[0]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3708), .Q(cordic_result[0])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3708), .Q(FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Z[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3708), .Q(
FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(FPADDSUB_DmP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(FPADDSUB_DmP_EXP_EWSW[0]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3664), .Q(
FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_EXP_EWSW[0]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3687), .Q(
FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT1_EWSW[0]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3663), .Q(
FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3708), .Q(FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_X[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3708), .Q(
FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(FPSENCOS_d_ff2_X[1]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3708), .Q(
FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3708), .Q(FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Y[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3708), .Q(
FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(FPSENCOS_d_ff2_Y[1]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3725), .Q(
FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(FPSENCOS_mux_sal[1]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3723), .Q(cordic_result[1])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3706), .Q(FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Z[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3720), .Q(
FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(FPADDSUB_DmP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3675), .Q(
FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(FPADDSUB_DmP_EXP_EWSW[1]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3675), .Q(
FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3663), .Q(
FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_EXP_EWSW[1]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3679), .Q(
FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT1_EWSW[1]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3679), .Q(
FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3707), .Q(FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_X[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3707), .Q(
FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(FPSENCOS_d_ff2_X[3]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3720), .Q(
FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3706), .Q(FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Y[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3723), .Q(
FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(FPSENCOS_d_ff2_Y[3]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3735), .Q(
FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(FPSENCOS_mux_sal[3]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3723), .Q(cordic_result[3])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3706), .Q(FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Z[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3719), .Q(
FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(FPADDSUB_DmP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3679), .Q(
FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(FPADDSUB_DmP_EXP_EWSW[3]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3679), .Q(
FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3679), .Q(
FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_EXP_EWSW[3]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3685), .Q(
FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT1_EWSW[3]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3675), .Q(
FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3706), .Q(FPSENCOS_d_ff_Xn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_X[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3709), .Q(
FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(FPSENCOS_d_ff2_X[6]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3707), .Q(
FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3710), .Q(FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Y[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3734), .Q(
FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(FPSENCOS_d_ff2_Y[6]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3729), .Q(
FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(FPSENCOS_mux_sal[6]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3721), .Q(cordic_result[6])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3708), .Q(FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Z[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3726), .Q(
FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(FPADDSUB_DmP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3680), .Q(
FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(FPADDSUB_DmP_EXP_EWSW[6]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3685), .Q(
FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_EXP_EWSW[6]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3680), .Q(
FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT1_EWSW[6]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3685), .Q(
FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Xn_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_X[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3711), .Q(
FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(FPSENCOS_d_ff2_X[7]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3725), .Q(
FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Yn_net8130640), .RN(n3706), .Q(FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Y[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3734), .Q(
FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(FPSENCOS_d_ff2_Y[7]), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n3734), .Q(
FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(FPSENCOS_mux_sal[7]), .CK(
FPSENCOS_d_ff5_data_out_net8130640), .RN(n3734), .Q(cordic_result[7])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Zn_net8130640), .RN(n3734), .Q(FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Z[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3734), .Q(
FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(FPADDSUB_DmP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3686), .Q(
FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(FPADDSUB_DmP_EXP_EWSW[7]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3681), .Q(
FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3686), .Q(
FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_EXP_EWSW[7]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3681), .Q(
FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT1_EWSW[7]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3686), .Q(
FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(FPADDSUB_DmP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3681), .Q(
FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(FPADDSUB_DmP_EXP_EWSW[9]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3686), .Q(
FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_EXP_EWSW[9]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT1_EWSW[9]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_EXP_EWSW[12]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT1_EWSW[12]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_EXP_EWSW[10]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT1_EWSW[10]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3679), .Q(
FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_EXP_EWSW[8]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3672), .Q(
FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT1_EWSW[8]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n2651), .Q(
FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3662), .Q(
FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_EXP_EWSW[11]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3671), .Q(
FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT1_EWSW[11]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n2651), .Q(
FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3688), .Q(
FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_EXP_EWSW[14]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3667), .Q(
FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT1_EWSW[14]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n2651), .Q(
FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n964), .Q(
FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_EXP_EWSW[13]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3683), .Q(
FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT1_EWSW[13]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n964), .Q(
FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3683), .Q(
FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_EXP_EWSW[5]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n964), .Q(
FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT1_EWSW[5]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3683), .Q(
FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n964), .Q(
FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_EXP_EWSW[15]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3683), .Q(
FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT1_EWSW[15]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n964), .Q(
FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3673), .Q(
FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_EXP_EWSW[4]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT1_EWSW[4]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3679), .Q(
FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_EXP_EWSW[17]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3661), .Q(
FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT1_EWSW[17]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3685), .Q(
FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3666), .Q(
FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_EXP_EWSW[20]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n2570), .Q(
FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT1_EWSW[20]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3686), .Q(
FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_EXP_EWSW[18]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3685), .Q(
FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT1_EWSW[18]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n964), .Q(
FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3680), .Q(
FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_EXP_EWSW[16]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT1_EWSW[16]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n2570), .Q(
FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3681), .Q(
FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_EXP_EWSW[2]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3666), .Q(
FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT1_EWSW[2]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n2569), .Q(
FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_EXP_EWSW[21]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3685), .Q(
FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT1_EWSW[21]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3686), .Q(
FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n964), .Q(
FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_EXP_EWSW[19]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3678), .Q(
FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT1_EWSW[19]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3685), .Q(
FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(FPADDSUB_Data_array_SWR[1]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3666), .Q(
FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(FPADDSUB_Data_array_SWR[0]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n2651), .Q(
FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3681), .Q(
FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_EXP_EWSW[22]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3666), .Q(
FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT1_EWSW[22]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8130406), .RN(n3680), .Q(
FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3666), .Q(
FPADDSUB_DmP_mant_SFG_SWR[25]) );
DFFRXLTS FPMULT_FS_Module_state_reg_reg_0_ ( .D(
FPMULT_FS_Module_state_next[0]), .CK(FPMULT_FS_Module_net8130622),
.RN(n3723), .QN(n998) );
DFFRXLTS FPMULT_FS_Module_state_reg_reg_2_ ( .D(
FPMULT_FS_Module_state_next[2]), .CK(FPMULT_FS_Module_net8130622),
.RN(n3707), .Q(FPMULT_FS_Module_state_reg[2]), .QN(n997) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(Data_2[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3704), .Q(
FPMULT_Op_MY[30]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(Data_2[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3704), .Q(
FPMULT_Op_MY[29]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(Data_2[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3704), .Q(
FPMULT_Op_MY[28]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(Data_2[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3695), .Q(
FPMULT_Op_MY[27]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(Data_2[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3704), .Q(
FPMULT_Op_MY[26]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(Data_2[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3701), .Q(
FPMULT_Op_MY[25]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(Data_2[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3699), .Q(
FPMULT_Op_MY[24]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(Data_2[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3697), .Q(
FPMULT_Op_MY[23]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3701), .Q(
FPMULT_Op_MX[6]), .QN(n1021) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3696), .Q(
FPMULT_Op_MX[1]), .QN(n927) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3698), .Q(
FPMULT_Op_MX[0]), .QN(n1002) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n106), .CK(
n3753), .RN(n3698), .QN(n996) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n926), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3697), .Q(
FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(
FPMULT_Sgf_operation_Result[42]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3707), .Q(
FPMULT_P_Sgf[42]), .QN(n981) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(
FPMULT_Sgf_operation_Result[40]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3723), .Q(
FPMULT_P_Sgf[40]), .QN(n983) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(
FPMULT_Sgf_operation_Result[23]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3705), .Q(
FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(
FPMULT_Exp_module_Data_S[8]), .CK(
FPMULT_Exp_module_exp_result_m_net8130586), .RN(n3701), .Q(
FPMULT_exp_oper_result[8]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(
FPMULT_Exp_module_Data_S[7]), .CK(
FPMULT_Exp_module_exp_result_m_net8130586), .RN(n3699), .Q(
FPMULT_exp_oper_result[7]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(
FPMULT_Exp_module_Data_S[6]), .CK(
FPMULT_Exp_module_exp_result_m_net8130586), .RN(n3694), .Q(
FPMULT_exp_oper_result[6]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(
FPMULT_Exp_module_Data_S[5]), .CK(
FPMULT_Exp_module_exp_result_m_net8130586), .RN(n3695), .Q(
FPMULT_exp_oper_result[5]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(
FPMULT_Exp_module_Data_S[4]), .CK(
FPMULT_Exp_module_exp_result_m_net8130586), .RN(n963), .Q(
FPMULT_exp_oper_result[4]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(
FPMULT_Exp_module_Data_S[3]), .CK(
FPMULT_Exp_module_exp_result_m_net8130586), .RN(n3692), .Q(
FPMULT_exp_oper_result[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(
FPMULT_Exp_module_Data_S[2]), .CK(
FPMULT_Exp_module_exp_result_m_net8130586), .RN(n3700), .Q(
FPMULT_exp_oper_result[2]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(
FPMULT_Exp_module_Data_S[1]), .CK(
FPMULT_Exp_module_exp_result_m_net8130586), .RN(n3693), .Q(
FPMULT_exp_oper_result[1]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Data_S[0]), .CK(
FPMULT_Exp_module_exp_result_m_net8130586), .RN(n3697), .Q(
FPMULT_exp_oper_result[0]) );
DFFRXLTS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Overflow_A), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3698), .Q(
FPMULT_Exp_module_Overflow_flag_A) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n3780), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3696), .Q(
FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n3778), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3699), .Q(
FPMULT_Sgf_normalized_result[21]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n3776), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n963), .Q(
FPMULT_Sgf_normalized_result[19]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n3774), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3696), .Q(
FPMULT_Sgf_normalized_result[17]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n3772), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3694), .Q(
FPMULT_Sgf_normalized_result[15]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n3770), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3692), .Q(
FPMULT_Sgf_normalized_result[13]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n3768), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3698), .Q(
FPMULT_Sgf_normalized_result[11]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n3766), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3693), .Q(
FPMULT_Sgf_normalized_result[9]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n3764), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3697), .Q(
FPMULT_Sgf_normalized_result[7]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n3762), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3696), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n3760), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3698), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3699), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3700), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3693), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3697), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3698), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3696), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3701), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3699), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3694), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n963), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3692), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3695), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3700), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n963), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3692), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3695), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3700), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3693), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3697), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3696), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3698), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3701), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3699), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3694), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3695), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3704), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3704), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3704), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3704), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3704), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3704), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
FPMULT_final_result_ieee_Module_Sign_S_mux), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8130352), .RN(
n3704), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n3748), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3691), .Q(
underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n3749), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3663), .Q(
overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n3747), .CK(
FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3678), .Q(
FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_EXP),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3666), .Q(
FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n819), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3686), .Q(
FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_SHT2),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3673), .Q(
FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_SIGN_FLAG_SFG),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3680), .Q(
FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n816), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3674), .Q(
FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n30), .CK(
FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_EXP), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n813), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3674), .Q(
FPADDSUB_OP_FLAG_SHT2) );
SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_FPMULT_Exp_module_Underflow_m_Q_reg (
.CLK(clk), .EN(n107), .ENCLK(n3753), .TE(1'b0) );
CMPR32X2TS DP_OP_26J312_126_1325_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n911), .C(DP_OP_26J312_126_1325_n18), .CO(DP_OP_26J312_126_1325_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J312_126_1325_U8 ( .A(DP_OP_26J312_126_1325_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J312_126_1325_n8), .CO(
DP_OP_26J312_126_1325_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J312_126_1325_U7 ( .A(DP_OP_26J312_126_1325_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J312_126_1325_n7), .CO(
DP_OP_26J312_126_1325_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J312_126_1325_U6 ( .A(DP_OP_26J312_126_1325_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J312_126_1325_n6), .CO(
DP_OP_26J312_126_1325_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_234J312_129_4955_U2 ( .A(n2536), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J312_129_4955_n2), .CO(DP_OP_234J312_129_4955_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_1050_U4 ( .A(FPADDSUB_DmP_EXP_EWSW[24]), .B(n3631), .C(
intadd_1050_CI), .CO(intadd_1050_n3), .S(intadd_1050_SUM_0_) );
CMPR32X2TS intadd_1050_U3 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n3630), .C(
intadd_1050_n3), .CO(intadd_1050_n2), .S(intadd_1050_SUM_1_) );
CMPR32X2TS intadd_1050_U2 ( .A(FPADDSUB_DmP_EXP_EWSW[26]), .B(n3645), .C(
intadd_1050_n2), .CO(intadd_1050_n1), .S(intadd_1050_SUM_2_) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(
FPSENCOS_reg_shift_y_net8130640), .RN(n2567), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(FPADDSUB_N59), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3664), .Q(
FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n3646) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_X[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff2_X[28]), .QN(n3644) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Y[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3724), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n3643) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(add_subt_data2[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3664), .Q(
FPADDSUB_intDY_EWSW[0]), .QN(n3641) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(add_subt_data2[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3691), .Q(
FPADDSUB_intDY_EWSW[26]), .QN(n3639) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(add_subt_data2[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3673), .Q(
FPADDSUB_intDY_EWSW[1]), .QN(n3638) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(add_subt_data2[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3672), .Q(
FPADDSUB_intDY_EWSW[18]), .QN(n3637) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(add_subt_data2[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3665), .Q(
FPADDSUB_intDY_EWSW[8]), .QN(n3636) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(add_subt_data2[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3675), .Q(
FPADDSUB_intDY_EWSW[25]), .QN(n3635) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(add_subt_data2[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3668), .Q(
FPADDSUB_intDY_EWSW[17]), .QN(n3634) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(add_subt_data2[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n2571), .Q(
FPADDSUB_intDY_EWSW[11]), .QN(n3632) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(add_subt_data2[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3670), .Q(
FPADDSUB_intDY_EWSW[20]), .QN(n3627) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(add_subt_data2[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3671), .Q(
FPADDSUB_intDY_EWSW[21]), .QN(n3626) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(add_subt_data2[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3663), .Q(
FPADDSUB_intDY_EWSW[27]), .QN(n3625) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(add_subt_data2[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3669), .Q(
FPADDSUB_intDY_EWSW[9]), .QN(n3624) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(add_subt_data2[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3663), .Q(
FPADDSUB_intDY_EWSW[24]), .QN(n3623) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(add_subt_data2[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n2569), .Q(
FPADDSUB_intDY_EWSW[2]), .QN(n3622) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(add_subt_data2[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3668), .Q(
FPADDSUB_intDY_EWSW[13]), .QN(n3621) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(add_subt_data2[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n2569), .Q(
FPADDSUB_intDY_EWSW[4]), .QN(n3620) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(add_subt_data2[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3671), .Q(
FPADDSUB_intDY_EWSW[16]), .QN(n3619) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(add_subt_data2[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3680), .Q(
FPADDSUB_intDY_EWSW[6]), .QN(n3618) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(add_subt_data2[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3676), .Q(
FPADDSUB_intDY_EWSW[10]), .QN(n3617) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(add_subt_data1[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3691), .Q(
FPADDSUB_intDX_EWSW[12]), .QN(n3616) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT2_EWSW[22]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3680), .Q(
FPADDSUB_DMP_SFG[22]), .QN(n3613) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(add_subt_data1[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3675), .Q(
FPADDSUB_intDX_EWSW[22]), .QN(n3610) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(FPADDSUB_Data_array_SWR[25]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3678), .Q(
FPADDSUB_Data_array_SWR[51]), .QN(n3609) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(add_subt_data1[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3672), .Q(
FPADDSUB_intDX_EWSW[14]), .QN(n3608) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3669), .Q(
FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n3607) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT2_EWSW[20]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3666), .Q(
FPADDSUB_DMP_SFG[20]), .QN(n3606) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n3756), .CK(
clk), .RN(n3687), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]),
.QN(n3605) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n834), .CK(FPMULT_FS_Module_net8130622),
.RN(n3692), .Q(FPMULT_FSM_selector_C), .QN(n3604) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(add_subt_data1[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3668), .QN(n3603)
);
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n3661), .Q(ready_add_subt), .QN(n3602) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(FPADDSUB_Data_array_SWR[23]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3661), .Q(
FPADDSUB_Data_array_SWR[49]), .QN(n3599) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(add_subt_data2[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3689), .Q(
FPADDSUB_intDY_EWSW[28]), .QN(n3597) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3666), .Q(
FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n3596) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(add_subt_data1[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3679), .Q(
FPADDSUB_intDX_EWSW[3]), .QN(n3595) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(add_subt_data1[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3669), .Q(
FPADDSUB_intDX_EWSW[20]), .QN(n3594) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(add_subt_data1[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3667), .Q(
FPADDSUB_intDX_EWSW[18]), .QN(n3593) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(add_subt_data1[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3665), .Q(
FPADDSUB_intDX_EWSW[8]), .QN(n3591) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(add_subt_data1[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3662), .Q(
FPADDSUB_intDX_EWSW[25]), .QN(n3589) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(add_subt_data1[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n2571), .Q(
FPADDSUB_intDX_EWSW[17]), .QN(n3588) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(add_subt_data1[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3674), .Q(
FPADDSUB_intDX_EWSW[1]), .QN(n3587) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(add_subt_data1[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3669), .Q(
FPADDSUB_intDX_EWSW[15]), .QN(n3586) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(add_subt_data1[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3666), .Q(
FPADDSUB_intDX_EWSW[19]), .QN(n3585) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(add_subt_data1[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n2570), .Q(
FPADDSUB_intDX_EWSW[11]), .QN(n3582) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[2]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3677), .Q(
FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n3581) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT2_EWSW[18]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3686), .Q(
FPADDSUB_DMP_SFG[18]), .QN(n3580) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT2_EWSW[17]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3666), .Q(
FPADDSUB_DMP_SFG[17]), .QN(n3579) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(add_subt_data1[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3662), .Q(
FPADDSUB_intDX_EWSW[28]), .QN(n3578) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT2_EWSW[16]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_SFG[16]), .QN(n3576) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
FPADDSUB_Raw_mant_SGF[12]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3676), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n3575) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n3574) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT2_EWSW[14]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n2569), .Q(
FPADDSUB_DMP_SFG[14]), .QN(n3573) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n3732), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n3571) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
FPADDSUB_Raw_mant_SGF[20]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3669), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n3570) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
FPADDSUB_Raw_mant_SGF[18]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3687), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n3568) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
FPADDSUB_Raw_mant_SGF[14]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3663), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n3567) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[15]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3683), .Q(
FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n3564) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT2_EWSW[12]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_SFG[12]), .QN(n3563) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
FPADDSUB_Raw_mant_SGF[17]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3673), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n3562) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(FPADDSUB_Raw_mant_SGF[1]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3674), .Q(
FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n3561) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT2_EWSW[10]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_SFG[10]), .QN(n3560) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[13]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n3559) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(FPADDSUB_Raw_mant_SGF[3]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3677), .Q(
FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n3558) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT2_EWSW[9]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3682), .Q(
FPADDSUB_DMP_SFG[9]), .QN(n3557) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(FPADDSUB_Raw_mant_SGF[6]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3674), .Q(
FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n3555) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT2_EWSW[8]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n2571), .Q(
FPADDSUB_DMP_SFG[8]), .QN(n3554) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3669), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n3553) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT2_EWSW[6]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3681), .Q(
FPADDSUB_DMP_SFG[6]), .QN(n3552) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3684), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n3551) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3670), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n3550) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT2_EWSW[4]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3687), .Q(
FPADDSUB_DMP_SFG[4]), .QN(n3549) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT2_EWSW[2]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3661), .Q(
FPADDSUB_DMP_SFG[2]), .QN(n3548) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT2_EWSW[0]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3664), .Q(
FPADDSUB_DMP_SFG[0]), .QN(n3547) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3681), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n3546) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(add_subt_data2[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3663), .Q(
FPADDSUB_intDY_EWSW[22]), .QN(n3544) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(add_subt_data2[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n964), .Q(
FPADDSUB_intDY_EWSW[19]), .QN(n3543) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(FPADDSUB_Data_array_SWR[24]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3674), .Q(
FPADDSUB_Data_array_SWR[50]), .QN(n3542) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(add_subt_data2[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3670), .Q(
FPADDSUB_intDY_EWSW[14]), .QN(n3541) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(add_subt_data1[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3662), .Q(
FPADDSUB_intDX_EWSW[23]), .QN(n3540) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT2_EWSW[21]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DMP_SFG[21]), .QN(n3539) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(
FPMULT_FS_Module_state_next[3]), .CK(FPMULT_FS_Module_net8130622),
.RN(n3707), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n3537) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT2_EWSW[19]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3680), .Q(
FPADDSUB_DMP_SFG[19]), .QN(n3536) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(add_subt_data1[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3662), .Q(
FPADDSUB_intDX_EWSW[24]), .QN(n3535) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(add_subt_data1[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3677), .Q(
FPADDSUB_intDX_EWSW[0]), .QN(n3533) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(add_subt_data1[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3667), .Q(
FPADDSUB_intDX_EWSW[21]), .QN(n3532) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(add_subt_data1[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3662), .Q(
FPADDSUB_intDX_EWSW[26]), .QN(n3531) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(add_subt_data1[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3686), .QN(n3530)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(add_subt_data1[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3662), .Q(
FPADDSUB_intDX_EWSW[27]), .QN(n3529) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(add_subt_data1[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3678), .Q(
FPADDSUB_intDX_EWSW[9]), .QN(n3528) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(add_subt_data1[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3672), .Q(
FPADDSUB_intDX_EWSW[2]), .QN(n3527) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(add_subt_data1[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3670), .Q(
FPADDSUB_intDX_EWSW[13]), .QN(n3525) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3681), .Q(
FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n3524) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT2_EWSW[15]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3680), .Q(
FPADDSUB_DMP_SFG[15]), .QN(n3523) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
FPADDSUB_Raw_mant_SGF[22]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3673), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n3521) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT2_EWSW[13]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n964), .Q(
FPADDSUB_DMP_SFG[13]), .QN(n3520) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT2_EWSW[11]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n964), .Q(
FPADDSUB_DMP_SFG[11]), .QN(n3518) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[11]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3685), .Q(
FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n3517) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT2_EWSW[7]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3686), .Q(
FPADDSUB_DMP_SFG[7]), .QN(n3516) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT2_EWSW[5]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3683), .Q(
FPADDSUB_DMP_SFG[5]), .QN(n3515) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT2_EWSW[3]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_DMP_SFG[3]), .QN(n3514) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT2_EWSW[1]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3679), .Q(
FPADDSUB_DMP_SFG[1]), .QN(n3513) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n3733), .Q(NaN_flag)
);
CMPR32X2TS DP_OP_234J312_129_4955_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n2536), .C(DP_OP_234J312_129_4955_n22), .CO(DP_OP_234J312_129_4955_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J312_129_4955_U9 ( .A(DP_OP_234J312_129_4955_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J312_129_4955_n9), .CO(
DP_OP_234J312_129_4955_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J312_129_4955_U8 ( .A(DP_OP_234J312_129_4955_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J312_129_4955_n8), .CO(
DP_OP_234J312_129_4955_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J312_129_4955_U7 ( .A(DP_OP_234J312_129_4955_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J312_129_4955_n7), .CO(
DP_OP_234J312_129_4955_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J312_129_4955_U6 ( .A(DP_OP_234J312_129_4955_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J312_129_4955_n6), .CO(
DP_OP_234J312_129_4955_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J312_129_4955_U5 ( .A(DP_OP_234J312_129_4955_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J312_129_4955_n5), .CO(
DP_OP_234J312_129_4955_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J312_129_4955_U4 ( .A(DP_OP_234J312_129_4955_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J312_129_4955_n4), .CO(
DP_OP_234J312_129_4955_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_26J312_126_1325_U5 ( .A(DP_OP_26J312_126_1325_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J312_126_1325_n5), .CO(
DP_OP_26J312_126_1325_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J312_126_1325_U4 ( .A(n911), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J312_126_1325_n4), .CO(
DP_OP_26J312_126_1325_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J312_126_1325_U3 ( .A(n911), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J312_126_1325_n3), .CO(
DP_OP_26J312_126_1325_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_234J312_129_4955_U3 ( .A(DP_OP_234J312_129_4955_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J312_129_4955_n3), .CO(
DP_OP_234J312_129_4955_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR42X1TS DP_OP_497J312_123_1725_U251 ( .A(DP_OP_497J312_123_1725_n358),
.B(DP_OP_497J312_123_1725_n331), .C(DP_OP_497J312_123_1725_n328), .D(
DP_OP_497J312_123_1725_n327), .ICI(DP_OP_497J312_123_1725_n325), .S(
DP_OP_497J312_123_1725_n323), .ICO(DP_OP_497J312_123_1725_n321), .CO(
DP_OP_497J312_123_1725_n322) );
CMPR42X1TS DP_OP_497J312_123_1725_U248 ( .A(DP_OP_497J312_123_1725_n326),
.B(DP_OP_497J312_123_1725_n320), .C(DP_OP_497J312_123_1725_n324), .D(
DP_OP_497J312_123_1725_n318), .ICI(DP_OP_497J312_123_1725_n321), .S(
DP_OP_497J312_123_1725_n316), .ICO(DP_OP_497J312_123_1725_n314), .CO(
DP_OP_497J312_123_1725_n315) );
CMPR42X1TS DP_OP_497J312_123_1725_U246 ( .A(DP_OP_497J312_123_1725_n351),
.B(DP_OP_497J312_123_1725_n319), .C(DP_OP_497J312_123_1725_n313), .D(
DP_OP_497J312_123_1725_n317), .ICI(DP_OP_497J312_123_1725_n314), .S(
DP_OP_497J312_123_1725_n311), .ICO(DP_OP_497J312_123_1725_n309), .CO(
DP_OP_497J312_123_1725_n310) );
CMPR42X1TS DP_OP_497J312_123_1725_U245 ( .A(n976), .B(FPMULT_Op_MY[21]), .C(
DP_OP_497J312_123_1725_n345), .D(DP_OP_497J312_123_1725_n312), .ICI(
DP_OP_497J312_123_1725_n309), .S(DP_OP_497J312_123_1725_n308), .ICO(
DP_OP_497J312_123_1725_n306), .CO(DP_OP_497J312_123_1725_n307) );
CMPR42X1TS DP_OP_497J312_123_1725_U180 ( .A(DP_OP_497J312_123_1725_n279),
.B(DP_OP_497J312_123_1725_n269), .C(DP_OP_497J312_123_1725_n274), .D(
DP_OP_497J312_123_1725_n244), .ICI(DP_OP_497J312_123_1725_n241), .S(
DP_OP_497J312_123_1725_n239), .ICO(DP_OP_497J312_123_1725_n237), .CO(
DP_OP_497J312_123_1725_n238) );
CMPR42X1TS DP_OP_497J312_123_1725_U177 ( .A(DP_OP_497J312_123_1725_n273),
.B(DP_OP_497J312_123_1725_n240), .C(DP_OP_497J312_123_1725_n237), .D(
DP_OP_497J312_123_1725_n236), .ICI(DP_OP_497J312_123_1725_n234), .S(
DP_OP_497J312_123_1725_n232), .ICO(DP_OP_497J312_123_1725_n230), .CO(
DP_OP_497J312_123_1725_n231) );
CMPR42X1TS DP_OP_497J312_123_1725_U174 ( .A(DP_OP_497J312_123_1725_n235),
.B(DP_OP_497J312_123_1725_n233), .C(DP_OP_497J312_123_1725_n229), .D(
DP_OP_497J312_123_1725_n227), .ICI(DP_OP_497J312_123_1725_n230), .S(
DP_OP_497J312_123_1725_n225), .ICO(DP_OP_497J312_123_1725_n223), .CO(
DP_OP_497J312_123_1725_n224) );
CMPR42X1TS DP_OP_497J312_123_1725_U172 ( .A(DP_OP_497J312_123_1725_n261),
.B(DP_OP_497J312_123_1725_n228), .C(DP_OP_497J312_123_1725_n226), .D(
DP_OP_497J312_123_1725_n222), .ICI(DP_OP_497J312_123_1725_n223), .S(
DP_OP_497J312_123_1725_n220), .ICO(DP_OP_497J312_123_1725_n218), .CO(
DP_OP_497J312_123_1725_n219) );
CMPR42X1TS DP_OP_497J312_123_1725_U171 ( .A(DP_OP_497J312_123_1725_n260),
.B(DP_OP_497J312_123_1725_n250), .C(DP_OP_497J312_123_1725_n255), .D(
DP_OP_497J312_123_1725_n221), .ICI(DP_OP_497J312_123_1725_n218), .S(
DP_OP_497J312_123_1725_n217), .ICO(DP_OP_497J312_123_1725_n215), .CO(
DP_OP_497J312_123_1725_n216) );
CMPR42X1TS DP_OP_497J312_123_1725_U39 ( .A(DP_OP_497J312_123_1725_n202), .B(
n1273), .C(DP_OP_497J312_123_1725_n201), .D(
DP_OP_497J312_123_1725_n118), .ICI(DP_OP_497J312_123_1725_n125), .S(
DP_OP_497J312_123_1725_n75), .ICO(DP_OP_497J312_123_1725_n73), .CO(
DP_OP_497J312_123_1725_n74) );
CMPR42X1TS DP_OP_497J312_123_1725_U37 ( .A(DP_OP_497J312_123_1725_n86), .B(
DP_OP_497J312_123_1725_n124), .C(DP_OP_497J312_123_1725_n72), .D(
DP_OP_497J312_123_1725_n117), .ICI(DP_OP_497J312_123_1725_n91), .S(
DP_OP_497J312_123_1725_n70), .ICO(DP_OP_497J312_123_1725_n68), .CO(
DP_OP_497J312_123_1725_n69) );
CMPR42X1TS DP_OP_497J312_123_1725_U28 ( .A(DP_OP_497J312_123_1725_n99), .B(
DP_OP_497J312_123_1725_n106), .C(DP_OP_497J312_123_1725_n54), .D(
DP_OP_497J312_123_1725_n50), .ICI(DP_OP_497J312_123_1725_n49), .S(
DP_OP_497J312_123_1725_n46), .ICO(DP_OP_497J312_123_1725_n44), .CO(
DP_OP_497J312_123_1725_n45) );
CMPR42X1TS DP_OP_497J312_123_1725_U27 ( .A(n980), .B(
DP_OP_497J312_123_1725_n112), .C(DP_OP_497J312_123_1725_n98), .D(
DP_OP_497J312_123_1725_n105), .ICI(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .S(
DP_OP_497J312_123_1725_n43), .ICO(DP_OP_497J312_123_1725_n41), .CO(
DP_OP_497J312_123_1725_n42) );
CMPR42X1TS DP_OP_497J312_123_1725_U24 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(
DP_OP_497J312_123_1725_n80), .C(DP_OP_497J312_123_1725_n42), .D(
DP_OP_497J312_123_1725_n38), .ICI(DP_OP_497J312_123_1725_n37), .S(
DP_OP_497J312_123_1725_n34), .ICO(DP_OP_497J312_123_1725_n32), .CO(
DP_OP_497J312_123_1725_n33) );
CMPR42X1TS DP_OP_497J312_123_1725_U23 ( .A(DP_OP_497J312_123_1725_n110), .B(
DP_OP_497J312_123_1725_n96), .C(DP_OP_497J312_123_1725_n103), .D(
DP_OP_497J312_123_1725_n35), .ICI(DP_OP_497J312_123_1725_n194), .S(
DP_OP_497J312_123_1725_n31), .ICO(DP_OP_497J312_123_1725_n29), .CO(
DP_OP_497J312_123_1725_n30) );
CMPR42X1TS DP_OP_498J312_124_1725_U244 ( .A(DP_OP_498J312_124_1725_n351),
.B(DP_OP_498J312_124_1725_n341), .C(DP_OP_498J312_124_1725_n346), .D(
DP_OP_498J312_124_1725_n312), .ICI(DP_OP_498J312_124_1725_n309), .S(
DP_OP_498J312_124_1725_n308), .ICO(DP_OP_498J312_124_1725_n306), .CO(
DP_OP_498J312_124_1725_n307) );
CMPR42X1TS DP_OP_498J312_124_1725_U174 ( .A(DP_OP_498J312_124_1725_n235),
.B(DP_OP_498J312_124_1725_n233), .C(DP_OP_498J312_124_1725_n229), .D(
DP_OP_498J312_124_1725_n227), .ICI(DP_OP_498J312_124_1725_n230), .S(
DP_OP_498J312_124_1725_n225), .ICO(DP_OP_498J312_124_1725_n223), .CO(
DP_OP_498J312_124_1725_n224) );
CMPR42X1TS DP_OP_498J312_124_1725_U172 ( .A(DP_OP_498J312_124_1725_n261),
.B(DP_OP_498J312_124_1725_n228), .C(DP_OP_498J312_124_1725_n226), .D(
DP_OP_498J312_124_1725_n222), .ICI(DP_OP_498J312_124_1725_n223), .S(
DP_OP_498J312_124_1725_n220), .ICO(DP_OP_498J312_124_1725_n218), .CO(
DP_OP_498J312_124_1725_n219) );
CMPR42X1TS DP_OP_498J312_124_1725_U171 ( .A(DP_OP_498J312_124_1725_n260),
.B(DP_OP_498J312_124_1725_n250), .C(DP_OP_498J312_124_1725_n255), .D(
DP_OP_498J312_124_1725_n221), .ICI(DP_OP_498J312_124_1725_n218), .S(
DP_OP_498J312_124_1725_n217), .ICO(DP_OP_498J312_124_1725_n215), .CO(
DP_OP_498J312_124_1725_n216) );
CMPR42X1TS DP_OP_498J312_124_1725_U27 ( .A(DP_OP_498J312_124_1725_n119), .B(
DP_OP_498J312_124_1725_n112), .C(DP_OP_498J312_124_1725_n105), .D(
DP_OP_498J312_124_1725_n98), .ICI(DP_OP_498J312_124_1725_n47), .S(
DP_OP_498J312_124_1725_n43), .ICO(DP_OP_498J312_124_1725_n41), .CO(
DP_OP_498J312_124_1725_n42) );
CMPR42X1TS DP_OP_498J312_124_1725_U25 ( .A(DP_OP_498J312_124_1725_n111), .B(
DP_OP_498J312_124_1725_n104), .C(DP_OP_498J312_124_1725_n97), .D(
DP_OP_498J312_124_1725_n41), .ICI(DP_OP_498J312_124_1725_n195), .S(
DP_OP_498J312_124_1725_n37), .ICO(DP_OP_498J312_124_1725_n35), .CO(
DP_OP_498J312_124_1725_n36) );
CMPR42X1TS DP_OP_498J312_124_1725_U24 ( .A(DP_OP_498J312_124_1725_n42), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .C(
DP_OP_498J312_124_1725_n80), .D(DP_OP_498J312_124_1725_n38), .ICI(
DP_OP_498J312_124_1725_n37), .S(DP_OP_498J312_124_1725_n34), .ICO(
DP_OP_498J312_124_1725_n32), .CO(DP_OP_498J312_124_1725_n33) );
CMPR42X1TS DP_OP_498J312_124_1725_U23 ( .A(DP_OP_498J312_124_1725_n110), .B(
DP_OP_498J312_124_1725_n103), .C(DP_OP_498J312_124_1725_n96), .D(
DP_OP_498J312_124_1725_n35), .ICI(DP_OP_498J312_124_1725_n194), .S(
DP_OP_498J312_124_1725_n31), .ICO(DP_OP_498J312_124_1725_n29), .CO(
DP_OP_498J312_124_1725_n30) );
CMPR42X1TS DP_OP_498J312_124_1725_U20 ( .A(DP_OP_498J312_124_1725_n25), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .C(
DP_OP_498J312_124_1725_n78), .D(DP_OP_498J312_124_1725_n30), .ICI(
DP_OP_498J312_124_1725_n26), .S(DP_OP_498J312_124_1725_n23), .ICO(
DP_OP_498J312_124_1725_n21), .CO(DP_OP_498J312_124_1725_n22) );
CMPR42X1TS DP_OP_498J312_124_1725_U19 ( .A(DP_OP_498J312_124_1725_n94), .B(
DP_OP_498J312_124_1725_n101), .C(DP_OP_498J312_124_1725_n24), .D(
DP_OP_498J312_124_1725_n192), .ICI(DP_OP_498J312_124_1725_n21), .S(
DP_OP_498J312_124_1725_n20), .ICO(DP_OP_498J312_124_1725_n18), .CO(
DP_OP_498J312_124_1725_n19) );
AFCSHCINX2TS DP_OP_496J312_122_3540_U747 ( .CI1N(DP_OP_496J312_122_3540_n831), .B(DP_OP_496J312_122_3540_n1014), .A(DP_OP_496J312_122_3540_n1015), .CI0N(
DP_OP_496J312_122_3540_n832), .CS(DP_OP_496J312_122_3540_n833), .CO1(
DP_OP_496J312_122_3540_n829), .CO0(DP_OP_496J312_122_3540_n830), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
AFCSIHCONX2TS DP_OP_496J312_122_3540_U745 ( .A(DP_OP_496J312_122_3540_n1013),
.B(DP_OP_496J312_122_3540_n1012), .CS(DP_OP_496J312_122_3540_n828),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]),
.CO0N(DP_OP_496J312_122_3540_n827), .CO1N(DP_OP_496J312_122_3540_n826)
);
AFCSHCINX2TS DP_OP_496J312_122_3540_U744 ( .CI1N(DP_OP_496J312_122_3540_n826), .B(DP_OP_496J312_122_3540_n1010), .A(DP_OP_496J312_122_3540_n1011), .CI0N(
DP_OP_496J312_122_3540_n827), .CS(DP_OP_496J312_122_3540_n828), .CO1(
DP_OP_496J312_122_3540_n824), .CO0(DP_OP_496J312_122_3540_n825), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]) );
AFCSHCONX2TS DP_OP_496J312_122_3540_U743 ( .B(DP_OP_496J312_122_3540_n1008),
.A(DP_OP_496J312_122_3540_n1009), .CI0(DP_OP_496J312_122_3540_n825),
.CI1(DP_OP_496J312_122_3540_n824), .CS(DP_OP_496J312_122_3540_n828),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]),
.CO0N(DP_OP_496J312_122_3540_n823), .CO1N(DP_OP_496J312_122_3540_n822)
);
AFCSIHCONX2TS DP_OP_496J312_122_3540_U741 ( .A(DP_OP_496J312_122_3540_n1007),
.B(DP_OP_496J312_122_3540_n1006), .CS(DP_OP_496J312_122_3540_n821),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]),
.CO0N(DP_OP_496J312_122_3540_n820), .CO1N(DP_OP_496J312_122_3540_n819)
);
AFCSHCINX2TS DP_OP_496J312_122_3540_U740 ( .CI1N(DP_OP_496J312_122_3540_n819), .B(DP_OP_496J312_122_3540_n1004), .A(DP_OP_496J312_122_3540_n272), .CI0N(
DP_OP_496J312_122_3540_n820), .CS(DP_OP_496J312_122_3540_n821), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]) );
AFCSIHCONX2TS DP_OP_496J312_122_3540_U498 ( .A(DP_OP_496J312_122_3540_n575),
.B(DP_OP_496J312_122_3540_n574), .CS(DP_OP_496J312_122_3540_n557), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .CO0N(
DP_OP_496J312_122_3540_n556), .CO1N(DP_OP_496J312_122_3540_n555) );
AFCSHCINX2TS DP_OP_496J312_122_3540_U497 ( .CI1N(DP_OP_496J312_122_3540_n555), .B(DP_OP_496J312_122_3540_n572), .A(DP_OP_496J312_122_3540_n573), .CI0N(
DP_OP_496J312_122_3540_n556), .CS(DP_OP_496J312_122_3540_n557), .CO1(
DP_OP_496J312_122_3540_n553), .CO0(DP_OP_496J312_122_3540_n554), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
AFCSIHCONX2TS DP_OP_496J312_122_3540_U495 ( .A(DP_OP_496J312_122_3540_n571),
.B(DP_OP_496J312_122_3540_n570), .CS(DP_OP_496J312_122_3540_n552), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .CO0N(
DP_OP_496J312_122_3540_n551), .CO1N(DP_OP_496J312_122_3540_n550) );
AFCSHCINX2TS DP_OP_496J312_122_3540_U494 ( .CI1N(DP_OP_496J312_122_3540_n550), .B(DP_OP_496J312_122_3540_n568), .A(DP_OP_496J312_122_3540_n569), .CI0N(
DP_OP_496J312_122_3540_n551), .CS(DP_OP_496J312_122_3540_n552), .CO1(
DP_OP_496J312_122_3540_n548), .CO0(DP_OP_496J312_122_3540_n549), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
AFCSHCONX2TS DP_OP_496J312_122_3540_U493 ( .B(DP_OP_496J312_122_3540_n566),
.A(DP_OP_496J312_122_3540_n567), .CI0(DP_OP_496J312_122_3540_n549),
.CI1(DP_OP_496J312_122_3540_n548), .CS(DP_OP_496J312_122_3540_n552),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .CO0N(
DP_OP_496J312_122_3540_n547), .CO1N(DP_OP_496J312_122_3540_n546) );
AFCSIHCONX2TS DP_OP_496J312_122_3540_U491 ( .A(DP_OP_496J312_122_3540_n564),
.B(DP_OP_496J312_122_3540_n565), .CS(DP_OP_496J312_122_3540_n545), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .CO0N(
DP_OP_496J312_122_3540_n544), .CO1N(DP_OP_496J312_122_3540_n543) );
AFCSHCINX2TS DP_OP_496J312_122_3540_U490 ( .CI1N(DP_OP_496J312_122_3540_n543), .B(DP_OP_496J312_122_3540_n562), .A(DP_OP_496J312_122_3540_n563), .CI0N(
DP_OP_496J312_122_3540_n544), .CS(DP_OP_496J312_122_3540_n545), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3694), .Q(
FPMULT_Op_MX[7]), .QN(n1018) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(Data_2[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3692), .Q(
FPMULT_Op_MY[20]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(Data_2[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3699), .Q(
FPMULT_Op_MY[21]) );
CMPR42X2TS DP_OP_499J312_125_1651_U44 ( .A(DP_OP_499J312_125_1651_n108), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .D(
DP_OP_499J312_125_1651_n75), .ICI(DP_OP_499J312_125_1651_n76), .S(
DP_OP_499J312_125_1651_n74), .ICO(DP_OP_499J312_125_1651_n72), .CO(
DP_OP_499J312_125_1651_n73) );
DFFSXLTS R_11 ( .D(n3654), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .SN(n963), .Q(n3744),
.QN(n3629) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(Data_2[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3694), .Q(
FPMULT_Op_MY[6]), .QN(DP_OP_498J312_124_1725_n379) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(Data_2[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n963), .Q(
FPMULT_Op_MY[10]), .QN(DP_OP_496J312_122_3540_n683) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(Data_2[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3694), .Q(
FPMULT_Op_MY[9]), .QN(DP_OP_498J312_124_1725_n376) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(Data_2[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3693), .Q(
FPMULT_Op_MY[8]), .QN(DP_OP_498J312_124_1725_n377) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(Data_2[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3699), .Q(
FPMULT_Op_MY[5]), .QN(DP_OP_498J312_124_1725_n283) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(Data_2[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3701), .Q(
FPMULT_Op_MY[7]), .QN(DP_OP_498J312_124_1725_n378) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3699), .Q(
FPMULT_Op_MX[5]), .QN(DP_OP_498J312_124_1725_n289) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3698), .Q(
FPMULT_Op_MX[9]), .QN(DP_OP_498J312_124_1725_n382) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(Data_1[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3698), .Q(
FPMULT_Op_MX[17]), .QN(n3509) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(Data_1[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3696), .Q(
FPMULT_Op_MX[14]), .QN(n3510) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(Data_1[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3701), .Q(
FPMULT_Op_MX[10]), .QN(DP_OP_498J312_124_1725_n381) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3680), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n3519), .CK(
FPSENCOS_ITER_CONT_net8130676), .RN(n3732), .Q(
FPSENCOS_cont_iter_out[0]), .QN(n3519) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
FPADDSUB_inst_ShiftRegister_net8130514), .RN(n3673), .Q(busy), .QN(
n3648) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(FPSENCOS_ITER_CONT_N4), .CK(
FPSENCOS_ITER_CONT_net8130676), .RN(n3732), .Q(
FPSENCOS_cont_iter_out[2]), .QN(n3511) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(FPSENCOS_ITER_CONT_N5), .CK(
FPSENCOS_ITER_CONT_net8130676), .RN(n3732), .Q(
FPSENCOS_cont_iter_out[3]), .QN(n3512) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n829), .CK(FPMULT_FS_Module_net8130622),
.RN(n963), .Q(FPMULT_FSM_selector_B[1]), .QN(n3566) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(FPADDSUB_Raw_mant_SGF[5]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3678), .Q(
FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n3611) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n843), .CK(clk), .RN(n3733), .Q(
FPSENCOS_cont_var_out[0]), .QN(n3522) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(
FPMULT_FS_Module_state_next[1]), .CK(FPMULT_FS_Module_net8130622),
.RN(n3706), .Q(FPMULT_FS_Module_state_reg[1]), .QN(n3526) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(add_subt_data1[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3672), .Q(
FPADDSUB_intDX_EWSW[4]), .QN(n3534) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(add_subt_data1[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3663), .Q(
FPADDSUB_intDX_EWSW[16]), .QN(n3592) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(add_subt_data1[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3677), .Q(
FPADDSUB_intDX_EWSW[10]), .QN(n3583) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(add_subt_data1[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3674), .Q(
FPADDSUB_intDX_EWSW[6]), .QN(n3590) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(add_subt_data2[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3668), .Q(
FPADDSUB_intDY_EWSW[5]), .QN(n3615) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(add_subt_data2[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3679), .Q(
FPADDSUB_intDY_EWSW[3]), .QN(n3640) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(add_subt_data2[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3662), .Q(
FPADDSUB_intDY_EWSW[23]), .QN(n3642) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(add_subt_data2[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3674), .Q(
FPADDSUB_intDY_EWSW[12]), .QN(n3584) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(add_subt_data2[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3667), .Q(
FPADDSUB_intDY_EWSW[15]), .QN(n3633) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(add_subt_data2[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3681), .Q(
FPADDSUB_intDY_EWSW[7]), .QN(n3614) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
FPADDSUB_inst_ShiftRegister_net8130514), .RN(n3691), .Q(
FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n3556) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(
FPADDSUB_Raw_mant_SGF[25]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3687), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n3569) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(Data_2[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3696), .Q(
FPMULT_Op_MY[0]), .QN(n1001) );
DFFRX1TS R_19 ( .D(n3650), .CK(clk), .RN(n3710), .Q(n3738) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(add_subt_data2[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3689), .QN(n3660)
);
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(
FPMULT_Sgf_operation_Result[47]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3735), .Q(
FPMULT_P_Sgf[47]), .QN(n3545) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(Data_1[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3704), .Q(
FPMULT_Op_MX[13]), .QN(n1026) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(Data_1[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3693), .Q(
FPMULT_Op_MX[12]), .QN(n1024) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(Data_2[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3697), .Q(
FPMULT_Op_MY[4]), .QN(n1016) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(Data_2[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3698), .Q(
FPMULT_Op_MY[12]), .QN(n1012) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(Data_2[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3696), .Q(
FPMULT_Op_MY[14]), .QN(n1009) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(Data_2[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3697), .Q(
FPMULT_Op_MY[16]), .QN(n1008) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(Data_1[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3697), .Q(
FPMULT_Op_MX[11]), .QN(n1007) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(Data_2[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3700), .Q(
FPMULT_Op_MY[15]), .QN(n1006) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3700), .Q(
FPMULT_Op_MX[3]), .QN(n1005) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3697), .Q(
FPMULT_Op_MX[4]), .QN(n1004) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(Data_2[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3700), .Q(
FPMULT_Op_MY[3]), .QN(n999) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3692), .Q(
FPMULT_Op_MX[8]), .QN(n995) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(Data_2[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3692), .Q(
FPMULT_Op_MY[1]), .QN(n993) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n963), .Q(
FPMULT_Op_MX[2]), .QN(n991) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(Data_2[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3692), .Q(
FPMULT_Op_MY[13]), .QN(n990) );
DFFRX4TS FPMULT_Sel_A_Q_reg_0_ ( .D(1'b1), .CK(n3753), .RN(n3697), .Q(
FPMULT_FSM_selector_A) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(Data_1[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3693), .Q(
FPMULT_Op_MX[22]) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n842), .CK(clk), .RN(n3733), .Q(
FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
FPADDSUB_Raw_mant_SGF[11]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3690), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
FPADDSUB_Raw_mant_SGF[23]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3673), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3687), .Q(
FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3688), .Q(
FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n3732), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3681), .Q(
FPADDSUB_DmP_mant_SFG_SWR[22]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3666), .Q(
FPADDSUB_DmP_mant_SFG_SWR[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3685), .Q(
FPADDSUB_DmP_mant_SFG_SWR[18]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
FPADDSUB_Raw_mant_SGF[24]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3664), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
FPADDSUB_Raw_mant_SGF[21]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3690), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3678), .Q(
FPADDSUB_DmP_mant_SFG_SWR[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[14]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3686), .Q(
FPADDSUB_DmP_mant_SFG_SWR[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[12]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3684), .Q(
FPADDSUB_DmP_mant_SFG_SWR[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[10]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3688), .Q(
FPADDSUB_DmP_mant_SFG_SWR[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n964), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3683), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3684), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n844), .CK(clk), .RN(n3678), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
FPADDSUB_Raw_mant_SGF[16]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n2571), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
FPADDSUB_Raw_mant_SGF[10]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3661), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(Data_1[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3699), .Q(
FPMULT_Op_MX[19]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(FPADDSUB_Data_array_SWR[17]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3680), .Q(
FPADDSUB_Data_array_SWR[43]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(FPADDSUB_Data_array_SWR[16]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3671), .Q(
FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(FPADDSUB_Raw_mant_SGF[7]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n2570), .Q(
FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
FPADDSUB_Raw_mant_SGF[19]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3665), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(FPADDSUB_Data_array_SWR[18]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3671), .Q(
FPADDSUB_Data_array_SWR[44]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(FPADDSUB_Data_array_SWR[19]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n2570), .Q(
FPADDSUB_Data_array_SWR[45]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(FPADDSUB_Raw_mant_SGF[8]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3676), .Q(
FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(add_subt_data1[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3662), .Q(
FPADDSUB_intDX_EWSW[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(add_subt_data1[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3662), .Q(
FPADDSUB_intDX_EWSW[30]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Y[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3724), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n3732), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_X[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(Data_2[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3695), .Q(
FPMULT_Op_MY[17]), .QN(n933) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(Data_1[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3695), .Q(
FPMULT_Op_MX[15]), .QN(n921) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
FPADDSUB_formatted_number_W[7]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3681), .Q(
result_add_subt[7]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
FPADDSUB_formatted_number_W[6]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3685), .Q(
result_add_subt[6]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
FPADDSUB_formatted_number_W[3]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3679), .Q(
result_add_subt[3]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
FPADDSUB_formatted_number_W[1]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3661), .Q(
result_add_subt[1]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
FPADDSUB_formatted_number_W[0]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3675), .Q(
result_add_subt[0]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
FPADDSUB_formatted_number_W[31]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3676), .Q(
result_add_subt[31]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
FPADDSUB_formatted_number_W[9]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3665), .Q(
result_add_subt[9]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
FPADDSUB_formatted_number_W[12]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3687), .Q(
result_add_subt[12]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
FPADDSUB_formatted_number_W[10]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3690), .Q(
result_add_subt[10]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
FPADDSUB_formatted_number_W[8]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3687), .Q(
result_add_subt[8]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
FPADDSUB_formatted_number_W[11]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3667), .Q(
result_add_subt[11]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
FPADDSUB_formatted_number_W[14]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3671), .Q(
result_add_subt[14]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
FPADDSUB_formatted_number_W[13]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n2571), .Q(
result_add_subt[13]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
FPADDSUB_formatted_number_W[5]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n2570), .Q(
result_add_subt[5]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
FPADDSUB_formatted_number_W[15]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3668), .Q(
result_add_subt[15]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
FPADDSUB_formatted_number_W[4]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3670), .Q(
result_add_subt[4]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
FPADDSUB_formatted_number_W[17]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3687), .Q(
result_add_subt[17]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
FPADDSUB_formatted_number_W[20]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3678), .Q(
result_add_subt[20]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
FPADDSUB_formatted_number_W[18]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3667), .Q(
result_add_subt[18]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
FPADDSUB_formatted_number_W[16]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n2569), .Q(
result_add_subt[16]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
FPADDSUB_formatted_number_W[2]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3669), .Q(
result_add_subt[2]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
FPADDSUB_formatted_number_W[21]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3668), .Q(
result_add_subt[21]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
FPADDSUB_formatted_number_W[19]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3670), .Q(
result_add_subt[19]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
FPADDSUB_formatted_number_W[22]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3685), .Q(
result_add_subt[22]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
FPADDSUB_formatted_number_W[30]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3691), .Q(
result_add_subt[30]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
FPADDSUB_formatted_number_W[29]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3688), .Q(
result_add_subt[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
FPADDSUB_formatted_number_W[28]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3688), .Q(
result_add_subt[28]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
FPADDSUB_formatted_number_W[27]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3688), .Q(
result_add_subt[27]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
FPADDSUB_formatted_number_W[26]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3688), .Q(
result_add_subt[26]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
FPADDSUB_formatted_number_W[25]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3688), .Q(
result_add_subt[25]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
FPADDSUB_formatted_number_W[24]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3688), .Q(
result_add_subt[24]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
FPADDSUB_formatted_number_W[23]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8130352), .RN(n3688), .Q(
result_add_subt[23]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(Data_1[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3695), .Q(
FPMULT_Op_MX[16]), .QN(n922) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(FPADDSUB_Data_array_SWR[9]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n2569), .Q(
FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n3755), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3730), .Q(
FPSENCOS_d_ff1_operation_out) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(FPADDSUB_Data_array_SWR[8]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3683), .Q(
FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(FPADDSUB_Data_array_SWR[11]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3677), .Q(
FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(FPADDSUB_Data_array_SWR[10]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3678), .Q(
FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n3759), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3693), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n3761), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3699), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Y[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3724), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_X[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n3763), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3701), .Q(
FPMULT_Sgf_normalized_result[6]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n3765), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3698), .Q(
FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n3767), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3696), .Q(
FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n3771), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n963), .Q(
FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n3773), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3692), .Q(
FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n3775), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3697), .Q(
FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n3777), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3693), .Q(
FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n3779), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3704), .Q(
FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(n953), .CK(clk), .RN(n3710), .Q(
operation_reg[0]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n3710),
.Q(operation_reg[1]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n3769), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3700), .Q(
FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[1]), .CK(
FPADDSUB_inst_ShiftRegister_net8130514), .RN(n3673), .Q(
FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(FPSENCOS_ITER_CONT_N3), .CK(
FPSENCOS_ITER_CONT_net8130676), .RN(n3732), .Q(
FPSENCOS_cont_iter_out[1]), .QN(n3565) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(Data_2[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n963), .Q(
FPMULT_Op_MY[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Y[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3735), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_X[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Y[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3724), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Y[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3735), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_X[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_X[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3726), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n3733), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n824), .Q(
dataA[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(
FPMULT_Sgf_operation_Result[45]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3707), .Q(
FPMULT_P_Sgf[45]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(
FPMULT_Sgf_operation_Result[24]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3722), .Q(
FPMULT_P_Sgf[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(
FPMULT_Sgf_operation_Result[26]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3705), .Q(
FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(
FPMULT_Sgf_operation_Result[28]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3722), .Q(
FPMULT_P_Sgf[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(
FPMULT_Sgf_operation_Result[30]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3705), .Q(
FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(
FPMULT_Sgf_operation_Result[32]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3705), .Q(
FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(
FPMULT_Sgf_operation_Result[34]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3705), .Q(
FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(
FPMULT_Sgf_operation_Result[36]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3706), .Q(
FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(
FPMULT_Sgf_operation_Result[38]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3725), .Q(
FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(
FPMULT_Adder_M_result_A_adder[1]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3694), .Q(
FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(
FPMULT_Adder_M_result_A_adder[3]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3693), .Q(
FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(
FPMULT_Adder_M_result_A_adder[5]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3699), .Q(
FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(
FPMULT_Adder_M_result_A_adder[7]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3701), .Q(
FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(
FPMULT_Adder_M_result_A_adder[9]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3694), .Q(
FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(
FPMULT_Adder_M_result_A_adder[11]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3699), .Q(
FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(
FPMULT_Adder_M_result_A_adder[13]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3701), .Q(
FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(
FPMULT_Adder_M_result_A_adder[15]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3698), .Q(
FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(
FPMULT_Adder_M_result_A_adder[17]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3696), .Q(
FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(
FPMULT_Adder_M_result_A_adder[19]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3697), .Q(
FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(
FPMULT_Adder_M_result_A_adder[21]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n963), .Q(
FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(
FPMULT_Adder_M_result_A_adder[23]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3700), .Q(
FPMULT_Add_result[23]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
FPADDSUB_Raw_mant_SGF[13]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3675), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n3733), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(FPADDSUB_Raw_mant_SGF[2]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3665), .Q(
FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(FPADDSUB_Data_array_SWR[13]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3669), .Q(
FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(FPADDSUB_Data_array_SWR[12]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n2569), .Q(
FPADDSUB_Data_array_SWR[38]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(FPADDSUB_Data_array_SWR[14]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3689), .Q(
FPADDSUB_Data_array_SWR[40]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(Data_1[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3701), .QN(
n918) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(FPADDSUB_Data_array_SWR[15]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3672), .Q(
FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
FPADDSUB_Raw_mant_SGF[15]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3661), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(FPADDSUB_Raw_mant_SGF[9]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3690), .Q(
FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n3732), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3677), .Q(
FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n3577) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(Data_2[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3695), .Q(
FPMULT_Op_MY[18]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n874), .CK(clk), .RN(n3678), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n3732), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .QN(n1035) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(region_flag[0]), .CK(
FPSENCOS_reg_Z0_net8130640), .RN(n3732), .Q(
FPSENCOS_d_ff1_shift_region_flag_out_0_), .QN(n1036) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(Data_1[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3695), .Q(
FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n3757), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3695), .Q(
FPMULT_Sgf_normalized_result[0]), .QN(n926) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(Data_1[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3693), .Q(
FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(Data_1[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3694), .Q(
FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(Data_1[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n963), .Q(
FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(Data_1[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3695), .Q(
FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(Data_1[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3692), .Q(
FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(Data_1[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3700), .Q(
FPMULT_Op_MX[23]) );
DFFRX1TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n3750), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8130388), .RN(n3676), .Q(
FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n3758), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8130550), .RN(n3701), .Q(
FPMULT_Sgf_normalized_result[1]), .QN(n938) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n3732), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(Data_1[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3696), .Q(
FPMULT_Op_MX[29]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(FPADDSUB_Data_array_SWR[6]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3672), .Q(
FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(
FPMULT_Adder_M_result_A_adder[22]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3701), .Q(
FPMULT_Add_result[22]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n3710), .Q(
dataA[30]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(FPADDSUB_Data_array_SWR[5]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3669), .Q(
FPADDSUB_Data_array_SWR[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(FPADDSUB_Data_array_SWR[7]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3670), .Q(
FPADDSUB_Data_array_SWR[33]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(FPADDSUB_Data_array_SWR[4]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3687), .Q(
FPADDSUB_Data_array_SWR[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(
FPMULT_Adder_M_result_A_adder[20]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3694), .Q(
FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(
FPMULT_Adder_M_result_A_adder[18]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n963), .Q(
FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(
FPMULT_Adder_M_result_A_adder[16]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3692), .Q(
FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(
FPMULT_Adder_M_result_A_adder[14]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3695), .Q(
FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(
FPMULT_Adder_M_result_A_adder[12]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3700), .Q(
FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(
FPMULT_Adder_M_result_A_adder[10]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3693), .Q(
FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(
FPMULT_Adder_M_result_A_adder[8]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3694), .Q(
FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(
FPMULT_Adder_M_result_A_adder[6]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n963), .Q(
FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(
FPMULT_Adder_M_result_A_adder[4]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3692), .Q(
FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(
FPMULT_Adder_M_result_A_adder[2]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3700), .Q(
FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(
FPMULT_Sgf_operation_Result[37]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3735), .Q(
FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(
FPMULT_Sgf_operation_Result[35]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3706), .Q(
FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(
FPMULT_Sgf_operation_Result[33]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3722), .Q(
FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(
FPMULT_Sgf_operation_Result[31]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3705), .Q(
FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(
FPMULT_Sgf_operation_Result[29]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3722), .Q(
FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(
FPMULT_Sgf_operation_Result[27]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3705), .Q(
FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(
FPMULT_Sgf_operation_Result[25]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3722), .Q(
FPMULT_P_Sgf[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n3729), .Q(
dataA[28]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n3717), .Q(
dataA[23]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n3733), .Q(
dataB[24]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n3711), .Q(
dataA[24]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(Data_2[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3700), .Q(
FPMULT_Op_MY[2]), .QN(n923) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n917), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFSX1TS R_1 ( .D(n3658), .CK(clk), .SN(n3712), .Q(n3740) );
DFFSX1TS R_2 ( .D(n3657), .CK(clk), .SN(n917), .Q(n3741) );
DFFSX1TS R_3 ( .D(n3656), .CK(clk), .SN(n3712), .Q(n3736) );
DFFSXLTS R_12 ( .D(n3653), .CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352),
.SN(n3661), .Q(n3746) );
DFFSXLTS R_13 ( .D(n3652), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .SN(n2567), .Q(n3743)
);
DFFSX1TS R_18 ( .D(n3651), .CK(clk), .SN(n3711), .Q(n3739) );
DFFSXLTS R_20 ( .D(n3649), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .SN(n2567), .Q(n3742)
);
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_X[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3727), .Q(FPSENCOS_d_ff2_X[23]), .QN(n3601) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Y[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8130640), .RN(n3735), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n3600) );
DFFSX1TS R_4 ( .D(n3655), .CK(clk), .SN(n3716), .Q(n3737) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n830), .CK(FPMULT_FS_Module_net8130622),
.RN(n3694), .Q(FPMULT_FSM_selector_B[0]), .QN(n3572) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3663), .Q(
FPADDSUB_DMP_EXP_EWSW[24]), .QN(n3631) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3665), .Q(
FPADDSUB_DMP_EXP_EWSW[26]), .QN(n3645) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8130406), .RN(n3676), .Q(
FPADDSUB_DMP_EXP_EWSW[25]), .QN(n3630) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(add_subt_data2[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8130352), .RN(n3663), .QN(n3659)
);
DFFRXLTS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n3752), .CK(n3753),
.RN(n3698), .Q(underflow_flag_mult), .QN(n3647) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(
FPMULT_Adder_M_result_A_adder[24]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8130532), .RN(n3696), .Q(
FPMULT_FSM_add_overflow_flag), .QN(n3628) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(FPADDSUB_Data_array_SWR[20]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3668), .Q(
FPADDSUB_Data_array_SWR[46]), .QN(n3612) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(FPADDSUB_Data_array_SWR[22]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3689), .Q(
FPADDSUB_Data_array_SWR[48]), .QN(n3598) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(FPADDSUB_Data_array_SWR[21]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3669), .Q(
FPADDSUB_Data_array_SWR[47]), .QN(n3538) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(
FPMULT_Sgf_operation_Result[44]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3725), .Q(
FPMULT_P_Sgf[44]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(
FPMULT_Sgf_operation_Result[43]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3707), .Q(
FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(
FPMULT_Sgf_operation_Result[41]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3720), .Q(
FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(
FPMULT_Sgf_operation_Result[39]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3706), .Q(
FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(
FPMULT_Sgf_operation_Result[46]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8130568), .RN(n3723), .Q(
FPMULT_P_Sgf[46]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3683), .Q(FPADDSUB_N60) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3683), .Q(FPADDSUB_N59) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(Data_1[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3699), .Q(
n913) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(Data_1[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3701), .Q(
n912) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(Data_2[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8130604), .RN(n3693), .Q(
n914) );
DFFSX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n3745), .CK(
FPMULT_Operands_load_reg_XMRegister_net8130604), .SN(n3694), .Q(
DP_OP_496J312_122_3540_n686), .QN(FPMULT_Op_MY[11]) );
CMPR42X1TS DP_OP_497J312_123_1725_U32 ( .A(DP_OP_497J312_123_1725_n62), .B(
DP_OP_497J312_123_1725_n122), .C(DP_OP_497J312_123_1725_n60), .D(
DP_OP_497J312_123_1725_n64), .ICI(DP_OP_497J312_123_1725_n108), .S(
DP_OP_497J312_123_1725_n58), .ICO(DP_OP_497J312_123_1725_n56), .CO(
DP_OP_497J312_123_1725_n57) );
CMPR42X1TS DP_OP_499J312_125_1651_U45 ( .A(DP_OP_499J312_125_1651_n109), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .C(
DP_OP_499J312_125_1651_n80), .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .ICI(
DP_OP_499J312_125_1651_n78), .S(DP_OP_499J312_125_1651_n77), .ICO(
DP_OP_499J312_125_1651_n75), .CO(DP_OP_499J312_125_1651_n76) );
CMPR42X1TS DP_OP_497J312_123_1725_U22 ( .A(DP_OP_497J312_123_1725_n36), .B(
DP_OP_497J312_123_1725_n79), .C(DP_OP_497J312_123_1725_n32), .D(
DP_OP_497J312_123_1725_n31), .ICI(DP_OP_497J312_123_1725_n193), .S(
DP_OP_497J312_123_1725_n28), .ICO(DP_OP_497J312_123_1725_n26), .CO(
DP_OP_497J312_123_1725_n27) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n810), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3675), .Q(
FPADDSUB_ADD_OVRFLW_NRM2), .QN(n911) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n3702), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8130388), .RN(n3689), .Q(
FPADDSUB_left_right_SHT2), .QN(n925) );
CMPR32X2TS intadd_1049_U4 ( .A(n3565), .B(FPSENCOS_d_ff2_Y[24]), .C(
intadd_1049_CI), .CO(intadd_1049_n3), .S(FPSENCOS_sh_exp_y[1]) );
CMPR32X2TS intadd_1048_U4 ( .A(n3565), .B(FPSENCOS_d_ff2_X[24]), .C(
intadd_1048_CI), .CO(intadd_1048_n3), .S(FPSENCOS_sh_exp_x[1]) );
CMPR32X2TS DP_OP_26J312_126_1325_U2 ( .A(n911), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J312_126_1325_n2), .CO(
DP_OP_26J312_126_1325_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX4TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_SHT2), .CK(
FPADDSUB_SGF_STAGE_DMP_net8130406), .RN(n3688), .Q(n910), .QN(n3703)
);
CMPR32X2TS intadd_1048_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n3511), .C(
intadd_1048_n3), .CO(intadd_1048_n2), .S(FPSENCOS_sh_exp_x[2]) );
CMPR32X2TS intadd_1049_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n3511), .C(
intadd_1049_n3), .CO(intadd_1049_n2), .S(FPSENCOS_sh_exp_y[2]) );
CMPR32X2TS intadd_1049_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n3512), .C(
intadd_1049_n2), .CO(intadd_1049_n1), .S(FPSENCOS_sh_exp_y[3]) );
CMPR32X2TS intadd_1048_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n3512), .C(
intadd_1048_n2), .CO(intadd_1048_n1), .S(FPSENCOS_sh_exp_x[3]) );
AOI221X4TS U1399 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n3702), .B0(
FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n2883), .C0(n2901), .Y(n3280) );
NAND2X4TS U1400 ( .A(n965), .B(n3577), .Y(n2592) );
AOI222X4TS U1401 ( .A0(FPADDSUB_DMP_SFG[22]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[24]), .B0(FPADDSUB_DMP_SFG[22]), .B1(n3251),
.C0(FPADDSUB_DmP_mant_SFG_SWR[24]), .C1(n3251), .Y(n3257) );
NAND2X1TS U1402 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n2998), .Y(n2997)
);
BUFX4TS U1403 ( .A(n3455), .Y(n3461) );
BUFX4TS U1404 ( .A(n3425), .Y(n3459) );
BUFX4TS U1405 ( .A(n3425), .Y(n3462) );
BUFX3TS U1406 ( .A(n2873), .Y(n3281) );
INVX2TS U1407 ( .A(n2924), .Y(n945) );
AOI222X4TS U1408 ( .A0(n2901), .A1(FPADDSUB_DmP_mant_SHT1_SW[2]), .B0(n3344),
.B1(FPADDSUB_Raw_mant_NRM_SWR[21]), .C0(n977), .C1(n950), .Y(n2948) );
NOR2X2TS U1409 ( .A(n3417), .B(operation[2]), .Y(n3425) );
CLKBUFX2TS U1410 ( .A(n3407), .Y(n3358) );
NOR2X1TS U1411 ( .A(n1455), .B(n1501), .Y(n1503) );
NAND2X1TS U1412 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n3001), .Y(n3000)
);
AND2X2TS U1413 ( .A(n2885), .B(n2884), .Y(n2886) );
NAND2X2TS U1414 ( .A(n1475), .B(n1474), .Y(n2249) );
NAND2X1TS U1415 ( .A(n2765), .B(operation[2]), .Y(n3472) );
NAND2X1TS U1416 ( .A(n1498), .B(n2240), .Y(n1501) );
NOR2X1TS U1417 ( .A(n3417), .B(n3307), .Y(n3359) );
OR2X2TS U1418 ( .A(n1466), .B(n1465), .Y(n2232) );
NAND2X1TS U1419 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n3004), .Y(n3003)
);
OAI22X1TS U1420 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(n3580), .B0(n2877),
.B1(n2876), .Y(n3240) );
NAND2X1TS U1421 ( .A(n1462), .B(n1461), .Y(n2236) );
NAND2X1TS U1422 ( .A(n1511), .B(n1509), .Y(n1497) );
NAND2X2TS U1423 ( .A(n1466), .B(n1465), .Y(n2231) );
AOI22X1TS U1424 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n3524), .B0(n3236), .B1(
n3235), .Y(n2876) );
NOR2X1TS U1425 ( .A(n1392), .B(n1481), .Y(n1509) );
NAND2X1TS U1426 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n3007), .Y(n3006)
);
OAI22X1TS U1427 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(n3576), .B0(n2816),
.B1(n2815), .Y(n3235) );
NOR2X1TS U1428 ( .A(n1452), .B(n1451), .Y(n2226) );
NAND2X1TS U1429 ( .A(n1452), .B(n1451), .Y(n2227) );
NAND2X1TS U1430 ( .A(n1457), .B(n1456), .Y(n2222) );
NAND2X1TS U1431 ( .A(n1484), .B(n1483), .Y(n1481) );
OR2X2TS U1432 ( .A(DP_OP_499J312_125_1651_n31), .B(n1439), .Y(n1437) );
AOI22X1TS U1433 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n3574), .B0(n3231), .B1(
n3230), .Y(n2815) );
NAND2X1TS U1434 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n3010), .Y(n3009)
);
ADDHX1TS U1435 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .B(
DP_OP_499J312_125_1651_n30), .CO(n1443), .S(n1439) );
OAI22X1TS U1436 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1(n3573), .B0(n2809),
.B1(n2808), .Y(n3230) );
NAND2X1TS U1437 ( .A(n2966), .B(n3558), .Y(n2986) );
AOI22X1TS U1438 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n3564), .B0(n3226), .B1(
n3225), .Y(n2808) );
INVX2TS U1439 ( .A(n1504), .Y(n1460) );
CLKINVX1TS U1440 ( .A(n2255), .Y(DP_OP_499J312_125_1651_n94) );
NOR2X1TS U1441 ( .A(n2134), .B(n1029), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
NAND2X1TS U1442 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n3013), .Y(n3012)
);
INVX2TS U1443 ( .A(n1496), .Y(n1455) );
AND2X2TS U1444 ( .A(n2133), .B(n2132), .Y(n1029) );
NAND2X1TS U1445 ( .A(n2983), .B(n3555), .Y(n2969) );
OAI21X2TS U1446 ( .A0(n2135), .A1(n2116), .B0(n2115), .Y(n2134) );
CMPR22X2TS U1447 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(n1428),
.CO(n1426), .S(n1504) );
AOI22X1TS U1448 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n3559), .B0(n2797), .B1(
n2796), .Y(n2802) );
CLKMX2X2TS U1449 ( .A(DP_OP_496J312_122_3540_n554), .B(
DP_OP_496J312_122_3540_n553), .S0(DP_OP_496J312_122_3540_n557), .Y(
DP_OP_496J312_122_3540_n552) );
NAND2XLTS U1450 ( .A(n2146), .B(n2114), .Y(n2116) );
NAND2X1TS U1451 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n3016), .Y(n3015)
);
AOI21X1TS U1452 ( .A0(n2145), .A1(n2114), .B0(n2113), .Y(n2115) );
OAI22X1TS U1453 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(n3560), .B0(n2792),
.B1(n2791), .Y(n2796) );
INVX2TS U1454 ( .A(n1479), .Y(n1447) );
NOR2X1TS U1455 ( .A(n2147), .B(n2140), .Y(n2114) );
NAND2X1TS U1456 ( .A(n2980), .B(n2538), .Y(n2548) );
AOI21X1TS U1457 ( .A0(n2162), .A1(n2146), .B0(n2145), .Y(n2151) );
CMPR32X2TS U1458 ( .A(DP_OP_499J312_125_1651_n53), .B(n1392), .C(n1391),
.CO(n1434), .S(n1516) );
CMPR32X2TS U1459 ( .A(n1433), .B(n2448), .C(n1432), .CO(n1431), .S(n1479) );
NAND2X1TS U1460 ( .A(n2112), .B(n2111), .Y(n2141) );
NAND2X1TS U1461 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n3019), .Y(n3018)
);
CMPR32X2TS U1462 ( .A(n1415), .B(n2453), .C(n1414), .CO(n1432), .S(n1511) );
CMPR32X2TS U1463 ( .A(n2119), .B(n2118), .C(n2117), .CO(n2133), .S(n2111) );
NOR2X2TS U1464 ( .A(n2152), .B(n2154), .Y(n2146) );
NAND2X1TS U1465 ( .A(n2108), .B(n2107), .Y(n2155) );
CMPR32X2TS U1466 ( .A(n1390), .B(n2384), .C(n1389), .CO(n1414), .S(n1478) );
CMPR32X2TS U1467 ( .A(n2128), .B(n2127), .C(n2126), .CO(n2129), .S(n2118) );
CMPR32X2TS U1468 ( .A(n2088), .B(n2087), .C(n2086), .CO(n2112), .S(n2109) );
NOR3X1TS U1469 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(
n2977) );
NAND2X1TS U1470 ( .A(n2166), .B(n2165), .Y(n2167) );
AND2X2TS U1471 ( .A(n2255), .B(n1494), .Y(n1028) );
NOR2X1TS U1472 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .B(n2542), .Y(n2537) );
CMPR32X2TS U1473 ( .A(DP_OP_499J312_125_1651_n62), .B(n1280), .C(n1279),
.CO(n1277), .S(n1399) );
CMPR32X2TS U1474 ( .A(n1117), .B(n2385), .C(n1116), .CO(n1389), .S(n1484) );
CMPR32X2TS U1475 ( .A(n2104), .B(n2103), .C(n2102), .CO(n2117), .S(n2087) );
CMPR32X2TS U1476 ( .A(DP_OP_496J312_122_3540_n272), .B(n2121), .C(n2120),
.CO(n2125), .S(n2127) );
NAND2X1TS U1477 ( .A(n2973), .B(n2970), .Y(n2542) );
CMPR32X2TS U1478 ( .A(n1119), .B(n2438), .C(n1118), .CO(n1116), .S(n1483) );
CMPR32X2TS U1479 ( .A(n2091), .B(n2090), .C(n2089), .CO(n2119), .S(n2102) );
CMPR32X2TS U1480 ( .A(n2101), .B(n2100), .C(n2099), .CO(n2126), .S(n2104) );
NOR3X1TS U1481 ( .A(FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(
n2970) );
NAND2X2TS U1482 ( .A(n2000), .B(n1999), .Y(n2170) );
NOR2X1TS U1483 ( .A(FPADDSUB_Raw_mant_NRM_SWR[18]), .B(n2541), .Y(n2973) );
OAI21X1TS U1484 ( .A0(n1418), .A1(n1417), .B0(n1416), .Y(n1419) );
CMPR32X2TS U1485 ( .A(n2085), .B(n2084), .C(n2083), .CO(n2086), .S(n2063) );
CMPR32X2TS U1486 ( .A(n2075), .B(n2074), .C(n2073), .CO(n2103), .S(n2085) );
CMPR32X2TS U1487 ( .A(n2067), .B(n2066), .C(n2065), .CO(n2088), .S(n2083) );
NAND2X1TS U1488 ( .A(n2964), .B(n2961), .Y(n2541) );
CMPR32X2TS U1489 ( .A(n1121), .B(n2446), .C(n1120), .CO(n1118), .S(n1474) );
CMPR32X2TS U1490 ( .A(n2007), .B(n2006), .C(n2005), .CO(n2035), .S(n2032) );
CMPR32X2TS U1491 ( .A(DP_OP_497J312_123_1725_n28), .B(
DP_OP_497J312_123_1725_n33), .C(n1385), .CO(n1411), .S(n1390) );
CMPR32X2TS U1492 ( .A(n2054), .B(n2053), .C(n2052), .CO(n2084), .S(n2060) );
NOR3X1TS U1493 ( .A(FPADDSUB_Raw_mant_NRM_SWR[19]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(
n2964) );
CMPR42X1TS U1494 ( .A(DP_OP_497J312_123_1725_n94), .B(
DP_OP_497J312_123_1725_n101), .C(DP_OP_497J312_123_1725_n24), .D(
DP_OP_497J312_123_1725_n192), .ICI(DP_OP_497J312_123_1725_n21), .S(
DP_OP_497J312_123_1725_n20), .ICO(DP_OP_497J312_123_1725_n18), .CO(
DP_OP_497J312_123_1725_n19) );
CMPR32X2TS U1495 ( .A(n2080), .B(n2079), .C(n2078), .CO(n2090), .S(n2073) );
AOI222X4TS U1496 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(FPADDSUB_DMP_SFG[2]), .B1(n2674),
.C0(FPADDSUB_DmP_mant_SFG_SWR[4]), .C1(n2674), .Y(n2691) );
ADDFHX2TS U1497 ( .A(DP_OP_499J312_125_1651_n71), .B(n1334), .CI(n1333),
.CO(n1383), .S(n2843) );
CMPR32X2TS U1498 ( .A(n1124), .B(n1123), .C(n1122), .CO(n1120), .S(n1472) );
CMPR32X2TS U1499 ( .A(n1856), .B(n1855), .C(n1854), .CO(n2031), .S(n1857) );
CMPR32X2TS U1500 ( .A(n1826), .B(n1825), .C(n1824), .CO(n2008), .S(n1859) );
CMPR32X2TS U1501 ( .A(n2029), .B(n2028), .C(n2027), .CO(n2036), .S(n2005) );
CMPR32X2TS U1502 ( .A(n2013), .B(n2012), .C(n2011), .CO(n2061), .S(n2009) );
CMPR42X1TS U1503 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .B(
DP_OP_497J312_123_1725_n25), .C(DP_OP_497J312_123_1725_n78), .D(
DP_OP_497J312_123_1725_n30), .ICI(DP_OP_497J312_123_1725_n26), .S(
DP_OP_497J312_123_1725_n23), .ICO(DP_OP_497J312_123_1725_n21), .CO(
DP_OP_497J312_123_1725_n22) );
CMPR32X2TS U1504 ( .A(n1677), .B(n1676), .C(n1675), .CO(
DP_OP_496J312_122_3540_n1004), .S(DP_OP_496J312_122_3540_n1007) );
CMPR32X2TS U1505 ( .A(DP_OP_497J312_123_1725_n34), .B(
DP_OP_497J312_123_1725_n39), .C(n1083), .CO(n1385), .S(n1117) );
NAND2X2TS U1506 ( .A(n1995), .B(n1994), .Y(n2179) );
AOI21X2TS U1507 ( .A0(n1031), .A1(n928), .B0(n1991), .Y(n2185) );
CMPR32X2TS U1508 ( .A(n1945), .B(n1944), .C(n1943), .CO(n1913), .S(n1994) );
CMPR32X2TS U1509 ( .A(DP_OP_499J312_125_1651_n77), .B(n1340), .C(n1339),
.CO(n1336), .S(n2860) );
CMPR32X2TS U1510 ( .A(DP_OP_497J312_123_1725_n40), .B(
DP_OP_497J312_123_1725_n45), .C(n1087), .CO(n1083), .S(n1119) );
OR2X2TS U1511 ( .A(n1990), .B(n1989), .Y(n1031) );
CMPR32X2TS U1512 ( .A(n2016), .B(n2015), .C(n2014), .CO(n2054), .S(n2013) );
NAND2X1TS U1513 ( .A(n1030), .B(n2189), .Y(n2191) );
XOR2X2TS U1514 ( .A(n1298), .B(n1297), .Y(n1342) );
CMPR32X2TS U1515 ( .A(DP_OP_497J312_123_1725_n46), .B(
DP_OP_497J312_123_1725_n51), .C(n1091), .CO(n1087), .S(n1121) );
CMPR32X2TS U1516 ( .A(n1820), .B(n1819), .C(n1818), .CO(n1825), .S(n1860) );
CMPR32X2TS U1517 ( .A(n1130), .B(n2441), .C(n1129), .CO(n1127), .S(n1461) );
CMPR32X2TS U1518 ( .A(n1674), .B(n1673), .C(n1672), .CO(
DP_OP_496J312_122_3540_n1006), .S(DP_OP_496J312_122_3540_n1009) );
CMPR32X2TS U1519 ( .A(n1917), .B(n1916), .C(n1915), .CO(n1911), .S(n1942) );
CMPR32X2TS U1520 ( .A(n1920), .B(n1919), .C(n1918), .CO(n1909), .S(n1941) );
CMPR32X2TS U1521 ( .A(n1951), .B(n1950), .C(n1949), .CO(n1943), .S(n1992) );
CMPR42X1TS U1522 ( .A(DP_OP_497J312_123_1725_n47), .B(
DP_OP_497J312_123_1725_n81), .C(DP_OP_497J312_123_1725_n44), .D(
DP_OP_497J312_123_1725_n48), .ICI(DP_OP_497J312_123_1725_n43), .S(
DP_OP_497J312_123_1725_n40), .ICO(DP_OP_497J312_123_1725_n38), .CO(
DP_OP_497J312_123_1725_n39) );
ADDFHX2TS U1523 ( .A(n1355), .B(n2360), .CI(n1354), .CO(n1349), .S(n2827) );
CMPR32X2TS U1524 ( .A(n1660), .B(n1659), .C(n1658), .CO(
DP_OP_496J312_122_3540_n1008), .S(DP_OP_496J312_122_3540_n1010) );
CMPR32X2TS U1525 ( .A(n1939), .B(n1938), .C(n1937), .CO(n1944), .S(n1946) );
CMPR32X2TS U1526 ( .A(n1957), .B(n1956), .C(n1955), .CO(n1948), .S(n1989) );
CMPR32X2TS U1527 ( .A(DP_OP_497J312_123_1725_n52), .B(
DP_OP_497J312_123_1725_n57), .C(n1092), .CO(n1091), .S(n1124) );
CMPR32X2TS U1528 ( .A(DP_OP_497J312_123_1725_n307), .B(n1404), .C(n1403),
.CO(n1405), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
NAND2X1TS U1529 ( .A(n1985), .B(n1984), .Y(n2193) );
XNOR2X1TS U1530 ( .A(n985), .B(n2068), .Y(n1752) );
ADDFX2TS U1531 ( .A(n1815), .B(DP_OP_496J312_122_3540_n567), .CI(n1814),
.CO(n2016), .S(n1755) );
XNOR2X1TS U1532 ( .A(n2122), .B(n986), .Y(n1751) );
CMPR32X2TS U1533 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MX[22]), .C(
DP_OP_497J312_123_1725_n306), .CO(n1406), .S(n1404) );
CMPR32X2TS U1534 ( .A(n1094), .B(n1093), .C(DP_OP_497J312_123_1725_n58),
.CO(n1092), .S(n1126) );
CMPR32X2TS U1535 ( .A(n1960), .B(n1959), .C(n1958), .CO(n1954), .S(n1987) );
CMPR32X2TS U1536 ( .A(n1657), .B(n1656), .C(n1655), .CO(n1672), .S(n1658) );
CMPR32X2TS U1537 ( .A(DP_OP_497J312_123_1725_n308), .B(
DP_OP_497J312_123_1725_n310), .C(n1402), .CO(n1403), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
CMPR32X2TS U1538 ( .A(n1668), .B(n1667), .C(n1666), .CO(
DP_OP_496J312_122_3540_n562), .S(DP_OP_496J312_122_3540_n564) );
CMPR42X1TS U1539 ( .A(DP_OP_497J312_123_1725_n121), .B(
DP_OP_497J312_123_1725_n59), .C(DP_OP_497J312_123_1725_n107), .D(
DP_OP_497J312_123_1725_n56), .ICI(DP_OP_497J312_123_1725_n55), .S(
DP_OP_497J312_123_1725_n52), .ICO(DP_OP_497J312_123_1725_n50), .CO(
DP_OP_497J312_123_1725_n51) );
CMPR32X2TS U1540 ( .A(n2045), .B(n2044), .C(n2043), .CO(n2046), .S(
DP_OP_496J312_122_3540_n563) );
NAND2X2TS U1541 ( .A(n2092), .B(n1027), .Y(n2094) );
CMPR32X2TS U1542 ( .A(n1646), .B(n1645), .C(n1644), .CO(
DP_OP_496J312_122_3540_n1011), .S(DP_OP_496J312_122_3540_n1012) );
XNOR2X1TS U1543 ( .A(n985), .B(n2050), .Y(n1804) );
CMPR32X2TS U1544 ( .A(n1932), .B(n1931), .C(n1930), .CO(n1936), .S(n1958) );
CMPR32X2TS U1545 ( .A(n1963), .B(n1962), .C(n1961), .CO(n1934), .S(n1986) );
CMPR32X2TS U1546 ( .A(DP_OP_497J312_123_1725_n65), .B(
DP_OP_497J312_123_1725_n69), .C(n1099), .CO(n1094), .S(n1128) );
CMPR32X2TS U1547 ( .A(n1643), .B(n1642), .C(n1641), .CO(n1659), .S(n1644) );
INVX2TS U1548 ( .A(n2131), .Y(n2081) );
OAI22X1TS U1549 ( .A0(n1879), .A1(n915), .B0(n1929), .B1(n1927), .Y(n1935)
);
XNOR2X1TS U1550 ( .A(n2095), .B(n1895), .Y(n1864) );
XNOR2X1TS U1551 ( .A(n2122), .B(n1895), .Y(n1827) );
XNOR2X1TS U1552 ( .A(n985), .B(n1880), .Y(n1863) );
CMPR32X2TS U1553 ( .A(n1652), .B(n1651), .C(n1650), .CO(
DP_OP_496J312_122_3540_n1015), .S(DP_OP_496J312_122_3540_n1016) );
CMPR32X2TS U1554 ( .A(n1966), .B(n1965), .C(n1964), .CO(n1961), .S(n1985) );
CMPR32X2TS U1555 ( .A(n1887), .B(n1886), .C(n1885), .CO(n1924), .S(n1962) );
CMPR32X2TS U1556 ( .A(n1634), .B(n1633), .C(n1632), .CO(n1666), .S(n1626) );
CMPR32X2TS U1557 ( .A(n1969), .B(n1968), .C(n1967), .CO(n1963), .S(n1984) );
OAI22X1TS U1558 ( .A0(n1574), .A1(n1662), .B0(n1631), .B1(n1661), .Y(n1628)
);
NOR2X2TS U1559 ( .A(n1745), .B(n1744), .Y(n2122) );
XNOR2X1TS U1560 ( .A(n2068), .B(n1895), .Y(n1879) );
XNOR2X1TS U1561 ( .A(n2050), .B(n1895), .Y(n1929) );
ADDFHX1TS U1562 ( .A(n1878), .B(n1877), .CI(n1876), .CO(n1841), .S(n1930) );
XNOR2X1TS U1563 ( .A(n2068), .B(n986), .Y(n1809) );
CMPR32X2TS U1564 ( .A(n1975), .B(n1974), .C(n1973), .CO(n1965), .S(n2198) );
CMPR32X2TS U1565 ( .A(n1107), .B(n1106), .C(DP_OP_497J312_123_1725_n75),
.CO(n1103), .S(n1132) );
NOR2X1TS U1566 ( .A(n1565), .B(n1664), .Y(n1633) );
NOR2BX1TS U1567 ( .AN(n1759), .B(n968), .Y(n1649) );
INVX2TS U1568 ( .A(n2475), .Y(n2488) );
OAI22X1TS U1569 ( .A0(n1670), .A1(n1606), .B0(n1605), .B1(n975), .Y(n1640)
);
OAI22X1TS U1570 ( .A0(n2020), .A1(n1883), .B0(n1835), .B1(n2019), .Y(n1886)
);
CMPR32X2TS U1571 ( .A(n1225), .B(n1224), .C(n1223), .CO(n1647), .S(n1921) );
ADDHXLTS U1572 ( .A(DP_OP_497J312_123_1725_n73), .B(n2487), .CO(n2389), .S(
DP_OP_497J312_123_1725_n72) );
CMPR32X2TS U1573 ( .A(DP_OP_497J312_123_1725_n323), .B(
DP_OP_497J312_123_1725_n329), .C(n1401), .CO(n1413), .S(n2453) );
CMPR32X2TS U1574 ( .A(n1972), .B(n1971), .C(n1970), .CO(n1902), .S(n2199) );
CMPR32X2TS U1575 ( .A(n1111), .B(n1110), .C(n1109), .CO(n1107), .S(n1245) );
CMPR32X2TS U1576 ( .A(n1980), .B(n2212), .C(n1979), .CO(n1975), .S(n2201) );
XOR2X1TS U1577 ( .A(n1694), .B(n1693), .Y(n1684) );
INVX2TS U1578 ( .A(n2474), .Y(n2434) );
OAI22X1TS U1579 ( .A0(n1670), .A1(n1599), .B0(n1606), .B1(n975), .Y(n1604)
);
OAI22X1TS U1580 ( .A0(n1670), .A1(n1669), .B0(n1208), .B1(n975), .Y(n1224)
);
XNOR2X1TS U1581 ( .A(n2023), .B(n1895), .Y(n1928) );
XNOR2X1TS U1582 ( .A(n986), .B(n1896), .Y(n1883) );
XNOR2X1TS U1583 ( .A(n1629), .B(n1571), .Y(n1574) );
CMPR32X2TS U1584 ( .A(DP_OP_498J312_124_1725_n308), .B(
DP_OP_498J312_124_1725_n310), .C(n1053), .CO(n1056), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
NOR2XLTS U1585 ( .A(n978), .B(n2412), .Y(DP_OP_497J312_123_1725_n118) );
NAND2X1TS U1586 ( .A(n1717), .B(n1716), .Y(n1723) );
NAND2X1TS U1587 ( .A(n1696), .B(n1695), .Y(n1766) );
CMPR32X2TS U1588 ( .A(n1978), .B(n1977), .C(n1976), .CO(n1899), .S(n2202) );
BUFX3TS U1589 ( .A(n1074), .Y(n2486) );
XNOR2X1TS U1590 ( .A(n1717), .B(n1727), .Y(n1599) );
BUFX3TS U1591 ( .A(n1882), .Y(n986) );
XNOR2X1TS U1592 ( .A(n1717), .B(n1740), .Y(n1209) );
XNOR2X1TS U1593 ( .A(n1694), .B(n1703), .Y(n1231) );
XNOR2X1TS U1594 ( .A(n1694), .B(n988), .Y(n1600) );
XNOR2X1TS U1595 ( .A(n1867), .B(n1866), .Y(n1900) );
XNOR2X2TS U1596 ( .A(n1771), .B(n1764), .Y(n1767) );
NOR2X1TS U1597 ( .A(n1540), .B(n1664), .Y(n1634) );
NAND2XLTS U1598 ( .A(n1014), .B(n1780), .Y(n1782) );
OR2X2TS U1599 ( .A(n1679), .B(FPMULT_Op_MX[11]), .Y(n1764) );
NAND2XLTS U1600 ( .A(n1694), .B(n1693), .Y(n1695) );
OAI22X2TS U1601 ( .A0(n1873), .A1(n1034), .B0(n1892), .B1(n1894), .Y(n2212)
);
OAI22X1TS U1602 ( .A0(n1637), .A1(n1198), .B0(n1197), .B1(n987), .Y(n1229)
);
OAI22X1TS U1603 ( .A0(n1874), .A1(n1034), .B0(n1873), .B1(n1894), .Y(n2211)
);
OAI22X1TS U1604 ( .A0(n1796), .A1(n1034), .B0(n1874), .B1(n1894), .Y(n2207)
);
OAI21X1TS U1605 ( .A0(n1694), .A1(n1693), .B0(n1692), .Y(n1696) );
NOR2X2TS U1606 ( .A(n1698), .B(n1697), .Y(n1720) );
OAI22X1TS U1607 ( .A0(n1662), .A1(n1664), .B0(n1567), .B1(n1661), .Y(n1611)
);
OAI22X1TS U1608 ( .A0(n1792), .A1(n1788), .B0(n1865), .B1(n1787), .Y(n1838)
);
XNOR2X1TS U1609 ( .A(n1618), .B(n1571), .Y(n1573) );
CMPR32X2TS U1610 ( .A(n1325), .B(DP_OP_498J312_124_1725_n74), .C(
DP_OP_498J312_124_1725_n70), .CO(n1321), .S(n2259) );
CMPR32X2TS U1611 ( .A(n1078), .B(n1077), .C(n1076), .CO(n1388), .S(n1086) );
INVX2TS U1612 ( .A(n1571), .Y(n1664) );
NAND2XLTS U1613 ( .A(n1774), .B(n1773), .Y(n1775) );
OR2X2TS U1614 ( .A(n988), .B(n1711), .Y(n1014) );
NAND2X2TS U1615 ( .A(n1661), .B(n1025), .Y(n1662) );
OAI22X1TS U1616 ( .A0(n1235), .A1(n1134), .B0(n1597), .B1(n1234), .Y(n1793)
);
OAI22X1TS U1617 ( .A0(n1230), .A1(n1134), .B0(n1235), .B1(n1597), .Y(n1237)
);
XNOR2X2TS U1618 ( .A(n1679), .B(FPMULT_Op_MX[11]), .Y(n1693) );
XNOR2X2TS U1619 ( .A(n1872), .B(n1571), .Y(n1569) );
XNOR2X1TS U1620 ( .A(n988), .B(n1727), .Y(n1197) );
XNOR2X1TS U1621 ( .A(n1872), .B(n1789), .Y(n1790) );
AOI21X2TS U1622 ( .A0(n1749), .A1(n1013), .B0(n1706), .Y(n1776) );
NAND2X2TS U1623 ( .A(n1034), .B(n1585), .Y(n1894) );
ADDHXLTS U1624 ( .A(n1062), .B(n1061), .CO(n1058), .S(n1265) );
CMPR32X2TS U1625 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[21]), .C(n2404),
.CO(n2402), .S(n2420) );
CMPR32X2TS U1626 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[22]), .C(n1073),
.CO(n1421), .S(n1075) );
CMPR32X2TS U1627 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .C(n1680),
.CO(n1679), .S(n1685) );
CMPR32X2TS U1628 ( .A(DP_OP_498J312_124_1725_n316), .B(
DP_OP_498J312_124_1725_n322), .C(n1301), .CO(n1299), .S(n1517) );
ADDHXLTS U1629 ( .A(n1082), .B(n1081), .CO(n1076), .S(n1088) );
INVX2TS U1630 ( .A(n2429), .Y(DP_OP_497J312_123_1725_n119) );
XNOR2X1TS U1631 ( .A(n1692), .B(n1703), .Y(n1230) );
XOR2X1TS U1632 ( .A(n1727), .B(n1729), .Y(n1734) );
CMPR32X2TS U1633 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .C(n1710),
.CO(n1715), .S(n1711) );
CMPR32X2TS U1634 ( .A(DP_OP_498J312_124_1725_n323), .B(
DP_OP_498J312_124_1725_n329), .C(n1303), .CO(n1301), .S(n2360) );
CMPR32X2TS U1635 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MY[5]), .C(n2268),
.CO(n2306), .S(n2307) );
CMPR32X2TS U1636 ( .A(n1288), .B(n1287), .C(n1286), .CO(n1330), .S(n1331) );
BUFX4TS U1637 ( .A(n2273), .Y(n2375) );
OR2X2TS U1638 ( .A(n1705), .B(FPMULT_Op_MY[20]), .Y(n1013) );
NOR2X2TS U1639 ( .A(n1709), .B(n1708), .Y(n1772) );
CMPR32X2TS U1640 ( .A(FPMULT_Op_MX[9]), .B(n1686), .C(n976), .CO(n1680), .S(
n1729) );
CLKXOR2X2TS U1641 ( .A(n1204), .B(n1203), .Y(n1698) );
CMPR32X2TS U1642 ( .A(FPMULT_Op_MX[8]), .B(n912), .C(n1728), .CO(n1686), .S(
n1739) );
CMPR32X2TS U1643 ( .A(FPMULT_Op_MY[13]), .B(n914), .C(n1420), .CO(n2406),
.S(n2424) );
CMPR32X2TS U1644 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[21]), .C(n1707),
.CO(n1710), .S(n1709) );
ADDHXLTS U1645 ( .A(n2343), .B(n2342), .CO(DP_OP_498J312_124_1725_n319), .S(
DP_OP_498J312_124_1725_n320) );
CMPR32X2TS U1646 ( .A(n1290), .B(n2383), .C(n1289), .CO(n1329), .S(n1286) );
NAND2X1TS U1647 ( .A(n976), .B(FPMULT_Op_MX[9]), .Y(n1557) );
BUFX3TS U1648 ( .A(n2297), .Y(n2366) );
NAND2XLTS U1649 ( .A(n1137), .B(n1700), .Y(n1138) );
NAND2X1TS U1650 ( .A(n1528), .B(n1527), .Y(n1545) );
XNOR2X1TS U1651 ( .A(n2340), .B(n2372), .Y(n2381) );
AOI21X1TS U1652 ( .A0(n1201), .A1(n1000), .B0(n1200), .Y(n1204) );
ADDHXLTS U1653 ( .A(n1489), .B(n1488), .CO(DP_OP_498J312_124_1725_n326), .S(
DP_OP_498J312_124_1725_n327) );
CMPR32X2TS U1654 ( .A(n1310), .B(n1309), .C(n1308), .CO(n1305), .S(n2355) );
BUFX3TS U1655 ( .A(n2298), .Y(n2363) );
BUFX3TS U1656 ( .A(n2299), .Y(n2369) );
NOR2X2TS U1657 ( .A(n976), .B(FPMULT_Op_MX[9]), .Y(n1558) );
CMPR32X2TS U1658 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[4]), .C(n2266),
.CO(n2268), .S(n2373) );
CMPR32X4TS U1659 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[19]), .C(n1070),
.CO(n2411), .S(n2429) );
CMPR32X2TS U1660 ( .A(n1050), .B(n1049), .C(n1048), .CO(n1306), .S(n1310) );
CMPR42X1TS U1661 ( .A(DP_OP_498J312_124_1725_n273), .B(
DP_OP_498J312_124_1725_n240), .C(DP_OP_498J312_124_1725_n237), .D(
DP_OP_498J312_124_1725_n236), .ICI(DP_OP_498J312_124_1725_n234), .S(
DP_OP_498J312_124_1725_n232), .ICO(DP_OP_498J312_124_1725_n230), .CO(
DP_OP_498J312_124_1725_n231) );
BUFX3TS U1662 ( .A(n1139), .Y(n2376) );
INVX4TS U1663 ( .A(n918), .Y(n976) );
NAND2X1TS U1664 ( .A(n994), .B(n1520), .Y(n1524) );
NAND2X2TS U1665 ( .A(n2294), .B(n1146), .Y(n1147) );
AOI21X1TS U1666 ( .A0(n994), .A1(n1522), .B0(n1521), .Y(n1523) );
CMPR32X2TS U1667 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[3]), .C(n2270), .CO(
n2269), .S(n2298) );
CMPR32X2TS U1668 ( .A(n1262), .B(n1261), .C(n1260), .CO(n1239), .S(n2856) );
BUFX3TS U1669 ( .A(n2294), .Y(n2372) );
INVX2TS U1670 ( .A(n1140), .Y(n1146) );
ADDHXLTS U1671 ( .A(n2354), .B(n2353), .CO(DP_OP_498J312_124_1725_n244), .S(
n1261) );
NAND2X1TS U1672 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[7]), .Y(n1534) );
NOR2X1TS U1673 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[7]), .Y(n1535) );
NOR2X1TS U1674 ( .A(n993), .B(n1004), .Y(n2350) );
NOR2X1TS U1675 ( .A(n1001), .B(DP_OP_498J312_124_1725_n289), .Y(n2349) );
NAND2X1TS U1676 ( .A(n912), .B(FPMULT_Op_MX[8]), .Y(n1537) );
NOR2X1TS U1677 ( .A(n993), .B(n991), .Y(n2354) );
NOR2X1TS U1678 ( .A(n1001), .B(n1005), .Y(n2353) );
NAND2X1TS U1679 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[5]), .Y(n1219) );
NOR2X1TS U1680 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[5]), .Y(n1211) );
NAND2X1TS U1681 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .Y(n1164) );
NOR2X2TS U1682 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n1158) );
NOR2X1TS U1683 ( .A(n993), .B(n927), .Y(n1144) );
NAND2X1TS U1684 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n1176) );
NAND2X1TS U1685 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n1202) );
NOR2X4TS U1686 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[13]), .Y(n1179) );
NAND2X2TS U1687 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n1182) );
NAND2X1TS U1688 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[4]), .Y(n1170) );
NAND2X1TS U1689 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n1188) );
NAND2X2TS U1690 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[0]), .Y(n1195) );
OR2X1TS U1691 ( .A(n1715), .B(FPMULT_Op_MY[11]), .Y(n1716) );
INVX2TS U1692 ( .A(DP_OP_496J312_122_3540_n562), .Y(n2041) );
XNOR2X1TS U1693 ( .A(n985), .B(n2122), .Y(n2039) );
XNOR2X1TS U1694 ( .A(n2095), .B(n2081), .Y(n2082) );
XNOR2X1TS U1695 ( .A(n2095), .B(n985), .Y(n2026) );
INVX2TS U1696 ( .A(DP_OP_496J312_122_3540_n572), .Y(n1801) );
XNOR2X1TS U1697 ( .A(n986), .B(n2023), .Y(n1784) );
OR2X1TS U1698 ( .A(n1867), .B(n1866), .Y(n1840) );
INVX2TS U1699 ( .A(n1872), .Y(n1540) );
OAI21XLTS U1700 ( .A0(n1560), .A1(n1557), .B0(n1561), .Y(n1525) );
INVX2TS U1701 ( .A(n1702), .Y(n1546) );
NAND2X2TS U1702 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[13]), .Y(n1180) );
NOR2XLTS U1703 ( .A(n1665), .B(n1664), .Y(n2044) );
NOR2X1TS U1704 ( .A(n1544), .B(n1664), .Y(n1577) );
OR2X1TS U1705 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n1022) );
XNOR2X1TS U1706 ( .A(n985), .B(n1896), .Y(n1925) );
OAI21XLTS U1707 ( .A0(n1167), .A1(n1163), .B0(n1164), .Y(n1162) );
XNOR2X1TS U1708 ( .A(n1717), .B(n1694), .Y(n1605) );
NAND2X1TS U1709 ( .A(DP_OP_497J312_123_1725_n20), .B(
DP_OP_497J312_123_1725_n22), .Y(n1416) );
NOR2XLTS U1710 ( .A(DP_OP_497J312_123_1725_n20), .B(
DP_OP_497J312_123_1725_n22), .Y(n1417) );
NOR2XLTS U1711 ( .A(DP_OP_498J312_124_1725_n376), .B(
DP_OP_498J312_124_1725_n382), .Y(n2325) );
BUFX3TS U1712 ( .A(n2267), .Y(n2287) );
NOR2XLTS U1713 ( .A(n1006), .B(n922), .Y(n2391) );
NOR2X2TS U1714 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .Y(n1163) );
ADDFX2TS U1715 ( .A(n1901), .B(n1900), .CI(n1899), .CO(n1904), .S(n1973) );
BUFX3TS U1716 ( .A(n1071), .Y(n2474) );
NOR2XLTS U1717 ( .A(n933), .B(n922), .Y(n1095) );
NOR2X1TS U1718 ( .A(n2486), .B(n978), .Y(DP_OP_497J312_123_1725_n109) );
NOR2X1TS U1719 ( .A(n1163), .B(n1158), .Y(n1047) );
NOR2XLTS U1720 ( .A(n923), .B(n1005), .Y(n2319) );
BUFX4TS U1721 ( .A(n2274), .Y(n2377) );
CMPR42X1TS U1722 ( .A(DP_OP_498J312_124_1725_n114), .B(
DP_OP_498J312_124_1725_n61), .C(DP_OP_498J312_124_1725_n83), .D(
DP_OP_498J312_124_1725_n197), .ICI(DP_OP_498J312_124_1725_n100), .S(
DP_OP_498J312_124_1725_n55), .ICO(DP_OP_498J312_124_1725_n53), .CO(
DP_OP_498J312_124_1725_n54) );
CMPR42X1TS U1723 ( .A(DP_OP_497J312_123_1725_n120), .B(
DP_OP_497J312_123_1725_n113), .C(DP_OP_497J312_123_1725_n53), .D(
DP_OP_497J312_123_1725_n196), .ICI(DP_OP_497J312_123_1725_n82), .S(
DP_OP_497J312_123_1725_n49), .ICO(DP_OP_497J312_123_1725_n47), .CO(
DP_OP_497J312_123_1725_n48) );
NOR2XLTS U1724 ( .A(n1008), .B(n3510), .Y(n2394) );
NOR2XLTS U1725 ( .A(n1009), .B(n921), .Y(n2399) );
NAND2X2TS U1726 ( .A(n1993), .B(n1992), .Y(n2183) );
NOR2XLTS U1727 ( .A(DP_OP_496J312_122_3540_n686), .B(
DP_OP_498J312_124_1725_n381), .Y(n1054) );
CMPR42X1TS U1728 ( .A(DP_OP_497J312_123_1725_n111), .B(
DP_OP_497J312_123_1725_n97), .C(DP_OP_497J312_123_1725_n104), .D(
DP_OP_497J312_123_1725_n195), .ICI(DP_OP_497J312_123_1725_n41), .S(
DP_OP_497J312_123_1725_n37), .ICO(DP_OP_497J312_123_1725_n35), .CO(
DP_OP_497J312_123_1725_n36) );
NOR2XLTS U1729 ( .A(n3080), .B(FPADDSUB_intDY_EWSW[16]), .Y(n3081) );
NOR2XLTS U1730 ( .A(DP_OP_498J312_124_1725_n283), .B(n1004), .Y(n1318) );
XNOR2X1TS U1731 ( .A(n2191), .B(n2190), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
OAI21XLTS U1732 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n3642), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n3087) );
NOR2X1TS U1733 ( .A(n1447), .B(n1497), .Y(n2240) );
CMPR42X1TS U1734 ( .A(DP_OP_498J312_124_1725_n116), .B(
DP_OP_498J312_124_1725_n109), .C(DP_OP_498J312_124_1725_n123), .D(
DP_OP_498J312_124_1725_n68), .ICI(DP_OP_498J312_124_1725_n67), .S(
DP_OP_498J312_124_1725_n65), .ICO(DP_OP_498J312_124_1725_n63), .CO(
DP_OP_498J312_124_1725_n64) );
NOR2XLTS U1735 ( .A(n1006), .B(n1024), .Y(n1059) );
XNOR2X1TS U1736 ( .A(n2188), .B(n928), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
NOR2X1TS U1737 ( .A(n1406), .B(n1405), .Y(DP_OP_497J312_123_1725_n192) );
CMPR42X1TS U1738 ( .A(DP_OP_499J312_125_1651_n107), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .C(
DP_OP_499J312_125_1651_n72), .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .ICI(
DP_OP_499J312_125_1651_n73), .S(DP_OP_499J312_125_1651_n71), .ICO(
DP_OP_499J312_125_1651_n69), .CO(DP_OP_499J312_125_1651_n70) );
NAND2X1TS U1739 ( .A(n1504), .B(n1503), .Y(n1507) );
NOR2X2TS U1740 ( .A(n1473), .B(n1472), .Y(n2246) );
OAI22X1TS U1741 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(n3563), .B0(n2803),
.B1(n2802), .Y(n3225) );
NOR2XLTS U1742 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n2554) );
NAND2X1TS U1743 ( .A(n2977), .B(n2537), .Y(n2979) );
INVX2TS U1744 ( .A(n3472), .Y(n3455) );
BUFX4TS U1745 ( .A(n3455), .Y(n3458) );
INVX2TS U1746 ( .A(n1505), .Y(n1464) );
INVX2TS U1747 ( .A(n2924), .Y(n946) );
INVX2TS U1748 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n3262) );
INVX2TS U1749 ( .A(n2958), .Y(n2873) );
BUFX3TS U1750 ( .A(n2648), .Y(n3452) );
AOI211XLTS U1751 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n3479), .B0(n3476), .C0(n2709), .Y(FPADDSUB_enable_Pipeline_input) );
OAI21XLTS U1752 ( .A0(n2955), .A1(n3279), .B0(n2905), .Y(
FPADDSUB_Data_array_SWR[21]) );
OAI21XLTS U1753 ( .A0(n2948), .A1(n2814), .B0(n2947), .Y(
FPADDSUB_Data_array_SWR[4]) );
OAI21XLTS U1754 ( .A0(n2944), .A1(n2814), .B0(n2925), .Y(
FPADDSUB_Data_array_SWR[7]) );
INVX2TS U1755 ( .A(n952), .Y(n953) );
OAI21XLTS U1756 ( .A0(n2932), .A1(n948), .B0(n2897), .Y(
FPADDSUB_Data_array_SWR[10]) );
OAI21XLTS U1757 ( .A0(n2938), .A1(n3279), .B0(n2918), .Y(
FPADDSUB_Data_array_SWR[19]) );
OAI211XLTS U1758 ( .A0(operation[1]), .A1(n2517), .B0(n2516), .C0(n2515),
.Y(add_subt_data2[22]) );
OAI211XLTS U1759 ( .A0(operation[1]), .A1(n2514), .B0(n2513), .C0(n2520),
.Y(add_subt_data2[20]) );
CLKXOR2X4TS U1760 ( .A(n1536), .B(n1760), .Y(n915) );
XNOR2X2TS U1761 ( .A(n1425), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n916)
);
BUFX4TS U1762 ( .A(n2765), .Y(n3417) );
INVX4TS U1763 ( .A(n953), .Y(n2765) );
INVX4TS U1764 ( .A(operation[1]), .Y(n952) );
INVX4TS U1765 ( .A(n1498), .Y(n2243) );
XOR2X4TS U1766 ( .A(n1382), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n2255) );
AOI22X1TS U1767 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n3596), .B0(n3241), .B1(
n3240), .Y(n3244) );
INVX2TS U1768 ( .A(DP_OP_496J312_122_3540_n564), .Y(n2022) );
AO22XLTS U1769 ( .A0(n3344), .A1(FPADDSUB_LZD_raw_out_EWR[3]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n3556), .Y(
FPADDSUB_shft_value_mux_o_EWR[3]) );
AO22XLTS U1770 ( .A0(n3702), .A1(FPADDSUB_LZD_raw_out_EWR[2]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n3556), .Y(
FPADDSUB_shft_value_mux_o_EWR[2]) );
INVX2TS U1771 ( .A(DP_OP_496J312_122_3540_n565), .Y(n2040) );
AO22XLTS U1772 ( .A0(n3344), .A1(FPADDSUB_LZD_raw_out_EWR[4]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n2901), .Y(
FPADDSUB_shft_value_mux_o_EWR[4]) );
ADDHX1TS U1773 ( .A(n1611), .B(n1610), .CO(n1588), .S(n1622) );
BUFX4TS U1774 ( .A(n3268), .Y(n3271) );
OAI22X1TS U1775 ( .A0(n1518), .A1(n975), .B0(n1670), .B1(n1605), .Y(n1642)
);
OAI21XLTS U1776 ( .A0(n2715), .A1(n2717), .B0(n2714), .Y(n2713) );
OAI22X1TS U1777 ( .A0(n1601), .A1(n987), .B0(n1600), .B1(n1637), .Y(n1603)
);
INVX3TS U1778 ( .A(n3296), .Y(n3297) );
INVX2TS U1779 ( .A(n1157), .Y(n1167) );
INVX2TS U1780 ( .A(n1174), .Y(n1201) );
AO22XLTS U1781 ( .A0(operation[1]), .A1(n3031), .B0(n3387), .B1(operation[0]), .Y(n3034) );
OAI211XLTS U1782 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n3636), .B0(n3061), .C0(
n3064), .Y(n3075) );
AND2X2TS U1783 ( .A(FPMULT_Op_MY[21]), .B(n976), .Y(n2471) );
OAI21XLTS U1784 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n3539), .B0(n3250),
.Y(n3247) );
AND2X2TS U1785 ( .A(FPMULT_Op_MY[20]), .B(n912), .Y(
DP_OP_497J312_123_1725_n359) );
AND2X2TS U1786 ( .A(n914), .B(n976), .Y(n2445) );
CMPR22X2TS U1787 ( .A(n913), .B(FPMULT_Op_MX[12]), .CO(n1070), .S(n2433) );
NAND3XLTS U1788 ( .A(n3636), .B(n3061), .C(FPADDSUB_intDX_EWSW[8]), .Y(n3062) );
CLKAND2X2TS U1789 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n3563), .Y(n2803)
);
CLKAND2X2TS U1790 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n3573), .Y(n2809)
);
CLKAND2X2TS U1791 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n3560), .Y(n2792)
);
AND2X2TS U1792 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[21]), .Y(n2400) );
NAND2X4TS U1793 ( .A(n1473), .B(n1472), .Y(n2245) );
NAND2X4TS U1794 ( .A(n1470), .B(n1469), .Y(n2218) );
NAND2X6TS U1795 ( .A(n1438), .B(n1437), .Y(n1441) );
CLKXOR2X2TS U1796 ( .A(n1443), .B(n1442), .Y(n1444) );
ADDHX2TS U1797 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .B(n1429),
.CO(n1428), .S(n1496) );
INVX3TS U1798 ( .A(n2163), .Y(n2173) );
XOR2X1TS U1799 ( .A(n3262), .B(n3261), .Y(FPADDSUB_Raw_mant_SGF[25]) );
OAI32X1TS U1800 ( .A0(n3703), .A1(n3259), .A2(n3258), .B0(n3257), .B1(n910),
.Y(n3261) );
INVX2TS U1801 ( .A(n2147), .Y(n2149) );
NOR2X4TS U1802 ( .A(n2110), .B(n2109), .Y(n2147) );
ADDFHX2TS U1803 ( .A(n2064), .B(n2063), .CI(n2062), .CO(n2110), .S(n2107) );
ADDFHX2TS U1804 ( .A(n2035), .B(n2034), .CI(n2033), .CO(n2108), .S(n2106) );
ADDFHX2TS U1805 ( .A(n1914), .B(n1913), .CI(n1912), .CO(n1999), .S(n1998) );
NOR2X4TS U1806 ( .A(n1993), .B(n1992), .Y(n2182) );
ADDFHX2TS U1807 ( .A(n1948), .B(n1947), .CI(n1946), .CO(n1940), .S(n1993) );
OR2X2TS U1808 ( .A(n1987), .B(n1986), .Y(n1030) );
ADDFHX1TS U1809 ( .A(n1755), .B(n1754), .CI(n1753), .CO(n2027), .S(n1821) );
NOR2X2TS U1810 ( .A(n1985), .B(n1984), .Y(n2192) );
XNOR2X1TS U1811 ( .A(n2077), .B(n2076), .Y(n2080) );
INVX2TS U1812 ( .A(DP_OP_496J312_122_3540_n569), .Y(n1758) );
INVX2TS U1813 ( .A(DP_OP_496J312_122_3540_n567), .Y(n2021) );
INVX2TS U1814 ( .A(DP_OP_496J312_122_3540_n568), .Y(n1757) );
INVX2TS U1815 ( .A(DP_OP_496J312_122_3540_n566), .Y(n1814) );
ADDHX1TS U1816 ( .A(n1786), .B(n1785), .CO(n1800), .S(n1842) );
ADDFHX2TS U1817 ( .A(n1628), .B(n1627), .CI(n1626), .CO(
DP_OP_496J312_122_3540_n565), .S(DP_OP_496J312_122_3540_n566) );
OAI22X2TS U1818 ( .A0(n1827), .A1(n1927), .B0(n1815), .B1(n915), .Y(n1778)
);
INVX2TS U1819 ( .A(DP_OP_496J312_122_3540_n574), .Y(n1785) );
INVX2TS U1820 ( .A(DP_OP_496J312_122_3540_n575), .Y(n1786) );
INVX2TS U1821 ( .A(n2207), .Y(n1839) );
XNOR2X1TS U1822 ( .A(n2081), .B(n2068), .Y(n2055) );
OAI22X1TS U1823 ( .A0(n2094), .A1(n1783), .B0(n2092), .B1(n1817), .Y(n1812)
);
CLKXOR2X2TS U1824 ( .A(n1406), .B(n1405), .Y(DP_OP_497J312_123_1725_n193) );
XNOR2X2TS U1825 ( .A(n1663), .B(n1789), .Y(n1566) );
AOI222X4TS U1826 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(FPADDSUB_DMP_SFG[10]), .B1(n2793),
.C0(FPADDSUB_DmP_mant_SFG_SWR[12]), .C1(n2793), .Y(n2798) );
OAI22X1TS U1827 ( .A0(n1670), .A1(n1210), .B0(n1209), .B1(n975), .Y(n1223)
);
NAND2X4TS U1828 ( .A(n1763), .B(n915), .Y(n1927) );
INVX4TS U1829 ( .A(n3099), .Y(n3268) );
NAND2X2TS U1830 ( .A(n1570), .B(n1584), .Y(n1551) );
AOI222X4TS U1831 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(FPADDSUB_DMP_SFG[8]), .B1(n2769),
.C0(FPADDSUB_DmP_mant_SFG_SWR[10]), .C1(n2769), .Y(n2776) );
XNOR2X1TS U1832 ( .A(n1684), .B(n1683), .Y(n1690) );
XNOR2X1TS U1833 ( .A(n1770), .B(n1765), .Y(n1769) );
OAI21XLTS U1834 ( .A0(n3480), .A1(n3522), .B0(FPSENCOS_cont_var_out[1]), .Y(
n2988) );
NAND2X4TS U1835 ( .A(n1548), .B(n1547), .Y(n1570) );
OAI21XLTS U1836 ( .A0(n2579), .A1(n2685), .B0(n2684), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[1]) );
XNOR2X1TS U1837 ( .A(n1732), .B(n1726), .Y(n1882) );
OAI21X2TS U1838 ( .A0(n914), .A1(FPMULT_Op_MY[7]), .B0(n1546), .Y(n1548) );
XNOR2X1TS U1839 ( .A(n1770), .B(n1703), .Y(n1598) );
OR2X2TS U1840 ( .A(n1771), .B(n1770), .Y(n1027) );
XNOR2X1TS U1841 ( .A(n1771), .B(n1703), .Y(n1226) );
AOI222X4TS U1842 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[8]), .B0(FPADDSUB_DMP_SFG[6]), .B1(n2718),
.C0(FPADDSUB_DmP_mant_SFG_SWR[8]), .C1(n2718), .Y(n2761) );
INVX3TS U1843 ( .A(n3296), .Y(n3295) );
OAI21XLTS U1844 ( .A0(n2621), .A1(n3609), .B0(n2598), .Y(n2599) );
XNOR2X1TS U1845 ( .A(n1734), .B(n1733), .Y(n1742) );
OAI21XLTS U1846 ( .A0(n2621), .A1(n3542), .B0(n2600), .Y(n2601) );
OAI21XLTS U1847 ( .A0(n3598), .A1(n2621), .B0(n2602), .Y(n2603) );
INVX6TS U1848 ( .A(n1712), .Y(n988) );
XOR2X1TS U1849 ( .A(n1762), .B(n1761), .Y(n1763) );
OAI21XLTS U1850 ( .A0(n2621), .A1(n3599), .B0(n2620), .Y(n2622) );
BUFX3TS U1851 ( .A(n3414), .Y(n3419) );
NOR2X1TS U1852 ( .A(n1734), .B(n1730), .Y(n1731) );
NOR2X1TS U1853 ( .A(n1740), .B(n1739), .Y(n1733) );
AOI222X4TS U1854 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[6]), .B0(FPADDSUB_DMP_SFG[4]), .B1(n2697),
.C0(FPADDSUB_DmP_mant_SFG_SWR[6]), .C1(n2697), .Y(n2712) );
NAND2X1TS U1855 ( .A(n1216), .B(n1215), .Y(n1217) );
BUFX4TS U1856 ( .A(n3359), .Y(n3326) );
BUFX4TS U1857 ( .A(n2501), .Y(n3407) );
OR2X2TS U1858 ( .A(n1211), .B(n1214), .Y(n1020) );
INVX2TS U1859 ( .A(n2541), .Y(n2555) );
AND2X2TS U1860 ( .A(FPMULT_Op_MY[22]), .B(n976), .Y(
DP_OP_497J312_123_1725_n351) );
CLKAND2X2TS U1861 ( .A(n914), .B(n913), .Y(n1079) );
CLKAND2X2TS U1862 ( .A(FPMULT_Op_MY[20]), .B(n913), .Y(n1082) );
NOR2X1TS U1863 ( .A(n1553), .B(n1552), .Y(n1555) );
OAI21X1TS U1864 ( .A0(n1164), .A1(n1158), .B0(n1159), .Y(n1046) );
NAND2X1TS U1865 ( .A(n1017), .B(n1202), .Y(n1203) );
XOR2X1TS U1866 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[9]), .Y(n1552) );
OR2X2TS U1867 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[0]), .Y(n1023) );
CLKAND2X2TS U1868 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n3576), .Y(n2816)
);
AND2X2TS U1869 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n3549), .Y(n2696) );
AND2X2TS U1870 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n3552), .Y(n2717) );
XOR2X1TS U1871 ( .A(n2247), .B(n2216), .Y(FPMULT_Sgf_operation_Result[36])
);
NAND2X6TS U1872 ( .A(n1441), .B(n1440), .Y(n1445) );
NAND2X2TS U1873 ( .A(n1439), .B(DP_OP_499J312_125_1651_n31), .Y(n1440) );
OR2X2TS U1874 ( .A(n1464), .B(n1507), .Y(n1010) );
INVX4TS U1875 ( .A(n2135), .Y(n2162) );
OAI21X1TS U1876 ( .A0(n2137), .A1(n2147), .B0(n2148), .Y(n2138) );
NOR2X1TS U1877 ( .A(n2136), .B(n2147), .Y(n2139) );
ADDFHX2TS U1878 ( .A(n2447), .B(n1431), .CI(n1430), .CO(n1429), .S(n1498) );
XOR2X2TS U1879 ( .A(n2178), .B(n2177), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
XOR2X2TS U1880 ( .A(n2186), .B(n2185), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
XOR2X1TS U1881 ( .A(n3254), .B(n3253), .Y(FPADDSUB_Raw_mant_SGF[24]) );
NAND2X1TS U1882 ( .A(n2142), .B(n2141), .Y(n2143) );
XOR2X2TS U1883 ( .A(DP_OP_497J312_123_1725_n18), .B(n1424), .Y(n1430) );
XNOR2X2TS U1884 ( .A(n2181), .B(n2180), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
NAND2X2TS U1885 ( .A(n1032), .B(n2179), .Y(n2181) );
XOR2X1TS U1886 ( .A(n3248), .B(n3247), .Y(FPADDSUB_Raw_mant_SGF[23]) );
NAND2X2TS U1887 ( .A(n2002), .B(n2001), .Y(n2165) );
INVX3TS U1888 ( .A(n2174), .Y(n2176) );
NAND2X2TS U1889 ( .A(n2184), .B(n2183), .Y(n2186) );
NAND2X2TS U1890 ( .A(n2110), .B(n2109), .Y(n2148) );
OAI21X1TS U1891 ( .A0(n2950), .A1(n948), .B0(n2891), .Y(
FPADDSUB_Data_array_SWR[14]) );
OAI21X1TS U1892 ( .A0(n2937), .A1(n3279), .B0(n2907), .Y(
FPADDSUB_Data_array_SWR[17]) );
OAI21X1TS U1893 ( .A0(n2954), .A1(n3279), .B0(n2953), .Y(
FPADDSUB_Data_array_SWR[12]) );
OAI21X1TS U1894 ( .A0(n2930), .A1(n2814), .B0(n2929), .Y(
FPADDSUB_Data_array_SWR[1]) );
OAI21X1TS U1895 ( .A0(n2938), .A1(n948), .B0(n2894), .Y(
FPADDSUB_Data_array_SWR[18]) );
ADDFHX2TS U1896 ( .A(n2032), .B(n2031), .CI(n2030), .CO(n2105), .S(n2002) );
OAI21X1TS U1897 ( .A0(n2926), .A1(n2814), .B0(n2903), .Y(
FPADDSUB_Data_array_SWR[2]) );
OAI21X1TS U1898 ( .A0(n2950), .A1(n3279), .B0(n2920), .Y(
FPADDSUB_Data_array_SWR[15]) );
OAI21X1TS U1899 ( .A0(n2949), .A1(n3279), .B0(n2911), .Y(
FPADDSUB_Data_array_SWR[13]) );
NOR2X6TS U1900 ( .A(n2000), .B(n1999), .Y(n2169) );
OAI21X1TS U1901 ( .A0(n2881), .A1(n3245), .B0(n2880), .Y(n2879) );
OAI21X1TS U1902 ( .A0(n2960), .A1(n3279), .B0(n2959), .Y(
FPADDSUB_Data_array_SWR[20]) );
NOR2X6TS U1903 ( .A(n1998), .B(n1997), .Y(n2174) );
OAI21X1TS U1904 ( .A0(n2944), .A1(n948), .B0(n2900), .Y(
FPADDSUB_Data_array_SWR[6]) );
OAI21X1TS U1905 ( .A0(n2932), .A1(n3279), .B0(n2922), .Y(
FPADDSUB_Data_array_SWR[11]) );
OR2X4TS U1906 ( .A(n1995), .B(n1994), .Y(n1032) );
OAI21X1TS U1907 ( .A0(n2931), .A1(n3279), .B0(n2913), .Y(
FPADDSUB_Data_array_SWR[9]) );
OAI21X1TS U1908 ( .A0(n2942), .A1(n2814), .B0(n2941), .Y(
FPADDSUB_Data_array_SWR[16]) );
OAI21X1TS U1909 ( .A0(n2936), .A1(n3279), .B0(n2935), .Y(
FPADDSUB_Data_array_SWR[8]) );
OAI21X1TS U1910 ( .A0(n2943), .A1(n2814), .B0(n2909), .Y(
FPADDSUB_Data_array_SWR[5]) );
OAI21X1TS U1911 ( .A0(n3280), .A1(n946), .B0(n2888), .Y(
FPADDSUB_Data_array_SWR[22]) );
ADDFHX2TS U1912 ( .A(n1942), .B(n1941), .CI(n1940), .CO(n1997), .S(n1995) );
XOR3X2TS U1913 ( .A(n2131), .B(n2130), .C(n2129), .Y(n2132) );
XOR2X1TS U1914 ( .A(n3243), .B(n3242), .Y(FPADDSUB_Raw_mant_SGF[21]) );
ADDHX2TS U1915 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(n1338),
.CO(n1335), .S(n2861) );
OAI21X1TS U1916 ( .A0(n2821), .A1(n2877), .B0(n2820), .Y(n2819) );
ADDFHX2TS U1917 ( .A(n1911), .B(n1910), .CI(n1909), .CO(n1858), .S(n1912) );
NAND2X2TS U1918 ( .A(n1990), .B(n1989), .Y(n2187) );
AOI222X4TS U1919 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .B0(FPADDSUB_DMP_SFG[20]), .B1(n3030),
.C0(FPADDSUB_DmP_mant_SFG_SWR[22]), .C1(n3030), .Y(n3246) );
XOR2X1TS U1920 ( .A(n3238), .B(n3237), .Y(FPADDSUB_Raw_mant_SGF[19]) );
ADDFHX2TS U1921 ( .A(n1813), .B(n1812), .CI(n1811), .CO(n2010), .S(n1855) );
OAI211X1TS U1922 ( .A0(n2926), .A1(n2873), .B0(n2930), .C0(n2875), .Y(
FPADDSUB_Data_array_SWR[0]) );
ADDFX1TS U1923 ( .A(n1823), .B(n1822), .CI(n1821), .CO(n2006), .S(n1824) );
ADDFHX2TS U1924 ( .A(n1862), .B(n1861), .CI(n1860), .CO(n1854), .S(n1914) );
AOI222X4TS U1925 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .B0(FPADDSUB_DMP_SFG[18]), .B1(n2878),
.C0(FPADDSUB_DmP_mant_SFG_SWR[20]), .C1(n2878), .Y(n3239) );
OAI21X1TS U1926 ( .A0(n3280), .A1(n3279), .B0(n2987), .Y(
FPADDSUB_Data_array_SWR[25]) );
ADDFHX2TS U1927 ( .A(n1779), .B(n1778), .CI(n1777), .CO(n1813), .S(n1847) );
OR2X2TS U1928 ( .A(n2098), .B(n2097), .Y(n2120) );
ADDFHX2TS U1929 ( .A(n1908), .B(n1907), .CI(n1906), .CO(n1915), .S(n1949) );
ADDFHX2TS U1930 ( .A(n1853), .B(n1852), .CI(n1851), .CO(n1862), .S(n1918) );
ADDFHX2TS U1931 ( .A(n1936), .B(n1935), .CI(n1934), .CO(n1937), .S(n1952) );
OAI21X1TS U1932 ( .A0(n2813), .A1(n2816), .B0(n2812), .Y(n2811) );
XOR2X1TS U1933 ( .A(n3233), .B(n3232), .Y(FPADDSUB_Raw_mant_SGF[17]) );
OR2X2TS U1934 ( .A(n2077), .B(n2076), .Y(n2097) );
ADDFHX2TS U1935 ( .A(n1758), .B(n1757), .CI(n1756), .CO(n1754), .S(n1779) );
BUFX4TS U1936 ( .A(n2814), .Y(n3279) );
ADDFHX2TS U1937 ( .A(n1360), .B(n2357), .CI(n1359), .CO(n1354), .S(n2830) );
NAND2X2TS U1938 ( .A(n2885), .B(n2874), .Y(n2814) );
ADDFHX2TS U1939 ( .A(DP_OP_496J312_122_3540_n565), .B(n2022), .CI(n2021),
.CO(n2047), .S(n2015) );
ADDFHX2TS U1940 ( .A(n1802), .B(n1801), .CI(n1800), .CO(n1807), .S(n1830) );
MX2X4TS U1941 ( .A(DP_OP_496J312_122_3540_n830), .B(
DP_OP_496J312_122_3540_n829), .S0(DP_OP_496J312_122_3540_n833), .Y(
DP_OP_496J312_122_3540_n828) );
ADDFHX2TS U1942 ( .A(n2042), .B(n2041), .CI(n2040), .CO(n2077), .S(n2048) );
AOI222X4TS U1943 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(FPADDSUB_DMP_SFG[16]), .B1(n2817),
.C0(FPADDSUB_DmP_mant_SFG_SWR[18]), .C1(n2817), .Y(n3234) );
OAI21X1TS U1944 ( .A0(n2807), .A1(n2809), .B0(n2806), .Y(n2805) );
OR2X2TS U1945 ( .A(DP_OP_497J312_123_1725_n23), .B(
DP_OP_497J312_123_1725_n27), .Y(n1410) );
ADDFHX2TS U1946 ( .A(DP_OP_498J312_124_1725_n34), .B(
DP_OP_498J312_124_1725_n39), .CI(n1307), .CO(n1304), .S(n1365) );
XOR2X1TS U1947 ( .A(n3228), .B(n3227), .Y(FPADDSUB_Raw_mant_SGF[15]) );
OAI21X1TS U1948 ( .A0(n2801), .A1(n2803), .B0(n2800), .Y(n2799) );
NOR2X1TS U1949 ( .A(n2131), .B(n2123), .Y(n2124) );
BUFX3TS U1950 ( .A(n2587), .Y(n954) );
INVX2TS U1951 ( .A(n2205), .Y(n1887) );
INVX2TS U1952 ( .A(DP_OP_496J312_122_3540_n573), .Y(n1802) );
ADDFHX2TS U1953 ( .A(n1904), .B(n1903), .CI(n1902), .CO(n1932), .S(n1964) );
ADDFHX2TS U1954 ( .A(n1581), .B(n1580), .CI(n1579), .CO(
DP_OP_496J312_122_3540_n567), .S(DP_OP_496J312_122_3540_n568) );
ADDFHX2TS U1955 ( .A(DP_OP_498J312_124_1725_n40), .B(
DP_OP_498J312_124_1725_n45), .CI(n1311), .CO(n1307), .S(n1370) );
ADDHX2TS U1956 ( .A(n1840), .B(n1839), .CO(n1877), .S(n1888) );
AOI222X4TS U1957 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(FPADDSUB_DMP_SFG[14]), .B1(n2810),
.C0(FPADDSUB_DmP_mant_SFG_SWR[16]), .C1(n2810), .Y(n3229) );
NOR2X1TS U1958 ( .A(n2131), .B(n2069), .Y(n2101) );
INVX2TS U1959 ( .A(DP_OP_496J312_122_3540_n1013), .Y(n1811) );
INVX2TS U1960 ( .A(DP_OP_496J312_122_3540_n563), .Y(n2042) );
NOR2X1TS U1961 ( .A(n2131), .B(n2051), .Y(n2078) );
ADDFHX2TS U1962 ( .A(DP_OP_498J312_124_1725_n46), .B(
DP_OP_498J312_124_1725_n51), .CI(n1315), .CO(n1311), .S(n1380) );
XOR2X1TS U1963 ( .A(n2795), .B(n2794), .Y(FPADDSUB_Raw_mant_SGF[13]) );
ADDFHX2TS U1964 ( .A(n1622), .B(n1621), .CI(n1620), .CO(
DP_OP_496J312_122_3540_n573), .S(DP_OP_496J312_122_3540_n574) );
ADDFHX2TS U1965 ( .A(n1649), .B(n1648), .CI(n1647), .CO(
DP_OP_496J312_122_3540_n1017), .S(n1905) );
NOR3X1TS U1966 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n2773), .Y(n3752) );
OAI31X1TS U1967 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n2550), .A2(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n2549), .Y(n2985) );
ADDFHX2TS U1968 ( .A(n1596), .B(n1595), .CI(n1594), .CO(n1652), .S(n1648) );
OAI21X1TS U1969 ( .A0(n2779), .A1(n2792), .B0(n2778), .Y(n2777) );
XNOR2X1TS U1970 ( .A(n2081), .B(n2050), .Y(n2017) );
NOR2X6TS U1971 ( .A(n3748), .B(n3749), .Y(n2587) );
AOI222X4TS U1972 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(FPADDSUB_DMP_SFG[12]), .B1(n2804),
.C0(FPADDSUB_DmP_mant_SFG_SWR[14]), .C1(n2804), .Y(n3224) );
OAI22X2TS U1973 ( .A0(n1619), .A1(n1894), .B0(n1613), .B1(n1034), .Y(n1620)
);
XNOR2X2TS U1974 ( .A(n1618), .B(n1789), .Y(n1612) );
AND3X2TS U1975 ( .A(n2527), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n2526),
.Y(n3749) );
OAI22X2TS U1976 ( .A0(n1572), .A1(n1661), .B0(n1569), .B1(n1662), .Y(n1589)
);
ADDFHX2TS U1977 ( .A(n1604), .B(n1603), .CI(n1602), .CO(n1624), .S(n1650) );
ADDFHX2TS U1978 ( .A(n1643), .B(n1640), .CI(n1639), .CO(n1645), .S(n1623) );
XOR2X1TS U1979 ( .A(n2771), .B(n2770), .Y(FPADDSUB_Raw_mant_SGF[11]) );
NOR2X1TS U1980 ( .A(n1630), .B(n1664), .Y(n1668) );
NAND2BX1TS U1981 ( .AN(n2969), .B(n977), .Y(n2978) );
ADDFHX2TS U1982 ( .A(DP_OP_498J312_124_1725_n65), .B(
DP_OP_498J312_124_1725_n69), .CI(n1321), .CO(n1317), .S(n2263) );
XNOR2X1TS U1983 ( .A(n2081), .B(n1880), .Y(n1783) );
XNOR2X1TS U1984 ( .A(n2081), .B(n2023), .Y(n1817) );
OAI21X1TS U1985 ( .A0(n2764), .A1(n2768), .B0(n2763), .Y(n2762) );
AO21X1TS U1986 ( .A0(n2072), .A1(n2071), .B0(n2070), .Y(n2100) );
ADDFHX2TS U1987 ( .A(n1229), .B(n1228), .CI(n1227), .CO(n1206), .S(n1875) );
OAI22X2TS U1988 ( .A0(n1569), .A1(n1661), .B0(n1662), .B1(n1568), .Y(n1610)
);
NAND2X1TS U1989 ( .A(n1015), .B(n1723), .Y(n1721) );
ADDHX2TS U1990 ( .A(n1237), .B(n1236), .CO(n1228), .S(n1871) );
OR2X2TS U1991 ( .A(n1717), .B(n1716), .Y(n1015) );
INVX4TS U1992 ( .A(n919), .Y(n968) );
OAI21X2TS U1993 ( .A0(n1776), .A1(n1772), .B0(n1773), .Y(n1781) );
AOI31X1TS U1994 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n2557), .A2(n3575),
.B0(n2556), .Y(n2558) );
NOR2X1TS U1995 ( .A(n2286), .B(n2277), .Y(n1295) );
NAND2X1TS U1996 ( .A(n1746), .B(n1762), .Y(n1741) );
AO21X1TS U1997 ( .A0(n2380), .A1(n2377), .B0(n2379), .Y(
DP_OP_498J312_124_1725_n101) );
OAI32X1TS U1998 ( .A0(n2433), .A1(n2432), .A2(n980), .B0(n2431), .B1(n1063),
.Y(DP_OP_497J312_123_1725_n121) );
OAI32X1TS U1999 ( .A0(n2433), .A1(n2418), .A2(n980), .B0(n2417), .B1(n1063),
.Y(DP_OP_497J312_123_1725_n122) );
NOR2X1TS U2000 ( .A(n2488), .B(n978), .Y(DP_OP_497J312_123_1725_n100) );
XOR2X1TS U2001 ( .A(n1722), .B(n1717), .Y(n919) );
NAND2X2TS U2002 ( .A(n988), .B(n1711), .Y(n1780) );
OAI32X1TS U2003 ( .A0(n2433), .A1(n2420), .A2(DP_OP_497J312_123_1725_n119),
.B0(n2419), .B1(n1063), .Y(DP_OP_497J312_123_1725_n123) );
AO21X1TS U2004 ( .A0(n2366), .A1(n2369), .B0(n2301), .Y(
DP_OP_498J312_124_1725_n110) );
INVX2TS U2005 ( .A(n2453), .Y(n2454) );
OAI211X1TS U2006 ( .A0(operation[1]), .A1(n2532), .B0(n2531), .C0(n2530),
.Y(add_subt_data2[5]) );
OAI211X1TS U2007 ( .A0(operation[1]), .A1(n2535), .B0(n2534), .C0(n2533),
.Y(add_subt_data2[3]) );
OAI211X1TS U2008 ( .A0(operation[1]), .A1(n2522), .B0(n2521), .C0(n2520),
.Y(add_subt_data2[15]) );
OAI211X1TS U2009 ( .A0(operation[1]), .A1(n2519), .B0(n2518), .C0(n2528),
.Y(add_subt_data2[7]) );
OAI211X1TS U2010 ( .A0(operation[1]), .A1(n2503), .B0(n2502), .C0(n2530),
.Y(add_subt_data2[14]) );
OAI211X1TS U2011 ( .A0(operation[1]), .A1(n2507), .B0(n2506), .C0(n2533),
.Y(add_subt_data2[16]) );
OAI211X1TS U2012 ( .A0(operation[1]), .A1(n2512), .B0(n2511), .C0(n2510),
.Y(add_subt_data2[18]) );
NAND3BX1TS U2013 ( .AN(n3080), .B(n3078), .C(n3077), .Y(n3097) );
XNOR2X1TS U2014 ( .A(n1771), .B(n1717), .Y(n1518) );
XNOR2X1TS U2015 ( .A(n1770), .B(n988), .Y(n1638) );
XNOR2X2TS U2016 ( .A(n1162), .B(n1161), .Y(n1722) );
XNOR2X1TS U2017 ( .A(n1771), .B(n988), .Y(n1601) );
NOR2X1TS U2018 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n2979), .Y(n2538) );
NAND2BX1TS U2019 ( .AN(n2979), .B(FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n2974)
);
XNOR2X1TS U2020 ( .A(n1692), .B(n988), .Y(n1191) );
CLKINVX3TS U2021 ( .A(n3141), .Y(n957) );
CLKINVX3TS U2022 ( .A(n3143), .Y(n959) );
NOR2XLTS U2023 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n3504), .Y(n3503) );
OAI32X1TS U2024 ( .A0(n2433), .A1(n2424), .A2(DP_OP_497J312_123_1725_n119),
.B0(n2423), .B1(n1063), .Y(DP_OP_497J312_123_1725_n125) );
CLKINVX3TS U2025 ( .A(n3145), .Y(n961) );
CLKINVX3TS U2026 ( .A(n3140), .Y(n955) );
NOR2XLTS U2027 ( .A(FPSENCOS_d_ff2_X[29]), .B(n3507), .Y(n3506) );
AOI31X1TS U2028 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n2555), .A2(n2554),
.B0(n2971), .Y(n2559) );
AOI22X4TS U2029 ( .A0(n2429), .A1(n2450), .B0(n2413), .B1(
DP_OP_497J312_123_1725_n119), .Y(n2412) );
AOI31X1TS U2030 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(n2555), .A2(n3562),
.B0(n2971), .Y(n2547) );
AO22X1TS U2031 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n3605), .B1(n3476),
.Y(n3478) );
XNOR2X2TS U2032 ( .A(n1692), .B(n1685), .Y(n1732) );
NAND2BXLTS U2033 ( .AN(n3311), .B(n3310), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
XOR2X2TS U2034 ( .A(n1175), .B(n1201), .Y(n1712) );
AOI21X1TS U2035 ( .A0(n1213), .A1(n1220), .B0(n1212), .Y(n1218) );
NOR2XLTS U2036 ( .A(n2665), .B(n2652), .Y(FPMULT_FSM_first_phase_load) );
INVX3TS U2037 ( .A(n3287), .Y(n3288) );
OAI21XLTS U2038 ( .A0(n2703), .A1(n2700), .B0(n3604), .Y(n834) );
NOR2XLTS U2039 ( .A(n2758), .B(n857), .Y(FPSENCOS_ITER_CONT_N5) );
OAI211X1TS U2040 ( .A0(n3039), .A1(n3094), .B0(n3038), .C0(n3037), .Y(n3044)
);
NOR2X4TS U2041 ( .A(n966), .B(n2597), .Y(n2595) );
NAND3XLTS U2042 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n2653), .C(n3139),
.Y(n2657) );
OR2X1TS U2043 ( .A(n3142), .B(n3604), .Y(n3140) );
OR2X1TS U2044 ( .A(n3604), .B(n3144), .Y(n3141) );
NOR2XLTS U2045 ( .A(n3023), .B(n3282), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]) );
NOR2XLTS U2046 ( .A(n3005), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]) );
OR2X1TS U2047 ( .A(FPMULT_FSM_selector_C), .B(n3144), .Y(n3145) );
NOR2XLTS U2048 ( .A(n3024), .B(n3282), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]) );
NOR2XLTS U2049 ( .A(n3002), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]) );
OR2X1TS U2050 ( .A(FPMULT_FSM_selector_C), .B(n3142), .Y(n3143) );
NOR2XLTS U2051 ( .A(n2999), .B(n3282), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]) );
NOR2XLTS U2052 ( .A(n938), .B(n3282), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]) );
NOR2XLTS U2053 ( .A(n926), .B(n3282), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]) );
INVX1TS U2054 ( .A(n2916), .Y(n2928) );
NAND2X4TS U2055 ( .A(n966), .B(n3577), .Y(n2579) );
OAI21X2TS U2056 ( .A0(n1045), .A1(n1174), .B0(n1044), .Y(n1157) );
CLKBUFX3TS U2057 ( .A(n2581), .Y(n939) );
NAND3XLTS U2058 ( .A(n3526), .B(n3139), .C(n2653), .Y(n2700) );
BUFX3TS U2059 ( .A(n3359), .Y(n3384) );
OAI21X1TS U2060 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(n969), .B0(n3265),
.Y(n3263) );
NAND3XLTS U2061 ( .A(enab_cont_iter), .B(n3465), .C(n3424), .Y(n3310) );
NAND3BXLTS U2062 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n2707), .Y(n2756) );
NAND2X1TS U2063 ( .A(n1220), .B(n1219), .Y(n1221) );
NOR2X1TS U2064 ( .A(n1558), .B(n1560), .Y(n1526) );
NOR2X1TS U2065 ( .A(n1582), .B(n914), .Y(n1583) );
AO22XLTS U2066 ( .A0(operation[2]), .A1(n3342), .B0(n3343), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
NOR2X4TS U2067 ( .A(n965), .B(n2597), .Y(n2585) );
BUFX3TS U2068 ( .A(n3716), .Y(n917) );
OR2X2TS U2069 ( .A(n1532), .B(DP_OP_496J312_122_3540_n686), .Y(n1025) );
NOR2X1TS U2070 ( .A(n3059), .B(FPADDSUB_intDY_EWSW[10]), .Y(n3060) );
INVX1TS U2071 ( .A(n2961), .Y(n2963) );
INVX1TS U2072 ( .A(n2970), .Y(n2972) );
INVX2TS U2073 ( .A(n1534), .Y(n1522) );
CLKAND2X2TS U2074 ( .A(n914), .B(FPMULT_Op_MX[19]), .Y(n1081) );
NAND3X1TS U2075 ( .A(n3639), .B(n3036), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n3038) );
CLKINVX3TS U2076 ( .A(n2621), .Y(n2580) );
NOR2X1TS U2077 ( .A(n3093), .B(FPADDSUB_intDY_EWSW[24]), .Y(n3035) );
OAI21X1TS U2078 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n2544), .B0(n3569),
.Y(n2545) );
NOR2X4TS U2079 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n2624), .Y(n2581)
);
OAI211X2TS U2080 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n3627), .B0(n3109),
.C0(n3076), .Y(n3085) );
OAI211X2TS U2081 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n3584), .B0(n3071),
.C0(n3057), .Y(n3073) );
OR2X1TS U2082 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n2723), .Y(n935) );
NOR2X1TS U2083 ( .A(n3509), .B(n1009), .Y(n2393) );
NAND2BX1TS U2084 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n3037) );
NAND2BX1TS U2085 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n3036) );
CLKAND2X2TS U2086 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MX[19]), .Y(n1080) );
OAI21X1TS U2087 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n3633), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n3067) );
NOR2X1TS U2088 ( .A(n3509), .B(n1012), .Y(n2456) );
NOR2X1TS U2089 ( .A(n990), .B(n922), .Y(n2457) );
OR2X2TS U2090 ( .A(FPADDSUB_N60), .B(FPADDSUB_N59), .Y(n3221) );
NOR2X1TS U2091 ( .A(n1006), .B(n3510), .Y(n2397) );
NOR2X1TS U2092 ( .A(n1009), .B(n922), .Y(n2459) );
NOR2X1TS U2093 ( .A(n3509), .B(n990), .Y(n2458) );
NOR2X1TS U2094 ( .A(n1006), .B(n921), .Y(n2396) );
AND2X2TS U2095 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n3554), .Y(n2768) );
NAND2BX1TS U2096 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n3091) );
NAND2BX1TS U2097 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n3061) );
NOR2X1TS U2098 ( .A(n1012), .B(n922), .Y(n2460) );
NOR2X1TS U2099 ( .A(n990), .B(n921), .Y(n2461) );
NAND2BX1TS U2100 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n3057) );
NAND2BX1TS U2101 ( .AN(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(n3521), .Y(n2551)
);
NOR2X1TS U2102 ( .A(n1012), .B(n921), .Y(n2462) );
NOR2X1TS U2103 ( .A(n990), .B(n3510), .Y(n2463) );
NOR2X1TS U2104 ( .A(n1009), .B(n1026), .Y(n1060) );
NAND2BX1TS U2105 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n3082) );
NOR2X1TS U2106 ( .A(FPADDSUB_Raw_mant_NRM_SWR[20]), .B(
FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n2553) );
NAND2BX1TS U2107 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n3076) );
NOR2X1TS U2108 ( .A(n1012), .B(n3510), .Y(n1266) );
NOR2X1TS U2109 ( .A(n3509), .B(n933), .Y(n1101) );
NOR2X1TS U2110 ( .A(DP_OP_496J312_122_3540_n683), .B(n1007), .Y(n1055) );
NOR2X1TS U2111 ( .A(n3509), .B(n1008), .Y(n1096) );
NOR2X1TS U2112 ( .A(DP_OP_496J312_122_3540_n686), .B(n1007), .Y(n1284) );
NOR2X1TS U2113 ( .A(DP_OP_496J312_122_3540_n686), .B(n995), .Y(n2321) );
NOR2X1TS U2114 ( .A(DP_OP_498J312_124_1725_n376), .B(
DP_OP_498J312_124_1725_n381), .Y(n2320) );
NOR2X1TS U2115 ( .A(DP_OP_496J312_122_3540_n686), .B(n1018), .Y(n2324) );
NOR2X1TS U2116 ( .A(DP_OP_496J312_122_3540_n683), .B(n995), .Y(n2323) );
NOR2X1TS U2117 ( .A(DP_OP_496J312_122_3540_n686), .B(n1021), .Y(n2327) );
NOR2X1TS U2118 ( .A(DP_OP_498J312_124_1725_n378), .B(n1018), .Y(n1313) );
NOR2X1TS U2119 ( .A(n1016), .B(DP_OP_498J312_124_1725_n289), .Y(n1319) );
NOR2X1TS U2120 ( .A(DP_OP_498J312_124_1725_n283), .B(
DP_OP_498J312_124_1725_n289), .Y(n1323) );
OR2X2TS U2121 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n992) );
NOR2X1TS U2122 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n1529) );
AO22XLTS U2123 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n3343),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
XNOR2X2TS U2124 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n1584) );
XNOR2X2TS U2125 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n1554) );
OR2X2TS U2126 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n1017) );
NOR2X1TS U2127 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n1549) );
NOR2X2TS U2128 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[10]), .Y(n1560) );
ADDHX2TS U2129 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[0]), .CO(n1291), .S(
n1140) );
AND2X2TS U2130 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MX[22]), .Y(
DP_OP_497J312_123_1725_n345) );
NOR2X6TS U2131 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n2577) );
NOR2X1TS U2132 ( .A(n999), .B(n991), .Y(n2317) );
NOR2X1TS U2133 ( .A(DP_OP_498J312_124_1725_n283), .B(n1002), .Y(n2318) );
NOR2X1TS U2134 ( .A(n993), .B(DP_OP_498J312_124_1725_n289), .Y(n2351) );
NOR2X1TS U2135 ( .A(n999), .B(n1004), .Y(n2311) );
NOR2X1TS U2136 ( .A(n923), .B(n1004), .Y(n2352) );
NOR2X1TS U2137 ( .A(DP_OP_498J312_124_1725_n283), .B(n927), .Y(n2315) );
NOR2X1TS U2138 ( .A(n1016), .B(n991), .Y(n2314) );
NOR2X1TS U2139 ( .A(n999), .B(n1005), .Y(n2316) );
NOR2X4TS U2140 ( .A(n953), .B(operation[2]), .Y(n2648) );
NAND3X1TS U2141 ( .A(n3201), .B(n3200), .C(n3199), .Y(n3650) );
INVX4TS U2142 ( .A(rst), .Y(n2567) );
XOR2X2TS U2143 ( .A(n2173), .B(n2172), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
NAND2X2TS U2144 ( .A(n2784), .B(n2783), .Y(n2785) );
NOR2X1TS U2145 ( .A(DP_OP_498J312_124_1725_n378), .B(n1021), .Y(n1154) );
NOR2X1TS U2146 ( .A(DP_OP_498J312_124_1725_n378), .B(n995), .Y(n1050) );
XNOR2X2TS U2147 ( .A(n2273), .B(n1293), .Y(n2267) );
NOR2X1TS U2148 ( .A(DP_OP_498J312_124_1725_n376), .B(n1021), .Y(n1049) );
INVX2TS U2149 ( .A(n2152), .Y(n2160) );
XNOR2X2TS U2150 ( .A(n2162), .B(n2161), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
OAI21X4TS U2151 ( .A0(n1536), .A1(n1524), .B0(n1523), .Y(n1541) );
NOR2X4TS U2152 ( .A(n2002), .B(n2001), .Y(n2164) );
ADDFHX2TS U2153 ( .A(n1365), .B(n2355), .CI(n1364), .CO(n1359), .S(n2833) );
ADDFHX2TS U2154 ( .A(n1370), .B(n2330), .CI(n1369), .CO(n1364), .S(n2781) );
ADDFHX2TS U2155 ( .A(n1380), .B(n2383), .CI(n1379), .CO(n1369), .S(n2835) );
INVX6TS U2156 ( .A(n2229), .Y(n1453) );
ADDHX1TS U2157 ( .A(n1145), .B(n1144), .CO(n1141), .S(n1268) );
CMPR42X2TS U2158 ( .A(DP_OP_498J312_124_1725_n86), .B(
DP_OP_498J312_124_1725_n124), .C(DP_OP_498J312_124_1725_n72), .D(
DP_OP_498J312_124_1725_n117), .ICI(DP_OP_498J312_124_1725_n91), .S(
DP_OP_498J312_124_1725_n70), .ICO(DP_OP_498J312_124_1725_n68), .CO(
DP_OP_498J312_124_1725_n69) );
AOI21X4TS U2159 ( .A0(n1032), .A1(n2180), .B0(n1996), .Y(n2177) );
OAI21X1TS U2160 ( .A0(n1736), .A1(n1759), .B0(n1735), .Y(n1738) );
CMPR22X2TS U2161 ( .A(n1427), .B(n1426), .CO(n1425), .S(n1505) );
ADDFHX4TS U2162 ( .A(DP_OP_499J312_125_1651_n56), .B(n1276), .CI(n1275),
.CO(n1391), .S(n1487) );
ADDFHX2TS U2163 ( .A(DP_OP_499J312_125_1651_n59), .B(n1278), .CI(n1277),
.CO(n1275), .S(n1514) );
ADDFHX4TS U2164 ( .A(DP_OP_499J312_125_1651_n35), .B(n1464), .CI(n1463),
.CO(n1468), .S(n1466) );
AFHCINX4TS U2165 ( .CIN(n1513), .B(n1514), .A(n2437), .S(
FPMULT_Sgf_operation_Result[26]), .CO(n1486) );
AFHCINX4TS U2166 ( .CIN(n2859), .B(n2860), .A(n2861), .S(n2868), .CO(n2852)
);
XNOR2X2TS U2167 ( .A(n2373), .B(n2372), .Y(n2382) );
CMPR42X2TS U2168 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
DP_OP_499J312_125_1651_n95), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .D(
DP_OP_499J312_125_1651_n36), .ICI(DP_OP_499J312_125_1651_n37), .S(
DP_OP_499J312_125_1651_n35), .ICO(DP_OP_499J312_125_1651_n33), .CO(
DP_OP_499J312_125_1651_n34) );
XNOR2X2TS U2169 ( .A(n1629), .B(n1789), .Y(n1587) );
OAI21X2TS U2170 ( .A0(n2164), .A1(n2170), .B0(n2165), .Y(n2003) );
XOR2X4TS U2171 ( .A(n1533), .B(FPMULT_Op_MX[11]), .Y(n1629) );
OAI22X4TS U2172 ( .A0(n1493), .A1(n1028), .B0(n2255), .B1(n1494), .Y(n1395)
);
XNOR2X2TS U2173 ( .A(n2307), .B(n2372), .Y(n2374) );
ADDFHX4TS U2174 ( .A(n1460), .B(DP_OP_499J312_125_1651_n38), .CI(n1459),
.CO(n1463), .S(n1462) );
ADDFHX2TS U2175 ( .A(FPMULT_Op_MY[8]), .B(n1704), .CI(n1703), .CO(n1707),
.S(n1705) );
AO21X2TS U2176 ( .A0(n1030), .A1(n2190), .B0(n1988), .Y(n928) );
OAI21X1TS U2177 ( .A0(n1727), .A1(n1729), .B0(n1740), .Y(n1688) );
ADDFHX2TS U2178 ( .A(n1317), .B(DP_OP_498J312_124_1725_n64), .CI(
DP_OP_498J312_124_1725_n58), .CO(n1316), .S(n2257) );
AFHCINX4TS U2179 ( .CIN(n1395), .B(n1396), .A(n1397), .S(
FPMULT_Sgf_operation_Result[24]), .CO(n1398) );
AFHCINX4TS U2180 ( .CIN(n1490), .B(n1491), .A(n1492), .S(
FPMULT_Sgf_operation_Result[30]), .CO(n2229) );
NAND2X4TS U2181 ( .A(n2176), .B(n2175), .Y(n2178) );
ADDFHX4TS U2182 ( .A(DP_OP_499J312_125_1651_n32), .B(n916), .CI(n1468), .CO(
n1438), .S(n1470) );
NAND2X4TS U2183 ( .A(n1998), .B(n1997), .Y(n2175) );
CLKXOR2X4TS U2184 ( .A(n1714), .B(n1719), .Y(n2050) );
ADDFHX4TS U2185 ( .A(DP_OP_499J312_125_1651_n68), .B(n1384), .CI(n1383),
.CO(n1281), .S(n1494) );
AFCSIHCONX2TS U2186 ( .A(DP_OP_496J312_122_3540_n1017), .B(
DP_OP_496J312_122_3540_n1016), .CS(DP_OP_496J312_122_3540_n833), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .CO0N(
DP_OP_496J312_122_3540_n832), .CO1N(DP_OP_496J312_122_3540_n831) );
NAND2X6TS U2187 ( .A(n1184), .B(n987), .Y(n1637) );
ADDFHX2TS U2188 ( .A(n1954), .B(n1953), .CI(n1952), .CO(n1947), .S(n1990) );
NAND2X2TS U2189 ( .A(n1738), .B(n1737), .Y(n1746) );
CMPR42X2TS U2190 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
DP_OP_499J312_125_1651_n100), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .D(
DP_OP_499J312_125_1651_n51), .ICI(DP_OP_499J312_125_1651_n52), .S(
DP_OP_499J312_125_1651_n50), .ICO(DP_OP_499J312_125_1651_n48), .CO(
DP_OP_499J312_125_1651_n49) );
CMPR42X2TS U2191 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
DP_OP_499J312_125_1651_n101), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .D(
DP_OP_499J312_125_1651_n54), .ICI(DP_OP_499J312_125_1651_n55), .S(
DP_OP_499J312_125_1651_n53), .ICO(DP_OP_499J312_125_1651_n51), .CO(
DP_OP_499J312_125_1651_n52) );
OAI22X2TS U2192 ( .A0(n1637), .A1(n1199), .B0(n1198), .B1(n987), .Y(n1236)
);
ADDFHX4TS U2193 ( .A(n1905), .B(n1828), .CI(n1394), .CO(
DP_OP_496J312_122_3540_n833), .S(n1248) );
AOI21X4TS U2194 ( .A0(n1177), .A1(n1022), .B0(n1042), .Y(n1174) );
ADDFHX4TS U2195 ( .A(n1455), .B(DP_OP_499J312_125_1651_n41), .CI(n1454),
.CO(n1459), .S(n1457) );
CMPR42X2TS U2196 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
DP_OP_499J312_125_1651_n97), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .D(
DP_OP_499J312_125_1651_n42), .ICI(DP_OP_499J312_125_1651_n43), .S(
DP_OP_499J312_125_1651_n41), .ICO(DP_OP_499J312_125_1651_n39), .CO(
DP_OP_499J312_125_1651_n40) );
ADDFHX4TS U2197 ( .A(n2243), .B(DP_OP_499J312_125_1651_n44), .CI(n1450),
.CO(n1454), .S(n1452) );
ADDFHX4TS U2198 ( .A(DP_OP_499J312_125_1651_n47), .B(n1447), .CI(n1446),
.CO(n1450), .S(n1491) );
CMPR42X2TS U2199 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
DP_OP_499J312_125_1651_n99), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .D(
DP_OP_499J312_125_1651_n48), .ICI(DP_OP_499J312_125_1651_n49), .S(
DP_OP_499J312_125_1651_n47), .ICO(DP_OP_499J312_125_1651_n45), .CO(
DP_OP_499J312_125_1651_n46) );
ADDFHX4TS U2200 ( .A(DP_OP_499J312_125_1651_n50), .B(n1435), .CI(n1434),
.CO(n1446), .S(n1448) );
ADDFHX2TS U2201 ( .A(n1808), .B(n1807), .CI(n1806), .CO(n1819), .S(n1851) );
ADDFHX2TS U2202 ( .A(n1578), .B(n1586), .CI(n1575), .CO(n1580), .S(n1591) );
OAI22X1TS U2203 ( .A0(n1573), .A1(n1661), .B0(n1572), .B1(n1662), .Y(n1575)
);
INVX2TS U2204 ( .A(n1213), .Y(n1222) );
NAND2X4TS U2205 ( .A(n1181), .B(n1180), .Y(n1183) );
INVX2TS U2206 ( .A(n1179), .Y(n1181) );
XOR2X1TS U2207 ( .A(n1555), .B(n1554), .Y(n1556) );
XOR2X1TS U2208 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[20]), .Y(n1553) );
OAI21X2TS U2209 ( .A0(n1720), .A1(n1719), .B0(n1718), .Y(n1725) );
INVX2TS U2210 ( .A(n1541), .Y(n1559) );
ADDFHX2TS U2211 ( .A(n1831), .B(n1830), .CI(n1829), .CO(n1853), .S(n1907) );
INVX2TS U2212 ( .A(DP_OP_496J312_122_3540_n1004), .Y(n2099) );
NOR2BX2TS U2213 ( .AN(n1759), .B(n975), .Y(n1227) );
INVX2TS U2214 ( .A(n1163), .Y(n1165) );
NAND2X1TS U2215 ( .A(n1160), .B(n1159), .Y(n1161) );
INVX2TS U2216 ( .A(n1158), .Y(n1160) );
ADDFHX2TS U2217 ( .A(n1593), .B(n1592), .CI(n1591), .CO(
DP_OP_496J312_122_3540_n569), .S(DP_OP_496J312_122_3540_n570) );
ADDFHX2TS U2218 ( .A(n1924), .B(n1923), .CI(n1922), .CO(n1906), .S(n1956) );
ADDHX1TS U2219 ( .A(n1838), .B(n1837), .CO(n2204), .S(n2208) );
NOR2X1TS U2220 ( .A(n2164), .B(n2169), .Y(n2004) );
INVX2TS U2221 ( .A(n1188), .Y(n1037) );
INVX2TS U2222 ( .A(n1185), .Y(n1169) );
INVX2TS U2223 ( .A(n2050), .Y(n2051) );
NOR2X1TS U2224 ( .A(n2131), .B(n1816), .Y(n2014) );
INVX2TS U2225 ( .A(n1880), .Y(n1816) );
NOR2BX1TS U2226 ( .AN(n972), .B(n2131), .Y(n1777) );
NOR2X1TS U2227 ( .A(n2131), .B(n1750), .Y(n1753) );
INVX2TS U2228 ( .A(n1896), .Y(n1750) );
INVX2TS U2229 ( .A(n1168), .Y(n1187) );
ADDFHX2TS U2230 ( .A(n1578), .B(n1577), .CI(n1576), .CO(n1627), .S(n1579) );
INVX2TS U2231 ( .A(n1795), .Y(n1544) );
NOR2X1TS U2232 ( .A(n1771), .B(n1764), .Y(n1765) );
NAND2X1TS U2233 ( .A(n1000), .B(n1173), .Y(n1175) );
INVX2TS U2234 ( .A(n1618), .Y(n1565) );
XOR2X1TS U2235 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[11]), .Y(n1532) );
OAI22X1TS U2236 ( .A0(n1613), .A1(n1894), .B0(n1586), .B1(n1034), .Y(n1616)
);
NOR2X1TS U2237 ( .A(n1684), .B(n1681), .Y(n1682) );
XOR2X1TS U2238 ( .A(n1693), .B(n1685), .Y(n1681) );
CLKAND2X2TS U2239 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[20]), .Y(n2470) );
CLKAND2X2TS U2240 ( .A(FPMULT_Op_MY[22]), .B(n912), .Y(n2469) );
XOR2X1TS U2241 ( .A(n2158), .B(n2157), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
NAND2X2TS U2242 ( .A(n2156), .B(n2155), .Y(n2157) );
CMPR42X2TS U2243 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
DP_OP_499J312_125_1651_n94), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .D(
DP_OP_499J312_125_1651_n33), .ICI(DP_OP_499J312_125_1651_n34), .S(
DP_OP_499J312_125_1651_n32), .ICO(DP_OP_499J312_125_1651_n30), .CO(
DP_OP_499J312_125_1651_n31) );
INVX2TS U2244 ( .A(n1747), .Y(n1706) );
NOR2X4TS U2245 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .Y(n1192) );
NAND2X2TS U2246 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .Y(n1193) );
XNOR2X1TS U2247 ( .A(n2081), .B(n2122), .Y(n2093) );
NAND2X1TS U2248 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[9]), .Y(n1527) );
OAI21X1TS U2249 ( .A0(FPMULT_Op_MY[21]), .A1(FPMULT_Op_MY[9]), .B0(
FPMULT_Op_MY[8]), .Y(n1528) );
XNOR2X1TS U2250 ( .A(n2081), .B(n1896), .Y(n1848) );
OAI22X1TS U2251 ( .A0(n1609), .A1(n1133), .B0(n968), .B1(n1608), .Y(n1602)
);
OAI22X1TS U2252 ( .A0(n1670), .A1(n1209), .B0(n1599), .B1(n975), .Y(n1594)
);
XOR2X1TS U2253 ( .A(n1732), .B(n1731), .Y(n1743) );
XOR2X1TS U2254 ( .A(n1729), .B(n1739), .Y(n1730) );
OAI22X1TS U2255 ( .A0(n1609), .A1(n1608), .B0(n968), .B1(n1607), .Y(n1639)
);
INVX2TS U2256 ( .A(n1214), .Y(n1216) );
OAI22X2TS U2257 ( .A0(n1631), .A1(n1662), .B0(n1661), .B1(n1664), .Y(n2043)
);
OAI22X1TS U2258 ( .A0(n1574), .A1(n1661), .B0(n1573), .B1(n1662), .Y(n1581)
);
NAND2X4TS U2259 ( .A(n1770), .B(n1764), .Y(n2131) );
INVX2TS U2260 ( .A(n1535), .Y(n1520) );
NAND2X1TS U2261 ( .A(n1732), .B(n1726), .Y(n1689) );
NOR2X1TS U2262 ( .A(n1692), .B(n1685), .Y(n1683) );
NOR2XLTS U2263 ( .A(DP_OP_498J312_124_1725_n377), .B(n1007), .Y(n2322) );
XNOR2X1TS U2264 ( .A(n2125), .B(n2124), .Y(n2130) );
NOR2X2TS U2265 ( .A(n2106), .B(n2105), .Y(n2152) );
ADDFHX2TS U2266 ( .A(n1834), .B(n1833), .CI(n1832), .CO(
DP_OP_496J312_122_3540_n575), .S(n2205) );
OAI22X1TS U2267 ( .A0(n1619), .A1(n1034), .B0(n1796), .B1(n1894), .Y(n1832)
);
NOR2X1TS U2268 ( .A(n995), .B(DP_OP_498J312_124_1725_n379), .Y(n1051) );
CLKAND2X2TS U2269 ( .A(FPMULT_Op_MY[21]), .B(n912), .Y(
DP_OP_497J312_123_1725_n358) );
INVX2TS U2270 ( .A(n2187), .Y(n1991) );
XOR2X1TS U2271 ( .A(n2144), .B(n2143), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
XNOR2X2TS U2272 ( .A(n2168), .B(n2167), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
NOR2X6TS U2273 ( .A(n1475), .B(n1474), .Y(n2248) );
AOI22X1TS U2274 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n3551), .B0(n2711), .B1(
n2710), .Y(n2716) );
AOI22X1TS U2275 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n3553), .B0(n2760), .B1(
n2759), .Y(n2767) );
AOI22X1TS U2276 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n3517), .B0(n2775), .B1(
n2774), .Y(n2791) );
INVX2TS U2277 ( .A(n1537), .Y(n1521) );
INVX2TS U2278 ( .A(n1895), .Y(n1815) );
ADDHX1TS U2279 ( .A(n1799), .B(n1798), .CO(n1756), .S(n1808) );
INVX2TS U2280 ( .A(DP_OP_496J312_122_3540_n570), .Y(n1798) );
INVX2TS U2281 ( .A(DP_OP_496J312_122_3540_n571), .Y(n1799) );
XNOR2X1TS U2282 ( .A(n2050), .B(n986), .Y(n1803) );
XNOR2X2TS U2283 ( .A(n1715), .B(FPMULT_Op_MY[11]), .Y(n1697) );
INVX2TS U2284 ( .A(n1634), .Y(n1578) );
INVX2TS U2285 ( .A(n2068), .Y(n2069) );
AOI21X2TS U2286 ( .A0(n1015), .A1(n1725), .B0(n1724), .Y(n1745) );
INVX2TS U2287 ( .A(n1723), .Y(n1724) );
INVX2TS U2288 ( .A(n2046), .Y(n2076) );
XNOR2X2TS U2289 ( .A(n1795), .B(n1571), .Y(n1572) );
INVX2TS U2290 ( .A(DP_OP_496J312_122_3540_n1007), .Y(n2074) );
ADDFX2TS U2291 ( .A(n2058), .B(n2057), .CI(n2056), .CO(n2065), .S(n2037) );
NOR2X1TS U2292 ( .A(n2131), .B(n2024), .Y(n2057) );
INVX2TS U2293 ( .A(n2023), .Y(n2024) );
INVX2TS U2294 ( .A(n1176), .Y(n1042) );
NAND2X1TS U2295 ( .A(n1705), .B(FPMULT_Op_MY[20]), .Y(n1747) );
OAI21X2TS U2296 ( .A0(n1702), .A1(n1701), .B0(n1700), .Y(n1749) );
AOI21X1TS U2297 ( .A0(n1781), .A1(n1014), .B0(n1713), .Y(n1719) );
NAND2X1TS U2298 ( .A(n1698), .B(n1697), .Y(n1718) );
ADDHX1TS U2299 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .CO(n1728), .S(
n1736) );
NAND2X1TS U2300 ( .A(n1736), .B(n1759), .Y(n1737) );
INVX2TS U2301 ( .A(n1793), .Y(n1867) );
NAND2X1TS U2302 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[3]), .Y(n1173) );
INVX2TS U2303 ( .A(n1173), .Y(n1200) );
NAND2X1TS U2304 ( .A(n1003), .B(n1170), .Y(n1171) );
AOI21X1TS U2305 ( .A0(n1187), .A1(n929), .B0(n1169), .Y(n1172) );
OAI21X2TS U2306 ( .A0(n1168), .A1(n1040), .B0(n1039), .Y(n1213) );
AOI21X1TS U2307 ( .A0(n1003), .A1(n1169), .B0(n1038), .Y(n1039) );
NAND2X1TS U2308 ( .A(n929), .B(n1003), .Y(n1040) );
INVX2TS U2309 ( .A(n1170), .Y(n1038) );
INVX2TS U2310 ( .A(n1211), .Y(n1220) );
INVX2TS U2311 ( .A(n1219), .Y(n1212) );
NAND2X4TS U2312 ( .A(DP_OP_496J312_122_3540_n686), .B(
DP_OP_496J312_122_3540_n683), .Y(n1571) );
AOI21X1TS U2313 ( .A0(n1541), .A1(n1526), .B0(n1525), .Y(n1533) );
XNOR2X2TS U2314 ( .A(n1663), .B(n1571), .Y(n1631) );
XNOR2X1TS U2315 ( .A(n2098), .B(n2097), .Y(n2091) );
INVX2TS U2316 ( .A(DP_OP_496J312_122_3540_n1006), .Y(n2067) );
OAI22X1TS U2317 ( .A0(n2094), .A1(n2055), .B0(n2092), .B1(n2082), .Y(n2066)
);
OAI22X1TS U2318 ( .A0(n2026), .A1(n2071), .B0(n2072), .B1(n1752), .Y(n2028)
);
INVX2TS U2319 ( .A(DP_OP_496J312_122_3540_n1011), .Y(n2011) );
OAI22X1TS U2320 ( .A0(n2094), .A1(n1817), .B0(n2092), .B1(n2017), .Y(n2012)
);
ADDFX2TS U2321 ( .A(n2038), .B(n2037), .CI(n2036), .CO(n2064), .S(n2059) );
INVX2TS U2322 ( .A(DP_OP_496J312_122_3540_n1008), .Y(n2038) );
INVX2TS U2323 ( .A(DP_OP_496J312_122_3540_n1009), .Y(n2053) );
NAND2X1TS U2324 ( .A(n1562), .B(n1561), .Y(n1563) );
INVX2TS U2325 ( .A(n1560), .Y(n1562) );
ADDFX2TS U2326 ( .A(n1847), .B(n1846), .CI(n1845), .CO(n1856), .S(n1910) );
OAI22X1TS U2327 ( .A0(n1810), .A1(n2020), .B0(n1751), .B1(n2019), .Y(n1822)
);
NAND2X1TS U2328 ( .A(n994), .B(n1537), .Y(n1538) );
OAI21X1TS U2329 ( .A0(n1536), .A1(n1535), .B0(n1534), .Y(n1539) );
CLKXOR2X2TS U2330 ( .A(n1559), .B(n1543), .Y(n1795) );
NAND2X1TS U2331 ( .A(n1542), .B(n1557), .Y(n1543) );
INVX2TS U2332 ( .A(n1558), .Y(n1542) );
NOR2X2TS U2333 ( .A(n913), .B(FPMULT_Op_MX[6]), .Y(n1214) );
NAND2X1TS U2334 ( .A(n913), .B(FPMULT_Op_MX[6]), .Y(n1215) );
NAND2X1TS U2335 ( .A(n1017), .B(n1000), .Y(n1045) );
AOI21X1TS U2336 ( .A0(n1017), .A1(n1200), .B0(n1043), .Y(n1044) );
INVX2TS U2337 ( .A(n1202), .Y(n1043) );
ADDFX2TS U2338 ( .A(n1843), .B(n1842), .CI(n1841), .CO(n1829), .S(n1923) );
NAND2BXLTS U2339 ( .AN(n972), .B(n1895), .Y(n1870) );
NAND2BXLTS U2340 ( .AN(n1759), .B(n988), .Y(n1232) );
OAI22X1TS U2341 ( .A0(n1231), .A1(n1134), .B0(n1230), .B1(n1597), .Y(n1797)
);
ADDHX1TS U2342 ( .A(n1207), .B(n1206), .CO(n1595), .S(n1225) );
OAI22X1TS U2343 ( .A0(n1637), .A1(n1197), .B0(n1191), .B1(n987), .Y(n1207)
);
NAND2X1TS U2344 ( .A(n1022), .B(n1176), .Y(n1178) );
NAND2X1TS U2345 ( .A(n1194), .B(n1193), .Y(n1196) );
INVX2TS U2346 ( .A(n1192), .Y(n1194) );
NAND2X1TS U2347 ( .A(n992), .B(n1188), .Y(n1190) );
INVX2TS U2348 ( .A(n1735), .Y(n1536) );
NAND2X1TS U2349 ( .A(n1699), .B(n1718), .Y(n1714) );
INVX2TS U2350 ( .A(n1720), .Y(n1699) );
NAND2X1TS U2351 ( .A(n1136), .B(n1135), .Y(n1700) );
NOR2X2TS U2352 ( .A(n1136), .B(n1135), .Y(n1701) );
CLKXOR2X2TS U2353 ( .A(n1736), .B(n1759), .Y(n1760) );
XNOR2X2TS U2354 ( .A(n1740), .B(n1739), .Y(n1762) );
NAND2X1TS U2355 ( .A(n1688), .B(n1687), .Y(n1726) );
NAND2X1TS U2356 ( .A(n1727), .B(n1729), .Y(n1687) );
NAND2X1TS U2357 ( .A(n929), .B(n1185), .Y(n1186) );
INVX2TS U2358 ( .A(n1727), .Y(n1607) );
INVX2TS U2359 ( .A(n1657), .Y(n1643) );
INVX2TS U2360 ( .A(n1703), .Y(n1657) );
INVX2TS U2361 ( .A(n1692), .Y(n1519) );
ADDFX2TS U2362 ( .A(n1890), .B(n1889), .CI(n1888), .CO(n1885), .S(n1966) );
INVX2TS U2363 ( .A(n1836), .Y(n1890) );
INVX2TS U2364 ( .A(n2208), .Y(n1889) );
XNOR2X1TS U2365 ( .A(n1896), .B(n1895), .Y(n1897) );
INVX2TS U2366 ( .A(n1694), .Y(n1653) );
NOR2X2TS U2367 ( .A(n2108), .B(n2107), .Y(n2154) );
INVX2TS U2368 ( .A(n2145), .Y(n2137) );
NAND2X2TS U2369 ( .A(n1533), .B(n1007), .Y(n1663) );
NOR2X2TS U2370 ( .A(n2112), .B(n2111), .Y(n2140) );
OAI21X1TS U2371 ( .A0(n2148), .A1(n2140), .B0(n2141), .Y(n2113) );
NOR2X1TS U2372 ( .A(n2096), .B(n2131), .Y(n2121) );
INVX2TS U2373 ( .A(n2095), .Y(n2096) );
ADDFX2TS U2374 ( .A(n2010), .B(n2009), .CI(n2008), .CO(n2034), .S(n2030) );
INVX2TS U2375 ( .A(DP_OP_496J312_122_3540_n1010), .Y(n2007) );
ADDFX2TS U2376 ( .A(n2061), .B(n2060), .CI(n2059), .CO(n2062), .S(n2033) );
XNOR2X1TS U2377 ( .A(n1529), .B(DP_OP_496J312_122_3540_n686), .Y(n1530) );
NAND2X1TS U2378 ( .A(n1545), .B(n1554), .Y(n1531) );
XNOR2X2TS U2379 ( .A(n1795), .B(n1789), .Y(n1617) );
INVX2TS U2380 ( .A(DP_OP_496J312_122_3540_n1012), .Y(n1826) );
XNOR2X1TS U2381 ( .A(n1552), .B(n1549), .Y(n1550) );
XNOR2X1TS U2382 ( .A(n2081), .B(n972), .Y(n1849) );
INVX2TS U2383 ( .A(DP_OP_496J312_122_3540_n1017), .Y(n1916) );
OAI22X1TS U2384 ( .A0(n1864), .A1(n1927), .B0(n1827), .B1(n915), .Y(n1917)
);
OAI22X1TS U2385 ( .A0(n1864), .A1(n915), .B0(n1879), .B1(n1927), .Y(n1938)
);
INVX2TS U2386 ( .A(n1905), .Y(n1950) );
OAI22X1TS U2387 ( .A0(n1598), .A1(n1597), .B0(n1657), .B1(n1134), .Y(n1651)
);
ADDFX2TS U2388 ( .A(n1625), .B(n1624), .CI(n1623), .CO(
DP_OP_496J312_122_3540_n1013), .S(DP_OP_496J312_122_3540_n1014) );
OAI22X1TS U2389 ( .A0(n1897), .A1(n915), .B0(n972), .B1(n1927), .Y(n1979) );
INVX2TS U2390 ( .A(n2213), .Y(n1980) );
NOR2BX1TS U2391 ( .AN(n972), .B(n915), .Y(n1982) );
OAI22X1TS U2392 ( .A0(n1226), .A1(n1134), .B0(n1231), .B1(n1597), .Y(n1844)
);
CMPR42X1TS U2393 ( .A(DP_OP_498J312_124_1725_n36), .B(
DP_OP_498J312_124_1725_n32), .C(DP_OP_498J312_124_1725_n79), .D(
DP_OP_498J312_124_1725_n193), .ICI(DP_OP_498J312_124_1725_n31), .S(
DP_OP_498J312_124_1725_n28), .ICO(DP_OP_498J312_124_1725_n26), .CO(
DP_OP_498J312_124_1725_n27) );
NAND2BXLTS U2394 ( .AN(n1759), .B(n1703), .Y(n1233) );
OAI22X1TS U2395 ( .A0(n1597), .A1(n1759), .B0(n1234), .B1(n1134), .Y(n1869)
);
INVX2TS U2396 ( .A(n1875), .Y(n1931) );
XNOR2X1TS U2397 ( .A(n1770), .B(n1717), .Y(n1654) );
OAI22X1TS U2398 ( .A0(n2020), .A1(n2018), .B0(n1881), .B1(n2019), .Y(n1968)
);
OAI22X1TS U2399 ( .A0(n1928), .A1(n915), .B0(n1898), .B1(n1927), .Y(n1969)
);
INVX2TS U2400 ( .A(n2212), .Y(n1972) );
OAI22X1TS U2401 ( .A0(n1898), .A1(n915), .B0(n1897), .B1(n1927), .Y(n1974)
);
CMPR42X1TS U2402 ( .A(DP_OP_497J312_123_1725_n114), .B(
DP_OP_497J312_123_1725_n61), .C(DP_OP_497J312_123_1725_n83), .D(
DP_OP_497J312_123_1725_n197), .ICI(DP_OP_497J312_123_1725_n100), .S(
DP_OP_497J312_123_1725_n55), .ICO(DP_OP_497J312_123_1725_n53), .CO(
DP_OP_497J312_123_1725_n54) );
ADDHXLTS U2403 ( .A(n2445), .B(n2444), .CO(DP_OP_497J312_123_1725_n331), .S(
DP_OP_497J312_123_1725_n332) );
CLKAND2X2TS U2404 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[18]), .Y(n2444) );
CLKAND2X2TS U2405 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MX[19]), .Y(n2467) );
CLKAND2X2TS U2406 ( .A(FPMULT_Op_MY[20]), .B(n976), .Y(n2466) );
CLKAND2X2TS U2407 ( .A(FPMULT_Op_MX[22]), .B(n914), .Y(n2468) );
INVX2TS U2408 ( .A(n2418), .Y(n2477) );
NOR2X2TS U2409 ( .A(n1678), .B(n1609), .Y(n2098) );
NAND2X4TS U2410 ( .A(n1205), .B(n975), .Y(n1670) );
INVX4TS U2411 ( .A(n932), .Y(n975) );
XOR2X1TS U2412 ( .A(n1698), .B(n988), .Y(n932) );
INVX2TS U2413 ( .A(n1771), .Y(n1671) );
OAI22X1TS U2414 ( .A0(n1609), .A1(n1653), .B0(n968), .B1(n1671), .Y(n1676)
);
INVX2TS U2415 ( .A(n1770), .Y(n1678) );
INVX2TS U2416 ( .A(n2154), .Y(n2156) );
AOI21X1TS U2417 ( .A0(n2162), .A1(n2160), .B0(n2153), .Y(n2158) );
INVX2TS U2418 ( .A(n2159), .Y(n2153) );
INVX2TS U2419 ( .A(n2140), .Y(n2142) );
AOI21X1TS U2420 ( .A0(n2162), .A1(n2139), .B0(n2138), .Y(n2144) );
INVX2TS U2421 ( .A(n2146), .Y(n2136) );
INVX2TS U2422 ( .A(n2043), .Y(n1667) );
INVX2TS U2423 ( .A(n1629), .Y(n1630) );
AO21X1TS U2424 ( .A0(n1662), .A1(n1661), .B0(n1664), .Y(n2045) );
INVX2TS U2425 ( .A(n1663), .Y(n1665) );
MXI2X2TS U2426 ( .A(DP_OP_496J312_122_3540_n547), .B(
DP_OP_496J312_122_3540_n546), .S0(DP_OP_496J312_122_3540_n552), .Y(
DP_OP_496J312_122_3540_n545) );
OAI32X1TS U2427 ( .A0(n2433), .A1(n2422), .A2(DP_OP_497J312_123_1725_n119),
.B0(n2421), .B1(n1063), .Y(DP_OP_497J312_123_1725_n124) );
ADDFX2TS U2428 ( .A(n1859), .B(n1858), .CI(n1857), .CO(n2001), .S(n2000) );
NAND2X1TS U2429 ( .A(n1520), .B(n1534), .Y(n1041) );
INVX2TS U2430 ( .A(DP_OP_496J312_122_3540_n1016), .Y(n1945) );
OAI22X1TS U2431 ( .A0(n2072), .A1(n2070), .B0(n1933), .B1(n2071), .Y(n1953)
);
NAND2BXLTS U2432 ( .AN(n972), .B(n985), .Y(n1933) );
INVX2TS U2433 ( .A(n1921), .Y(n1957) );
CMPR42X1TS U2434 ( .A(DP_OP_498J312_124_1725_n352), .B(
DP_OP_498J312_124_1725_n319), .C(DP_OP_498J312_124_1725_n317), .D(
DP_OP_498J312_124_1725_n313), .ICI(DP_OP_498J312_124_1725_n314), .S(
DP_OP_498J312_124_1725_n311), .ICO(DP_OP_498J312_124_1725_n309), .CO(
DP_OP_498J312_124_1725_n310) );
CMPR42X1TS U2435 ( .A(DP_OP_498J312_124_1725_n364), .B(
DP_OP_498J312_124_1725_n331), .C(DP_OP_498J312_124_1725_n328), .D(
DP_OP_498J312_124_1725_n327), .ICI(DP_OP_498J312_124_1725_n325), .S(
DP_OP_498J312_124_1725_n323), .ICO(DP_OP_498J312_124_1725_n321), .CO(
DP_OP_498J312_124_1725_n322) );
ADDFHX2TS U2436 ( .A(DP_OP_498J312_124_1725_n28), .B(
DP_OP_498J312_124_1725_n33), .CI(n1304), .CO(n1302), .S(n1360) );
NAND2X1TS U2437 ( .A(n1023), .B(n1195), .Y(n1133) );
CMPR42X1TS U2438 ( .A(DP_OP_498J312_124_1725_n53), .B(
DP_OP_498J312_124_1725_n82), .C(DP_OP_498J312_124_1725_n50), .D(
DP_OP_498J312_124_1725_n54), .ICI(DP_OP_498J312_124_1725_n49), .S(
DP_OP_498J312_124_1725_n46), .ICO(DP_OP_498J312_124_1725_n44), .CO(
DP_OP_498J312_124_1725_n45) );
ADDHXLTS U2439 ( .A(n1868), .B(n1869), .CO(n1274), .S(n1373) );
NOR2BX1TS U2440 ( .AN(n972), .B(n2071), .Y(n1959) );
OAI22X1TS U2441 ( .A0(n1929), .A1(n915), .B0(n1928), .B1(n1927), .Y(n1960)
);
OAI22X1TS U2442 ( .A0(n1654), .A1(n1670), .B0(n1669), .B1(n975), .Y(n1673)
);
INVX2TS U2443 ( .A(n1676), .Y(n1674) );
OAI22X1TS U2444 ( .A0(n1654), .A1(n975), .B0(n1518), .B1(n1670), .Y(n1660)
);
CLKAND2X2TS U2445 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MX[19]), .Y(n1078) );
CLKAND2X2TS U2446 ( .A(FPMULT_Op_MY[21]), .B(n913), .Y(n1077) );
ADDHXLTS U2447 ( .A(n2465), .B(n2464), .CO(DP_OP_497J312_123_1725_n335), .S(
n1085) );
CLKAND2X2TS U2448 ( .A(n914), .B(n912), .Y(n2465) );
CLKAND2X2TS U2449 ( .A(FPMULT_Op_MY[18]), .B(n976), .Y(n2464) );
INVX4TS U2450 ( .A(n2482), .Y(n2480) );
CMPR42X1TS U2451 ( .A(DP_OP_497J312_123_1725_n369), .B(
DP_OP_497J312_123_1725_n359), .C(DP_OP_497J312_123_1725_n364), .D(
DP_OP_497J312_123_1725_n335), .ICI(DP_OP_497J312_123_1725_n332), .S(
DP_OP_497J312_123_1725_n330), .ICO(DP_OP_497J312_123_1725_n328), .CO(
DP_OP_497J312_123_1725_n329) );
CLKAND2X2TS U2452 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[19]), .Y(
DP_OP_497J312_123_1725_n364) );
CLKAND2X2TS U2453 ( .A(FPMULT_Op_MY[22]), .B(n913), .Y(
DP_OP_497J312_123_1725_n369) );
INVX2TS U2454 ( .A(n2182), .Y(n2184) );
MXI2X2TS U2455 ( .A(DP_OP_496J312_122_3540_n823), .B(
DP_OP_496J312_122_3540_n822), .S0(DP_OP_496J312_122_3540_n828), .Y(
DP_OP_496J312_122_3540_n821) );
INVX2TS U2456 ( .A(n2098), .Y(DP_OP_496J312_122_3540_n272) );
AO21X1TS U2457 ( .A0(n1670), .A1(n975), .B0(n1669), .Y(n1677) );
OAI22X1TS U2458 ( .A0(n1678), .A1(n968), .B0(n1609), .B1(n1671), .Y(n1675)
);
INVX2TS U2459 ( .A(n2179), .Y(n1996) );
ADDHX1TS U2460 ( .A(n2213), .B(n2212), .CO(n2209), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
XNOR2X1TS U2461 ( .A(n2134), .B(n1029), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
XOR2X1TS U2462 ( .A(n2151), .B(n2150), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
INVX2TS U2463 ( .A(n2164), .Y(n2166) );
OAI21X1TS U2464 ( .A0(n2173), .A1(n2169), .B0(n2170), .Y(n2168) );
OAI21X2TS U2465 ( .A0(n2182), .A1(n2185), .B0(n2183), .Y(n2180) );
INVX2TS U2466 ( .A(n2189), .Y(n1988) );
ADDFHX2TS U2467 ( .A(DP_OP_498J312_124_1725_n20), .B(
DP_OP_498J312_124_1725_n22), .CI(n1300), .CO(n1298), .S(n1350) );
INVX4TS U2468 ( .A(n1133), .Y(n1759) );
CMPR42X1TS U2469 ( .A(DP_OP_498J312_124_1725_n122), .B(
DP_OP_498J312_124_1725_n62), .C(DP_OP_498J312_124_1725_n108), .D(
DP_OP_498J312_124_1725_n90), .ICI(DP_OP_498J312_124_1725_n60), .S(
DP_OP_498J312_124_1725_n58), .ICO(DP_OP_498J312_124_1725_n56), .CO(
DP_OP_498J312_124_1725_n57) );
OAI32X1TS U2470 ( .A0(n2474), .A1(n979), .A2(n2486), .B0(n2472), .B1(n2474),
.Y(n1093) );
NAND2X1TS U2471 ( .A(n1987), .B(n1986), .Y(n2189) );
OAI21X1TS U2472 ( .A0(n2192), .A1(n2195), .B0(n2193), .Y(n2190) );
ADDFX2TS U2473 ( .A(DP_OP_498J312_124_1725_n307), .B(n1057), .CI(n1056),
.CO(n1283), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
XOR2X1TS U2474 ( .A(n2196), .B(n2195), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
CLKAND2X2TS U2475 ( .A(FPMULT_Op_MY[18]), .B(n912), .Y(n1089) );
INVX2TS U2476 ( .A(DP_OP_497J312_123_1725_n23), .Y(n1408) );
INVX2TS U2477 ( .A(DP_OP_497J312_123_1725_n27), .Y(n1409) );
NAND2X1TS U2478 ( .A(n2171), .B(n2170), .Y(n2172) );
ADDHX1TS U2479 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .B(n1335),
.CO(n1381), .S(n2854) );
ADDFHX2TS U2480 ( .A(n1350), .B(n1517), .CI(n1349), .CO(n1341), .S(n2863) );
NAND2BXLTS U2481 ( .AN(n2376), .B(n2372), .Y(n1148) );
ADDFHX2TS U2482 ( .A(DP_OP_498J312_124_1725_n225), .B(
DP_OP_498J312_124_1725_n231), .CI(n1156), .CO(n1320), .S(n2332) );
NOR2X1TS U2483 ( .A(n923), .B(n1002), .Y(n1145) );
ADDFHX2TS U2484 ( .A(n1316), .B(DP_OP_498J312_124_1725_n57), .CI(
DP_OP_498J312_124_1725_n52), .CO(n1315), .S(n1376) );
XOR2X1TS U2485 ( .A(DP_OP_497J312_123_1725_n23), .B(
DP_OP_497J312_123_1725_n27), .Y(n1386) );
BUFX4TS U2486 ( .A(n2648), .Y(n3464) );
AO22XLTS U2487 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n940), .B0(n943),
.B1(FPADDSUB_Data_array_SWR[40]), .Y(n2618) );
CLKAND2X2TS U2488 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n3606), .Y(n3245)
);
OAI211X1TS U2489 ( .A0(n3577), .A1(n2737), .B0(n2736), .C0(n2735), .Y(n2743)
);
AOI22X1TS U2490 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n3550), .B0(n2690), .B1(
n2689), .Y(n2695) );
AO22XLTS U2491 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n943),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n2604) );
CLKAND2X2TS U2492 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n3580), .Y(n2877)
);
BUFX4TS U2493 ( .A(n2493), .Y(n3329) );
BUFX4TS U2494 ( .A(n3326), .Y(n3414) );
BUFX4TS U2495 ( .A(n3358), .Y(n3392) );
ADDFHX2TS U2496 ( .A(n2257), .B(n2337), .CI(n2256), .CO(n1374), .S(n2825) );
CLKAND2X2TS U2497 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n3548), .Y(n2673)
);
OAI211XLTS U2498 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n3605), .B0(n3477), .C0(n3192), .Y(n875) );
XNOR2X1TS U2499 ( .A(n1506), .B(n1464), .Y(FPMULT_Sgf_operation_Result[46])
);
NOR2XLTS U2500 ( .A(n2242), .B(n1507), .Y(n1506) );
XOR2XLTS U2501 ( .A(n1449), .B(n1393), .Y(FPMULT_Sgf_operation_Result[29])
);
XOR2X1TS U2502 ( .A(n1448), .B(n2387), .Y(n1393) );
NAND2X1TS U2503 ( .A(n2228), .B(n2227), .Y(n2230) );
XOR2XLTS U2504 ( .A(n2239), .B(n2238), .Y(FPMULT_Sgf_operation_Result[33])
);
XOR2XLTS U2505 ( .A(n2221), .B(n2220), .Y(FPMULT_Sgf_operation_Result[35])
);
XNOR2X1TS U2506 ( .A(n2252), .B(n2251), .Y(FPMULT_Sgf_operation_Result[37])
);
NAND2X1TS U2507 ( .A(n2250), .B(n2249), .Y(n2251) );
XNOR2X1TS U2508 ( .A(n1485), .B(n1276), .Y(FPMULT_Sgf_operation_Result[39])
);
NOR2XLTS U2509 ( .A(n2242), .B(n1278), .Y(n1485) );
XNOR2X1TS U2510 ( .A(n1512), .B(n1435), .Y(FPMULT_Sgf_operation_Result[41])
);
NOR2XLTS U2511 ( .A(n2242), .B(n1510), .Y(n1512) );
XNOR2X1TS U2512 ( .A(n2244), .B(n2243), .Y(FPMULT_Sgf_operation_Result[43])
);
NOR2XLTS U2513 ( .A(n2242), .B(n2241), .Y(n2244) );
XNOR2X1TS U2514 ( .A(n1502), .B(n1455), .Y(FPMULT_Sgf_operation_Result[44])
);
NOR2XLTS U2515 ( .A(n2242), .B(n1501), .Y(n1502) );
XNOR2X1TS U2516 ( .A(n1500), .B(n1460), .Y(FPMULT_Sgf_operation_Result[45])
);
NOR2X1TS U2517 ( .A(n2242), .B(n1499), .Y(n1500) );
OAI21XLTS U2518 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n3579), .B0(n3236),
.Y(n3237) );
OAI21XLTS U2519 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n3536), .B0(n3241),
.Y(n3242) );
XNOR2X1TS U2520 ( .A(n1508), .B(n916), .Y(FPMULT_Sgf_operation_Result[47])
);
NOR2X1TS U2521 ( .A(n2242), .B(n1010), .Y(n1508) );
NOR2X1TS U2522 ( .A(n2996), .B(n2997), .Y(FPMULT_Adder_M_result_A_adder[24])
);
OAI211XLTS U2523 ( .A0(operation[1]), .A1(n2495), .B0(n2494), .C0(n2498),
.Y(add_subt_data2[29]) );
OAI211XLTS U2524 ( .A0(operation[1]), .A1(n2492), .B0(n2491), .C0(n2515),
.Y(add_subt_data2[19]) );
OAI211XLTS U2525 ( .A0(n953), .A1(n2497), .B0(n2496), .C0(n2498), .Y(
add_subt_data2[28]) );
OAI222X1TS U2526 ( .A0(n2873), .A1(n3280), .B0(n3279), .B1(n3278), .C0(n948),
.C1(n3277), .Y(FPADDSUB_Data_array_SWR[23]) );
OAI211XLTS U2527 ( .A0(n953), .A1(n2509), .B0(n2508), .C0(n2510), .Y(
add_subt_data2[13]) );
OAI211XLTS U2528 ( .A0(n953), .A1(n3745), .B0(n2529), .C0(n2528), .Y(
add_subt_data2[11]) );
OAI211XLTS U2529 ( .A0(n953), .A1(n2505), .B0(n2504), .C0(n2520), .Y(
add_subt_data2[17]) );
AND4X1TS U2530 ( .A(n2872), .B(n2871), .C(n2870), .D(n2869), .Y(n3649) );
MX2X1TS U2531 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
OAI21XLTS U2532 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n2637), .B0(n2644), .Y(
n2638) );
MX2X1TS U2533 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U2534 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U2535 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U2536 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U2537 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U2538 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U2539 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
XOR2X1TS U2540 ( .A(n1493), .B(n1495), .Y(FPMULT_Sgf_operation_Result[23])
);
XOR2X1TS U2541 ( .A(n2255), .B(n1494), .Y(n1495) );
XNOR2X1TS U2542 ( .A(n1482), .B(n1392), .Y(FPMULT_Sgf_operation_Result[40])
);
XNOR2X1TS U2543 ( .A(n1480), .B(n1447), .Y(FPMULT_Sgf_operation_Result[42])
);
INVX4TS U2544 ( .A(n2568), .Y(n2651) );
NAND2BXLTS U2545 ( .AN(enab_cont_iter), .B(n2567), .Y(n2568) );
NAND4X1TS U2546 ( .A(n2985), .B(n2560), .C(n2559), .D(n2558), .Y(
FPADDSUB_LZD_raw_out_EWR[1]) );
OAI32X1TS U2547 ( .A0(n1036), .A1(FPSENCOS_d_ff1_operation_out), .A2(n969),
.B0(FPSENCOS_d_ff1_shift_region_flag_out_0_), .B1(n3265), .Y(n3266) );
NAND2BXLTS U2548 ( .AN(FPADDSUB_intDX_EWSW[30]), .B(n3660), .Y(
FPADDSUB_DMP_INIT_EWSW[30]) );
INVX2TS U2549 ( .A(n966), .Y(n2738) );
OR2X2TS U2550 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[3]), .Y(n929) );
XOR2X1TS U2551 ( .A(n1546), .B(n1138), .Y(n930) );
NAND2X4TS U2552 ( .A(n968), .B(n1722), .Y(n1609) );
INVX2TS U2553 ( .A(n2433), .Y(n1063) );
INVX2TS U2554 ( .A(rst), .Y(n824) );
CMPR42X2TS U2555 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
DP_OP_499J312_125_1651_n98), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .D(
DP_OP_499J312_125_1651_n45), .ICI(DP_OP_499J312_125_1651_n46), .S(
DP_OP_499J312_125_1651_n44), .ICO(DP_OP_499J312_125_1651_n42), .CO(
DP_OP_499J312_125_1651_n43) );
INVX2TS U2556 ( .A(n935), .Y(n940) );
INVX2TS U2557 ( .A(n935), .Y(n941) );
INVX2TS U2558 ( .A(n2582), .Y(n942) );
INVX2TS U2559 ( .A(n942), .Y(n943) );
INVX2TS U2560 ( .A(n942), .Y(n944) );
INVX2TS U2561 ( .A(n2886), .Y(n947) );
INVX4TS U2562 ( .A(n2886), .Y(n948) );
INVX2TS U2563 ( .A(n3279), .Y(n949) );
INVX2TS U2564 ( .A(n2987), .Y(n950) );
INVX3TS U2565 ( .A(n2987), .Y(n951) );
INVX3TS U2566 ( .A(n3140), .Y(n956) );
INVX3TS U2567 ( .A(n3141), .Y(n958) );
INVX3TS U2568 ( .A(n3143), .Y(n960) );
INVX3TS U2569 ( .A(n3145), .Y(n962) );
OAI221X1TS U2570 ( .A0(n3588), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n3592),
.B1(FPADDSUB_intDY_EWSW[16]), .C0(n3110), .Y(n3113) );
OAI21X1TS U2571 ( .A0(n2723), .A1(n3599), .B0(n2722), .Y(n2588) );
OAI21X1TS U2572 ( .A0(n2723), .A1(n3598), .B0(n2722), .Y(n2607) );
ADDHX1TS U2573 ( .A(n914), .B(FPMULT_Op_MX[19]), .CO(
DP_OP_497J312_123_1725_n319), .S(DP_OP_497J312_123_1725_n320) );
XOR2X1TS U2574 ( .A(n1584), .B(n1583), .Y(n1585) );
AFHCONX2TS U2575 ( .A(n2443), .B(n1487), .CI(n1486), .CON(n1515), .S(
FPMULT_Sgf_operation_Result[27]) );
CMPR42X1TS U2576 ( .A(DP_OP_498J312_124_1725_n326), .B(
DP_OP_498J312_124_1725_n324), .C(DP_OP_498J312_124_1725_n320), .D(
DP_OP_498J312_124_1725_n318), .ICI(DP_OP_498J312_124_1725_n321), .S(
DP_OP_498J312_124_1725_n316), .ICO(DP_OP_498J312_124_1725_n314), .CO(
DP_OP_498J312_124_1725_n315) );
OAI21XLTS U2577 ( .A0(n2916), .A1(n3279), .B0(n2915), .Y(
FPADDSUB_Data_array_SWR[3]) );
NOR4X2TS U2578 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n2564) );
INVX4TS U2579 ( .A(n3474), .Y(n963) );
OAI211X1TS U2580 ( .A0(n3577), .A1(n2688), .B0(n2629), .C0(n2628), .Y(n2631)
);
AOI21X2TS U2581 ( .A0(n2577), .A1(FPADDSUB_Data_array_SWR[51]), .B0(n2627),
.Y(n2688) );
ADDHX1TS U2582 ( .A(n2346), .B(n1251), .CO(DP_OP_498J312_124_1725_n61), .S(
DP_OP_498J312_124_1725_n62) );
BUFX4TS U2583 ( .A(n3723), .Y(n3721) );
BUFX4TS U2584 ( .A(n3707), .Y(n3729) );
BUFX4TS U2585 ( .A(n3720), .Y(n3718) );
NOR4X1TS U2586 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MX[28]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[30]), .Y(n3491) );
NOR4X1TS U2587 ( .A(FPMULT_Op_MX[10]), .B(n912), .C(FPMULT_Op_MX[22]), .D(
n976), .Y(n3496) );
OAI211X1TS U2588 ( .A0(n3577), .A1(n2685), .B0(n2584), .C0(n2583), .Y(n2611)
);
AOI21X2TS U2589 ( .A0(n2577), .A1(FPADDSUB_Data_array_SWR[50]), .B0(n2627),
.Y(n2685) );
BUFX4TS U2590 ( .A(n2567), .Y(n3717) );
BUFX4TS U2591 ( .A(n2567), .Y(n3719) );
BUFX3TS U2592 ( .A(n2567), .Y(n2572) );
BUFX4TS U2593 ( .A(n3719), .Y(n3705) );
BUFX4TS U2594 ( .A(n3717), .Y(n3707) );
BUFX4TS U2595 ( .A(n2572), .Y(n3735) );
BUFX4TS U2596 ( .A(n3717), .Y(n3706) );
BUFX4TS U2597 ( .A(n3735), .Y(n3726) );
OAI211X1TS U2598 ( .A0(n3577), .A1(n2733), .B0(n2732), .C0(n2731), .Y(n2740)
);
AOI21X2TS U2599 ( .A0(FPADDSUB_Data_array_SWR[48]), .A1(n2577), .B0(n2627),
.Y(n2733) );
BUFX4TS U2600 ( .A(n3728), .Y(n3708) );
BUFX4TS U2601 ( .A(n3717), .Y(n3709) );
BUFX4TS U2602 ( .A(n3713), .Y(n3711) );
BUFX4TS U2603 ( .A(n3721), .Y(n3712) );
BUFX4TS U2604 ( .A(n2572), .Y(n3710) );
BUFX4TS U2605 ( .A(n2651), .Y(n3671) );
BUFX4TS U2606 ( .A(n2651), .Y(n3672) );
BUFX4TS U2607 ( .A(n2651), .Y(n3667) );
BUFX3TS U2608 ( .A(n2570), .Y(n964) );
BUFX4TS U2609 ( .A(n3671), .Y(n3687) );
BUFX4TS U2610 ( .A(n3668), .Y(n3684) );
BUFX3TS U2611 ( .A(n2651), .Y(n2569) );
AOI21X2TS U2612 ( .A0(n2577), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n2724),
.Y(n2753) );
OAI21X1TS U2613 ( .A0(n2723), .A1(n3609), .B0(n2722), .Y(n2724) );
AOI21X2TS U2614 ( .A0(n2577), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n2721),
.Y(n2748) );
OAI21X1TS U2615 ( .A0(n2723), .A1(n3542), .B0(n2722), .Y(n2721) );
BUFX4TS U2616 ( .A(n3731), .Y(n3733) );
BUFX4TS U2617 ( .A(n3667), .Y(n3676) );
BUFX4TS U2618 ( .A(n3671), .Y(n3678) );
BUFX4TS U2619 ( .A(n3672), .Y(n3675) );
BUFX4TS U2620 ( .A(n3667), .Y(n3674) );
BUFX3TS U2621 ( .A(n2651), .Y(n2570) );
NOR2X4TS U2622 ( .A(n3511), .B(n3512), .Y(n3465) );
INVX2TS U2623 ( .A(FPADDSUB_left_right_SHT2), .Y(n965) );
INVX2TS U2624 ( .A(n965), .Y(n966) );
AFHCONX2TS U2625 ( .A(n1400), .B(n1399), .CI(n1398), .CON(n1513), .S(
FPMULT_Sgf_operation_Result[25]) );
ADDHX1TS U2626 ( .A(n1065), .B(n1064), .CO(n1267), .S(n1400) );
NAND2BX1TS U2627 ( .AN(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n3192) );
NAND2X1TS U2628 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3605),
.Y(n3477) );
INVX2TS U2629 ( .A(n936), .Y(n969) );
INVX2TS U2630 ( .A(n937), .Y(n970) );
INVX4TS U2631 ( .A(n930), .Y(n972) );
NAND2X1TS U2632 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n1159) );
XOR2X2TS U2633 ( .A(DP_OP_499J312_125_1651_n31), .B(n1439), .Y(n1436) );
NOR2X1TS U2634 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n2980) );
NOR4X1TS U2635 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .D(
n2976), .Y(n2543) );
INVX2TS U2636 ( .A(n934), .Y(n977) );
INVX2TS U2637 ( .A(n2481), .Y(n978) );
INVX2TS U2638 ( .A(n978), .Y(n979) );
ADDHXLTS U2639 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[12]), .CO(n1420), .S(
n2481) );
AOI222X4TS U2640 ( .A0(n2901), .A1(FPADDSUB_DmP_mant_SHT1_SW[0]), .B0(n3702),
.B1(FPADDSUB_Raw_mant_NRM_SWR[23]), .C0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.C1(n951), .Y(n2926) );
OA21XLTS U2641 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(n2966), .Y(n2550) );
NOR4X4TS U2642 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n2647), .D(n3571), .Y(
enab_cont_iter) );
NOR4X2TS U2643 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n2566) );
NAND3BX1TS U2644 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .C(n2706), .Y(n3309) );
NAND2X1TS U2645 ( .A(n914), .B(FPMULT_Op_MY[7]), .Y(n1547) );
XOR2X1TS U2646 ( .A(n914), .B(FPMULT_Op_MY[7]), .Y(n1582) );
ADDHX1TS U2647 ( .A(FPMULT_Op_MY[7]), .B(n914), .CO(n1704), .S(n1136) );
INVX2TS U2648 ( .A(n2429), .Y(n980) );
OAI221X1TS U2649 ( .A0(n3587), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n3533), .B1(
FPADDSUB_intDY_EWSW[0]), .C0(n3102), .Y(n3105) );
OAI221X1TS U2650 ( .A0(FPADDSUB_intDX_EWSW[14]), .A1(n3541), .B0(n3608),
.B1(FPADDSUB_intDY_EWSW[14]), .C0(n3119), .Y(n3129) );
OAI221X1TS U2651 ( .A0(n3603), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n3534), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n3108), .Y(n3115) );
AOI222X4TS U2652 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n3547), .B0(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(n3221), .C0(n3547), .C1(n3221), .Y(
n2668) );
INVX2TS U2653 ( .A(n981), .Y(n982) );
INVX2TS U2654 ( .A(n983), .Y(n984) );
NAND4X1TS U2655 ( .A(n2968), .B(n2547), .C(n2546), .D(n2545), .Y(
FPADDSUB_LZD_raw_out_EWR[0]) );
NOR4X1TS U2656 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[18]), .C(
FPMULT_Op_MY[6]), .D(FPMULT_Op_MY[22]), .Y(n3488) );
NOR4X1TS U2657 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[0]), .C(
FPMULT_Op_MX[2]), .D(FPMULT_Op_MX[6]), .Y(n3493) );
BUFX4TS U2658 ( .A(n3672), .Y(n3663) );
BUFX3TS U2659 ( .A(n2651), .Y(n2571) );
INVX2TS U2660 ( .A(n1891), .Y(n1586) );
XNOR2X2TS U2661 ( .A(n1629), .B(n1891), .Y(n1619) );
XNOR2X2TS U2662 ( .A(n1663), .B(n1891), .Y(n1613) );
XNOR2X2TS U2663 ( .A(n1618), .B(n1891), .Y(n1796) );
XNOR2X2TS U2664 ( .A(n1795), .B(n1891), .Y(n1874) );
XNOR2X2TS U2665 ( .A(n1891), .B(n1872), .Y(n1873) );
NOR2X2TS U2666 ( .A(n3537), .B(n3137), .Y(n2653) );
NOR2X4TS U2667 ( .A(n3519), .B(n3565), .Y(n3424) );
AOI21X2TS U2668 ( .A0(n2577), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n2627),
.Y(n2737) );
OAI22X1TS U2669 ( .A0(n1587), .A1(n1792), .B0(n1566), .B1(n1865), .Y(n1593)
);
OAI22X1TS U2670 ( .A0(n1566), .A1(n1792), .B0(n1865), .B1(n1788), .Y(n1576)
);
AO21X1TS U2671 ( .A0(n1792), .A1(n1865), .B0(n1788), .Y(n1632) );
OAI22X2TS U2672 ( .A0(n1612), .A1(n1865), .B0(n1792), .B1(n1617), .Y(n1621)
);
OAI22X2TS U2673 ( .A0(n1792), .A1(n1790), .B0(n1617), .B1(n1865), .Y(n1833)
);
OAI22X1TS U2674 ( .A0(n1587), .A1(n1865), .B0(n1612), .B1(n1792), .Y(n1615)
);
OAI22X1TS U2675 ( .A0(n1792), .A1(n1791), .B0(n1865), .B1(n1790), .Y(n1837)
);
NAND2X4TS U2676 ( .A(n1865), .B(n1556), .Y(n1792) );
NOR2BX1TS U2677 ( .AN(n1892), .B(n1034), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
NOR2BX1TS U2678 ( .AN(n1892), .B(n1661), .Y(n1834) );
XNOR2X1TS U2679 ( .A(n1892), .B(n1789), .Y(n1791) );
NAND2BX1TS U2680 ( .AN(n1892), .B(n1789), .Y(n1787) );
NOR2BX1TS U2681 ( .AN(n1892), .B(n1865), .Y(n2210) );
NOR2BX1TS U2682 ( .AN(n1892), .B(n1664), .Y(n1590) );
NAND2BX1TS U2683 ( .AN(n1892), .B(n1571), .Y(n1567) );
XNOR2X1TS U2684 ( .A(n1892), .B(n1571), .Y(n1568) );
NAND2BX1TS U2685 ( .AN(n1892), .B(n1891), .Y(n1893) );
OAI22X1TS U2686 ( .A0(n2094), .A1(n2093), .B0(n2092), .B1(n2131), .Y(n2128)
);
OAI22X1TS U2687 ( .A0(n2094), .A1(n2082), .B0(n2092), .B1(n2093), .Y(n2089)
);
OAI22X1TS U2688 ( .A0(n2094), .A1(n2017), .B0(n2092), .B1(n2055), .Y(n2052)
);
OAI22X1TS U2689 ( .A0(n2094), .A1(n1848), .B0(n2092), .B1(n1783), .Y(n1845)
);
NOR2BX1TS U2690 ( .AN(n972), .B(n2092), .Y(n1951) );
OAI22X1TS U2691 ( .A0(n2094), .A1(n1849), .B0(n2092), .B1(n1848), .Y(n1920)
);
NAND2X1TS U2692 ( .A(FPMULT_Sgf_normalized_result[6]), .B(n3022), .Y(n3021)
);
AOI21X2TS U2693 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n3512), .B0(n2574),
.Y(n2678) );
OAI21X2TS U2694 ( .A0(n2883), .A1(n3558), .B0(n2882), .Y(n2957) );
OAI22X1TS U2695 ( .A0(n2072), .A1(n2039), .B0(n2070), .B1(n2071), .Y(n2075)
);
OAI22X1TS U2696 ( .A0(n2026), .A1(n2072), .B0(n2039), .B1(n2071), .Y(n2056)
);
OAI22X1TS U2697 ( .A0(n2072), .A1(n1805), .B0(n1804), .B1(n2071), .Y(n1820)
);
OAI22X2TS U2698 ( .A0(n2072), .A1(n1863), .B0(n1805), .B1(n2071), .Y(n1852)
);
OAI22X1TS U2699 ( .A0(n2072), .A1(n1925), .B0(n1863), .B1(n2071), .Y(n1939)
);
NAND2X4TS U2700 ( .A(n1691), .B(n2071), .Y(n2072) );
XNOR2X2TS U2701 ( .A(n1880), .B(n1895), .Y(n1898) );
INVX2TS U2702 ( .A(n1717), .Y(n1669) );
XNOR2X2TS U2703 ( .A(n1717), .B(n1692), .Y(n1606) );
XOR2X1TS U2704 ( .A(n1717), .B(n1698), .Y(n1205) );
OAI22X1TS U2705 ( .A0(n1751), .A1(n2020), .B0(n2018), .B1(n2019), .Y(n2029)
);
OAI22X1TS U2706 ( .A0(n1810), .A1(n2019), .B0(n1809), .B1(n2020), .Y(n1818)
);
AO21X1TS U2707 ( .A0(n2020), .A1(n2019), .B0(n2018), .Y(n2049) );
OAI22X1TS U2708 ( .A0(n1809), .A1(n2019), .B0(n1803), .B1(n2020), .Y(n1806)
);
OAI22X1TS U2709 ( .A0(n1803), .A1(n2019), .B0(n2020), .B1(n1784), .Y(n1831)
);
OAI22X1TS U2710 ( .A0(n2020), .A1(n1835), .B0(n1784), .B1(n2019), .Y(n1843)
);
OAI22X1TS U2711 ( .A0(n2020), .A1(n1884), .B0(n1883), .B1(n2019), .Y(n1967)
);
NAND2X4TS U2712 ( .A(n1743), .B(n2019), .Y(n2020) );
NOR2BX1TS U2713 ( .AN(n972), .B(n2019), .Y(n1970) );
OR2X2TS U2714 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[4]), .Y(n1003) );
NOR4X1TS U2715 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[14]), .C(
FPMULT_Op_MX[16]), .D(FPMULT_Op_MX[3]), .Y(n3494) );
NAND2X2TS U2716 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[3]), .Y(n1185) );
INVX2TS U2717 ( .A(n2070), .Y(n985) );
INVX2TS U2718 ( .A(n2025), .Y(n2070) );
XNOR2X2TS U2719 ( .A(n985), .B(n2023), .Y(n1805) );
XNOR2X1TS U2720 ( .A(n1767), .B(n1766), .Y(n2025) );
NOR4X1TS U2721 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[16]), .C(
FPMULT_Op_MY[15]), .D(FPMULT_Op_MY[17]), .Y(n3486) );
AOI221X1TS U2722 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n3660), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n3659), .C0(n3041), .Y(n3043) );
OAI221X1TS U2723 ( .A0(n3660), .A1(FPADDSUB_intDX_EWSW[30]), .B0(n3594),
.B1(FPADDSUB_intDY_EWSW[20]), .C0(n3116), .Y(n3131) );
XNOR2X2TS U2724 ( .A(n2095), .B(n986), .Y(n1810) );
INVX2TS U2725 ( .A(n986), .Y(n2018) );
NAND2BX1TS U2726 ( .AN(n972), .B(n986), .Y(n1881) );
XNOR2X2TS U2727 ( .A(n986), .B(n1880), .Y(n1835) );
OAI221X1TS U2728 ( .A0(n3659), .A1(FPADDSUB_intDX_EWSW[29]), .B0(n3593),
.B1(FPADDSUB_intDY_EWSW[18]), .C0(n3100), .Y(n3107) );
AOI21X2TS U2729 ( .A0(n2577), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n2588),
.Y(n2742) );
AOI21X2TS U2730 ( .A0(n2577), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n2607),
.Y(n2745) );
NOR4BX2TS U2731 ( .AN(n2566), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]),
.C(n2565), .D(n1035), .Y(FPSENCOS_enab_RB3) );
XOR2X1TS U2732 ( .A(n1708), .B(n1703), .Y(n1635) );
INVX4TS U2733 ( .A(n1635), .Y(n987) );
OAI22X1TS U2734 ( .A0(n1638), .A1(n1637), .B0(n1636), .B1(n987), .Y(n1646)
);
AO21X1TS U2735 ( .A0(n1637), .A1(n987), .B0(n1636), .Y(n1656) );
OAI22X1TS U2736 ( .A0(n1638), .A1(n987), .B0(n1601), .B1(n1637), .Y(n1625)
);
OAI22X1TS U2737 ( .A0(n1600), .A1(n987), .B0(n1637), .B1(n1191), .Y(n1596)
);
OAI22X1TS U2738 ( .A0(n1637), .A1(n1636), .B0(n1232), .B1(n987), .Y(n1836)
);
NOR2BX1TS U2739 ( .AN(n1759), .B(n987), .Y(n1794) );
OAI2BB1X1TS U2740 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1N(n951), .B0(
n2895), .Y(n2934) );
OAI32X1TS U2741 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n3570), .B0(n3521), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n2544) );
NOR4X2TS U2742 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .C(FPADDSUB_Raw_mant_NRM_SWR[22]), .D(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n2961) );
OAI22X1TS U2743 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(n3606), .B0(n3245),
.B1(n3244), .Y(n3249) );
INVX2TS U2744 ( .A(n988), .Y(n1636) );
XNOR2X2TS U2745 ( .A(n988), .B(n1740), .Y(n1198) );
XOR2X1TS U2746 ( .A(n988), .B(n1708), .Y(n1184) );
AOI21X1TS U2747 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n3613), .B0(n3255),
.Y(n3258) );
OAI31X1TS U2748 ( .A0(n3480), .A1(FPSENCOS_cont_var_out[1]), .A2(n3522),
.B0(n2988), .Y(n842) );
NAND2X1TS U2749 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[10]), .Y(n1561) );
OR2X2TS U2750 ( .A(n912), .B(FPMULT_Op_MX[8]), .Y(n994) );
INVX2TS U2751 ( .A(FPMULT_FS_Module_state_reg[2]), .Y(n2573) );
INVX2TS U2752 ( .A(n998), .Y(n3138) );
OR2X2TS U2753 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[3]), .Y(n1000) );
NOR2X1TS U2754 ( .A(n1001), .B(n1002), .Y(n2855) );
NOR2X1TS U2755 ( .A(n1012), .B(n1024), .Y(n1397) );
INVX2TS U2756 ( .A(n2787), .Y(n1272) );
OR2X1TS U2757 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n1011) );
INVX2TS U2758 ( .A(n1134), .Y(n1135) );
NAND2X4TS U2759 ( .A(n1011), .B(n1182), .Y(n1134) );
OA21XLTS U2760 ( .A0(n1219), .A1(n1214), .B0(n1215), .Y(n1019) );
INVX2TS U2761 ( .A(n2437), .Y(n1273) );
AND2X2TS U2762 ( .A(n1448), .B(n2387), .Y(n1033) );
CLKXOR2X4TS U2763 ( .A(n1702), .B(n1582), .Y(n1034) );
BUFX4TS U2764 ( .A(n3289), .Y(n3290) );
BUFX3TS U2765 ( .A(n3290), .Y(n3287) );
INVX2TS U2766 ( .A(n1780), .Y(n1713) );
NAND2X1TS U2767 ( .A(n1709), .B(n1708), .Y(n1773) );
INVX2TS U2768 ( .A(n1722), .Y(n1744) );
INVX2TS U2769 ( .A(n2122), .Y(n2123) );
NOR2X1TS U2770 ( .A(n1760), .B(n1759), .Y(n1761) );
NAND2X1TS U2771 ( .A(n1013), .B(n1747), .Y(n1748) );
INVX2TS U2772 ( .A(n2204), .Y(n1878) );
ADDFX2TS U2773 ( .A(n2049), .B(n2048), .CI(n2047), .CO(n2079), .S(n2058) );
INVX2TS U2774 ( .A(n1794), .Y(n1866) );
XOR2X1TS U2775 ( .A(n1767), .B(n1682), .Y(n1691) );
NAND2X1TS U2776 ( .A(n1767), .B(n1766), .Y(n1768) );
NAND2BX1TS U2777 ( .AN(n972), .B(n2081), .Y(n1850) );
INVX2TS U2778 ( .A(DP_OP_496J312_122_3540_n1015), .Y(n1846) );
OAI22X1TS U2779 ( .A0(n2072), .A1(n1804), .B0(n1752), .B1(n2071), .Y(n1823)
);
INVX2TS U2780 ( .A(n1844), .Y(n1922) );
NAND2X1TS U2781 ( .A(n1165), .B(n1164), .Y(n1166) );
INVX2TS U2782 ( .A(DP_OP_496J312_122_3540_n1014), .Y(n1861) );
OAI21X1TS U2783 ( .A0(n1559), .A1(n1558), .B0(n1557), .Y(n1564) );
INVX2TS U2784 ( .A(n2211), .Y(n1971) );
OAI22X1TS U2785 ( .A0(n2072), .A1(n1926), .B0(n1925), .B1(n2071), .Y(n1955)
);
OAI22X1TS U2786 ( .A0(n1609), .A1(n1607), .B0(n968), .B1(n1519), .Y(n1641)
);
ADDFX2TS U2787 ( .A(n1590), .B(n1589), .CI(n1588), .CO(n1592), .S(n1614) );
OAI22X2TS U2788 ( .A0(n1598), .A1(n1134), .B0(n1226), .B1(n1597), .Y(n1828)
);
OAI22X1TS U2789 ( .A0(n1609), .A1(n1519), .B0(n968), .B1(n1653), .Y(n1655)
);
NAND2X1TS U2790 ( .A(n2194), .B(n2193), .Y(n2196) );
INVX2TS U2791 ( .A(n1789), .Y(n1788) );
NAND2X1TS U2792 ( .A(n2149), .B(n2148), .Y(n2150) );
ADDFX2TS U2793 ( .A(n1616), .B(n1615), .CI(n1614), .CO(
DP_OP_496J312_122_3540_n571), .S(DP_OP_496J312_122_3540_n572) );
INVX2TS U2794 ( .A(n2169), .Y(n2171) );
NAND2X2TS U2795 ( .A(n2106), .B(n2105), .Y(n2159) );
CMPR42X1TS U2796 ( .A(DP_OP_497J312_123_1725_n116), .B(
DP_OP_497J312_123_1725_n109), .C(DP_OP_497J312_123_1725_n123), .D(
DP_OP_497J312_123_1725_n68), .ICI(DP_OP_497J312_123_1725_n67), .S(
DP_OP_497J312_123_1725_n65), .ICO(DP_OP_497J312_123_1725_n63), .CO(
DP_OP_497J312_123_1725_n64) );
NOR2BX1TS U2797 ( .AN(n2376), .B(n2377), .Y(DP_OP_498J312_124_1725_n109) );
NAND2X1TS U2798 ( .A(n2160), .B(n2159), .Y(n2161) );
AOI2BB2X2TS U2799 ( .B0(n1411), .B1(n1410), .A0N(n1409), .A1N(n1408), .Y(
n1418) );
ADDFHX2TS U2800 ( .A(DP_OP_498J312_124_1725_n217), .B(
DP_OP_498J312_124_1725_n219), .CI(n1328), .CO(n1326), .S(n2334) );
NOR2XLTS U2801 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n2962) );
OR2X1TS U2802 ( .A(n2784), .B(n2783), .Y(n2786) );
AOI22X1TS U2803 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n3546), .B0(n2668), .B1(
n2667), .Y(n2672) );
OAI21XLTS U2804 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n3514), .B0(n2690),
.Y(n2675) );
OAI21XLTS U2805 ( .A0(n2694), .A1(n2696), .B0(n2693), .Y(n2692) );
INVX2TS U2806 ( .A(FPMULT_Sgf_normalized_result[23]), .Y(n2996) );
OAI21XLTS U2807 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n3557), .B0(n2775),
.Y(n2770) );
OAI21XLTS U2808 ( .A0(n2671), .A1(n2673), .B0(n2670), .Y(n2669) );
OAI211XLTS U2809 ( .A0(n2989), .A1(n996), .B0(n2666), .C0(n2662), .Y(
FPMULT_FS_Module_state_next[3]) );
OAI211XLTS U2810 ( .A0(operation[1]), .A1(n2500), .B0(n2499), .C0(n2498),
.Y(add_subt_data2[27]) );
OR2X1TS U2811 ( .A(FPSENCOS_d_ff_Xn[28]), .B(n3288), .Y(
FPSENCOS_first_mux_X[28]) );
OAI21XLTS U2812 ( .A0(n3505), .A1(n3643), .B0(n3504), .Y(
FPSENCOS_sh_exp_y[5]) );
OR2X1TS U2813 ( .A(n3748), .B(FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
FPADDSUB_formatted_number_W[27]) );
OAI21XLTS U2814 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n989), .B0(n2661), .Y(
FPADDSUB_Shift_amount_EXP_EW[0]) );
OAI21X4TS U2815 ( .A0(n1192), .A1(n1195), .B0(n1193), .Y(n1189) );
AOI21X4TS U2816 ( .A0(n1189), .A1(n992), .B0(n1037), .Y(n1168) );
OAI21X4TS U2817 ( .A0(n1020), .A1(n1222), .B0(n1019), .Y(n1735) );
XNOR2X4TS U2818 ( .A(n1735), .B(n1041), .Y(n1892) );
OAI21X4TS U2819 ( .A0(n1179), .A1(n1182), .B0(n1180), .Y(n1177) );
AOI21X4TS U2820 ( .A0(n1157), .A1(n1047), .B0(n1046), .Y(n1702) );
NOR2X1TS U2821 ( .A(DP_OP_498J312_124_1725_n377), .B(n1021), .Y(n1052) );
NOR2X1TS U2822 ( .A(DP_OP_498J312_124_1725_n382), .B(
DP_OP_498J312_124_1725_n379), .Y(n2348) );
NOR2X1TS U2823 ( .A(DP_OP_498J312_124_1725_n377), .B(n1018), .Y(n2347) );
NOR2X1TS U2824 ( .A(n1018), .B(DP_OP_498J312_124_1725_n379), .Y(n1155) );
ADDHX1TS U2825 ( .A(n1052), .B(n1051), .CO(n1048), .S(n1312) );
CMPR32X2TS U2826 ( .A(n1055), .B(n1054), .C(DP_OP_498J312_124_1725_n306),
.CO(n1285), .S(n1057) );
NOR2X1TS U2827 ( .A(n1009), .B(n1024), .Y(n1062) );
NOR2X1TS U2828 ( .A(n990), .B(n1026), .Y(n1061) );
CMPR32X2TS U2829 ( .A(n1060), .B(n1059), .C(n1058), .CO(n1098), .S(n1259) );
NOR2X1TS U2830 ( .A(n1012), .B(n1026), .Y(n1065) );
NOR2X1TS U2831 ( .A(n990), .B(n1024), .Y(n1064) );
AOI21X1TS U2832 ( .A0(n979), .A1(n2433), .B0(DP_OP_497J312_123_1725_n119),
.Y(n1111) );
NAND2X1TS U2833 ( .A(FPMULT_Op_MY[18]), .B(n913), .Y(n1115) );
NOR2X1TS U2834 ( .A(n978), .B(n1063), .Y(n1114) );
INVX2TS U2835 ( .A(n1400), .Y(n1069) );
NAND2X1TS U2836 ( .A(n2429), .B(n1063), .Y(n1067) );
INVX2TS U2837 ( .A(n2424), .Y(n2427) );
AOI22X1TS U2838 ( .A0(n2424), .A1(DP_OP_497J312_123_1725_n119), .B0(n2429),
.B1(n2427), .Y(n1066) );
OAI22X1TS U2839 ( .A0(n979), .A1(n1067), .B0(n1066), .B1(n1063), .Y(n1068)
);
CMPR32X2TS U2840 ( .A(n1069), .B(n2446), .C(n1068), .CO(n1106), .S(n1109) );
AOI2BB2X1TS U2841 ( .B0(n1421), .B1(FPMULT_Op_MX[17]), .A0N(FPMULT_Op_MX[17]), .A1N(n1421), .Y(n1071) );
CMPR32X4TS U2842 ( .A(FPMULT_Op_MX[15]), .B(n976), .C(n1072), .CO(n1073),
.S(n2482) );
INVX2TS U2843 ( .A(n1075), .Y(n2435) );
AOI22X1TS U2844 ( .A0(n2482), .A1(n2435), .B0(n1075), .B1(n2480), .Y(n1074)
);
OAI221X4TS U2845 ( .A0(n1075), .A1(n2434), .B0(n2435), .B1(n2474), .C0(n2486), .Y(n2472) );
ADDHX1TS U2846 ( .A(n1080), .B(n1079), .CO(n1090), .S(n2446) );
CMPR32X2TS U2847 ( .A(n1086), .B(n1085), .C(n1084), .CO(n1387), .S(n2385) );
CMPR32X2TS U2848 ( .A(n1090), .B(n1089), .C(n1088), .CO(n1084), .S(n2438) );
INVX2TS U2849 ( .A(n1115), .Y(n1123) );
CMPR32X2TS U2850 ( .A(n1096), .B(n1095), .C(DP_OP_497J312_123_1725_n215),
.CO(n1102), .S(n1105) );
CMPR32X2TS U2851 ( .A(DP_OP_497J312_123_1725_n239), .B(n1098), .C(n1097),
.CO(n1243), .S(n2386) );
CMPR32X2TS U2852 ( .A(n1102), .B(n1101), .C(n1100), .CO(n2449), .S(n2440) );
CMPR32X2TS U2853 ( .A(n1103), .B(DP_OP_497J312_123_1725_n74), .C(
DP_OP_497J312_123_1725_n70), .CO(n1099), .S(n1130) );
CMPR32X2TS U2854 ( .A(DP_OP_497J312_123_1725_n216), .B(n1105), .C(n1104),
.CO(n1100), .S(n2441) );
CMPR32X2TS U2855 ( .A(DP_OP_497J312_123_1725_n217), .B(
DP_OP_497J312_123_1725_n219), .C(n1108), .CO(n1104), .S(n2439) );
CMPR32X2TS U2856 ( .A(DP_OP_497J312_123_1725_n220), .B(
DP_OP_497J312_123_1725_n224), .C(n1112), .CO(n1108), .S(n2442) );
CMPR32X2TS U2857 ( .A(DP_OP_497J312_123_1725_n225), .B(
DP_OP_497J312_123_1725_n231), .C(n1113), .CO(n1112), .S(n2436) );
CMPR32X2TS U2858 ( .A(n1115), .B(n1378), .C(n1114), .CO(n1110), .S(n1249) );
INVX2TS U2859 ( .A(n1478), .Y(n1392) );
INVX2TS U2860 ( .A(n1484), .Y(n1276) );
INVX2TS U2861 ( .A(n1483), .Y(n1278) );
INVX2TS U2862 ( .A(n1474), .Y(n1280) );
INVX2TS U2863 ( .A(n1472), .Y(n1282) );
CMPR32X2TS U2864 ( .A(n1126), .B(n2449), .C(n1125), .CO(n1122), .S(n1469) );
INVX2TS U2865 ( .A(n1469), .Y(n1384) );
CMPR32X2TS U2866 ( .A(n1128), .B(n2440), .C(n1127), .CO(n1125), .S(n1465) );
INVX2TS U2867 ( .A(n1465), .Y(n1334) );
INVX2TS U2868 ( .A(n1461), .Y(n1337) );
CMPR32X2TS U2869 ( .A(n1132), .B(n2439), .C(n1131), .CO(n1129), .S(n1456) );
INVX2TS U2870 ( .A(n1456), .Y(n1340) );
NOR2BX1TS U2871 ( .AN(n1759), .B(n1134), .Y(n1377) );
INVX2TS U2872 ( .A(n1377), .Y(n1983) );
INVX2TS U2873 ( .A(n1701), .Y(n1137) );
INVX2TS U2874 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(n1981)
);
NOR2X1TS U2875 ( .A(DP_OP_498J312_124_1725_n379), .B(n1021), .Y(n1375) );
INVX2TS U2876 ( .A(n1375), .Y(n1151) );
INVX2TS U2877 ( .A(n2855), .Y(n1150) );
NOR2BX1TS U2878 ( .AN(n2376), .B(n1146), .Y(n1149) );
NOR2X1TS U2879 ( .A(n923), .B(n927), .Y(n1143) );
NOR2X1TS U2880 ( .A(n999), .B(n1002), .Y(n1142) );
CMPR32X2TS U2881 ( .A(n1143), .B(n1142), .C(n1141), .CO(n1240), .S(n1262) );
NOR2X1TS U2882 ( .A(n1001), .B(n927), .Y(n1153) );
NOR2X1TS U2883 ( .A(n993), .B(n1002), .Y(n1152) );
NOR2X1TS U2884 ( .A(n1001), .B(n991), .Y(n1269) );
NAND2X1TS U2885 ( .A(n1148), .B(n1147), .Y(n1288) );
CMPR32X2TS U2886 ( .A(n1151), .B(n1150), .C(n1149), .CO(n1287), .S(n1238) );
ADDHX1TS U2887 ( .A(n1153), .B(n1152), .CO(n1270), .S(n2865) );
INVX2TS U2888 ( .A(n2865), .Y(n1290) );
ADDHX1TS U2889 ( .A(n1155), .B(n1154), .CO(n1314), .S(n2383) );
ADDHXLTS U2890 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[0]), .CO(n1294), .S(
n1139) );
XNOR2X1TS U2891 ( .A(n2305), .B(n2372), .Y(n2310) );
OAI22X1TS U2892 ( .A0(n1147), .A1(n2376), .B0(n2310), .B1(n1146), .Y(n1289)
);
INVX2TS U2893 ( .A(n2823), .Y(n2264) );
CLKXOR2X4TS U2894 ( .A(n1167), .B(n1166), .Y(n1717) );
CLKXOR2X4TS U2895 ( .A(n1172), .B(n1171), .Y(n1694) );
XNOR2X4TS U2896 ( .A(n1178), .B(n1177), .Y(n1708) );
CLKXOR2X4TS U2897 ( .A(n1183), .B(n1182), .Y(n1703) );
XNOR2X4TS U2898 ( .A(n1187), .B(n1186), .Y(n1692) );
XNOR2X4TS U2899 ( .A(n1190), .B(n1189), .Y(n1727) );
CLKXOR2X4TS U2900 ( .A(n1196), .B(n1195), .Y(n1740) );
XNOR2X2TS U2901 ( .A(n1727), .B(n1703), .Y(n1235) );
NAND2X4TS U2902 ( .A(n1703), .B(n1134), .Y(n1597) );
XNOR2X1TS U2903 ( .A(n988), .B(n1759), .Y(n1199) );
NAND2BX1TS U2904 ( .AN(n1759), .B(n1717), .Y(n1208) );
XNOR2X1TS U2905 ( .A(n1717), .B(n1759), .Y(n1210) );
CLKXOR2X4TS U2906 ( .A(n1218), .B(n1217), .Y(n1770) );
CLKXOR2X4TS U2907 ( .A(n1222), .B(n1221), .Y(n1771) );
NAND2X1TS U2908 ( .A(n1233), .B(n1597), .Y(n1868) );
XNOR2X2TS U2909 ( .A(n1740), .B(n1703), .Y(n1234) );
ADDHX1TS U2910 ( .A(n1238), .B(n2332), .CO(n1332), .S(n2822) );
INVX2TS U2911 ( .A(n2822), .Y(n1247) );
INVX2TS U2912 ( .A(n2386), .Y(n1256) );
CMPR32X2TS U2913 ( .A(DP_OP_498J312_124_1725_n239), .B(n1240), .C(n1239),
.CO(n1242), .S(n2866) );
INVX2TS U2914 ( .A(n2866), .Y(n1255) );
CMPR32X2TS U2915 ( .A(n1875), .B(n1797), .C(n1241), .CO(n1253), .S(n1254) );
CMPR32X2TS U2916 ( .A(DP_OP_498J312_124_1725_n232), .B(
DP_OP_498J312_124_1725_n238), .C(n1242), .CO(n1156), .S(n2857) );
INVX2TS U2917 ( .A(n2857), .Y(n1251) );
CMPR32X2TS U2918 ( .A(DP_OP_497J312_123_1725_n232), .B(
DP_OP_497J312_123_1725_n238), .C(n1243), .CO(n1113), .S(n2387) );
INVX2TS U2919 ( .A(n2387), .Y(n1250) );
CMPR32X2TS U2920 ( .A(n1245), .B(n2442), .C(n1244), .CO(n1131), .S(n1451) );
INVX2TS U2921 ( .A(n1451), .Y(n1344) );
CMPR32X2TS U2922 ( .A(n1248), .B(n1247), .C(n1246), .CO(n2253), .S(n1348) );
ADDHX1TS U2923 ( .A(n2436), .B(n1249), .CO(n1244), .S(n1492) );
INVX2TS U2924 ( .A(n1492), .Y(n1347) );
CMPR32X2TS U2925 ( .A(n1252), .B(n1251), .C(n1250), .CO(n1246), .S(n1353) );
CMPR32X2TS U2926 ( .A(n1921), .B(n1844), .C(n1253), .CO(n1394), .S(n1352) );
CMPR32X2TS U2927 ( .A(n1256), .B(n1255), .C(n1254), .CO(n1252), .S(n1358) );
CMPR32X2TS U2928 ( .A(n1259), .B(n1258), .C(n1257), .CO(n1097), .S(n2443) );
CMPR32X2TS U2929 ( .A(n1836), .B(n1263), .C(n1871), .CO(n1241), .S(n1264) );
CMPR32X2TS U2930 ( .A(DP_OP_497J312_123_1725_n86), .B(
DP_OP_498J312_124_1725_n86), .C(n1264), .CO(n1357), .S(n1363) );
CMPR32X2TS U2931 ( .A(n1267), .B(n1266), .C(n1265), .CO(n1257), .S(n2437) );
CMPR32X2TS U2932 ( .A(n1270), .B(n1269), .C(n1268), .CO(n1260), .S(n2787) );
OR2X1TS U2933 ( .A(n1069), .B(n1290), .Y(n1271) );
CMPR32X2TS U2934 ( .A(n1273), .B(n1272), .C(n1271), .CO(n1362), .S(n1368) );
CMPR32X2TS U2935 ( .A(n1794), .B(n1274), .C(n1793), .CO(n1263), .S(n1367) );
INVX2TS U2936 ( .A(n1397), .Y(n1378) );
XNOR2X1TS U2937 ( .A(n1069), .B(n1290), .Y(n1371) );
ADDFHX4TS U2938 ( .A(DP_OP_499J312_125_1651_n65), .B(n1282), .CI(n1281),
.CO(n1279), .S(n1396) );
CMPR32X2TS U2939 ( .A(n1285), .B(n1284), .C(n1283), .CO(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .S(n2331) );
CMPR32X2TS U2940 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[1]), .C(n1291), .CO(
n2293), .S(n2294) );
CMPR32X2TS U2941 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MX[5]), .C(n1292),
.CO(n1293), .S(n2273) );
NAND2X2TS U2942 ( .A(n2267), .B(n1293), .Y(n2286) );
CMPR32X2TS U2943 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[1]), .C(n1294), .CO(
n2281), .S(n2305) );
INVX2TS U2944 ( .A(n2306), .Y(n2277) );
XOR2X1TS U2945 ( .A(DP_OP_498J312_124_1725_n18), .B(n1295), .Y(n1296) );
XOR2X1TS U2946 ( .A(DP_OP_498J312_124_1725_n19), .B(n1296), .Y(n1297) );
CMPR32X2TS U2947 ( .A(DP_OP_498J312_124_1725_n311), .B(
DP_OP_498J312_124_1725_n315), .C(n1299), .CO(n1053), .S(n2329) );
CMPR32X2TS U2948 ( .A(DP_OP_498J312_124_1725_n23), .B(
DP_OP_498J312_124_1725_n27), .C(n1302), .CO(n1300), .S(n1355) );
CMPR32X2TS U2949 ( .A(DP_OP_498J312_124_1725_n330), .B(n1306), .C(n1305),
.CO(n1303), .S(n2357) );
CMPR32X2TS U2950 ( .A(n1314), .B(n1313), .C(n1312), .CO(n1308), .S(n2330) );
CMPR32X2TS U2951 ( .A(n1319), .B(n1318), .C(DP_OP_498J312_124_1725_n215),
.CO(n1324), .S(n1327) );
CMPR32X2TS U2952 ( .A(DP_OP_498J312_124_1725_n220), .B(
DP_OP_498J312_124_1725_n224), .C(n1320), .CO(n1328), .S(n2336) );
CMPR32X2TS U2953 ( .A(n1324), .B(n1323), .C(n1322), .CO(n2337), .S(n2335) );
CMPR32X2TS U2954 ( .A(DP_OP_498J312_124_1725_n216), .B(n1327), .C(n1326),
.CO(n1322), .S(n2333) );
CMPR32X2TS U2955 ( .A(n1330), .B(n1329), .C(DP_OP_498J312_124_1725_n75),
.CO(n1325), .S(n2261) );
CMPR32X2TS U2956 ( .A(n1332), .B(n1331), .C(n2336), .CO(n2260), .S(n2823) );
CMPR32X2TS U2957 ( .A(DP_OP_499J312_125_1651_n74), .B(n1337), .C(n1336),
.CO(n1333), .S(n2853) );
ADDFHX4TS U2958 ( .A(n1342), .B(n2329), .CI(n1341), .CO(n1338), .S(n2847) );
CMPR32X2TS U2959 ( .A(n1345), .B(n1344), .C(n1343), .CO(n1339), .S(n2846) );
CMPR32X2TS U2960 ( .A(n1348), .B(n1347), .C(n1346), .CO(n1343), .S(n2864) );
CMPR32X2TS U2961 ( .A(n1353), .B(n1352), .C(n1351), .CO(n1346), .S(n2828) );
CMPR32X2TS U2962 ( .A(n1358), .B(n1357), .C(n1356), .CO(n1351), .S(n2831) );
CMPR32X2TS U2963 ( .A(n1363), .B(n1362), .C(n1361), .CO(n1356), .S(n2834) );
CMPR32X2TS U2964 ( .A(n1368), .B(n1367), .C(n1366), .CO(n1361), .S(n2782) );
CMPR32X2TS U2965 ( .A(n1373), .B(n1372), .C(n1371), .CO(n1366), .S(n2837) );
CMPR32X2TS U2966 ( .A(n1376), .B(n1375), .C(n1374), .CO(n1379), .S(n2784) );
CMPR32X2TS U2967 ( .A(n1378), .B(n1150), .C(n1377), .CO(n1372), .S(n2783) );
INVX2TS U2968 ( .A(n2785), .Y(n2836) );
CMPR22X2TS U2969 ( .A(n2331), .B(n1381), .CO(n1382), .S(n2844) );
XOR2X1TS U2970 ( .A(n1411), .B(n1386), .Y(n1415) );
CMPR32X2TS U2971 ( .A(DP_OP_497J312_123_1725_n330), .B(n1388), .C(n1387),
.CO(n1401), .S(n2384) );
INVX2TS U2972 ( .A(n1511), .Y(n1435) );
INVX2TS U2973 ( .A(DP_OP_497J312_123_1725_n192), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
INVX2TS U2974 ( .A(DP_OP_497J312_123_1725_n193), .Y(n1427) );
CMPR32X2TS U2975 ( .A(DP_OP_497J312_123_1725_n311), .B(
DP_OP_497J312_123_1725_n315), .C(n1407), .CO(n1402), .S(n2447) );
XNOR2X1TS U2976 ( .A(DP_OP_497J312_123_1725_n22), .B(
DP_OP_497J312_123_1725_n20), .Y(n1412) );
XOR2X1TS U2977 ( .A(n1418), .B(n1412), .Y(n1433) );
CMPR32X2TS U2978 ( .A(DP_OP_497J312_123_1725_n316), .B(
DP_OP_497J312_123_1725_n322), .C(n1413), .CO(n1407), .S(n2448) );
XOR2X4TS U2979 ( .A(n1419), .B(DP_OP_497J312_123_1725_n19), .Y(n1423) );
NOR2X4TS U2980 ( .A(FPMULT_Op_MY[17]), .B(n2401), .Y(n2430) );
NAND2X4TS U2981 ( .A(n1421), .B(FPMULT_Op_MX[17]), .Y(n2475) );
OAI21X2TS U2982 ( .A0(n2430), .A1(n2475), .B0(n1423), .Y(n1422) );
OAI31X2TS U2983 ( .A0(n1423), .A1(n2430), .A2(n2475), .B0(n1422), .Y(n1424)
);
XOR2X4TS U2984 ( .A(n1438), .B(n1436), .Y(n1473) );
INVX2TS U2985 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]), .Y(n1442) );
XOR2X4TS U2986 ( .A(n1445), .B(n1444), .Y(n1475) );
NOR2X8TS U2987 ( .A(n2246), .B(n2248), .Y(n1471) );
OAI22X4TS U2988 ( .A0(n1449), .A1(n1033), .B0(n1448), .B1(n2387), .Y(n1490)
);
OAI21X4TS U2989 ( .A0(n1453), .A1(n2226), .B0(n2227), .Y(n2224) );
OR2X2TS U2990 ( .A(n1457), .B(n1456), .Y(n2223) );
INVX2TS U2991 ( .A(n2222), .Y(n1458) );
AOI21X4TS U2992 ( .A0(n2224), .A1(n2223), .B0(n1458), .Y(n2238) );
NOR2X2TS U2993 ( .A(n1462), .B(n1461), .Y(n2235) );
OAI21X4TS U2994 ( .A0(n2238), .A1(n2235), .B0(n2236), .Y(n2233) );
INVX2TS U2995 ( .A(n2231), .Y(n1467) );
AOI21X4TS U2996 ( .A0(n2233), .A1(n2232), .B0(n1467), .Y(n2220) );
NOR2X4TS U2997 ( .A(n1470), .B(n1469), .Y(n2217) );
OAI21X4TS U2998 ( .A0(n2220), .A1(n2217), .B0(n2218), .Y(n2214) );
AND2X8TS U2999 ( .A(n1471), .B(n2214), .Y(n1477) );
OAI21X4TS U3000 ( .A0(n2248), .A1(n2245), .B0(n2249), .Y(n1476) );
NOR2X8TS U3001 ( .A(n1477), .B(n1476), .Y(n2242) );
NOR2X1TS U3002 ( .A(n2242), .B(n1497), .Y(n1480) );
NOR2X1TS U3003 ( .A(n2242), .B(n1481), .Y(n1482) );
NOR2X1TS U3004 ( .A(n1007), .B(DP_OP_498J312_124_1725_n379), .Y(n1489) );
NOR2X1TS U3005 ( .A(DP_OP_498J312_124_1725_n378), .B(
DP_OP_498J312_124_1725_n381), .Y(n1488) );
INVX2TS U3006 ( .A(n1503), .Y(n1499) );
INVX2TS U3007 ( .A(n1509), .Y(n1510) );
AFHCINX4TS U3008 ( .CIN(n1515), .B(n1516), .A(n2386), .S(
FPMULT_Sgf_operation_Result[28]), .CO(n1449) );
INVX2TS U3009 ( .A(n1517), .Y(DP_OP_498J312_124_1725_n197) );
CLKXOR2X4TS U3010 ( .A(n1531), .B(n1530), .Y(n1661) );
XNOR2X4TS U3011 ( .A(n1539), .B(n1538), .Y(n1872) );
XNOR2X4TS U3012 ( .A(n1545), .B(n1554), .Y(n1789) );
CLKXOR2X4TS U3013 ( .A(n1551), .B(n1550), .Y(n1865) );
XNOR2X4TS U3014 ( .A(n1564), .B(n1563), .Y(n1618) );
XNOR2X4TS U3015 ( .A(n1570), .B(n1584), .Y(n1891) );
INVX2TS U3016 ( .A(n1740), .Y(n1608) );
CLKXOR2X4TS U3017 ( .A(n1690), .B(n1689), .Y(n2071) );
XNOR2X4TS U3018 ( .A(n1721), .B(n1725), .Y(n2068) );
CLKXOR2X4TS U3019 ( .A(n1744), .B(n1745), .Y(n2095) );
CLKXOR2X4TS U3020 ( .A(n1742), .B(n1741), .Y(n2019) );
XNOR2X4TS U3021 ( .A(n1746), .B(n1762), .Y(n1895) );
XNOR2X4TS U3022 ( .A(n1749), .B(n1748), .Y(n1896) );
CLKXOR2X4TS U3023 ( .A(n1769), .B(n1768), .Y(n2092) );
INVX2TS U3024 ( .A(n1772), .Y(n1774) );
CLKXOR2X4TS U3025 ( .A(n1776), .B(n1775), .Y(n1880) );
XNOR2X4TS U3026 ( .A(n1782), .B(n1781), .Y(n2023) );
INVX2TS U3027 ( .A(n1797), .Y(n1876) );
INVX2TS U3028 ( .A(n1828), .Y(n1908) );
OAI21X1TS U3029 ( .A0(n2094), .A1(n2131), .B0(n1850), .Y(n1919) );
INVX2TS U3030 ( .A(n2210), .Y(n1901) );
INVX2TS U3031 ( .A(n1868), .Y(n1978) );
INVX2TS U3032 ( .A(n1869), .Y(n1977) );
NAND2X1TS U3033 ( .A(n1927), .B(n1870), .Y(n1976) );
INVX2TS U3034 ( .A(n1871), .Y(n1903) );
XNOR2X1TS U3035 ( .A(n986), .B(n972), .Y(n1884) );
NAND2X1TS U3036 ( .A(n1894), .B(n1893), .Y(n2213) );
XNOR2X1TS U3037 ( .A(n2025), .B(n972), .Y(n1926) );
AFHCONX2TS U3038 ( .A(n1983), .B(n1982), .CI(n1981), .CON(n2200), .S(n2265)
);
OAI21X4TS U3039 ( .A0(n2174), .A1(n2177), .B0(n2175), .Y(n2163) );
AOI21X4TS U3040 ( .A0(n2004), .A1(n2163), .B0(n2003), .Y(n2135) );
OAI21X4TS U3041 ( .A0(n2154), .A1(n2159), .B0(n2155), .Y(n2145) );
NAND2X2TS U3042 ( .A(n1031), .B(n2187), .Y(n2188) );
INVX2TS U3043 ( .A(n2192), .Y(n2194) );
AFHCONX2TS U3044 ( .A(n2199), .B(n2198), .CI(n2197), .CON(n2195), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
AFHCINX2TS U3045 ( .CIN(n2200), .B(n2201), .A(n2202), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .CO(n2197)
);
CMPR32X2TS U3046 ( .A(n2205), .B(n2204), .C(n2203), .CO(
DP_OP_496J312_122_3540_n557), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
CMPR32X2TS U3047 ( .A(n2208), .B(n2207), .C(n2206), .CO(n2203), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
CMPR32X2TS U3048 ( .A(n2211), .B(n2210), .C(n2209), .CO(n2206), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
INVX2TS U3049 ( .A(n2214), .Y(n2247) );
INVX2TS U3050 ( .A(n2246), .Y(n2215) );
NAND2X1TS U3051 ( .A(n2215), .B(n2245), .Y(n2216) );
INVX2TS U3052 ( .A(n2217), .Y(n2219) );
NAND2X1TS U3053 ( .A(n2219), .B(n2218), .Y(n2221) );
NAND2X1TS U3054 ( .A(n2223), .B(n2222), .Y(n2225) );
XNOR2X1TS U3055 ( .A(n2225), .B(n2224), .Y(FPMULT_Sgf_operation_Result[32])
);
INVX2TS U3056 ( .A(n2226), .Y(n2228) );
XNOR2X1TS U3057 ( .A(n2230), .B(n2229), .Y(FPMULT_Sgf_operation_Result[31])
);
NAND2X1TS U3058 ( .A(n2232), .B(n2231), .Y(n2234) );
XNOR2X1TS U3059 ( .A(n2234), .B(n2233), .Y(FPMULT_Sgf_operation_Result[34])
);
INVX2TS U3060 ( .A(n2235), .Y(n2237) );
NAND2X1TS U3061 ( .A(n2237), .B(n2236), .Y(n2239) );
XOR2X1TS U3062 ( .A(n2242), .B(n1278), .Y(FPMULT_Sgf_operation_Result[38])
);
INVX2TS U3063 ( .A(n2240), .Y(n2241) );
OAI21X1TS U3064 ( .A0(n2247), .A1(n2246), .B0(n2245), .Y(n2252) );
INVX2TS U3065 ( .A(n2248), .Y(n2250) );
CMPR32X2TS U3066 ( .A(n2254), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .C(n2253), .CO(DP_OP_499J312_125_1651_n78), .S(n1345) );
INVX2TS U3067 ( .A(n2861), .Y(DP_OP_499J312_125_1651_n97) );
INVX2TS U3068 ( .A(n2854), .Y(DP_OP_499J312_125_1651_n96) );
INVX2TS U3069 ( .A(n2844), .Y(DP_OP_499J312_125_1651_n95) );
INVX2TS U3070 ( .A(n2863), .Y(DP_OP_499J312_125_1651_n99) );
INVX2TS U3071 ( .A(n2847), .Y(DP_OP_499J312_125_1651_n98) );
INVX2TS U3072 ( .A(n2827), .Y(DP_OP_499J312_125_1651_n100) );
INVX2TS U3073 ( .A(n2830), .Y(DP_OP_499J312_125_1651_n101) );
INVX2TS U3074 ( .A(n2833), .Y(DP_OP_499J312_125_1651_n102) );
INVX2TS U3075 ( .A(n2781), .Y(DP_OP_499J312_125_1651_n103) );
INVX2TS U3076 ( .A(n2835), .Y(DP_OP_499J312_125_1651_n104) );
INVX2TS U3077 ( .A(n2784), .Y(DP_OP_499J312_125_1651_n105) );
INVX2TS U3078 ( .A(n2825), .Y(DP_OP_499J312_125_1651_n106) );
CMPR32X2TS U3079 ( .A(n2259), .B(n2333), .C(n2258), .CO(n2262), .S(n2824) );
INVX2TS U3080 ( .A(n2824), .Y(DP_OP_499J312_125_1651_n108) );
CMPR32X2TS U3081 ( .A(n2334), .B(n2261), .C(n2260), .CO(n2258), .S(n2850) );
INVX2TS U3082 ( .A(n2850), .Y(DP_OP_499J312_125_1651_n109) );
CMPR32X2TS U3083 ( .A(n2263), .B(n2335), .C(n2262), .CO(n2256), .S(n2788) );
INVX2TS U3084 ( .A(n2788), .Y(DP_OP_499J312_125_1651_n107) );
ADDHXLTS U3085 ( .A(n2265), .B(n2264), .CO(DP_OP_499J312_125_1651_n80), .S(
n2254) );
INVX2TS U3086 ( .A(n2373), .Y(n2280) );
INVX2TS U3087 ( .A(n2307), .Y(n2278) );
OAI22X1TS U3088 ( .A0(n2286), .A1(n2280), .B0(n2287), .B1(n2278), .Y(n2276)
);
CMPR32X2TS U3089 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[4]), .C(n2269),
.CO(n1292), .S(n2271) );
XOR2X1TS U3090 ( .A(n2273), .B(n2271), .Y(n2272) );
XNOR2X2TS U3091 ( .A(n2271), .B(n2298), .Y(n2274) );
NAND2X4TS U3092 ( .A(n2272), .B(n2274), .Y(n2380) );
XNOR2X1TS U3093 ( .A(n2375), .B(n2306), .Y(n2288) );
INVX2TS U3094 ( .A(n2375), .Y(n2379) );
OAI22X1TS U3095 ( .A0(n2380), .A1(n2288), .B0(n2379), .B1(n2377), .Y(n2275)
);
CMPR32X2TS U3096 ( .A(n2276), .B(n2275), .C(DP_OP_498J312_124_1725_n29),
.CO(DP_OP_498J312_124_1725_n24), .S(DP_OP_498J312_124_1725_n25) );
OAI22X1TS U3097 ( .A0(n2286), .A1(n2278), .B0(n2287), .B1(n2277), .Y(
DP_OP_498J312_124_1725_n94) );
CMPR32X2TS U3098 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[3]), .C(n2279), .CO(
n2266), .S(n2340) );
INVX2TS U3099 ( .A(n2340), .Y(n2282) );
OAI22X1TS U3100 ( .A0(n2286), .A1(n2282), .B0(n2287), .B1(n2280), .Y(
DP_OP_498J312_124_1725_n96) );
CMPR32X2TS U3101 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[2]), .C(n2281), .CO(
n2279), .S(n2309) );
INVX2TS U3102 ( .A(n2309), .Y(n2283) );
OAI22X1TS U3103 ( .A0(n2286), .A1(n2283), .B0(n2287), .B1(n2282), .Y(
DP_OP_498J312_124_1725_n97) );
INVX2TS U3104 ( .A(n2305), .Y(n2284) );
OAI22X1TS U3105 ( .A0(n2286), .A1(n2284), .B0(n2287), .B1(n2283), .Y(
DP_OP_498J312_124_1725_n98) );
INVX2TS U3106 ( .A(n2376), .Y(n2285) );
OAI22X1TS U3107 ( .A0(n2286), .A1(n2285), .B0(n2287), .B1(n2284), .Y(
DP_OP_498J312_124_1725_n99) );
NOR2BX1TS U3108 ( .AN(n2376), .B(n2287), .Y(DP_OP_498J312_124_1725_n100) );
XNOR2X1TS U3109 ( .A(n2307), .B(n2375), .Y(n2289) );
OAI22X1TS U3110 ( .A0(n2380), .A1(n2289), .B0(n2288), .B1(n2377), .Y(
DP_OP_498J312_124_1725_n103) );
XNOR2X1TS U3111 ( .A(n2375), .B(n2373), .Y(n2290) );
OAI22X1TS U3112 ( .A0(n2380), .A1(n2290), .B0(n2289), .B1(n2377), .Y(
DP_OP_498J312_124_1725_n104) );
XNOR2X1TS U3113 ( .A(n2375), .B(n2340), .Y(n2291) );
OAI22X1TS U3114 ( .A0(n2380), .A1(n2291), .B0(n2290), .B1(n2377), .Y(
DP_OP_498J312_124_1725_n105) );
XNOR2X1TS U3115 ( .A(n2375), .B(n2309), .Y(n2292) );
OAI22X1TS U3116 ( .A0(n2380), .A1(n2292), .B0(n2291), .B1(n2377), .Y(
DP_OP_498J312_124_1725_n106) );
XNOR2X1TS U3117 ( .A(n2375), .B(n2305), .Y(n2367) );
OAI22X1TS U3118 ( .A0(n2380), .A1(n2367), .B0(n2292), .B1(n2377), .Y(
DP_OP_498J312_124_1725_n107) );
CMPR32X2TS U3119 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[2]), .C(n2293), .CO(
n2270), .S(n2295) );
XOR2X1TS U3120 ( .A(n2298), .B(n2295), .Y(n2296) );
XNOR2X1TS U3121 ( .A(n2295), .B(n2294), .Y(n2299) );
NAND2X1TS U3122 ( .A(n2296), .B(n2299), .Y(n2297) );
INVX2TS U3123 ( .A(n2363), .Y(n2301) );
NAND2BX1TS U3124 ( .AN(n2376), .B(n2363), .Y(n2300) );
OAI22X1TS U3125 ( .A0(n2366), .A1(n2301), .B0(n2300), .B1(n2369), .Y(
DP_OP_498J312_124_1725_n91) );
XNOR2X1TS U3126 ( .A(n2306), .B(n2363), .Y(n2302) );
OAI22X1TS U3127 ( .A0(n2302), .A1(n2366), .B0(n2301), .B1(n2369), .Y(
DP_OP_498J312_124_1725_n111) );
XNOR2X1TS U3128 ( .A(n2307), .B(n2363), .Y(n2303) );
OAI22X1TS U3129 ( .A0(n2303), .A1(n2366), .B0(n2302), .B1(n2369), .Y(
DP_OP_498J312_124_1725_n112) );
XNOR2X1TS U3130 ( .A(n2373), .B(n2363), .Y(n2304) );
OAI22X1TS U3131 ( .A0(n2303), .A1(n2369), .B0(n2304), .B1(n2366), .Y(
DP_OP_498J312_124_1725_n113) );
XNOR2X1TS U3132 ( .A(n2340), .B(n2363), .Y(n2344) );
OAI22X1TS U3133 ( .A0(n2304), .A1(n2369), .B0(n2366), .B1(n2344), .Y(
DP_OP_498J312_124_1725_n114) );
XNOR2X1TS U3134 ( .A(n2363), .B(n2305), .Y(n2364) );
XNOR2X1TS U3135 ( .A(n2363), .B(n2309), .Y(n2345) );
OAI22X1TS U3136 ( .A0(n2366), .A1(n2364), .B0(n2345), .B1(n2369), .Y(
DP_OP_498J312_124_1725_n116) );
INVX2TS U3137 ( .A(n2372), .Y(DP_OP_498J312_124_1725_n119) );
XNOR2X1TS U3138 ( .A(n2306), .B(n2372), .Y(n2308) );
OAI22X1TS U3139 ( .A0(n2308), .A1(n1147), .B0(DP_OP_498J312_124_1725_n119),
.B1(n1146), .Y(DP_OP_498J312_124_1725_n120) );
OAI22X1TS U3140 ( .A0(n2374), .A1(n1147), .B0(n2308), .B1(n1146), .Y(
DP_OP_498J312_124_1725_n121) );
XNOR2X1TS U3141 ( .A(n2309), .B(n2372), .Y(n2341) );
OAI22X1TS U3142 ( .A0(n2341), .A1(n1146), .B0(n1147), .B1(n2310), .Y(
DP_OP_498J312_124_1725_n125) );
NOR2X1TS U3143 ( .A(n923), .B(DP_OP_498J312_124_1725_n289), .Y(n2313) );
NOR2X1TS U3144 ( .A(DP_OP_498J312_124_1725_n283), .B(n991), .Y(n2312) );
CMPR32X2TS U3145 ( .A(n2313), .B(n2312), .C(n2311), .CO(
DP_OP_498J312_124_1725_n221), .S(DP_OP_498J312_124_1725_n222) );
CMPR32X2TS U3146 ( .A(n2316), .B(n2315), .C(n2314), .CO(
DP_OP_498J312_124_1725_n226), .S(DP_OP_498J312_124_1725_n227) );
CMPR32X2TS U3147 ( .A(n2319), .B(n2318), .C(n2317), .CO(
DP_OP_498J312_124_1725_n233), .S(DP_OP_498J312_124_1725_n234) );
CMPR32X2TS U3148 ( .A(n2322), .B(n2321), .C(n2320), .CO(
DP_OP_498J312_124_1725_n312), .S(DP_OP_498J312_124_1725_n313) );
CMPR32X2TS U3149 ( .A(n2325), .B(n2324), .C(n2323), .CO(
DP_OP_498J312_124_1725_n317), .S(DP_OP_498J312_124_1725_n318) );
NOR2X1TS U3150 ( .A(DP_OP_498J312_124_1725_n377), .B(
DP_OP_498J312_124_1725_n382), .Y(n2328) );
NOR2X1TS U3151 ( .A(DP_OP_498J312_124_1725_n376), .B(n995), .Y(n2326) );
CMPR32X2TS U3152 ( .A(n2328), .B(n2327), .C(n2326), .CO(
DP_OP_498J312_124_1725_n324), .S(DP_OP_498J312_124_1725_n325) );
INVX2TS U3153 ( .A(n2329), .Y(DP_OP_498J312_124_1725_n196) );
INVX2TS U3154 ( .A(n2330), .Y(DP_OP_498J312_124_1725_n201) );
INVX2TS U3155 ( .A(n2331), .Y(DP_OP_498J312_124_1725_n193) );
INVX2TS U3156 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
DP_OP_498J312_124_1725_n195) );
NOR2X1TS U3157 ( .A(DP_OP_496J312_122_3540_n683), .B(n1021), .Y(
DP_OP_498J312_124_1725_n370) );
NOR2X1TS U3158 ( .A(DP_OP_498J312_124_1725_n378), .B(
DP_OP_498J312_124_1725_n382), .Y(DP_OP_498J312_124_1725_n355) );
INVX2TS U3159 ( .A(n2332), .Y(DP_OP_498J312_124_1725_n83) );
NOR2X1TS U3160 ( .A(n999), .B(n927), .Y(DP_OP_498J312_124_1725_n274) );
INVX2TS U3161 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
DP_OP_498J312_124_1725_n194) );
NOR2X1TS U3162 ( .A(DP_OP_498J312_124_1725_n377), .B(n995), .Y(
DP_OP_498J312_124_1725_n360) );
INVX2TS U3163 ( .A(n2333), .Y(DP_OP_498J312_124_1725_n80) );
INVX2TS U3164 ( .A(n2334), .Y(DP_OP_498J312_124_1725_n81) );
INVX2TS U3165 ( .A(n2335), .Y(DP_OP_498J312_124_1725_n79) );
NOR2X1TS U3166 ( .A(n1016), .B(n927), .Y(DP_OP_498J312_124_1725_n273) );
INVX2TS U3167 ( .A(n2856), .Y(DP_OP_498J312_124_1725_n86) );
INVX2TS U3168 ( .A(n2336), .Y(DP_OP_498J312_124_1725_n82) );
INVX2TS U3169 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(
DP_OP_498J312_124_1725_n192) );
INVX2TS U3170 ( .A(n2337), .Y(DP_OP_498J312_124_1725_n78) );
NOR2X1TS U3171 ( .A(n1016), .B(n1005), .Y(DP_OP_498J312_124_1725_n261) );
NOR2X1TS U3172 ( .A(DP_OP_498J312_124_1725_n283), .B(n1005), .Y(
DP_OP_498J312_124_1725_n260) );
NOR2X1TS U3173 ( .A(DP_OP_496J312_122_3540_n686), .B(
DP_OP_498J312_124_1725_n382), .Y(DP_OP_498J312_124_1725_n351) );
NOR2X1TS U3174 ( .A(n999), .B(DP_OP_498J312_124_1725_n289), .Y(
DP_OP_498J312_124_1725_n250) );
NOR2X1TS U3175 ( .A(DP_OP_498J312_124_1725_n376), .B(n1007), .Y(
DP_OP_498J312_124_1725_n341) );
NOR2X1TS U3176 ( .A(DP_OP_496J312_122_3540_n683), .B(
DP_OP_498J312_124_1725_n382), .Y(DP_OP_498J312_124_1725_n352) );
NOR2X1TS U3177 ( .A(n1016), .B(n1004), .Y(DP_OP_498J312_124_1725_n255) );
NOR2X1TS U3178 ( .A(DP_OP_496J312_122_3540_n683), .B(
DP_OP_498J312_124_1725_n381), .Y(DP_OP_498J312_124_1725_n346) );
NOR2X1TS U3179 ( .A(DP_OP_498J312_124_1725_n381), .B(
DP_OP_498J312_124_1725_n379), .Y(n2339) );
NOR2X1TS U3180 ( .A(DP_OP_498J312_124_1725_n376), .B(n1018), .Y(n2338) );
ADDHXLTS U3181 ( .A(n2339), .B(n2338), .CO(DP_OP_498J312_124_1725_n331), .S(
DP_OP_498J312_124_1725_n332) );
OAI22X1TS U3182 ( .A0(n2381), .A1(n1146), .B0(n2341), .B1(n1147), .Y(
DP_OP_498J312_124_1725_n124) );
NOR2X1TS U3183 ( .A(DP_OP_498J312_124_1725_n377), .B(
DP_OP_498J312_124_1725_n381), .Y(n2343) );
NOR2X1TS U3184 ( .A(DP_OP_498J312_124_1725_n378), .B(n1007), .Y(n2342) );
OAI22X1TS U3185 ( .A0(n2366), .A1(n2345), .B0(n2344), .B1(n2369), .Y(n2346)
);
ADDHXLTS U3186 ( .A(n2348), .B(n2347), .CO(DP_OP_498J312_124_1725_n335), .S(
n1309) );
ADDHXLTS U3187 ( .A(n2350), .B(n2349), .CO(DP_OP_498J312_124_1725_n235), .S(
DP_OP_498J312_124_1725_n236) );
ADDHXLTS U3188 ( .A(n2352), .B(n2351), .CO(DP_OP_498J312_124_1725_n228), .S(
DP_OP_498J312_124_1725_n229) );
INVX2TS U3189 ( .A(n2355), .Y(n2356) );
ADDHX1TS U3190 ( .A(DP_OP_498J312_124_1725_n73), .B(n2356), .CO(n2359), .S(
DP_OP_498J312_124_1725_n72) );
INVX2TS U3191 ( .A(n2357), .Y(n2358) );
CMPR32X2TS U3192 ( .A(n2359), .B(n1255), .C(n2358), .CO(n2362), .S(
DP_OP_498J312_124_1725_n67) );
INVX2TS U3193 ( .A(n2360), .Y(n2361) );
CMPR32X2TS U3194 ( .A(n2362), .B(n2361), .C(DP_OP_498J312_124_1725_n63),
.CO(DP_OP_498J312_124_1725_n59), .S(DP_OP_498J312_124_1725_n60) );
XNOR2X1TS U3195 ( .A(n2363), .B(n2376), .Y(n2365) );
OAI22X1TS U3196 ( .A0(n2366), .A1(n2365), .B0(n2364), .B1(n2369), .Y(
DP_OP_498J312_124_1725_n117) );
XNOR2X1TS U3197 ( .A(n2375), .B(n2376), .Y(n2368) );
OAI22X1TS U3198 ( .A0(n2380), .A1(n2368), .B0(n2367), .B1(n2377), .Y(
DP_OP_498J312_124_1725_n108) );
NOR2BX1TS U3199 ( .AN(n2376), .B(n2369), .Y(DP_OP_498J312_124_1725_n118) );
NOR2X1TS U3200 ( .A(n993), .B(n1005), .Y(n2371) );
NOR2X1TS U3201 ( .A(n1001), .B(n1004), .Y(n2370) );
ADDHXLTS U3202 ( .A(n2371), .B(n2370), .CO(DP_OP_498J312_124_1725_n240), .S(
DP_OP_498J312_124_1725_n241) );
OAI22X1TS U3203 ( .A0(n2374), .A1(n1146), .B0(n2382), .B1(n1147), .Y(
DP_OP_498J312_124_1725_n122) );
NAND2BX1TS U3204 ( .AN(n2376), .B(n2375), .Y(n2378) );
OAI22X1TS U3205 ( .A0(n2380), .A1(n2379), .B0(n2378), .B1(n2377), .Y(
DP_OP_498J312_124_1725_n90) );
NOR2X1TS U3206 ( .A(n1016), .B(n1002), .Y(DP_OP_498J312_124_1725_n279) );
OAI22X1TS U3207 ( .A0(n2382), .A1(n1146), .B0(n2381), .B1(n1147), .Y(
DP_OP_498J312_124_1725_n123) );
NOR2X1TS U3208 ( .A(n923), .B(n991), .Y(DP_OP_498J312_124_1725_n269) );
NOR2X1TS U3209 ( .A(DP_OP_496J312_122_3540_n683), .B(n1018), .Y(
DP_OP_498J312_124_1725_n364) );
INVX2TS U3210 ( .A(n2383), .Y(DP_OP_498J312_124_1725_n202) );
INVX2TS U3211 ( .A(n2384), .Y(n2390) );
INVX2TS U3212 ( .A(n2385), .Y(n2487) );
CMPR32X2TS U3213 ( .A(n2388), .B(n1250), .C(DP_OP_497J312_123_1725_n63),
.CO(DP_OP_497J312_123_1725_n59), .S(DP_OP_497J312_123_1725_n60) );
CMPR32X2TS U3214 ( .A(n2390), .B(n2389), .C(n1256), .CO(n2388), .S(
DP_OP_497J312_123_1725_n67) );
NOR2X1TS U3215 ( .A(n933), .B(n3510), .Y(n2392) );
CMPR32X2TS U3216 ( .A(n2393), .B(n2392), .C(n2391), .CO(
DP_OP_497J312_123_1725_n221), .S(DP_OP_497J312_123_1725_n222) );
NOR2X1TS U3217 ( .A(n933), .B(n1026), .Y(n2395) );
CMPR32X2TS U3218 ( .A(n2396), .B(n2395), .C(n2394), .CO(
DP_OP_497J312_123_1725_n226), .S(DP_OP_497J312_123_1725_n227) );
NOR2X1TS U3219 ( .A(n933), .B(n1024), .Y(n2398) );
CMPR32X2TS U3220 ( .A(n2399), .B(n2398), .C(n2397), .CO(
DP_OP_497J312_123_1725_n233), .S(DP_OP_497J312_123_1725_n234) );
CMPR32X2TS U3221 ( .A(FPMULT_Op_MY[20]), .B(n912), .C(n2400), .CO(
DP_OP_497J312_123_1725_n312), .S(DP_OP_497J312_123_1725_n313) );
ADDHXLTS U3222 ( .A(FPMULT_Op_MY[18]), .B(n913), .CO(
DP_OP_497J312_123_1725_n326), .S(DP_OP_497J312_123_1725_n327) );
INVX2TS U3223 ( .A(n2430), .Y(n2428) );
AOI22X1TS U3224 ( .A0(n2474), .A1(n2428), .B0(n2430), .B1(n2434), .Y(n2473)
);
OAI2BB2X4TS U3225 ( .B0(n933), .B1(n2401), .A0N(n2401), .A1N(n933), .Y(n2476) );
INVX2TS U3226 ( .A(n2476), .Y(n2432) );
AOI22X1TS U3227 ( .A0(n2474), .A1(n2432), .B0(n2476), .B1(n2434), .Y(n2403)
);
OAI22X1TS U3228 ( .A0(n2486), .A1(n2473), .B0(n2472), .B1(n2403), .Y(
DP_OP_497J312_123_1725_n103) );
CMPR32X2TS U3229 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[22]), .C(n2402),
.CO(n2401), .S(n2418) );
AOI22X1TS U3230 ( .A0(n2474), .A1(n2418), .B0(n2477), .B1(n2434), .Y(n2405)
);
OAI22X1TS U3231 ( .A0(n2405), .A1(n2472), .B0(n2486), .B1(n2403), .Y(
DP_OP_497J312_123_1725_n104) );
INVX2TS U3232 ( .A(n2420), .Y(n2425) );
AOI22X1TS U3233 ( .A0(n2474), .A1(n2420), .B0(n2425), .B1(n2434), .Y(n2407)
);
OAI22X1TS U3234 ( .A0(n2405), .A1(n2486), .B0(n2407), .B1(n2472), .Y(
DP_OP_497J312_123_1725_n105) );
CMPR32X2TS U3235 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[20]), .C(n2406),
.CO(n2404), .S(n2422) );
INVX2TS U3236 ( .A(n2422), .Y(n2426) );
AOI22X1TS U3237 ( .A0(n2474), .A1(n2422), .B0(n2426), .B1(n2434), .Y(n2408)
);
OAI22X1TS U3238 ( .A0(n2407), .A1(n2486), .B0(n2408), .B1(n2472), .Y(
DP_OP_497J312_123_1725_n106) );
AOI22X1TS U3239 ( .A0(n2474), .A1(n2424), .B0(n2427), .B1(n2434), .Y(n2410)
);
OAI22X1TS U3240 ( .A0(n2408), .A1(n2486), .B0(n2410), .B1(n2472), .Y(
DP_OP_497J312_123_1725_n107) );
AOI22X1TS U3241 ( .A0(n2474), .A1(n979), .B0(n978), .B1(n2434), .Y(n2409) );
OAI22X1TS U3242 ( .A0(n2410), .A1(n2486), .B0(n2472), .B1(n2409), .Y(
DP_OP_497J312_123_1725_n108) );
AOI22X1TS U3243 ( .A0(n2482), .A1(n2430), .B0(n2428), .B1(n2480), .Y(n2414)
);
CMPR32X2TS U3244 ( .A(FPMULT_Op_MX[14]), .B(n912), .C(n2411), .CO(n1072),
.S(n2413) );
INVX2TS U3245 ( .A(n2413), .Y(n2450) );
OAI221X4TS U3246 ( .A0(n2413), .A1(n2482), .B0(n2450), .B1(n2480), .C0(n2412), .Y(n2484) );
OAI22X1TS U3247 ( .A0(n2414), .A1(n2484), .B0(n2480), .B1(n2412), .Y(
DP_OP_497J312_123_1725_n111) );
AOI22X1TS U3248 ( .A0(n2482), .A1(n2476), .B0(n2432), .B1(n2480), .Y(n2415)
);
OAI22X1TS U3249 ( .A0(n2414), .A1(n2412), .B0(n2415), .B1(n2484), .Y(
DP_OP_497J312_123_1725_n112) );
AOI22X1TS U3250 ( .A0(n2482), .A1(n2477), .B0(n2418), .B1(n2480), .Y(n2416)
);
OAI22X1TS U3251 ( .A0(n2415), .A1(n2412), .B0(n2484), .B1(n2416), .Y(
DP_OP_497J312_123_1725_n113) );
AOI22X1TS U3252 ( .A0(n2482), .A1(n2425), .B0(n2420), .B1(n2480), .Y(n2452)
);
OAI22X1TS U3253 ( .A0(n2412), .A1(n2416), .B0(n2484), .B1(n2452), .Y(
DP_OP_497J312_123_1725_n114) );
AOI22X1TS U3254 ( .A0(n2482), .A1(n2426), .B0(n2422), .B1(n2480), .Y(n2451)
);
AOI22X1TS U3255 ( .A0(n2482), .A1(n2427), .B0(n2424), .B1(n2480), .Y(n2485)
);
OAI22X1TS U3256 ( .A0(n2412), .A1(n2451), .B0(n2484), .B1(n2485), .Y(
DP_OP_497J312_123_1725_n116) );
AOI21X1TS U3257 ( .A0(n2428), .A1(n1063), .B0(n980), .Y(
DP_OP_497J312_123_1725_n120) );
AOI22X1TS U3258 ( .A0(n2476), .A1(n2429), .B0(n980), .B1(n2432), .Y(n2417)
);
AOI22X1TS U3259 ( .A0(n2418), .A1(DP_OP_497J312_123_1725_n119), .B0(n2429),
.B1(n2477), .Y(n2419) );
AOI22X1TS U3260 ( .A0(n2420), .A1(DP_OP_497J312_123_1725_n119), .B0(n2429),
.B1(n2425), .Y(n2421) );
AOI22X1TS U3261 ( .A0(n2422), .A1(DP_OP_497J312_123_1725_n119), .B0(n2429),
.B1(n2426), .Y(n2423) );
AOI22X1TS U3262 ( .A0(n2488), .A1(n2476), .B0(n2430), .B1(n2475), .Y(
DP_OP_497J312_123_1725_n94) );
AOI22X1TS U3263 ( .A0(n2488), .A1(n2425), .B0(n2477), .B1(n2475), .Y(
DP_OP_497J312_123_1725_n96) );
AOI22X1TS U3264 ( .A0(n2488), .A1(n2426), .B0(n2425), .B1(n2475), .Y(
DP_OP_497J312_123_1725_n97) );
AOI22X1TS U3265 ( .A0(n2488), .A1(n2427), .B0(n2426), .B1(n2475), .Y(
DP_OP_497J312_123_1725_n98) );
AOI22X1TS U3266 ( .A0(n2488), .A1(n978), .B0(n2427), .B1(n2475), .Y(
DP_OP_497J312_123_1725_n99) );
AOI22X1TS U3267 ( .A0(n2430), .A1(n2429), .B0(n980), .B1(n2428), .Y(n2431)
);
OAI21X1TS U3268 ( .A0(n2480), .A1(n2435), .B0(n2434), .Y(
DP_OP_497J312_123_1725_n101) );
INVX2TS U3269 ( .A(n2436), .Y(DP_OP_497J312_123_1725_n83) );
NOR2X1TS U3270 ( .A(n1008), .B(n1024), .Y(DP_OP_497J312_123_1725_n279) );
INVX2TS U3271 ( .A(n2438), .Y(DP_OP_497J312_123_1725_n201) );
NOR2X1TS U3272 ( .A(n1006), .B(n1026), .Y(DP_OP_497J312_123_1725_n274) );
INVX2TS U3273 ( .A(n2439), .Y(DP_OP_497J312_123_1725_n81) );
INVX2TS U3274 ( .A(n2440), .Y(DP_OP_497J312_123_1725_n79) );
INVX2TS U3275 ( .A(n2441), .Y(DP_OP_497J312_123_1725_n80) );
INVX2TS U3276 ( .A(n2442), .Y(DP_OP_497J312_123_1725_n82) );
NOR2X1TS U3277 ( .A(n1009), .B(n3510), .Y(DP_OP_497J312_123_1725_n269) );
INVX2TS U3278 ( .A(n2443), .Y(DP_OP_497J312_123_1725_n86) );
NOR2X1TS U3279 ( .A(n1008), .B(n1026), .Y(DP_OP_497J312_123_1725_n273) );
INVX2TS U3280 ( .A(n2446), .Y(DP_OP_497J312_123_1725_n202) );
INVX2TS U3281 ( .A(n2447), .Y(DP_OP_497J312_123_1725_n196) );
INVX2TS U3282 ( .A(n2448), .Y(DP_OP_497J312_123_1725_n197) );
INVX2TS U3283 ( .A(n2449), .Y(DP_OP_497J312_123_1725_n78) );
INVX2TS U3284 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(DP_OP_497J312_123_1725_n195) );
INVX2TS U3285 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(DP_OP_497J312_123_1725_n194) );
NOR2X1TS U3286 ( .A(n933), .B(n921), .Y(DP_OP_497J312_123_1725_n260) );
NOR2X1TS U3287 ( .A(n1008), .B(n921), .Y(DP_OP_497J312_123_1725_n261) );
NOR2X1TS U3288 ( .A(n3509), .B(n1006), .Y(DP_OP_497J312_123_1725_n250) );
NOR2X1TS U3289 ( .A(n1008), .B(n922), .Y(DP_OP_497J312_123_1725_n255) );
OAI21X1TS U3290 ( .A0(n980), .A1(n2450), .B0(n2482), .Y(
DP_OP_497J312_123_1725_n110) );
OAI22X1TS U3291 ( .A0(n2412), .A1(n2452), .B0(n2484), .B1(n2451), .Y(n2455)
);
ADDHX1TS U3292 ( .A(n2455), .B(n2454), .CO(DP_OP_497J312_123_1725_n61), .S(
DP_OP_497J312_123_1725_n62) );
ADDHXLTS U3293 ( .A(n2457), .B(n2456), .CO(DP_OP_497J312_123_1725_n235), .S(
DP_OP_497J312_123_1725_n236) );
OAI32X1TS U3294 ( .A0(n2480), .A1(n979), .A2(n2412), .B0(n2484), .B1(n2480),
.Y(DP_OP_497J312_123_1725_n91) );
ADDHXLTS U3295 ( .A(n2459), .B(n2458), .CO(DP_OP_497J312_123_1725_n228), .S(
DP_OP_497J312_123_1725_n229) );
ADDHXLTS U3296 ( .A(n2461), .B(n2460), .CO(DP_OP_497J312_123_1725_n240), .S(
DP_OP_497J312_123_1725_n241) );
ADDHXLTS U3297 ( .A(n2463), .B(n2462), .CO(DP_OP_497J312_123_1725_n244), .S(
n1258) );
CMPR32X2TS U3298 ( .A(n2468), .B(n2467), .C(n2466), .CO(
DP_OP_497J312_123_1725_n324), .S(DP_OP_497J312_123_1725_n325) );
CMPR32X2TS U3299 ( .A(n2471), .B(n2470), .C(n2469), .CO(
DP_OP_497J312_123_1725_n317), .S(DP_OP_497J312_123_1725_n318) );
OAI22X1TS U3300 ( .A0(n2474), .A1(n2486), .B0(n2473), .B1(n2472), .Y(n2479)
);
AOI22X1TS U3301 ( .A0(n2488), .A1(n2477), .B0(n2476), .B1(n2475), .Y(n2478)
);
CMPR32X2TS U3302 ( .A(n2479), .B(n2478), .C(DP_OP_497J312_123_1725_n29),
.CO(DP_OP_497J312_123_1725_n24), .S(DP_OP_497J312_123_1725_n25) );
AOI22X1TS U3303 ( .A0(n2482), .A1(n978), .B0(n979), .B1(n2480), .Y(n2483) );
OAI22X1TS U3304 ( .A0(n2412), .A1(n2485), .B0(n2484), .B1(n2483), .Y(
DP_OP_497J312_123_1725_n117) );
INVX2TS U3305 ( .A(n3138), .Y(n3139) );
INVX2TS U3306 ( .A(n2573), .Y(n3137) );
NOR2X1TS U3307 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n3137), .Y(n2576) );
INVX2TS U3308 ( .A(n2576), .Y(n2652) );
NOR3X2TS U3309 ( .A(n3526), .B(n3139), .C(n2652), .Y(n107) );
NOR3BX2TS U3310 ( .AN(FPSENCOS_cont_var_out[1]), .B(n3602), .C(
FPSENCOS_cont_var_out[0]), .Y(FPSENCOS_enab_d_ff4_Zn) );
NOR4X1TS U3311 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n3656) );
NOR4X1TS U3312 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n3657) );
NOR4X1TS U3313 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n3658) );
NOR4X1TS U3314 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n3655) );
INVX2TS U3315 ( .A(n3465), .Y(n865) );
NAND2X1TS U3316 ( .A(n3511), .B(FPSENCOS_cont_iter_out[3]), .Y(n2655) );
INVX2TS U3317 ( .A(n2655), .Y(n2574) );
NAND2X1TS U3318 ( .A(n865), .B(FPSENCOS_cont_iter_out[0]), .Y(n3470) );
INVX2TS U3319 ( .A(n3470), .Y(n3469) );
NOR2X1TS U3320 ( .A(n2574), .B(n3469), .Y(n3466) );
OAI211X1TS U3321 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3519), .B0(n3511),
.C0(n3565), .Y(n3468) );
OAI21XLTS U3322 ( .A0(n3466), .A1(n3565), .B0(n3468), .Y(n854) );
OR4X2TS U3323 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n2489) );
NOR4X1TS U3324 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n2489),
.Y(n3651) );
INVX2TS U3325 ( .A(Data_2[19]), .Y(n2492) );
NOR3X2TS U3326 ( .A(FPSENCOS_cont_var_out[1]), .B(n3417), .C(n3522), .Y(
n2501) );
BUFX4TS U3327 ( .A(n2501), .Y(n3420) );
NAND2X1TS U3328 ( .A(FPSENCOS_cont_var_out[1]), .B(n3522), .Y(n2490) );
NOR2X4TS U3329 ( .A(n3417), .B(n2490), .Y(n2493) );
AOI22X1TS U3330 ( .A0(n3420), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n3329),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n2491) );
NAND2X1TS U3331 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n3307) );
NAND2X1TS U3332 ( .A(n3326), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n2515) );
INVX2TS U3333 ( .A(Data_2[29]), .Y(n2495) );
BUFX4TS U3334 ( .A(n2493), .Y(n3357) );
AOI22X1TS U3335 ( .A0(n3420), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n2494) );
NAND2X1TS U3336 ( .A(n3326), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n2498) );
INVX2TS U3337 ( .A(Data_2[28]), .Y(n2497) );
AOI22X1TS U3338 ( .A0(n3420), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n3329),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n2496) );
INVX2TS U3339 ( .A(Data_2[27]), .Y(n2500) );
AOI22X1TS U3340 ( .A0(n3420), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n3329),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n2499) );
INVX2TS U3341 ( .A(Data_2[14]), .Y(n2503) );
BUFX4TS U3342 ( .A(n3358), .Y(n3410) );
AOI22X1TS U3343 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n2502) );
NAND2X1TS U3344 ( .A(n3326), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n2530) );
INVX2TS U3345 ( .A(Data_2[17]), .Y(n2505) );
AOI22X1TS U3346 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n2504) );
NAND2X1TS U3347 ( .A(n3326), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n2520) );
INVX2TS U3348 ( .A(Data_2[16]), .Y(n2507) );
AOI22X1TS U3349 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n2506) );
NAND2X1TS U3350 ( .A(n3326), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n2533) );
INVX2TS U3351 ( .A(Data_2[13]), .Y(n2509) );
AOI22X1TS U3352 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n2508) );
NAND2X1TS U3353 ( .A(n3326), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n2510) );
INVX2TS U3354 ( .A(Data_2[18]), .Y(n2512) );
AOI22X1TS U3355 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n3329),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n2511) );
INVX2TS U3356 ( .A(Data_2[20]), .Y(n2514) );
AOI22X1TS U3357 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n3329),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n2513) );
INVX2TS U3358 ( .A(Data_2[22]), .Y(n2517) );
AOI22X1TS U3359 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n3329),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n2516) );
INVX2TS U3360 ( .A(Data_2[7]), .Y(n2519) );
AOI22X1TS U3361 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n2518) );
NAND2X1TS U3362 ( .A(n3326), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n2528) );
INVX2TS U3363 ( .A(Data_2[15]), .Y(n2522) );
AOI22X1TS U3364 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n2521) );
XNOR2X2TS U3365 ( .A(DP_OP_26J312_126_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n2527) );
OR4X2TS U3366 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n2523) );
OR4X2TS U3367 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n2523), .Y(n2524) );
NOR3X6TS U3368 ( .A(n2527), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n2524),
.Y(n3748) );
AND4X1TS U3369 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n2525) );
AND4X1TS U3370 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n2525), .Y(n2526) );
INVX2TS U3371 ( .A(Data_2[11]), .Y(n3745) );
AOI22X1TS U3372 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n2529) );
INVX2TS U3373 ( .A(Data_2[5]), .Y(n2532) );
AOI22X1TS U3374 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n2531) );
INVX2TS U3375 ( .A(Data_2[3]), .Y(n2535) );
AOI22X1TS U3376 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n3357),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n2534) );
OR2X1TS U3377 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n2565) );
NAND2X1TS U3378 ( .A(n2566), .B(n1035), .Y(n2562) );
NOR3BX2TS U3379 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n2565),
.C(n2562), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
NOR2X2TS U3380 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n997), .Y(n2659) );
NOR2X1TS U3381 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n3138), .Y(n2575) );
AND2X4TS U3382 ( .A(n2659), .B(n2575), .Y(n2536) );
BUFX4TS U3383 ( .A(n3556), .Y(n2901) );
OR2X2TS U3384 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n3556), .Y(n2883) );
INVX4TS U3385 ( .A(n2883), .Y(n3702) );
NAND2X2TS U3386 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n2987) );
INVX2TS U3387 ( .A(n2537), .Y(n2976) );
NOR2X1TS U3388 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n2976), .Y(n2557) );
OAI21X1TS U3389 ( .A0(n2541), .A1(n3568), .B0(n2974), .Y(n2556) );
NOR2X2TS U3390 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n2548), .Y(n2983) );
AOI21X1TS U3391 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n3561), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n2539) );
NOR3X2TS U3392 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n977), .C(n2969), .Y(
n2966) );
OAI22X1TS U3393 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n2978), .B0(n2539),
.B1(n2986), .Y(n2540) );
AOI211X1TS U3394 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n2557), .B0(n2556), .C0(n2540), .Y(n2968) );
NOR2X2TS U3395 ( .A(n3567), .B(n2542), .Y(n2971) );
AOI22X1TS U3396 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n2543), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n2983), .Y(n2546) );
INVX2TS U3397 ( .A(n2548), .Y(n2549) );
NOR2X1TS U3398 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n2552) );
AOI32X1TS U3399 ( .A0(n2553), .A1(n2552), .A2(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B0(n2551), .B1(n2552), .Y(n2560) );
INVX2TS U3400 ( .A(FPMULT_Sgf_normalized_result[21]), .Y(n2999) );
INVX2TS U3401 ( .A(FPMULT_Sgf_normalized_result[19]), .Y(n3002) );
INVX2TS U3402 ( .A(FPMULT_Sgf_normalized_result[17]), .Y(n3005) );
INVX2TS U3403 ( .A(FPMULT_Sgf_normalized_result[15]), .Y(n3008) );
INVX2TS U3404 ( .A(FPMULT_Sgf_normalized_result[13]), .Y(n3011) );
INVX2TS U3405 ( .A(FPMULT_Sgf_normalized_result[11]), .Y(n3014) );
INVX2TS U3406 ( .A(FPMULT_Sgf_normalized_result[9]), .Y(n3017) );
INVX2TS U3407 ( .A(FPMULT_Sgf_normalized_result[7]), .Y(n3020) );
INVX2TS U3408 ( .A(FPMULT_Sgf_normalized_result[5]), .Y(n3023) );
INVX2TS U3409 ( .A(FPMULT_Sgf_normalized_result[3]), .Y(n3024) );
NOR3X2TS U3410 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n3025) );
NOR2X2TS U3411 ( .A(n3024), .B(n3025), .Y(n3028) );
NOR2X2TS U3412 ( .A(FPMULT_Sgf_normalized_result[4]), .B(n3028), .Y(n3027)
);
NOR2X2TS U3413 ( .A(n3023), .B(n3027), .Y(n3022) );
NOR2X2TS U3414 ( .A(n3020), .B(n3021), .Y(n3019) );
NOR2X2TS U3415 ( .A(n3017), .B(n3018), .Y(n3016) );
NOR2X2TS U3416 ( .A(n3014), .B(n3015), .Y(n3013) );
NOR2X2TS U3417 ( .A(n3011), .B(n3012), .Y(n3010) );
NOR2X2TS U3418 ( .A(n3008), .B(n3009), .Y(n3007) );
NOR2X2TS U3419 ( .A(n3005), .B(n3006), .Y(n3004) );
NOR2X2TS U3420 ( .A(n3002), .B(n3003), .Y(n3001) );
NOR2X2TS U3421 ( .A(n2999), .B(n3000), .Y(n2998) );
NOR2X1TS U3422 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .Y(n3193) );
NAND2X1TS U3423 ( .A(n3647), .B(n3193), .Y(n3283) );
BUFX4TS U3424 ( .A(n3283), .Y(n3282) );
OR2X1TS U3425 ( .A(n3282), .B(FPMULT_exp_oper_result[7]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]) );
NAND2X1TS U3426 ( .A(n3424), .B(n3511), .Y(n2654) );
OAI31X1TS U3427 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[1]), .A2(n3511), .B0(n2654), .Y(n856) );
OAI31X4TS U3428 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n3519), .B0(n865), .Y(n3467) );
OAI21XLTS U3429 ( .A0(n3465), .A1(n3565), .B0(n3467), .Y(n859) );
OAI21XLTS U3430 ( .A0(n3565), .A1(n3467), .B0(n2655), .Y(n860) );
AOI22X1TS U3431 ( .A0(n3743), .A1(n3742), .B0(r_mode[0]), .B1(r_mode[1]),
.Y(n2561) );
OAI221X1TS U3432 ( .A0(n3629), .A1(r_mode[1]), .B0(n3744), .B1(r_mode[0]),
.C0(n2561), .Y(n2703) );
NAND2BX1TS U3433 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n2564),
.Y(n2647) );
NOR2X1TS U3434 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n2562),
.Y(n2707) );
NOR2XLTS U3435 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n2563) );
NAND4X1TS U3436 ( .A(n2564), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.C(n2563), .D(n3571), .Y(n3304) );
NAND2X1TS U3437 ( .A(n2756), .B(n3304), .Y(FPSENCOS_enab_d_ff_RB1) );
BUFX3TS U3438 ( .A(n3719), .Y(n3713) );
CLKBUFX2TS U3439 ( .A(n3706), .Y(n3734) );
BUFX3TS U3440 ( .A(n2572), .Y(n3724) );
BUFX3TS U3441 ( .A(n3717), .Y(n3723) );
BUFX3TS U3442 ( .A(n3670), .Y(n3664) );
BUFX3TS U3443 ( .A(n3670), .Y(n3690) );
BUFX3TS U3444 ( .A(n3667), .Y(n3665) );
BUFX3TS U3445 ( .A(n3719), .Y(n3722) );
BUFX3TS U3446 ( .A(n2572), .Y(n3725) );
BUFX3TS U3447 ( .A(n3672), .Y(n3691) );
BUFX3TS U3448 ( .A(n3671), .Y(n3661) );
BUFX3TS U3449 ( .A(n3728), .Y(n3731) );
BUFX3TS U3450 ( .A(n3667), .Y(n3688) );
BUFX3TS U3451 ( .A(n3717), .Y(n3728) );
BUFX3TS U3452 ( .A(n3719), .Y(n3727) );
BUFX3TS U3453 ( .A(n2572), .Y(n3730) );
BUFX3TS U3454 ( .A(n3672), .Y(n3679) );
BUFX3TS U3455 ( .A(n3672), .Y(n3689) );
BUFX3TS U3456 ( .A(n2570), .Y(n3683) );
BUFX3TS U3457 ( .A(n3713), .Y(n3715) );
BUFX3TS U3458 ( .A(n2571), .Y(n3681) );
BUFX3TS U3459 ( .A(n3668), .Y(n3682) );
BUFX3TS U3460 ( .A(n917), .Y(n3732) );
BUFX3TS U3461 ( .A(n2571), .Y(n3686) );
BUFX3TS U3462 ( .A(n2569), .Y(n3685) );
BUFX3TS U3463 ( .A(n3667), .Y(n3677) );
BUFX3TS U3464 ( .A(n3668), .Y(n3666) );
BUFX3TS U3465 ( .A(n3731), .Y(n3714) );
BUFX3TS U3466 ( .A(n3671), .Y(n3662) );
BUFX3TS U3467 ( .A(n3671), .Y(n3673) );
BUFX3TS U3468 ( .A(n2569), .Y(n3680) );
BUFX3TS U3469 ( .A(n2572), .Y(n3720) );
BUFX3TS U3470 ( .A(n3718), .Y(n3716) );
OR2X1TS U3471 ( .A(n3282), .B(FPMULT_exp_oper_result[5]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]) );
OR2X1TS U3472 ( .A(n3282), .B(FPMULT_exp_oper_result[4]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]) );
OR2X1TS U3473 ( .A(n3282), .B(FPMULT_exp_oper_result[3]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]) );
OR2X1TS U3474 ( .A(n3282), .B(FPMULT_exp_oper_result[2]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]) );
OR2X1TS U3475 ( .A(n3282), .B(FPMULT_exp_oper_result[6]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]) );
OR2X1TS U3476 ( .A(n3282), .B(FPMULT_exp_oper_result[1]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]) );
INVX2TS U3477 ( .A(n2659), .Y(n2658) );
OAI32X1TS U3478 ( .A0(n3526), .A1(n3137), .A2(n3139), .B0(
FPMULT_FS_Module_state_reg[1]), .B1(n2658), .Y(
FPMULT_FS_Module_state_next[2]) );
NAND2X1TS U3479 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n2659), .Y(n2662) );
NAND2X1TS U3480 ( .A(n2657), .B(n2662), .Y(FPMULT_FSM_barrel_shifter_load)
);
NAND2X1TS U3481 ( .A(n2678), .B(n3470), .Y(n851) );
NAND2X4TS U3482 ( .A(n2576), .B(n2575), .Y(n3704) );
INVX4TS U3483 ( .A(n3704), .Y(n3474) );
NAND2X2TS U3484 ( .A(n970), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2722)
);
NOR2X2TS U3485 ( .A(n2722), .B(n3581), .Y(n2626) );
NAND2BX2TS U3486 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n2723) );
NAND2X1TS U3487 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n3581), .Y(n2624)
);
OAI22X1TS U3488 ( .A0(n2723), .A1(n3538), .B0(n2624), .B1(n3609), .Y(n2578)
);
AOI211X2TS U3489 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n2577), .B0(n2626),
.C0(n2578), .Y(n2613) );
NOR2BX2TS U3490 ( .AN(n970), .B(n2577), .Y(n2627) );
NAND3X2TS U3491 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n3577), .Y(n2621) );
AOI22X1TS U3492 ( .A0(n2580), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[42]), .Y(n2584) );
NOR2BX1TS U3493 ( .AN(n2577), .B(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n2582) );
AOI22X1TS U3494 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n2583) );
NAND2X1TS U3495 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n970), .Y(n2597)
);
AOI21X1TS U3496 ( .A0(n965), .A1(n2611), .B0(n2585), .Y(n2586) );
OAI21X1TS U3497 ( .A0(n2613), .A1(n2579), .B0(n2586), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[8]) );
CLKAND2X2TS U3498 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
FPADDSUB_formatted_number_W[6]) );
AOI22X1TS U3499 ( .A0(n2580), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n2590) );
AOI22X1TS U3500 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[33]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[29]), .Y(n2589) );
OAI211X1TS U3501 ( .A0(n2742), .A1(n3577), .B0(n2590), .C0(n2589), .Y(n2605)
);
AOI21X1TS U3502 ( .A0(n2738), .A1(n2605), .B0(n2585), .Y(n2591) );
OAI21X1TS U3503 ( .A0(n2579), .A1(n2733), .B0(n2591), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[3]) );
CLKAND2X2TS U3504 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
FPADDSUB_formatted_number_W[1]) );
AOI22X1TS U3505 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[31]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[27]), .Y(n2594) );
AOI22X1TS U3506 ( .A0(n2580), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[35]), .Y(n2593) );
OAI211X1TS U3507 ( .A0(n2613), .A1(n3577), .B0(n2594), .C0(n2593), .Y(n2683)
);
AOI21X1TS U3508 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2683), .B0(n2595), .Y(
n2596) );
OAI21X1TS U3509 ( .A0(n2685), .A1(n2592), .B0(n2596), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[24]) );
CLKAND2X2TS U3510 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
FPADDSUB_formatted_number_W[22]) );
INVX2TS U3511 ( .A(n2597), .Y(n2623) );
AOI22X1TS U3512 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n943),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n2598) );
AOI211X1TS U3513 ( .A0(n2581), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n2623),
.C0(n2599), .Y(n2616) );
AOI22X1TS U3514 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n943),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n2600) );
AOI211X1TS U3515 ( .A0(n2581), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n2623),
.C0(n2601), .Y(n2617) );
AOI22X1TS U3516 ( .A0(n966), .A1(n2616), .B0(n2617), .B1(n2738), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[12]) );
CLKAND2X2TS U3517 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[12]), .Y(
FPADDSUB_formatted_number_W[10]) );
AOI22X1TS U3518 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n943),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n2602) );
AOI211X1TS U3519 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n2581), .B0(n2623),
.C0(n2603), .Y(n2635) );
OR2X1TS U3520 ( .A(n2626), .B(n2623), .Y(n2619) );
AOI211X1TS U3521 ( .A0(n2581), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n2619),
.C0(n2604), .Y(n2636) );
AOI22X1TS U3522 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2635), .B0(n2636),
.B1(n2738), .Y(FPADDSUB_sftr_odat_SHT2_SWR[15]) );
CLKAND2X2TS U3523 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[15]), .Y(
FPADDSUB_formatted_number_W[13]) );
AOI21X1TS U3524 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2605), .B0(n2595), .Y(
n2606) );
OAI21X1TS U3525 ( .A0(n2733), .A1(n2592), .B0(n2606), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[22]) );
CLKAND2X2TS U3526 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
FPADDSUB_formatted_number_W[20]) );
AOI22X1TS U3527 ( .A0(n2580), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n2609) );
AOI22X1TS U3528 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[32]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[28]), .Y(n2608) );
OAI211X1TS U3529 ( .A0(n2745), .A1(n3577), .B0(n2609), .C0(n2608), .Y(n2614)
);
AOI21X1TS U3530 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2614), .B0(n2595), .Y(
n2610) );
OAI21X1TS U3531 ( .A0(n2737), .A1(n2592), .B0(n2610), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[23]) );
CLKAND2X2TS U3532 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
FPADDSUB_formatted_number_W[21]) );
AOI21X1TS U3533 ( .A0(n966), .A1(n2611), .B0(n2595), .Y(n2612) );
OAI21X1TS U3534 ( .A0(n2613), .A1(n2592), .B0(n2612), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[17]) );
CLKAND2X2TS U3535 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
FPADDSUB_formatted_number_W[15]) );
AOI21X1TS U3536 ( .A0(n2738), .A1(n2614), .B0(n2585), .Y(n2615) );
OAI21X1TS U3537 ( .A0(n2737), .A1(n2579), .B0(n2615), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[2]) );
CLKAND2X2TS U3538 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
FPADDSUB_formatted_number_W[0]) );
AOI22X1TS U3539 ( .A0(n966), .A1(n2617), .B0(n2616), .B1(n2738), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[13]) );
CLKAND2X2TS U3540 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[13]), .Y(
FPADDSUB_formatted_number_W[11]) );
AOI211X1TS U3541 ( .A0(FPADDSUB_Data_array_SWR[48]), .A1(n2581), .B0(n2619),
.C0(n2618), .Y(n2633) );
AOI22X1TS U3542 ( .A0(n940), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n943),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n2620) );
AOI211X1TS U3543 ( .A0(n2581), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n2623),
.C0(n2622), .Y(n2634) );
AOI22X1TS U3544 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2633), .B0(n2634),
.B1(n965), .Y(FPADDSUB_sftr_odat_SHT2_SWR[11]) );
CLKAND2X2TS U3545 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[11]), .Y(
FPADDSUB_formatted_number_W[9]) );
OAI22X1TS U3546 ( .A0(n2723), .A1(n3612), .B0(n2624), .B1(n3542), .Y(n2625)
);
AOI211X2TS U3547 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n2577), .B0(n2626),
.C0(n2625), .Y(n2681) );
AOI22X1TS U3548 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[43]), .Y(n2629) );
AOI22X1TS U3549 ( .A0(n943), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n2580),
.B1(FPADDSUB_Data_array_SWR[47]), .Y(n2628) );
AOI21X1TS U3550 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2631), .B0(n2595), .Y(
n2630) );
OAI21X1TS U3551 ( .A0(n2681), .A1(n2592), .B0(n2630), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[16]) );
CLKAND2X2TS U3552 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
FPADDSUB_formatted_number_W[14]) );
AOI21X1TS U3553 ( .A0(n925), .A1(n2631), .B0(n2585), .Y(n2632) );
OAI21X1TS U3554 ( .A0(n2681), .A1(n2579), .B0(n2632), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[9]) );
CLKAND2X2TS U3555 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
FPADDSUB_formatted_number_W[7]) );
AOI22X1TS U3556 ( .A0(n966), .A1(n2634), .B0(n2633), .B1(n965), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[14]) );
CLKAND2X2TS U3557 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[14]), .Y(
FPADDSUB_formatted_number_W[12]) );
AOI22X1TS U3558 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2636), .B0(n2635),
.B1(n965), .Y(FPADDSUB_sftr_odat_SHT2_SWR[10]) );
CLKAND2X2TS U3559 ( .A(n2587), .B(FPADDSUB_sftr_odat_SHT2_SWR[10]), .Y(
FPADDSUB_formatted_number_W[8]) );
NOR2XLTS U3560 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n2637) );
OR2X2TS U3561 ( .A(FPMULT_FSM_selector_B[1]), .B(n3572), .Y(n2644) );
XOR2X1TS U3562 ( .A(n2536), .B(n2638), .Y(DP_OP_234J312_129_4955_n22) );
OAI2BB1X1TS U3563 ( .A0N(FPMULT_Op_MY[24]), .A1N(n3566), .B0(n2644), .Y(
n2639) );
XOR2X1TS U3564 ( .A(n2536), .B(n2639), .Y(DP_OP_234J312_129_4955_n21) );
OAI2BB1X1TS U3565 ( .A0N(FPMULT_Op_MY[25]), .A1N(n3566), .B0(n2644), .Y(
n2640) );
XOR2X1TS U3566 ( .A(n2536), .B(n2640), .Y(DP_OP_234J312_129_4955_n20) );
OAI2BB1X1TS U3567 ( .A0N(FPMULT_Op_MY[26]), .A1N(n3566), .B0(n2644), .Y(
n2641) );
XOR2X1TS U3568 ( .A(n2536), .B(n2641), .Y(DP_OP_234J312_129_4955_n19) );
OAI2BB1X1TS U3569 ( .A0N(FPMULT_Op_MY[27]), .A1N(n3566), .B0(n2644), .Y(
n2642) );
XOR2X1TS U3570 ( .A(n2536), .B(n2642), .Y(DP_OP_234J312_129_4955_n18) );
OAI2BB1X1TS U3571 ( .A0N(FPMULT_Op_MY[28]), .A1N(n3566), .B0(n2644), .Y(
n2643) );
XOR2X1TS U3572 ( .A(n2536), .B(n2643), .Y(DP_OP_234J312_129_4955_n17) );
OAI2BB1X1TS U3573 ( .A0N(FPMULT_Op_MY[29]), .A1N(n3566), .B0(n2644), .Y(
n2645) );
XOR2X1TS U3574 ( .A(n2536), .B(n2645), .Y(DP_OP_234J312_129_4955_n16) );
NOR3BX1TS U3575 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n2646) );
XOR2X1TS U3576 ( .A(n2536), .B(n2646), .Y(DP_OP_234J312_129_4955_n15) );
NOR2X1TS U3577 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n2647),
.Y(n2706) );
NAND3BX1TS U3578 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n2706), .Y(n3300) );
INVX2TS U3579 ( .A(n3300), .Y(n2650) );
NAND2X1TS U3580 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n3137), .Y(n2701) );
NOR3X2TS U3581 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n3138), .C(n2701),
.Y(n3475) );
AOI22X1TS U3582 ( .A0(n3464), .A1(ready_add_subt), .B0(n3475), .B1(n3458),
.Y(n2649) );
OAI2BB1X1TS U3583 ( .A0N(n2650), .A1N(n3425), .B0(n2649), .Y(operation_ready) );
INVX4TS U3584 ( .A(n3474), .Y(n3694) );
INVX4TS U3585 ( .A(n3474), .Y(n3693) );
INVX4TS U3586 ( .A(n3474), .Y(n3692) );
INVX4TS U3587 ( .A(n3474), .Y(n3695) );
INVX4TS U3588 ( .A(n3474), .Y(n3697) );
INVX4TS U3589 ( .A(n3474), .Y(n3698) );
INVX4TS U3590 ( .A(n3474), .Y(n3699) );
INVX4TS U3591 ( .A(n3474), .Y(n3700) );
INVX4TS U3592 ( .A(n3474), .Y(n3701) );
INVX4TS U3593 ( .A(n3474), .Y(n3696) );
BUFX3TS U3594 ( .A(n2651), .Y(n3670) );
BUFX3TS U3595 ( .A(n2651), .Y(n3668) );
BUFX3TS U3596 ( .A(n2651), .Y(n3669) );
NAND2X1TS U3597 ( .A(n3601), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1048_CI) );
OAI21XLTS U3598 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n3601), .B0(
intadd_1048_CI), .Y(FPSENCOS_sh_exp_x[0]) );
NAND2X1TS U3599 ( .A(n3600), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1049_CI) );
OAI21XLTS U3600 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n3600), .B0(
intadd_1049_CI), .Y(FPSENCOS_sh_exp_y[0]) );
NAND2X1TS U3601 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n989), .Y(n2661) );
NAND2X1TS U3602 ( .A(n3526), .B(n3138), .Y(n2665) );
NAND2X1TS U3603 ( .A(n938), .B(n926), .Y(n3026) );
OAI21XLTS U3604 ( .A0(n926), .A1(n938), .B0(n3026), .Y(
FPMULT_Adder_M_result_A_adder[1]) );
BUFX4TS U3605 ( .A(n3283), .Y(n3284) );
NOR2XLTS U3606 ( .A(n3017), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]) );
NOR2XLTS U3607 ( .A(n3014), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]) );
NOR2XLTS U3608 ( .A(n3011), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]) );
NOR2XLTS U3609 ( .A(n3008), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]) );
NOR2XLTS U3610 ( .A(n3020), .B(n3282), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]) );
OR2X1TS U3611 ( .A(n3282), .B(FPMULT_exp_oper_result[0]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]) );
INVX2TS U3612 ( .A(intadd_1050_SUM_0_), .Y(FPADDSUB_Shift_amount_EXP_EW[1])
);
NOR2X1TS U3613 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[1]), .Y(n2656) );
NOR2XLTS U3614 ( .A(n3424), .B(n2656), .Y(FPSENCOS_ITER_CONT_N3) );
OAI21XLTS U3615 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n3477), .B0(n3192), .Y(n874) );
INVX2TS U3616 ( .A(intadd_1050_SUM_1_), .Y(FPADDSUB_Shift_amount_EXP_EW[2])
);
INVX2TS U3617 ( .A(n2653), .Y(n2666) );
NOR3XLTS U3618 ( .A(n3526), .B(n3139), .C(n2666), .Y(
FPMULT_FSM_final_result_load) );
OAI21XLTS U3619 ( .A0(n3465), .A1(FPSENCOS_cont_iter_out[1]), .B0(n2678),
.Y(n864) );
NAND3X2TS U3620 ( .A(n3512), .B(n3519), .C(n3565), .Y(n3194) );
OAI211XLTS U3621 ( .A0(n2656), .A1(n2655), .B0(n2654), .C0(n3194), .Y(n855)
);
OAI22X1TS U3622 ( .A0(n3138), .A1(n2658), .B0(n2657), .B1(n3628), .Y(
FPMULT_FSM_load_second_step) );
OR2X1TS U3623 ( .A(n107), .B(FPMULT_FSM_load_second_step), .Y(
FPMULT_FSM_exp_operation_load_result) );
INVX2TS U3624 ( .A(intadd_1050_SUM_2_), .Y(FPADDSUB_Shift_amount_EXP_EW[3])
);
INVX2TS U3625 ( .A(n2665), .Y(n2702) );
CLKAND2X2TS U3626 ( .A(n2702), .B(n2659), .Y(n2993) );
AOI22X1TS U3627 ( .A0(n2993), .A1(n3545), .B0(n2536), .B1(n996), .Y(n2660)
);
OAI21XLTS U3628 ( .A0(n3138), .A1(n3137), .B0(n2660), .Y(
FPMULT_FS_Module_state_next[0]) );
NOR2X1TS U3629 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_1049_n1), .Y(n3505) );
OR3X1TS U3630 ( .A(FPSENCOS_d_ff2_Y[27]), .B(FPSENCOS_d_ff2_Y[28]), .C(
intadd_1049_n1), .Y(n3504) );
NOR2X1TS U3631 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_1048_n1), .Y(n3508) );
OR3X1TS U3632 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_1048_n1), .Y(n3507) );
OAI21XLTS U3633 ( .A0(n3508), .A1(n3644), .B0(n3507), .Y(
FPSENCOS_sh_exp_x[5]) );
INVX2TS U3634 ( .A(n2661), .Y(intadd_1050_CI) );
INVX2TS U3635 ( .A(n2536), .Y(n2989) );
NAND2X1TS U3636 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n3220) );
AOI22X1TS U3637 ( .A0(n910), .A1(n2668), .B0(n3220), .B1(n3703), .Y(n2664)
);
NAND2X1TS U3638 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(n3513), .Y(n2667) );
OAI21XLTS U3639 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n3513), .B0(n2667),
.Y(n2663) );
XOR2XLTS U3640 ( .A(n2664), .B(n2663), .Y(FPADDSUB_Raw_mant_SGF[3]) );
NOR2X1TS U3641 ( .A(n2666), .B(n2665), .Y(FPMULT_FSM_adder_round_norm_load)
);
NAND2X1TS U3642 ( .A(FPSENCOS_cont_iter_out[2]), .B(n3424), .Y(n3423) );
CLKAND2X2TS U3643 ( .A(n3423), .B(n3512), .Y(n857) );
NOR2X1TS U3644 ( .A(n3512), .B(n3423), .Y(n2758) );
OAI21XLTS U3645 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n865), .B0(n3470), .Y(
n849) );
OAI21XLTS U3646 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3467), .B0(n2678),
.Y(n862) );
NOR2X1TS U3647 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n3548), .Y(n2671) );
AOI222X4TS U3648 ( .A0(n3513), .A1(n3220), .B0(n3513), .B1(n3546), .C0(n3220), .C1(n3546), .Y(n2674) );
BUFX3TS U3649 ( .A(n3703), .Y(n2818) );
AOI22X1TS U3650 ( .A0(n910), .A1(n2672), .B0(n2674), .B1(n2818), .Y(n2670)
);
OAI31X1TS U3651 ( .A0(n2671), .A1(n2670), .A2(n2673), .B0(n2669), .Y(
FPADDSUB_Raw_mant_SGF[4]) );
OR2X4TS U3652 ( .A(FPSENCOS_cont_iter_out[2]), .B(n3194), .Y(n3289) );
OR2X1TS U3653 ( .A(FPSENCOS_d_ff_Xn[27]), .B(n3288), .Y(
FPSENCOS_first_mux_X[27]) );
OR2X1TS U3654 ( .A(FPSENCOS_d_ff_Xn[24]), .B(n3288), .Y(
FPSENCOS_first_mux_X[24]) );
OR2X1TS U3655 ( .A(FPSENCOS_d_ff_Xn[25]), .B(n3288), .Y(
FPSENCOS_first_mux_X[25]) );
OR2X1TS U3656 ( .A(FPSENCOS_d_ff_Xn[26]), .B(n3288), .Y(
FPSENCOS_first_mux_X[26]) );
OR2X1TS U3657 ( .A(FPSENCOS_d_ff_Xn[19]), .B(n3288), .Y(
FPSENCOS_first_mux_X[19]) );
OR2X1TS U3658 ( .A(FPSENCOS_d_ff_Xn[20]), .B(n3288), .Y(
FPSENCOS_first_mux_X[20]) );
OR2X1TS U3659 ( .A(FPSENCOS_d_ff_Xn[17]), .B(n3288), .Y(
FPSENCOS_first_mux_X[17]) );
OR2X1TS U3660 ( .A(FPSENCOS_d_ff_Xn[29]), .B(n3288), .Y(
FPSENCOS_first_mux_X[29]) );
OR2X1TS U3661 ( .A(FPSENCOS_d_ff_Xn[14]), .B(n3288), .Y(
FPSENCOS_first_mux_X[14]) );
OR2X1TS U3662 ( .A(FPSENCOS_d_ff_Xn[16]), .B(n3288), .Y(
FPSENCOS_first_mux_X[16]) );
OR2X1TS U3663 ( .A(FPSENCOS_d_ff_Xn[13]), .B(n3288), .Y(
FPSENCOS_first_mux_X[13]) );
OAI22X1TS U3664 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(n3548), .B0(n2673),
.B1(n2672), .Y(n2689) );
AOI22X1TS U3665 ( .A0(n910), .A1(n2689), .B0(n2691), .B1(n2818), .Y(n2676)
);
NAND2X1TS U3666 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n3514), .Y(n2690) );
XOR2XLTS U3667 ( .A(n2676), .B(n2675), .Y(FPADDSUB_Raw_mant_SGF[5]) );
INVX2TS U3668 ( .A(n3287), .Y(n2677) );
OR2X1TS U3669 ( .A(FPSENCOS_d_ff_Xn[7]), .B(n2677), .Y(
FPSENCOS_first_mux_X[7]) );
OR2X1TS U3670 ( .A(FPSENCOS_d_ff_Xn[1]), .B(n2677), .Y(
FPSENCOS_first_mux_X[1]) );
OR2X1TS U3671 ( .A(FPSENCOS_d_ff_Xn[12]), .B(n2677), .Y(
FPSENCOS_first_mux_X[12]) );
OR2X1TS U3672 ( .A(FPSENCOS_d_ff_Xn[10]), .B(n2677), .Y(
FPSENCOS_first_mux_X[10]) );
OR2X1TS U3673 ( .A(FPSENCOS_d_ff_Xn[3]), .B(n2677), .Y(
FPSENCOS_first_mux_X[3]) );
OR2X1TS U3674 ( .A(FPSENCOS_d_ff_Xn[6]), .B(n2677), .Y(
FPSENCOS_first_mux_X[6]) );
OR2X1TS U3675 ( .A(FPSENCOS_d_ff_Xn[5]), .B(n2677), .Y(
FPSENCOS_first_mux_X[5]) );
OR2X1TS U3676 ( .A(FPSENCOS_d_ff_Xn[2]), .B(n2677), .Y(
FPSENCOS_first_mux_X[2]) );
OAI21X1TS U3677 ( .A0(n3465), .A1(n3565), .B0(n2678), .Y(n863) );
OR2X1TS U3678 ( .A(n863), .B(n3469), .Y(n850) );
AOI22X1TS U3679 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[30]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n2680) );
AOI22X1TS U3680 ( .A0(n944), .A1(FPADDSUB_Data_array_SWR[26]), .B0(n2580),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n2679) );
OAI211X1TS U3681 ( .A0(n2681), .A1(n3577), .B0(n2680), .C0(n2679), .Y(n2686)
);
AOI21X1TS U3682 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2686), .B0(n2595), .Y(
n2682) );
OAI21XLTS U3683 ( .A0(n2688), .A1(n2592), .B0(n2682), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[25]) );
AOI21X1TS U3684 ( .A0(n965), .A1(n2683), .B0(n2585), .Y(n2684) );
AOI21X1TS U3685 ( .A0(n965), .A1(n2686), .B0(n2585), .Y(n2687) );
OAI21XLTS U3686 ( .A0(n2579), .A1(n2688), .B0(n2687), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[0]) );
NOR2X1TS U3687 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n3549), .Y(n2694) );
AOI222X4TS U3688 ( .A0(n2691), .A1(n3514), .B0(n2691), .B1(n3550), .C0(n3514), .C1(n3550), .Y(n2697) );
AOI22X1TS U3689 ( .A0(n910), .A1(n2695), .B0(n2697), .B1(n2818), .Y(n2693)
);
OAI31X1TS U3690 ( .A0(n2694), .A1(n2693), .A2(n2696), .B0(n2692), .Y(
FPADDSUB_Raw_mant_SGF[6]) );
OAI22X1TS U3691 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n3549), .B0(n2696),
.B1(n2695), .Y(n2710) );
AOI22X1TS U3692 ( .A0(n910), .A1(n2710), .B0(n2712), .B1(n2818), .Y(n2699)
);
NAND2X1TS U3693 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n3515), .Y(n2711) );
OAI21XLTS U3694 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n3515), .B0(n2711),
.Y(n2698) );
XOR2XLTS U3695 ( .A(n2699), .B(n2698), .Y(FPADDSUB_Raw_mant_SGF[7]) );
INVX2TS U3696 ( .A(n2700), .Y(n2704) );
AOI22X1TS U3697 ( .A0(n2704), .A1(n2703), .B0(n2702), .B1(n2701), .Y(n2705)
);
OAI31X1TS U3698 ( .A0(n3138), .A1(n3137), .A2(n3526), .B0(n2705), .Y(
FPMULT_FS_Module_state_next[1]) );
OR2X1TS U3699 ( .A(n3748), .B(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
FPADDSUB_formatted_number_W[26]) );
OR2X1TS U3700 ( .A(n3748), .B(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
FPADDSUB_formatted_number_W[25]) );
OR2X1TS U3701 ( .A(n3748), .B(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
FPADDSUB_formatted_number_W[23]) );
OR2X1TS U3702 ( .A(n3748), .B(FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
FPADDSUB_formatted_number_W[24]) );
OR2X1TS U3703 ( .A(n3748), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
FPADDSUB_formatted_number_W[29]) );
OR2X1TS U3704 ( .A(n3748), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
FPADDSUB_formatted_number_W[28]) );
INVX2TS U3705 ( .A(n3192), .Y(n3479) );
NAND3BX1TS U3706 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n2707),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n3308) );
NAND2X1TS U3707 ( .A(n3309), .B(n3308), .Y(n2708) );
AOI22X1TS U3708 ( .A0(n953), .A1(n2708), .B0(begin_operation), .B1(n3464),
.Y(n3476) );
INVX2TS U3709 ( .A(n3477), .Y(n2709) );
NOR2X1TS U3710 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n3552), .Y(n2715) );
AOI222X4TS U3711 ( .A0(n2712), .A1(n3515), .B0(n2712), .B1(n3551), .C0(n3515), .C1(n3551), .Y(n2718) );
AOI22X1TS U3712 ( .A0(n910), .A1(n2716), .B0(n2718), .B1(n2818), .Y(n2714)
);
OAI31X1TS U3713 ( .A0(n2715), .A1(n2714), .A2(n2717), .B0(n2713), .Y(
FPADDSUB_Raw_mant_SGF[8]) );
OAI22X1TS U3714 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(n3552), .B0(n2717),
.B1(n2716), .Y(n2759) );
AOI22X1TS U3715 ( .A0(n910), .A1(n2759), .B0(n2761), .B1(n2818), .Y(n2720)
);
NAND2X1TS U3716 ( .A(FPADDSUB_DmP_mant_SFG_SWR[9]), .B(n3516), .Y(n2760) );
OAI21XLTS U3717 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n3516), .B0(n2760),
.Y(n2719) );
XOR2XLTS U3718 ( .A(n2720), .B(n2719), .Y(FPADDSUB_Raw_mant_SGF[9]) );
AOI22X1TS U3719 ( .A0(n2580), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n2726) );
AOI22X1TS U3720 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[31]), .Y(n2725) );
OAI211X1TS U3721 ( .A0(n2753), .A1(n3577), .B0(n2726), .C0(n2725), .Y(n2746)
);
AOI21X1TS U3722 ( .A0(n925), .A1(n2746), .B0(n2585), .Y(n2727) );
OAI21X1TS U3723 ( .A0(n2748), .A1(n2579), .B0(n2727), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[5]) );
AOI22X1TS U3724 ( .A0(n2580), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n939),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n2729) );
AOI22X1TS U3725 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[30]), .Y(n2728) );
OAI211X1TS U3726 ( .A0(n2748), .A1(n3577), .B0(n2729), .C0(n2728), .Y(n2749)
);
AOI21X1TS U3727 ( .A0(n2738), .A1(n2749), .B0(n2585), .Y(n2730) );
OAI21X1TS U3728 ( .A0(n2753), .A1(n2579), .B0(n2730), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[4]) );
AOI22X1TS U3729 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n2580), .B0(
FPADDSUB_Data_array_SWR[40]), .B1(n939), .Y(n2732) );
AOI22X1TS U3730 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[36]), .B0(
FPADDSUB_Data_array_SWR[32]), .B1(n943), .Y(n2731) );
AOI21X1TS U3731 ( .A0(n2738), .A1(n2740), .B0(n2585), .Y(n2734) );
OAI21X1TS U3732 ( .A0(n2742), .A1(n2579), .B0(n2734), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[6]) );
AOI22X1TS U3733 ( .A0(n2580), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n2736) );
AOI22X1TS U3734 ( .A0(n941), .A1(FPADDSUB_Data_array_SWR[37]), .B0(n944),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n2735) );
AOI21X1TS U3735 ( .A0(n2738), .A1(n2743), .B0(n2585), .Y(n2739) );
OAI21X1TS U3736 ( .A0(n2745), .A1(n2579), .B0(n2739), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[7]) );
AOI21X1TS U3737 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2740), .B0(n2595), .Y(
n2741) );
OAI21X1TS U3738 ( .A0(n2742), .A1(n2592), .B0(n2741), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[19]) );
AOI21X1TS U3739 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2743), .B0(n2595), .Y(
n2744) );
OAI21X1TS U3740 ( .A0(n2745), .A1(n2592), .B0(n2744), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[18]) );
AOI21X1TS U3741 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2746), .B0(n2595), .Y(
n2747) );
OAI21X1TS U3742 ( .A0(n2748), .A1(n2592), .B0(n2747), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[20]) );
AOI21X1TS U3743 ( .A0(n966), .A1(n2749), .B0(n2595), .Y(n2751) );
OAI21X1TS U3744 ( .A0(n2753), .A1(n2592), .B0(n2751), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[21]) );
NOR2BX1TS U3745 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2754) );
XOR2X1TS U3746 ( .A(n911), .B(n2754), .Y(DP_OP_26J312_126_1325_n15) );
NOR2BX1TS U3747 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2755) );
XOR2X1TS U3748 ( .A(n911), .B(n2755), .Y(DP_OP_26J312_126_1325_n14) );
INVX2TS U3749 ( .A(enab_cont_iter), .Y(n2757) );
OAI21XLTS U3750 ( .A0(n2758), .A1(n2757), .B0(n2756), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
NOR2X1TS U3751 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n3554), .Y(n2764) );
AOI222X4TS U3752 ( .A0(n2761), .A1(n3516), .B0(n2761), .B1(n3553), .C0(n3516), .C1(n3553), .Y(n2769) );
AOI22X1TS U3753 ( .A0(n910), .A1(n2767), .B0(n2769), .B1(n2818), .Y(n2763)
);
OAI31X1TS U3754 ( .A0(n2764), .A1(n2763), .A2(n2768), .B0(n2762), .Y(
FPADDSUB_Raw_mant_SGF[10]) );
AOI222X1TS U3755 ( .A0(n2765), .A1(Data_2[30]), .B0(n3357), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .C0(FPSENCOS_d_ff3_sh_y_out[30]), .C1(
n3392), .Y(n2766) );
INVX2TS U3756 ( .A(n2766), .Y(add_subt_data2[30]) );
OAI22X1TS U3757 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(n3554), .B0(n2768),
.B1(n2767), .Y(n2774) );
AOI22X1TS U3758 ( .A0(n910), .A1(n2774), .B0(n2776), .B1(n2818), .Y(n2771)
);
NAND2X1TS U3759 ( .A(FPADDSUB_DmP_mant_SFG_SWR[11]), .B(n3557), .Y(n2775) );
AND4X1TS U3760 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[0]), .D(
FPMULT_Exp_module_Data_S[1]), .Y(n2772) );
AND4X1TS U3761 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n2772), .Y(n2773) );
CLKAND2X2TS U3762 ( .A(FPMULT_FSM_selector_A), .B(FPMULT_exp_oper_result[8]),
.Y(FPMULT_S_Oper_A_exp[8]) );
NOR2X1TS U3763 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n3560), .Y(n2779) );
INVX4TS U3764 ( .A(n3703), .Y(n3252) );
AOI222X4TS U3765 ( .A0(n2776), .A1(n3557), .B0(n2776), .B1(n3517), .C0(n3557), .C1(n3517), .Y(n2793) );
AOI22X1TS U3766 ( .A0(n3252), .A1(n2791), .B0(n2793), .B1(n2818), .Y(n2778)
);
OAI31X1TS U3767 ( .A0(n2779), .A1(n2778), .A2(n2792), .B0(n2777), .Y(
FPADDSUB_Raw_mant_SGF[12]) );
AFHCINX2TS U3768 ( .CIN(n2780), .B(n2781), .A(n2782), .S(n2790), .CO(n2832)
);
CLKAND2X2TS U3769 ( .A(n2786), .B(n2785), .Y(n2789) );
NOR4X1TS U3770 ( .A(n2790), .B(n2789), .C(n2788), .D(n2787), .Y(n3652) );
AOI22X1TS U3771 ( .A0(n3252), .A1(n2796), .B0(n2798), .B1(n2818), .Y(n2795)
);
NAND2X1TS U3772 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n3518), .Y(n2797) );
OAI21XLTS U3773 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n3518), .B0(n2797),
.Y(n2794) );
NOR2X1TS U3774 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n3563), .Y(n2801) );
AOI222X4TS U3775 ( .A0(n2798), .A1(n3518), .B0(n2798), .B1(n3559), .C0(n3518), .C1(n3559), .Y(n2804) );
AOI22X1TS U3776 ( .A0(n3252), .A1(n2802), .B0(n2804), .B1(n3703), .Y(n2800)
);
OAI31X1TS U3777 ( .A0(n2801), .A1(n2800), .A2(n2803), .B0(n2799), .Y(
FPADDSUB_Raw_mant_SGF[14]) );
NOR2X1TS U3778 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n3573), .Y(n2807) );
NAND2X1TS U3779 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n3520), .Y(n3226) );
AOI222X4TS U3780 ( .A0(n3224), .A1(n3520), .B0(n3224), .B1(n3564), .C0(n3520), .C1(n3564), .Y(n2810) );
AOI22X1TS U3781 ( .A0(n3252), .A1(n2808), .B0(n2810), .B1(n2818), .Y(n2806)
);
OAI31X1TS U3782 ( .A0(n2807), .A1(n2806), .A2(n2809), .B0(n2805), .Y(
FPADDSUB_Raw_mant_SGF[16]) );
NOR2X1TS U3783 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n3576), .Y(n2813) );
NAND2X1TS U3784 ( .A(FPADDSUB_DmP_mant_SFG_SWR[17]), .B(n3523), .Y(n3231) );
AOI222X4TS U3785 ( .A0(n3229), .A1(n3523), .B0(n3229), .B1(n3574), .C0(n3523), .C1(n3574), .Y(n2817) );
AOI22X1TS U3786 ( .A0(n3252), .A1(n2815), .B0(n2817), .B1(n2818), .Y(n2812)
);
OAI31X1TS U3787 ( .A0(n2813), .A1(n2812), .A2(n2816), .B0(n2811), .Y(
FPADDSUB_Raw_mant_SGF[18]) );
AOI22X2TS U3788 ( .A0(n3702), .A1(FPADDSUB_LZD_raw_out_EWR[1]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n2901), .Y(n2885) );
OAI22X2TS U3789 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(FPADDSUB_LZD_raw_out_EWR[0]),
.B1(n2883), .Y(n2874) );
NOR2X1TS U3790 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n3580), .Y(n2821) );
NAND2X1TS U3791 ( .A(FPADDSUB_DmP_mant_SFG_SWR[19]), .B(n3579), .Y(n3236) );
AOI222X4TS U3792 ( .A0(n3234), .A1(n3579), .B0(n3234), .B1(n3524), .C0(n3579), .C1(n3524), .Y(n2878) );
AOI22X1TS U3793 ( .A0(n3252), .A1(n2876), .B0(n2878), .B1(n2818), .Y(n2820)
);
OAI31X1TS U3794 ( .A0(n2821), .A1(n2820), .A2(n2877), .B0(n2819), .Y(
FPADDSUB_Raw_mant_SGF[20]) );
NOR4X1TS U3795 ( .A(n2825), .B(n2824), .C(n2823), .D(n2822), .Y(n2872) );
AFHCONX2TS U3796 ( .A(n2828), .B(n2827), .CI(n2826), .CON(n2862), .S(n2841)
);
AFHCINX2TS U3797 ( .CIN(n2829), .B(n2830), .A(n2831), .S(n2840), .CO(n2826)
);
AFHCONX2TS U3798 ( .A(n2834), .B(n2833), .CI(n2832), .CON(n2829), .S(n2839)
);
AFHCONX2TS U3799 ( .A(n2837), .B(n2836), .CI(n2835), .CON(n2780), .S(n2838)
);
NOR4X1TS U3800 ( .A(n2841), .B(n2840), .C(n2839), .D(n2838), .Y(n2851) );
AFHCINX4TS U3801 ( .CIN(n2842), .B(n2843), .A(n2844), .S(n2849), .CO(n1493)
);
AFHCONX2TS U3802 ( .A(n2847), .B(n2846), .CI(n2845), .CON(n2859), .S(n2848)
);
NOR4BX1TS U3803 ( .AN(n2851), .B(n2850), .C(n2849), .D(n2848), .Y(n2871) );
AFHCONX2TS U3804 ( .A(n2854), .B(n2853), .CI(n2852), .CON(n2842), .S(n2858)
);
NOR4X1TS U3805 ( .A(n2858), .B(n2857), .C(n2856), .D(n2855), .Y(n2870) );
AFHCINX2TS U3806 ( .CIN(n2862), .B(n2863), .A(n2864), .S(n2867), .CO(n2845)
);
NOR4X1TS U3807 ( .A(n2868), .B(n2867), .C(n2866), .D(n2865), .Y(n2869) );
INVX2TS U3808 ( .A(n2874), .Y(n2884) );
NOR2X4TS U3809 ( .A(n2885), .B(n2884), .Y(n2958) );
AOI22X1TS U3810 ( .A0(n3702), .A1(FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n951), .Y(n2930) );
NOR2X4TS U3811 ( .A(n2874), .B(n2885), .Y(n2924) );
AOI222X1TS U3812 ( .A0(n2901), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(n3702),
.B1(FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.C1(n950), .Y(n2916) );
AOI22X1TS U3813 ( .A0(n3702), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n2924),
.B1(n2928), .Y(n2875) );
NOR2X1TS U3814 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n3606), .Y(n2881) );
NAND2X1TS U3815 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n3536), .Y(n3241) );
AOI222X4TS U3816 ( .A0(n3239), .A1(n3536), .B0(n3239), .B1(n3596), .C0(n3536), .C1(n3596), .Y(n3030) );
AOI22X1TS U3817 ( .A0(n3252), .A1(n3244), .B0(n3030), .B1(n3703), .Y(n2880)
);
OAI31X1TS U3818 ( .A0(n2881), .A1(n2880), .A2(n3245), .B0(n2879), .Y(
FPADDSUB_Raw_mant_SGF[22]) );
AOI22X1TS U3819 ( .A0(n951), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n2901), .Y(n2882) );
BUFX3TS U3820 ( .A(n2901), .Y(n3482) );
INVX4TS U3821 ( .A(n2883), .Y(n3344) );
AOI222X4TS U3822 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n951), .C0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .C1(n3344), .Y(n3277) );
AOI222X4TS U3823 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n951), .C0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .C1(n3344), .Y(n3278) );
OAI22X1TS U3824 ( .A0(n3277), .A1(n3281), .B0(n3278), .B1(n948), .Y(n2887)
);
AOI21X1TS U3825 ( .A0(n949), .A1(n2957), .B0(n2887), .Y(n2888) );
AOI222X4TS U3826 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n3702), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(
n950), .Y(n2950) );
AOI22X1TS U3827 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n3702), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n2901), .Y(n2889) );
OAI21X2TS U3828 ( .A0(n3567), .A1(n2987), .B0(n2889), .Y(n2952) );
AOI222X4TS U3829 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(n3702), .B1(FPADDSUB_Raw_mant_NRM_SWR[8]), .C0(FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(
n950), .Y(n2937) );
AOI222X4TS U3830 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[14]), .B0(n3702), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(
n950), .Y(n2942) );
OAI22X1TS U3831 ( .A0(n2937), .A1(n946), .B0(n2942), .B1(n3281), .Y(n2890)
);
AOI21X1TS U3832 ( .A0(n949), .A1(n2952), .B0(n2890), .Y(n2891) );
AOI222X4TS U3833 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n951), .C0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .C1(n3344), .Y(n2938) );
AOI22X1TS U3834 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n3702), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n2901), .Y(n2892) );
OAI21X2TS U3835 ( .A0(n3568), .A1(n2987), .B0(n2892), .Y(n2940) );
AOI222X4TS U3836 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n951), .C0(n977), .C1(n3344), .Y(
n2955) );
AOI222X4TS U3837 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[18]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n951), .C0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .C1(n3344), .Y(n2960) );
OAI22X1TS U3838 ( .A0(n2955), .A1(n946), .B0(n2960), .B1(n3281), .Y(n2893)
);
AOI21X1TS U3839 ( .A0(n949), .A1(n2940), .B0(n2893), .Y(n2894) );
AOI222X4TS U3840 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n951), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n3344), .Y(n2932) );
AOI22X1TS U3841 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n3702), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n2901), .Y(n2895) );
AOI222X4TS U3842 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n3344), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(
n950), .Y(n2949) );
AOI222X4TS U3843 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n951), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n3344), .Y(n2954) );
OAI22X1TS U3844 ( .A0(n2949), .A1(n946), .B0(n2954), .B1(n3281), .Y(n2896)
);
AOI21X1TS U3845 ( .A0(n949), .A1(n2934), .B0(n2896), .Y(n2897) );
AOI222X4TS U3846 ( .A0(n2901), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(n3344),
.B1(FPADDSUB_Raw_mant_NRM_SWR[18]), .C0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.C1(n950), .Y(n2944) );
AOI22X1TS U3847 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n3702), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n2901), .Y(n2898) );
OAI21X2TS U3848 ( .A0(n3555), .A1(n2987), .B0(n2898), .Y(n2946) );
AOI222X4TS U3849 ( .A0(n2901), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n951), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n3344), .Y(n2931) );
AOI222X4TS U3850 ( .A0(n3482), .A1(FPADDSUB_DmP_mant_SHT1_SW[6]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n951), .C0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n3344), .Y(n2936) );
OAI22X1TS U3851 ( .A0(n2931), .A1(n946), .B0(n2936), .B1(n3281), .Y(n2899)
);
AOI21X1TS U3852 ( .A0(n949), .A1(n2946), .B0(n2899), .Y(n2900) );
AOI222X4TS U3853 ( .A0(n2901), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(n3344),
.B1(FPADDSUB_Raw_mant_NRM_SWR[20]), .C0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C1(n950), .Y(n2943) );
OAI22X1TS U3854 ( .A0(n2943), .A1(n946), .B0(n2948), .B1(n3281), .Y(n2902)
);
AOI21X1TS U3855 ( .A0(n2886), .A1(n2928), .B0(n2902), .Y(n2903) );
OAI22X1TS U3856 ( .A0(n3277), .A1(n946), .B0(n3278), .B1(n3281), .Y(n2904)
);
AOI21X1TS U3857 ( .A0(n2886), .A1(n2957), .B0(n2904), .Y(n2905) );
OAI22X1TS U3858 ( .A0(n2960), .A1(n945), .B0(n2938), .B1(n3281), .Y(n2906)
);
AOI21X1TS U3859 ( .A0(n2886), .A1(n2940), .B0(n2906), .Y(n2907) );
OAI22X1TS U3860 ( .A0(n2936), .A1(n945), .B0(n2944), .B1(n3281), .Y(n2908)
);
AOI21X1TS U3861 ( .A0(n2886), .A1(n2946), .B0(n2908), .Y(n2909) );
OAI22X1TS U3862 ( .A0(n2942), .A1(n945), .B0(n2950), .B1(n3281), .Y(n2910)
);
AOI21X1TS U3863 ( .A0(n2886), .A1(n2952), .B0(n2910), .Y(n2911) );
OAI22X1TS U3864 ( .A0(n2954), .A1(n945), .B0(n2932), .B1(n3281), .Y(n2912)
);
AOI21X1TS U3865 ( .A0(n2886), .A1(n2934), .B0(n2912), .Y(n2913) );
OAI22X1TS U3866 ( .A0(n2943), .A1(n3281), .B0(n2948), .B1(n948), .Y(n2914)
);
AOI21X1TS U3867 ( .A0(n2924), .A1(n2946), .B0(n2914), .Y(n2915) );
OAI22X1TS U3868 ( .A0(n2955), .A1(n2873), .B0(n2960), .B1(n948), .Y(n2917)
);
AOI21X1TS U3869 ( .A0(n2924), .A1(n2957), .B0(n2917), .Y(n2918) );
OAI22X1TS U3870 ( .A0(n2937), .A1(n2873), .B0(n2942), .B1(n947), .Y(n2919)
);
AOI21X1TS U3871 ( .A0(n2924), .A1(n2940), .B0(n2919), .Y(n2920) );
OAI22X1TS U3872 ( .A0(n2949), .A1(n2873), .B0(n2954), .B1(n947), .Y(n2921)
);
AOI21X1TS U3873 ( .A0(n2924), .A1(n2952), .B0(n2921), .Y(n2922) );
OAI22X1TS U3874 ( .A0(n2931), .A1(n2873), .B0(n2936), .B1(n948), .Y(n2923)
);
AOI21X1TS U3875 ( .A0(n2924), .A1(n2934), .B0(n2923), .Y(n2925) );
OAI22X1TS U3876 ( .A0(n2948), .A1(n946), .B0(n2926), .B1(n948), .Y(n2927) );
AOI21X1TS U3877 ( .A0(n2958), .A1(n2928), .B0(n2927), .Y(n2929) );
OAI22X1TS U3878 ( .A0(n2932), .A1(n945), .B0(n2931), .B1(n947), .Y(n2933) );
AOI21X1TS U3879 ( .A0(n2958), .A1(n2934), .B0(n2933), .Y(n2935) );
OAI22X1TS U3880 ( .A0(n2938), .A1(n945), .B0(n2937), .B1(n947), .Y(n2939) );
AOI21X1TS U3881 ( .A0(n2958), .A1(n2940), .B0(n2939), .Y(n2941) );
OAI22X1TS U3882 ( .A0(n2944), .A1(n945), .B0(n2943), .B1(n947), .Y(n2945) );
AOI21X1TS U3883 ( .A0(n2958), .A1(n2946), .B0(n2945), .Y(n2947) );
OAI22X1TS U3884 ( .A0(n2950), .A1(n945), .B0(n2949), .B1(n947), .Y(n2951) );
AOI21X1TS U3885 ( .A0(n2958), .A1(n2952), .B0(n2951), .Y(n2953) );
OAI22X1TS U3886 ( .A0(n3278), .A1(n946), .B0(n2955), .B1(n948), .Y(n2956) );
AOI21X1TS U3887 ( .A0(n2958), .A1(n2957), .B0(n2956), .Y(n2959) );
OAI22X1TS U3888 ( .A0(n2964), .A1(n2963), .B0(n2962), .B1(n2976), .Y(n2965)
);
AOI21X1TS U3889 ( .A0(n2966), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n2965),
.Y(n2967) );
OAI211X1TS U3890 ( .A0(n2969), .A1(n3611), .B0(n2968), .C0(n2967), .Y(
FPADDSUB_LZD_raw_out_EWR[2]) );
NOR3X1TS U3891 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(n2986), .C(n3561), .Y(
n2982) );
AOI211X1TS U3892 ( .A0(n2973), .A1(n2972), .B0(n2971), .C0(n2982), .Y(n2975)
);
OAI211X1TS U3893 ( .A0(n2977), .A1(n2976), .B0(n2975), .C0(n2974), .Y(
FPADDSUB_LZD_raw_out_EWR[3]) );
OAI31X1TS U3894 ( .A0(n2980), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n2979),
.B0(n2978), .Y(n2981) );
AOI211X1TS U3895 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n2983), .B0(n2982),
.C0(n2981), .Y(n2984) );
OAI211X1TS U3896 ( .A0(n3646), .A1(n2986), .B0(n2985), .C0(n2984), .Y(
FPADDSUB_LZD_raw_out_EWR[4]) );
NOR3XLTS U3897 ( .A(FPSENCOS_cont_var_out[1]), .B(n3522), .C(n3602), .Y(
FPSENCOS_enab_d_ff4_Yn) );
NOR3XLTS U3898 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n3602), .Y(FPSENCOS_enab_d_ff4_Xn) );
OAI21XLTS U3899 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n911), .B0(n2987),
.Y(n810) );
INVX2TS U3900 ( .A(n3308), .Y(n3306) );
NOR2X1TS U3901 ( .A(enab_cont_iter), .B(n3306), .Y(n3302) );
NAND2X1TS U3902 ( .A(n3302), .B(n3602), .Y(n3481) );
INVX2TS U3903 ( .A(n3481), .Y(n3480) );
XNOR2X1TS U3904 ( .A(DP_OP_234J312_129_4955_n1), .B(n2989), .Y(
FPMULT_Exp_module_Overflow_A) );
NOR2BX1TS U3905 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2990) );
XOR2X1TS U3906 ( .A(n911), .B(n2990), .Y(DP_OP_26J312_126_1325_n16) );
NOR2BX1TS U3907 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2991) );
XOR2X1TS U3908 ( .A(n911), .B(n2991), .Y(DP_OP_26J312_126_1325_n17) );
OR2X1TS U3909 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2992) );
XOR2X1TS U3910 ( .A(n911), .B(n2992), .Y(DP_OP_26J312_126_1325_n18) );
NOR2X1TS U3911 ( .A(n107), .B(FPMULT_FSM_adder_round_norm_load), .Y(n2994)
);
NAND2X1TS U3912 ( .A(n2993), .B(FPMULT_P_Sgf[47]), .Y(n2995) );
OAI2BB1X1TS U3913 ( .A0N(FPMULT_FSM_selector_B[1]), .A1N(n2994), .B0(n2995),
.Y(n829) );
OAI2BB1X1TS U3914 ( .A0N(FPMULT_FSM_selector_B[0]), .A1N(n2995), .B0(n2994),
.Y(n830) );
NOR2BX1TS U3915 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n3749), .Y(
FPADDSUB_formatted_number_W[30]) );
AOI2BB1XLTS U3916 ( .A0N(n3748), .A1N(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
n3749), .Y(FPADDSUB_formatted_number_W[31]) );
AOI21X1TS U3917 ( .A0(n2997), .A1(n2996), .B0(
FPMULT_Adder_M_result_A_adder[24]), .Y(
FPMULT_Adder_M_result_A_adder[23]) );
OA21XLTS U3918 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n2998), .B0(
n2997), .Y(FPMULT_Adder_M_result_A_adder[22]) );
AOI21X1TS U3919 ( .A0(n2999), .A1(n3000), .B0(n2998), .Y(
FPMULT_Adder_M_result_A_adder[21]) );
OA21XLTS U3920 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n3001), .B0(
n3000), .Y(FPMULT_Adder_M_result_A_adder[20]) );
AOI21X1TS U3921 ( .A0(n3002), .A1(n3003), .B0(n3001), .Y(
FPMULT_Adder_M_result_A_adder[19]) );
OA21XLTS U3922 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n3004), .B0(
n3003), .Y(FPMULT_Adder_M_result_A_adder[18]) );
AOI21X1TS U3923 ( .A0(n3005), .A1(n3006), .B0(n3004), .Y(
FPMULT_Adder_M_result_A_adder[17]) );
OA21XLTS U3924 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n3007), .B0(
n3006), .Y(FPMULT_Adder_M_result_A_adder[16]) );
AOI21X1TS U3925 ( .A0(n3008), .A1(n3009), .B0(n3007), .Y(
FPMULT_Adder_M_result_A_adder[15]) );
OA21XLTS U3926 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n3010), .B0(
n3009), .Y(FPMULT_Adder_M_result_A_adder[14]) );
AOI21X1TS U3927 ( .A0(n3011), .A1(n3012), .B0(n3010), .Y(
FPMULT_Adder_M_result_A_adder[13]) );
OA21XLTS U3928 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n3013), .B0(
n3012), .Y(FPMULT_Adder_M_result_A_adder[12]) );
AOI21X1TS U3929 ( .A0(n3014), .A1(n3015), .B0(n3013), .Y(
FPMULT_Adder_M_result_A_adder[11]) );
OA21XLTS U3930 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n3016), .B0(
n3015), .Y(FPMULT_Adder_M_result_A_adder[10]) );
AOI21X1TS U3931 ( .A0(n3017), .A1(n3018), .B0(n3016), .Y(
FPMULT_Adder_M_result_A_adder[9]) );
OA21XLTS U3932 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n3019), .B0(n3018), .Y(FPMULT_Adder_M_result_A_adder[8]) );
AOI21X1TS U3933 ( .A0(n3020), .A1(n3021), .B0(n3019), .Y(
FPMULT_Adder_M_result_A_adder[7]) );
OA21XLTS U3934 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n3022), .B0(n3021), .Y(FPMULT_Adder_M_result_A_adder[6]) );
AOI21X1TS U3935 ( .A0(n3027), .A1(n3023), .B0(n3022), .Y(
FPMULT_Adder_M_result_A_adder[5]) );
AOI21X1TS U3936 ( .A0(n3025), .A1(n3024), .B0(n3028), .Y(
FPMULT_Adder_M_result_A_adder[3]) );
AO21XLTS U3937 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n3026), .B0(n3025), .Y(FPMULT_Adder_M_result_A_adder[2]) );
AO21XLTS U3938 ( .A0(n3028), .A1(FPMULT_Sgf_normalized_result[4]), .B0(n3027), .Y(FPMULT_Adder_M_result_A_adder[4]) );
XOR2XLTS U3939 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(FPADDSUB_DmP_EXP_EWSW[27]), .Y(n3029) );
XOR2XLTS U3940 ( .A(intadd_1050_n1), .B(n3029), .Y(
FPADDSUB_Shift_amount_EXP_EW[4]) );
AOI222X4TS U3941 ( .A0(n3246), .A1(n3539), .B0(n3246), .B1(n3607), .C0(n3539), .C1(n3607), .Y(n3251) );
AOI21X1TS U3942 ( .A0(n3257), .A1(n3262), .B0(n910), .Y(n3750) );
BUFX4TS U3943 ( .A(n3417), .Y(n3387) );
NOR2BX1TS U3944 ( .AN(operation[0]), .B(n3387), .Y(n3755) );
AOI2BB2XLTS U3945 ( .B0(FPSENCOS_cont_var_out[0]), .B1(
FPSENCOS_d_ff3_sign_out), .A0N(FPSENCOS_d_ff3_sign_out), .A1N(
FPSENCOS_cont_var_out[0]), .Y(n3031) );
AOI222X1TS U3946 ( .A0(n2765), .A1(Data_2[31]), .B0(n3357), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .C0(FPSENCOS_d_ff3_sh_y_out[31]), .C1(
n3392), .Y(n3032) );
INVX2TS U3947 ( .A(n3032), .Y(n3033) );
XNOR2X1TS U3948 ( .A(n3034), .B(n3033), .Y(n3653) );
NOR2X1TS U3949 ( .A(n3635), .B(FPADDSUB_intDX_EWSW[25]), .Y(n3093) );
AOI22X1TS U3950 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n3635), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n3035), .Y(n3039) );
OAI21X1TS U3951 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n3639), .B0(n3036), .Y(
n3094) );
NOR2X1TS U3952 ( .A(n3660), .B(FPADDSUB_intDX_EWSW[30]), .Y(n3042) );
NOR2X1TS U3953 ( .A(n3659), .B(FPADDSUB_intDX_EWSW[29]), .Y(n3040) );
AOI211X1TS U3954 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n3578), .B0(n3042),
.C0(n3040), .Y(n3092) );
NOR3X1TS U3955 ( .A(n3578), .B(n3040), .C(FPADDSUB_intDY_EWSW[28]), .Y(n3041) );
AOI2BB2X1TS U3956 ( .B0(n3044), .B1(n3092), .A0N(n3043), .A1N(n3042), .Y(
n3098) );
NOR2X1TS U3957 ( .A(n3634), .B(FPADDSUB_intDX_EWSW[17]), .Y(n3080) );
NOR2X1TS U3958 ( .A(n3632), .B(FPADDSUB_intDX_EWSW[11]), .Y(n3059) );
AOI21X1TS U3959 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3583), .B0(n3059), .Y(
n3064) );
OAI2BB1X1TS U3960 ( .A0N(n3603), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n3045) );
OAI22X1TS U3961 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3045), .B0(n3603), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n3056) );
OAI2BB1X1TS U3962 ( .A0N(n3530), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n3046) );
OAI22X1TS U3963 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3046), .B0(n3530), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n3055) );
OAI21XLTS U3964 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n3638), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n3047) );
OAI2BB2XLTS U3965 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n3047), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n3638), .Y(n3049) );
NAND2BXLTS U3966 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n3048) );
OAI211XLTS U3967 ( .A0(n3640), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n3049), .C0(
n3048), .Y(n3052) );
OAI21XLTS U3968 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n3640), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n3050) );
AOI2BB2XLTS U3969 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n3640), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n3050), .Y(n3051) );
AOI222X1TS U3970 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3534), .B0(n3052), .B1(
n3051), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n3603), .Y(n3054) );
AOI22X1TS U3971 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3530), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n3590), .Y(n3053) );
OAI32X1TS U3972 ( .A0(n3056), .A1(n3055), .A2(n3054), .B0(n3053), .B1(n3055),
.Y(n3074) );
OA22X1TS U3973 ( .A0(n3541), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n3633), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n3071) );
OAI21XLTS U3974 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n3621), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n3058) );
OAI2BB2XLTS U3975 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n3058), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n3621), .Y(n3070) );
AOI22X1TS U3976 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n3632), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n3060), .Y(n3066) );
NAND2BXLTS U3977 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n3063) );
AOI21X1TS U3978 ( .A0(n3063), .A1(n3062), .B0(n3073), .Y(n3065) );
OAI2BB2XLTS U3979 ( .B0(n3066), .B1(n3073), .A0N(n3065), .A1N(n3064), .Y(
n3069) );
OAI2BB2XLTS U3980 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n3067), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n3633), .Y(n3068) );
AOI211X1TS U3981 ( .A0(n3071), .A1(n3070), .B0(n3069), .C0(n3068), .Y(n3072)
);
OAI31X1TS U3982 ( .A0(n3075), .A1(n3074), .A2(n3073), .B0(n3072), .Y(n3078)
);
OA22X1TS U3983 ( .A0(n3544), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n3642), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n3109) );
OAI21X1TS U3984 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n3637), .B0(n3082), .Y(
n3086) );
AOI211X1TS U3985 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3592), .B0(n3085),
.C0(n3086), .Y(n3077) );
OAI21XLTS U3986 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n3626), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n3079) );
OAI2BB2XLTS U3987 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n3079), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n3626), .Y(n3090) );
AOI22X1TS U3988 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n3634), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n3081), .Y(n3084) );
AOI32X1TS U3989 ( .A0(n3637), .A1(n3082), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n3543), .Y(n3083) );
OAI32X1TS U3990 ( .A0(n3086), .A1(n3085), .A2(n3084), .B0(n3083), .B1(n3085),
.Y(n3089) );
OAI2BB2XLTS U3991 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n3087), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n3642), .Y(n3088) );
AOI211X1TS U3992 ( .A0(n3109), .A1(n3090), .B0(n3089), .C0(n3088), .Y(n3096)
);
NAND4BBX1TS U3993 ( .AN(n3094), .BN(n3093), .C(n3092), .D(n3091), .Y(n3095)
);
AOI32X1TS U3994 ( .A0(n3098), .A1(n3097), .A2(n3096), .B0(n3095), .B1(n3098),
.Y(n3099) );
NAND2X1TS U3995 ( .A(FPADDSUB_intDY_EWSW[18]), .B(n3593), .Y(n3100) );
AOI22X1TS U3996 ( .A0(n3597), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n3590), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n3101) );
OAI221XLTS U3997 ( .A0(n3597), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n3590),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n3101), .Y(n3106) );
AOI22X1TS U3998 ( .A0(n3587), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n3533), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n3102) );
AOI22X1TS U3999 ( .A0(n3531), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n3595), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n3103) );
OAI221XLTS U4000 ( .A0(n3531), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n3595),
.B1(FPADDSUB_intDY_EWSW[3]), .C0(n3103), .Y(n3104) );
NOR4X1TS U4001 ( .A(n3107), .B(n3106), .C(n3105), .D(n3104), .Y(n3134) );
AOI22X1TS U4002 ( .A0(n3603), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n3534), .B1(
FPADDSUB_intDY_EWSW[4]), .Y(n3108) );
OAI221XLTS U4003 ( .A0(n3540), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n3610),
.B1(FPADDSUB_intDY_EWSW[22]), .C0(n3109), .Y(n3114) );
AOI22X1TS U4004 ( .A0(n3588), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n3592), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n3110) );
AOI22X1TS U4005 ( .A0(n3532), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n3591), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n3111) );
OAI221XLTS U4006 ( .A0(n3532), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n3591),
.B1(FPADDSUB_intDY_EWSW[8]), .C0(n3111), .Y(n3112) );
NOR4X1TS U4007 ( .A(n3115), .B(n3114), .C(n3113), .D(n3112), .Y(n3133) );
NAND2X1TS U4008 ( .A(FPADDSUB_intDY_EWSW[20]), .B(n3594), .Y(n3116) );
AOI22X1TS U4009 ( .A0(n3589), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n3535), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n3117) );
OAI221XLTS U4010 ( .A0(n3589), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n3535),
.B1(FPADDSUB_intDY_EWSW[24]), .C0(n3117), .Y(n3130) );
OAI22X1TS U4011 ( .A0(n3585), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n3529), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n3118) );
AOI221X1TS U4012 ( .A0(n3585), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[27]), .B1(n3529), .C0(n3118), .Y(n3119) );
OAI22X1TS U4013 ( .A0(n3584), .A1(FPADDSUB_intDX_EWSW[12]), .B0(n3527), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n3120) );
AOI221X1TS U4014 ( .A0(n3584), .A1(FPADDSUB_intDX_EWSW[12]), .B0(
FPADDSUB_intDY_EWSW[2]), .B1(n3527), .C0(n3120), .Y(n3127) );
OAI22X1TS U4015 ( .A0(n3530), .A1(FPADDSUB_intDY_EWSW[7]), .B0(n3528), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n3121) );
AOI221X1TS U4016 ( .A0(n3530), .A1(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDY_EWSW[9]), .B1(n3528), .C0(n3121), .Y(n3126) );
OAI22X1TS U4017 ( .A0(n3583), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n3582), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n3122) );
AOI221X1TS U4018 ( .A0(n3583), .A1(FPADDSUB_intDY_EWSW[10]), .B0(
FPADDSUB_intDY_EWSW[11]), .B1(n3582), .C0(n3122), .Y(n3125) );
OAI22X1TS U4019 ( .A0(n3586), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n3525), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n3123) );
AOI221X1TS U4020 ( .A0(n3586), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[13]), .B1(n3525), .C0(n3123), .Y(n3124) );
NAND4XLTS U4021 ( .A(n3127), .B(n3126), .C(n3125), .D(n3124), .Y(n3128) );
NOR4X1TS U4022 ( .A(n3131), .B(n3130), .C(n3129), .D(n3128), .Y(n3132) );
INVX4TS U4023 ( .A(n3268), .Y(n3276) );
AOI31XLTS U4024 ( .A0(n3134), .A1(n3133), .A2(n3132), .B0(n3276), .Y(n3135)
);
AOI2BB2XLTS U4025 ( .B0(n3271), .B1(n3746), .A0N(FPADDSUB_intDX_EWSW[31]),
.A1N(n3135), .Y(n3747) );
OAI21X2TS U4028 ( .A0(n3137), .A1(FPMULT_FSM_add_overflow_flag), .B0(n3139),
.Y(n3144) );
AOI22X1TS U4029 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n3604), .Y(n3136) );
AOI22X1TS U4030 ( .A0(n2573), .A1(n3138), .B0(n3144), .B1(n3136), .Y(n3780)
);
AOI32X1TS U4031 ( .A0(n3139), .A1(n2573), .A2(n3628), .B0(n3138), .B1(n3137),
.Y(n3142) );
AOI22X1TS U4032 ( .A0(n955), .A1(FPMULT_Add_result[22]), .B0(n957), .B1(
FPMULT_Add_result[23]), .Y(n3147) );
AOI22X1TS U4033 ( .A0(n960), .A1(FPMULT_P_Sgf[45]), .B0(n962), .B1(
FPMULT_P_Sgf[46]), .Y(n3146) );
NAND2X1TS U4034 ( .A(n3147), .B(n3146), .Y(n3779) );
AOI22X1TS U4035 ( .A0(n955), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Add_result[22]), .B1(n957), .Y(n3149) );
AOI22X1TS U4036 ( .A0(n959), .A1(FPMULT_P_Sgf[44]), .B0(FPMULT_P_Sgf[45]),
.B1(n961), .Y(n3148) );
NAND2X1TS U4037 ( .A(n3149), .B(n3148), .Y(n3778) );
AOI22X1TS U4038 ( .A0(n956), .A1(FPMULT_Add_result[20]), .B0(n958), .B1(
FPMULT_Add_result[21]), .Y(n3151) );
AOI22X1TS U4039 ( .A0(n960), .A1(FPMULT_P_Sgf[43]), .B0(n962), .B1(
FPMULT_P_Sgf[44]), .Y(n3150) );
NAND2X1TS U4040 ( .A(n3151), .B(n3150), .Y(n3777) );
AOI22X1TS U4041 ( .A0(n955), .A1(FPMULT_Add_result[19]), .B0(n957), .B1(
FPMULT_Add_result[20]), .Y(n3153) );
AOI22X1TS U4042 ( .A0(n959), .A1(FPMULT_P_Sgf[42]), .B0(n961), .B1(
FPMULT_P_Sgf[43]), .Y(n3152) );
NAND2X1TS U4043 ( .A(n3153), .B(n3152), .Y(n3776) );
AOI22X1TS U4044 ( .A0(n956), .A1(FPMULT_Add_result[18]), .B0(n958), .B1(
FPMULT_Add_result[19]), .Y(n3155) );
AOI22X1TS U4045 ( .A0(n960), .A1(FPMULT_P_Sgf[41]), .B0(n962), .B1(n982),
.Y(n3154) );
NAND2X1TS U4046 ( .A(n3155), .B(n3154), .Y(n3775) );
AOI22X1TS U4047 ( .A0(n955), .A1(FPMULT_Add_result[17]), .B0(n957), .B1(
FPMULT_Add_result[18]), .Y(n3157) );
AOI22X1TS U4048 ( .A0(n959), .A1(FPMULT_P_Sgf[40]), .B0(n961), .B1(
FPMULT_P_Sgf[41]), .Y(n3156) );
NAND2X1TS U4049 ( .A(n3157), .B(n3156), .Y(n3774) );
AOI22X1TS U4050 ( .A0(n956), .A1(FPMULT_Add_result[16]), .B0(n958), .B1(
FPMULT_Add_result[17]), .Y(n3159) );
AOI22X1TS U4051 ( .A0(n960), .A1(FPMULT_P_Sgf[39]), .B0(n962), .B1(n984),
.Y(n3158) );
NAND2X1TS U4052 ( .A(n3159), .B(n3158), .Y(n3773) );
AOI22X1TS U4053 ( .A0(n955), .A1(FPMULT_Add_result[15]), .B0(n957), .B1(
FPMULT_Add_result[16]), .Y(n3161) );
AOI22X1TS U4054 ( .A0(n959), .A1(FPMULT_P_Sgf[38]), .B0(n961), .B1(
FPMULT_P_Sgf[39]), .Y(n3160) );
NAND2X1TS U4055 ( .A(n3161), .B(n3160), .Y(n3772) );
AOI22X1TS U4056 ( .A0(n956), .A1(FPMULT_Add_result[14]), .B0(n958), .B1(
FPMULT_Add_result[15]), .Y(n3163) );
AOI22X1TS U4057 ( .A0(n959), .A1(FPMULT_P_Sgf[37]), .B0(n961), .B1(
FPMULT_P_Sgf[38]), .Y(n3162) );
NAND2X1TS U4058 ( .A(n3163), .B(n3162), .Y(n3771) );
AOI22X1TS U4059 ( .A0(n955), .A1(FPMULT_Add_result[13]), .B0(n957), .B1(
FPMULT_Add_result[14]), .Y(n3165) );
AOI22X1TS U4060 ( .A0(n959), .A1(FPMULT_P_Sgf[36]), .B0(n961), .B1(
FPMULT_P_Sgf[37]), .Y(n3164) );
NAND2X1TS U4061 ( .A(n3165), .B(n3164), .Y(n3770) );
AOI22X1TS U4062 ( .A0(n956), .A1(FPMULT_Add_result[12]), .B0(n958), .B1(
FPMULT_Add_result[13]), .Y(n3167) );
AOI22X1TS U4063 ( .A0(n960), .A1(FPMULT_P_Sgf[35]), .B0(n962), .B1(
FPMULT_P_Sgf[36]), .Y(n3166) );
NAND2X1TS U4064 ( .A(n3167), .B(n3166), .Y(n3769) );
AOI22X1TS U4065 ( .A0(n955), .A1(FPMULT_Add_result[11]), .B0(n957), .B1(
FPMULT_Add_result[12]), .Y(n3169) );
AOI22X1TS U4066 ( .A0(n959), .A1(FPMULT_P_Sgf[34]), .B0(n961), .B1(
FPMULT_P_Sgf[35]), .Y(n3168) );
NAND2X1TS U4067 ( .A(n3169), .B(n3168), .Y(n3768) );
AOI22X1TS U4068 ( .A0(n956), .A1(FPMULT_Add_result[10]), .B0(n958), .B1(
FPMULT_Add_result[11]), .Y(n3171) );
AOI22X1TS U4069 ( .A0(n960), .A1(FPMULT_P_Sgf[33]), .B0(n962), .B1(
FPMULT_P_Sgf[34]), .Y(n3170) );
NAND2X1TS U4070 ( .A(n3171), .B(n3170), .Y(n3767) );
AOI22X1TS U4071 ( .A0(n955), .A1(FPMULT_Add_result[9]), .B0(n957), .B1(
FPMULT_Add_result[10]), .Y(n3173) );
AOI22X1TS U4072 ( .A0(n959), .A1(FPMULT_P_Sgf[32]), .B0(n961), .B1(
FPMULT_P_Sgf[33]), .Y(n3172) );
NAND2X1TS U4073 ( .A(n3173), .B(n3172), .Y(n3766) );
AOI22X1TS U4074 ( .A0(n956), .A1(FPMULT_Add_result[8]), .B0(n958), .B1(
FPMULT_Add_result[9]), .Y(n3175) );
AOI22X1TS U4075 ( .A0(n960), .A1(FPMULT_P_Sgf[31]), .B0(n962), .B1(
FPMULT_P_Sgf[32]), .Y(n3174) );
NAND2X1TS U4076 ( .A(n3175), .B(n3174), .Y(n3765) );
AOI22X1TS U4077 ( .A0(n955), .A1(FPMULT_Add_result[7]), .B0(n957), .B1(
FPMULT_Add_result[8]), .Y(n3177) );
AOI22X1TS U4078 ( .A0(n959), .A1(FPMULT_P_Sgf[30]), .B0(n961), .B1(
FPMULT_P_Sgf[31]), .Y(n3176) );
NAND2X1TS U4079 ( .A(n3177), .B(n3176), .Y(n3764) );
AOI22X1TS U4080 ( .A0(n956), .A1(FPMULT_Add_result[6]), .B0(n958), .B1(
FPMULT_Add_result[7]), .Y(n3179) );
AOI22X1TS U4081 ( .A0(n960), .A1(FPMULT_P_Sgf[29]), .B0(n962), .B1(
FPMULT_P_Sgf[30]), .Y(n3178) );
NAND2X1TS U4082 ( .A(n3179), .B(n3178), .Y(n3763) );
AOI22X1TS U4083 ( .A0(n955), .A1(FPMULT_Add_result[5]), .B0(n957), .B1(
FPMULT_Add_result[6]), .Y(n3181) );
AOI22X1TS U4084 ( .A0(n959), .A1(FPMULT_P_Sgf[28]), .B0(n961), .B1(
FPMULT_P_Sgf[29]), .Y(n3180) );
NAND2X1TS U4085 ( .A(n3181), .B(n3180), .Y(n3762) );
AOI22X1TS U4086 ( .A0(n956), .A1(FPMULT_Add_result[4]), .B0(n958), .B1(
FPMULT_Add_result[5]), .Y(n3183) );
AOI22X1TS U4087 ( .A0(n960), .A1(FPMULT_P_Sgf[27]), .B0(n962), .B1(
FPMULT_P_Sgf[28]), .Y(n3182) );
NAND2X1TS U4088 ( .A(n3183), .B(n3182), .Y(n3761) );
AOI22X1TS U4089 ( .A0(n955), .A1(FPMULT_Add_result[3]), .B0(n957), .B1(
FPMULT_Add_result[4]), .Y(n3185) );
AOI22X1TS U4090 ( .A0(n959), .A1(FPMULT_P_Sgf[26]), .B0(n961), .B1(
FPMULT_P_Sgf[27]), .Y(n3184) );
NAND2X1TS U4091 ( .A(n3185), .B(n3184), .Y(n3760) );
AOI22X1TS U4092 ( .A0(n956), .A1(FPMULT_Add_result[2]), .B0(n958), .B1(
FPMULT_Add_result[3]), .Y(n3187) );
AOI22X1TS U4093 ( .A0(n960), .A1(FPMULT_P_Sgf[25]), .B0(n962), .B1(
FPMULT_P_Sgf[26]), .Y(n3186) );
NAND2X1TS U4094 ( .A(n3187), .B(n3186), .Y(n3759) );
AOI22X1TS U4095 ( .A0(n956), .A1(FPMULT_Add_result[1]), .B0(n958), .B1(
FPMULT_Add_result[2]), .Y(n3189) );
AOI22X1TS U4096 ( .A0(n960), .A1(FPMULT_P_Sgf[24]), .B0(n962), .B1(
FPMULT_P_Sgf[25]), .Y(n3188) );
NAND2X1TS U4097 ( .A(n3189), .B(n3188), .Y(n3758) );
AOI22X1TS U4098 ( .A0(n956), .A1(FPMULT_Add_result[0]), .B0(n958), .B1(
FPMULT_Add_result[1]), .Y(n3191) );
AOI22X1TS U4099 ( .A0(n960), .A1(FPMULT_P_Sgf[23]), .B0(n962), .B1(
FPMULT_P_Sgf[24]), .Y(n3190) );
NAND2X1TS U4100 ( .A(n3191), .B(n3190), .Y(n3757) );
AOI22X1TS U4101 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n3192), .B1(n3605),
.Y(n3756) );
XNOR2X1TS U4102 ( .A(Data_2[31]), .B(Data_1[31]), .Y(n3654) );
INVX2TS U4103 ( .A(n3193), .Y(n3342) );
AOI2BB1XLTS U4104 ( .A0N(n3629), .A1N(underflow_flag_mult), .B0(n3342), .Y(
FPMULT_final_result_ieee_Module_Sign_S_mux) );
AOI32X1TS U4105 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3194), .A2(n3565),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n3194), .Y(
FPSENCOS_data_out_LUT[4]) );
OAI22X1TS U4106 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3423), .B0(
FPSENCOS_cont_iter_out[2]), .B1(n3424), .Y(FPSENCOS_data_out_LUT[25])
);
NOR4X1TS U4107 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n3201) );
NOR4X1TS U4108 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n3200) );
NOR4X1TS U4109 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n3198) );
NOR3XLTS U4110 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n3197) );
NOR4X1TS U4111 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n3196) );
NOR4X1TS U4112 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n3195) );
AND4X1TS U4113 ( .A(n3198), .B(n3197), .C(n3196), .D(n3195), .Y(n3199) );
NAND4XLTS U4114 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n3203) );
NAND4XLTS U4115 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n3202) );
NOR3X1TS U4116 ( .A(n3738), .B(n3203), .C(n3202), .Y(n3208) );
NOR4X1TS U4117 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[28]), .D(dataB[23]),
.Y(n3205) );
NOR3XLTS U4118 ( .A(dataB[26]), .B(dataB[29]), .C(dataB[25]), .Y(n3204) );
NAND4XLTS U4119 ( .A(n3208), .B(operation_reg[1]), .C(n3205), .D(n3204), .Y(
n3206) );
NOR3XLTS U4120 ( .A(operation_reg[0]), .B(dataB[31]), .C(n3206), .Y(n3207)
);
OAI211XLTS U4121 ( .A0(dataB[27]), .A1(n3207), .B0(n3737), .C0(n3736), .Y(
n3218) );
NOR4X1TS U4122 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[28]), .D(dataA[26]),
.Y(n3211) );
NOR4BX1TS U4123 ( .AN(operation_reg[1]), .B(dataA[31]), .C(dataA[24]), .D(
dataA[25]), .Y(n3210) );
NOR4X1TS U4124 ( .A(n3738), .B(dataA[30]), .C(operation_reg[0]), .D(
dataA[27]), .Y(n3209) );
NOR2BX1TS U4125 ( .AN(n3208), .B(operation_reg[1]), .Y(n3216) );
AOI31XLTS U4126 ( .A0(n3211), .A1(n3210), .A2(n3209), .B0(n3216), .Y(n3214)
);
NAND3XLTS U4127 ( .A(dataB[23]), .B(dataB[28]), .C(dataB[25]), .Y(n3213) );
NAND4XLTS U4128 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n3212) );
OAI31X1TS U4129 ( .A0(n3214), .A1(n3213), .A2(n3212), .B0(dataB[27]), .Y(
n3215) );
NAND4XLTS U4130 ( .A(n3741), .B(n3740), .C(n3739), .D(n3215), .Y(n3217) );
OAI2BB2XLTS U4131 ( .B0(n3218), .B1(n3217), .A0N(n3216), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NAND2X1TS U4132 ( .A(FPADDSUB_N59), .B(n910), .Y(n3219) );
XNOR2X1TS U4133 ( .A(n3219), .B(FPADDSUB_N60), .Y(FPADDSUB_Raw_mant_SGF[1])
);
OAI21XLTS U4134 ( .A0(FPADDSUB_DMP_SFG[0]), .A1(FPADDSUB_DmP_mant_SFG_SWR[2]), .B0(n3220), .Y(n3223) );
NAND2X1TS U4135 ( .A(n3221), .B(n910), .Y(n3222) );
XOR2XLTS U4136 ( .A(n3223), .B(n3222), .Y(FPADDSUB_Raw_mant_SGF[2]) );
AOI22X1TS U4137 ( .A0(n3252), .A1(n3225), .B0(n3224), .B1(n3703), .Y(n3228)
);
OAI21XLTS U4138 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n3520), .B0(n3226),
.Y(n3227) );
AOI22X1TS U4139 ( .A0(n3252), .A1(n3230), .B0(n3229), .B1(n3703), .Y(n3233)
);
OAI21XLTS U4140 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n3523), .B0(n3231),
.Y(n3232) );
AOI22X1TS U4141 ( .A0(n3252), .A1(n3235), .B0(n3234), .B1(n3703), .Y(n3238)
);
AOI22X1TS U4142 ( .A0(n3252), .A1(n3240), .B0(n3239), .B1(n3703), .Y(n3243)
);
AOI22X1TS U4143 ( .A0(n3252), .A1(n3249), .B0(n3246), .B1(n3703), .Y(n3248)
);
NAND2X1TS U4144 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n3539), .Y(n3250) );
NOR2X1TS U4145 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(n3613), .Y(n3259) );
AOI21X1TS U4146 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n3613), .B0(n3259),
.Y(n3254) );
AOI22X1TS U4147 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n3607), .B0(n3250), .B1(
n3249), .Y(n3255) );
AOI22X1TS U4148 ( .A0(n3252), .A1(n3255), .B0(n3251), .B1(n3703), .Y(n3253)
);
NAND2X1TS U4149 ( .A(FPSENCOS_d_ff1_operation_out), .B(n969), .Y(n3265) );
XOR2X1TS U4150 ( .A(n1036), .B(n3263), .Y(n3264) );
INVX2TS U4151 ( .A(n3264), .Y(n3296) );
BUFX4TS U4152 ( .A(n3296), .Y(n3294) );
AOI22X1TS U4153 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[31]), .B0(
FPSENCOS_d_ff_Xn[31]), .B1(n3294), .Y(n3267) );
XNOR2X1TS U4154 ( .A(n3267), .B(n3266), .Y(FPSENCOS_fmtted_Result_31_) );
AOI22X1TS U4155 ( .A0(n3276), .A1(n3641), .B0(n3533), .B1(n3271), .Y(
FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U4156 ( .A0(n3276), .A1(n3638), .B0(n3587), .B1(n3271), .Y(
FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U4157 ( .A0(n3276), .A1(n3622), .B0(n3527), .B1(n3271), .Y(
FPADDSUB_DmP_INIT_EWSW[2]) );
BUFX4TS U4158 ( .A(n3271), .Y(n3269) );
AOI22X1TS U4159 ( .A0(n3276), .A1(n3640), .B0(n3595), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[3]) );
AOI22X1TS U4160 ( .A0(n3276), .A1(n3620), .B0(n3534), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[4]) );
AOI22X1TS U4161 ( .A0(n3273), .A1(n3615), .B0(n3603), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[5]) );
AOI22X1TS U4162 ( .A0(n3276), .A1(n3618), .B0(n3590), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U4163 ( .A0(n3276), .A1(n3614), .B0(n3530), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U4164 ( .A0(n3275), .A1(n3636), .B0(n3591), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U4165 ( .A0(n3276), .A1(n3624), .B0(n3528), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U4166 ( .A0(n3099), .A1(n3617), .B0(n3583), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U4167 ( .A0(n3270), .A1(n3632), .B0(n3582), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U4168 ( .A0(n3276), .A1(n3584), .B0(n3616), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[12]) );
BUFX4TS U4169 ( .A(n3271), .Y(n3272) );
AOI22X1TS U4170 ( .A0(n3273), .A1(n3621), .B0(n3525), .B1(n3272), .Y(
FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U4171 ( .A0(n3270), .A1(n3541), .B0(n3608), .B1(n3272), .Y(
FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U4172 ( .A0(n3276), .A1(n3633), .B0(n3586), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[15]) );
AOI22X1TS U4173 ( .A0(n3275), .A1(n3619), .B0(n3592), .B1(n3268), .Y(
FPADDSUB_DmP_INIT_EWSW[16]) );
INVX4TS U4174 ( .A(n3268), .Y(n3273) );
AOI22X1TS U4175 ( .A0(n3273), .A1(n3634), .B0(n3588), .B1(n3272), .Y(
FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U4176 ( .A0(n3273), .A1(n3637), .B0(n3593), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U4177 ( .A0(n3273), .A1(n3543), .B0(n3585), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U4178 ( .A0(n3273), .A1(n3627), .B0(n3594), .B1(n3268), .Y(
FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U4179 ( .A0(n3273), .A1(n3626), .B0(n3532), .B1(n3269), .Y(
FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U4180 ( .A0(n3273), .A1(n3544), .B0(n3610), .B1(n3272), .Y(
FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U4181 ( .A0(n3273), .A1(n3642), .B0(n3540), .B1(n3271), .Y(
FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U4182 ( .A0(n3273), .A1(n3623), .B0(n3535), .B1(n3271), .Y(
FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U4183 ( .A0(n3273), .A1(n3635), .B0(n3589), .B1(n3268), .Y(
FPADDSUB_DmP_INIT_EWSW[25]) );
AOI22X1TS U4184 ( .A0(n3273), .A1(n3639), .B0(n3531), .B1(n3271), .Y(
FPADDSUB_DmP_INIT_EWSW[26]) );
AOI22X1TS U4185 ( .A0(n3273), .A1(n3625), .B0(n3529), .B1(n3271), .Y(
FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U4186 ( .A0(n3273), .A1(n3533), .B0(n3641), .B1(n3271), .Y(
FPADDSUB_DMP_INIT_EWSW[0]) );
INVX4TS U4187 ( .A(n3271), .Y(n3270) );
AOI22X1TS U4188 ( .A0(n3270), .A1(n3587), .B0(n3638), .B1(n3268), .Y(
FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U4189 ( .A0(n3270), .A1(n3527), .B0(n3622), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U4190 ( .A0(n3270), .A1(n3595), .B0(n3640), .B1(n3268), .Y(
FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U4191 ( .A0(n3270), .A1(n3534), .B0(n3620), .B1(n3269), .Y(
FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U4192 ( .A0(n3270), .A1(n3603), .B0(n3615), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U4193 ( .A0(n3270), .A1(n3590), .B0(n3618), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U4194 ( .A0(n3270), .A1(n3530), .B0(n3614), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U4195 ( .A0(n3270), .A1(n3591), .B0(n3636), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U4196 ( .A0(n3270), .A1(n3528), .B0(n3624), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U4197 ( .A0(n3270), .A1(n3583), .B0(n3617), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U4198 ( .A0(n3270), .A1(n3582), .B0(n3632), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U4199 ( .A0(n3270), .A1(n3616), .B0(n3584), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U4200 ( .A0(n3270), .A1(n3525), .B0(n3621), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[13]) );
INVX4TS U4201 ( .A(n3271), .Y(n3275) );
AOI22X1TS U4202 ( .A0(n3275), .A1(n3608), .B0(n3541), .B1(n3272), .Y(
FPADDSUB_DMP_INIT_EWSW[14]) );
BUFX3TS U4203 ( .A(n3268), .Y(n3274) );
AOI22X1TS U4204 ( .A0(n3275), .A1(n3586), .B0(n3633), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U4205 ( .A0(n3275), .A1(n3592), .B0(n3619), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U4206 ( .A0(n3275), .A1(n3588), .B0(n3634), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U4207 ( .A0(n3275), .A1(n3593), .B0(n3637), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U4208 ( .A0(n3273), .A1(n3585), .B0(n3543), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U4209 ( .A0(n3275), .A1(n3594), .B0(n3627), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U4210 ( .A0(n3275), .A1(n3532), .B0(n3626), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U4211 ( .A0(n3275), .A1(n3610), .B0(n3544), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U4212 ( .A0(n3275), .A1(n3540), .B0(n3642), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U4213 ( .A0(n3275), .A1(n3535), .B0(n3623), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U4214 ( .A0(n3275), .A1(n3589), .B0(n3635), .B1(n3271), .Y(
FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U4215 ( .A0(n3275), .A1(n3531), .B0(n3639), .B1(n3271), .Y(
FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U4216 ( .A0(n3275), .A1(n3529), .B0(n3625), .B1(n3274), .Y(
FPADDSUB_DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U4217 ( .B0(n3276), .B1(n3597), .A0N(n3276), .A1N(
FPADDSUB_intDX_EWSW[28]), .Y(FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U4218 ( .B0(n3276), .B1(n3659), .A0N(n3276), .A1N(
FPADDSUB_intDX_EWSW[29]), .Y(FPADDSUB_DMP_INIT_EWSW[29]) );
OAI22X1TS U4219 ( .A0(n3277), .A1(n3279), .B0(n3280), .B1(n948), .Y(
FPADDSUB_Data_array_SWR[24]) );
NAND2X1TS U4220 ( .A(n3300), .B(n3310), .Y(FPSENCOS_enab_d_ff5_data_out) );
CLKAND2X2TS U4221 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
FPADDSUB_formatted_number_W[2]) );
CLKAND2X2TS U4222 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
FPADDSUB_formatted_number_W[3]) );
CLKAND2X2TS U4223 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U4224 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
FPADDSUB_formatted_number_W[5]) );
CLKAND2X2TS U4225 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
FPADDSUB_formatted_number_W[16]) );
CLKAND2X2TS U4226 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
FPADDSUB_formatted_number_W[17]) );
CLKAND2X2TS U4227 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
FPADDSUB_formatted_number_W[18]) );
CLKAND2X2TS U4228 ( .A(n954), .B(FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
FPADDSUB_formatted_number_W[19]) );
NOR2BX1TS U4229 ( .AN(FPMULT_Sgf_normalized_result[2]), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]) );
NOR2BX1TS U4230 ( .AN(FPMULT_Sgf_normalized_result[4]), .B(n3282), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]) );
NOR2BX1TS U4231 ( .AN(FPMULT_Sgf_normalized_result[6]), .B(n3283), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]) );
NOR2BX1TS U4232 ( .AN(FPMULT_Sgf_normalized_result[8]), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]) );
NOR2BX1TS U4233 ( .AN(FPMULT_Sgf_normalized_result[10]), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]) );
NOR2BX1TS U4234 ( .AN(FPMULT_Sgf_normalized_result[12]), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]) );
NOR2BX1TS U4235 ( .AN(FPMULT_Sgf_normalized_result[14]), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]) );
NOR2BX1TS U4236 ( .AN(FPMULT_Sgf_normalized_result[16]), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]) );
NOR2BX1TS U4237 ( .AN(FPMULT_Sgf_normalized_result[18]), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]) );
NOR2BX1TS U4238 ( .AN(FPMULT_Sgf_normalized_result[20]), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]) );
NOR2BX1TS U4239 ( .AN(FPMULT_Sgf_normalized_result[22]), .B(n3284), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]) );
INVX4TS U4240 ( .A(n3287), .Y(n3285) );
NOR2BX1TS U4241 ( .AN(FPSENCOS_d_ff_Xn[0]), .B(n3285), .Y(
FPSENCOS_first_mux_X[0]) );
NOR2BX1TS U4242 ( .AN(FPSENCOS_d_ff_Xn[4]), .B(n3285), .Y(
FPSENCOS_first_mux_X[4]) );
NOR2BX1TS U4243 ( .AN(FPSENCOS_d_ff_Xn[8]), .B(n3285), .Y(
FPSENCOS_first_mux_X[8]) );
NOR2BX1TS U4244 ( .AN(FPSENCOS_d_ff_Xn[9]), .B(n3285), .Y(
FPSENCOS_first_mux_X[9]) );
NOR2BX1TS U4245 ( .AN(FPSENCOS_d_ff_Xn[11]), .B(n3285), .Y(
FPSENCOS_first_mux_X[11]) );
INVX4TS U4246 ( .A(n3287), .Y(n3293) );
NOR2BX1TS U4247 ( .AN(FPSENCOS_d_ff_Xn[15]), .B(n3293), .Y(
FPSENCOS_first_mux_X[15]) );
NOR2BX1TS U4248 ( .AN(FPSENCOS_d_ff_Xn[18]), .B(n3285), .Y(
FPSENCOS_first_mux_X[18]) );
NOR2BX1TS U4249 ( .AN(FPSENCOS_d_ff_Xn[21]), .B(n3293), .Y(
FPSENCOS_first_mux_X[21]) );
NOR2BX1TS U4250 ( .AN(FPSENCOS_d_ff_Xn[22]), .B(n3285), .Y(
FPSENCOS_first_mux_X[22]) );
NOR2BX1TS U4251 ( .AN(FPSENCOS_d_ff_Xn[23]), .B(n3285), .Y(
FPSENCOS_first_mux_X[23]) );
NOR2BX1TS U4252 ( .AN(FPSENCOS_d_ff_Xn[30]), .B(n3285), .Y(
FPSENCOS_first_mux_X[30]) );
NOR2BX1TS U4253 ( .AN(FPSENCOS_d_ff_Xn[31]), .B(n3285), .Y(
FPSENCOS_first_mux_X[31]) );
INVX4TS U4254 ( .A(n3290), .Y(n3292) );
NOR2BX1TS U4255 ( .AN(FPSENCOS_d_ff_Yn[0]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[0]) );
INVX4TS U4256 ( .A(n3289), .Y(n3286) );
NOR2BX1TS U4257 ( .AN(FPSENCOS_d_ff_Yn[1]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[1]) );
INVX4TS U4258 ( .A(n3289), .Y(n3291) );
NOR2BX1TS U4259 ( .AN(FPSENCOS_d_ff_Yn[2]), .B(n3291), .Y(
FPSENCOS_first_mux_Y[2]) );
NOR2BX1TS U4260 ( .AN(FPSENCOS_d_ff_Yn[3]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[3]) );
NOR2BX1TS U4261 ( .AN(FPSENCOS_d_ff_Yn[4]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[4]) );
NOR2BX1TS U4262 ( .AN(FPSENCOS_d_ff_Yn[5]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[5]) );
NOR2BX1TS U4263 ( .AN(FPSENCOS_d_ff_Yn[6]), .B(n3285), .Y(
FPSENCOS_first_mux_Y[6]) );
NOR2BX1TS U4264 ( .AN(FPSENCOS_d_ff_Yn[7]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[7]) );
NOR2BX1TS U4265 ( .AN(FPSENCOS_d_ff_Yn[8]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[8]) );
NOR2BX1TS U4266 ( .AN(FPSENCOS_d_ff_Yn[9]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[9]) );
NOR2BX1TS U4267 ( .AN(FPSENCOS_d_ff_Yn[10]), .B(n3285), .Y(
FPSENCOS_first_mux_Y[10]) );
NOR2BX1TS U4268 ( .AN(FPSENCOS_d_ff_Yn[11]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[11]) );
NOR2BX1TS U4269 ( .AN(FPSENCOS_d_ff_Yn[12]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[12]) );
NOR2BX1TS U4270 ( .AN(FPSENCOS_d_ff_Yn[13]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[13]) );
NOR2BX1TS U4271 ( .AN(FPSENCOS_d_ff_Yn[14]), .B(n3285), .Y(
FPSENCOS_first_mux_Y[14]) );
NOR2BX1TS U4272 ( .AN(FPSENCOS_d_ff_Yn[15]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[15]) );
NOR2BX1TS U4273 ( .AN(FPSENCOS_d_ff_Yn[16]), .B(n3291), .Y(
FPSENCOS_first_mux_Y[16]) );
NOR2BX1TS U4274 ( .AN(FPSENCOS_d_ff_Yn[17]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[17]) );
NOR2BX1TS U4275 ( .AN(FPSENCOS_d_ff_Yn[18]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[18]) );
NOR2BX1TS U4276 ( .AN(FPSENCOS_d_ff_Yn[19]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[19]) );
NOR2BX1TS U4277 ( .AN(FPSENCOS_d_ff_Yn[20]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[20]) );
NOR2BX1TS U4278 ( .AN(FPSENCOS_d_ff_Yn[21]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[21]) );
NOR2BX1TS U4279 ( .AN(FPSENCOS_d_ff_Yn[22]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[22]) );
NOR2BX1TS U4280 ( .AN(FPSENCOS_d_ff_Yn[23]), .B(n3285), .Y(
FPSENCOS_first_mux_Y[23]) );
NOR2BX1TS U4281 ( .AN(FPSENCOS_d_ff_Yn[24]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[24]) );
NOR2BX1TS U4282 ( .AN(FPSENCOS_d_ff_Yn[25]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[25]) );
NOR2BX1TS U4283 ( .AN(FPSENCOS_d_ff_Yn[26]), .B(n3285), .Y(
FPSENCOS_first_mux_Y[26]) );
NOR2BX1TS U4284 ( .AN(FPSENCOS_d_ff_Yn[27]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[27]) );
NOR2BX1TS U4285 ( .AN(FPSENCOS_d_ff_Yn[28]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[28]) );
NOR2BX1TS U4286 ( .AN(FPSENCOS_d_ff_Yn[29]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[29]) );
NOR2BX1TS U4287 ( .AN(FPSENCOS_d_ff_Yn[30]), .B(n3286), .Y(
FPSENCOS_first_mux_Y[30]) );
NOR2BX1TS U4288 ( .AN(FPSENCOS_d_ff_Yn[31]), .B(n3292), .Y(
FPSENCOS_first_mux_Y[31]) );
AO22XLTS U4289 ( .A0(n3288), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n3287), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(FPSENCOS_first_mux_Z[0]) );
AO22XLTS U4290 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(FPSENCOS_first_mux_Z[1]) );
AO22XLTS U4291 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(FPSENCOS_first_mux_Z[2]) );
AO22XLTS U4292 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(FPSENCOS_first_mux_Z[3]) );
AO22XLTS U4293 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(FPSENCOS_first_mux_Z[4]) );
AO22XLTS U4294 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(FPSENCOS_first_mux_Z[5]) );
AO22XLTS U4295 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(FPSENCOS_first_mux_Z[6]) );
AO22XLTS U4296 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(FPSENCOS_first_mux_Z[7]) );
AO22XLTS U4297 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(FPSENCOS_first_mux_Z[8]) );
AO22XLTS U4298 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(FPSENCOS_first_mux_Z[9]) );
AO22XLTS U4299 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(FPSENCOS_first_mux_Z[10]) );
AO22XLTS U4300 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n3287), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(FPSENCOS_first_mux_Z[11]) );
AO22XLTS U4301 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(FPSENCOS_first_mux_Z[12]) );
AO22XLTS U4302 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n3287), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(FPSENCOS_first_mux_Z[13]) );
AO22XLTS U4303 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n3287), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(FPSENCOS_first_mux_Z[14]) );
AO22XLTS U4304 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n3287), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(FPSENCOS_first_mux_Z[15]) );
AO22XLTS U4305 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n3287), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(FPSENCOS_first_mux_Z[16]) );
AO22XLTS U4306 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(FPSENCOS_first_mux_Z[17]) );
AO22XLTS U4307 ( .A0(n3292), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(FPSENCOS_first_mux_Z[18]) );
AO22XLTS U4308 ( .A0(n3292), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(FPSENCOS_first_mux_Z[19]) );
AO22XLTS U4309 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(FPSENCOS_first_mux_Z[20]) );
AO22XLTS U4310 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(FPSENCOS_first_mux_Z[21]) );
AO22XLTS U4311 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(FPSENCOS_first_mux_Z[22]) );
AO22XLTS U4312 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(FPSENCOS_first_mux_Z[23]) );
AO22XLTS U4313 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(FPSENCOS_first_mux_Z[24]) );
AO22XLTS U4314 ( .A0(n3292), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(FPSENCOS_first_mux_Z[25]) );
AO22XLTS U4315 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(FPSENCOS_first_mux_Z[26]) );
AO22XLTS U4316 ( .A0(n3292), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n3290), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(FPSENCOS_first_mux_Z[27]) );
AO22XLTS U4317 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(FPSENCOS_first_mux_Z[28]) );
AO22XLTS U4318 ( .A0(n3291), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(FPSENCOS_first_mux_Z[29]) );
AO22XLTS U4319 ( .A0(n3292), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n3289), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(FPSENCOS_first_mux_Z[30]) );
AO22XLTS U4320 ( .A0(n3293), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n3287), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(FPSENCOS_first_mux_Z[31]) );
BUFX3TS U4321 ( .A(n3294), .Y(n3298) );
AO22XLTS U4322 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[0]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(FPSENCOS_mux_sal[0]) );
AO22XLTS U4323 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[1]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(FPSENCOS_mux_sal[1]) );
AO22XLTS U4324 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[2]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(FPSENCOS_mux_sal[2]) );
AO22XLTS U4325 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[3]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(FPSENCOS_mux_sal[3]) );
AO22XLTS U4326 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[4]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(FPSENCOS_mux_sal[4]) );
AO22XLTS U4327 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[5]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(FPSENCOS_mux_sal[5]) );
AO22XLTS U4328 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[6]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(FPSENCOS_mux_sal[6]) );
AO22XLTS U4329 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[7]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(FPSENCOS_mux_sal[7]) );
AO22XLTS U4330 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[8]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(FPSENCOS_mux_sal[8]) );
AO22XLTS U4331 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[9]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(FPSENCOS_mux_sal[9]) );
AO22XLTS U4332 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[10]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(FPSENCOS_mux_sal[10]) );
AO22XLTS U4333 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[11]), .B0(n3296), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(FPSENCOS_mux_sal[11]) );
AO22XLTS U4334 ( .A0(n3295), .A1(FPSENCOS_d_ff_Yn[12]), .B0(n3296), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(FPSENCOS_mux_sal[12]) );
AO22XLTS U4335 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[13]), .B0(n3296), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(FPSENCOS_mux_sal[13]) );
AO22XLTS U4336 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[14]), .B0(n3296), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(FPSENCOS_mux_sal[14]) );
AO22XLTS U4337 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[15]), .B0(n3296), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(FPSENCOS_mux_sal[15]) );
AO22XLTS U4338 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[16]), .B0(n3296), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(FPSENCOS_mux_sal[16]) );
AO22XLTS U4339 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[17]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(FPSENCOS_mux_sal[17]) );
AO22XLTS U4340 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[18]), .B0(n3294), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(FPSENCOS_mux_sal[18]) );
AO22XLTS U4341 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[19]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(FPSENCOS_mux_sal[19]) );
AO22XLTS U4342 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[20]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(FPSENCOS_mux_sal[20]) );
AO22XLTS U4343 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[21]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(FPSENCOS_mux_sal[21]) );
AO22XLTS U4344 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[22]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(FPSENCOS_mux_sal[22]) );
AO22XLTS U4345 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[23]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(FPSENCOS_mux_sal[23]) );
AO22XLTS U4346 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[24]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(FPSENCOS_mux_sal[24]) );
AO22XLTS U4347 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[25]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(FPSENCOS_mux_sal[25]) );
AO22XLTS U4348 ( .A0(n3297), .A1(FPSENCOS_d_ff_Yn[26]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(FPSENCOS_mux_sal[26]) );
INVX2TS U4349 ( .A(n3294), .Y(n3299) );
AO22XLTS U4350 ( .A0(n3299), .A1(FPSENCOS_d_ff_Yn[27]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(FPSENCOS_mux_sal[27]) );
AO22XLTS U4351 ( .A0(n3299), .A1(FPSENCOS_d_ff_Yn[28]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(FPSENCOS_mux_sal[28]) );
AO22XLTS U4352 ( .A0(n3299), .A1(FPSENCOS_d_ff_Yn[29]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(FPSENCOS_mux_sal[29]) );
AO22XLTS U4353 ( .A0(n3299), .A1(FPSENCOS_d_ff_Yn[30]), .B0(n3298), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(FPSENCOS_mux_sal[30]) );
AOI21X1TS U4354 ( .A0(operation[1]), .A1(ack_operation), .B0(n3300), .Y(
n3311) );
NOR3XLTS U4355 ( .A(FPSENCOS_enab_RB3), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .C(FPSENCOS_enab_d_ff_RB1),
.Y(n3301) );
NAND3XLTS U4356 ( .A(n3302), .B(n3309), .C(n3301), .Y(n3303) );
NOR2BX1TS U4357 ( .AN(begin_operation), .B(n3417), .Y(n3305) );
OAI22X1TS U4358 ( .A0(n3311), .A1(n3303), .B0(n3305), .B1(n3304), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U4359 ( .AN(n3305), .B(n3304), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
AO21XLTS U4360 ( .A0(n3306), .A1(n3307), .B0(FPSENCOS_enab_RB3), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
OAI22X1TS U4361 ( .A0(FPSENCOS_enab_d_ff4_Zn), .A1(n3309), .B0(n3308), .B1(
n3307), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U4362 ( .AN(FPSENCOS_enab_d_ff4_Zn), .B(n3309), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
BUFX4TS U4363 ( .A(n3329), .Y(n3413) );
AOI22X1TS U4364 ( .A0(FPSENCOS_d_ff3_sh_x_out[0]), .A1(n3413), .B0(Data_2[0]), .B1(n952), .Y(n3313) );
AOI22X1TS U4365 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n3414),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n3312) );
NAND2X1TS U4366 ( .A(n3313), .B(n3312), .Y(add_subt_data2[0]) );
BUFX4TS U4367 ( .A(n3329), .Y(n3418) );
AOI22X1TS U4368 ( .A0(FPSENCOS_d_ff3_sh_x_out[1]), .A1(n3418), .B0(Data_2[1]), .B1(n952), .Y(n3315) );
AOI22X1TS U4369 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n3326),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n3314) );
NAND2X1TS U4370 ( .A(n3315), .B(n3314), .Y(add_subt_data2[1]) );
AOI22X1TS U4371 ( .A0(FPSENCOS_d_ff3_sh_x_out[2]), .A1(n3329), .B0(Data_2[2]), .B1(n952), .Y(n3317) );
AOI22X1TS U4372 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n3326),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n3316) );
NAND2X1TS U4373 ( .A(n3317), .B(n3316), .Y(add_subt_data2[2]) );
AOI22X1TS U4374 ( .A0(FPSENCOS_d_ff3_sh_x_out[4]), .A1(n3329), .B0(Data_2[4]), .B1(n952), .Y(n3319) );
AOI22X1TS U4375 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n3326),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n3318) );
NAND2X1TS U4376 ( .A(n3319), .B(n3318), .Y(add_subt_data2[4]) );
AOI22X1TS U4377 ( .A0(FPSENCOS_d_ff3_sh_x_out[6]), .A1(n3329), .B0(Data_2[6]), .B1(n952), .Y(n3321) );
AOI22X1TS U4378 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n3326),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n3320) );
NAND2X1TS U4379 ( .A(n3321), .B(n3320), .Y(add_subt_data2[6]) );
AOI22X1TS U4380 ( .A0(FPSENCOS_d_ff3_sh_x_out[8]), .A1(n3329), .B0(Data_2[8]), .B1(n952), .Y(n3323) );
AOI22X1TS U4381 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n3326),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n3322) );
NAND2X1TS U4382 ( .A(n3323), .B(n3322), .Y(add_subt_data2[8]) );
AOI22X1TS U4383 ( .A0(FPSENCOS_d_ff3_sh_x_out[9]), .A1(n3329), .B0(Data_2[9]), .B1(n2765), .Y(n3325) );
AOI22X1TS U4384 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n3326),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n3324) );
NAND2X1TS U4385 ( .A(n3325), .B(n3324), .Y(add_subt_data2[9]) );
AOI22X1TS U4386 ( .A0(FPSENCOS_d_ff3_sh_x_out[10]), .A1(n3329), .B0(
Data_2[10]), .B1(n2765), .Y(n3328) );
AOI22X1TS U4387 ( .A0(n3392), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n3326),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n3327) );
NAND2X1TS U4388 ( .A(n3328), .B(n3327), .Y(add_subt_data2[10]) );
AOI22X1TS U4389 ( .A0(FPSENCOS_d_ff3_sh_x_out[12]), .A1(n3329), .B0(
Data_2[12]), .B1(n2765), .Y(n3331) );
AOI22X1TS U4390 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n3419),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n3330) );
NAND2X1TS U4391 ( .A(n3331), .B(n3330), .Y(add_subt_data2[12]) );
AOI22X1TS U4392 ( .A0(FPSENCOS_d_ff3_sh_x_out[21]), .A1(n3418), .B0(
Data_2[21]), .B1(n3387), .Y(n3333) );
AOI22X1TS U4393 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n3419),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n3332) );
NAND2X1TS U4394 ( .A(n3333), .B(n3332), .Y(add_subt_data2[21]) );
AOI22X1TS U4395 ( .A0(FPSENCOS_d_ff3_sh_x_out[23]), .A1(n3418), .B0(
Data_2[23]), .B1(n952), .Y(n3335) );
AOI22X1TS U4396 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n3419),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n3334) );
NAND2X1TS U4397 ( .A(n3335), .B(n3334), .Y(add_subt_data2[23]) );
AOI22X1TS U4398 ( .A0(FPSENCOS_d_ff3_sh_x_out[24]), .A1(n3418), .B0(
Data_2[24]), .B1(n952), .Y(n3337) );
AOI22X1TS U4399 ( .A0(n3410), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n3419),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n3336) );
NAND2X1TS U4400 ( .A(n3337), .B(n3336), .Y(add_subt_data2[24]) );
AOI22X1TS U4401 ( .A0(FPSENCOS_d_ff3_sh_x_out[25]), .A1(n3418), .B0(
Data_2[25]), .B1(n3387), .Y(n3339) );
AOI22X1TS U4402 ( .A0(n3420), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n3419),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n3338) );
NAND2X1TS U4403 ( .A(n3339), .B(n3338), .Y(add_subt_data2[25]) );
AOI22X1TS U4404 ( .A0(FPSENCOS_d_ff3_sh_x_out[26]), .A1(n3418), .B0(
Data_2[26]), .B1(n3387), .Y(n3341) );
AOI22X1TS U4405 ( .A0(n3420), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n3419),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n3340) );
NAND2X1TS U4406 ( .A(n3341), .B(n3340), .Y(add_subt_data2[26]) );
INVX2TS U4407 ( .A(operation[2]), .Y(n3343) );
AOI22X1TS U4408 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n3418), .B0(Data_1[0]), .B1(
n3387), .Y(n3346) );
AOI22X1TS U4409 ( .A0(n3420), .A1(FPSENCOS_d_ff2_X[0]), .B0(n3419), .B1(
FPSENCOS_d_ff2_Z[0]), .Y(n3345) );
NAND2X1TS U4410 ( .A(n3346), .B(n3345), .Y(add_subt_data1[0]) );
AOI22X1TS U4411 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n3418), .B0(Data_1[1]), .B1(
n3387), .Y(n3348) );
AOI22X1TS U4412 ( .A0(n3420), .A1(FPSENCOS_d_ff2_X[1]), .B0(n3419), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n3347) );
NAND2X1TS U4413 ( .A(n3348), .B(n3347), .Y(add_subt_data1[1]) );
AOI22X1TS U4414 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n3418), .B0(Data_1[2]), .B1(
n3387), .Y(n3350) );
AOI22X1TS U4415 ( .A0(n3420), .A1(FPSENCOS_d_ff2_X[2]), .B0(n3419), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n3349) );
NAND2X1TS U4416 ( .A(n3350), .B(n3349), .Y(add_subt_data1[2]) );
AOI22X1TS U4417 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n3418), .B0(Data_1[3]), .B1(
n3387), .Y(n3352) );
AOI22X1TS U4418 ( .A0(n3420), .A1(FPSENCOS_d_ff2_X[3]), .B0(n3419), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n3351) );
NAND2X1TS U4419 ( .A(n3352), .B(n3351), .Y(add_subt_data1[3]) );
AOI22X1TS U4420 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n3418), .B0(Data_1[4]), .B1(
n3387), .Y(n3354) );
AOI22X1TS U4421 ( .A0(n3420), .A1(FPSENCOS_d_ff2_X[4]), .B0(n3419), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n3353) );
NAND2X1TS U4422 ( .A(n3354), .B(n3353), .Y(add_subt_data1[4]) );
AOI22X1TS U4423 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n3418), .B0(Data_1[5]), .B1(
n3387), .Y(n3356) );
AOI22X1TS U4424 ( .A0(n3420), .A1(FPSENCOS_d_ff2_X[5]), .B0(n3419), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n3355) );
NAND2X1TS U4425 ( .A(n3356), .B(n3355), .Y(add_subt_data1[5]) );
AOI22X1TS U4426 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n3357), .B0(Data_1[6]), .B1(
n3387), .Y(n3361) );
AOI22X1TS U4427 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[6]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n3360) );
NAND2X1TS U4428 ( .A(n3361), .B(n3360), .Y(add_subt_data1[6]) );
AOI22X1TS U4429 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n3357), .B0(Data_1[7]), .B1(
n3387), .Y(n3363) );
AOI22X1TS U4430 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[7]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n3362) );
NAND2X1TS U4431 ( .A(n3363), .B(n3362), .Y(add_subt_data1[7]) );
AOI22X1TS U4432 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n3418), .B0(Data_1[8]), .B1(
n3387), .Y(n3365) );
AOI22X1TS U4433 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[8]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n3364) );
NAND2X1TS U4434 ( .A(n3365), .B(n3364), .Y(add_subt_data1[8]) );
AOI22X1TS U4435 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n3413), .B0(Data_1[9]), .B1(
n952), .Y(n3367) );
AOI22X1TS U4436 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[9]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n3366) );
NAND2X1TS U4437 ( .A(n3367), .B(n3366), .Y(add_subt_data1[9]) );
AOI22X1TS U4438 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n3357), .B0(Data_1[10]),
.B1(n2765), .Y(n3369) );
AOI22X1TS U4439 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[10]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n3368) );
NAND2X1TS U4440 ( .A(n3369), .B(n3368), .Y(add_subt_data1[10]) );
AOI22X1TS U4441 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n2493), .B0(Data_1[11]),
.B1(n952), .Y(n3371) );
AOI22X1TS U4442 ( .A0(n2501), .A1(FPSENCOS_d_ff2_X[11]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n3370) );
NAND2X1TS U4443 ( .A(n3371), .B(n3370), .Y(add_subt_data1[11]) );
AOI22X1TS U4444 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n2493), .B0(Data_1[12]),
.B1(n952), .Y(n3373) );
AOI22X1TS U4445 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[12]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n3372) );
NAND2X1TS U4446 ( .A(n3373), .B(n3372), .Y(add_subt_data1[12]) );
AOI22X1TS U4447 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n2493), .B0(Data_1[13]),
.B1(n952), .Y(n3375) );
AOI22X1TS U4448 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[13]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n3374) );
NAND2X1TS U4449 ( .A(n3375), .B(n3374), .Y(add_subt_data1[13]) );
AOI22X1TS U4450 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n2493), .B0(Data_1[14]),
.B1(n952), .Y(n3377) );
AOI22X1TS U4451 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[14]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n3376) );
NAND2X1TS U4452 ( .A(n3377), .B(n3376), .Y(add_subt_data1[14]) );
AOI22X1TS U4453 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n2493), .B0(Data_1[15]),
.B1(n952), .Y(n3379) );
AOI22X1TS U4454 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[15]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n3378) );
NAND2X1TS U4455 ( .A(n3379), .B(n3378), .Y(add_subt_data1[15]) );
AOI22X1TS U4456 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n3418), .B0(Data_1[16]),
.B1(n2765), .Y(n3381) );
AOI22X1TS U4457 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[16]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n3380) );
NAND2X1TS U4458 ( .A(n3381), .B(n3380), .Y(add_subt_data1[16]) );
AOI22X1TS U4459 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n2493), .B0(Data_1[17]),
.B1(n2765), .Y(n3383) );
AOI22X1TS U4460 ( .A0(n3358), .A1(FPSENCOS_d_ff2_X[17]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n3382) );
NAND2X1TS U4461 ( .A(n3383), .B(n3382), .Y(add_subt_data1[17]) );
AOI22X1TS U4462 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n2493), .B0(Data_1[18]),
.B1(n2765), .Y(n3386) );
AOI22X1TS U4463 ( .A0(n3358), .A1(FPSENCOS_d_ff2_X[18]), .B0(n3384), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n3385) );
NAND2X1TS U4464 ( .A(n3386), .B(n3385), .Y(add_subt_data1[18]) );
AOI22X1TS U4465 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n3413), .B0(Data_1[19]),
.B1(n3387), .Y(n3389) );
AOI22X1TS U4466 ( .A0(n3392), .A1(FPSENCOS_d_ff2_X[19]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n3388) );
NAND2X1TS U4467 ( .A(n3389), .B(n3388), .Y(add_subt_data1[19]) );
AOI22X1TS U4468 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n3413), .B0(Data_1[20]),
.B1(n2765), .Y(n3391) );
AOI22X1TS U4469 ( .A0(n3420), .A1(FPSENCOS_d_ff2_X[20]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n3390) );
NAND2X1TS U4470 ( .A(n3391), .B(n3390), .Y(add_subt_data1[20]) );
AOI22X1TS U4471 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n3413), .B0(Data_1[21]),
.B1(n2765), .Y(n3394) );
AOI22X1TS U4472 ( .A0(n3392), .A1(FPSENCOS_d_ff2_X[21]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n3393) );
NAND2X1TS U4473 ( .A(n3394), .B(n3393), .Y(add_subt_data1[21]) );
AOI22X1TS U4474 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n3413), .B0(Data_1[22]),
.B1(n2765), .Y(n3396) );
AOI22X1TS U4475 ( .A0(n3358), .A1(FPSENCOS_d_ff2_X[22]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n3395) );
NAND2X1TS U4476 ( .A(n3396), .B(n3395), .Y(add_subt_data1[22]) );
AOI22X1TS U4477 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n3413), .B0(Data_1[23]),
.B1(n3417), .Y(n3398) );
AOI22X1TS U4478 ( .A0(n3358), .A1(FPSENCOS_d_ff2_X[23]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n3397) );
NAND2X1TS U4479 ( .A(n3398), .B(n3397), .Y(add_subt_data1[23]) );
AOI22X1TS U4480 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n3413), .B0(Data_1[24]),
.B1(n3417), .Y(n3400) );
AOI22X1TS U4481 ( .A0(n3410), .A1(FPSENCOS_d_ff2_X[24]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n3399) );
NAND2X1TS U4482 ( .A(n3400), .B(n3399), .Y(add_subt_data1[24]) );
AOI22X1TS U4483 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n3413), .B0(Data_1[25]),
.B1(n3417), .Y(n3402) );
AOI22X1TS U4484 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[25]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n3401) );
NAND2X1TS U4485 ( .A(n3402), .B(n3401), .Y(add_subt_data1[25]) );
AOI22X1TS U4486 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n3413), .B0(Data_1[26]),
.B1(n3417), .Y(n3404) );
AOI22X1TS U4487 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[26]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n3403) );
NAND2X1TS U4488 ( .A(n3404), .B(n3403), .Y(add_subt_data1[26]) );
AOI22X1TS U4489 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n3413), .B0(Data_1[27]),
.B1(n3417), .Y(n3406) );
AOI22X1TS U4490 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[27]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n3405) );
NAND2X1TS U4491 ( .A(n3406), .B(n3405), .Y(add_subt_data1[27]) );
AOI22X1TS U4492 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n3413), .B0(Data_1[28]),
.B1(n3417), .Y(n3409) );
AOI22X1TS U4493 ( .A0(n3407), .A1(FPSENCOS_d_ff2_X[28]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n3408) );
NAND2X1TS U4494 ( .A(n3409), .B(n3408), .Y(add_subt_data1[28]) );
AOI22X1TS U4495 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n3413), .B0(Data_1[29]),
.B1(n3417), .Y(n3412) );
AOI22X1TS U4496 ( .A0(n3410), .A1(FPSENCOS_d_ff2_X[29]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n3411) );
NAND2X1TS U4497 ( .A(n3412), .B(n3411), .Y(add_subt_data1[29]) );
AOI22X1TS U4498 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n3413), .B0(Data_1[30]),
.B1(n3417), .Y(n3416) );
AOI22X1TS U4499 ( .A0(n3420), .A1(FPSENCOS_d_ff2_X[30]), .B0(n3414), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n3415) );
NAND2X1TS U4500 ( .A(n3416), .B(n3415), .Y(add_subt_data1[30]) );
AOI22X1TS U4501 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n3418), .B0(Data_1[31]),
.B1(n3417), .Y(n3422) );
AOI22X1TS U4502 ( .A0(n3420), .A1(FPSENCOS_d_ff2_X[31]), .B0(n3419), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n3421) );
NAND2X1TS U4503 ( .A(n3422), .B(n3421), .Y(add_subt_data1[31]) );
OA21XLTS U4504 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n3424), .B0(n3423), .Y(
FPSENCOS_ITER_CONT_N4) );
AOI22X1TS U4505 ( .A0(n3462), .A1(cordic_result[31]), .B0(n3461), .B1(
mult_result[31]), .Y(n3426) );
OAI2BB1X1TS U4506 ( .A0N(n3464), .A1N(result_add_subt[31]), .B0(n3426), .Y(
op_result[31]) );
AOI22X1TS U4507 ( .A0(n3462), .A1(cordic_result[30]), .B0(n3461), .B1(
mult_result[30]), .Y(n3427) );
OAI2BB1X1TS U4508 ( .A0N(n3452), .A1N(result_add_subt[30]), .B0(n3427), .Y(
op_result[30]) );
AOI22X1TS U4509 ( .A0(n3462), .A1(cordic_result[29]), .B0(n3461), .B1(
mult_result[29]), .Y(n3428) );
OAI2BB1X1TS U4510 ( .A0N(n3464), .A1N(result_add_subt[29]), .B0(n3428), .Y(
op_result[29]) );
AOI22X1TS U4511 ( .A0(n3462), .A1(cordic_result[28]), .B0(n3461), .B1(
mult_result[28]), .Y(n3429) );
OAI2BB1X1TS U4512 ( .A0N(n2648), .A1N(result_add_subt[28]), .B0(n3429), .Y(
op_result[28]) );
AOI22X1TS U4513 ( .A0(n3462), .A1(cordic_result[27]), .B0(n3461), .B1(
mult_result[27]), .Y(n3430) );
OAI2BB1X1TS U4514 ( .A0N(n2648), .A1N(result_add_subt[27]), .B0(n3430), .Y(
op_result[27]) );
AOI22X1TS U4515 ( .A0(n3462), .A1(cordic_result[26]), .B0(n3461), .B1(
mult_result[26]), .Y(n3431) );
OAI2BB1X1TS U4516 ( .A0N(n2648), .A1N(result_add_subt[26]), .B0(n3431), .Y(
op_result[26]) );
AOI22X1TS U4517 ( .A0(n3462), .A1(cordic_result[25]), .B0(n3461), .B1(
mult_result[25]), .Y(n3432) );
OAI2BB1X1TS U4518 ( .A0N(n2648), .A1N(result_add_subt[25]), .B0(n3432), .Y(
op_result[25]) );
AOI22X1TS U4519 ( .A0(n3462), .A1(cordic_result[24]), .B0(n3461), .B1(
mult_result[24]), .Y(n3433) );
OAI2BB1X1TS U4520 ( .A0N(n3452), .A1N(result_add_subt[24]), .B0(n3433), .Y(
op_result[24]) );
AOI22X1TS U4521 ( .A0(n3462), .A1(cordic_result[23]), .B0(n3461), .B1(
mult_result[23]), .Y(n3434) );
OAI2BB1X1TS U4522 ( .A0N(n3452), .A1N(result_add_subt[23]), .B0(n3434), .Y(
op_result[23]) );
AOI22X1TS U4523 ( .A0(n3462), .A1(cordic_result[22]), .B0(n3461), .B1(
mult_result[22]), .Y(n3435) );
OAI2BB1X1TS U4524 ( .A0N(n3452), .A1N(result_add_subt[22]), .B0(n3435), .Y(
op_result[22]) );
AOI22X1TS U4525 ( .A0(n3462), .A1(cordic_result[21]), .B0(n3461), .B1(
mult_result[21]), .Y(n3436) );
OAI2BB1X1TS U4526 ( .A0N(n3452), .A1N(result_add_subt[21]), .B0(n3436), .Y(
op_result[21]) );
AOI22X1TS U4527 ( .A0(n3462), .A1(cordic_result[20]), .B0(n3461), .B1(
mult_result[20]), .Y(n3437) );
OAI2BB1X1TS U4528 ( .A0N(n3452), .A1N(result_add_subt[20]), .B0(n3437), .Y(
op_result[20]) );
AOI22X1TS U4529 ( .A0(n3462), .A1(cordic_result[19]), .B0(n3461), .B1(
mult_result[19]), .Y(n3438) );
OAI2BB1X1TS U4530 ( .A0N(n3452), .A1N(result_add_subt[19]), .B0(n3438), .Y(
op_result[19]) );
AOI22X1TS U4531 ( .A0(n3459), .A1(cordic_result[18]), .B0(n3458), .B1(
mult_result[18]), .Y(n3439) );
OAI2BB1X1TS U4532 ( .A0N(n3452), .A1N(result_add_subt[18]), .B0(n3439), .Y(
op_result[18]) );
AOI22X1TS U4533 ( .A0(n3459), .A1(cordic_result[17]), .B0(n3458), .B1(
mult_result[17]), .Y(n3440) );
OAI2BB1X1TS U4534 ( .A0N(n3452), .A1N(result_add_subt[17]), .B0(n3440), .Y(
op_result[17]) );
AOI22X1TS U4535 ( .A0(n3459), .A1(cordic_result[16]), .B0(n3458), .B1(
mult_result[16]), .Y(n3441) );
OAI2BB1X1TS U4536 ( .A0N(n3452), .A1N(result_add_subt[16]), .B0(n3441), .Y(
op_result[16]) );
AOI22X1TS U4537 ( .A0(n3459), .A1(cordic_result[15]), .B0(n3458), .B1(
mult_result[15]), .Y(n3442) );
OAI2BB1X1TS U4538 ( .A0N(n3452), .A1N(result_add_subt[15]), .B0(n3442), .Y(
op_result[15]) );
AOI22X1TS U4539 ( .A0(n3459), .A1(cordic_result[14]), .B0(n3458), .B1(
mult_result[14]), .Y(n3443) );
OAI2BB1X1TS U4540 ( .A0N(n3452), .A1N(result_add_subt[14]), .B0(n3443), .Y(
op_result[14]) );
AOI22X1TS U4541 ( .A0(n3459), .A1(cordic_result[13]), .B0(n3458), .B1(
mult_result[13]), .Y(n3444) );
OAI2BB1X1TS U4542 ( .A0N(n3452), .A1N(result_add_subt[13]), .B0(n3444), .Y(
op_result[13]) );
AOI22X1TS U4543 ( .A0(n3459), .A1(cordic_result[12]), .B0(n3458), .B1(
mult_result[12]), .Y(n3445) );
OAI2BB1X1TS U4544 ( .A0N(n3452), .A1N(result_add_subt[12]), .B0(n3445), .Y(
op_result[12]) );
AOI22X1TS U4545 ( .A0(n3459), .A1(cordic_result[11]), .B0(n3458), .B1(
mult_result[11]), .Y(n3446) );
OAI2BB1X1TS U4546 ( .A0N(n3464), .A1N(result_add_subt[11]), .B0(n3446), .Y(
op_result[11]) );
AOI22X1TS U4547 ( .A0(n3459), .A1(cordic_result[10]), .B0(n3458), .B1(
mult_result[10]), .Y(n3447) );
OAI2BB1X1TS U4548 ( .A0N(n3464), .A1N(result_add_subt[10]), .B0(n3447), .Y(
op_result[10]) );
AOI22X1TS U4549 ( .A0(n3459), .A1(cordic_result[9]), .B0(n3458), .B1(
mult_result[9]), .Y(n3448) );
OAI2BB1X1TS U4550 ( .A0N(n3464), .A1N(result_add_subt[9]), .B0(n3448), .Y(
op_result[9]) );
AOI22X1TS U4551 ( .A0(n3459), .A1(cordic_result[8]), .B0(n3458), .B1(
mult_result[8]), .Y(n3449) );
OAI2BB1X1TS U4552 ( .A0N(n3464), .A1N(result_add_subt[8]), .B0(n3449), .Y(
op_result[8]) );
AOI22X1TS U4553 ( .A0(n3459), .A1(cordic_result[7]), .B0(n3458), .B1(
mult_result[7]), .Y(n3450) );
OAI2BB1X1TS U4554 ( .A0N(n3464), .A1N(result_add_subt[7]), .B0(n3450), .Y(
op_result[7]) );
AOI22X1TS U4555 ( .A0(n3459), .A1(cordic_result[6]), .B0(n3458), .B1(
mult_result[6]), .Y(n3451) );
OAI2BB1X1TS U4556 ( .A0N(n3452), .A1N(result_add_subt[6]), .B0(n3451), .Y(
op_result[6]) );
AOI22X1TS U4557 ( .A0(n3425), .A1(cordic_result[5]), .B0(n3455), .B1(
mult_result[5]), .Y(n3453) );
OAI2BB1X1TS U4558 ( .A0N(n3464), .A1N(result_add_subt[5]), .B0(n3453), .Y(
op_result[5]) );
AOI22X1TS U4559 ( .A0(n3425), .A1(cordic_result[4]), .B0(n3455), .B1(
mult_result[4]), .Y(n3454) );
OAI2BB1X1TS U4560 ( .A0N(n3464), .A1N(result_add_subt[4]), .B0(n3454), .Y(
op_result[4]) );
AOI22X1TS U4561 ( .A0(n3459), .A1(cordic_result[3]), .B0(n3455), .B1(
mult_result[3]), .Y(n3456) );
OAI2BB1X1TS U4562 ( .A0N(n3464), .A1N(result_add_subt[3]), .B0(n3456), .Y(
op_result[3]) );
AOI22X1TS U4563 ( .A0(n3462), .A1(cordic_result[2]), .B0(n3461), .B1(
mult_result[2]), .Y(n3457) );
OAI2BB1X1TS U4564 ( .A0N(n3464), .A1N(result_add_subt[2]), .B0(n3457), .Y(
op_result[2]) );
AOI22X1TS U4565 ( .A0(n3459), .A1(cordic_result[1]), .B0(n3458), .B1(
mult_result[1]), .Y(n3460) );
OAI2BB1X1TS U4566 ( .A0N(n3464), .A1N(result_add_subt[1]), .B0(n3460), .Y(
op_result[1]) );
AOI22X1TS U4567 ( .A0(n3462), .A1(cordic_result[0]), .B0(n3461), .B1(
mult_result[0]), .Y(n3463) );
OAI2BB1X1TS U4568 ( .A0N(n3464), .A1N(result_add_subt[0]), .B0(n3463), .Y(
op_result[0]) );
AOI22X1TS U4569 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3467), .B0(n3465),
.B1(n3565), .Y(n861) );
AOI22X1TS U4570 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3467), .B0(n3466),
.B1(n3565), .Y(n853) );
OAI2BB1X1TS U4571 ( .A0N(FPSENCOS_cont_iter_out[1]), .A1N(n851), .B0(n3468),
.Y(n852) );
AOI22X1TS U4572 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3470), .B0(n3469),
.B1(n3565), .Y(n848) );
INVX2TS U4573 ( .A(n3475), .Y(n3471) );
AOI22X1TS U4574 ( .A0(ack_operation), .A1(n3704), .B0(begin_operation), .B1(
n3471), .Y(n3473) );
OAI22X1TS U4575 ( .A0(n3475), .A1(n3474), .B0(n3473), .B1(n3472), .Y(n846)
);
OAI22X1TS U4576 ( .A0(n3479), .A1(n3478), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n3477), .Y(n844) );
AOI22X1TS U4577 ( .A0(FPSENCOS_cont_var_out[0]), .A1(n3481), .B0(n3480),
.B1(n3522), .Y(n843) );
NAND2X1TS U4578 ( .A(n3482), .B(n3648), .Y(FPADDSUB__6_net_) );
NOR4X1TS U4579 ( .A(FPMULT_Op_MY[0]), .B(FPMULT_Op_MY[2]), .C(
FPMULT_Op_MY[3]), .D(FPMULT_Op_MY[11]), .Y(n3485) );
NOR4X1TS U4580 ( .A(FPMULT_Op_MY[24]), .B(FPMULT_Op_MY[25]), .C(
FPMULT_Op_MY[26]), .D(FPMULT_Op_MY[27]), .Y(n3484) );
NOR4X1TS U4581 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[28]), .C(
FPMULT_Op_MY[29]), .D(FPMULT_Op_MY[30]), .Y(n3483) );
NAND4XLTS U4582 ( .A(n3486), .B(n3485), .C(n3484), .D(n3483), .Y(n3502) );
NOR4X1TS U4583 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[9]), .C(
FPMULT_Op_MY[21]), .D(FPMULT_Op_MY[10]), .Y(n3490) );
NOR4X1TS U4584 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[4]), .C(
FPMULT_Op_MY[13]), .D(FPMULT_Op_MY[5]), .Y(n3489) );
NOR3XLTS U4585 ( .A(FPMULT_Op_MY[12]), .B(n914), .C(FPMULT_Op_MY[23]), .Y(
n3487) );
NAND4XLTS U4586 ( .A(n3490), .B(n3489), .C(n3488), .D(n3487), .Y(n3501) );
NOR4X1TS U4587 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_Op_MX[25]), .C(
FPMULT_Op_MX[26]), .D(FPMULT_Op_MX[27]), .Y(n3492) );
NAND4XLTS U4588 ( .A(n3494), .B(n3493), .C(n3492), .D(n3491), .Y(n3500) );
NOR4X1TS U4589 ( .A(FPMULT_Op_MX[9]), .B(n913), .C(FPMULT_Op_MX[7]), .D(
FPMULT_Op_MX[8]), .Y(n3498) );
NOR4X1TS U4590 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[4]), .C(
FPMULT_Op_MX[13]), .D(FPMULT_Op_MX[5]), .Y(n3497) );
NOR3XLTS U4591 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[19]), .C(
FPMULT_Op_MX[24]), .Y(n3495) );
NAND4XLTS U4592 ( .A(n3498), .B(n3497), .C(n3496), .D(n3495), .Y(n3499) );
OAI22X1TS U4593 ( .A0(n3502), .A1(n3501), .B0(n3500), .B1(n3499), .Y(n106)
);
AO22XLTS U4594 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n3648), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n819) );
AO22XLTS U4595 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n3556), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n816) );
XNOR2X1TS U4596 ( .A(FPADDSUB_intDX_EWSW[31]), .B(n3746), .Y(n30) );
AO22XLTS U4597 ( .A0(busy), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n3648), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n813) );
NOR2BX1TS U4598 ( .AN(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(FPADDSUB__19_net_) );
XOR2XLTS U4599 ( .A(n3503), .B(FPSENCOS_d_ff2_Y[30]), .Y(
FPSENCOS_sh_exp_y[7]) );
XNOR2X1TS U4600 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n3504), .Y(
FPSENCOS_sh_exp_y[6]) );
AO21XLTS U4601 ( .A0(intadd_1049_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n3505),
.Y(FPSENCOS_sh_exp_y[4]) );
XOR2XLTS U4602 ( .A(n3506), .B(FPSENCOS_d_ff2_X[30]), .Y(
FPSENCOS_sh_exp_x[7]) );
XNOR2X1TS U4603 ( .A(FPSENCOS_d_ff2_X[29]), .B(n3507), .Y(
FPSENCOS_sh_exp_x[6]) );
AO21XLTS U4604 ( .A0(intadd_1048_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n3508),
.Y(FPSENCOS_sh_exp_x[4]) );
CMPR42X2TS U4605 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
DP_OP_499J312_125_1651_n96), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .D(
DP_OP_499J312_125_1651_n39), .ICI(DP_OP_499J312_125_1651_n40), .S(
DP_OP_499J312_125_1651_n38), .ICO(DP_OP_499J312_125_1651_n36), .CO(
DP_OP_499J312_125_1651_n37) );
CMPR42X2TS U4606 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
DP_OP_499J312_125_1651_n104), .C(DP_OP_499J312_125_1651_n63), .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .ICI(
DP_OP_499J312_125_1651_n64), .S(DP_OP_499J312_125_1651_n62), .ICO(
DP_OP_499J312_125_1651_n60), .CO(DP_OP_499J312_125_1651_n61) );
CMPR42X2TS U4607 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
DP_OP_499J312_125_1651_n102), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .D(
DP_OP_499J312_125_1651_n57), .ICI(DP_OP_499J312_125_1651_n58), .S(
DP_OP_499J312_125_1651_n56), .ICO(DP_OP_499J312_125_1651_n54), .CO(
DP_OP_499J312_125_1651_n55) );
CMPR42X2TS U4608 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
DP_OP_499J312_125_1651_n103), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .D(
DP_OP_499J312_125_1651_n60), .ICI(DP_OP_499J312_125_1651_n61), .S(
DP_OP_499J312_125_1651_n59), .ICO(DP_OP_499J312_125_1651_n57), .CO(
DP_OP_499J312_125_1651_n58) );
CMPR42X2TS U4609 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
DP_OP_499J312_125_1651_n106), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .D(
DP_OP_499J312_125_1651_n69), .ICI(DP_OP_499J312_125_1651_n70), .S(
DP_OP_499J312_125_1651_n68), .ICO(DP_OP_499J312_125_1651_n66), .CO(
DP_OP_499J312_125_1651_n67) );
CMPR42X2TS U4610 ( .A(DP_OP_498J312_124_1725_n120), .B(
DP_OP_498J312_124_1725_n113), .C(DP_OP_498J312_124_1725_n106), .D(
DP_OP_498J312_124_1725_n99), .ICI(DP_OP_498J312_124_1725_n196), .S(
DP_OP_498J312_124_1725_n49), .ICO(DP_OP_498J312_124_1725_n47), .CO(
DP_OP_498J312_124_1725_n48) );
CMPR42X2TS U4611 ( .A(DP_OP_498J312_124_1725_n202), .B(n1272), .C(
DP_OP_498J312_124_1725_n201), .D(DP_OP_498J312_124_1725_n118), .ICI(
DP_OP_498J312_124_1725_n125), .S(DP_OP_498J312_124_1725_n75), .ICO(
DP_OP_498J312_124_1725_n73), .CO(DP_OP_498J312_124_1725_n74) );
CMPR42X2TS U4612 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
DP_OP_499J312_125_1651_n105), .C(DP_OP_499J312_125_1651_n66), .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .ICI(
DP_OP_499J312_125_1651_n67), .S(DP_OP_499J312_125_1651_n65), .ICO(
DP_OP_499J312_125_1651_n63), .CO(DP_OP_499J312_125_1651_n64) );
CMPR42X2TS U4613 ( .A(DP_OP_498J312_124_1725_n279), .B(
DP_OP_498J312_124_1725_n269), .C(DP_OP_498J312_124_1725_n274), .D(
DP_OP_498J312_124_1725_n244), .ICI(DP_OP_498J312_124_1725_n241), .S(
DP_OP_498J312_124_1725_n239), .ICO(DP_OP_498J312_124_1725_n237), .CO(
DP_OP_498J312_124_1725_n238) );
CMPR42X1TS U4614 ( .A(DP_OP_498J312_124_1725_n121), .B(
DP_OP_498J312_124_1725_n107), .C(DP_OP_498J312_124_1725_n59), .D(
DP_OP_498J312_124_1725_n56), .ICI(DP_OP_498J312_124_1725_n55), .S(
DP_OP_498J312_124_1725_n52), .ICO(DP_OP_498J312_124_1725_n50), .CO(
DP_OP_498J312_124_1725_n51) );
CMPR42X1TS U4615 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(
DP_OP_498J312_124_1725_n81), .C(DP_OP_498J312_124_1725_n48), .D(
DP_OP_498J312_124_1725_n44), .ICI(DP_OP_498J312_124_1725_n43), .S(
DP_OP_498J312_124_1725_n40), .ICO(DP_OP_498J312_124_1725_n38), .CO(
DP_OP_498J312_124_1725_n39) );
CMPR42X2TS U4616 ( .A(DP_OP_498J312_124_1725_n370), .B(
DP_OP_498J312_124_1725_n355), .C(DP_OP_498J312_124_1725_n360), .D(
DP_OP_498J312_124_1725_n335), .ICI(DP_OP_498J312_124_1725_n332), .S(
DP_OP_498J312_124_1725_n330), .ICO(DP_OP_498J312_124_1725_n328), .CO(
DP_OP_498J312_124_1725_n329) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CONB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__CONB_BEHAVIORAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_ls__udp_pwrgood_pp_p.v"
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_ls__udp_pwrgood_pp_g.v"
`celldefine
module sky130_fd_sc_ls__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_ls__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_ls__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CONB_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 20:32:40 05/17/2016
// Design Name:
// Module Name: picture_timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module generador_imagenes
(
input clk,
input reset,
input wire video_on,//señal que indica que se encuentra en la región visible de resolución 640x480
input wire [9:0] pixel_x, pixel_y,
output wire pic_on,
output wire [7:0] pic_RGB
);
//Declaración de constantes
localparam pic_hora_XL = 256; //Límite izquierdo
localparam pic_hora_XR = 384; //Límite derecho
localparam pic_hora_YB = 64; //Límite inferior
localparam pic_hora_size = 8192;// (128x64)
localparam pic_timer_XL = 416; //Límite izquierdo
localparam pic_timer_XR = 496; //Límite derecho
localparam pic_timer_YT = 416; //Límite superior
localparam pic_timer_YB = 479; //Límite inferior
localparam pic_timer_size = 2560;// (80x32)
localparam pic_ring_XL = 512; //Límite izquierdo
localparam pic_ring_XR = 639; //Límite derecho
localparam pic_ring_YT = 128; //Límite superior
localparam pic_ring_YB = 191; //Límite inferior
localparam pic_ring_size = 8192;// (128x64)
localparam pic_ringball_XL = 544; //Límite izquierdo
localparam pic_ringball_XR = 592; //Límite derecho
localparam pic_ringball_YT = 64; //Límite superior
localparam pic_ringball_YB = 112; //Límite inferior
localparam pic_ringball_size = 2304;// (48x48)
localparam pic_logo_XR = 128; //Límite derecho
localparam pic_logo_YB = 16; //Límite inferior
localparam pic_logo_size = 2048;// (128x16)
//Declaración de señales
reg [7:0] pic_RGB_aux;
reg [7:0] colour_data_hora [0:pic_hora_size-1]; //datos de los colores
reg [7:0] colour_data_timer [0:pic_timer_size-1]; //datos de los colores
reg [7:0] colour_data_ring [0:pic_ring_size-1]; //datos de los colores
reg [7:0] colour_data_ringball [0:pic_ringball_size-1]; //datos de los colores
reg [7:0] colour_data_logo [0:pic_logo_size-1]; //datos de los colores
wire pic_hora_on, pic_timer_on, pic_ring_on, pic_ringball_on, pic_logo_on;
reg [12:0] index_counter_hora_reg, index_counter_hora_next;
wire [12:0] index_counter_hora;
reg [11:0] index_counter_timer_reg, index_counter_timer_next;
wire [11:0] index_counter_timer;
reg [12:0] index_counter_ring_reg, index_counter_ring_next;
wire [12:0] index_counter_ring;
reg [11:0] index_counter_ringball_reg, index_counter_ringball_next;
wire [11:0] index_counter_ringball;
reg [10:0] index_counter_logo_reg, index_counter_logo_next;
wire [10:0] index_counter_logo;
//Contadores para recorrer la memoria
always @(posedge clk)//Todos los contadores tienen la misma lógica de asignación de estados
begin
if(reset)
begin
index_counter_hora_reg <= 0;
index_counter_timer_reg <= 0;
index_counter_ring_reg <= 0;
index_counter_ringball_reg <= 0;
index_counter_logo_reg <= 0;
end
else
begin
index_counter_hora_reg <= index_counter_hora_next;
index_counter_timer_reg <= index_counter_timer_next;
index_counter_ring_reg <= index_counter_ring_next;
index_counter_ringball_reg <= index_counter_ringball_next;
index_counter_logo_reg <= index_counter_logo_next;
end
end
//===================================================
// Imagen HORA
//===================================================
initial
$readmemh ("hora.list", colour_data_hora);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_hora_on = (pic_hora_XL<=pixel_x)&&(pixel_x<=pic_hora_XR)&&(pixel_y<=pic_hora_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_hora_on)
begin
index_counter_hora_next = index_counter_hora_reg + 1'b1;
end
else
begin
index_counter_hora_next = 0;
end
end
assign index_counter_hora = index_counter_hora_reg;
//===================================================
// Imagen TIMER
//===================================================
initial
$readmemh ("timer.list", colour_data_timer);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_timer_on = (pic_timer_XL<=pixel_x)&&(pixel_x<=pic_timer_XR)&&(pic_timer_YT<=pixel_y)&&(pixel_y<=pic_timer_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_timer_on)
begin
index_counter_timer_next = index_counter_timer_reg + 1'b1;
end
else
begin
index_counter_timer_next = 0;
end
end
assign index_counter_timer = index_counter_timer_reg;
//===================================================
// Imagen RING
//===================================================
initial
$readmemh ("ring.list", colour_data_ring);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_ring_on = (pic_ring_XL<=pixel_x)&&(pixel_x<=pic_ring_XR)&&(pic_ring_YT<=pixel_y)&&(pixel_y<=pic_ring_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_ring_on)
begin
index_counter_ring_next = index_counter_ring_reg + 1'b1;
end
else
begin
index_counter_ring_next = 0;
end
end
assign index_counter_ring = index_counter_ring_reg;
//===================================================
// Imagen RING BALL
//===================================================
initial
$readmemh ("ring_ball.list", colour_data_ringball);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_ringball_on = (pic_ringball_XL<=pixel_x)&&(pixel_x<=pic_ringball_XR)&&(pic_ringball_YT<=pixel_y)&&(pixel_y<=pic_ringball_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_ringball_on)
begin
index_counter_ringball_next = index_counter_ringball_reg + 1'b1;
end
else
begin
index_counter_ringball_next = 0;
end
end
assign index_counter_ringball = index_counter_ringball_reg;
//===================================================
// Imagen LOGO
//===================================================
initial
$readmemh ("logo.list", colour_data_logo);//Leer datos RBG de archivo de texto, sintetiza una ROM
//Imprime la imagen de hora dentro de la región
assign pic_logo_on = (pixel_x<=pic_logo_XR)&&(pixel_y<=pic_logo_YB);//Para saber cuando se está imprimiendo la imagen
always@*
begin
if(pic_logo_on)
begin
index_counter_logo_next = index_counter_logo_reg + 1'b1;
end
else
begin
index_counter_logo_next = 0;
end
end
assign index_counter_logo = index_counter_logo_reg;
//------------------------------------------------------------------------------------------------------------------------
//Multiplexa el RGB
always @*
begin
if(~video_on)
pic_RGB_aux = 12'b0;//fondo negro
else
if(pic_hora_on) pic_RGB_aux = colour_data_hora[index_counter_hora];
else if (pic_timer_on) pic_RGB_aux = colour_data_timer[index_counter_timer];
else if (pic_ring_on) pic_RGB_aux = colour_data_ring[index_counter_ring];
else if (pic_ringball_on) pic_RGB_aux = colour_data_ringball[index_counter_ringball];
else if (pic_logo_on) pic_RGB_aux = colour_data_logo[index_counter_logo];
else pic_RGB_aux = 12'b0;//fondo negro
end
//assign pic_RGB = {pic_RGB_aux[7:5],1'b0,pic_RGB_aux[4:2],1'b0,pic_RGB_aux[1:0],2'b0}; //Rellena pic_RGB para pasar de 8 bits a 12 bits
assign pic_RGB = pic_RGB_aux;//Para 8 bits (Nexys 3)
assign pic_on = pic_hora_on | pic_timer_on| pic_ring_on| pic_ringball_on| pic_logo_on;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_code_distance (clock, reset, enable, test_expr1, test_expr2, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min = 1;
parameter max = 1;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1 : 0] test_expr1;
input [width-1 : 0] test_expr2;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_CODE_DISTANCE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_code_distance_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_code_distance
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221A_4_V
`define SKY130_FD_SC_HD__O221A_4_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o221a_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221A_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:20:37 02/23/2012
// Design Name:
// Module Name: clkdiv
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_div(input clk, output clk1);
parameter divide = 16;
wire clk0;
DCM_SP #(
.CLKDV_DIVIDE(divide) // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
) DCM_SP_inst (
.CLKDV(clk1), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKIN(clk), // Clock input (from IBUFG, BUFG or DCM)
.CLK0(clk0),
.CLKFB(clk0),
.RST(0)
);
endmodule
module my_clk_div(input clk, output reg clk1 = 0);
parameter divide = 16;
integer cnt = 0;
always @(posedge clk) begin
cnt <= (cnt?cnt:(divide/2)) - 1;
if (!cnt) clk1 <= ~clk1;
end
endmodule
|
module helloworld (
input clk,
input rst,
output [7:0] tx_data,
output reg new_tx_data,
input tx_busy,
input [7:0] rx_data,
input new_rx_data
);
localparam STATE_SIZE = 1;
localparam IDLE = 0,
PRINT_MESSAGE = 1;
localparam MESSAGE_LEN = 23;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [4:0] addr_d, addr_q;
rom_helloworld rom_helloworld (
.clk(clk),
.addr(addr_q),
.data(tx_data)
);
always @(*) begin
state_d = state_q; // default values
addr_d = addr_q; // needed to prevent latches
new_tx_data = 1'b0;
case (state_q)
IDLE: begin
addr_d = 4'd0;
if (new_rx_data && rx_data == "h")
state_d = PRINT_MESSAGE;
end
PRINT_MESSAGE: begin
if (!tx_busy) begin
new_tx_data = 1'b1;
addr_d = addr_q + 1'b1;
if (addr_q == MESSAGE_LEN-1)
state_d = IDLE;
end
end
default: state_d = IDLE;
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
addr_q <= addr_d;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:51:58 03/24/2014
// Design Name:
// Module Name: MIPS32
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mips32(/*AUTOARG*/
// Outputs
port_PC, port_inst, port_alu,
// Inputs
rst, clk, interrupts
);
input rst;
input clk;
//input port_in;
input [4:0] interrupts;
output reg [31:0] port_PC, port_inst, port_alu;
reg [31:0] PC;
reg [31:0] PCadd4;
wire [31:0] PCout, PCnext;
wire [31:0] HI;
wire [31:0] LO;
wire [31:0] inst;
wire [31:0] immediate;
wire [4:0] rs, rt, rd;
wire load, store, move, ssnop, nop,jump, branch,sign, regwrite,memtoreg,memread, memwrite;
wire [20:0] aluc;
wire [3:0] move_op;
wire [8:0] load_op;
wire [5:0] store_op;
wire [31:0] regrs_data, regrt_data;
wire [31:0] memaddr;
wire [31:0] memdata_in;
// IF stage
wire IF_stall;
wire IF_flush;
wire [31:0] IF_inst;
reg [31:0] IF_PC, IF_PCnext;
//wire [31:0] ID_inst;
//wire [31:0] ID_PCnext;
// ID stage
wire ID_stall;
wire ID_flush;
wire [31:0] ID_inst;
wire [31:0] ID_PCnext;
wire [4:0] ID_reg_dst;
wire [31:0] ID_data_a, ID_data_b, ID_data_c;
//wire [20:0] aluc;
wire ID_sign;
wire ID_memread, ID_memwrite;
wire [31:0] ID_memaddr;
wire [8:0] ID_load_op;
wire [5:0] ID_store_op;
wire ID_memtoreg, ID_regwrite;
wire [31:0] EX_data_a, EX_data_b, EX_data_c;
wire [20:0] EX_aluc;
wire EX_sign;
wire EX_memread, EX_memwrite;
wire [31:0] EX_memaddr;
wire [8:0] EX_load_op;
wire [5:0] EX_store_op;
wire EX_memtoreg, EX_regwrite;
// EXE stage:
wire EX_stall;
wire EX_flush;
wire [31:0] EX_alu_out;
wire [31:0] EX_alu_out_t;
wire [4:0] EX_rt_rd;
wire M_regwrite;
wire M_memtoreg;
wire M_memread;
wire M_memwrite;
wire [31:0] M_memaddr;
wire [8:0] M_load_op;
wire [5:0] M_store_op;
wire [31:0] M_alu_out;
wire [31:0] M_readdata;
wire [4:0] M_rt_rd;
wire M_flush;
wire M_stall;
wire WB_stall;
wire WB_regwrite;
wire WB_memtoreg;
wire [31:0] WB_readdata;
wire [31:0] WB_alu_out;
wire [4:0] WB_rtrd;
IF_stage IF_stage_0(/*AUTOINST*/
// Outputs
.ID_inst (ID_inst),
.ID_PCnext (ID_PCnext),
// Inputs
.clk (clk),
.rst (rst),
.IF_stall (IF_stall),
.IF_flush (IF_flush),
.ID_stall (ID_stall),
.IF_inst (IF_inst),
.IF_PCnext (IF_PCnext),
.IF_PC (IF_PC));
always @(posedge clk) begin
if (rst) begin
PC <= 32'b0;
//PCnext <= 32'b0;
IF_PCnext <= 32'b0;
end else begin
PC <= PCnext;
IF_PCnext <= PC;
PCadd4 <= PC + 32'h0000_0004;
end
end
mux2 #(.WIDTH(32)) PC_mux(
.sel (jump|branch),
.in0 (PCadd4),
.in1 (PCout),
.out (PCnext)
);
rom rom_0(
.PC (PC),
.inst (IF_inst),
.clk (clk)
);
//wire [31:0] target_offset;
//wire [25:0] inst_idx;
//wire [4:0] regdst;
decode decode_0(
.clk (clk),
.inst_in (ID_inst),
.PCin (ID_PCnext),
.regrs_data (regrs_data),
.regrt_data (regrt_data),
//Outputs
.PCout (PCout),
.jump (jump),
.ssnop (ssnop),
.branch (branch),
.aluc (ID_aluc),
.sign (ID_sign),
//.base (base),
//.immediate (immediate),
.store (store),
.store_op (ID_store_op),
.op_a (ID_data_a),
.op_b (ID_data_b),
.op_sa (ID_data_c),
.move (move),
.move_op (move_op),
.rs (rs),
.rt (rt),
.rd (rd),
.nop (nop),
.load (load),
.load_op (ID_load_op),
//.target_offset(target_offset),
//.inst_idx (inst_idx),
.regwrite (ID_regwrite),
.memtoreg (ID_memtoreg),
.memread (ID_memread),
.regdst (ID_reg_dst),
.memwrite (ID_memwrite),
.memaddr (ID_memaddr)
);
ID_stage ID_stage_0(/*AUTOINST*/
// Outputs
.EX_data_a (EX_data_a[31:0]),
.EX_data_b (EX_data_b[31:0]),
.EX_data_c (EX_data_c[31:0]),
.EX_aluc (EX_aluc[20:0]),
.EX_sign (EX_sign),
.EX_memread (EX_memread),
.EX_memwrite (EX_memwrite),
.EX_memaddr (EX_memaddr),
.EX_load_op (EX_load_op[8:0]),
.EX_store_op (EX_store_op[5:0]),
.EX_memtoreg (EX_memtoreg),
.EX_regwrite (EX_regwrite),
// Inputs
.clk (clk),
.rst (rst),
.ID_stall (ID_stall),
.ID_flush (ID_flush),
.EX_stall (EX_stall),
.ID_reg_dst (ID_reg_dst[4:0]),
.ID_data_a (ID_data_a[31:0]),
.ID_data_b (ID_data_b[31:0]),
.ID_data_c (ID_data_c[31:0]),
.ID_aluc (ID_aluc),
.ID_sign (ID_sign),
.ID_memread (ID_memread),
.ID_memwrite (ID_memwrite),
.ID_memaddr (ID_memaddr),
.ID_load_op (ID_load_op[8:0]),
.ID_store_op (ID_store_op[5:0]),
.ID_memtoreg (ID_memtoreg),
.ID_regwrite (ID_regwrite));
alu alu_0(
//Inputs
//.data_c (ID_data_c),
.clk (clk),
.aluc (EX_aluc),
.sign (EX_sign),
.data_a (EX_data_a),
.data_b (EX_data_b),
.data_c (EX_data_c),
//Outputs
.data_out_t (EX_alu_out_t),
.overflow (overflow),
.ready (ready),
.data_out (EX_alu_out));
EX_stage EX_stage_0(
// Outputs
.M_regwrite (M_regwrite),
.M_memtoreg (M_memtoreg),
.M_memread (M_memread),
.M_memwrite (M_memwrite),
.M_memaddr (M_memaddr),
.M_load_op (M_load_op[8:0]),
.M_store_op (M_store_op[5:0]),
.M_alu_out (M_alu_out[31:0]),
.M_rt_rd (M_rt_rd[4:0]),
// Inputs
.clk (clk),
.rst (rst),
.EX_stall (EX_stall),
.EX_flush (EX_flush),
.M_stall (M_stall),
.EX_regwrite (EX_regwrite),
//.EX_reg_dst (ID_reg_dst),
.EX_memtoreg (EX_memtoreg),
.EX_memread (EX_memread),
.EX_memwrite (EX_memwrite),
.EX_memaddr (EX_memaddr),
.EX_load_op (EX_load_op[8:0]),
.EX_store_op (EX_store_op[5:0]),
.EX_alu_out (EX_alu_out[31:0]),
.EX_alu_out_t (EX_alu_out_t[31:0]),
.EX_rt_rd (ID_reg_dst));
reg [31:0] gpr_data_in;
always @* begin
case (WB_memtoreg)
1'b1: gpr_data_in <= WB_readdata;
1'b0: gpr_data_in <= WB_alu_out;
endcase
end
gpr gpr_0(
// Outputs
.reg_out1 (regrt_data),
.reg_out2 (regrs_data),
// Inputs
.clk (clk),
.regwrite (WB_regwrite),
.data_in (gpr_data_in),
.write_addr (WB_rtrd),
.reg_addr1 (rs),
.reg_addr2 (rt));
data_ram data_ram_0(
.clk (clk),
.rst (rst),
.m_read (M_memread),
.m_write (M_memwrite),
.m_addr (M_memaddr),
.m_din (memdata_in),
// Outputs
.m_dout (M_readdata)
);
MEM_stage MEM_stage_0(
// Outputs
.WB_regwrite (WB_regwrite),
.WB_memtoreg (WB_memtoreg),
.WB_readdata (WB_readdata),
.WB_alu_out (WB_alu_out[31:0]),
.WB_rt_rd (WB_rtrd),
// Inputs
.clk (clk),
.rst (rst),
.M_flush (M_flush),
.M_stall (M_stall),
.WB_stall (WB_stall),
.M_regwrite (M_regwrite),
.M_memtoreg (M_memtoreg),
.M_readdata (M_readdata),
.M_alu_out (M_alu_out[31:0]),
.M_rt_rd (M_rt_rd[4:0]));
always @(posedge clk) begin
port_PC <= PCnext;
port_alu <= WB_alu_out;
port_inst <= IF_inst;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbarbiter.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: At some point in time, I might wish to have two masters connect
// to the same wishbone bus. As an example, I might wish to have
// both the instruction fetch and the load/store operators
// of my Zip CPU access the the same bus. How shall they both
// get access to the same resource? This module allows the
// wishbone interfaces from two sources to drive the bus, while
// guaranteeing that only one drives the bus at a time.
//
// The core logic works like this:
//
// 1. If 'A' or 'B' asserts the o_cyc line, a bus cycle will begin,
// with acccess granted to whomever requested it.
// 2. If both 'A' and 'B' assert o_cyc at the same time, only 'A'
// will be granted the bus. (If the alternating parameter
// is set, A and B will alternate who gets the bus in
// this case.)
// 3. The bus will remain owned by whomever the bus was granted to
// until they deassert the o_cyc line.
// 4. At the end of a bus cycle, o_cyc is guaranteed to be
// deasserted (low) for one clock.
// 5. On the next clock, bus arbitration takes place again. If
// 'A' requests the bus, no matter how long 'B' was
// waiting, 'A' will then be granted the bus. (Unless
// again the alternating parameter is set, then the
// access is guaranteed to switch to B.)
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`define WBA_ALTERNATING
module wbarbiter(i_clk, i_rst,
// Bus A
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
// Bus B
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
// Both buses
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err);
// 18 bits will address one GB, 4 bytes at a time.
// 19 bits will allow the ability to address things other than just
// the 1GB of memory we are expecting.
parameter DW=32, AW=19;
// Wishbone doesn't use an i_ce signal. While it could, they dislike
// what it would (might) do to the synchronous reset signal, i_rst.
input wire i_clk, i_rst;
// Bus A
input wire i_a_cyc, i_a_stb, i_a_we;
input wire [(AW-1):0] i_a_adr;
input wire [(DW-1):0] i_a_dat;
input wire [(DW/8-1):0] i_a_sel;
output wire o_a_ack, o_a_stall, o_a_err;
// Bus B
input wire i_b_cyc, i_b_stb, i_b_we;
input wire [(AW-1):0] i_b_adr;
input wire [(DW-1):0] i_b_dat;
input wire [(DW/8-1):0] i_b_sel;
output wire o_b_ack, o_b_stall, o_b_err;
//
output wire o_cyc, o_stb, o_we;
output wire [(AW-1):0] o_adr;
output wire [(DW-1):0] o_dat;
output wire [(DW/8-1):0] o_sel;
input wire i_ack, i_stall, i_err;
// All the fancy stuff here is done with the three primary signals:
// o_cyc
// w_a_owner
// w_b_owner
// These signals are helped by r_cyc, r_a_owner, and r_b_owner.
// If you understand these signals, all else will fall into place.
// r_cyc just keeps track of the last o_cyc value. That way, on
// the next clock we can tell if we've had one non-cycle before
// starting another cycle. Specifically, no new cycles will be
// allowed to begin unless r_cyc=0.
reg r_cyc;
always @(posedge i_clk)
if (i_rst)
r_cyc <= 1'b0;
else
r_cyc <= o_cyc;
// Go high immediately (new cycle) if ...
// Previous cycle was low and *someone* is requesting a bus cycle
// Go low immadiately if ...
// We were just high and the owner no longer wants the bus
// WISHBONE Spec recommends no logic between a FF and the o_cyc
// This violates that spec. (Rec 3.15, p35)
wire w_a_owner, w_b_owner;
assign o_cyc = ((~r_cyc)&&((i_a_cyc)||(i_b_cyc))) || ((r_cyc)&&((w_a_owner)||(w_b_owner)));
// Register keeping track of the last owner, wire keeping track of the
// current owner allowing us to not lose a clock in arbitrating the
// first clock of the bus cycle
reg r_a_owner, r_b_owner;
`ifdef WBA_ALTERNATING
reg r_a_last_owner;
`endif
always @(posedge i_clk)
if (i_rst)
begin
r_a_owner <= 1'b0;
r_b_owner <= 1'b0;
end else begin
r_a_owner <= w_a_owner;
r_b_owner <= w_b_owner;
`ifdef WBA_ALTERNATING
if (w_a_owner)
r_a_last_owner <= 1'b1;
else if (w_b_owner)
r_a_last_owner <= 1'b0;
`endif
end
//
// If you are the owner, retain ownership until i_x_cyc is no
// longer asserted. Likewise, you cannot become owner until o_cyc
// is de-asserted for one cycle.
//
// 'A' is given arbitrary priority over 'B'
// 'A' may own the bus only if he wants it. When 'A' drops i_a_cyc,
// o_cyc must drop and so must w_a_owner on the same cycle.
// However, when 'A' asserts i_a_cyc, he can only capture the bus if
// it's had an idle cycle.
// The same is true for 'B' with one exception: if both contend for the
// bus on the same cycle, 'A' arbitrarily wins.
`ifdef WBA_ALTERNATING
assign w_a_owner = (i_a_cyc) // if A requests ownership, and either
&& ((r_a_owner) // A has already been recognized or
|| ((~r_cyc) // the bus is free and
&&((~i_b_cyc) // B has not requested, or if he
||(~r_a_last_owner)) )); // has, it's A's turn
assign w_b_owner = (i_b_cyc)&& ((r_b_owner) || ((~r_cyc)&&((~i_a_cyc)||(r_a_last_owner)) ));
`else
assign w_a_owner = (i_a_cyc)&& ((r_a_owner) || (~r_cyc) );
assign w_b_owner = (i_b_cyc)&& ((r_b_owner) || ((~r_cyc)&&(~i_a_cyc)) );
`endif
// Realistically, if neither master owns the bus, the output is a
// don't care. Thus we trigger off whether or not 'A' owns the bus.
// If 'B' owns it all we care is that 'A' does not. Likewise, if
// neither owns the bus than the values on the various lines are
// irrelevant. (This allows us to get two outputs per Xilinx 6-LUT)
assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb);
assign o_we = (w_a_owner) ? i_a_we : i_b_we;
assign o_adr = (w_a_owner) ? i_a_adr : i_b_adr;
assign o_dat = (w_a_owner) ? i_a_dat : i_b_dat;
assign o_sel = (w_a_owner) ? i_a_sel : i_b_sel;
// We cannot allow the return acknowledgement to ever go high if
// the master in question does not own the bus. Hence we force it
// low if the particular master doesn't own the bus.
assign o_a_ack = (w_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (w_b_owner) ? i_ack : 1'b0;
// Stall must be asserted on the same cycle the input master asserts
// the bus, if the bus isn't granted to him.
assign o_a_stall = (w_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (w_b_owner) ? i_stall : 1'b1;
//
//
assign o_a_err = (w_a_owner) ? i_err : 1'b0;
assign o_b_err = (w_b_owner) ? i_err : 1'b0;
endmodule
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dcache_core
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input outport_accept_i
,input outport_ack_i
,input outport_error_i
,input [ 31:0] outport_read_data_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output [ 3:0] outport_wr_o
,output outport_rd_o
,output [ 7:0] outport_len_o
,output [ 31:0] outport_addr_o
,output [ 31:0] outport_write_data_o
);
//-----------------------------------------------------------------
// This cache instance is 2 way set associative.
// The total size is 16KB.
// The replacement policy is a limited pseudo random scheme
// (between lines, toggling on line thrashing).
// The cache is a write back cache, with allocate on read and write.
//-----------------------------------------------------------------
// Number of ways
localparam DCACHE_NUM_WAYS = 2;
// Number of cache lines
localparam DCACHE_NUM_LINES = 256;
localparam DCACHE_LINE_ADDR_W = 8;
// Line size (e.g. 32-bytes)
localparam DCACHE_LINE_SIZE_W = 5;
localparam DCACHE_LINE_SIZE = 32;
localparam DCACHE_LINE_WORDS = 8;
// Request -> tag address mapping
localparam DCACHE_TAG_REQ_LINE_L = 5; // DCACHE_LINE_SIZE_W
localparam DCACHE_TAG_REQ_LINE_H = 12; // DCACHE_LINE_ADDR_W+DCACHE_LINE_SIZE_W-1
localparam DCACHE_TAG_REQ_LINE_W = 8; // DCACHE_LINE_ADDR_W
`define DCACHE_TAG_REQ_RNG DCACHE_TAG_REQ_LINE_H:DCACHE_TAG_REQ_LINE_L
// Tag fields
`define CACHE_TAG_ADDR_RNG 18:0
localparam CACHE_TAG_ADDR_BITS = 19;
localparam CACHE_TAG_DIRTY_BIT = CACHE_TAG_ADDR_BITS + 0;
localparam CACHE_TAG_VALID_BIT = CACHE_TAG_ADDR_BITS + 1;
localparam CACHE_TAG_DATA_W = CACHE_TAG_ADDR_BITS + 2;
// Tag compare bits
localparam DCACHE_TAG_CMP_ADDR_L = DCACHE_TAG_REQ_LINE_H + 1;
localparam DCACHE_TAG_CMP_ADDR_H = 32-1;
localparam DCACHE_TAG_CMP_ADDR_W = DCACHE_TAG_CMP_ADDR_H - DCACHE_TAG_CMP_ADDR_L + 1;
`define DCACHE_TAG_CMP_ADDR_RNG 31:13
// Address mapping example:
// 31 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
// |--------------| | | | | | | | | | | | | | | | |
// +--------------------+ +--------------------+ +------------+
// | Tag address. | | Line address | Address
// | | | | within line
// | | | |
// | | | |- DCACHE_TAG_REQ_LINE_L
// | | |- DCACHE_TAG_REQ_LINE_H
// | |- DCACHE_TAG_CMP_ADDR_L
// |- DCACHE_TAG_CMP_ADDR_H
//-----------------------------------------------------------------
// States
//-----------------------------------------------------------------
localparam STATE_W = 4;
localparam STATE_RESET = 4'd0;
localparam STATE_FLUSH_ADDR = 4'd1;
localparam STATE_FLUSH = 4'd2;
localparam STATE_LOOKUP = 4'd3;
localparam STATE_READ = 4'd4;
localparam STATE_WRITE = 4'd5;
localparam STATE_REFILL = 4'd6;
localparam STATE_EVICT = 4'd7;
localparam STATE_EVICT_WAIT = 4'd8;
localparam STATE_INVALIDATE = 4'd9;
localparam STATE_WRITEBACK = 4'd10;
// States
reg [STATE_W-1:0] next_state_r;
reg [STATE_W-1:0] state_q;
//-----------------------------------------------------------------
// Request buffer
//-----------------------------------------------------------------
reg [31:0] mem_addr_m_q;
reg [31:0] mem_data_m_q;
reg [3:0] mem_wr_m_q;
reg mem_rd_m_q;
reg [10:0] mem_tag_m_q;
reg mem_inval_m_q;
reg mem_writeback_m_q;
reg mem_flush_m_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
mem_addr_m_q <= 32'b0;
mem_data_m_q <= 32'b0;
mem_wr_m_q <= 4'b0;
mem_rd_m_q <= 1'b0;
mem_tag_m_q <= 11'b0;
mem_inval_m_q <= 1'b0;
mem_writeback_m_q <= 1'b0;
mem_flush_m_q <= 1'b0;
end
else if (mem_accept_o)
begin
mem_addr_m_q <= mem_addr_i;
mem_data_m_q <= mem_data_wr_i;
mem_wr_m_q <= mem_wr_i;
mem_rd_m_q <= mem_rd_i;
mem_tag_m_q <= mem_req_tag_i;
mem_inval_m_q <= mem_invalidate_i;
mem_writeback_m_q <= mem_writeback_i;
mem_flush_m_q <= mem_flush_i;
end
else if (mem_ack_o)
begin
mem_addr_m_q <= 32'b0;
mem_data_m_q <= 32'b0;
mem_wr_m_q <= 4'b0;
mem_rd_m_q <= 1'b0;
mem_tag_m_q <= 11'b0;
mem_inval_m_q <= 1'b0;
mem_writeback_m_q <= 1'b0;
mem_flush_m_q <= 1'b0;
end
reg mem_accept_r;
always @ *
begin
mem_accept_r = 1'b0;
if (state_q == STATE_LOOKUP)
begin
// Previous access missed - do not accept new requests
if ((mem_rd_m_q || (mem_wr_m_q != 4'b0)) && !tag_hit_any_m_w)
mem_accept_r = 1'b0;
// Write followed by read - detect writes to the same line, or addresses which alias in tag lookups
else if ((|mem_wr_m_q) && mem_rd_i && mem_addr_i[31:2] == mem_addr_m_q[31:2])
mem_accept_r = 1'b0;
else
mem_accept_r = 1'b1;
end
end
assign mem_accept_o = mem_accept_r;
// Tag comparison address
wire [DCACHE_TAG_CMP_ADDR_W-1:0] req_addr_tag_cmp_m_w = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
assign mem_resp_tag_o = mem_tag_m_q;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
reg [0:0] replace_way_q;
wire [ 3:0] pmem_wr_w;
wire pmem_rd_w;
wire [ 7:0] pmem_len_w;
wire pmem_last_w;
wire [ 31:0] pmem_addr_w;
wire [ 31:0] pmem_write_data_w;
wire pmem_accept_w;
wire pmem_ack_w;
wire pmem_error_w;
wire [ 31:0] pmem_read_data_w;
wire evict_way_w;
wire tag_dirty_any_m_w;
wire tag_hit_and_dirty_m_w;
reg flushing_q;
//-----------------------------------------------------------------
// TAG RAMS
//-----------------------------------------------------------------
reg [DCACHE_TAG_REQ_LINE_W-1:0] tag_addr_x_r;
reg [DCACHE_TAG_REQ_LINE_W-1:0] tag_addr_m_r;
// Tag RAM address
always @ *
begin
// Read Port
tag_addr_x_r = mem_addr_i[`DCACHE_TAG_REQ_RNG];
// Lookup
if (state_q == STATE_LOOKUP && (next_state_r == STATE_LOOKUP || next_state_r == STATE_WRITEBACK))
tag_addr_x_r = mem_addr_i[`DCACHE_TAG_REQ_RNG];
// Cache flush
else if (flushing_q)
tag_addr_x_r = flush_addr_q;
else
tag_addr_x_r = mem_addr_m_q[`DCACHE_TAG_REQ_RNG];
// Write Port
tag_addr_m_r = flush_addr_q;
// Cache flush
if (flushing_q || state_q == STATE_RESET)
tag_addr_m_r = flush_addr_q;
// Line refill / write
else
tag_addr_m_r = mem_addr_m_q[`DCACHE_TAG_REQ_RNG];
end
// Tag RAM write data
reg [CACHE_TAG_DATA_W-1:0] tag_data_in_m_r;
always @ *
begin
tag_data_in_m_r = {(CACHE_TAG_DATA_W){1'b0}};
// Cache flush
if (state_q == STATE_FLUSH || state_q == STATE_RESET || flushing_q)
tag_data_in_m_r = {(CACHE_TAG_DATA_W){1'b0}};
// Line refill
else if (state_q == STATE_REFILL)
begin
tag_data_in_m_r[CACHE_TAG_VALID_BIT] = 1'b1;
tag_data_in_m_r[CACHE_TAG_DIRTY_BIT] = 1'b0;
tag_data_in_m_r[`CACHE_TAG_ADDR_RNG] = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
end
// Invalidate - mark entry (if matching line) not valid (even if dirty...)
else if (state_q == STATE_INVALIDATE)
begin
tag_data_in_m_r[CACHE_TAG_VALID_BIT] = 1'b0;
tag_data_in_m_r[CACHE_TAG_DIRTY_BIT] = 1'b0;
tag_data_in_m_r[`CACHE_TAG_ADDR_RNG] = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
end
// Evict completion
else if (state_q == STATE_EVICT_WAIT)
begin
tag_data_in_m_r[CACHE_TAG_VALID_BIT] = 1'b1;
tag_data_in_m_r[CACHE_TAG_DIRTY_BIT] = 1'b0;
tag_data_in_m_r[`CACHE_TAG_ADDR_RNG] = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
end
// Write - mark entry as dirty
else if (state_q == STATE_WRITE || (state_q == STATE_LOOKUP && (|mem_wr_m_q)))
begin
tag_data_in_m_r[CACHE_TAG_VALID_BIT] = 1'b1;
tag_data_in_m_r[CACHE_TAG_DIRTY_BIT] = 1'b1;
tag_data_in_m_r[`CACHE_TAG_ADDR_RNG] = mem_addr_m_q[`DCACHE_TAG_CMP_ADDR_RNG];
end
end
// Tag RAM write enable (way 0)
reg tag0_write_m_r;
always @ *
begin
tag0_write_m_r = 1'b0;
// Cache flush (reset)
if (state_q == STATE_RESET)
tag0_write_m_r = 1'b1;
// Cache flush
else if (state_q == STATE_FLUSH)
tag0_write_m_r = !tag_dirty_any_m_w;
// Write - hit, mark as dirty
else if (state_q == STATE_LOOKUP && (|mem_wr_m_q))
tag0_write_m_r = tag0_hit_m_w;
// Write - write after refill
else if (state_q == STATE_WRITE)
tag0_write_m_r = (replace_way_q == 0);
// Write - mark entry as dirty
else if (state_q == STATE_EVICT_WAIT && pmem_ack_w)
tag0_write_m_r = (replace_way_q == 0);
// Line refill
else if (state_q == STATE_REFILL)
tag0_write_m_r = pmem_ack_w && pmem_last_w && (replace_way_q == 0);
// Invalidate - line matches address - invalidate
else if (state_q == STATE_INVALIDATE)
tag0_write_m_r = tag0_hit_m_w;
end
wire [CACHE_TAG_DATA_W-1:0] tag0_data_out_m_w;
dcache_core_tag_ram
u_tag0
(
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Read
.addr0_i(tag_addr_x_r),
.data0_o(tag0_data_out_m_w),
// Write
.addr1_i(tag_addr_m_r),
.data1_i(tag_data_in_m_r),
.wr1_i(tag0_write_m_r)
);
wire tag0_valid_m_w = tag0_data_out_m_w[CACHE_TAG_VALID_BIT];
wire tag0_dirty_m_w = tag0_data_out_m_w[CACHE_TAG_DIRTY_BIT];
wire [CACHE_TAG_ADDR_BITS-1:0] tag0_addr_bits_m_w = tag0_data_out_m_w[`CACHE_TAG_ADDR_RNG];
// Tag hit?
wire tag0_hit_m_w = tag0_valid_m_w ? (tag0_addr_bits_m_w == req_addr_tag_cmp_m_w) : 1'b0;
// Tag RAM write enable (way 1)
reg tag1_write_m_r;
always @ *
begin
tag1_write_m_r = 1'b0;
// Cache flush (reset)
if (state_q == STATE_RESET)
tag1_write_m_r = 1'b1;
// Cache flush
else if (state_q == STATE_FLUSH)
tag1_write_m_r = !tag_dirty_any_m_w;
// Write - hit, mark as dirty
else if (state_q == STATE_LOOKUP && (|mem_wr_m_q))
tag1_write_m_r = tag1_hit_m_w;
// Write - write after refill
else if (state_q == STATE_WRITE)
tag1_write_m_r = (replace_way_q == 1);
// Write - mark entry as dirty
else if (state_q == STATE_EVICT_WAIT && pmem_ack_w)
tag1_write_m_r = (replace_way_q == 1);
// Line refill
else if (state_q == STATE_REFILL)
tag1_write_m_r = pmem_ack_w && pmem_last_w && (replace_way_q == 1);
// Invalidate - line matches address - invalidate
else if (state_q == STATE_INVALIDATE)
tag1_write_m_r = tag1_hit_m_w;
end
wire [CACHE_TAG_DATA_W-1:0] tag1_data_out_m_w;
dcache_core_tag_ram
u_tag1
(
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Read
.addr0_i(tag_addr_x_r),
.data0_o(tag1_data_out_m_w),
// Write
.addr1_i(tag_addr_m_r),
.data1_i(tag_data_in_m_r),
.wr1_i(tag1_write_m_r)
);
wire tag1_valid_m_w = tag1_data_out_m_w[CACHE_TAG_VALID_BIT];
wire tag1_dirty_m_w = tag1_data_out_m_w[CACHE_TAG_DIRTY_BIT];
wire [CACHE_TAG_ADDR_BITS-1:0] tag1_addr_bits_m_w = tag1_data_out_m_w[`CACHE_TAG_ADDR_RNG];
// Tag hit?
wire tag1_hit_m_w = tag1_valid_m_w ? (tag1_addr_bits_m_w == req_addr_tag_cmp_m_w) : 1'b0;
wire tag_hit_any_m_w = 1'b0
| tag0_hit_m_w
| tag1_hit_m_w
;
assign tag_hit_and_dirty_m_w = 1'b0
| (tag0_hit_m_w & tag0_dirty_m_w)
| (tag1_hit_m_w & tag1_dirty_m_w)
;
assign tag_dirty_any_m_w = 1'b0
| (tag0_valid_m_w & tag0_dirty_m_w)
| (tag1_valid_m_w & tag1_dirty_m_w)
;
localparam EVICT_ADDR_W = 32 - DCACHE_LINE_SIZE_W;
reg evict_way_r;
reg [31:0] evict_data_r;
reg [EVICT_ADDR_W-1:0] evict_addr_r;
always @ *
begin
evict_way_r = 1'b0;
evict_addr_r = flushing_q ? {tag0_addr_bits_m_w, flush_addr_q} :
{tag0_addr_bits_m_w, mem_addr_m_q[`DCACHE_TAG_REQ_RNG]};
evict_data_r = data0_data_out_m_w;
case (replace_way_q)
1'd0:
begin
evict_way_r = tag0_valid_m_w && tag0_dirty_m_w;
evict_addr_r = flushing_q ? {tag0_addr_bits_m_w, flush_addr_q} :
{tag0_addr_bits_m_w, mem_addr_m_q[`DCACHE_TAG_REQ_RNG]};
evict_data_r = data0_data_out_m_w;
end
1'd1:
begin
evict_way_r = tag1_valid_m_w && tag1_dirty_m_w;
evict_addr_r = flushing_q ? {tag1_addr_bits_m_w, flush_addr_q} :
{tag1_addr_bits_m_w, mem_addr_m_q[`DCACHE_TAG_REQ_RNG]};
evict_data_r = data1_data_out_m_w;
end
endcase
end
assign evict_way_w = (flushing_q || !tag_hit_any_m_w) && evict_way_r;
wire [EVICT_ADDR_W-1:0] evict_addr_w = evict_addr_r;
wire [31:0] evict_data_w = evict_data_r;
//-----------------------------------------------------------------
// DATA RAMS
//-----------------------------------------------------------------
// Data addressing
localparam CACHE_DATA_ADDR_W = DCACHE_LINE_ADDR_W+DCACHE_LINE_SIZE_W-2;
reg [CACHE_DATA_ADDR_W-1:0] data_addr_x_r;
reg [CACHE_DATA_ADDR_W-1:0] data_addr_m_r;
reg [CACHE_DATA_ADDR_W-1:0] data_write_addr_q;
// Data RAM refill write address
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_write_addr_q <= {(CACHE_DATA_ADDR_W){1'b0}};
else if (state_q != STATE_REFILL && next_state_r == STATE_REFILL)
data_write_addr_q <= pmem_addr_w[CACHE_DATA_ADDR_W+2-1:2];
else if (state_q != STATE_EVICT && next_state_r == STATE_EVICT)
data_write_addr_q <= data_addr_m_r + 1;
else if (state_q == STATE_REFILL && pmem_ack_w)
data_write_addr_q <= data_write_addr_q + 1;
else if (state_q == STATE_EVICT && pmem_accept_w)
data_write_addr_q <= data_write_addr_q + 1;
// Data RAM address
always @ *
begin
data_addr_x_r = mem_addr_i[CACHE_DATA_ADDR_W+2-1:2];
data_addr_m_r = mem_addr_m_q[CACHE_DATA_ADDR_W+2-1:2];
// Line refill / evict
if (state_q == STATE_REFILL || state_q == STATE_EVICT)
begin
data_addr_x_r = data_write_addr_q;
data_addr_m_r = data_addr_x_r;
end
else if (state_q == STATE_FLUSH || state_q == STATE_RESET)
begin
data_addr_x_r = {flush_addr_q, {(DCACHE_LINE_SIZE_W-2){1'b0}}};
data_addr_m_r = data_addr_x_r;
end
else if (state_q != STATE_EVICT && next_state_r == STATE_EVICT)
begin
data_addr_x_r = {mem_addr_m_q[`DCACHE_TAG_REQ_RNG], {(DCACHE_LINE_SIZE_W-2){1'b0}}};
data_addr_m_r = data_addr_x_r;
end
// Lookup post refill
else if (state_q == STATE_READ)
begin
data_addr_x_r = mem_addr_m_q[CACHE_DATA_ADDR_W+2-1:2];
end
// Possible line update on write
else
data_addr_m_r = mem_addr_m_q[CACHE_DATA_ADDR_W+2-1:2];
end
// Data RAM write enable (way 0)
reg [3:0] data0_write_m_r;
always @ *
begin
data0_write_m_r = 4'b0;
if (state_q == STATE_REFILL)
data0_write_m_r = (pmem_ack_w && replace_way_q == 0) ? 4'b1111 : 4'b0000;
else if (state_q == STATE_WRITE || state_q == STATE_LOOKUP)
data0_write_m_r = mem_wr_m_q & {4{tag0_hit_m_w}};
end
wire [31:0] data0_data_out_m_w;
wire [31:0] data0_data_in_m_w = (state_q == STATE_REFILL) ? pmem_read_data_w : mem_data_m_q;
dcache_core_data_ram
u_data0
(
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Read
.addr0_i(data_addr_x_r),
.data0_i(32'b0),
.wr0_i(4'b0),
.data0_o(data0_data_out_m_w),
// Write
.addr1_i(data_addr_m_r),
.data1_i(data0_data_in_m_w),
.wr1_i(data0_write_m_r),
.data1_o()
);
// Data RAM write enable (way 1)
reg [3:0] data1_write_m_r;
always @ *
begin
data1_write_m_r = 4'b0;
if (state_q == STATE_REFILL)
data1_write_m_r = (pmem_ack_w && replace_way_q == 1) ? 4'b1111 : 4'b0000;
else if (state_q == STATE_WRITE || state_q == STATE_LOOKUP)
data1_write_m_r = mem_wr_m_q & {4{tag1_hit_m_w}};
end
wire [31:0] data1_data_out_m_w;
wire [31:0] data1_data_in_m_w = (state_q == STATE_REFILL) ? pmem_read_data_w : mem_data_m_q;
dcache_core_data_ram
u_data1
(
.clk0_i(clk_i),
.rst0_i(rst_i),
.clk1_i(clk_i),
.rst1_i(rst_i),
// Read
.addr0_i(data_addr_x_r),
.data0_i(32'b0),
.wr0_i(4'b0),
.data0_o(data1_data_out_m_w),
// Write
.addr1_i(data_addr_m_r),
.data1_i(data1_data_in_m_w),
.wr1_i(data1_write_m_r),
.data1_o()
);
//-----------------------------------------------------------------
// Flush counter
//-----------------------------------------------------------------
reg [DCACHE_TAG_REQ_LINE_W-1:0] flush_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
flush_addr_q <= {(DCACHE_TAG_REQ_LINE_W){1'b0}};
else if ((state_q == STATE_RESET) || (state_q == STATE_FLUSH && next_state_r == STATE_FLUSH_ADDR))
flush_addr_q <= flush_addr_q + 1;
else if (state_q == STATE_LOOKUP)
flush_addr_q <= {(DCACHE_TAG_REQ_LINE_W){1'b0}};
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
flushing_q <= 1'b0;
else if (state_q == STATE_LOOKUP && next_state_r == STATE_FLUSH_ADDR)
flushing_q <= 1'b1;
else if (state_q == STATE_FLUSH && next_state_r == STATE_LOOKUP)
flushing_q <= 1'b0;
reg flush_last_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
flush_last_q <= 1'b0;
else if (state_q == STATE_LOOKUP)
flush_last_q <= 1'b0;
else if (flush_addr_q == {(DCACHE_TAG_REQ_LINE_W){1'b1}})
flush_last_q <= 1'b1;
//-----------------------------------------------------------------
// Replacement Policy
//-----------------------------------------------------------------
// Using random replacement policy - this way we cycle through the ways
// when needing to replace a line.
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
replace_way_q <= 0;
else if (state_q == STATE_WRITE || state_q == STATE_READ)
replace_way_q <= replace_way_q + 1;
else if (flushing_q && tag_dirty_any_m_w && !evict_way_w && state_q != STATE_FLUSH_ADDR)
replace_way_q <= replace_way_q + 1;
else if (state_q == STATE_EVICT_WAIT && next_state_r == STATE_FLUSH_ADDR)
replace_way_q <= 0;
else if (state_q == STATE_FLUSH && next_state_r == STATE_LOOKUP)
replace_way_q <= 0;
else if (state_q == STATE_LOOKUP && next_state_r == STATE_FLUSH_ADDR)
replace_way_q <= 0;
else if (state_q == STATE_WRITEBACK)
begin
case (1'b1)
tag0_hit_m_w: replace_way_q <= 0;
tag1_hit_m_w: replace_way_q <= 1;
endcase
end
//-----------------------------------------------------------------
// Output Result
//-----------------------------------------------------------------
// Data output mux
reg [31:0] data_r;
always @ *
begin
data_r = data0_data_out_m_w;
case (1'b1)
tag0_hit_m_w: data_r = data0_data_out_m_w;
tag1_hit_m_w: data_r = data1_data_out_m_w;
endcase
end
assign mem_data_rd_o = data_r;
//-----------------------------------------------------------------
// Next State Logic
//-----------------------------------------------------------------
always @ *
begin
next_state_r = state_q;
case (state_q)
//-----------------------------------------
// STATE_RESET
//-----------------------------------------
STATE_RESET :
begin
// Final line checked
if (flush_last_q)
next_state_r = STATE_LOOKUP;
end
//-----------------------------------------
// STATE_FLUSH_ADDR
//-----------------------------------------
STATE_FLUSH_ADDR : next_state_r = STATE_FLUSH;
//-----------------------------------------
// STATE_FLUSH
//-----------------------------------------
STATE_FLUSH :
begin
// Dirty line detected - evict unless initial cache reset cycle
if (tag_dirty_any_m_w)
begin
// Evict dirty line - else wait for dirty way to be selected
if (evict_way_w)
next_state_r = STATE_EVICT;
end
// Final line checked, nothing dirty
else if (flush_last_q)
next_state_r = STATE_LOOKUP;
else
next_state_r = STATE_FLUSH_ADDR;
end
//-----------------------------------------
// STATE_LOOKUP
//-----------------------------------------
STATE_LOOKUP :
begin
// Previous access missed in the cache
if ((mem_rd_m_q || (mem_wr_m_q != 4'b0)) && !tag_hit_any_m_w)
begin
// Evict dirty line first
if (evict_way_w)
next_state_r = STATE_EVICT;
// Allocate line and fill
else
next_state_r = STATE_REFILL;
end
// Writeback a single line
else if (mem_writeback_i && mem_accept_o)
next_state_r = STATE_WRITEBACK;
// Flush whole cache
else if (mem_flush_i && mem_accept_o)
next_state_r = STATE_FLUSH_ADDR;
// Invalidate line (even if dirty)
else if (mem_invalidate_i && mem_accept_o)
next_state_r = STATE_INVALIDATE;
end
//-----------------------------------------
// STATE_REFILL
//-----------------------------------------
STATE_REFILL :
begin
// End of refill
if (pmem_ack_w && pmem_last_w)
begin
// Refill reason was write
if (mem_wr_m_q != 4'b0)
next_state_r = STATE_WRITE;
// Refill reason was read
else
next_state_r = STATE_READ;
end
end
//-----------------------------------------
// STATE_WRITE/READ
//-----------------------------------------
STATE_WRITE, STATE_READ :
begin
next_state_r = STATE_LOOKUP;
end
//-----------------------------------------
// STATE_EVICT
//-----------------------------------------
STATE_EVICT :
begin
// End of evict, wait for write completion
if (pmem_accept_w && pmem_last_w)
next_state_r = STATE_EVICT_WAIT;
end
//-----------------------------------------
// STATE_EVICT_WAIT
//-----------------------------------------
STATE_EVICT_WAIT :
begin
// Single line writeback
if (pmem_ack_w && mem_writeback_m_q)
next_state_r = STATE_LOOKUP;
// Evict due to flush
else if (pmem_ack_w && flushing_q)
next_state_r = STATE_FLUSH_ADDR;
// Write ack, start re-fill now
else if (pmem_ack_w)
next_state_r = STATE_REFILL;
end
//-----------------------------------------
// STATE_WRITEBACK: Writeback a cache line
//-----------------------------------------
STATE_WRITEBACK:
begin
// Line is dirty - write back to memory
if (tag_hit_and_dirty_m_w)
next_state_r = STATE_EVICT;
// Line not dirty, carry on
else
next_state_r = STATE_LOOKUP;
end
//-----------------------------------------
// STATE_INVALIDATE: Invalidate a cache line
//-----------------------------------------
STATE_INVALIDATE:
begin
next_state_r = STATE_LOOKUP;
end
default:
;
endcase
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_RESET;
else
state_q <= next_state_r;
reg mem_ack_r;
always @ *
begin
mem_ack_r = 1'b0;
if (state_q == STATE_LOOKUP)
begin
// Normal hit - read or write
if ((mem_rd_m_q || (mem_wr_m_q != 4'b0)) && tag_hit_any_m_w)
mem_ack_r = 1'b1;
// Flush, invalidate or writeback
else if (mem_flush_m_q || mem_inval_m_q || mem_writeback_m_q)
mem_ack_r = 1'b1;
end
end
assign mem_ack_o = mem_ack_r;
//-----------------------------------------------------------------
// AXI Request
//-----------------------------------------------------------------
reg pmem_rd_q;
reg pmem_wr0_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_rd_q <= 1'b0;
else if (pmem_rd_w)
pmem_rd_q <= ~pmem_accept_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_wr0_q <= 1'b0;
else if (state_q != STATE_EVICT && next_state_r == STATE_EVICT)
pmem_wr0_q <= 1'b1;
else if (pmem_accept_w)
pmem_wr0_q <= 1'b0;
reg [7:0] pmem_len_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_len_q <= 8'b0;
else if (state_q != STATE_EVICT && next_state_r == STATE_EVICT)
pmem_len_q <= 8'd7;
else if (pmem_rd_w && pmem_accept_w)
pmem_len_q <= pmem_len_w;
else if (state_q == STATE_REFILL && pmem_ack_w)
pmem_len_q <= pmem_len_q - 8'd1;
else if (state_q == STATE_EVICT && pmem_accept_w)
pmem_len_q <= pmem_len_q - 8'd1;
assign pmem_last_w = (pmem_len_q == 8'd0);
reg [31:0] pmem_addr_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_addr_q <= 32'b0;
else if (|pmem_len_w && pmem_accept_w)
pmem_addr_q <= pmem_addr_w + 32'd4;
else if (pmem_accept_w)
pmem_addr_q <= pmem_addr_q + 32'd4;
//-----------------------------------------------------------------
// Skid buffer for write data
//-----------------------------------------------------------------
reg [3:0] pmem_wr_q;
reg [31:0] pmem_write_data_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_wr_q <= 4'b0;
else if ((|pmem_wr_w) && !pmem_accept_w)
pmem_wr_q <= pmem_wr_w;
else if (pmem_accept_w)
pmem_wr_q <= 4'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
pmem_write_data_q <= 32'b0;
else if (!pmem_accept_w)
pmem_write_data_q <= pmem_write_data_w;
//-----------------------------------------------------------------
// AXI Error Handling
//-----------------------------------------------------------------
reg error_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
error_q <= 1'b0;
else if (pmem_ack_w && pmem_error_w)
error_q <= 1'b1;
else if (mem_ack_o)
error_q <= 1'b0;
assign mem_error_o = error_q;
//-----------------------------------------------------------------
// Outport
//-----------------------------------------------------------------
wire refill_request_w = (state_q != STATE_REFILL && next_state_r == STATE_REFILL);
wire evict_request_w = (state_q == STATE_EVICT) && (evict_way_w || mem_writeback_m_q);
// AXI Read channel
assign pmem_rd_w = (refill_request_w || pmem_rd_q);
assign pmem_wr_w = (evict_request_w || (|pmem_wr_q)) ? 4'hF : 4'b0;
assign pmem_addr_w = (|pmem_len_w) ?
pmem_rd_w ? {mem_addr_m_q[31:DCACHE_LINE_SIZE_W], {(DCACHE_LINE_SIZE_W){1'b0}}} :
{evict_addr_w, {(DCACHE_LINE_SIZE_W){1'b0}}} :
pmem_addr_q;
assign pmem_len_w = (refill_request_w || pmem_rd_q || (state_q == STATE_EVICT && pmem_wr0_q)) ? 8'd7 : 8'd0;
assign pmem_write_data_w = (|pmem_wr_q) ? pmem_write_data_q : evict_data_w;
assign outport_wr_o = pmem_wr_w;
assign outport_rd_o = pmem_rd_w;
assign outport_len_o = pmem_len_w;
assign outport_addr_o = pmem_addr_w;
assign outport_write_data_o = pmem_write_data_w;
assign pmem_accept_w = outport_accept_i;
assign pmem_ack_w = outport_ack_i;
assign pmem_error_w = outport_error_i;
assign pmem_read_data_w = outport_read_data_i;
//-------------------------------------------------------------------
// Debug
//-------------------------------------------------------------------
`ifdef verilator
/* verilator lint_off WIDTH */
reg [79:0] dbg_state;
always @ *
begin
dbg_state = "-";
case (state_q)
STATE_RESET:
dbg_state = "RESET";
STATE_FLUSH_ADDR:
dbg_state = "FLUSH_ADDR";
STATE_FLUSH:
dbg_state = "FLUSH";
STATE_LOOKUP:
dbg_state = "LOOKUP";
STATE_READ:
dbg_state = "READ";
STATE_WRITE:
dbg_state = "WRITE";
STATE_REFILL:
dbg_state = "REFILL";
STATE_EVICT:
dbg_state = "EVICT";
STATE_EVICT_WAIT:
dbg_state = "EVICT_WAIT";
STATE_INVALIDATE:
dbg_state = "INVAL";
STATE_WRITEBACK:
dbg_state = "WRITEBACK";
default:
;
endcase
end
/* verilator lint_on WIDTH */
`endif
endmodule
|
module F_D_M_tb;
/****************OPCODES******************/
// R-Type FUNC Codes
parameter ADD = 6'b100000; //ADD;
parameter ADDU = 6'b100001; //ADDU;
parameter SUB = 6'b100010; //SUB;
parameter SUBU = 6'b100011; //SUBU;
parameter MULT = 6'b011000; //MULT;
parameter MULTU = 6'b011001; //MULTU;
parameter DIV = 6'b011010; //DIV;
parameter DIVU = 6'b011011; //DIVU;
parameter MFHI = 6'b010000; //MFHI;
parameter MFLO = 6'b010010; //MFLO;
parameter SLT = 6'b101010; //SLT;
parameter SLTU = 6'b101011; //SLTU;
parameter SLL = 6'b000000; //SLL;
parameter SLLV = 6'b000100; //SLLV;
parameter SRL = 6'b000010; //SRL;
parameter SRLV = 6'b000110; //SRLV;
parameter SRA = 6'b000011; //SRA;
parameter SRAV = 6'b000111; //SRAV;
parameter AND = 6'b100100; //AND;
parameter OR = 6'b100101; //OR;
parameter XOR = 6'b100110; //XOR;
parameter NOR = 6'b100111; //NOR
parameter JALR = 6'b001001; //JALR;
parameter JR = 6'b001000; //JR;
// MUL R-TYPE Opcode
parameter MUL_OP = 6'b011100; //MUL OPCODE
parameter MUL_FUNC = 6'b000010; //MUL FUNCTION CODE
// I-Type Opcodes
parameter ADDI = 6'b001000; //ADDI (LI)
parameter ADDIU = 6'b001001; //ADDIU
parameter SLTI = 6'b001010; //SLTI
parameter SLTIU = 6'b001011; //SLTIU
parameter ORI = 6'b001101; //ORI
parameter XORI = 6'b001110; //XORI
parameter LW = 6'b100011; //LW
parameter SW = 6'b101011; //SW
parameter LB = 6'b100000; //LB
parameter LUI = 6'b001111; //LUI
parameter SB = 6'b101000; //SB
parameter LBU = 6'b100100; //LBU
parameter BEQ = 6'b000100; //BEQ
parameter BNE = 6'b000101; //BNE
parameter BGTZ = 6'b000111; //BGTZ
parameter BLEZ = 6'b000110; //BLEZ
// REGIMM Opcodes
parameter BLTZ = 5'b00000; // BLTZ
parameter BGEZ = 5'b00001; // BGEZ
// J-Type Opcodes
parameter J = 6'b000010;
parameter JAL = 6'b000011;
// Other
parameter NOP = 6'b000000;
parameter RTYPE = 6'b000000;
/******************************************/
// Constants
parameter data_width = 32;
parameter address_width = 32;
parameter depth = 1048576;
parameter bytes_in_word = 4-1; // -1 for 0 based indexed
parameter bits_in_bytes = 8-1; // -1 for 0 based indexed
parameter BYTE = 8;
parameter start_addr = 32'h80020000;
// Input Ports
reg clock;
reg [address_width-1:0] address;
reg [data_width-1:0] data_in;
reg [1:0] access_size;
reg rw;
reg enable;
reg enable_fetch;
reg enable_decode;
reg enable_execute;
reg [31:0] pc_decode, insn_decode;
reg [31:0] pc_execute, insn_execute, imm_execute, rsData_execute, rtData_execute;
reg [4:0] saData_execute;
reg [5:0] ALUOp_execute;
reg we_regfile;
reg stall;
reg [31:0] dVal_regfile;
// Output Ports
wire busy;
wire [data_width-1:0] data_out;
wire [31:0] pc_fetch;
wire [5:0] opcode_out;
wire [4:0] rs_out;
wire [4:0] rt_out;
wire [4:0] rd_out;
wire [4:0] sa_out;
wire [5:0] func_out;
wire [25:0] imm_out;
wire [31:0] pc_out;
wire [31:0] insn_decode_out;
wire [31:0] rsOut_regfile;
wire [31:0] rtOut_regfile;
wire [31:0] imm_out_sx_decode;
wire rw_fetch;
wire [31:0] access_size_fetch;
wire [31:0] dataOut_execute;
wire branch_taken_execute;
wire [5:0] ALUOp_decode;
// fileIO stuff
integer fd;
integer scan_fd;
integer status_read, status_write;
integer sscanf_ret;
integer words_read;
integer words_written;
integer words_fetched;
integer words_decoded;
integer words_executed;
integer words_run;
integer words_processed;
integer fetch_not_enabled;
integer decode_not_enabled;
integer execute_not_enabled;
reg [31:0] line;
// testbench registers
reg [5:0] opcode_out_tb;
reg [4:0] rs_out_tb;
reg [4:0] rt_out_tb;
reg [4:0] rd_out_tb;
reg [4:0] sa_out_tb;
reg [5:0] func_out_tb;
reg [25:0] imm_out_tb;
reg [31:0] pc_out_tb;
reg [31:0] insn_out_tb;
reg [31:0] dataOut_execute_tb;
reg branch_taken_tb;
reg [31:0] pc_from_fetch_temp;
reg [31:0] pc_from_decode_temp;
reg [31:0] insn_execute_temp;
reg [31:0] rsOut_regfile_tb;
reg [31:0] rtOut_regfile_tb;
reg [31:0] imm_out_sx_decode_tb;
// Instantiate the memory module.
memory M0 (
.clock (clock),
.address (address),
.data_in (data_in),
.access_size (access_size),
.rw (rw),
.enable (enable),
.busy (busy),
.data_out (data_out)
);
// Instantiate the fetch module.
fetch F0 (
.clock (clock),
.pc (pc_fetch),
.rw (rw_fetch),
.stall (stall),
.access_size (access_size_fetch),
.enable_fetch (enable_fetch)
);
// Instantiate the decode module.
decode D0 (
.clock (clock),
.insn (insn_decode),
.pc (pc_decode),
.opcode_out (opcode_out),
.rs_out (rs_out),
.rt_out (rt_out),
.rd_out (rd_out),
.sa_out (sa_out),
.imm_out (imm_out),
.func_out (func_out),
.pc_out (pc_out),
.insn_out (insn_decode_out),
.enable_decode (enable_decode),
.ALUOp (ALUOp_decode),
.rsOut_regfile (rsOut_regfile),
.rtOut_regfile (rtOut_regfile),
.dVal_regfile (dVal_regfile),
.we_regfile (we_regfile),
.imm_out_sx (imm_out_sx_decode)
);
// Instantiate the execute module.
alu X0 (
.clock (clock),
.enable_execute (enable_execute),
.pc (pc_execute),
.insn (insn_execute),
.rsData (rsData_execute),
.rtData (rtData_execute),
.saData (saData_execute),
.ALUOp (ALUOp_execute),
.immSXData (imm_execute),
.dataOut (dataOut_execute),
.branch_taken (branch_taken_execute)
);
initial begin
fd = $fopen("SimpleAdd.x", "r");
if (!fd)
$display("Could not open");
clock = 0;
address = start_addr;
scan_fd = $fscanf(fd, "%x", data_in);
access_size = 2'b0_0;
enable = 1;
rw = 0; // Start writing first.
words_read = 0;
words_written = 1;
words_fetched = 0;
words_decoded = 0;
words_executed = 0;
words_processed = 0;
words_run = 0;
fetch_not_enabled = 1;
decode_not_enabled = 1;
execute_not_enabled = 1;
stall = 0;
end
always @(posedge clock) begin: POPULATE
if (rw == 0) begin
enable = 1;
//rw = 0;
scan_fd = $fscanf(fd, "%x", line);
if (!$feof(fd)) begin
data_in = line;
$display("line = %x", data_in);
address = address + 4;
words_written = words_written + 1;
end
else begin: ENDWRITE
rw <= 1;
address <= 32'h80020000;
//enable_fetch <= 1;
stall = 0;
end
end
if (rw == 1 && fetch_not_enabled == 1) begin : ENABLEFETCH
//address <= 32'h80020000;
//pc_decode <= pc_fetch;
enable_fetch <= 1;
fetch_not_enabled = 0;
end
if (enable_fetch && (words_fetched <= words_written)) begin : FETCHSTAGE
address = pc_fetch;
insn_decode <= data_out;
pc_from_fetch_temp <= pc_fetch;
pc_decode = pc_from_fetch_temp;
words_fetched <= words_fetched + 1;
//enable_decode <= 1;
end
if ((rw_fetch == 1) && (decode_not_enabled == 1)) begin : ENABLEDECODE
//address <= 32'h80020000;
enable_decode <= 1;
decode_not_enabled = 0;
end
if (enable_decode && (words_decoded <= words_written)) begin : DECODESTAGE
//pc_decode <= pc_fetch;
//pc_decode = pc_from_fetch_temp;
opcode_out_tb = opcode_out;
rs_out_tb = rs_out;
rt_out_tb = rt_out;
rd_out_tb = rd_out;
sa_out_tb = sa_out;
func_out_tb = func_out;
imm_out_tb = imm_out;
pc_out_tb = pc_out;
insn_out_tb = insn_decode_out;
rsOut_regfile_tb = rsOut_regfile;
rtOut_regfile_tb = rtOut_regfile;
imm_out_sx_decode_tb = imm_out_sx_decode;
pc_from_decode_temp <= pc_out;
//pc_execute = pc_from_decode_temp;
insn_execute_temp <= insn_decode;
//insn_execute = insn_execute_temp;
enable_execute <= 1;
words_decoded <= words_decoded + 1;
if (opcode_out_tb == 6'b000000 && rs_out_tb == 5'b00000 && rt_out_tb == 5'b00000 && rd_out_tb == 5'b00000 && sa_out_tb == 5'b00000 && func_out_tb == 6'b000000) begin
$display("%x:\t%x\tNOP", pc_out_tb, insn_out_tb);
end else if (opcode_out_tb == RTYPE || opcode_out_tb == MUL_OP) begin
// INSN is R-TYPE (including MUL, which has a non-zer0 opcode)
case (func_out_tb)
ADD: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tADD RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
ADDU: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tADDU RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SUB: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSUB RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SUBU: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSUBU RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
MUL_FUNC: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tMUL RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
MULT: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tMULT RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
MULTU: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tMULTU RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
DIV: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tDIV RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
DIVU: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tDIVU RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
MFHI: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tMFHI RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
MFLO: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tMFLO RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SLT: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSLT RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SLTU: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSLTU RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SLL: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSLL RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SLLV: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSLLV RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SRL: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSRL RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SRLV: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSRLV RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SRA: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSRA RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
SRAV: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSRAV RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
AND: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tAND RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
OR: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tOR RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
XOR: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tXOR RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
NOR: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tNOR RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
JALR: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tJALR RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
JR: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tJR RS=%b RT=%b RD=%b SA=%b rsOut_regfile=%b rtOut_regfile=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, rsOut_regfile_tb, rtOut_regfile_tb);
end
end
endcase
end else if (opcode_out_tb != 6'b000000 && opcode_out_tb[5:1] != 5'b00001) begin
// INSN is I-TYPE
case (opcode_out_tb)
ADDI: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tADDI RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
ADDIU: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tADDIU RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
SLTI: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSLTI RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
SLTIU: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSLTIU RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
ORI: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tORI RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
XORI: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tXORI RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
LW: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tLW RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
SW: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSW RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
LB: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tLB RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
LUI: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tLUI RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
SB: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tSB RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
LBU: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tLBU RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
BEQ: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tBEQ RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
BNE: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tBNE RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
BGTZ: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tBGTZ RS=%b RT=%b rsOut_regfile=%b IMM=%b", pc_out_tb, insn_out_tb, rs_out_tb, rt_out_tb, rsOut_regfile_tb, imm_out_tb[25:10]);
end
end
endcase
end else if (opcode_out_tb[5:1] == 5'b00001) begin
// INSN is J-Type
case (opcode_out_tb)
J: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tJ IMM=%b", pc_out_tb, insn_out_tb, imm_out_tb);
end
end
JAL: begin
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("%x:\t%x\tJAL IMM=%b", pc_out_tb, insn_out_tb, imm_out_tb);
end
end
endcase
end else
if((words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_processed < words_written)) begin
words_processed = words_processed + 1;
$display("PC=%x INSN=%x OPCODE=%b RS/BASE=%b RT=%b RD=%b SA/OFFSET=%b IMM=%b FUNC=%b", pc_out_tb, insn_out_tb, opcode_out_tb, rs_out_tb, rt_out_tb, rd_out_tb, sa_out_tb, imm_out_tb, func_out_tb);
end
end
if (words_decoded > 0) begin : ENABLEEXECUTE
//enable_execute = 1;
execute_not_enabled = 0;
we_regfile <= 1;
end
if (enable_execute == 1 && execute_not_enabled == 0 && words_executed <= words_written) begin : EXECUTESTAGE
dataOut_execute_tb = dataOut_execute;
branch_taken_tb = branch_taken_execute;
pc_execute = pc_from_decode_temp;
rsData_execute <= rsOut_regfile;
rtData_execute <= rtOut_regfile;
saData_execute <= sa_out;
imm_execute <= imm_out_sx_decode;
ALUOp_execute <= ALUOp_decode;
insn_execute <= insn_execute_temp;
dVal_regfile <= dataOut_execute;
we_regfile <= 0;
words_executed <= words_executed + 1;
if((words_executed > 0) && (words_decoded > 0) && (words_fetched > 0) && enable_fetch && enable_decode && (words_run < words_written)) begin
words_run = words_run + 1;
if (branch_taken_tb == 1) begin
$display("%x INSN=%x ALUOp_execute=%b DATAOUT=%x branch_taken=%b", pc_execute, insn_execute, ALUOp_execute, dataOut_execute_tb, branch_taken_tb);
end else begin
$display("%x INSN=%x ALUOp_execute=%b DATAOUT=%x branch_taken=NA", pc_execute, insn_execute, ALUOp_execute, dataOut_execute_tb);
end
end
end
end
always
#5 clock = ! clock;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.68d
// \ \ Application: netgen
// / / Filename: add13bit.v
// /___/ /\ Timestamp: Fri Aug 29 10:36:02 2014
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog "C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/lab2_part2/ipcore_dir/tmp/_cg/add13bit.ngc" "C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/lab2_part2/ipcore_dir/tmp/_cg/add13bit.v"
// Device : 3s50cp132-5
// Input file : C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/lab2_part2/ipcore_dir/tmp/_cg/add13bit.ngc
// Output file : C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/lab2_part2/ipcore_dir/tmp/_cg/add13bit.v
// # of Modules : 1
// Design Name : add13bit
// Xilinx : C:\Xilinx\14.6\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module add13bit (
s, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
output [12 : 0] s;
input [12 : 0] a;
input [12 : 0] b;
// synthesis translate_off
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \blk00000001/sig00000031 ;
wire \blk00000001/sig00000030 ;
wire \blk00000001/sig0000002f ;
wire \blk00000001/sig0000002e ;
wire \blk00000001/sig0000002d ;
wire \blk00000001/sig0000002c ;
wire \blk00000001/sig0000002b ;
wire \blk00000001/sig0000002a ;
wire \blk00000001/sig00000029 ;
wire \blk00000001/sig0000001b ;
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000028 (
.I0(b[0]),
.I1(a[0]),
.O(\blk00000001/sig00000035 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000027 (
.I0(b[1]),
.I1(a[1]),
.O(\blk00000001/sig00000039 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000026 (
.I0(b[2]),
.I1(a[2]),
.O(\blk00000001/sig0000003a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000025 (
.I0(b[3]),
.I1(a[3]),
.O(\blk00000001/sig0000003b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000024 (
.I0(b[4]),
.I1(a[4]),
.O(\blk00000001/sig0000003c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000023 (
.I0(b[5]),
.I1(a[5]),
.O(\blk00000001/sig0000003d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000022 (
.I0(b[6]),
.I1(a[6]),
.O(\blk00000001/sig0000003e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000021 (
.I0(b[7]),
.I1(a[7]),
.O(\blk00000001/sig0000003f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000020 (
.I0(b[8]),
.I1(a[8]),
.O(\blk00000001/sig00000040 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001f (
.I0(b[9]),
.I1(a[9]),
.O(\blk00000001/sig00000041 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001e (
.I0(b[10]),
.I1(a[10]),
.O(\blk00000001/sig00000036 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001d (
.I0(b[11]),
.I1(a[11]),
.O(\blk00000001/sig00000037 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001c (
.I0(b[12]),
.I1(a[12]),
.O(\blk00000001/sig00000038 )
);
MUXCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig0000001b ),
.DI(a[0]),
.S(\blk00000001/sig00000035 ),
.O(\blk00000001/sig00000029 )
);
XORCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig0000001b ),
.LI(\blk00000001/sig00000035 ),
.O(s[0])
);
XORCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig0000002b ),
.LI(\blk00000001/sig00000038 ),
.O(s[12])
);
MUXCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig00000029 ),
.DI(a[1]),
.S(\blk00000001/sig00000039 ),
.O(\blk00000001/sig0000002c )
);
XORCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig00000029 ),
.LI(\blk00000001/sig00000039 ),
.O(s[1])
);
MUXCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig0000002c ),
.DI(a[2]),
.S(\blk00000001/sig0000003a ),
.O(\blk00000001/sig0000002d )
);
XORCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig0000002c ),
.LI(\blk00000001/sig0000003a ),
.O(s[2])
);
MUXCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig0000002d ),
.DI(a[3]),
.S(\blk00000001/sig0000003b ),
.O(\blk00000001/sig0000002e )
);
XORCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig0000002d ),
.LI(\blk00000001/sig0000003b ),
.O(s[3])
);
MUXCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig0000002e ),
.DI(a[4]),
.S(\blk00000001/sig0000003c ),
.O(\blk00000001/sig0000002f )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig0000002e ),
.LI(\blk00000001/sig0000003c ),
.O(s[4])
);
MUXCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig0000002f ),
.DI(a[5]),
.S(\blk00000001/sig0000003d ),
.O(\blk00000001/sig00000030 )
);
XORCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig0000003d ),
.O(s[5])
);
MUXCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig00000030 ),
.DI(a[6]),
.S(\blk00000001/sig0000003e ),
.O(\blk00000001/sig00000031 )
);
XORCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig00000030 ),
.LI(\blk00000001/sig0000003e ),
.O(s[6])
);
MUXCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig00000031 ),
.DI(a[7]),
.S(\blk00000001/sig0000003f ),
.O(\blk00000001/sig00000032 )
);
XORCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig00000031 ),
.LI(\blk00000001/sig0000003f ),
.O(s[7])
);
MUXCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig00000032 ),
.DI(a[8]),
.S(\blk00000001/sig00000040 ),
.O(\blk00000001/sig00000033 )
);
XORCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig00000032 ),
.LI(\blk00000001/sig00000040 ),
.O(s[8])
);
MUXCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig00000033 ),
.DI(a[9]),
.S(\blk00000001/sig00000041 ),
.O(\blk00000001/sig00000034 )
);
XORCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig00000033 ),
.LI(\blk00000001/sig00000041 ),
.O(s[9])
);
MUXCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig00000034 ),
.DI(a[10]),
.S(\blk00000001/sig00000036 ),
.O(\blk00000001/sig0000002a )
);
XORCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig00000034 ),
.LI(\blk00000001/sig00000036 ),
.O(s[10])
);
MUXCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig0000002a ),
.DI(a[11]),
.S(\blk00000001/sig00000037 ),
.O(\blk00000001/sig0000002b )
);
XORCY \blk00000001/blk00000003 (
.CI(\blk00000001/sig0000002a ),
.LI(\blk00000001/sig00000037 ),
.O(s[11])
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig0000001b )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_4_V
`define SKY130_FD_SC_LS__O22AI_4_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_4_V
|
`include "senior_defines.vh"
module combined_agu
#(parameter nat_w = `SENIOR_NATIVE_WIDTH,
parameter ctrl_w = `AGU_CTRL_WIDTH,
parameter adr_w = `SENIOR_ADDRESS_WIDTH,
parameter spr_dat_w = `SPR_DATA_BUS_WIDTH,
parameter spr_adr_w = `SPR_ADR_BUS_WIDTH,
parameter spr_group = `SPR_AGU_GROUP)
(
input wire clk_i,
input wire reset_i,
input wire [ctrl_w-1:0] ctrl_i,
input wire [nat_w-1:0] id_data_bus_i,
input wire [nat_w-1:0] rf_opa_bus_i,
output reg [adr_w-1:0] dm0_address_o,
output wire dm0_wren_o,
output reg [adr_w-1:0] dm1_address_o,
output wire dm1_wren_o,
input wire [spr_dat_w-1:0] spr_dat_i,
input wire [spr_adr_w-1:0] spr_adr_i,
input wire spr_wren_i,
output reg [spr_dat_w-1:0] spr_dat_o
);
reg [adr_w-1:0] ar_rf [3:0];
reg [nat_w-1:0] btm_rf [1:0];
reg [nat_w-1:0] top_rf [1:0];
reg [nat_w-1:0] stp_rf [1:0];
reg [adr_w-1:0] sp;
reg [2:0] bitrev_rf;
reg [adr_w-1:0] ar0_data_out;
reg [adr_w-1:0] ar1_data_out;
wire [nat_w-1:0] btm_o_dat_a;
wire [nat_w-1:0] btm_o_dat_b;
wire [nat_w-1:0] top_o_dat_a;
wire [nat_w-1:0] top_o_dat_b;
wire [nat_w-1:0] stp_o_dat_a;
wire [nat_w-1:0] stp_o_dat_b;
reg [1:0] spr_sel;
reg spr_ar_wren;
reg spr_top_wren;
reg spr_btm_wren;
reg spr_stp_wren;
reg spr_top_read;
reg spr_btm_read;
reg spr_stp_read;
reg spr_bitrev_wren;
reg spr_sp_wren;
//Need to do like this to be able to synthesize, bug in xst
wire [adr_w-1:0] ar_rf0;
wire [adr_w-1:0] ar_rf1;
wire [adr_w-1:0] ar_rf2;
wire [adr_w-1:0] ar_rf3;
assign ar_rf0 = ar_rf[0];
assign ar_rf1 = ar_rf[1];
assign ar_rf2 = ar_rf[2];
assign ar_rf3 = ar_rf[3];
always@(*) begin
spr_sel = 0;
spr_dat_o = 0;
spr_ar_wren = 0;
spr_top_wren = 0;
spr_btm_wren = 0;
spr_stp_wren = 0;
spr_top_read = 0;
spr_btm_read = 0;
spr_stp_read = 0;
spr_bitrev_wren = 0;
spr_sp_wren =0;
case(spr_adr_i)
(spr_group+`AGU_SPR_AR0): begin
spr_dat_o = ar_rf0;
spr_sel = 0;
spr_ar_wren = spr_wren_i;
end
(spr_group+`AGU_SPR_AR1): begin
spr_dat_o = ar_rf1;
spr_sel = 1;
spr_ar_wren = spr_wren_i;
end
(spr_group+`AGU_SPR_AR2): begin
spr_dat_o = ar_rf2;
spr_sel = 2;
spr_ar_wren = spr_wren_i;
end
(spr_group+`AGU_SPR_AR3): begin
spr_dat_o = ar_rf3;
spr_sel = 3;
spr_ar_wren = spr_wren_i;
end
(spr_group+`AGU_SPR_TOP0): begin
spr_dat_o = top_o_dat_a;
spr_sel = 0;
spr_top_wren = spr_wren_i;
spr_top_read = 1;
end
(spr_group+`AGU_SPR_TOP1): begin
spr_dat_o = top_o_dat_a;
spr_sel = 1;
spr_top_wren = spr_wren_i;
spr_top_read = 1;
end
(spr_group+`AGU_SPR_BTM0): begin
spr_dat_o = btm_o_dat_a;
spr_sel = 0;
spr_btm_wren = spr_wren_i;
spr_btm_read = 1;
end
(spr_group+`AGU_SPR_BTM1): begin
spr_dat_o = btm_o_dat_a;
spr_sel = 1;
spr_btm_wren = spr_wren_i;
spr_btm_read = 1;
end
(spr_group+`AGU_SPR_STP0): begin
spr_dat_o = stp_o_dat_a;
spr_sel = 0;
spr_stp_wren = spr_wren_i;
spr_stp_read = 1;
end
(spr_group+`AGU_SPR_STP1): begin
spr_dat_o = stp_o_dat_a;
spr_sel = 1;
spr_stp_wren = spr_wren_i;
spr_stp_read = 1;
end
(spr_group+`AGU_SPR_BITREV): begin
spr_dat_o = bitrev_rf;
spr_bitrev_wren = spr_wren_i;
end
(spr_group+`AGU_SPR_SP): begin
spr_dat_o = sp;
spr_sp_wren=spr_wren_i;
end
endcase // case(spr_adr_i)
end
wire ar0_rf_wren;
wire ar1_rf_wren;
wire [1:0] ar0_rf_adr;
wire [1:0] ar1_rf_adr;
wire [1:0] agu_ar0_sel;
wire [1:0] agu_ar1_sel;
reg [adr_w-1:0] ar0_data_in;
reg [adr_w-1:0] ar1_data_in;
wire [adr_w-1:0] add_res_a;
wire carry_out_a;
reg carry_in_a;
reg [adr_w-1:0] add_a_other_op;
wire [adr_w-1:0] add_res_b;
wire carry_out_b;
reg carry_in_b;
reg [adr_w-1:0] add_b_other_op;
wire ar0_at_top;
wire ar1_at_top;
wire [adr_w-1:0] bit_rv_a;
wire [adr_w-1:0] bit_rv_b;
wire [nat_w-1:0] value0;
wire [nat_w-1:0] value1;
reg [adr_w-1:0] address_0;
reg [adr_w-1:0] address_1;
assign value0 = ctrl_i`AGU_IMM0_VALUE ? id_data_bus_i : rf_opa_bus_i;
assign value1 = ctrl_i`AGU_IMM1_VALUE ? id_data_bus_i : rf_opa_bus_i;
assign ar0_at_top = (ar0_data_out == top_o_dat_a);
assign ar1_at_top = (ar1_data_out == top_o_dat_b);
assign agu_ar0_sel = ctrl_i`AGU_AR0_SEL;
assign agu_ar1_sel = ctrl_i`AGU_AR1_SEL;
assign ar0_rf_wren = ctrl_i`AGU_AR0_WREN;
assign ar1_rf_wren = ctrl_i`AGU_AR1_WREN;
always@* begin
casex(ar0_at_top & ctrl_i`AGU_MODULO_0)
1'b0: ar0_data_in = add_res_a;
1'b1: ar0_data_in = btm_o_dat_a;
endcase
if(ar1_at_top & ctrl_i`AGU_MODULO_1) begin
ar1_data_in = btm_o_dat_b;
end
else begin
ar1_data_in = add_res_b;
end
end
//Stack pointer special register
always@(posedge clk_i) begin
if(spr_sp_wren)
sp <= spr_dat_i;
if(ctrl_i`AGU_SP_EN & ~ctrl_i`AGU_IMM0_VALUE) //Not write to sp with offset
sp <= ar0_data_in;
end
always@(posedge clk_i) begin
if(ar0_rf_wren) begin
ar_rf[agu_ar0_sel] <= ar0_data_in;
end
if(spr_ar_wren) begin
ar_rf[spr_sel] <= spr_dat_i;
end
if(ar1_rf_wren) begin
ar_rf[agu_ar1_sel] <= ar1_data_in;
end
end
//Need to do like this to be able to synthesize, bug in xst
wire [adr_w-1:0] ar_rf_ar0_sel;
wire [adr_w-1:0] ar_rf_ar1_sel;
assign ar_rf_ar0_sel = ctrl_i`AGU_SP_EN ? sp : ar_rf[ctrl_i`AGU_AR0_SEL];
assign ar_rf_ar1_sel = ar_rf[ctrl_i`AGU_AR1_SEL];
always@* begin
ar0_data_out = ar_rf_ar0_sel;
ar1_data_out = ar_rf_ar1_sel;
end
bit_reversal #(.dat_w(adr_w))
bit_reversal0
(
// Outputs
.dat_o (bit_rv_a),
// Inputs
.dat_i (ar0_data_out),
.bitrev (bitrev_rf));
bit_reversal #(.dat_w(adr_w))
bit_reversal1
(
// Outputs
.dat_o (bit_rv_b),
// Inputs
.dat_i (ar1_data_out),
.bitrev (bitrev_rf));
//Bit reversal special register
always@(posedge clk_i) begin
if(spr_bitrev_wren)
bitrev_rf = spr_dat_i[2:0];
end
always@* begin
casex({ctrl_i`AGU_PRE_OP_0, ctrl_i`AGU_BR0, ctrl_i`AGU_AR0_OUT})
3'b000: address_0 = value0;
3'b001: address_0 = ar0_data_out;
3'b01x: address_0 = bit_rv_a;
3'b1xx: address_0 = ar0_data_in;
endcase // casex({ctrl_i`AGU_BR0, ctrl_i`AGU_AR0_OUT})
end
always@* begin
casex({ctrl_i`AGU_PRE_OP_1, ctrl_i`AGU_BR1, ctrl_i`AGU_AR1_OUT})
3'b000: address_1 = value1;
3'b001: address_1 = ar1_data_out;
3'b01x: address_1 = bit_rv_b;
3'b1xx: address_1 = ar1_data_in;
endcase // casex({ctrl_i`AGU_BR0, ctrl_i`AGU_AR0_OUT})
end
always@* begin
case(ctrl_i`AGU_OUT_MODE)
1'b0: begin
dm0_address_o = address_0;
dm1_address_o = address_1;
end
1'b1: begin
dm0_address_o = address_1;
dm1_address_o = address_0;
end
endcase // case(ctrl_i`AGU_OUT_MODE)
end
assign dm0_wren_o = ctrl_i`AGU_DM0_WREN;
assign dm1_wren_o = ctrl_i`AGU_DM1_WREN;
agu_rf #(.other_value({adr_w{1'b1}}))
top
(
// Outputs
.dat_a_o (top_o_dat_a),
.dat_b_o (top_o_dat_b),
// Inputs
.clk_i (clk_i),
.adr_a_i (agu_ar0_sel),
.adr_b_i (agu_ar1_sel),
.spr_wren_i (spr_top_wren),
.spr_read_i (spr_top_read),
.spr_sel_i (spr_sel),
.spr_dat_i (spr_dat_i));
agu_rf #(.other_value(0))
btm
(
// Outputs
.dat_a_o (btm_o_dat_a),
.dat_b_o (btm_o_dat_b),
// Inputs
.clk_i (clk_i),
.adr_a_i (agu_ar0_sel),
.adr_b_i (agu_ar1_sel),
.spr_wren_i (spr_btm_wren),
.spr_read_i (spr_btm_read),
.spr_sel_i (spr_sel),
.spr_dat_i (spr_dat_i));
agu_rf #(.other_value(1))
stp
(
// Outputs
.dat_a_o (stp_o_dat_a),
.dat_b_o (stp_o_dat_b),
// Inputs
.clk_i (clk_i),
.adr_a_i (agu_ar0_sel),
.adr_b_i (agu_ar1_sel),
.spr_wren_i (spr_stp_wren),
.spr_read_i (spr_stp_read),
.spr_sel_i (spr_sel),
.spr_dat_i (spr_dat_i));
assign {carry_out_a,add_res_a} = ar0_data_out + add_a_other_op + carry_in_a;
assign {carry_out_b,add_res_b} = ar1_data_out + add_b_other_op + carry_in_b;
always@* begin
add_a_other_op = 0;
carry_in_a = 0;
casex({ctrl_i`AGU_SP_EN, ctrl_i`AGU_OTHER_VAL0})
3'b000,3'b100: add_a_other_op = value0;
3'b001: add_a_other_op = stp_o_dat_a;
3'b01x: begin
add_a_other_op = ~stp_o_dat_a;
carry_in_a = 1;
end
3'b101: add_a_other_op = 1;
3'b111: begin
add_a_other_op = -1;
end
endcase
end
always@* begin
add_b_other_op = 0;
carry_in_b = 0;
casex(ctrl_i`AGU_OTHER_VAL1)
2'b00: add_b_other_op = value1;
2'b01: add_b_other_op = stp_o_dat_b;
2'b1x: begin
add_b_other_op = ~stp_o_dat_b;
carry_in_b = 1;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BLACKBOX_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_BLACKBOX_V
|
module ok2wbm(
// Wishbone master interface
input wire wb_clk_i,
input wire wb_rst_i,
input wire wb_ack_i,
input wire wb_int_i,
output reg wb_cyc_o,
output reg wb_stb_o,
output reg wb_we_o,
input wire [15:0] wb_data_i,
output reg [15:0] wb_data_o,
output wire [4:0] wb_addr_o,
output wire [1:0] wb_sel_o,
output reg [2:0] wb_cti_o,
// Status triggers and signals
output wire trg_irq,
output wire trg_done,
output wire busy,
// Transaction triggers and signals
input wire trg_sngl_rd,
input wire trg_sngl_wr,
input wire trg_brst_rd,
input wire trg_brst_wr,
input wire brst_rd,
input wire brst_wr,
// Address
input wire [15:0] addr_in,
// Single transaction data ports
input wire [15:0] sngl_data_in,
output reg [15:0] sngl_data_out,
// Burst transaction data ports
input wire [15:0] brst_data_in,
output wire [15:0] brst_data_out,
// Debug
output wire [15:0] debug_out
);
// DEBUG!
assign debug_out = sngl_data_out;
// May need to change in future - for now everything is 16bit wide
assign wb_sel_o = 2'b11;
// Start of Transaction (SOT) - both single and burst mdoes
wire sot;
assign sot = trg_sngl_rd | trg_sngl_wr | trg_brst_rd | trg_delay_wr[1];
// End of Transaction (EOT) - burst mode only
wire eot;
assign eot = wb_stb_o & ((wb_we_o & ~brst_wr) | (rd_burst_live & ~brst_rd));
// Delay the write trigger to get data to align with Opal Kelly BT Pipe
reg [1:0] trg_delay_wr;
always @(posedge wb_clk_i) begin
trg_delay_wr <= {trg_delay_wr[0], trg_brst_wr};
end
// Detect burst mode
reg rd_burst_live;
reg wr_burst_live;
always @(posedge wb_clk_i) begin
// Set by burst triggers or itself. Cleared by EOT or reset
rd_burst_live <= (trg_brst_rd | rd_burst_live) & ~(eot | wb_rst_i);
wr_burst_live <= (trg_delay_wr[1] | wr_burst_live) & ~(eot | wb_rst_i);
end
// Denote when the system is using burst-mode functionality
wire burst_mode;
assign burst_mode = rd_burst_live | wr_burst_live;
// End of Transation - both modes
assign trg_done = (wb_ack_i & ~burst_mode) | eot;
// Transaction type identification
always @(burst_mode or eot) begin
if (burst_mode & ~eot)
wb_cti_o = 3'b001; // Constant address
else if (burst_mode & eot)
wb_cti_o = 3'b111; // Last transaction of burst
else
wb_cti_o = 3'b000; // Classic transaction type
end
// Frame transaction
always @(posedge wb_clk_i) begin
// Set by SOT or itself, cleared by trg_done or RST
wb_cyc_o <= (sot | wb_cyc_o) & ~(trg_done | wb_rst_i);
wb_stb_o <= (sot | wb_stb_o) & ~(trg_done | wb_rst_i);
end
assign busy = wb_cyc_o;
// Put one clock delay on incoming data to align with WB control signals
always @(posedge wb_clk_i) begin
if (burst_mode)
wb_data_o <= brst_data_in;
else
wb_data_o <= sngl_data_in;
end
// Straight pass-throughs
assign wb_addr_o = addr_in[4:0];
assign irq = wb_int_i;
assign brst_data_out = wb_data_i;
// Read handling
always @(posedge wb_clk_i) begin
// Latch on ACK - qualify with STB and CYC
if (wb_ack_i && wb_stb_o && wb_cyc_o)
sngl_data_out <= wb_data_i;
else
sngl_data_out <= sngl_data_out; // Explicit latch
end
// Write enable
always @(posedge wb_clk_i) begin
// Set by single write, write burst live, or itself; cleared by trg_done or RST
wb_we_o <= (trg_sngl_wr | wr_burst_live | wb_we_o) & ~(trg_done | wb_rst_i);
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fast_spi_rx_core
#(
parameter ABUSWIDTH = 16,
parameter IDENTYFIER = 4'b0001
)(
input wire SCLK,
input wire SDI,
input wire SEN,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD
);
localparam VERSION = 0;
//output format #ID (as parameter IDENTYFIER + 12 id-frame + 16 bit data)
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg CONF_EN;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
end
end
reg [7:0] LOST_DATA_CNT;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {7'b0, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= LOST_DATA_CNT;
else
BUS_DATA_OUT <= 8'b0;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SCLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire CONF_EN_SYNC;
assign CONF_EN_SYNC = CONF_EN;
reg [7:0] sync_cnt;
always@(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
reg [11:0] frame_cnt;
wire SEN_START, SEN_FINISH;
reg SEN_DLY;
always@(posedge SCLK) begin
SEN_DLY <= SEN;
end
assign SEN_START = (SEN_DLY ==0 && SEN == 1);
assign SEN_FINISH = (SEN_DLY ==1 && SEN == 0);
always@(posedge SCLK) begin
if(RST_SYNC)
frame_cnt <= 0;
else if(SEN_FINISH && CONF_EN_SYNC)
frame_cnt <= frame_cnt + 1;
end
wire cdc_fifo_write;
reg [4:0] bit_cnt;
always@(posedge SCLK) begin
if(RST_SYNC | SEN_START)
bit_cnt <= 0;
else if(cdc_fifo_write)
bit_cnt <= 0;
else if(SEN)
bit_cnt <= bit_cnt + 1;
end
assign cdc_fifo_write = ( (bit_cnt == 15) || SEN_FINISH ) && CONF_EN_SYNC;
reg [15:0] spi_data;
always@(posedge SCLK) begin
if(RST_SYNC | SEN_FINISH)
spi_data <= 0;
else if(cdc_fifo_write)
spi_data <= {15'b0, SDI};
else if(SEN)
spi_data <= {spi_data[14:0], SDI};
end
wire fifo_full,cdc_fifo_empty;
wire wfull;
always@(posedge SCLK) begin
if(RST_SYNC)
LOST_DATA_CNT <= 0;
else if (wfull && cdc_fifo_write && LOST_DATA_CNT != -1)
LOST_DATA_CNT <= LOST_DATA_CNT +1;
end
wire [31:0] cdc_data;
assign cdc_data = {IDENTYFIER, frame_cnt[11:0], spi_data};
wire [31:0] cdc_data_out;
cdc_syncfifo #(.DSIZE(32), .ASIZE(2)) cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(cdc_data),
.winc(cdc_fifo_write), .wclk(SCLK), .wrst(RST_LONG),
.rinc(!fifo_full), .rclk(BUS_CLK), .rrst(RST_LONG)
);
gerneric_fifo #(.DATA_SIZE(32), .DEPTH(1024)) fifo_i
( .clk(BUS_CLK), .reset(RST_LONG | BUS_RST),
.write(!cdc_fifo_empty),
.read(FIFO_READ),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]), .size()
);
//assign FIFO_DATA[31:30] = 0;
endmodule
|
/*
-- ============================================================================
-- FILE NAME : bus_slave_mux.v
-- DESCRIPTION : oXX[u}`vNT
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "bus.h"
/********** W
[ **********/
module bus_slave_mux (
/********** `bvZNg **********/
input wire s0_cs_, // oXX[u0Ô
input wire s1_cs_, // oXX[u1Ô
input wire s2_cs_, // oXX[u2Ô
input wire s3_cs_, // oXX[u3Ô
input wire s4_cs_, // oXX[u4Ô
input wire s5_cs_, // oXX[u5Ô
input wire s6_cs_, // oXX[u6Ô
input wire s7_cs_, // oXX[u7Ô
/********** oXX[uM **********/
// oXX[u0Ô
input wire [`WordDataBus] s0_rd_data, // ÇÝoµf[^
input wire s0_rdy_, // fB
// oXX[u1Ô
input wire [`WordDataBus] s1_rd_data, // ÇÝoµf[^
input wire s1_rdy_, // fB
// oXX[u2Ô
input wire [`WordDataBus] s2_rd_data, // ÇÝoµf[^
input wire s2_rdy_, // fB
// oXX[u3Ô
input wire [`WordDataBus] s3_rd_data, // ÇÝoµf[^
input wire s3_rdy_, // fB
// oXX[u4Ô
input wire [`WordDataBus] s4_rd_data, // ÇÝoµf[^
input wire s4_rdy_, // fB
// oXX[u5Ô
input wire [`WordDataBus] s5_rd_data, // ÇÝoµf[^
input wire s5_rdy_, // fB
// oXX[u6Ô
input wire [`WordDataBus] s6_rd_data, // ÇÝoµf[^
input wire s6_rdy_, // fB
// oXX[u7Ô
input wire [`WordDataBus] s7_rd_data, // ÇÝoµf[^
input wire s7_rdy_, // fB
/********** oX}X^¤ÊM **********/
output reg [`WordDataBus] m_rd_data, // ÇÝoµf[^
output reg m_rdy_ // fB
);
/********** oXX[u}`vNT **********/
always @(*) begin
/* `bvZNgÉηéX[uÌIð */
if (s0_cs_ == `ENABLE_) begin // oXX[u0Ô
m_rd_data = s0_rd_data;
m_rdy_ = s0_rdy_;
end else if (s1_cs_ == `ENABLE_) begin // oXX[u1Ô
m_rd_data = s1_rd_data;
m_rdy_ = s1_rdy_;
end else if (s2_cs_ == `ENABLE_) begin // oXX[u2Ô
m_rd_data = s2_rd_data;
m_rdy_ = s2_rdy_;
end else if (s3_cs_ == `ENABLE_) begin // oXX[u3Ô
m_rd_data = s3_rd_data;
m_rdy_ = s3_rdy_;
end else if (s4_cs_ == `ENABLE_) begin // oXX[u4Ô
m_rd_data = s4_rd_data;
m_rdy_ = s4_rdy_;
end else if (s5_cs_ == `ENABLE_) begin // oXX[u5Ô
m_rd_data = s5_rd_data;
m_rdy_ = s5_rdy_;
end else if (s6_cs_ == `ENABLE_) begin // oXX[u6Ô
m_rd_data = s6_rd_data;
m_rdy_ = s6_rdy_;
end else if (s7_cs_ == `ENABLE_) begin // oXX[u7Ô
m_rd_data = s7_rd_data;
m_rdy_ = s7_rdy_;
end else begin // ftHgl
m_rd_data = `WORD_DATA_W'h0;
m_rdy_ = `DISABLE_;
end
end
endmodule
|
//-----------------------------------------------------------------------------
// system_xillybus_0_wrapper.v
//-----------------------------------------------------------------------------
module system_xillybus_0_wrapper
(
S_AXI_ACLK,
S_AXI_ARESETN,
Interrupt,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WVALID,
S_AXI_BREADY,
S_AXI_ARADDR,
S_AXI_ARVALID,
S_AXI_RREADY,
S_AXI_ARREADY,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RVALID,
S_AXI_WREADY,
S_AXI_BRESP,
S_AXI_BVALID,
S_AXI_AWREADY,
m_axi_aclk,
m_axi_aresetn,
m_axi_arready,
m_axi_arvalid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arprot,
m_axi_arcache,
m_axi_rready,
m_axi_rvalid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_awready,
m_axi_awvalid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awprot,
m_axi_awcache,
m_axi_wready,
m_axi_wvalid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_bready,
m_axi_bvalid,
m_axi_bresp,
xillybus_bus_clk,
xillybus_bus_rst_n,
xillybus_S_AXI_AWADDR,
xillybus_S_AXI_AWVALID,
xillybus_S_AXI_WDATA,
xillybus_S_AXI_WSTRB,
xillybus_S_AXI_WVALID,
xillybus_S_AXI_BREADY,
xillybus_S_AXI_ARADDR,
xillybus_S_AXI_ARVALID,
xillybus_S_AXI_RREADY,
xillybus_S_AXI_ARREADY,
xillybus_S_AXI_RDATA,
xillybus_S_AXI_RRESP,
xillybus_S_AXI_RVALID,
xillybus_S_AXI_WREADY,
xillybus_S_AXI_BRESP,
xillybus_S_AXI_BVALID,
xillybus_S_AXI_AWREADY,
xillybus_M_AXI_ARREADY,
xillybus_M_AXI_ARVALID,
xillybus_M_AXI_ARADDR,
xillybus_M_AXI_ARLEN,
xillybus_M_AXI_ARSIZE,
xillybus_M_AXI_ARBURST,
xillybus_M_AXI_ARPROT,
xillybus_M_AXI_ARCACHE,
xillybus_M_AXI_RREADY,
xillybus_M_AXI_RVALID,
xillybus_M_AXI_RDATA,
xillybus_M_AXI_RRESP,
xillybus_M_AXI_RLAST,
xillybus_M_AXI_AWREADY,
xillybus_M_AXI_AWVALID,
xillybus_M_AXI_AWADDR,
xillybus_M_AXI_AWLEN,
xillybus_M_AXI_AWSIZE,
xillybus_M_AXI_AWBURST,
xillybus_M_AXI_AWPROT,
xillybus_M_AXI_AWCACHE,
xillybus_M_AXI_WREADY,
xillybus_M_AXI_WVALID,
xillybus_M_AXI_WDATA,
xillybus_M_AXI_WSTRB,
xillybus_M_AXI_WLAST,
xillybus_M_AXI_BREADY,
xillybus_M_AXI_BVALID,
xillybus_M_AXI_BRESP,
xillybus_host_interrupt
);
input S_AXI_ACLK;
input S_AXI_ARESETN;
output Interrupt;
input [31:0] S_AXI_AWADDR;
input S_AXI_AWVALID;
input [31:0] S_AXI_WDATA;
input [3:0] S_AXI_WSTRB;
input S_AXI_WVALID;
input S_AXI_BREADY;
input [31:0] S_AXI_ARADDR;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_ARREADY;
output [31:0] S_AXI_RDATA;
output [1:0] S_AXI_RRESP;
output S_AXI_RVALID;
output S_AXI_WREADY;
output [1:0] S_AXI_BRESP;
output S_AXI_BVALID;
output S_AXI_AWREADY;
input m_axi_aclk;
input m_axi_aresetn;
input m_axi_arready;
output m_axi_arvalid;
output [31:0] m_axi_araddr;
output [3:0] m_axi_arlen;
output [2:0] m_axi_arsize;
output [1:0] m_axi_arburst;
output [2:0] m_axi_arprot;
output [3:0] m_axi_arcache;
output m_axi_rready;
input m_axi_rvalid;
input [31:0] m_axi_rdata;
input [1:0] m_axi_rresp;
input m_axi_rlast;
input m_axi_awready;
output m_axi_awvalid;
output [31:0] m_axi_awaddr;
output [3:0] m_axi_awlen;
output [2:0] m_axi_awsize;
output [1:0] m_axi_awburst;
output [2:0] m_axi_awprot;
output [3:0] m_axi_awcache;
input m_axi_wready;
output m_axi_wvalid;
output [31:0] m_axi_wdata;
output [3:0] m_axi_wstrb;
output m_axi_wlast;
output m_axi_bready;
input m_axi_bvalid;
input [1:0] m_axi_bresp;
output xillybus_bus_clk;
output xillybus_bus_rst_n;
output [31:0] xillybus_S_AXI_AWADDR;
output xillybus_S_AXI_AWVALID;
output [31:0] xillybus_S_AXI_WDATA;
output [3:0] xillybus_S_AXI_WSTRB;
output xillybus_S_AXI_WVALID;
output xillybus_S_AXI_BREADY;
output [31:0] xillybus_S_AXI_ARADDR;
output xillybus_S_AXI_ARVALID;
output xillybus_S_AXI_RREADY;
input xillybus_S_AXI_ARREADY;
input [31:0] xillybus_S_AXI_RDATA;
input [1:0] xillybus_S_AXI_RRESP;
input xillybus_S_AXI_RVALID;
input xillybus_S_AXI_WREADY;
input [1:0] xillybus_S_AXI_BRESP;
input xillybus_S_AXI_BVALID;
input xillybus_S_AXI_AWREADY;
output xillybus_M_AXI_ARREADY;
input xillybus_M_AXI_ARVALID;
input [31:0] xillybus_M_AXI_ARADDR;
input [3:0] xillybus_M_AXI_ARLEN;
input [2:0] xillybus_M_AXI_ARSIZE;
input [1:0] xillybus_M_AXI_ARBURST;
input [2:0] xillybus_M_AXI_ARPROT;
input [3:0] xillybus_M_AXI_ARCACHE;
input xillybus_M_AXI_RREADY;
output xillybus_M_AXI_RVALID;
output [31:0] xillybus_M_AXI_RDATA;
output [1:0] xillybus_M_AXI_RRESP;
output xillybus_M_AXI_RLAST;
output xillybus_M_AXI_AWREADY;
input xillybus_M_AXI_AWVALID;
input [31:0] xillybus_M_AXI_AWADDR;
input [3:0] xillybus_M_AXI_AWLEN;
input [2:0] xillybus_M_AXI_AWSIZE;
input [1:0] xillybus_M_AXI_AWBURST;
input [2:0] xillybus_M_AXI_AWPROT;
input [3:0] xillybus_M_AXI_AWCACHE;
output xillybus_M_AXI_WREADY;
input xillybus_M_AXI_WVALID;
input [31:0] xillybus_M_AXI_WDATA;
input [3:0] xillybus_M_AXI_WSTRB;
input xillybus_M_AXI_WLAST;
input xillybus_M_AXI_BREADY;
output xillybus_M_AXI_BVALID;
output [1:0] xillybus_M_AXI_BRESP;
input xillybus_host_interrupt;
xillybus
#(
.C_S_AXI_DATA_WIDTH ( 32 ),
.C_S_AXI_ADDR_WIDTH ( 32 ),
.C_S_AXI_MIN_SIZE ( 32'h000001ff ),
.C_USE_WSTRB ( 1 ),
.C_DPHASE_TIMEOUT ( 8 ),
.C_BASEADDR ( 32'h50000000 ),
.C_HIGHADDR ( 32'h50000FFF ),
.C_SLV_AWIDTH ( 32 ),
.C_SLV_DWIDTH ( 32 ),
.C_M_AXI_ADDR_WIDTH ( 32 ),
.C_M_AXI_DATA_WIDTH ( 32 ),
.C_MAX_BURST_LEN ( 16 ),
.C_NATIVE_DATA_WIDTH ( 32 )
)
xillybus_0 (
.S_AXI_ACLK ( S_AXI_ACLK ),
.S_AXI_ARESETN ( S_AXI_ARESETN ),
.Interrupt ( Interrupt ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.m_axi_aclk ( m_axi_aclk ),
.m_axi_aresetn ( m_axi_aresetn ),
.m_axi_arready ( m_axi_arready ),
.m_axi_arvalid ( m_axi_arvalid ),
.m_axi_araddr ( m_axi_araddr ),
.m_axi_arlen ( m_axi_arlen ),
.m_axi_arsize ( m_axi_arsize ),
.m_axi_arburst ( m_axi_arburst ),
.m_axi_arprot ( m_axi_arprot ),
.m_axi_arcache ( m_axi_arcache ),
.m_axi_rready ( m_axi_rready ),
.m_axi_rvalid ( m_axi_rvalid ),
.m_axi_rdata ( m_axi_rdata ),
.m_axi_rresp ( m_axi_rresp ),
.m_axi_rlast ( m_axi_rlast ),
.m_axi_awready ( m_axi_awready ),
.m_axi_awvalid ( m_axi_awvalid ),
.m_axi_awaddr ( m_axi_awaddr ),
.m_axi_awlen ( m_axi_awlen ),
.m_axi_awsize ( m_axi_awsize ),
.m_axi_awburst ( m_axi_awburst ),
.m_axi_awprot ( m_axi_awprot ),
.m_axi_awcache ( m_axi_awcache ),
.m_axi_wready ( m_axi_wready ),
.m_axi_wvalid ( m_axi_wvalid ),
.m_axi_wdata ( m_axi_wdata ),
.m_axi_wstrb ( m_axi_wstrb ),
.m_axi_wlast ( m_axi_wlast ),
.m_axi_bready ( m_axi_bready ),
.m_axi_bvalid ( m_axi_bvalid ),
.m_axi_bresp ( m_axi_bresp ),
.xillybus_bus_clk ( xillybus_bus_clk ),
.xillybus_bus_rst_n ( xillybus_bus_rst_n ),
.xillybus_S_AXI_AWADDR ( xillybus_S_AXI_AWADDR ),
.xillybus_S_AXI_AWVALID ( xillybus_S_AXI_AWVALID ),
.xillybus_S_AXI_WDATA ( xillybus_S_AXI_WDATA ),
.xillybus_S_AXI_WSTRB ( xillybus_S_AXI_WSTRB ),
.xillybus_S_AXI_WVALID ( xillybus_S_AXI_WVALID ),
.xillybus_S_AXI_BREADY ( xillybus_S_AXI_BREADY ),
.xillybus_S_AXI_ARADDR ( xillybus_S_AXI_ARADDR ),
.xillybus_S_AXI_ARVALID ( xillybus_S_AXI_ARVALID ),
.xillybus_S_AXI_RREADY ( xillybus_S_AXI_RREADY ),
.xillybus_S_AXI_ARREADY ( xillybus_S_AXI_ARREADY ),
.xillybus_S_AXI_RDATA ( xillybus_S_AXI_RDATA ),
.xillybus_S_AXI_RRESP ( xillybus_S_AXI_RRESP ),
.xillybus_S_AXI_RVALID ( xillybus_S_AXI_RVALID ),
.xillybus_S_AXI_WREADY ( xillybus_S_AXI_WREADY ),
.xillybus_S_AXI_BRESP ( xillybus_S_AXI_BRESP ),
.xillybus_S_AXI_BVALID ( xillybus_S_AXI_BVALID ),
.xillybus_S_AXI_AWREADY ( xillybus_S_AXI_AWREADY ),
.xillybus_M_AXI_ARREADY ( xillybus_M_AXI_ARREADY ),
.xillybus_M_AXI_ARVALID ( xillybus_M_AXI_ARVALID ),
.xillybus_M_AXI_ARADDR ( xillybus_M_AXI_ARADDR ),
.xillybus_M_AXI_ARLEN ( xillybus_M_AXI_ARLEN ),
.xillybus_M_AXI_ARSIZE ( xillybus_M_AXI_ARSIZE ),
.xillybus_M_AXI_ARBURST ( xillybus_M_AXI_ARBURST ),
.xillybus_M_AXI_ARPROT ( xillybus_M_AXI_ARPROT ),
.xillybus_M_AXI_ARCACHE ( xillybus_M_AXI_ARCACHE ),
.xillybus_M_AXI_RREADY ( xillybus_M_AXI_RREADY ),
.xillybus_M_AXI_RVALID ( xillybus_M_AXI_RVALID ),
.xillybus_M_AXI_RDATA ( xillybus_M_AXI_RDATA ),
.xillybus_M_AXI_RRESP ( xillybus_M_AXI_RRESP ),
.xillybus_M_AXI_RLAST ( xillybus_M_AXI_RLAST ),
.xillybus_M_AXI_AWREADY ( xillybus_M_AXI_AWREADY ),
.xillybus_M_AXI_AWVALID ( xillybus_M_AXI_AWVALID ),
.xillybus_M_AXI_AWADDR ( xillybus_M_AXI_AWADDR ),
.xillybus_M_AXI_AWLEN ( xillybus_M_AXI_AWLEN ),
.xillybus_M_AXI_AWSIZE ( xillybus_M_AXI_AWSIZE ),
.xillybus_M_AXI_AWBURST ( xillybus_M_AXI_AWBURST ),
.xillybus_M_AXI_AWPROT ( xillybus_M_AXI_AWPROT ),
.xillybus_M_AXI_AWCACHE ( xillybus_M_AXI_AWCACHE ),
.xillybus_M_AXI_WREADY ( xillybus_M_AXI_WREADY ),
.xillybus_M_AXI_WVALID ( xillybus_M_AXI_WVALID ),
.xillybus_M_AXI_WDATA ( xillybus_M_AXI_WDATA ),
.xillybus_M_AXI_WSTRB ( xillybus_M_AXI_WSTRB ),
.xillybus_M_AXI_WLAST ( xillybus_M_AXI_WLAST ),
.xillybus_M_AXI_BREADY ( xillybus_M_AXI_BREADY ),
.xillybus_M_AXI_BVALID ( xillybus_M_AXI_BVALID ),
.xillybus_M_AXI_BRESP ( xillybus_M_AXI_BRESP ),
.xillybus_host_interrupt ( xillybus_host_interrupt )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BO_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A21BO_BEHAVIORAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BO_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR3_PP_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_PP_BLACKBOX_V
|
module DM9000A_IF( // HOST Side
// Signals fro Avalon-MM slave port "s1"
avs_s1_writedata_iDATA,
avs_s1_readdata_oDATA,
avs_s1_address_iCMD,
avs_s1_read_n_iRD_N,
avs_s1_write_n_iWR_N,
avs_s1_chipselect_n_iCS_N,
avs_s1_reset_n_iRST_N,
avs_s1_clk_iCLK,
avs_s1_irq_oINT,
// export signal to DM9000A Chip
avs_s1_export_ENET_DATA,
avs_s1_export_ENET_CMD,
avs_s1_export_ENET_RD_N,
avs_s1_export_ENET_WR_N,
avs_s1_export_ENET_CS_N,
avs_s1_export_ENET_RST_N,
avs_s1_export_ENET_INT,
avs_s1_export_ENET_CLK
);
// HOST Side
input [15:0] avs_s1_writedata_iDATA;
input avs_s1_address_iCMD;
input avs_s1_read_n_iRD_N;
input avs_s1_write_n_iWR_N;
input avs_s1_chipselect_n_iCS_N;
input avs_s1_reset_n_iRST_N;
input avs_s1_clk_iCLK;
output [15:0] avs_s1_readdata_oDATA;
output avs_s1_irq_oINT;
// DM9000A Side
inout [15:0] avs_s1_export_ENET_DATA;
output avs_s1_export_ENET_CMD;
output avs_s1_export_ENET_RD_N;
output avs_s1_export_ENET_WR_N;
output avs_s1_export_ENET_CS_N;
output avs_s1_export_ENET_RST_N;
output avs_s1_export_ENET_CLK;
input avs_s1_export_ENET_INT;
assign avs_s1_export_ENET_DATA = avs_s1_write_n_iWR_N ? 16'hzzzz : avs_s1_writedata_iDATA;
assign avs_s1_readdata_oDATA = avs_s1_read_n_iRD_N ? 16'hzzzz : avs_s1_export_ENET_DATA;
assign avs_s1_export_ENET_RST_N = avs_s1_reset_n_iRST_N;
assign avs_s1_irq_oINT = avs_s1_export_ENET_INT;
assign avs_s1_export_ENET_CMD = avs_s1_address_iCMD;
assign avs_s1_export_ENET_CS_N = avs_s1_chipselect_n_iCS_N;
assign avs_s1_export_ENET_RD_N = avs_s1_read_n_iRD_N;
assign avs_s1_export_ENET_WR_N = avs_s1_write_n_iWR_N;
assign avs_s1_export_ENET_CLK = avs_s1_clk_iCLK;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O41A_FUNCTIONAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_FUNCTIONAL_V |
module I2C(
clk,
scl,
sda,
rst_n,
LED,
accXdata
);
input clk,rst_n;
output scl;
//output [7:0]data;
inout sda;
output reg LED;
output wire [15:0] accXdata;
reg [2:0]cnt;//cnt=0，scl上升沿；cnt=1，scl高电平中间；cnt=2，scl下降沿；cnt=3，scl低电平中间
reg [8:0]cnt_sum;//产生IIC所需要的时钟
reg scl_r;//产生的时钟脉冲
reg [19:0]cnt_10ms;
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt_10ms <= 20'd0;
else
cnt_10ms <= cnt_10ms+1'b1;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt_sum <= 0;
else if(cnt_sum ==9'd499)
cnt_sum <= 0;
else
cnt_sum <= cnt_sum+1'b1;
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt <= 3'd5;
else
begin
case(cnt_sum)
9'd124: cnt<=3'd1;//高电平
9'd249: cnt<=3'd2;//下降沿
9'd374: cnt<=3'd3;//低电平
9'd499: cnt<=3'd0;//上升沿
default: cnt<=3'd5;
endcase
end
end
`define SCL_POS (cnt==3'd0)
`define SCL_HIG (cnt==3'd1)
`define SCL_NEG (cnt==3'd2)
`define SCL_LOW (cnt==3'd3)
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
scl_r <= 1'b0;
else if(cnt==3'd0)
scl_r <= 1'b1;
else if(cnt==3'd2)
scl_r <= 1'b0;
end
assign scl = scl_r;//scl时钟信号
`define DEVICE_READ 8'hD1//寻址器件，读操作
`define DEVICE_WRITE 8'hD0//寻址器件，写操作
`define ACC_XH 8'h3B//加速度x轴高位地址
`define ACC_XL 8'h3C//加速度x轴低位地址
`define ACC_YH 8'h3D//加速度y轴高位地址
`define ACC_YL 8'h3E//加速度y轴低位地址
`define ACC_ZH 8'h3F//加速度z轴高位地址
`define ACC_ZL 8'h40//加速度z轴低位地址
`define GYRO_XH 8'h43//陀螺仪x轴高位地址
`define GYRO_XL 8'h44//陀螺仪x轴低位地址
`define GYRO_YH 8'h45//陀螺仪y轴高位地址
`define GYRO_YL 8'h46//陀螺仪y轴低位地址
`define GYRO_ZH 8'h47//陀螺仪z轴高位地址
`define GYRO_ZL 8'h48//陀螺仪z轴低位地址
//陀螺仪初始化寄存器
`define PWR_MGMT_1 8'h6B
`define SMPLRT_DIV 8'h19
`define CONFIG1 8'h1A
`define GYRO_CONFIG 8'h1B
`define ACC_CONFIG 8'h1C
//陀螺仪初始化对应寄存器值配置
`define PWR_MGMT_1_VAL 8'h00
`define SMPLRT_DIV_VAL 8'h07
`define CONFIG1_VAL 8'h06
`define GYRO_CONFIG_VAL 8'h18
`define ACC_CONFIG_VAL 8'h01
parameter IDLE = 4'd0;
parameter START1 = 4'd1;
parameter ADD1 = 4'd2;
parameter ACK1 = 4'd3;
parameter ADD2 = 4'd4;
parameter ACK2 = 4'd5;
parameter START2 = 4'd6;
parameter ADD3 =4'd7;
parameter ACK3 = 4'd8;
parameter DATA = 4'd9;
parameter ACK4 = 4'd10;
parameter STOP1 = 4'd11;
parameter STOP2 = 4'd12;
parameter ADD_EXT = 4'd13;
parameter ACK_EXT = 4'd14;
reg [3:0]state;//状态寄存器
reg sda_r;//输出
reg sda_link;//sda_link=1,sda输出;sda_link=0,sda高阻态
reg [3:0]num;
reg [7:0]db_r;
reg [7:0]ACC_XH_READ;//存储加速度X轴高八位
reg [7:0]ACC_XL_READ;//存储加速度X轴低八位
reg [7:0]ACC_YH_READ;//存储加速度Y轴高八位
reg [7:0]ACC_YL_READ;//存储加速度Y轴低八位
reg [7:0]ACC_ZH_READ;//存储加速度Z轴高八位
reg [7:0]ACC_ZL_READ;//存储加速度Z轴低八位
reg [7:0]GYRO_XH_READ;//存储陀螺仪X轴高八位
reg [7:0]GYRO_XL_READ;//存储陀螺仪X轴低八位
reg [7:0]GYRO_YH_READ;//存储陀螺仪Y轴高八位
reg [7:0]GYRO_YL_READ;//存储陀螺仪Y轴低八位
reg [7:0]GYRO_ZH_READ;//存储陀螺仪Z轴高八位
reg [7:0]GYRO_ZL_READ;//存储陀螺仪Z轴低八位
reg [4:0]times;//记录已初始化配置的寄存器个数
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
state <= IDLE;
sda_r <= 1'b1;//拉高数据线
sda_link <= 1'b0;//高阻态
num <= 4'd0;
//初始化寄存器
ACC_XH_READ <= 8'h00;
ACC_XL_READ <= 8'h00;
ACC_YH_READ <= 8'h00;
ACC_YL_READ <= 8'h00;
ACC_ZH_READ <= 8'h00;
ACC_ZL_READ <= 8'h00;
GYRO_XH_READ <= 8'h00;
GYRO_XL_READ <= 8'h00;
GYRO_YH_READ <= 8'h00;
GYRO_YL_READ <= 8'h00;
GYRO_ZH_READ <= 8'h00;
GYRO_ZL_READ <= 8'h00;
times <= 5'b0;
end
else
case(state)
IDLE: begin
times <= times+1'b1;
sda_link <= 1'b1;//sda为输出
sda_r <= 1'b1;//拉高sda
db_r <= `DEVICE_WRITE;//向从机写入数据地址
state = START1;
end
START1:begin//IIC start
if(`SCL_HIG)//scl为高电平
begin
sda_link <= 1'b1;//sda输出
sda_r <= 1'b0;//拉低sda，产生start信号
state <= ADD1;
num <= 4'd0;
end
else
state <= START1;
end
ADD1: begin//数据写入
if(`SCL_LOW)//scl为低电平
begin
if(num == 4'd8)//当8位全部输出
begin
num <= 4'd0;//计数清零
sda_r <= 1'b1;
sda_link <= 1'b0;//sda高阻态
state <= ACK1;
end
else
begin
state <= ADD1;
num <= num+1'b1;
sda_r <= db_r[4'd7-num];//按位输出
end
end
else
state <= ADD1;
end
ACK1: begin//应答
if(`SCL_NEG)
begin
state <= ADD2;
case(times)//选择下一个写入寄存器地址
5'd1: db_r <= `PWR_MGMT_1;
5'd2: db_r <= `SMPLRT_DIV;
5'd3: db_r <= `CONFIG1;
5'd4: db_r <= `GYRO_CONFIG;
5'd5: db_r <= `ACC_CONFIG;
5'd6: db_r <= `ACC_XH;
5'd7: db_r <= `ACC_XL;
5'd8: db_r <= `ACC_YH;
5'd9: db_r <= `ACC_YL;
5'd10: db_r <= `ACC_ZH;
5'd11: db_r <= `ACC_ZL;
5'd12: db_r <= `GYRO_XH;
5'd13: db_r <= `GYRO_XL;
5'd14: db_r <= `GYRO_YH;
5'd15: db_r <= `GYRO_YL;
5'd16: db_r <= `GYRO_ZH;
5'd17: db_r <= `GYRO_ZL;
default: begin
db_r <= `PWR_MGMT_1;
times <= 5'd1;
end
endcase
end
else
state <= ACK1;//等待响应
end
ADD2: begin
if(`SCL_LOW)//scl为低
begin
if(num == 4'd8)
begin
num <= 4'd0;
sda_r <= 1'b1;
sda_link <= 1'b0;
state <= ACK2;
end
else
begin
sda_link <= 1'b1;
state <= ADD2;
num <= num+1'b1;
sda_r <= db_r[4'd7-num];//按位送寄存器地址
end
end
else
state <= ADD2;
end
ACK2: begin//应答
if(`SCL_NEG)
begin
case(times)//对应寄存器的设定值
3'd1: db_r <= `PWR_MGMT_1_VAL;
3'd2: db_r <= `SMPLRT_DIV_VAL;
3'd3: db_r <= `CONFIG1_VAL;
3'd4: db_r <= `GYRO_CONFIG_VAL;
3'd5: db_r <= `ACC_CONFIG_VAL;
3'd6: db_r <= `DEVICE_READ;
default: db_r <= `DEVICE_READ;
endcase
if(times >= 5'd6)
state <= START2;
else
state <= ADD_EXT;
end
else
state <= ACK2;//等待响应
end
ADD_EXT:begin//初始化一些设定寄存器
if(`SCL_LOW)
begin
if(num == 4'd8)
begin
num <= 4'd0;
sda_r <= 1'b1;
sda_link <= 1'b0;//sda高阻态
state <= ACK_EXT;
end
else
begin
sda_link <= 1'b1;
state <= ADD_EXT;
num <= num+1'b1;
sda_r <= db_r[4'd7-num];//按位设定寄存器工作方式
end
end
else
state <= ADD_EXT;
end
ACK_EXT:begin
if(`SCL_NEG)
begin
sda_r <= 1'b1;//拉高sda
state <= STOP1;
end
else
state <= ACK_EXT;//等待响应
end
START2:begin
if(`SCL_LOW)//scl为低
begin
sda_link <= 1'b1;//sda为输出
sda_r <= 1'b1;//拉高sda
state <= START2;
end
else if(`SCL_HIG)//scl为高
begin
sda_r <= 1'b0;//拉低sda，产生start信号
state <= ADD3;
end
else
state <= START2;
end
ADD3: begin
if(`SCL_LOW)//scl位低
begin
if(num == 4'd8)
begin
num <= 4'd0;
sda_r <= 1'b1;//拉高sda
sda_link <= 1'b0;//scl高阻态
state <= ACK3;
end
else
begin
num <= num+1'b1;
sda_r <= db_r[4'd7-num];//按位写入读取寄存器地址
state <= ADD3;
end
end
else state <= ADD3;
end
ACK3: begin
if(`SCL_NEG)
begin
state <= DATA;
sda_link <= 1'b0;//sda高阻态
end
else
state <= ACK3;//等待响应
end
DATA: begin
if(num <= 4'd7)
begin
state <= DATA;
if(`SCL_HIG)
begin
num <= num+1'b1;
case(times)
5'd6: ACC_XH_READ[4'd7-num] <= sda;
5'd7: ACC_XL_READ[4'd7-num] <= sda;
5'd8: ACC_YH_READ[4'd7-num] <= sda;
5'd9: ACC_YL_READ[4'd7-num] <= sda;
5'd10: ACC_ZH_READ[4'd7-num] <= sda;
5'd11: ACC_ZL_READ[4'd7-num] <= sda;
5'd12: GYRO_XH_READ[4'd7-num] <= sda;
5'd13: GYRO_XL_READ[4'd7-num] <= sda;
5'd14: GYRO_YH_READ[4'd7-num] <= sda;
5'd15: GYRO_YL_READ[4'd7-num] <= sda;
5'd16: GYRO_ZH_READ[4'd7-num] <= sda;
5'd17: GYRO_ZL_READ[4'd7-num] <= sda;
default: ;//暂时未考虑，可添加代码提高系统稳定性
endcase
end
end
else if((`SCL_LOW)&&(num == 4'd8))
begin
sda_link <= 1'b1;//sda为输出
num <= 4'd0;//计数清零
state <= ACK4;
end
else
state <= DATA;
end
ACK4: begin
if(times == 5'd17)
times <= 5'd0;
if(`SCL_NEG)
begin
sda_r <= 1'b1;//拉高sda
state <= STOP1;
end
else
state <= ACK4;//等待响应
end
STOP1:begin
if(`SCL_LOW)//scl为低
begin
sda_link <= 1'b1;//sda输出
sda_r <= 1'b0;//拉低sda
state <= STOP1;
end
else if(`SCL_HIG)//sda为高
begin
sda_r <= 1'b1;//拉高sda,产生stop信号
state <= STOP2;
end
else
state <= STOP1;
end
STOP2:begin
if(`SCL_LOW)
sda_r <= 1'b1;
else if(cnt_10ms == 20'hffff0)//约10ms得一个数据
state <= IDLE;
else
state <= STOP2;
end
default:state <= IDLE;
endcase
end
assign sda = sda_link?sda_r:1'bz;
assign accXdata = {ACC_XH_READ,ACC_XL_READ};
reg [15:0] tmpData;
always@(posedge scl)
begin
//ACC_XH_READ = 8'h1f;
//ACC_XL_READ = 8'h00;
tmpData[15:0] = {ACC_XH_READ,ACC_XL_READ};
if(($signed(tmpData)>16'sd10000)) begin
LED <= 1'b1;
end
else begin
LED <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_SYMBOL_V
`define SKY130_FD_SC_MS__MUX2_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRBP_FUNCTIONAL_PP_V |
// Define if SDRAM controller still screws up frequent random reads
`define SDRAMBUGPRESENT 1
`ifdef ATLYS
`define BLOCKRAM 1
`endif
`ifdef SIMULATION
`define BLOCKRAM 1
`endif
`ifndef BLOCKRAM
`ifdef SDRAMBUGPRESENT
`define SDRAMBUG 1
`endif
`endif
`ifdef BLOCKRAM
`ifdef ATLYS
`define SIM_RAM_SIZE 12*512
`else
`define SIM_RAM_SIZE 1024*512
`endif
module temp_blockram (input clk,
input reset,
input [31:0] cmd_address,
input cmd_wr,
input cmd_enable,
output reg cmd_ready,
input [31:0] cmd_data_in,
output [31:0] data_out,
output reg data_out_ready);
wire [31:0] none;
toyblockram #(.RAM_DEPTH(`SIM_RAM_SIZE))
inner
(.clk(clk),
.addr_a({2'b0,cmd_address[31:2]}),
.datain_a(cmd_data_in),
.wr_a(cmd_wr),
.data_a(data_out),
.data_b(none),
.addr_b({2'b0,cmd_address[31:2]}));
always @(posedge clk)
if (!reset) begin
cmd_ready <= 1;
data_out_ready <= 0;
end else
begin
if(cmd_ready) begin
if (cmd_wr && cmd_enable) begin
data_out_ready <= 0; cmd_ready <= 0;
end else if(cmd_enable) begin
data_out_ready <= 1; cmd_ready <= 0;
end else if (!cmd_enable) begin data_out_ready <= 0; end
end else cmd_ready <= 1;
end
endmodule
`endif
module small1soc(
// External clock input
`ifndef SIMULATION
`ifdef LOGIPI
input OSC_FPGA,
`else
input sys_clk_in, // 100mhz
`endif
`endif
`ifdef SIMULATION
input clk100mhz,
`endif
// Buttons, switches
`ifdef LOGIPI
input [1:0] PB,
input [1:0] SW,
`else
input sys_reset,
`endif
`ifdef ATLYS
input uart_rxd,
output uart_txd,
`endif
`ifndef SIMULATION
// SDRAM interface
output SDRAM_CLK,
output SDRAM_CKE,
output SDRAM_CS,
output SDRAM_nRAS,
output SDRAM_nCAS,
output SDRAM_nWE,
output [1:0] SDRAM_DQM,
output [12:0] SDRAM_ADDR,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
`endif
`ifdef SIMULATION
output reg FINISH,
`endif
// SPI interface
input SYS_SPI_SCK,
input RP_SPI_CE0N,
input SYS_SPI_MOSI,
output SYS_SPI_MISO,
// LEDs to blink
`ifdef LOGIPI
output [1:0] LED
`else
output reg [7:0] LED
`endif
);
reg [31:0] clk_ctr;
wire cpu_reset;
`ifdef LOGIPI
assign cpu_reset = PB[0];
`else
assign cpu_reset = sys_reset;
`endif
always @(posedge clk100mhz)
if (!cpu_reset) begin
clk_ctr <= 0;
end else clk_ctr <= clk_ctr + 1;
reg [31:0] FAILED_ADDR;
parameter test_frequency = 100_000_000 ;
parameter test_frequency_mhz = test_frequency/1_000_000 ;
parameter freq_multiplier = 16 ;
`ifdef LOGIPI
parameter freq_divider = (freq_multiplier*50_000_000)/test_frequency ;
`else
parameter freq_divider = (freq_multiplier*100_000_000)/test_frequency ;
`endif
parameter sdram_address_width= 24;
parameter sdram_column_bits = 9;
parameter sdram_startup_cycles = 10100; // 100us, plus a little more
parameter cycles_per_refresh = (64000*test_frequency_mhz)/8192-1;
reg [4:0] spi_state;
wire [sdram_address_width-1:0] cmd_address;
wire cmd_wr;
wire cmd_enable;
wire cmd_ready;
wire [31:0] cmd_data_in;
wire [31:0] data_out;
wire [31:0] data_out_from_sdram;
wire data_out_ready;
wire clkfb;
wire clk100mhz;
wire clkb;
wire clku;
reg cpu_force_reset;
reg mem_acc_irq; // if accessing unmapped address
`ifdef BLOCKRAM
temp_blockram RAM (.clk(clk100mhz),
.reset(cpu_reset),
.cmd_address(cmd_address),
.cmd_wr(cmd_wr),
.cmd_enable(cmd_enable),
.cmd_ready(cmd_ready),
.cmd_data_in(cmd_data_in),
.data_out(data_out),
.data_out_ready(data_out_ready));
`endif // `ifdef BLOCKRAM
`ifdef ATLYS
BUFG BUFG1 (.O(clk100mhz), .I(sys_clk_in));
`endif
`ifndef BLOCKRAM
SDRAM_Controller
#(
.sdram_address_width(sdram_address_width),
.sdram_column_bits(sdram_column_bits),
.sdram_startup_cycles(sdram_startup_cycles),
.cycles_per_refresh(cycles_per_refresh),
.very_low_speed(0)
) RAM (
.clk(clk100mhz),
.reset(0),
.cmd_address(cmd_address),
.cmd_wr(cmd_wr),
.cmd_enable(cmd_enable),
.cmd_ready(cmd_ready),
.cmd_byte_enable(4'b1111),
.cmd_data_in(cmd_data_in),
.data_out(data_out),
.data_out_ready(data_out_ready),
.SDRAM_CLK(SDRAM_CLK),
.SDRAM_CKE(SDRAM_CKE),
.SDRAM_CS(SDRAM_CS),
.SDRAM_RAS(SDRAM_nRAS),
.SDRAM_CAS(SDRAM_nCAS),
.SDRAM_WE(SDRAM_nWE),
.SDRAM_DQM(SDRAM_DQM),
.SDRAM_BA(SDRAM_BA),
.SDRAM_ADDR(SDRAM_ADDR),
.SDRAM_DATA(SDRAM_DQ)
);
// assign data_out = {data_out_from_sdram[15:0], data_out_from_sdram[31:16]};
`endif
`ifdef LOGIPI
`ifdef FPGA
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(freq_multiplier), //Multiply value for all CLKOUT clock outputs (1-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of the clock feedback output (0.0-360.0).
.CLKIN_PERIOD(20.00), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
.CLKOUT0_DIVIDE(freq_divider),
.CLKOUT1_DIVIDE(freq_divider),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0), // Capture clock
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLK_FEEDBACK("CLKFBOUT"), // Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
.DIVCLK_DIVIDE(1), // Division value for all output clocks (1-52)
.REF_JITTER(0.1), // Reference Clock Jitter in UI (0.000-0.999).
.RESET_ON_LOSS_OF_LOCK(0) // Must be set to FALSE
) PLL1 (
.CLKFBOUT(clkfb), // 1-bit output: PLL_BASE feedback output
// CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
.CLKOUT0(clku), // CLKOUT1 => open,
.CLKOUT2(), // CLKOUT3 => open,
.CLKOUT4(), // CLKOUT5 => open,
.LOCKED(), // 1-bit output: PLL_BASE lock status output
.CLKFBIN(clkfb), // 1-bit input: Feedback clock input
.CLKIN(clkb), // 1-bit input: Clock input
.RST(0) // 1-bit input: Reset input
);
BUFG BUFG1 (.O(clkb), .I(OSC_FPGA));
BUFG BUFG3 (.O(clk100mhz), .I(clku));
`endif // `ifdef FPGA
`endif
// SPI interface
wire [31:0] spi_data_in;
wire [31:0] spi_data_out;
wire spi_data_in_rdy;
wire spi_data_in_ack;
wire spi_data_out_rdy;
wire spi_data_out_ack;
wire spi_data_in_rq;
wire cpu_reset_1;
reg mem_bootload;
assign cpu_reset_1 = /*cpu_force_reset*/ mem_bootload?1'b0:cpu_reset;
reg led0;
reg led1;
`ifdef LOGIPI
wire spi_led;
assign LED[0] = spi_led;
assign LED[1] = led1;
`endif
`ifdef LOGIPI
spi_wrapper spi1(.clk(clk100mhz),
.reset(cpu_reset),
.mosi(SYS_SPI_MOSI),
.miso(SYS_SPI_MISO),
.sck(SYS_SPI_SCK),
.ss(RP_SPI_CE0N),
.data_in(spi_data_in),
.data_in_rdy(spi_data_in_rdy),
.data_in_ack(spi_data_in_ack),
.data_in_rq(spi_data_in_rq),
.data_out(spi_data_out),
.data_out_rdy(spi_data_out_rdy),
.data_out_ack(spi_data_out_ack),
.spi_led(spi_led)
);
`endif // `ifdef LOGIPI
`ifdef ATLYS
spi_mock spi1 (.clk100mhz(clk100mhz),
.reset(cpu_reset),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.data_in(spi_data_in),
.data_in_rdy(spi_data_in_rdy),
.data_in_ack(spi_data_in_ack),
.data_in_rq(spi_data_in_rq),
.data_out(spi_data_out),
.data_out_rdy(spi_data_out_rdy),
.data_out_ack(spi_data_out_ack)
);
`endif
// "UART" over SPI
// uart_in fifo is filled by the SPI controller and read from mem-mapped
// register 0x10001 (empty status: 0x10002)
// uart_out fifo is filled by writing to mem-mapped register 0x10004,
// and emptied by the SPI controller by the master polling request.
// If no data is available it sends 0xffffffff;
reg [31:0] uart_in_data_in;
wire [31:0] uart_in_data_out;
reg uart_in_data_in_wr;
reg uart_in_data_out_en;
wire uart_in_full;
wire uart_in_empty;
reg [31:0] uart_out_data_in;
wire [31:0] uart_out_data_out;
reg uart_out_data_in_wr;
reg uart_out_data_out_en;
wire uart_out_full;
wire uart_out_empty;
reg [31:0] spi_word_send;
reg spi_send_ready;
assign spi_data_in = spi_word_send/*(spi_send_ready&&!spi_send_done)?spi_word_send:32'hffffffff*/;
//assign spi_data_in_rdy = (spi_send_ready&&!spi_send_done);
assign spi_data_in_rq = (spi_send_ready&&!spi_send_done);
reg spi_send_done;
always @(posedge clk100mhz) begin
if (spi_send_ready && spi_data_in_ack)
spi_send_done <= 1; // sent
else if (!spi_send_ready && spi_send_done) spi_send_done <= 0;
end
fifo #(.DEBUG(0)) uart_in(.clk(clk100mhz),
.reset(cpu_reset),
.data_in(uart_in_data_in),
.data_in_wr(uart_in_data_in_wr),
.data_out(uart_in_data_out),
.data_out_en(uart_in_data_out_en),
.full(uart_in_full),
.empty(uart_in_empty)
);
fifo uart_out(.clk(clk100mhz),
.reset(cpu_reset),
.data_in(uart_out_data_in),
.data_in_wr(uart_out_data_in_wr),
.data_out(uart_out_data_out),
.data_out_en(uart_out_data_out_en),
.full(uart_out_full),
.empty(uart_out_empty)
);
reg [31:0] membus_data_in;
reg membus_data_in_ready;
wire [31:0] membus_data_out;
reg membus_data_wr_ack;
wire membus_data_wr;
wire membus_data_rd;
wire [31:0] membus_data_address;
reg cpu_irq;
reg [4:0] cpu_irqn;
wire cpu_irq_ack;
wire cpu_irq_busy;
wire [31:0] debug_reg_out;
reg [3:0] debug_reg_num;
reg cpu_debug;
reg cpu_step;
wire cpu_step_ack;
reg [31:0] top_last_read;
reg [31:0] top_last_addr;
// CPU instance
toycpu cpu1(.clk(clk100mhz),
.rst(cpu_reset_1),
.bus_data_in(membus_data_in),
.bus_data_in_ready(membus_data_in_ready),
.bus_data_ack(membus_data_wr_ack),
.bus_data_wr(membus_data_wr),
.bus_data_rd(membus_data_rd),
.bus_data_address(membus_data_address),
.bus_data_out(membus_data_out),
.irq(cpu_irq),
.irqn(cpu_irqn),
.irq_ack(cpu_irq_ack),
.irq_busy(cpu_irq_busy),
.debug_reg_out(debug_reg_out),
.debug_reg_num(debug_reg_num),
.debug(cpu_debug|mem_acc_irq),
.step(cpu_step),
.step_ack(cpu_step_ack),
.stall(mem_bootload)
);
reg mem_enable;
reg [31:0] spi_boot_word;
reg [31:0] spi_boot_addr;
reg [31:0] spi_boot_count;
reg spi_boot_write;
reg spi_boot_read;
wire is_mem_req;
assign is_mem_req = membus_data_address>=32'h20000;
wire [31:0] addr;
assign addr = mem_bootload?spi_boot_addr:
(is_mem_req?
membus_data_address-32'h20000:0);
// word address to byte-address
assign cmd_address = {addr[29:0],2'b0};
assign cmd_enable = mem_bootload?(spi_boot_write|spi_boot_read):
(is_mem_req?mem_enable&(membus_data_rd|
membus_data_wr):0);
assign cmd_wr = mem_bootload?spi_boot_write:
(is_mem_req?membus_data_wr:0);
assign cmd_data_in = mem_bootload?spi_boot_word:
(is_mem_req?membus_data_out:0);
parameter MEM_IDLE = 0;
parameter MEM_READ = 1;
parameter MEM_WRITE = 2;
parameter MEM_WAIT_RD0 = 3;
parameter MEM_WAIT_WR0 = 4;
parameter MAP_READ = 5;
parameter MAP_WRITE = 6;
parameter MEM_READ_UART_IN = 7;
parameter MEM_READ0 = 8;
parameter MEM_READ1 = 9;
parameter MEM_READ_UART_IN1 = 10;
reg [5:0] mem_state;
reg [4:0] mem_ticks;
reg cpu_release_reset;
always @(posedge clk100mhz)
begin
if (!cpu_reset) begin
mem_state <= MEM_IDLE;
mem_enable <= 1'b0;
cpu_release_reset <= 1'b0;
membus_data_wr_ack <= 1'b0;
uart_in_data_out_en <= 1'b0;
uart_out_data_in <= 0;
membus_data_in <= 0;
membus_data_in_ready <= 0;
top_last_read <= 0;
top_last_addr <= 0;
mem_ticks <= 0;
mem_acc_irq <= 0;
FAILED_ADDR <= 0;
`ifdef SIMULATION
FINISH <= 0;
`endif
end else begin
case (mem_state)
MEM_IDLE: begin
if (cpu_force_reset)
cpu_release_reset <= 1; // Disable reset state
else if (!cpu_force_reset)
cpu_release_reset <= 0;
membus_data_in <= 0;
if (is_mem_req) begin
if (membus_data_rd && cmd_ready) begin
`ifdef SDRAMBUG
mem_state <= MEM_READ0;
`else
mem_state <= MEM_READ;
`endif
mem_ticks <= 0;
mem_enable <= 1;
end else if(membus_data_wr && cmd_ready) begin
mem_enable <= 1;
mem_state <= MEM_WRITE;
end else mem_enable <= 0;
end else begin
mem_enable <= 0;
if (membus_data_rd) begin
case (membus_data_address)
32'h10001: begin
if (!uart_in_empty) begin
uart_in_data_out_en <= 1;
mem_state <= MEM_READ_UART_IN;
end else mem_state <= MEM_IDLE; // keep trying
end
32'h10002: begin
membus_data_in <= {31'b0,~uart_in_empty};
membus_data_in_ready <= 1;
mem_state <= MEM_WAIT_RD0;
end
32'h10005: begin
membus_data_in <= {31'b0,~uart_out_full};
membus_data_in_ready <= 1;
mem_state <= MEM_WAIT_RD0;
end
default: begin
membus_data_in <= 0;
membus_data_in_ready <= 1;
mem_state <= MEM_WAIT_RD0;
mem_acc_irq <= 1;
FAILED_ADDR <= membus_data_address;
end
endcase // case (membus_data_address)
end else if(membus_data_wr) begin
case (membus_data_address)
32'h10004: begin
`ifdef DEBUG
$display("WRITING TO UART OUT [%c] %x",
membus_data_out[7:0], uart_out_full);
`endif
if (!uart_out_full) begin
uart_out_data_in <= membus_data_out;
uart_out_data_in_wr <= 1;
membus_data_wr_ack <= 1;
mem_state <= MEM_WAIT_WR0; // wait for CPU to release the write signal
end else mem_state <= MEM_IDLE; // keep trying
end // case: 32'h10004
`ifdef SIMULATION
32'h10111: begin
FINISH <= 1;
membus_data_wr_ack <= 1;
mem_state <= MEM_WAIT_WR0;
end
`endif
endcase
end
end
end // case: MEM_IDLE
MEM_READ_UART_IN: begin
uart_in_data_out_en <= 0;
mem_state <= MEM_READ_UART_IN1;
end
MEM_READ_UART_IN1: begin
mem_enable <= 0;
membus_data_in <= uart_in_data_out;
`ifdef DEBUG
$display("UART IN CONSUMED [%x]", uart_in_data_out);
`endif
uart_in_data_out_en <= 0;
membus_data_in_ready <= 1;
mem_state <= MEM_WAIT_RD0;
end
MEM_WRITE: begin
mem_enable <= 0;
if (cmd_ready) begin
mem_state <= MEM_WAIT_WR0;
membus_data_wr_ack <= 1;
end else mem_state <= MEM_WRITE;
end
`ifdef SDRAMBUG
MEM_READ0: begin
if (data_out_ready && cmd_ready) begin
mem_enable <= 0;
top_last_addr <= membus_data_address;
mem_state <= MEM_READ1;
end
end
MEM_READ1: begin // repeat
if (cmd_ready) begin
mem_enable <= 1;
mem_state <= MEM_READ;
end
end
`endif
MEM_READ: begin
if (data_out_ready && cmd_ready) begin
membus_data_in <= data_out;
top_last_read <= data_out;
`ifdef SDRAMBUG
if (data_out != top_last_read) begin
// TODO: log failure in debuggable registers
mem_state <= MEM_READ1;
end else begin
`endif
membus_data_in_ready <= 1;
mem_state <= MEM_WAIT_RD0;
`ifdef SDRAMBUG
end
`endif
end else mem_state <= MEM_READ;
end
MEM_WAIT_RD0: begin
mem_enable <= 0;
if (!membus_data_rd && cmd_ready) begin
mem_state <= MEM_IDLE;
membus_data_in_ready <= 0;
end
else mem_state <= MEM_WAIT_RD0;
end
MEM_WAIT_WR0: begin
mem_enable <= 0;
uart_out_data_in_wr <= 0; // release (TODO: separate always block?)
if (!membus_data_wr) begin
mem_state <= MEM_IDLE;
membus_data_wr_ack <= 0;
end
else mem_state <= MEM_WAIT_WR0;
end
endcase
end
end // always @ (posedge clk100mhz)
//// SPI controller
//
// Master will send command words:
// 0 - initiate bootload,
// Followed by 1 word of length and N words of data
// Forces a CPU reset when done filling memory
// 1 - poll for a word from UART fifo
// 2 - send a word to UART (followed by a word of data)
// 3 - reset, force a CPU reset
//
wire [31:0] spi_word;
wire spi_word_new;
assign spi_word = spi_data_out;
assign spi_word_new = spi_data_out_rdy && ~spi_data_out_ack;
parameter SPI_IDLE = 0;
parameter SPI_BOOTLOAD_START = 1;
parameter SPI_FIFO_POLL = 2;
parameter SPI_FIFO_SEND = 3;
parameter SPI_BOOTLOAD_NEXT = 4;
parameter SPI_BOOTLOAD_WRITE = 5;
parameter SPI_FIFO_READ = 6;
parameter SPI_FIFO_READ0 = 7;
parameter SPI_FIFO_READ_DUMMY = 8;
parameter SPI_BOOTLOAD_READ = 9;
parameter SPI_DEAD = 10;
parameter SPI_FIFO_SENDREG = 11;
parameter SPI_FIFO_POLLREG_WAIT = 12;
parameter SPI_DEBUGSTEP = 13;
parameter SPI_DEBUGWAIT = 14;
parameter SPI_GET_MEMADDR = 15;
parameter SPI_DEBUG_WAITREAD = 16;
parameter SPI_DEBUG_MEMSEND = 17;
parameter SPI_FIFO_POLLREG = 18;
parameter SPI_CMD_BOOTLOAD = 16'd99;
parameter SPI_CMD_POLL = 16'd1;
parameter SPI_CMD_SEND = 16'd2;
parameter SPI_CMD_RESET = 16'd3;
parameter SPI_CMD_POLLREG = 16'd4;
parameter SPI_CMD_DEBUGSTEP = 16'd5;
parameter SPI_CMD_DEBUGSTART = 16'd6;
parameter SPI_CMD_DEBUGSTOP = 16'd7;
parameter SPI_CMD_DEBUGMEM = 16'd8;
reg spi_word_consumed;
assign spi_data_out_ack = spi_word_consumed;
reg [15:0] spi_cmd_arg;
always @(posedge clk100mhz)
begin
if (!cpu_reset) begin
spi_state <= SPI_IDLE;
spi_word_consumed <= 0;
mem_bootload <= 1; // start in a bootload state, suspend CPU
spi_boot_write <= 0;
spi_boot_read <= 0;
uart_out_data_out_en <= 0;
uart_in_data_in_wr <= 0;
spi_boot_addr <= 0;
spi_boot_count <= 0;
led1 <= 0;
led0 <= 0;
spi_cmd_arg <= 0;
cpu_debug <= 0;
cpu_step <= 0;
debug_reg_num <= 0;
spi_word_send <= 32'h0;
spi_send_ready <= 0;
end else begin // if (!cpu_reset)
if (~spi_data_out_rdy) begin
spi_word_consumed <= 0;
end
case (spi_state)
SPI_IDLE: begin
uart_in_data_in_wr <= 0;
if (spi_send_done && spi_send_ready) begin
spi_send_ready <= 0;
end
if (cpu_release_reset)
cpu_force_reset <= 0;
if (spi_word_new) begin
`ifdef ATLYS
LED <= spi_word[7:0];
`endif
// The first word contains a command (maybe with an immediate)
spi_cmd_arg <= spi_word[31:16];
case(spi_word[15:0])
SPI_CMD_BOOTLOAD: begin
spi_state <= SPI_BOOTLOAD_START;
cpu_debug <= spi_word[16]; // turn on debugging on bootload time
end
SPI_CMD_POLL: spi_state <= SPI_FIFO_POLL;
SPI_CMD_SEND: spi_state <= SPI_FIFO_SEND;
SPI_CMD_POLLREG: begin
debug_reg_num <= spi_word[19:16];
spi_state <= SPI_FIFO_POLLREG;
end
SPI_CMD_DEBUGSTEP: spi_state <= SPI_DEBUGSTEP;
SPI_CMD_DEBUGSTART: begin
cpu_debug <= 1;
spi_state <= SPI_IDLE;
end
SPI_CMD_DEBUGSTOP: begin
cpu_debug <= 0;
spi_state <= SPI_IDLE;
end
SPI_CMD_DEBUGMEM: begin
spi_state <= SPI_GET_MEMADDR;
end
SPI_CMD_RESET: begin
spi_state <= SPI_IDLE;
cpu_force_reset <= 1;
end
//default: spi_state <= SPI_IDLE;
endcase // case (spi_word[1:0])
spi_word_consumed <= 1;
end
end // case: SPI_IDLE
SPI_GET_MEMADDR: begin
if (spi_word_new) begin
spi_word_consumed <= 1;
spi_boot_addr <= spi_word;
spi_boot_read <= 1;
mem_bootload <= 1; // reusing bootload checking mechanics
spi_state <= SPI_DEBUG_WAITREAD;
end
end
SPI_DEBUG_WAITREAD: begin
if (data_out_ready) begin
spi_boot_read <= 0;
mem_bootload <= 0;
spi_word_send <= data_out;
spi_send_ready <= 1;
spi_state <= SPI_DEBUG_MEMSEND;
end
end
SPI_DEBUG_MEMSEND: begin
if (spi_word_new) begin
spi_word_consumed <= 1;
spi_state <= SPI_IDLE;
end
end
SPI_FIFO_POLL: begin // Check if there is a word in an UART fifo
if (!uart_out_empty) begin
uart_out_data_out_en <= 1;
spi_state <= SPI_FIFO_READ0;
//led1 <= ~led1;
end else begin
spi_state <= SPI_FIFO_READ_DUMMY;
end
end
SPI_FIFO_READ0: begin
uart_out_data_out_en <= 0;
spi_state <= SPI_FIFO_READ;
end
SPI_FIFO_READ: begin // TODO: ?!?
spi_word_send <= uart_out_data_out;
spi_send_ready <= 1;
spi_state <= SPI_IDLE;
end
SPI_FIFO_POLLREG: begin
debug_reg_num <= spi_cmd_arg[3:0];
spi_state <= SPI_FIFO_SENDREG;
end
SPI_FIFO_SENDREG: begin
spi_word_send <= debug_reg_out;
spi_send_ready <= 1;
spi_state <= SPI_FIFO_POLLREG_WAIT;
end
SPI_FIFO_POLLREG_WAIT: begin
if (spi_word_new) begin
spi_state <= SPI_IDLE;
spi_word_consumed <= 1;
end
end
SPI_DEBUGSTEP: begin
cpu_step <= 1;
spi_state <= SPI_DEBUGWAIT;
end
SPI_DEBUGWAIT: begin
if (cpu_step_ack) begin
cpu_step <= 0;
spi_state <= SPI_IDLE;
end else if (spi_word_new) begin // waited for too long, CPU stuck
spi_state <= SPI_IDLE;
end
end
SPI_FIFO_READ_DUMMY: begin
spi_word_send <= 32'hffffffff;
spi_send_ready <= 1;
spi_state <= SPI_IDLE;
end
SPI_FIFO_SEND: begin // Push incoming word into an UART fifo
if (spi_word_new) begin
spi_word_consumed <= 1;
if (!uart_in_full) begin
uart_in_data_in <= spi_word;
`ifdef DEBUG
$display("UART IN [%x]\n", spi_word);
`endif
uart_in_data_in_wr <= 1;
spi_state <= SPI_IDLE;
end else begin
spi_state <= SPI_IDLE; // ???
end
end
end
SPI_BOOTLOAD_START: begin
if (spi_word_new) begin
// Next word is a number of words of data to be loaded
spi_boot_count <= spi_word;
`ifdef DEBUG
$display("Starting bootload, reading [%X] words", spi_word);
`endif
spi_boot_addr <= 0;
mem_bootload <= 1; // Hijack memory bus, suspend CPU
led1 <= 1;
led0 <= 0;
spi_state <= SPI_BOOTLOAD_NEXT;
spi_word_consumed <= 1;
end
end
SPI_BOOTLOAD_NEXT: begin
if (spi_word_new && cmd_ready) begin
spi_boot_word <= spi_word;
spi_boot_write <= 1;
spi_state <= SPI_BOOTLOAD_WRITE; // TODO: fifo?
spi_word_consumed <= 1;
end else if (spi_word_new && !cmd_ready) begin
spi_word_send <= {16'hdead,spi_boot_addr[15:0]}; spi_send_ready <= 1;
spi_state <= SPI_DEAD;
spi_word_consumed <= 1;
end else if (spi_word_new) begin
spi_word_consumed <= 1;
end
end
SPI_DEAD: begin
led0 <= clk_ctr[10];led1 <= clk_ctr[9];
spi_state <= SPI_DEAD;
end
SPI_BOOTLOAD_WRITE: begin
spi_boot_write <= 0;
if (cmd_ready) begin // writing done
spi_boot_read <= 1;
spi_state <= SPI_BOOTLOAD_READ;
end
end
SPI_BOOTLOAD_READ: begin
// spi_boot_read <= 0;
if (data_out_ready) begin // reading done
spi_boot_read <= 0;
spi_boot_addr <= spi_boot_addr + 1;
spi_boot_count <= spi_boot_count - 1;
spi_word_send <= data_out; spi_send_ready <= 1; // Verification
if (spi_boot_count>1)
spi_state <= SPI_BOOTLOAD_NEXT;
else begin
mem_bootload <= 0;
cpu_force_reset <= 1;
led0 <= 1;
led1 <= 1; // indicate that program is in
`ifdef DEBUG
$display("Bootload sequence done");
`endif
spi_state <= SPI_IDLE;
end
end
end
endcase
end
end // always @ (posedge clk)
// Interrupts. TODO: add timers
always @(posedge clk100mhz) begin
if (!cpu_reset) begin
cpu_irq <= 0;
end else begin
if (cpu_irq_ack) begin
cpu_irq <= 0;
end else
if (!uart_in_empty && !cpu_irq_busy) begin
cpu_irq <= 1;
cpu_irqn <= 0; // UART IRQ
end else if (mem_acc_irq) begin
cpu_irq <= 1;
cpu_irqn <= 6; // mem trap IRQ
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_SYMBOL_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_SYMBOL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd3 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_1_V
`define SKY130_FD_SC_MS__FAHCON_1_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog wrapper for fahcon with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fahcon.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__TAP_BEHAVIORAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4B_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A311OI_FUNCTIONAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_FUNCTIONAL_PP_V |
// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
// Component : VexRiscv
// Git hash : 5faa2eb26b83d3074089934f54d9526fa856225c
`define Input2Kind_binary_sequential_type [0:0]
`define Input2Kind_binary_sequential_RS 1'b0
`define Input2Kind_binary_sequential_IMM_I 1'b1
`define EnvCtrlEnum_binary_sequential_type [1:0]
`define EnvCtrlEnum_binary_sequential_NONE 2'b00
`define EnvCtrlEnum_binary_sequential_XRET 2'b01
`define EnvCtrlEnum_binary_sequential_WFI 2'b10
`define EnvCtrlEnum_binary_sequential_ECALL 2'b11
`define BranchCtrlEnum_binary_sequential_type [1:0]
`define BranchCtrlEnum_binary_sequential_INC 2'b00
`define BranchCtrlEnum_binary_sequential_B 2'b01
`define BranchCtrlEnum_binary_sequential_JAL 2'b10
`define BranchCtrlEnum_binary_sequential_JALR 2'b11
`define ShiftCtrlEnum_binary_sequential_type [1:0]
`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11
`define AluBitwiseCtrlEnum_binary_sequential_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10
`define Src2CtrlEnum_binary_sequential_type [1:0]
`define Src2CtrlEnum_binary_sequential_RS 2'b00
`define Src2CtrlEnum_binary_sequential_IMI 2'b01
`define Src2CtrlEnum_binary_sequential_IMS 2'b10
`define Src2CtrlEnum_binary_sequential_PC 2'b11
`define AluCtrlEnum_binary_sequential_type [1:0]
`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequential_BITWISE 2'b10
`define Src1CtrlEnum_binary_sequential_type [1:0]
`define Src1CtrlEnum_binary_sequential_RS 2'b00
`define Src1CtrlEnum_binary_sequential_IMU 2'b01
`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10
`define Src1CtrlEnum_binary_sequential_URS1 2'b11
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg streamFifoLowLatency_1_io_pop_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire streamFifoLowLatency_1_io_push_ready;
wire streamFifoLowLatency_1_io_pop_valid;
wire [31:0] streamFifoLowLatency_1_io_pop_payload_outputs_0;
wire [1:0] streamFifoLowLatency_1_io_occupancy;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [2:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
reg CsrPlugin_inWfi /* verilator public */ ;
wire CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire CsrPlugin_allowEbreakException;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
reg [1:0] CsrPlugin_misa_base;
reg [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg [31:0] CsrPlugin_mscratch;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
reg CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1108;
wire when_CsrPlugin_l1110;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1129;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire when_CfuPlugin_l208;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_52;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_54;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_57;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_60;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_61;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_62;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_3857;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_3858;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_3859;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_3860;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_769;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_832;
wire when_CsrPlugin_l1264_12;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_13;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_14;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_15;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_16;
reg execute_CsrPlugin_csr_2818;
wire when_CsrPlugin_l1264_17;
reg execute_CsrPlugin_csr_2946;
wire when_CsrPlugin_l1264_18;
reg execute_CsrPlugin_csr_3072;
wire when_CsrPlugin_l1264_19;
reg execute_CsrPlugin_csr_3200;
wire when_CsrPlugin_l1264_20;
reg execute_CsrPlugin_csr_3074;
wire when_CsrPlugin_l1264_21;
reg execute_CsrPlugin_csr_3202;
wire when_CsrPlugin_l1264_22;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_23;
reg execute_CsrPlugin_csr_4032;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [2:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h00203050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00002040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00002040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00001040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h00001040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00400040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0;
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
StreamFifoLowLatency streamFifoLowLatency_1 (
.io_push_valid (CfuPlugin_bus_rsp_valid ), //i
.io_push_ready (streamFifoLowLatency_1_io_push_ready ), //o
.io_push_payload_outputs_0 (CfuPlugin_bus_rsp_payload_outputs_0 ), //i
.io_pop_valid (streamFifoLowLatency_1_io_pop_valid ), //o
.io_pop_ready (streamFifoLowLatency_1_io_pop_ready ), //i
.io_pop_payload_outputs_0 (streamFifoLowLatency_1_io_pop_payload_outputs_0 ), //o
.io_flush (1'b0 ), //i
.io_occupancy (streamFifoLowLatency_1_io_occupancy ), //o
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = streamFifoLowLatency_1_io_pop_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1108) begin
if(when_CsrPlugin_l1110) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
always @(*) begin
CsrPlugin_inWfi = 1'b0;
if(when_CsrPlugin_l1108) begin
CsrPlugin_inWfi = 1'b1;
end
end
assign CsrPlugin_thirdPartyWake = 1'b0;
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign CsrPlugin_allowEbreakException = 1'b1;
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake);
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3857) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3858) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3859) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3860) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_769) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_832) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_835) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2816) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2944) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2818) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2946) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_3072) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3200) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3074) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3202) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_valid = 1'b1;
end
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_payload_code = 4'b0010;
end
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction);
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = 1'b1;
always @(*) begin
streamFifoLowLatency_1_io_pop_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
streamFifoLowLatency_1_io_pop_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! streamFifoLowLatency_1_io_pop_valid);
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000;
_zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0;
if(execute_CsrPlugin_csr_3857) begin
_zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0;
if(execute_CsrPlugin_csr_3858) begin
_zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0;
if(execute_CsrPlugin_csr_3859) begin
_zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0;
if(execute_CsrPlugin_csr_769) begin
_zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base;
_zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_773) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base;
_zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_832) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0;
if(execute_CsrPlugin_csr_2818) begin
_zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0;
if(execute_CsrPlugin_csr_2946) begin
_zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0;
if(execute_CsrPlugin_csr_3072) begin
_zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0;
if(execute_CsrPlugin_csr_3200) begin
_zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0;
if(execute_CsrPlugin_csr_3074) begin
_zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0;
if(execute_CsrPlugin_csr_3202) begin
_zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24))));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_misa_base <= 2'b01;
CsrPlugin_misa_extensions <= 26'h0000042;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_lastStageWasWfi <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 3'b000;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(when_Pipeline_l124_61) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
if(execute_CsrPlugin_csr_769) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30];
CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0];
end
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 3'b000;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_52) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_54) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_55) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_60) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_62) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340);
end
if(when_CsrPlugin_l1264_12) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_13) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_14) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_15) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_16) begin
execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02);
end
if(when_CsrPlugin_l1264_17) begin
execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82);
end
if(when_CsrPlugin_l1264_18) begin
execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00);
end
if(when_CsrPlugin_l1264_19) begin
execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80);
end
if(when_CsrPlugin_l1264_20) begin
execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02);
end
if(when_CsrPlugin_l1264_21) begin
execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82);
end
if(when_CsrPlugin_l1264_22) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_23) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_832) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31];
CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0];
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2818) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2946) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
endmodule
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input [31:0] io_push_payload_outputs_0,
output reg io_pop_valid,
input io_pop_ready,
output reg [31:0] io_pop_payload_outputs_0,
input io_flush,
output [1:0] io_occupancy,
input clk,
input reset
);
wire [31:0] _zz_ram_port0;
wire [31:0] _zz_io_pop_payload_outputs_0;
reg _zz_1;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
reg [0:0] pushPtr_valueNext;
reg [0:0] pushPtr_value;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
reg [0:0] popPtr_valueNext;
reg [0:0] popPtr_value;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire when_Stream_l995;
wire when_Stream_l1008;
wire [0:0] ptrDif;
(* ram_style = "distributed" *) reg [31:0] ram [0:1];
assign _zz_io_pop_payload_outputs_0 = _zz_ram_port0[31 : 0];
assign _zz_ram_port0 = ram[popPtr_value];
always @(posedge clk) begin
if(_zz_1) begin
ram[pushPtr_value] <= io_push_payload_outputs_0;
end
end
always @(*) begin
_zz_1 = 1'b0;
if(pushing) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
pushPtr_willIncrement = 1'b0;
if(pushing) begin
pushPtr_willIncrement = 1'b1;
end
end
always @(*) begin
pushPtr_willClear = 1'b0;
if(io_flush) begin
pushPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = (pushPtr_value == 1'b1);
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @(*) begin
pushPtr_valueNext = (pushPtr_value + pushPtr_willIncrement);
if(pushPtr_willClear) begin
pushPtr_valueNext = 1'b0;
end
end
always @(*) begin
popPtr_willIncrement = 1'b0;
if(popping) begin
popPtr_willIncrement = 1'b1;
end
end
always @(*) begin
popPtr_willClear = 1'b0;
if(io_flush) begin
popPtr_willClear = 1'b1;
end
end
assign popPtr_willOverflowIfInc = (popPtr_value == 1'b1);
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
always @(*) begin
popPtr_valueNext = (popPtr_value + popPtr_willIncrement);
if(popPtr_willClear) begin
popPtr_valueNext = 1'b0;
end
end
assign ptrMatch = (pushPtr_value == popPtr_value);
assign empty = (ptrMatch && (! risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (! full);
assign when_Stream_l995 = (! empty);
always @(*) begin
if(when_Stream_l995) begin
io_pop_valid = 1'b1;
end else begin
io_pop_valid = io_push_valid;
end
end
always @(*) begin
if(when_Stream_l995) begin
io_pop_payload_outputs_0 = _zz_io_pop_payload_outputs_0[31 : 0];
end else begin
io_pop_payload_outputs_0 = io_push_payload_outputs_0;
end
end
assign when_Stream_l1008 = (pushing != popping);
assign ptrDif = (pushPtr_value - popPtr_value);
assign io_occupancy = {(risingOccupancy && ptrMatch),ptrDif};
always @(posedge clk) begin
if(reset) begin
pushPtr_value <= 1'b0;
popPtr_value <= 1'b0;
risingOccupancy <= 1'b0;
end else begin
pushPtr_value <= pushPtr_valueNext;
popPtr_value <= popPtr_valueNext;
if(when_Stream_l1008) begin
risingOccupancy <= pushing;
end
if(io_flush) begin
risingOccupancy <= 1'b0;
end
end
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [2:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [21:0] _zz_ways_0_tags_port;
wire [9:0] _zz_stage0_dataColisions;
wire [9:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [2:0] _zz_loader_counter_valueNext;
wire [0:0] _zz_loader_counter_valueNext_1;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [6:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [6:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [6:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [19:0] ways_0_tagsReadRsp_address;
wire [21:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [7:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [2:0] loader_counter_valueNext;
reg [2:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement;
assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1};
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 7'bxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 5];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 10'bxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 7'bxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[6:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 10'bxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[7]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[4 : 0] = 5'h0;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = {1'd0, stageB_request_size};
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 3'b101;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext);
if(loader_counter_willClear) begin
loader_counter_valueNext = 3'b000;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 8'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 3'b000;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 8'h01);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 8'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [21:0] _zz_ways_0_tags_port1;
wire [21:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [7:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [6:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [19:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [9:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [19:0] fetchStage_read_waysValues_0_tag_address;
wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [31:0] banks_0 [0:1023];
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 8'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__OR2_PP_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_PP_SYMBOL_V
|
/* Generated by Yosys 0.7 (git sha1 61f6811, gcc 5.4.0-6ubuntu1~16.04.4 -O2 -fstack-protector-strong -fPIC -Os) */
(* top = 1 *)
(* src = "var14_multi.v:2" *)
module var14_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire _316_;
wire _317_;
wire _318_;
wire _319_;
wire _320_;
wire _321_;
wire _322_;
wire _323_;
wire _324_;
wire _325_;
wire _326_;
wire _327_;
wire _328_;
wire _329_;
wire _330_;
wire _331_;
wire _332_;
wire _333_;
wire _334_;
wire _335_;
wire _336_;
wire _337_;
wire _338_;
wire _339_;
wire _340_;
wire _341_;
wire _342_;
wire _343_;
wire _344_;
wire _345_;
wire _346_;
wire _347_;
wire _348_;
wire _349_;
wire _350_;
wire _351_;
wire _352_;
wire _353_;
wire _354_;
wire _355_;
wire _356_;
wire _357_;
wire _358_;
wire _359_;
wire _360_;
wire _361_;
(* src = "var14_multi.v:3" *)
input A;
(* src = "var14_multi.v:3" *)
input B;
(* src = "var14_multi.v:3" *)
input C;
(* src = "var14_multi.v:3" *)
input D;
(* src = "var14_multi.v:3" *)
input E;
(* src = "var14_multi.v:3" *)
input F;
(* src = "var14_multi.v:3" *)
input G;
(* src = "var14_multi.v:3" *)
input H;
(* src = "var14_multi.v:3" *)
input I;
(* src = "var14_multi.v:3" *)
input J;
(* src = "var14_multi.v:3" *)
input K;
(* src = "var14_multi.v:3" *)
input L;
(* src = "var14_multi.v:3" *)
input M;
(* src = "var14_multi.v:3" *)
input N;
(* src = "var14_multi.v:9" *)
wire [7:0] total_value;
(* src = "var14_multi.v:4" *)
output valid;
assign _060_ = ~N;
assign _071_ = ~J;
assign _082_ = ~(B ^ A);
assign _093_ = _082_ ^ _071_;
assign _104_ = ~(_093_ & K);
assign _115_ = B & A;
assign _126_ = ~(B | A);
assign _137_ = J ? _115_ : _126_;
assign _148_ = _137_ ^ _104_;
assign _159_ = _148_ & L;
assign _170_ = _115_ ^ C;
assign _181_ = _170_ ^ D;
assign _192_ = _181_ ^ G;
assign _203_ = _192_ ^ H;
assign _214_ = _203_ ^ I;
assign _235_ = _126_ & J;
assign _236_ = _235_ ^ _214_;
assign _247_ = _236_ ^ K;
assign _258_ = _247_ & _159_;
assign _269_ = ~(_137_ | _104_);
assign _280_ = _236_ & K;
assign _299_ = _280_ | _269_;
assign _300_ = ~_126_;
assign _301_ = ~((_214_ | _300_) & J);
assign _302_ = ~I;
assign _303_ = _203_ | _302_;
assign _304_ = ~(_170_ & D);
assign _305_ = B ^ A;
assign _306_ = D & C;
assign _307_ = _306_ & _305_;
assign _308_ = ~(_115_ & C);
assign _309_ = _308_ & _082_;
assign _310_ = ~((_309_ & _304_) | _307_);
assign _311_ = _310_ ^ F;
assign _312_ = _181_ & G;
assign _313_ = ~((_192_ & H) | _312_);
assign _314_ = ~(_313_ ^ _311_);
assign _315_ = _314_ ^ J;
assign _316_ = _315_ ^ _303_;
assign _317_ = _316_ ^ _301_;
assign _318_ = _317_ ^ _299_;
assign _319_ = _318_ ^ _258_;
assign _320_ = _319_ & M;
assign _321_ = _319_ ^ M;
assign _322_ = _148_ ^ L;
assign _323_ = _093_ ^ K;
assign _324_ = _323_ & M;
assign _325_ = _324_ & _322_;
assign _326_ = ~(_159_ | _269_);
assign _327_ = ~(_326_ ^ _247_);
assign _328_ = _327_ & _325_;
assign _329_ = _328_ & _321_;
assign _330_ = _329_ | _320_;
assign _331_ = _318_ & _258_;
assign _332_ = _317_ & _299_;
assign _333_ = _126_ | _071_;
assign _334_ = _214_ | _333_;
assign _335_ = ~((_314_ | _214_) & J);
assign _336_ = ~((_334_ | _316_) & _335_);
assign _337_ = _314_ | _203_;
assign _338_ = _337_ & I;
assign _339_ = ~(_311_ & _312_);
assign _340_ = ~F;
assign _341_ = ~(_310_ | _340_);
assign _342_ = ~C;
assign _343_ = ~D;
assign _344_ = _115_ | _343_;
assign _345_ = ~((_344_ | _342_) & _300_);
assign _346_ = _345_ ^ _341_;
assign _347_ = ~(_346_ ^ _339_);
assign _348_ = _192_ & H;
assign _349_ = ~(_311_ & _348_);
assign _350_ = ~(_349_ & H);
assign _351_ = _350_ ^ _347_;
assign _352_ = _351_ ^ _338_;
assign _353_ = _352_ ^ _336_;
assign _354_ = _353_ ^ _332_;
assign _355_ = _354_ ^ _331_;
assign _356_ = ~(_355_ ^ _330_);
assign _357_ = ~(_323_ | M);
assign _358_ = _322_ ? _324_ : _357_;
assign _359_ = ~_358_;
assign _360_ = _359_ & _327_;
assign _361_ = ~(_360_ & _321_);
assign _000_ = _361_ | _356_;
assign _001_ = _328_ ^ _321_;
assign _002_ = ~(_327_ | _325_);
assign _003_ = ~((_002_ | _328_) & _358_);
assign _004_ = ~(_003_ | _001_);
assign _005_ = ~((_004_ & _356_) | (_000_ & _060_));
assign _006_ = ~(_354_ & _331_);
assign _007_ = _351_ & _338_;
assign _008_ = ~H;
assign _009_ = ~((_347_ | _008_) & _349_);
assign _010_ = ~(_346_ | _339_);
assign _011_ = _307_ | _115_;
assign _012_ = _309_ & _304_;
assign _013_ = _012_ | _307_;
assign _014_ = ~((_345_ & _013_) | _340_);
assign _015_ = _014_ ^ _011_;
assign _016_ = _015_ ^ _010_;
assign _017_ = _016_ ^ _009_;
assign _018_ = ~(_017_ ^ _007_);
assign _019_ = _352_ & _336_;
assign _020_ = ~((_353_ & _332_) | _019_);
assign _021_ = ~(_020_ ^ _018_);
assign _022_ = _355_ & _330_;
assign _023_ = ~(_021_ ^ _022_);
assign _024_ = _006_ ? _023_ : _021_;
assign _025_ = ~_021_;
assign _026_ = _025_ & _022_;
assign _027_ = E ^ D;
assign _028_ = C ? _343_ : _027_;
assign _029_ = _306_ ^ A;
assign _030_ = ~E;
assign _031_ = ~((_343_ & _342_) | _030_);
assign _032_ = _031_ ^ _029_;
assign _033_ = _032_ ^ F;
assign _034_ = ~((_033_ | _028_) & G);
assign _035_ = ~(_032_ | _340_);
assign _036_ = A & D;
assign _037_ = ~(_036_ | _342_);
assign _038_ = _037_ ^ _082_;
assign _039_ = ~(_031_ & _029_);
assign _040_ = _039_ & E;
assign _041_ = _040_ ^ _038_;
assign _042_ = _041_ ^ _035_;
assign _043_ = ~(_042_ | _034_);
assign _044_ = _041_ & _035_;
assign _045_ = ~((_038_ | _030_) & _039_);
assign _046_ = ~B;
assign _047_ = _046_ | A;
assign _048_ = ~A;
assign _049_ = ~((B | _048_) & _342_);
assign _050_ = ~((_049_ & _047_) | D);
assign _051_ = B | _048_;
assign _052_ = ~((_046_ | A) & C);
assign _053_ = ~((_052_ & _051_) | _343_);
assign _054_ = ~((_053_ & _308_) | _050_);
assign _055_ = _054_ ^ E;
assign _056_ = _055_ ^ _045_;
assign _057_ = _056_ ^ _044_;
assign _058_ = ~(_057_ & _043_);
assign _059_ = _055_ & _045_;
assign _061_ = _054_ & E;
assign _062_ = _306_ & A;
assign _063_ = ~(_049_ & _047_);
assign _064_ = _063_ | _343_;
assign _065_ = ~((_115_ | C) & _300_);
assign _066_ = ~((_065_ & _064_) | _062_);
assign _067_ = _066_ | _061_;
assign _068_ = ~((_067_ | _059_) & _039_);
assign _069_ = ~(_040_ ^ _038_);
assign _070_ = ~(_069_ | _032_);
assign _072_ = ~(_055_ ^ _045_);
assign _073_ = ~((_072_ & _070_) | _340_);
assign _074_ = _073_ ^ _068_;
assign _075_ = _028_ ^ G;
assign _076_ = E ^ C;
assign _077_ = _076_ & H;
assign _078_ = _077_ & _075_;
assign _079_ = ~G;
assign _080_ = ~(_028_ | _079_);
assign _081_ = _080_ ^ _033_;
assign _083_ = ~(_081_ & _078_);
assign _084_ = ~(_042_ ^ _034_);
assign _085_ = _084_ | _083_;
assign _086_ = ~(_057_ ^ _043_);
assign _087_ = ~((_086_ | _085_) & (_074_ | _058_));
assign _088_ = ~((_074_ & _058_) | _087_);
assign _089_ = ~(_086_ ^ _085_);
assign _090_ = _042_ ^ _034_;
assign _091_ = _081_ ^ _078_;
assign _092_ = ~(_091_ & _090_);
assign _094_ = ~((_092_ & _089_) | _302_);
assign _095_ = ~(_094_ ^ _088_);
assign _096_ = ~K;
assign _097_ = _076_ ^ H;
assign _098_ = _097_ & K;
assign _099_ = ~(_098_ & _075_);
assign _100_ = _091_ ^ _302_;
assign _101_ = ~((_100_ | _096_) & _099_);
assign _102_ = ~(_091_ & I);
assign _103_ = _102_ & _083_;
assign _105_ = _103_ ^ _084_;
assign _106_ = _105_ & _101_;
assign _107_ = _092_ & I;
assign _108_ = ~(_107_ ^ _089_);
assign _109_ = ~(_108_ & _106_);
assign _110_ = _108_ ^ _106_;
assign _111_ = _105_ ^ _101_;
assign _112_ = _111_ & L;
assign _113_ = _099_ & K;
assign _114_ = ~(_113_ ^ _100_);
assign _116_ = _097_ ^ K;
assign _117_ = _116_ & L;
assign _118_ = ~(_098_ | _077_);
assign _119_ = ~(_118_ ^ _075_);
assign _120_ = _119_ & _117_;
assign _121_ = _120_ | _114_;
assign _122_ = _121_ & L;
assign _123_ = ~((_122_ | _112_) & _110_);
assign _124_ = _123_ & _109_;
assign _125_ = ~(_124_ ^ _095_);
assign _127_ = ~L;
assign _128_ = ~(_121_ | _127_);
assign _129_ = _128_ ^ _111_;
assign _130_ = _129_ & M;
assign _131_ = _122_ | _112_;
assign _132_ = _131_ ^ _110_;
assign _133_ = _132_ ^ _130_;
assign _134_ = ~(_120_ | _127_);
assign _135_ = ~(_134_ ^ _114_);
assign _136_ = _129_ ^ M;
assign _138_ = _119_ ^ _117_;
assign _139_ = ~(_138_ | _136_);
assign _140_ = ~((_139_ & _135_) | _060_);
assign _141_ = ~(_140_ & _133_);
assign _142_ = ~(_132_ & _130_);
assign _143_ = _142_ | _125_;
assign _144_ = _021_ | _006_;
assign _145_ = G ^ E;
assign _146_ = _145_ ^ H;
assign _147_ = ~(G & E);
assign _149_ = A ^ D;
assign _150_ = _149_ ^ _340_;
assign _151_ = _150_ ^ _147_;
assign _152_ = ~((_151_ | _146_) & I);
assign _153_ = ~(_150_ | _147_);
assign _154_ = _149_ | _340_;
assign _155_ = _036_ ^ B;
assign _156_ = _155_ ^ _030_;
assign _157_ = _156_ ^ _154_;
assign _158_ = _157_ ^ _153_;
assign _160_ = _145_ & H;
assign _161_ = _150_ & _160_;
assign _162_ = _161_ | _008_;
assign _163_ = _162_ | _151_;
assign _164_ = _163_ ^ _158_;
assign _165_ = ~(_164_ | _152_);
assign _166_ = ~_161_;
assign _167_ = ~(_158_ | _151_);
assign _168_ = ~((_167_ | _008_) & _166_);
assign _169_ = _157_ & _153_;
assign _171_ = ~(_155_ & E);
assign _172_ = E & D;
assign _173_ = _172_ & _305_;
assign _174_ = ~((_171_ & _344_) | _173_);
assign _175_ = ~_149_;
assign _176_ = ~((_156_ & _175_) | _340_);
assign _177_ = _176_ ^ _174_;
assign _178_ = _177_ ^ G;
assign _179_ = _178_ ^ _169_;
assign _180_ = _179_ ^ _168_;
assign _182_ = _180_ ^ _165_;
assign _183_ = ~(_164_ ^ _152_);
assign _184_ = ~(_145_ | _008_);
assign _185_ = _184_ ^ _151_;
assign _186_ = ~_185_;
assign _187_ = _146_ ^ _302_;
assign _188_ = _187_ & _186_;
assign _189_ = ~((_188_ & _183_) | _071_);
assign _190_ = _189_ ^ _182_;
assign _191_ = _187_ & J;
assign _193_ = ~(_187_ | J);
assign _194_ = ~(_193_ | _191_);
assign _195_ = ~_194_;
assign _196_ = ~(_146_ | _302_);
assign _197_ = _196_ ^ _185_;
assign _198_ = _191_ ? _186_ : _197_;
assign _199_ = _198_ | _195_;
assign _200_ = ~_199_;
assign _201_ = _200_ & _183_;
assign _202_ = ~_201_;
assign _204_ = _202_ | _190_;
assign _205_ = _204_ & K;
assign _206_ = _189_ & _182_;
assign _207_ = _177_ & G;
assign _208_ = _178_ & _169_;
assign _209_ = _208_ | _207_;
assign _210_ = ~(_176_ & _174_);
assign _211_ = ~((_115_ & D) | _173_);
assign _212_ = _211_ & _210_;
assign _213_ = _212_ ^ _209_;
assign _215_ = _179_ & _168_;
assign _216_ = ~((_180_ & _165_) | _215_);
assign _217_ = ~(_216_ ^ _213_);
assign _218_ = ~(_217_ ^ _206_);
assign _219_ = ~(_218_ & _205_);
assign _220_ = ~_206_;
assign _221_ = _217_ | _220_;
assign _222_ = ~_212_;
assign _223_ = _222_ & _209_;
assign _224_ = _222_ | _209_;
assign _225_ = ~((_223_ | _215_) & _224_);
assign _226_ = ~(_180_ & _165_);
assign _227_ = _213_ | _226_;
assign _228_ = _227_ & _225_;
assign _229_ = _228_ & _221_;
assign _230_ = ~(_353_ & _332_);
assign _231_ = _072_ & _070_;
assign _232_ = _231_ | _340_;
assign _233_ = ~((_031_ & _029_) | _062_);
assign _234_ = ~((_232_ | _068_) & _233_);
assign _237_ = _234_ | _087_;
assign _238_ = ~((_094_ & _088_) | _237_);
assign _239_ = ~((_018_ | _230_) & _238_);
assign _240_ = ~(_016_ & _009_);
assign _241_ = _115_ & F;
assign _242_ = ~((_015_ & _010_) | _241_);
assign _243_ = _242_ & _240_;
assign _244_ = _017_ & _007_;
assign _245_ = _017_ | _007_;
assign _246_ = ~((_245_ & _019_) | _244_);
assign _248_ = ~((_246_ | _243_) & (_109_ | _095_));
assign _249_ = _248_ | _239_;
assign _250_ = ~(_246_ ^ _243_);
assign _251_ = ~((_123_ | _095_) & _250_);
assign _252_ = _251_ | _249_;
assign _253_ = ~((_229_ & _219_) | _252_);
assign _254_ = _253_ & _144_;
assign _255_ = _254_ & _143_;
assign _256_ = ~((_141_ | _125_) & _255_);
assign _257_ = _256_ | _026_;
assign _259_ = ~(_199_ | _096_);
assign _260_ = _191_ & _186_;
assign _261_ = _260_ ^ _183_;
assign _262_ = _261_ & _259_;
assign _263_ = _262_ ^ _190_;
assign _264_ = ~(_263_ | M);
assign _265_ = _218_ ^ _205_;
assign _266_ = _261_ ^ _259_;
assign _267_ = _266_ & _127_;
assign _268_ = ~_267_;
assign _270_ = ~((_268_ | N) & _265_);
assign _271_ = ~(_266_ | _127_);
assign _272_ = ~(_198_ | K);
assign _273_ = ~_272_;
assign _274_ = ~((_195_ & K) | _060_);
assign _275_ = ~_274_;
assign _276_ = ~((_197_ & _194_) | _275_);
assign _277_ = _276_ & _273_;
assign _278_ = ~((_277_ | _265_) & _271_);
assign _279_ = ~((_278_ & _270_) | _264_);
assign _281_ = ~(_267_ | _060_);
assign _282_ = _281_ | _277_;
assign _283_ = ~(_282_ | _265_);
assign _284_ = ~((_282_ & _265_) | (_263_ & M));
assign _285_ = ~((_284_ | _283_) & (_229_ | _219_));
assign _286_ = _138_ | _060_;
assign _287_ = _135_ ? _139_ : _286_;
assign _288_ = _116_ ^ L;
assign _289_ = ~((_138_ & _060_) | _288_);
assign _290_ = ~((_135_ & N) | _136_);
assign _291_ = ~((_289_ & _286_) | _290_);
assign _292_ = _291_ & _287_;
assign _293_ = ~(_292_ & _141_);
assign _294_ = _142_ & _125_;
assign _295_ = ~((_140_ | _133_) & _143_);
assign _296_ = _295_ | _294_;
assign _297_ = ~((_296_ | _293_) & (_285_ | _279_));
assign _298_ = _297_ | _257_;
assign valid = ~((_024_ & _005_) | _298_);
assign total_value[0] = J;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: counter.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple up-counter. The maximum value is the largest expected
// value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE,
// the counter will roll over and never stop. On RST_IN, the counter
// synchronously resets to the RST_VALUE
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module counter
#(parameter C_MAX_VALUE = 10,
parameter C_SAT_VALUE = 10,
parameter C_RST_VALUE = 0)
(
input CLK,
input RST_IN,
input ENABLE,
output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
);
wire wEnable;
reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue;
reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue;
/* verilator lint_off WIDTH */
assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);
/* verilator lint_on WIDTH */
assign VALUE = rCtrValue;
always @(posedge CLK) begin
if(RST_IN) begin
rCtrValue <= C_RST_VALUE;
end else if(wEnable) begin
rCtrValue <= rCtrValue + 1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V |
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`timescale 1ns/1ns
module unitTestNext();
reg clk;
wire rst;
reg start;
reg test_expr;
wire inv;
wire assert;
initial begin
clk = 1'b0;
start = 1'b0;
test_expr = 1'b0;
end
assign rst = 1'b0;
assign inv = 1'b0;
always begin
#10 clk = ~clk;
#10 clk = ~clk;
// Make sure missing start doesn't fire
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test to make sure test can fire early and stay late as long as it is valid at num cks
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start =1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test normal operation
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test for assertion violations
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
// Test for overlapping starts
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
start = 1'b0;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b1;
#10 clk = ~clk;
#10 clk = ~clk;
test_expr = 1'b0;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
#10 clk = ~clk;
end
ovl_next_wrapped onw(
.clk(clk),
.rst(rst),
.num_cks(3'd3),
.start_event(start),
.test_expr(test_expr),
.prevConfigInvalid(inv),
.out(assert)
);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_BEHAVIORAL_PP_V |
// megafunction wizard: %altmemphy v15.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// nios_altmemddr_0_phy_alt_mem_phy
// ============================================================
// Generated by altmemphy 15.1 [Altera, IP Toolbench 1.3.0 Build 185]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module nios_altmemddr_0_phy (
pll_ref_clk,
global_reset_n,
soft_reset_n,
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_mem_clk_disable,
ctl_doing_rd,
ctl_cal_req,
ctl_cal_byte_lane_sel_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
reset_request_n,
ctl_clk,
ctl_reset_n,
ctl_wlat,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_reset_n,
dbg_rd_data,
dbg_waitrequest,
aux_half_rate_clk,
aux_full_rate_clk,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqs_n);
input pll_ref_clk;
input global_reset_n;
input soft_reset_n;
input [1:0] ctl_dqs_burst;
input [1:0] ctl_wdata_valid;
input [31:0] ctl_wdata;
input [3:0] ctl_dm;
input [27:0] ctl_addr;
input [3:0] ctl_ba;
input [1:0] ctl_cas_n;
input [1:0] ctl_cke;
input [1:0] ctl_cs_n;
input [1:0] ctl_odt;
input [1:0] ctl_ras_n;
input [1:0] ctl_we_n;
input [1:0] ctl_rst_n;
input [0:0] ctl_mem_clk_disable;
input [1:0] ctl_doing_rd;
input ctl_cal_req;
input [0:0] ctl_cal_byte_lane_sel_n;
input dbg_clk;
input dbg_reset_n;
input [12:0] dbg_addr;
input dbg_wr;
input dbg_rd;
input dbg_cs;
input [31:0] dbg_wr_data;
output reset_request_n;
output ctl_clk;
output ctl_reset_n;
output [4:0] ctl_wlat;
output [31:0] ctl_rdata;
output [1:0] ctl_rdata_valid;
output [4:0] ctl_rlat;
output ctl_cal_success;
output ctl_cal_fail;
output ctl_cal_warning;
output [13:0] mem_addr;
output [1:0] mem_ba;
output mem_cas_n;
output [0:0] mem_cke;
output [0:0] mem_cs_n;
output [0:0] mem_dm;
output [0:0] mem_odt;
output mem_ras_n;
output mem_we_n;
output mem_reset_n;
output [31:0] dbg_rd_data;
output dbg_waitrequest;
output aux_half_rate_clk;
output aux_full_rate_clk;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [7:0] mem_dq;
inout [0:0] mem_dqs;
inout [0:0] mem_dqs_n;
nios_altmemddr_0_phy_alt_mem_phy nios_altmemddr_0_phy_alt_mem_phy_inst(
.pll_ref_clk(pll_ref_clk),
.global_reset_n(global_reset_n),
.soft_reset_n(soft_reset_n),
.ctl_dqs_burst(ctl_dqs_burst),
.ctl_wdata_valid(ctl_wdata_valid),
.ctl_wdata(ctl_wdata),
.ctl_dm(ctl_dm),
.ctl_addr(ctl_addr),
.ctl_ba(ctl_ba),
.ctl_cas_n(ctl_cas_n),
.ctl_cke(ctl_cke),
.ctl_cs_n(ctl_cs_n),
.ctl_odt(ctl_odt),
.ctl_ras_n(ctl_ras_n),
.ctl_we_n(ctl_we_n),
.ctl_rst_n(ctl_rst_n),
.ctl_mem_clk_disable(ctl_mem_clk_disable),
.ctl_doing_rd(ctl_doing_rd),
.ctl_cal_req(ctl_cal_req),
.ctl_cal_byte_lane_sel_n(ctl_cal_byte_lane_sel_n),
.dbg_clk(dbg_clk),
.dbg_reset_n(dbg_reset_n),
.dbg_addr(dbg_addr),
.dbg_wr(dbg_wr),
.dbg_rd(dbg_rd),
.dbg_cs(dbg_cs),
.dbg_wr_data(dbg_wr_data),
.reset_request_n(reset_request_n),
.ctl_clk(ctl_clk),
.ctl_reset_n(ctl_reset_n),
.ctl_wlat(ctl_wlat),
.ctl_rdata(ctl_rdata),
.ctl_rdata_valid(ctl_rdata_valid),
.ctl_rlat(ctl_rlat),
.ctl_cal_success(ctl_cal_success),
.ctl_cal_fail(ctl_cal_fail),
.ctl_cal_warning(ctl_cal_warning),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_cas_n(mem_cas_n),
.mem_cke(mem_cke),
.mem_cs_n(mem_cs_n),
.mem_dm(mem_dm),
.mem_odt(mem_odt),
.mem_ras_n(mem_ras_n),
.mem_we_n(mem_we_n),
.mem_reset_n(mem_reset_n),
.dbg_rd_data(dbg_rd_data),
.dbg_waitrequest(dbg_waitrequest),
.aux_half_rate_clk(aux_half_rate_clk),
.aux_full_rate_clk(aux_full_rate_clk),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqs_n(mem_dqs_n));
defparam
nios_altmemddr_0_phy_alt_mem_phy_inst.FAMILY = "Cyclone IV E",
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MEMTYPE = "DDR2",
nios_altmemddr_0_phy_alt_mem_phy_inst.DLL_DELAY_BUFFER_MODE = "LOW",
nios_altmemddr_0_phy_alt_mem_phy_inst.DLL_DELAY_CHAIN_LENGTH = 12,
nios_altmemddr_0_phy_alt_mem_phy_inst.DQS_DELAY_CTL_WIDTH = 6,
nios_altmemddr_0_phy_alt_mem_phy_inst.DQS_OUT_MODE = "DELAY_CHAIN2",
nios_altmemddr_0_phy_alt_mem_phy_inst.DQS_PHASE = 6000,
nios_altmemddr_0_phy_alt_mem_phy_inst.DQS_PHASE_SETTING = 2,
nios_altmemddr_0_phy_alt_mem_phy_inst.DWIDTH_RATIO = 4,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DWIDTH = 8,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_ADDR_WIDTH = 14,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_BANKADDR_WIDTH = 2,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CS_WIDTH = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CS_PER_RANK = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DM_WIDTH = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DM_PINS_EN = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DQ_PER_DQS = 8,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DQS_WIDTH = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_OCT_EN = 0,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CLK_PAIR_COUNT = 1,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CLK_PS = 8000,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_CLK_PS_STR = "8000 ps",
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MR_0 = 579,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MR_1 = 1024,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MR_2 = 0,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_MR_3 = 0,
nios_altmemddr_0_phy_alt_mem_phy_inst.PLL_STEPS_PER_CYCLE = 80,
nios_altmemddr_0_phy_alt_mem_phy_inst.SCAN_CLK_DIVIDE_BY = 2,
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_DQSN_EN = 0,
nios_altmemddr_0_phy_alt_mem_phy_inst.DLL_EXPORT_IMPORT = "EXPORT",
nios_altmemddr_0_phy_alt_mem_phy_inst.MEM_IF_ADDR_CMD_PHASE = 90,
nios_altmemddr_0_phy_alt_mem_phy_inst.RANK_HAS_ADDR_SWAP = 0;
endmodule
// =========================================================
// altmemphy Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, altmemphy Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="ALTMEMPHY" version="15.1" build="198" iptb_version="1.3.0 Build 185" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRPHYMVCModel" active_core="nios_altmemddr_0_phy_alt_mem_phy" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="62.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="125.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_drate" value="Half" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "project_family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(8000 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR2 SDRAM" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "quartus_project_exists" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "speed_grade" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dwidth" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_9" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_8" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_7" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "vendor" value="JEDEC" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset" value="JEDEC DDR2-533 512Mb x8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_13" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_12" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_15" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_14" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_11" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_10" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_rank" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="14" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_2" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_1" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_0" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_6" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_5" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_4" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_3" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="45.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="7.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdha_ps" value="350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="450" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="105.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.25" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tfaw_ns" value="37.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.36" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trrd_ns" value="7.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tiha_ps" value="500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tac_ps" value="500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tisa_ps" value="500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="7.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trtp_ns" value="7.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_phase" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSCK_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_odt" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mp_calibration" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSQ_percent" value="0.65" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_bl" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_bank_info" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QHS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl" value="4.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_clk_select" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_lookahead_depth" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_allocation" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "multicast_wr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_hrb_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "controller_type" value="ngv110_ctl" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_num" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "qsys_mode" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_cycles" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_auto_correct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "burst_merge_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_data_reordering_type" value="INTER_BANK" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tool_context" value="SOPC_BUILDER" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_addr_mapping" value="CHIP_ROW_BANK_COL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_starve_limit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_latency" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ref_clk_source" value="clk_0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_reorder_data" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "max_local_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "csr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_nom" value="ODT Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast Exit" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_wtcl" value="5.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS_calculated" value="0.350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dq_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_minCK_DQS_skew" value="-0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS" value="0.35" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_maxCK_DQS_skew" value="0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "num_slots_or_devices" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_inter_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "addr_cmd_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS_calculated" value="0.500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH" value="0.35" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH_calculated" value="0.500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_tpd_inter_DIMM" value="0.05" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dqs_dqsn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_intra_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH_calculated" value="0.350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_hold" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_setup" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ck_ckn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "restore_default_toggle" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_settings_valid" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQS" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_addresscmd_CK_skew" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQ" value="0.0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "alt_top" value="nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen2">
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper;+nios_altmemddr_0_phy_alt_mem_phy_reconfig;+nios_altmemddr_0_phy_alt_mem_phy_pll;+nios_altmemddr_0_phy_alt_mem_phy_delay --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/tmp/alt6939_8123991092649822378.dir/0001_iptb_gen/nios_altmemddr_0_phy_simgen_init.txt" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "qip">
// Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="nios_altmemddr_0_phy_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
`timescale 1ns / 1ps
/*
-- Module Name: Control Path
-- Description: Modulo top level para el camino de control de un router.
Instancia a los modulos 'control de enlace' y
'planificador de salida'.
Ademas de los modulos mencionados, en este archivo se
encuentra el desglose necesario de señales y la
interconexion de los modulos.
-- Dependencies: -- system.vh
-- link_controller.v x 4
-- outport_scheduler.v x 4
-- Parameters: -- X_LOCAL: Direccion en dimension "x" del nodo
en la red.
-- Y_LOCAL: Direccion en dimension "y" del nodo
en la red.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas: ** Esta pendiente arreglar los indices de las señales
'input_channel_xxxx_din' y 'buffer_xxxx_din'
-- History:
-- 05 de Junio 2015: Creacion
-- 10 de Junio 2015: * actualizacion de instancia de link
controllers.
* se agregan puerto para recibir el campo
'destino' del flit de cabecera desde las
colas de almacenamiento temporal del
datapath
*/
`include "system.vh"
module control_path #(
parameter X_LOCAL = 2,
parameter Y_LOCAL = 2,
parameter X_WIDTH = 2,
parameter Y_WIDTH = 2
)
(
input wire clk,
input wire reset,
// -- segmentos de puertos de entrada ------------------------ >>>>>
output wire credit_out_xpos_dout,
input wire [31:24] input_channel_xpos_din,
input wire [29:24] buffer_xpos_din,
input wire done_buffer_xpos_din,
output wire credit_out_ypos_dout,
input wire [31:24] input_channel_ypos_din,
input wire [29:24] buffer_ypos_din,
input wire done_buffer_ypos_din,
output wire credit_out_xneg_dout,
input wire [31:24] input_channel_xneg_din,
input wire [29:24] buffer_xneg_din,
input wire done_buffer_xneg_din,
output wire credit_out_yneg_dout,
input wire [31:24] input_channel_yneg_din,
input wire [29:24] buffer_yneg_din,
input wire done_buffer_yneg_din,
output wire credit_out_pe_dout,
input wire [31:24] input_channel_pe_din,
input wire [29:24] buffer_pe_din,
input wire done_buffer_pe_din,
// -- puertos de recepcion de creditos ----------------------- >>>>>
input wire credit_in_xpos_din,
input wire credit_in_ypos_din,
input wire credit_in_xneg_din,
input wire credit_in_yneg_din,
input wire credit_in_pe_din,
// -- señales de salida a camino de datos -------------------- >>>>>
output wire [4:0] write_strobe_dout,
output wire [4:0] read_strobe_dout,
output wire [3:0] xbar_conf_vector_xpos_dout,
output wire [3:0] xbar_conf_vector_ypos_dout,
output wire [3:0] xbar_conf_vector_xneg_dout,
output wire [3:0] xbar_conf_vector_yneg_dout,
output wire [3:0] xbar_conf_vector_pe_dout
);
// -- Parametros locales ----------------------------------------- >>>>>
localparam X_ADDR = clog2(X_WIDTH);
localparam Y_ADDR = clog2(Y_WIDTH);
/*
-- Instancia :: Controladores de Enlace
-- Descripcion: Modulo para la administracion de paquetes entrando al
router. Se encarga de la recepcion de paquetes,
solicitud del uso de un puerto de salida y de la
transferencia de paquetes recibidos al puerto de salida
destino.
Cada instancia de este modulo esta ligada a un puerto
de entrada y a una cola de almacenamiento.
La negociacion de recursos se lleva a cabo con los
modulos "planificador de salida".
*/
// -- Link Controllers ------------------------------------------- >>>>>
/*
-- Las señales son agrupadas en vectores para poder hacer el enlace
entre puertos dentro de los ciclos Generate.
*/
// -- Desglose de Señales ------------------------------------ >>>>>
// -- Entrada :: Campo header de Flit de Cabecera -------- >>>>>
wire [4:0] header_field;
assign header_field[`X_POS] = input_channel_xpos_din[31];
assign header_field[`Y_POS] = input_channel_ypos_din[31];
assign header_field[`X_NEG] = input_channel_xneg_din[31];
assign header_field[`Y_NEG] = input_channel_yneg_din[31];
assign header_field[`PE] = input_channel_pe_din [31];
// -- Entrada :: Campo done de Flit de Cabecera ---------- >>>>>
wire [4:0] done_field;
assign done_field[`X_POS] = input_channel_xpos_din[30];
assign done_field[`Y_POS] = input_channel_ypos_din[30];
assign done_field[`X_NEG] = input_channel_xneg_din[30];
assign done_field[`Y_NEG] = input_channel_yneg_din[30];
assign done_field[`PE] = input_channel_pe_din [30];
// -- Entrada :: Campo done desde Buffer ----------------- >>>>>
wire [4:0] done_buffer;
assign done_buffer[`X_POS] = done_buffer_xpos_din;
assign done_buffer[`Y_POS] = done_buffer_ypos_din;
assign done_buffer[`X_NEG] = done_buffer_xneg_din;
assign done_buffer[`Y_NEG] = done_buffer_yneg_din;
assign done_buffer[`PE] = done_buffer_pe_din;
// -- Entrada :: Campo destino X de Flit de Cabecera ----- >>>>>
wire [`ADDR_FIELD-1:0] x_field [4:0];
assign x_field[`X_POS] = input_channel_xpos_din[29-:`ADDR_FIELD];
assign x_field[`Y_POS] = input_channel_ypos_din[29-:`ADDR_FIELD];
assign x_field[`X_NEG] = input_channel_xneg_din[29-:`ADDR_FIELD];
assign x_field[`Y_NEG] = input_channel_yneg_din[29-:`ADDR_FIELD];
assign x_field[`PE] = input_channel_pe_din [29-:`ADDR_FIELD];
// -- Entrada :: Campo destino Y de Flit de Cabecera ----- >>>>>
wire [`ADDR_FIELD-1:0] y_field [4:0];
assign y_field[`X_POS] = input_channel_xpos_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_field[`Y_POS] = input_channel_ypos_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_field[`X_NEG] = input_channel_xneg_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_field[`Y_NEG] = input_channel_yneg_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_field[`PE] = input_channel_pe_din [(29-`ADDR_FIELD)-:`ADDR_FIELD];
// -- Entrada :: Campo destino X desde Buffer ------------ >>>>>
wire [`ADDR_FIELD-1:0] x_buffer [4:0];
assign x_buffer[`X_POS] = buffer_xpos_din[29-:`ADDR_FIELD];
assign x_buffer[`Y_POS] = buffer_ypos_din[29-:`ADDR_FIELD];
assign x_buffer[`X_NEG] = buffer_xneg_din[29-:`ADDR_FIELD];
assign x_buffer[`Y_NEG] = buffer_yneg_din[29-:`ADDR_FIELD];
assign x_buffer[`PE] = buffer_pe_din [29-:`ADDR_FIELD];
// -- Entrada :: Campo destino Y desde Buffer ------------ >>>>>
wire [`ADDR_FIELD-1:0] y_buffer [4:0];
assign y_buffer[`X_POS] = buffer_xpos_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_buffer[`Y_POS] = buffer_ypos_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_buffer[`X_NEG] = buffer_xneg_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_buffer[`Y_NEG] = buffer_yneg_din[(29-`ADDR_FIELD)-:`ADDR_FIELD];
assign y_buffer[`PE] = buffer_pe_din [(29-`ADDR_FIELD)-:`ADDR_FIELD];
// -- Salida :: Señal transfer strobe -------------------- >>>>>
wire [4:0] transfer_strobe;
// -- Salida :: Señal credit add out --------------------- >>>>>
wire [4:0] credit_out; // +1
assign credit_out_xpos_dout = credit_out[`X_POS];
assign credit_out_ypos_dout = credit_out[`Y_POS];
assign credit_out_xneg_dout = credit_out[`X_NEG];
assign credit_out_yneg_dout = credit_out[`Y_NEG];
assign credit_out_pe_dout = credit_out[`PE]; // PE
// -- Salida :: Señal request vector --------------------- >>>>>
wire [3:0] request_vector [4:0]; // +1
// -- Intancias :: Link Controller --------------------------- >>>>>
genvar index;
generate
for (index = `X_POS; index < (`PE + 1); index=index + 1)
begin: link_controller
link_controller
#(
.PORT_DIR (index),
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL),
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH)
)
controlador_de_enlace
(
.clk (clk),
.reset (reset),
// -- input ------------------------------ >>>>>
.transfer_strobe_din(transfer_strobe[index]),
.header_field_din (header_field[index]),
.done_field_din (done_field[index]),
.done_buffer_din (done_buffer[index]),
.x_field_din (x_field[index]),
.y_field_din (y_field[index]),
.x_buffer_din (x_buffer[index]),
.y_buffer_din (y_buffer[index]),
// -- output ----------------------------- >>>>>
.write_strobe_dout (write_strobe_dout[index]),
.read_strobe_dout (read_strobe_dout[index]),
.credit_out_dout (credit_out[index]),
.request_vector_dout(request_vector[index])
);
end
endgenerate
/*
-- Instancia :: Selector
-- Descripcion: Modulo de filtrado de peticiones. El uso de algoritmos
adaptativos o parcialmente adaptativos ofrece varios
caminos para dar salida a un paquete, sin embargo la
ejecucion de multiples peticiones produce resultados
impredecibles: duplicacion de paquetes, paquetes
corruptos, etc.
Los modulos 'selector' solo permiten la salida de una
peticion por ciclo de reloj (por puerto de salida).
*/
// -- Selector de Peticiones ------------------------------------- >>>>>
// -- Desglose de Señales ------------------------------------ >>>>>
// -- Entrada :: Status Register ------------------------- >>>>>
// -- Nota :: PSR esta modelado como una memoria pero debe de
// -- inferir registros (memoria distribuida).
wire [3:0] port_status_register [4:0];
// -- Salida :: Vector de Solicitudes Acotado ------------ >>>>>
wire [3:0] masked_request_vector [4:0];
// -- Instancias :: Selector --------------------------------- >>>>>
generate
for (index = `X_POS; index < (`PE + 1); index=index + 1)
begin: selectores
selector
#(
.PORT_DIR (index)
)
selector
(
// -- inputs ------------------------- >>>>>
.request_vector_din (request_vector[index]),
.transfer_strobe_din (transfer_strobe[index]),
.status_register_din (port_status_register[index]),
// -- outputs ------------------------ >>>>>
.masked_request_vector_dout (masked_request_vector[index])
);
end
endgenerate
/*
-- Descripcion: Cada puerto de salida solo puede recibir peticiones de
puertos de entrada opuestos a el.
Ej: Puerto de salida 'x+' solo puede recibir peticiones
de los puertos {pe, y+, x-, y-}. Las lineas de codigo
a continuacion reparten peticiones a sus repestectivos
'planificadores de salida'.
*/
// -- Distribucion de Peticiones por Puerto ---------------------- >>>>>
wire [3:0] request_to_port [4:0];
assign request_to_port[`X_POS] = {
masked_request_vector[`Y_NEG][`YNEG_XPOS],
masked_request_vector[`X_NEG][`XNEG_XPOS],
masked_request_vector[`Y_POS][`YPOS_XPOS],
masked_request_vector[`PE][`PE_XPOS]
};
assign request_to_port[`Y_POS] = {
masked_request_vector[`Y_NEG][`YNEG_YPOS],
masked_request_vector[`X_NEG][`XNEG_YPOS],
masked_request_vector[`X_POS][`XPOS_YPOS],
masked_request_vector[`PE][`PE_YPOS]
};
assign request_to_port[`X_NEG] = {
masked_request_vector[`Y_NEG][`YNEG_XNEG],
masked_request_vector[`Y_POS][`YPOS_XNEG],
masked_request_vector[`X_POS][`XPOS_XNEG],
masked_request_vector[`PE][`PE_XNEG]
};
assign request_to_port[`Y_NEG] = {
masked_request_vector[`X_NEG][`XNEG_YNEG],
masked_request_vector[`Y_POS][`YPOS_YNEG],
masked_request_vector[`X_POS][`XPOS_YNEG],
masked_request_vector[`PE][`PE_YNEG]
};
assign request_to_port[`PE] = {
masked_request_vector[`Y_NEG][`YNEG_PE],
masked_request_vector[`X_NEG][`XNEG_PE],
masked_request_vector[`Y_POS][`YPOS_PE],
masked_request_vector[`X_POS][`XPOS_PE]
};
// -- Planificador de Salida ------------------------------------- >>>>>
// -- Desglose de Señales ------------------------------------ >>>>>
// -- Entrada :: credit add in ----------------------- >>>>>
wire [4:0] credit_in; // +1
assign credit_in[`X_POS] = credit_in_xpos_din;
assign credit_in[`Y_POS] = credit_in_ypos_din;
assign credit_in[`X_NEG] = credit_in_xneg_din;
assign credit_in[`Y_NEG] = credit_in_yneg_din;
assign credit_in[`PE] = credit_in_pe_din; // PE
// -- Salida :: vector de configuracion de crossbar ------ >>>>>
wire [3:0] xbar_conf_vector [4:0]; // +1
// -- Salida :: vector de pulso de transferencia --------- >>>>>
wire [3:0] transfer_strobe_vector [4:0]; // +1
// -- Salida :: bits del registro de estado de puertos --- >>>>>
wire [4:0] status_register;
// -- Instancias :: Planificador de Salida --------------------------- >>>>>
generate
for (index = `X_POS; index < (`PE + 1); index=index + 1)
begin: output_scheduler
outport_scheduler
#(
.PORT_DIR(index)
)
planificador_de_salida
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------- >>>>>
.port_request_din (request_to_port[index]),
.credit_in_din (credit_in[index]),
// -- outputs ------------------------------------ >>>>>
.transfer_strobe_vector_dout (transfer_strobe_vector[index]),
.port_status_dout (status_register[index]),
.xbar_conf_vector_dout (xbar_conf_vector[index])
);
end
endgenerate
// -- Asignador de vectores de configuracion para crossbar ----------- >>>>>
assign xbar_conf_vector_xpos_dout = xbar_conf_vector[`X_POS];
assign xbar_conf_vector_ypos_dout = xbar_conf_vector[`Y_POS];
assign xbar_conf_vector_xneg_dout = xbar_conf_vector[`X_NEG];
assign xbar_conf_vector_yneg_dout = xbar_conf_vector[`Y_NEG];
assign xbar_conf_vector_pe_dout = xbar_conf_vector[`PE];
// -- Distribucion de Bits de estado de puerto ----------------------- >>>>>
assign port_status_register[`X_POS] = {
status_register[`Y_NEG],
status_register[`X_NEG],
status_register[`Y_POS],
status_register[`PE]
};
assign port_status_register[`Y_POS] = {
status_register[`Y_NEG],
status_register[`X_NEG],
status_register[`X_POS],
status_register[`PE]
};
assign port_status_register[`X_NEG] = {
status_register[`Y_NEG],
status_register[`Y_POS],
status_register[`X_POS],
status_register[`PE]
};
assign port_status_register[`Y_NEG] = {
status_register[`X_NEG],
status_register[`Y_POS],
status_register[`X_POS],
status_register[`PE]
};
assign port_status_register[`PE] = {
status_register[`Y_NEG],
status_register[`X_NEG],
status_register[`Y_POS],
status_register[`X_POS]
};
// -- Distribucion de Señales Transfer Strobe ---------------------- >>>>>
assign transfer_strobe[`X_POS] = transfer_strobe_vector[`Y_POS][`YPOS_XPOS] |
transfer_strobe_vector[`X_NEG][`XNEG_XPOS] |
transfer_strobe_vector[`Y_NEG][`YNEG_XPOS] |
transfer_strobe_vector[`PE][`PE_XPOS];
assign transfer_strobe[`Y_POS] = transfer_strobe_vector[`X_POS][`XPOS_YPOS] |
transfer_strobe_vector[`X_NEG][`XNEG_YPOS] |
transfer_strobe_vector[`Y_NEG][`YNEG_YPOS] |
transfer_strobe_vector[`PE][`PE_YPOS];
assign transfer_strobe[`X_NEG] = transfer_strobe_vector[`X_POS][`XPOS_XNEG] |
transfer_strobe_vector[`Y_POS][`YPOS_XNEG] |
transfer_strobe_vector[`Y_NEG][`YNEG_XNEG] |
transfer_strobe_vector[`PE][`PE_XNEG];
assign transfer_strobe[`Y_NEG] = transfer_strobe_vector[`X_POS][`XPOS_YNEG] |
transfer_strobe_vector[`Y_POS][`YPOS_YNEG] |
transfer_strobe_vector[`X_NEG][`XNEG_YNEG] |
transfer_strobe_vector[`PE][`PE_YNEG];
assign transfer_strobe[`PE] = transfer_strobe_vector[`X_POS][`XPOS_PE] |
transfer_strobe_vector[`Y_POS][`YPOS_PE] |
transfer_strobe_vector[`X_NEG][`XNEG_PE] |
transfer_strobe_vector[`Y_NEG][`YNEG_PE];
// -- Codigo no sintetizable ------------------------------------- >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// Funcion de calculo: log2(x) ---------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
control_path
#(
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL)
)
camino_de_control
(
.clk (clk),
.reset (reset),
// -- segmentos de puertos de entrada ------------------------ >>>>>
.credit_out_xpos_dout (credit_out_xpos_dout),
.input_channel_xpos_din (input_channel_xpos_din),
.buffer_xpos_din (buffer_xpos_din),
.done_buffer_xpos_din (done_buffer_xpos_din),
.credit_out_ypos_dout (credit_out_ypos_dout),
.input_channel_ypos_din (input_channel_ypos_din),
.buffer_ypos_din (buffer_ypos_din),
.done_buffer_ypos_din (done_buffer_ypos_din),
.credit_out_xneg_dout (credit_out_xneg_dout),
.input_channel_xneg_din (input_channel_xneg_din),
.buffer_xneg_din (buffer_xneg_din),
.done_buffer_xneg_din (done_buffer_xneg_din),
.credit_out_yneg_dout (credit_out_yneg_dout),
.input_channel_yneg_din (input_channel_yneg_din),
.buffer_yneg_din (buffer_yneg_din),
.done_buffer_yneg_din (done_buffer_yneg_din),
.credit_out_pe_dout (credit_out_pe_dout),
.input_channel_pe_din (input_channel_pe_din),
.buffer_pe_din (buffer_pe_din),
.done_buffer_pe_din (done_buffer_pe_din),
// -- puertos de recepcion de creditos ----------------------- >>>>>
.credit_in_xpos_din (credit_in_xpos_din),
.credit_in_ypos_din (credit_in_ypos_din),
.credit_in_xneg_din (credit_in_xneg_din),
.credit_in_yneg_din (credit_in_yneg_din),
.credit_in_pe_din (credit_in_pe_din),
// -- señales de salida a camino de datos -------------------- >>>>>
.write_strobe_dout (write_strobe_dout),
.read_strobe_dout (read_strobe_dout),
.xbar_conf_vector_xpos_dout (xbar_conf_vector_xpos_dout),
.xbar_conf_vector_ypos_dout (xbar_conf_vector_ypos_dout),
.xbar_conf_vector_xneg_dout (xbar_conf_vector_xneg_dout),
.xbar_conf_vector_yneg_dout (xbar_conf_vector_yneg_dout),
.xbar_conf_vector_pe_dout (xbar_conf_vector_pe_dout)
);
*/ |
module Control(OpCode, Funct,
PCSrc, Branch, RegWrite, RegDst,
MemRead, MemWrite, MemtoReg,
ALUSrc1, ALUSrc2, ExtOp, LuOp, ALUOp);
input [5:0] OpCode;
input [5:0] Funct;
output [1:0] PCSrc;
output Branch;
output RegWrite;
output [1:0] RegDst;
output MemRead;
output MemWrite;
output [1:0] MemtoReg;
output ALUSrc1;
output ALUSrc2;
output ExtOp;
output LuOp;
output [3:0] ALUOp;
// Your code below
assign PCSrc =
(OpCode == 6'h02 || OpCode == 6'h03) ? 2'b01 :
(OpCode == 6'h00 && (Funct == 6'h08 ||
Funct == 6'h09)) ? 2'b10 : 2'b00;
assign Branch = (OpCode == 6'h04) ? 1'b1: 1'b0;
assign RegWrite =
(OpCode == 6'h2b ||
OpCode == 6'h04 ||
OpCode == 6'h02 ||
OpCode == 6'h00 && Funct == 6'h08) ? 1'b0 : 1'b1;
assign RegDst =
(OpCode == 6'h23 ||
OpCode == 6'h0f ||
OpCode == 6'h08 ||
OpCode == 6'h09 ||
OpCode == 6'h0c ||
OpCode == 6'h0a ||
OpCode == 6'h0b) ? 2'b00 :
(OpCode == 6'h03 ||
OpCode == 6'h00 && Funct == 6'h09) ? 2'b10 : 2'b01;
assign MemRead = (OpCode == 6'h23) ? 1'b1 : 1'b0;
assign MemWrite = (OpCode == 6'h2b) ? 1'b1 : 1'b0;
assign MemtoReg =
(OpCode == 6'h23) ? 2'b01 :
(OpCode == 6'h03 ||
OpCode == 6'h00 && Funct == 6'h09) ? 2'b10 : 2'b00;
assign ALUSrc1 =
(OpCode == 6'h00 && (Funct == 6'h00 ||
Funct == 6'h02 ||
Funct == 6'h03)) ? 1'b1 : 1'b0;
assign ALUSrc2 =
(OpCode == 6'h23 ||
OpCode == 6'h2b ||
OpCode == 6'h0f ||
OpCode == 6'h08 ||
OpCode == 6'h09 ||
OpCode == 6'h0c ||
OpCode == 6'h0a ||
OpCode == 6'h0b) ? 1'b1 : 1'b0;
assign ExtOp = (OpCode == 6'h0b) ? 1'b0 : 1'b1;
assign LuOp = (OpCode == 6'h0f) ? 1'b1 : 1'b0;
// Your code above
assign ALUOp[2:0] =
(OpCode == 6'h00)? 3'b010:
(OpCode == 6'h04)? 3'b001:
(OpCode == 6'h0c)? 3'b100:
(OpCode == 6'h0a || OpCode == 6'h0b)? 3'b101:
3'b000;
assign ALUOp[3] = OpCode[0];
endmodule
|
module RegisterFileTestBench3;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] in,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
initial fork
//Clk 0
Clk = 0 ; RESET = 1 ; Pcin = 32'bz ; in = 32'bz ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT = 0 ;
//Clk 1 (Rising Edge)
#1 RESET = 0 ; #1 Pcin = 32'bz ; #1 in = 1 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT = 0 ;
//Clk 0 (Falling Edge)
#2 Pcin = 32'bz ; #2 in = 1 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT = 1 ;
//Clk 1 (Rising Edge)
#3 Pcin = 32'bz ; #3 in = 1 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT = 1 ;
//Clk 0 (Falling Edge)
#4 Pcin = 32'bz ; #4 in = 1 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT = 1 ;
//Clk 1 (Rising Edge)
#5 Pcin = 32'bz ; #5 in = 1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT = 1 ;
//Clk 0 (Falling Edge)
#6 Pcin = 32'bz ; #6 in = 1 ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 1 ; #6 RSLCT = 2 ;
//Clk 1 (Rising Edge)
#7 Pcin = 32'bz ; #7 in = 1 ; #7 LOADPC = 0 ; #7 LOAD = 1 ; #7 IR_CU = 1 ; #7 RSLCT = 2 ;
//Clk 0 (Falling Edge)
#8 Pcin = 32'bz ; #8 in = 1 ; #8 LOADPC = 0 ; #8 LOAD = 1 ; #8 IR_CU = 1 ; #8 RSLCT = 2 ;
//Clk 1 (Rising Edge)
#9 Pcin = 32'bz ; #9 in = 1 ; #9 LOADPC = 0 ; #9 LOAD = 1 ; #9 IR_CU = 1 ; #9 RSLCT = 2 ;
//Clk 0 (Falling Edge)
#10 Pcin = 32'bz ; #10 in = 1 ; #10 LOADPC = 0 ; #10 LOAD = 0 ; #10 IR_CU = 1 ; #10 RSLCT = 0 ;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("RegisterFileTestBench3.vcd");
$dumpvars(0,RegisterFileTestBench3);
$display(" Test Results" );
$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v RegisterFileTestBench.v |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFRTN_PP_SYMBOL_V
/**
* srsdfrtn: Scan flop with sleep mode, inverted reset, inverted
* clock, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTN_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/04/2016 09:15:54 PM
// Design Name:
// Module Name: hapara_lmb_dma_dup
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module hapara_lmb_dma_dup #(
parameter integer DATA_WIDTH = 32,
parameter integer NUM_SLAVE = 4
)
(
//----------------FROM DMA BRAM CONTROLLER-----------------
input [DATA_WIDTH - 1 : 0] addr_ctrl,
input [DATA_WIDTH - 1 : 0] data_in_ctrl,
output [DATA_WIDTH - 1 : 0] data_out_ctrl,
input [DATA_WIDTH / 8 - 1 : 0] we_ctrl,
input clk_ctrl,
input rst_ctrl,
input en_ctrl,
//----------------FROM SLAVE 0-----------------
input [DATA_WIDTH - 1 : 0] addr_s0,
input [DATA_WIDTH - 1 : 0] data_in_s0,
output [DATA_WIDTH - 1 : 0] data_out_s0,
input [DATA_WIDTH / 8 - 1 : 0] we_s0,
input clk_s0,
input rst_s0,
input en_s0,
//----------------FROM SLAVE 1-----------------
input [DATA_WIDTH - 1 : 0] addr_s1,
input [DATA_WIDTH - 1 : 0] data_in_s1,
output [DATA_WIDTH - 1 : 0] data_out_s1,
input [DATA_WIDTH / 8 - 1 : 0] we_s1,
input clk_s1,
input rst_s1,
input en_s1,
//----------------FROM SLAVE 2-----------------
input [DATA_WIDTH - 1 : 0] addr_s2,
input [DATA_WIDTH - 1 : 0] data_in_s2,
output [DATA_WIDTH - 1 : 0] data_out_s2,
input [DATA_WIDTH / 8 - 1 : 0] we_s2,
input clk_s2,
input rst_s2,
input en_s2,
//----------------FROM SLAVE 3-----------------
input [DATA_WIDTH - 1 : 0] addr_s3,
input [DATA_WIDTH - 1 : 0] data_in_s3,
output [DATA_WIDTH - 1 : 0] data_out_s3,
input [DATA_WIDTH / 8 - 1 : 0] we_s3,
input clk_s3,
input rst_s3,
input en_s3,
//----------------FROM SLAVE 4-----------------
input [DATA_WIDTH - 1 : 0] addr_s4,
input [DATA_WIDTH - 1 : 0] data_in_s4,
output [DATA_WIDTH - 1 : 0] data_out_s4,
input [DATA_WIDTH / 8 - 1 : 0] we_s4,
input clk_s4,
input rst_s4,
input en_s4,
//----------------FROM SLAVE 5-----------------
input [DATA_WIDTH - 1 : 0] addr_s5,
input [DATA_WIDTH - 1 : 0] data_in_s5,
output [DATA_WIDTH - 1 : 0] data_out_s5,
input [DATA_WIDTH / 8 - 1 : 0] we_s5,
input clk_s5,
input rst_s5,
input en_s5,
//----------------FROM SLAVE 6-----------------
input [DATA_WIDTH - 1 : 0] addr_s6,
input [DATA_WIDTH - 1 : 0] data_in_s6,
output [DATA_WIDTH - 1 : 0] data_out_s6,
input [DATA_WIDTH / 8 - 1 : 0] we_s6,
input clk_s6,
input rst_s6,
input en_s6,
//----------------FROM SLAVE 7-----------------
input [DATA_WIDTH - 1 : 0] addr_s7,
input [DATA_WIDTH - 1 : 0] data_in_s7,
output [DATA_WIDTH - 1 : 0] data_out_s7,
input [DATA_WIDTH / 8 - 1 : 0] we_s7,
input clk_s7,
input rst_s7,
input en_s7,
//----------------TO BRAM 0-----------------
output [DATA_WIDTH - 1 : 0] addr_b0,
output [DATA_WIDTH - 1 : 0] data_in_b0,
input [DATA_WIDTH - 1 : 0] data_out_b0,
output [DATA_WIDTH / 8 - 1 : 0] we_b0,
output clk_b0,
output rst_b0,
output en_b0,
//----------------TO BRAM 1-----------------
output [DATA_WIDTH - 1 : 0] addr_b1,
output [DATA_WIDTH - 1 : 0] data_in_b1,
input [DATA_WIDTH - 1 : 0] data_out_b1,
output [DATA_WIDTH / 8 - 1 : 0] we_b1,
output clk_b1,
output rst_b1,
output en_b1,
//----------------TO BRAM 2-----------------
output [DATA_WIDTH - 1 : 0] addr_b2,
output [DATA_WIDTH - 1 : 0] data_in_b2,
input [DATA_WIDTH - 1 : 0] data_out_b2,
output [DATA_WIDTH / 8 - 1 : 0] we_b2,
output clk_b2,
output rst_b2,
output en_b2,
//----------------TO BRAM 3-----------------
output [DATA_WIDTH - 1 : 0] addr_b3,
output [DATA_WIDTH - 1 : 0] data_in_b3,
input [DATA_WIDTH - 1 : 0] data_out_b3,
output [DATA_WIDTH / 8 - 1 : 0] we_b3,
output clk_b3,
output rst_b3,
output en_b3,
//----------------TO BRAM 4-----------------
output [DATA_WIDTH - 1 : 0] addr_b4,
output [DATA_WIDTH - 1 : 0] data_in_b4,
input [DATA_WIDTH - 1 : 0] data_out_b4,
output [DATA_WIDTH / 8 - 1 : 0] we_b4,
output clk_b4,
output rst_b4,
output en_b4,
//----------------TO BRAM 5-----------------
output [DATA_WIDTH - 1 : 0] addr_b5,
output [DATA_WIDTH - 1 : 0] data_in_b5,
input [DATA_WIDTH - 1 : 0] data_out_b5,
output [DATA_WIDTH / 8 - 1 : 0] we_b5,
output clk_b5,
output rst_b5,
output en_b5,
//----------------TO BRAM 6-----------------
output [DATA_WIDTH - 1 : 0] addr_b6,
output [DATA_WIDTH - 1 : 0] data_in_b6,
input [DATA_WIDTH - 1 : 0] data_out_b6,
output [DATA_WIDTH / 8 - 1 : 0] we_b6,
output clk_b6,
output rst_b6,
output en_b6,
//----------------TO BRAM 7-----------------
output [DATA_WIDTH - 1 : 0] addr_b7,
output [DATA_WIDTH - 1 : 0] data_in_b7,
input [DATA_WIDTH - 1 : 0] data_out_b7,
output [DATA_WIDTH / 8 - 1 : 0] we_b7,
output clk_b7,
output rst_b7,
output en_b7
);
wire dma_tran;
localparam NUM_BYTE = DATA_WIDTH / 8;
assign dma_tran = en_ctrl && (we_ctrl == {NUM_BYTE{1'b1}});
assign data_out_ctrl = {DATA_WIDTH{1'b0}};
generate if (NUM_SLAVE > 0)
begin
assign clk_b0 = clk_s0; //output
assign rst_b0 = rst_s0; //output
assign data_out_s0 = data_out_b0; //input
assign addr_b0 = (dma_tran == 1'b1)?addr_ctrl:addr_s0; //output
assign data_in_b0 = (dma_tran == 1'b1)?data_in_ctrl:data_in_s0; //output
assign we_b0 = (dma_tran == 1'b1)?we_ctrl:we_s0; //output
assign en_b0 = (dma_tran == 1'b1)?en_ctrl:en_s0; //output
end
endgenerate
generate if (NUM_SLAVE > 1)
begin
assign clk_b1 = clk_s1;
assign rst_b1 = rst_s1;
assign data_out_s1 = data_out_b1;
assign addr_b1 = (dma_tran == 1'b1)?addr_ctrl:addr_s1;
assign data_in_b1 = (dma_tran == 1'b1)?data_in_ctrl:data_in_s1;
assign we_b1 = (dma_tran == 1'b1)?we_ctrl:we_s1;
assign en_b1 = (dma_tran == 1'b1)?en_ctrl:en_s1;
end
endgenerate
generate if (NUM_SLAVE > 2)
begin
assign clk_b2 = clk_s2;
assign rst_b2 = rst_s2;
assign data_out_s2 = data_out_b2;
assign addr_b2 = (dma_tran == 1'b1)?addr_ctrl:addr_s2;
assign data_in_b2 = (dma_tran == 1'b1)?data_in_ctrl:data_in_s2;
assign we_b2 = (dma_tran == 1'b1)?we_ctrl:we_s2;
assign en_b2 = (dma_tran == 1'b1)?en_ctrl:en_s2;
end
endgenerate
generate if (NUM_SLAVE > 3)
begin
assign clk_b3 = clk_s3;
assign rst_b3 = rst_s3;
assign data_out_s3 = data_out_b3;
assign addr_b3 = (dma_tran == 1'b1)?addr_ctrl:addr_s3;
assign data_in_b3 = (dma_tran == 1'b1)?data_in_ctrl:data_in_s3;
assign we_b3 = (dma_tran == 1'b1)?we_ctrl:we_s3;
assign en_b3 = (dma_tran == 1'b1)?en_ctrl:en_s3;
end
endgenerate
generate if (NUM_SLAVE > 4)
begin
assign clk_b4 = clk_s4;
assign rst_b4 = rst_s4;
assign data_out_s4 = data_out_b4;
assign addr_b4 = (dma_tran == 1'b1)?addr_ctrl:addr_s4;
assign data_in_b4 = (dma_tran == 1'b1)?data_in_ctrl:data_in_s4;
assign we_b4 = (dma_tran == 1'b1)?we_ctrl:we_s4;
assign en_b4 = (dma_tran == 1'b1)?en_ctrl:en_s4;
end
endgenerate
generate if (NUM_SLAVE > 5)
begin
assign clk_b5 = clk_s5;
assign rst_b5 = rst_s5;
assign data_out_s5 = data_out_b5;
assign addr_b5 = (dma_tran == 1'b1)?addr_ctrl:addr_s5;
assign data_in_b5 = (dma_tran == 1'b1)?data_in_ctrl:data_in_s5;
assign we_b5 = (dma_tran == 1'b1)?we_ctrl:we_s5;
assign en_b5 = (dma_tran == 1'b1)?en_ctrl:en_s5;
end
endgenerate
generate if (NUM_SLAVE > 6)
begin
assign clk_b6 = clk_s6;
assign rst_b6 = rst_s6;
assign data_out_s6 = data_out_b6;
assign addr_b6 = (dma_tran == 1'b1)?addr_ctrl:addr_s6;
assign data_in_b6 = (dma_tran == 1'b1)?data_in_ctrl:data_in_s6;
assign we_b6 = (dma_tran == 1'b1)?we_ctrl:we_s6;
assign en_b6 = (dma_tran == 1'b1)?en_ctrl:en_s6;
end
endgenerate
generate if (NUM_SLAVE > 7)
begin
assign clk_b7 = clk_s7;
assign rst_b7 = rst_s7;
assign data_out_s7 = data_out_b7;
assign addr_b7 = (dma_tran == 1'b1)?addr_ctrl:addr_s7;
assign data_in_b7 = (dma_tran == 1'b1)?data_in_ctrl:data_in_s7;
assign we_b7 = (dma_tran == 1'b1)?we_ctrl:we_s7;
assign en_b7 = (dma_tran == 1'b1)?en_ctrl:en_s7;
end
endgenerate
endmodule
|
// -------------------------------------------------------------------------
//Reed-Solomon decoder
//Copyright (C) Wed May 22 09:59:27 2002
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module top(x, error, with_error, enable, valid, k, clk, clrn);
input enable, clk, clrn;
input [4:0] k, x;
output [4:0] error;
wire [4:0] error;
output with_error, valid;
reg valid;
wire with_error;
wire [4:0] s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
wire [4:0] lambda, omega, alpha;
reg [3:0] count;
reg [12:0] phase;
wire [4:0] D0, D1, DI;
//reg [4:0] D, D2;
wire [4:0] D, D2;
reg [4:0] u, length0, length2;
wire [4:0] length1, length3;
reg syn_enable, syn_init, syn_shift, berl_enable;
reg chien_search, chien_load, shorten;
always @ (chien_search or shorten)
valid = chien_search & ~shorten;
wire bit1;
assign bit1 = syn_shift&phase[0];
rsdec_syn x0 (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, u, syn_enable, bit1, syn_init, clk, clrn);
rsdec_berl x1 (lambda, omega, s0, s11, s10, s9, s8, s7, s6, s5, s4, s3, s2, s1, D0, D2, count, phase[0], phase[12], berl_enable, clk, clrn);
rsdec_chien x2 (error, alpha, lambda, omega, D1, DI, chien_search, chien_load, shorten, clk, clrn);
inverse x3 (DI, D);
always @ (posedge clk)// or negedge clrn)
begin
if (~clrn)
begin
syn_enable <= 0;
syn_shift <= 0;
berl_enable <= 0;
chien_search <= 1;
chien_load <= 0;
length0 <= 0;
length2 <= 31 - k;
count <= -1;
phase <= 1;
u <= 0;
shorten <= 1;
syn_init <= 0;
end
else
begin
if (enable & ~syn_enable & ~syn_shift)
begin
syn_enable <= 1;
syn_init <= 1;
end
else if (syn_enable)
begin
length0 <= length1;
syn_init <= 0;
if (length1 == k)
begin
syn_enable <= 0;
syn_shift <= 1;
berl_enable <= 1;
end
end
else if (berl_enable & with_error)
begin
if (phase[0])
begin
count <= count + 1;
if (count == 11)
begin
syn_shift <= 0;
length0 <= 0;
chien_load <= 1;
length2 <= length0;
end
end
phase <= {phase[11:0], phase[12]};
end
else if (berl_enable & ~with_error)
if (&count)
begin
syn_shift <= 0;
length0 <= 0;
berl_enable <= 0;
end
else
phase <= {phase[11:0], phase[12]};
else if (chien_load & phase[12])
begin
berl_enable <= 0;
chien_load <= 0;
chien_search <= 1;
count <= -1;
phase <= 1;
end
else if (chien_search)
begin
length2 <= length3;
if (length3 == 0)
chien_search <= 0;
end
else if (enable) u <= x;
else if (shorten == 1 && length2 == 0)
shorten <= 0;
end
end
// always @ (chien_search or D0 or D1)
// if (chien_search) D = D1;
// else D = D0;
assign D = chien_search ? D1 : D0;
// always @ (DI or alpha or chien_load)
// if (chien_load) D2 = alpha;
// else D2 = DI;
assign D2 = chien_load ? alpha : DI;
assign length1 = length0 + 1;
assign length3 = length2 - 1;
// always @ (syn_shift or s0 or s1 or s2 or s3 or s4 or s5 or s6 or s7 or s8 or s9 or s10 or s11)
// if (syn_shift && (s0 | s1 | s2 | s3 | s4 | s5 | s6 | s7 | s8 | s9 | s10 | s11)!= 0)
// with_error = 1;
// else with_error = 0;
wire temp;
assign temp = syn_shift && (s0 | s1 | s2 | s3 | s4 | s5 | s6 | s7 | s8 | s9 | s10 | s11);
assign with_error = temp != 0 ? 1'b1 : 1'b0;
endmodule
// -------------------------------------------------------------------------
//The inverse lookup table for Galois field
//Copyright (C) Tue Apr 2 17:21:59 2002
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module inverse(y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
case (x) // synopsys full_case parallel_case
1: y = 1; // 0 -> 31
2: y = 18; // 1 -> 30
4: y = 9; // 2 -> 29
8: y = 22; // 3 -> 28
16: y = 11; // 4 -> 27
5: y = 23; // 5 -> 26
10: y = 25; // 6 -> 25
20: y = 30; // 7 -> 24
13: y = 15; // 8 -> 23
26: y = 21; // 9 -> 22
17: y = 24; // 10 -> 21
7: y = 12; // 11 -> 20
14: y = 6; // 12 -> 19
28: y = 3; // 13 -> 18
29: y = 19; // 14 -> 17
31: y = 27; // 15 -> 16
27: y = 31; // 16 -> 15
19: y = 29; // 17 -> 14
3: y = 28; // 18 -> 13
6: y = 14; // 19 -> 12
12: y = 7; // 20 -> 11
24: y = 17; // 21 -> 10
21: y = 26; // 22 -> 9
15: y = 13; // 23 -> 8
30: y = 20; // 24 -> 7
25: y = 10; // 25 -> 6
23: y = 5; // 26 -> 5
11: y = 16; // 27 -> 4
22: y = 8; // 28 -> 3
9: y = 4; // 29 -> 2
18: y = 2; // 30 -> 1
endcase
endmodule
// -------------------------------------------------------------------------
//Berlekamp circuit for Reed-Solomon decoder
//Copyright (C) Tue Apr 2 17:21:42 2002
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module rsdec_berl (lambda_out, omega_out, syndrome0, syndrome1, syndrome2, syndrome3, syndrome4, syndrome5, syndrome6, syndrome7, syndrome8, syndrome9, syndrome10, syndrome11,
D, DI, count, phase0, phase12, enable, clk, clrn);
input clk, clrn, enable, phase0, phase12;
input [4:0] syndrome0;
input [4:0] syndrome1;
input [4:0] syndrome2;
input [4:0] syndrome3;
input [4:0] syndrome4;
input [4:0] syndrome5;
input [4:0] syndrome6;
input [4:0] syndrome7;
input [4:0] syndrome8;
input [4:0] syndrome9;
input [4:0] syndrome10;
input [4:0] syndrome11;
input [4:0] DI;
input [3:0] count;
output [4:0] lambda_out;
output [4:0] omega_out;
reg [4:0] lambda_out;
reg [4:0] omega_out;
output [4:0] D;
reg [4:0] D;
reg init, delta;
reg [2:0] L;
reg [4:0] lambda0;
reg [4:0] lambda1;
reg [4:0] lambda2;
reg [4:0] lambda3;
reg [4:0] lambda4;
reg [4:0] lambda5;
reg [4:0] lambda6;
reg [4:0] lambda7;
reg [4:0] lambda8;
reg [4:0] lambda9;
reg [4:0] lambda10;
reg [4:0] lambda11;
reg [4:0] B0;
reg [4:0] B1;
reg [4:0] B2;
reg [4:0] B3;
reg [4:0] B4;
reg [4:0] B5;
reg [4:0] B6;
reg [4:0] B7;
reg [4:0] B8;
reg [4:0] B9;
reg [4:0] B10;
reg [4:0] omega0;
reg [4:0] omega1;
reg [4:0] omega2;
reg [4:0] omega3;
reg [4:0] omega4;
reg [4:0] omega5;
reg [4:0] omega6;
reg [4:0] omega7;
reg [4:0] omega8;
reg [4:0] omega9;
reg [4:0] omega10;
reg [4:0] omega11;
reg [4:0] A0;
reg [4:0] A1;
reg [4:0] A2;
reg [4:0] A3;
reg [4:0] A4;
reg [4:0] A5;
reg [4:0] A6;
reg [4:0] A7;
reg [4:0] A8;
reg [4:0] A9;
reg [4:0] A10;
wire [4:0] tmp0;
wire [4:0] tmp1;
wire [4:0] tmp2;
wire [4:0] tmp3;
wire [4:0] tmp4;
wire [4:0] tmp5;
wire [4:0] tmp6;
wire [4:0] tmp7;
wire [4:0] tmp8;
wire [4:0] tmp9;
wire [4:0] tmp10;
wire [4:0] tmp11;
always @ (tmp1) lambda_out = tmp1;
always @ (tmp3) omega_out = tmp3;
always @ (L or D or count)
// delta = (D != 0 && 2*L <= i);
if (D != 0 && count >= {L, 1'b0}) delta = 1;
else delta = 0;
rsdec_berl_multiply x0 (tmp0, B10, D, lambda0, syndrome0, phase0);
rsdec_berl_multiply x1 (tmp1, lambda11, DI, lambda1, syndrome1, phase0);
rsdec_berl_multiply x2 (tmp2, A10, D, lambda2, syndrome2, phase0);
rsdec_berl_multiply x3 (tmp3, omega11, DI, lambda3, syndrome3, phase0);
multiply x4 (tmp4, lambda4, syndrome4);
multiply x5 (tmp5, lambda5, syndrome5);
multiply x6 (tmp6, lambda6, syndrome6);
multiply x7 (tmp7, lambda7, syndrome7);
multiply x8 (tmp8, lambda8, syndrome8);
multiply x9 (tmp9, lambda9, syndrome9);
multiply x10 (tmp10, lambda10, syndrome10);
multiply x11 (tmp11, lambda11, syndrome11);
always @ (posedge clk)// or negedge clrn)
begin
// for (j = t-1; j >=0; j--)
// if (j != 0) lambda[j] += D * B[j-1];
/* if (~clrn)
begin
lambda0 <= 0;
lambda1 <= 0;
lambda2 <= 0;
lambda3 <= 0;
lambda4 <= 0;
lambda5 <= 0;
lambda6 <= 0;
lambda7 <= 0;
lambda8 <= 0;
lambda9 <= 0;
lambda10 <= 0;
lambda11 <= 0;
B0 <= 0;
B1 <= 0;
B2 <= 0;
B3 <= 0;
B4 <= 0;
B5 <= 0;
B6 <= 0;
B7 <= 0;
B8 <= 0;
B9 <= 0;
B10 <= 0;
omega0 <= 0;
omega1 <= 0;
omega2 <= 0;
omega3 <= 0;
omega4 <= 0;
omega5 <= 0;
omega6 <= 0;
omega7 <= 0;
omega8 <= 0;
omega9 <= 0;
omega10 <= 0;
omega11 <= 0;
A0 <= 0;
A1 <= 0;
A2 <= 0;
A3 <= 0;
A4 <= 0;
A5 <= 0;
A6 <= 0;
A7 <= 0;
A8 <= 0;
A9 <= 0;
A10 <= 0;
// for (j = 0; j < 12; j = j + 1) lambda[j] <= 0;
// for (j = 0; j < 11; j = j + 1) B[j] <= 0;
// for (j = 0; j < 12; j = j + 1) omega[j] <= 0;
// for (j = 0; j < 11; j = j + 1) A[j] <= 0;
end
else*/ if (~enable)
begin
lambda0 <= 1;
lambda1 <= 0;
lambda2 <= 0;
lambda3 <= 0;
lambda4 <= 0;
lambda5 <= 0;
lambda6 <= 0;
lambda7 <= 0;
lambda8 <= 0;
lambda9 <= 0;
lambda10 <= 0;
lambda11 <= 0;
//for (j = 1; j < 12; j = j +1) lambda[j] <= 0;
B0 <= 1;
B1 <= 0;
B2 <= 0;
B3 <= 0;
B4 <= 0;
B5 <= 0;
B6 <= 0;
B7 <= 0;
B8 <= 0;
B9 <= 0;
B10 <= 0;
//for (j = 1; j < 11; j = j +1) B[j] <= 0;
omega0 <= 1;
omega1 <= 0;
omega2 <= 0;
omega3 <= 0;
omega4 <= 0;
omega5 <= 0;
omega6 <= 0;
omega7 <= 0;
omega8 <= 0;
omega9 <= 0;
omega10 <= 0;
omega11 <= 0;
//for (j = 1; j < 12; j = j +1) omega[j] <= 0;
A0 <= 0;
A1 <= 0;
A2 <= 0;
A3 <= 0;
A4 <= 0;
A5 <= 0;
A6 <= 0;
A7 <= 0;
A8 <= 0;
A9 <= 0;
A10 <= 0;
//for (j = 0; j < 11; j = j + 1) A[j] <= 0;
end
else
begin
if (~phase0)
begin
if (~phase12) lambda0 <= lambda11 ^ tmp0;
else lambda0 <= lambda11;
//for (j = 1; j < 12; j = j + 1)
//lambda[j] <= lambda[j-1];
lambda1 <= lambda0;
lambda2 <= lambda1;
lambda3 <= lambda2;
lambda4 <= lambda3;
lambda5 <= lambda4;
lambda6 <= lambda5;
lambda7 <= lambda6;
lambda8 <= lambda7;
lambda9 <= lambda8;
lambda10 <= lambda9;
lambda11 <= lambda10;
// end
// for (j = t-1; j >=0; j--)
// if (delta) B[j] = lambda[j] *DI;
// else if (j != 0) B[j] = B[j-1];
// else B[j] = 0;
// if (~phase0)
// begin
if (delta) B0 <= tmp1;
else if (~phase12) B0 <= B10;
else B0 <= 0;
//for (j = 1; j < 11; j = j + 1)
// B[j] <= B[j-1];
B1 <= B0;
B2 <= B1;
B3 <= B2;
B4 <= B3;
B5 <= B4;
B6 <= B5;
B7 <= B6;
B8 <= B7;
B9 <= B8;
B10 <= B9;
// end
// for (j = t-1; j >=0; j--)
// if (j != 0) omega[j] += D * A[j-1];
// if (~phase0)
// begin
if (~phase12) omega0 <= omega11 ^ tmp2;
else omega0 <= omega11;
//for (j = 1; j < 12; j = j + 1)
// omega[j] <= omega[j-1];
omega1 <= omega0;
omega2 <= omega1;
omega3 <= omega2;
omega4 <= omega3;
omega5 <= omega4;
omega6 <= omega5;
omega7 <= omega6;
omega8 <= omega7;
omega9 <= omega8;
omega10 <= omega9;
omega11 <= omega10;
// end
// for (j = t-1; j >=0; j--)
// if (delta) A[j] = omega[j] *DI;
// else if (j != 0) A[j] = A[j-1];
// else A[j] = 0;
// if (~phase0)
// begin
if (delta) A0 <= tmp3;
else if (~phase12) A0 <= A10;
//for (j = 1; j < 11; j = j + 1)
// A[j] <= A[j-1];
A1 <= A0;
A2 <= A1;
A3 <= A2;
A4 <= A3;
A5 <= A4;
A6 <= A5;
A7 <= A6;
A8 <= A7;
A9 <= A8;
A10 <= A9;
// end
end
end
end
always @ (posedge clk)// or negedge clrn)
begin
if (~clrn)
begin
L <= 0;
D <= 0;
end
else
begin
// if (delta) L = i - L + 1;
if ((phase0 & delta) && (count != -1)) L <= count - L + 1;
//for (D = j = 0; j < t; j = j + 1)
// D += lambda[j] * syndrome[t-j-1];
if (phase0)
D <= tmp0 ^ tmp1 ^ tmp2 ^ tmp3 ^ tmp4 ^ tmp5 ^ tmp6 ^ tmp7 ^ tmp8 ^ tmp9 ^ tmp10 ^ tmp11;
end
end
endmodule
module rsdec_berl_multiply (y, a, b, c, d, e);
input [4:0] a, b, c, d;
input e;
output [4:0] y;
wire [4:0] y;
reg [4:0] p, q;
always @ (a or c or e)
if (e) p = c;
else p = a;
always @ (b or d or e)
if (e) q = d;
else q = b;
multiply x0 (y, p, q);
endmodule
module multiply (y, a, b);
input [4:0] a, b;
output [4:0] y;
reg [9:0] tempy;
wire [4:0] y;
assign y = tempy[4:0];
always @(a or b)
begin
tempy = a * b;
end
/*
always @ (a or b)
begin
y[0] = (a[0] & b[0]) ^ (a[1] & b[4]) ^ (a[2] & b[3]) ^ (a[3] & b[2]) ^ (a[4] & b[1]) ^ (a[4] & b[4]);
y[1] = (a[0] & b[1]) ^ (a[1] & b[0]) ^ (a[2] & b[4]) ^ (a[3] & b[3]) ^ (a[4] & b[2]);
y[2] = (a[0] & b[2]) ^ (a[1] & b[1]) ^ (a[1] & b[4]) ^ (a[2] & b[0]) ^ (a[2] & b[3]) ^ (a[3] & b[2]) ^ (a[3] & b[4]) ^ (a[4] & b[1]) ^ (a[4] & b[3]) ^ (a[4] & b[4]);
y[3] = (a[0] & b[3]) ^ (a[1] & b[2]) ^ (a[2] & b[1]) ^ (a[2] & b[4]) ^ (a[3] & b[0]) ^ (a[3] & b[3]) ^ (a[4] & b[2]) ^ (a[4] & b[4]);
y[4] = (a[0] & b[4]) ^ (a[1] & b[3]) ^ (a[2] & b[2]) ^ (a[3] & b[1]) ^ (a[3] & b[4]) ^ (a[4] & b[0]) ^ (a[4] & b[3]);
endi
*/
endmodule
// -------------------------------------------------------------------------
//Chien-Forney search circuit for Reed-Solomon decoder
//Copyright (C) Tue Apr 2 17:21:51 2002
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module rsdec_chien_scale0 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[0];
y[1] = x[1];
y[2] = x[2];
y[3] = x[3];
y[4] = x[4];
end
endmodule
module rsdec_chien_scale1 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[4];
y[1] = x[0];
y[2] = x[1] ^ x[4];
y[3] = x[2];
y[4] = x[3];
end
endmodule
module rsdec_chien_scale2 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[3];
y[1] = x[4];
y[2] = x[0] ^ x[3];
y[3] = x[1] ^ x[4];
y[4] = x[2];
end
endmodule
module rsdec_chien_scale3 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[2];
y[1] = x[3];
y[2] = x[2] ^ x[4];
y[3] = x[0] ^ x[3];
y[4] = x[1] ^ x[4];
end
endmodule
module rsdec_chien_scale4 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[1] ^ x[4];
y[1] = x[2];
y[2] = x[1] ^ x[3] ^ x[4];
y[3] = x[2] ^ x[4];
y[4] = x[0] ^ x[3];
end
endmodule
module rsdec_chien_scale5 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[0] ^ x[3];
y[1] = x[1] ^ x[4];
y[2] = x[0] ^ x[2] ^ x[3];
y[3] = x[1] ^ x[3] ^ x[4];
y[4] = x[2] ^ x[4];
end
endmodule
module rsdec_chien_scale6 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[2] ^ x[4];
y[1] = x[0] ^ x[3];
y[2] = x[1] ^ x[2];
y[3] = x[0] ^ x[2] ^ x[3];
y[4] = x[1] ^ x[3] ^ x[4];
end
endmodule
module rsdec_chien_scale7 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[1] ^ x[3] ^ x[4];
y[1] = x[2] ^ x[4];
y[2] = x[0] ^ x[1] ^ x[4];
y[3] = x[1] ^ x[2];
y[4] = x[0] ^ x[2] ^ x[3];
end
endmodule
module rsdec_chien_scale8 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[0] ^ x[2] ^ x[3];
y[1] = x[1] ^ x[3] ^ x[4];
y[2] = x[0] ^ x[3] ^ x[4];
y[3] = x[0] ^ x[1] ^ x[4];
y[4] = x[1] ^ x[2];
end
endmodule
module rsdec_chien_scale9 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[1] ^ x[2];
y[1] = x[0] ^ x[2] ^ x[3];
y[2] = x[2] ^ x[3] ^ x[4];
y[3] = x[0] ^ x[3] ^ x[4];
y[4] = x[0] ^ x[1] ^ x[4];
end
endmodule
module rsdec_chien_scale10 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[0] ^ x[1] ^ x[4];
y[1] = x[1] ^ x[2];
y[2] = x[1] ^ x[2] ^ x[3] ^ x[4];
y[3] = x[2] ^ x[3] ^ x[4];
y[4] = x[0] ^ x[3] ^ x[4];
end
endmodule
module rsdec_chien_scale11 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[0] ^ x[3] ^ x[4];
y[1] = x[0] ^ x[1] ^ x[4];
y[2] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4];
y[3] = x[1] ^ x[2] ^ x[3] ^ x[4];
y[4] = x[2] ^ x[3] ^ x[4];
end
endmodule
module rsdec_chien (error, alpha, lambda, omega, even, D, search, load, shorten, clk, clrn);
input clk, clrn, load, search, shorten;
input [4:0] D;
input [4:0] lambda;
input [4:0] omega;
output [4:0] even, error;
output [4:0] alpha;
reg [4:0] even, error;
reg [4:0] alpha;
wire [4:0] scale0;
wire [4:0] scale1;
wire [4:0] scale2;
wire [4:0] scale3;
wire [4:0] scale4;
wire [4:0] scale5;
wire [4:0] scale6;
wire [4:0] scale7;
wire [4:0] scale8;
wire [4:0] scale9;
wire [4:0] scale10;
wire [4:0] scale11;
wire [4:0] scale12;
wire [4:0] scale13;
wire [4:0] scale14;
wire [4:0] scale15;
wire [4:0] scale16;
wire [4:0] scale17;
wire [4:0] scale18;
wire [4:0] scale19;
wire [4:0] scale20;
wire [4:0] scale21;
wire [4:0] scale22;
wire [4:0] scale23;
reg [4:0] data0;
reg [4:0] data1;
reg [4:0] data2;
reg [4:0] data3;
reg [4:0] data4;
reg [4:0] data5;
reg [4:0] data6;
reg [4:0] data7;
reg [4:0] data8;
reg [4:0] data9;
reg [4:0] data10;
reg [4:0] data11;
reg [4:0] a0;
reg [4:0] a1;
reg [4:0] a2;
reg [4:0] a3;
reg [4:0] a4;
reg [4:0] a5;
reg [4:0] a6;
reg [4:0] a7;
reg [4:0] a8;
reg [4:0] a9;
reg [4:0] a10;
reg [4:0] a11;
reg [4:0] l0;
reg [4:0] l1;
reg [4:0] l2;
reg [4:0] l3;
reg [4:0] l4;
reg [4:0] l5;
reg [4:0] l6;
reg [4:0] l7;
reg [4:0] l8;
reg [4:0] l9;
reg [4:0] l10;
reg [4:0] l11;
reg [4:0] o0;
reg [4:0] o1;
reg [4:0] o2;
reg [4:0] o3;
reg [4:0] o4;
reg [4:0] o5;
reg [4:0] o6;
reg [4:0] o7;
reg [4:0] o8;
reg [4:0] o9;
reg [4:0] o10;
reg [4:0] o11;
reg [4:0] odd, numerator;
wire [4:0] tmp;
rsdec_chien_scale0 x0 (scale0, data0);
rsdec_chien_scale1 x1 (scale1, data1);
rsdec_chien_scale2 x2 (scale2, data2);
rsdec_chien_scale3 x3 (scale3, data3);
rsdec_chien_scale4 x4 (scale4, data4);
rsdec_chien_scale5 x5 (scale5, data5);
rsdec_chien_scale6 x6 (scale6, data6);
rsdec_chien_scale7 x7 (scale7, data7);
rsdec_chien_scale8 x8 (scale8, data8);
rsdec_chien_scale9 x9 (scale9, data9);
rsdec_chien_scale10 x10 (scale10, data10);
rsdec_chien_scale11 x11 (scale11, data11);
rsdec_chien_scale0 x12 (scale12, o0);
rsdec_chien_scale1 x13 (scale13, o1);
rsdec_chien_scale2 x14 (scale14, o2);
rsdec_chien_scale3 x15 (scale15, o3);
rsdec_chien_scale4 x16 (scale16, o4);
rsdec_chien_scale5 x17 (scale17, o5);
rsdec_chien_scale6 x18 (scale18, o6);
rsdec_chien_scale7 x19 (scale19, o7);
rsdec_chien_scale8 x20 (scale20, o8);
rsdec_chien_scale9 x21 (scale21, o9);
rsdec_chien_scale10 x22 (scale22, o10);
rsdec_chien_scale11 x23 (scale23, o11);
always @ (shorten or a0 or l0)
if (shorten) data0 = a0;
else data0 = l0;
always @ (shorten or a1 or l1)
if (shorten) data1 = a1;
else data1 = l1;
always @ (shorten or a2 or l2)
if (shorten) data2 = a2;
else data2 = l2;
always @ (shorten or a3 or l3)
if (shorten) data3 = a3;
else data3 = l3;
always @ (shorten or a4 or l4)
if (shorten) data4 = a4;
else data4 = l4;
always @ (shorten or a5 or l5)
if (shorten) data5 = a5;
else data5 = l5;
always @ (shorten or a6 or l6)
if (shorten) data6 = a6;
else data6 = l6;
always @ (shorten or a7 or l7)
if (shorten) data7 = a7;
else data7 = l7;
always @ (shorten or a8 or l8)
if (shorten) data8 = a8;
else data8 = l8;
always @ (shorten or a9 or l9)
if (shorten) data9 = a9;
else data9 = l9;
always @ (shorten or a10 or l10)
if (shorten) data10 = a10;
else data10 = l10;
always @ (shorten or a11 or l11)
if (shorten) data11 = a11;
else data11 = l11;
always @ (posedge clk)// or negedge clrn)
begin
if (~clrn)
begin
l0 <= 0;
l1 <= 0;
l2 <= 0;
l3 <= 0;
l4 <= 0;
l5 <= 0;
l6 <= 0;
l7 <= 0;
l8 <= 0;
l9 <= 0;
l10 <= 0;
l11 <= 0;
o0 <= 0;
o1 <= 0;
o2 <= 0;
o3 <= 0;
o4 <= 0;
o5 <= 0;
o6 <= 0;
o7 <= 0;
o8 <= 0;
o9 <= 0;
o10 <= 0;
o11 <= 0;
a0 <= 1;
a1 <= 1;
a2 <= 1;
a3 <= 1;
a4 <= 1;
a5 <= 1;
a6 <= 1;
a7 <= 1;
a8 <= 1;
a9 <= 1;
a10 <= 1;
a11 <= 1;
end
else if (shorten)
begin
a0 <= scale0;
a1 <= scale1;
a2 <= scale2;
a3 <= scale3;
a4 <= scale4;
a5 <= scale5;
a6 <= scale6;
a7 <= scale7;
a8 <= scale8;
a9 <= scale9;
a10 <= scale10;
a11 <= scale11;
end
else if (search)
begin
l0 <= scale0;
l1 <= scale1;
l2 <= scale2;
l3 <= scale3;
l4 <= scale4;
l5 <= scale5;
l6 <= scale6;
l7 <= scale7;
l8 <= scale8;
l9 <= scale9;
l10 <= scale10;
l11 <= scale11;
o0 <= scale12;
o1 <= scale13;
o2 <= scale14;
o3 <= scale15;
o4 <= scale16;
o5 <= scale17;
o6 <= scale18;
o7 <= scale19;
o8 <= scale20;
o9 <= scale21;
o10 <= scale22;
o11 <= scale23;
end
else if (load)
begin
l0 <= lambda;
l1 <= l0;
l2 <= l1;
l3 <= l2;
l4 <= l3;
l5 <= l4;
l6 <= l5;
l7 <= l6;
l8 <= l7;
l9 <= l8;
l10 <= l9;
l11 <= l10;
o0 <= omega;
o1 <= o0;
o2 <= o1;
o3 <= o2;
o4 <= o3;
o5 <= o4;
o6 <= o5;
o7 <= o6;
o8 <= o7;
o9 <= o8;
o10 <= o9;
o11 <= o10;
a0 <= a11;
a1 <= a0;
a2 <= a1;
a3 <= a2;
a4 <= a3;
a5 <= a4;
a6 <= a5;
a7 <= a6;
a8 <= a7;
a9 <= a8;
a10 <= a9;
a11 <= a10;
end
end
always @ (l0 or l2 or l4 or l6 or l8 or l10)
even = l0 ^ l2 ^ l4 ^ l6 ^ l8 ^ l10;
always @ (l1 or l3 or l5 or l7 or l9 or l11)
odd = l1 ^ l3 ^ l5 ^ l7 ^ l9 ^ l11;
always @ (o0 or o1 or o2 or o3 or o4 or o5 or o6 or o7 or o8 or o9 or o10 or o11)
numerator = o0 ^ o1 ^ o2 ^ o3 ^ o4 ^ o5 ^ o6 ^ o7 ^ o8 ^ o9 ^ o10 ^ o11;
multiply m0 (tmp, numerator, D);
always @ (even or odd or tmp)
if (even == odd) error = tmp;
else error = 0;
always @ (a11) alpha = a11;
endmodule
// -------------------------------------------------------------------------
//Syndrome generator circuit in Reed-Solomon Decoder
//Copyright (C) Tue Apr 2 17:22:07 2002
//by Ming-Han Lei([email protected])
//
//This program is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public License
//as published by the Free Software Foundation; either version 2
//of the License, or (at your option) any later version.
//
//This program is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with this program; if not, write to the Free Software
//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
// --------------------------------------------------------------------------
module rsdec_syn_m0 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[4];
y[1] = x[0];
y[2] = x[1] ^ x[4];
y[3] = x[2];
y[4] = x[3];
end
endmodule
module rsdec_syn_m1 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[3];
y[1] = x[4];
y[2] = x[0] ^ x[3];
y[3] = x[1] ^ x[4];
y[4] = x[2];
end
endmodule
module rsdec_syn_m2 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[2];
y[1] = x[3];
y[2] = x[2] ^ x[4];
y[3] = x[0] ^ x[3];
y[4] = x[1] ^ x[4];
end
endmodule
module rsdec_syn_m3 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[1] ^ x[4];
y[1] = x[2];
y[2] = x[1] ^ x[3] ^ x[4];
y[3] = x[2] ^ x[4];
y[4] = x[0] ^ x[3];
end
endmodule
module rsdec_syn_m4 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[0] ^ x[3];
y[1] = x[1] ^ x[4];
y[2] = x[0] ^ x[2] ^ x[3];
y[3] = x[1] ^ x[3] ^ x[4];
y[4] = x[2] ^ x[4];
end
endmodule
module rsdec_syn_m5 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[2] ^ x[4];
y[1] = x[0] ^ x[3];
y[2] = x[1] ^ x[2];
y[3] = x[0] ^ x[2] ^ x[3];
y[4] = x[1] ^ x[3] ^ x[4];
end
endmodule
module rsdec_syn_m6 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[1] ^ x[3] ^ x[4];
y[1] = x[2] ^ x[4];
y[2] = x[0] ^ x[1] ^ x[4];
y[3] = x[1] ^ x[2];
y[4] = x[0] ^ x[2] ^ x[3];
end
endmodule
module rsdec_syn_m7 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[0] ^ x[2] ^ x[3];
y[1] = x[1] ^ x[3] ^ x[4];
y[2] = x[0] ^ x[3] ^ x[4];
y[3] = x[0] ^ x[1] ^ x[4];
y[4] = x[1] ^ x[2];
end
endmodule
module rsdec_syn_m8 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[1] ^ x[2];
y[1] = x[0] ^ x[2] ^ x[3];
y[2] = x[2] ^ x[3] ^ x[4];
y[3] = x[0] ^ x[3] ^ x[4];
y[4] = x[0] ^ x[1] ^ x[4];
end
endmodule
module rsdec_syn_m9 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[0] ^ x[1] ^ x[4];
y[1] = x[1] ^ x[2];
y[2] = x[1] ^ x[2] ^ x[3] ^ x[4];
y[3] = x[2] ^ x[3] ^ x[4];
y[4] = x[0] ^ x[3] ^ x[4];
end
endmodule
module rsdec_syn_m10 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[0] ^ x[3] ^ x[4];
y[1] = x[0] ^ x[1] ^ x[4];
y[2] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4];
y[3] = x[1] ^ x[2] ^ x[3] ^ x[4];
y[4] = x[2] ^ x[3] ^ x[4];
end
endmodule
module rsdec_syn_m11 (y, x);
input [4:0] x;
output [4:0] y;
reg [4:0] y;
always @ (x)
begin
y[0] = x[2] ^ x[3] ^ x[4];
y[1] = x[0] ^ x[3] ^ x[4];
y[2] = x[0] ^ x[1] ^ x[2] ^ x[3];
y[3] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4];
y[4] = x[1] ^ x[2] ^ x[3] ^ x[4];
end
endmodule
module rsdec_syn (y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, u, enable, shift, init, clk, clrn);
input [4:0] u;
input clk, clrn, shift, init, enable;
output [4:0] y0;
output [4:0] y1;
output [4:0] y2;
output [4:0] y3;
output [4:0] y4;
output [4:0] y5;
output [4:0] y6;
output [4:0] y7;
output [4:0] y8;
output [4:0] y9;
output [4:0] y10;
output [4:0] y11;
reg [4:0] y0;
reg [4:0] y1;
reg [4:0] y2;
reg [4:0] y3;
reg [4:0] y4;
reg [4:0] y5;
reg [4:0] y6;
reg [4:0] y7;
reg [4:0] y8;
reg [4:0] y9;
reg [4:0] y10;
reg [4:0] y11;
wire [4:0] scale0;
wire [4:0] scale1;
wire [4:0] scale2;
wire [4:0] scale3;
wire [4:0] scale4;
wire [4:0] scale5;
wire [4:0] scale6;
wire [4:0] scale7;
wire [4:0] scale8;
wire [4:0] scale9;
wire [4:0] scale10;
wire [4:0] scale11;
rsdec_syn_m0 m0 (scale0, y0);
rsdec_syn_m1 m1 (scale1, y1);
rsdec_syn_m2 m2 (scale2, y2);
rsdec_syn_m3 m3 (scale3, y3);
rsdec_syn_m4 m4 (scale4, y4);
rsdec_syn_m5 m5 (scale5, y5);
rsdec_syn_m6 m6 (scale6, y6);
rsdec_syn_m7 m7 (scale7, y7);
rsdec_syn_m8 m8 (scale8, y8);
rsdec_syn_m9 m9 (scale9, y9);
rsdec_syn_m10 m10 (scale10, y10);
rsdec_syn_m11 m11 (scale11, y11);
always @ (posedge clk)// or negedge clrn)
begin
if (~clrn)
begin
y0 <= 0;
y1 <= 0;
y2 <= 0;
y3 <= 0;
y4 <= 0;
y5 <= 0;
y6 <= 0;
y7 <= 0;
y8 <= 0;
y9 <= 0;
y10 <= 0;
y11 <= 0;
end
else if (init)
begin
y0 <= u;
y1 <= u;
y2 <= u;
y3 <= u;
y4 <= u;
y5 <= u;
y6 <= u;
y7 <= u;
y8 <= u;
y9 <= u;
y10 <= u;
y11 <= u;
end
else if (enable)
begin
y0 <= scale0 ^ u;
y1 <= scale1 ^ u;
y2 <= scale2 ^ u;
y3 <= scale3 ^ u;
y4 <= scale4 ^ u;
y5 <= scale5 ^ u;
y6 <= scale6 ^ u;
y7 <= scale7 ^ u;
y8 <= scale8 ^ u;
y9 <= scale9 ^ u;
y10 <= scale10 ^ u;
y11 <= scale11 ^ u;
end
else if (shift)
begin
y0 <= y1;
y1 <= y2;
y2 <= y3;
y3 <= y4;
y4 <= y5;
y5 <= y6;
y6 <= y7;
y7 <= y8;
y8 <= y9;
y9 <= y10;
y10 <= y11;
y11 <= y0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAH_4_V
`define SKY130_FD_SC_MS__FAH_4_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fah_4 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fah_4 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAH_4_V
|
/* Generated by Yosys 0.7 (git sha1 61f6811, gcc 5.4.0-6ubuntu1~16.04.4 -O2 -fstack-protector-strong -fPIC -Os) */
(* top = 1 *)
(* src = "var17_multi.v:2" *)
module var17_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire _316_;
wire _317_;
wire _318_;
wire _319_;
wire _320_;
wire _321_;
wire _322_;
wire _323_;
wire _324_;
wire _325_;
wire _326_;
wire _327_;
wire _328_;
wire _329_;
wire _330_;
wire _331_;
wire _332_;
wire _333_;
wire _334_;
wire _335_;
wire _336_;
wire _337_;
wire _338_;
wire _339_;
wire _340_;
wire _341_;
wire _342_;
wire _343_;
wire _344_;
wire _345_;
wire _346_;
wire _347_;
wire _348_;
wire _349_;
wire _350_;
wire _351_;
wire _352_;
wire _353_;
wire _354_;
wire _355_;
wire _356_;
wire _357_;
wire _358_;
wire _359_;
wire _360_;
wire _361_;
wire _362_;
wire _363_;
wire _364_;
wire _365_;
wire _366_;
wire _367_;
wire _368_;
wire _369_;
wire _370_;
wire _371_;
wire _372_;
wire _373_;
wire _374_;
wire _375_;
wire _376_;
wire _377_;
wire _378_;
wire _379_;
wire _380_;
wire _381_;
wire _382_;
wire _383_;
wire _384_;
wire _385_;
wire _386_;
wire _387_;
wire _388_;
wire _389_;
wire _390_;
wire _391_;
wire _392_;
wire _393_;
wire _394_;
wire _395_;
wire _396_;
wire _397_;
wire _398_;
wire _399_;
wire _400_;
wire _401_;
wire _402_;
wire _403_;
wire _404_;
wire _405_;
wire _406_;
wire _407_;
wire _408_;
wire _409_;
wire _410_;
wire _411_;
wire _412_;
wire _413_;
wire _414_;
wire _415_;
wire _416_;
wire _417_;
wire _418_;
wire _419_;
wire _420_;
wire _421_;
wire _422_;
wire _423_;
wire _424_;
wire _425_;
wire _426_;
wire _427_;
wire _428_;
wire _429_;
wire _430_;
wire _431_;
wire _432_;
wire _433_;
wire _434_;
wire _435_;
wire _436_;
wire _437_;
wire _438_;
wire _439_;
wire _440_;
wire _441_;
wire _442_;
wire _443_;
wire _444_;
wire _445_;
wire _446_;
wire _447_;
wire _448_;
wire _449_;
wire _450_;
wire _451_;
wire _452_;
wire _453_;
wire _454_;
wire _455_;
wire _456_;
wire _457_;
wire _458_;
wire _459_;
wire _460_;
wire _461_;
wire _462_;
wire _463_;
wire _464_;
wire _465_;
wire _466_;
wire _467_;
wire _468_;
wire _469_;
wire _470_;
wire _471_;
wire _472_;
wire _473_;
(* src = "var17_multi.v:3" *)
input A;
(* src = "var17_multi.v:3" *)
input B;
(* src = "var17_multi.v:3" *)
input C;
(* src = "var17_multi.v:3" *)
input D;
(* src = "var17_multi.v:3" *)
input E;
(* src = "var17_multi.v:3" *)
input F;
(* src = "var17_multi.v:3" *)
input G;
(* src = "var17_multi.v:3" *)
input H;
(* src = "var17_multi.v:3" *)
input I;
(* src = "var17_multi.v:3" *)
input J;
(* src = "var17_multi.v:3" *)
input K;
(* src = "var17_multi.v:3" *)
input L;
(* src = "var17_multi.v:3" *)
input M;
(* src = "var17_multi.v:3" *)
input N;
(* src = "var17_multi.v:3" *)
input O;
(* src = "var17_multi.v:3" *)
input P;
(* src = "var17_multi.v:3" *)
input Q;
(* src = "var17_multi.v:4" *)
output valid;
assign _090_ = ~N;
assign _101_ = ~I;
assign _112_ = G ^ E;
assign _123_ = _112_ ^ H;
assign _134_ = _123_ ^ _101_;
assign _145_ = _134_ ^ J;
assign _156_ = _145_ ^ K;
assign _167_ = ~(_156_ | _090_);
assign _178_ = ~(_145_ & K);
assign _189_ = ~_178_;
assign _200_ = _112_ & H;
assign _211_ = ~F;
assign _222_ = D ^ A;
assign _233_ = _222_ ^ _211_;
assign _244_ = ~(_233_ & _200_);
assign _255_ = ~(G & E);
assign _266_ = _233_ ^ _255_;
assign _277_ = ~H;
assign _288_ = _112_ | _277_;
assign _299_ = _266_ ? _288_ : H;
assign _310_ = _299_ & _244_;
assign _331_ = _123_ | _101_;
assign _332_ = ~(_134_ & J);
assign _343_ = _332_ & _331_;
assign _354_ = _343_ ^ _310_;
assign _365_ = _354_ ^ _189_;
assign _376_ = ~_365_;
assign _387_ = _376_ & _167_;
assign _408_ = ~L;
assign _409_ = ~(_310_ | _332_);
assign _420_ = ~(_354_ & _189_);
assign _424_ = ~((_310_ | _123_) & I);
assign _425_ = ~(_233_ | _255_);
assign _426_ = _222_ | _211_;
assign _427_ = ~E;
assign _428_ = ~B;
assign _429_ = ~(D & A);
assign _430_ = _429_ ^ _428_;
assign _431_ = _430_ ^ _427_;
assign _432_ = _431_ ^ _426_;
assign _433_ = _432_ ^ _425_;
assign _434_ = ~(_266_ | _277_);
assign _435_ = ~(_434_ & _244_);
assign _436_ = _435_ ^ _433_;
assign _437_ = _436_ ^ _424_;
assign _438_ = _437_ ^ _420_;
assign _439_ = _438_ ^ _409_;
assign _440_ = _439_ ^ _408_;
assign _441_ = _440_ & _387_;
assign _442_ = _439_ | _408_;
assign _443_ = _437_ | _420_;
assign _444_ = ~(_436_ | _424_);
assign _445_ = ~((_433_ | _266_) & H);
assign _446_ = ~((_433_ | _244_) & _445_);
assign _447_ = _432_ & _425_;
assign _448_ = _430_ & E;
assign _449_ = ~D;
assign _450_ = B & A;
assign _451_ = ~(_450_ | _449_);
assign _452_ = _451_ ^ _448_;
assign _453_ = ~_222_;
assign _454_ = ~((_431_ & _453_) | _211_);
assign _455_ = _454_ ^ _452_;
assign _456_ = _455_ ^ G;
assign _457_ = _456_ ^ _447_;
assign _458_ = _457_ ^ _446_;
assign _459_ = _458_ ^ _444_;
assign _460_ = ~J;
assign _461_ = ~_310_;
assign _462_ = _461_ & _134_;
assign _463_ = ~_437_;
assign _464_ = ~((_463_ & _462_) | _460_);
assign _465_ = _464_ ^ _459_;
assign _466_ = _465_ ^ _443_;
assign _467_ = _466_ ^ _442_;
assign _468_ = _467_ ^ M;
assign _469_ = _468_ ^ N;
assign _470_ = _469_ ^ _441_;
assign _471_ = _470_ & O;
assign _472_ = _156_ ^ _090_;
assign _473_ = _472_ & O;
assign _000_ = _473_ & _376_;
assign _001_ = _440_ ^ _387_;
assign _002_ = _001_ & _000_;
assign _003_ = _470_ ^ O;
assign _004_ = ~((_003_ & _002_) | _471_);
assign _005_ = _468_ & N;
assign _006_ = ~((_469_ & _441_) | _005_);
assign _007_ = _464_ & _459_;
assign _008_ = ~(_455_ & G);
assign _009_ = ~(_456_ & _447_);
assign _010_ = _009_ & _008_;
assign _011_ = _450_ & D;
assign _012_ = _451_ & _448_;
assign _013_ = _012_ | _011_;
assign _014_ = ~((_454_ & _452_) | _013_);
assign _015_ = _014_ ^ _010_;
assign _016_ = ~(_457_ & _446_);
assign _017_ = ~(_458_ & _444_);
assign _018_ = _017_ & _016_;
assign _019_ = _018_ ^ _015_;
assign _020_ = ~(_019_ ^ _007_);
assign _021_ = ~(_354_ & _145_);
assign _022_ = _437_ | _021_;
assign _023_ = _465_ | _022_;
assign _024_ = _023_ & K;
assign _025_ = ~(_024_ ^ _020_);
assign _026_ = _466_ | _442_;
assign _027_ = ~(_467_ & M);
assign _028_ = _027_ & _026_;
assign _029_ = ~(_028_ ^ _025_);
assign _030_ = ~(_029_ ^ _006_);
assign _031_ = _030_ | _004_;
assign _032_ = ~P;
assign _033_ = ~(_473_ | _167_);
assign _034_ = _033_ ^ _376_;
assign _035_ = _001_ ^ _000_;
assign _036_ = _472_ ^ O;
assign _037_ = ~(_036_ | _035_);
assign _038_ = ~((_037_ & _034_) | _032_);
assign _039_ = ~Q;
assign _040_ = ~(_036_ | _032_);
assign _041_ = _040_ | J;
assign _042_ = ~((_036_ & _032_) | _041_);
assign _043_ = ~((_042_ & _034_) | _039_);
assign _044_ = _040_ & _034_;
assign _045_ = _044_ ^ _035_;
assign _046_ = _045_ | _043_;
assign _047_ = _046_ | _038_;
assign _048_ = _003_ ^ _002_;
assign _049_ = _046_ & _038_;
assign _050_ = ~((_049_ | _048_) & _047_);
assign _051_ = _029_ | _006_;
assign _052_ = ~(_025_ | _027_);
assign _053_ = _025_ | _026_;
assign _054_ = ~_015_;
assign _055_ = ~_016_;
assign _056_ = ~(_014_ | _010_);
assign _057_ = ~(_014_ & _010_);
assign _058_ = ~((_057_ & _055_) | _056_);
assign _059_ = ~((_054_ | _017_) & _058_);
assign _060_ = ~_007_;
assign _061_ = _019_ | _060_;
assign _062_ = ~(_024_ & _020_);
assign _063_ = _062_ & _061_;
assign _064_ = _063_ ^ _059_;
assign _065_ = _064_ ^ _053_;
assign _066_ = ~(_065_ ^ _052_);
assign _067_ = ~(_066_ ^ _051_);
assign _068_ = _030_ & _004_;
assign _069_ = _068_ | _067_;
assign _070_ = ~((_050_ & _031_) | _069_);
assign _071_ = ~_062_;
assign _072_ = ~(_059_ & _071_);
assign _073_ = ~((_064_ | _053_) & _072_);
assign _074_ = ~((_065_ & _052_) | _073_);
assign _075_ = ~((_066_ | _051_) & _074_);
assign _076_ = _075_ | _070_;
assign _077_ = ~O;
assign _078_ = ~(B ^ A);
assign _079_ = _078_ ^ _460_;
assign _080_ = _079_ ^ K;
assign _081_ = _080_ & M;
assign _082_ = ~(_079_ & K);
assign _083_ = ~(B | A);
assign _084_ = J ? _450_ : _083_;
assign _085_ = _084_ ^ _082_;
assign _086_ = _085_ ^ L;
assign _087_ = ~(_086_ ^ _081_);
assign _088_ = ~M;
assign _089_ = _080_ ^ _088_;
assign _091_ = _089_ & _087_;
assign _092_ = _091_ | _077_;
assign _093_ = _086_ & _081_;
assign _094_ = ~C;
assign _095_ = _450_ ^ _094_;
assign _096_ = _095_ ^ _449_;
assign _097_ = _096_ ^ G;
assign _098_ = _097_ ^ H;
assign _099_ = _098_ ^ I;
assign _100_ = _083_ & J;
assign _102_ = _100_ ^ _099_;
assign _103_ = _102_ ^ K;
assign _104_ = ~(_084_ | _082_);
assign _105_ = _085_ & L;
assign _106_ = _105_ | _104_;
assign _107_ = _106_ ^ _103_;
assign _108_ = ~(_107_ ^ _093_);
assign _109_ = _108_ ^ N;
assign _110_ = ~(_109_ | _092_);
assign _111_ = _108_ & N;
assign _113_ = _107_ & _093_;
assign _114_ = _103_ & _105_;
assign _115_ = ~_104_;
assign _116_ = ~(_102_ & K);
assign _117_ = ~(_116_ & _115_);
assign _118_ = ~(_083_ | _460_);
assign _119_ = _099_ & J;
assign _120_ = ~(_119_ | _118_);
assign _121_ = _098_ | _101_;
assign _122_ = _095_ | _449_;
assign _124_ = ~((_450_ & _094_) | _083_);
assign _125_ = _124_ ^ _122_;
assign _126_ = _125_ ^ _211_;
assign _127_ = _096_ & G;
assign _128_ = ~((_097_ & H) | _127_);
assign _129_ = ~(_128_ ^ _126_);
assign _130_ = _129_ ^ J;
assign _131_ = ~(_130_ ^ _121_);
assign _132_ = _131_ ^ _120_;
assign _133_ = ~(_132_ ^ _117_);
assign _135_ = _133_ ^ _114_;
assign _136_ = _135_ ^ M;
assign _137_ = ~(_136_ ^ _113_);
assign _138_ = ~(_137_ ^ _111_);
assign _139_ = _138_ & _110_;
assign _140_ = _137_ & _111_;
assign _141_ = ~(_135_ & M);
assign _142_ = ~(_136_ & _113_);
assign _143_ = ~(_142_ & _141_);
assign _144_ = _133_ & _114_;
assign _146_ = ~((_116_ & _115_) | _132_);
assign _147_ = _129_ & J;
assign _148_ = _147_ | _119_;
assign _149_ = ~((_131_ & _118_) | _148_);
assign _150_ = ~((_129_ | _098_) & I);
assign _151_ = ~(_126_ & _127_);
assign _152_ = _125_ & F;
assign _153_ = ~_083_;
assign _154_ = ~(D & C);
assign _155_ = ~((_154_ | _450_) & _153_);
assign _157_ = _155_ ^ _152_;
assign _158_ = _157_ ^ _151_;
assign _159_ = _097_ & H;
assign _160_ = _126_ & _159_;
assign _161_ = _160_ | _277_;
assign _162_ = _161_ ^ _158_;
assign _163_ = ~(_162_ ^ _150_);
assign _164_ = _163_ ^ _149_;
assign _165_ = _164_ ^ _146_;
assign _166_ = _165_ ^ _144_;
assign _168_ = ~(_166_ ^ _143_);
assign _169_ = ~(_168_ ^ _140_);
assign _170_ = _169_ ^ O;
assign _171_ = _170_ ^ _139_;
assign _172_ = _171_ & P;
assign _173_ = _089_ & O;
assign _174_ = _173_ ^ _087_;
assign _175_ = _174_ | _032_;
assign _176_ = ~(_109_ ^ _092_);
assign _177_ = _176_ | _175_;
assign _179_ = ~(_138_ ^ _110_);
assign _180_ = ~(_179_ | _177_);
assign _181_ = _171_ | P;
assign _182_ = ~((_181_ & _180_) | _172_);
assign _183_ = _169_ & O;
assign _184_ = _170_ & _139_;
assign _185_ = _184_ | _183_;
assign _186_ = _166_ & _143_;
assign _187_ = _165_ & _144_;
assign _188_ = _164_ & _146_;
assign _190_ = ~((_158_ & H) | _160_);
assign _191_ = ~(_157_ | _151_);
assign _192_ = _155_ & _125_;
assign _193_ = _192_ | _211_;
assign _194_ = D & C;
assign _195_ = ~((_194_ & _153_) | _450_);
assign _196_ = _195_ ^ _193_;
assign _197_ = ~(_196_ ^ _191_);
assign _198_ = _197_ ^ _190_;
assign _199_ = _162_ | _150_;
assign _201_ = ~((_163_ | _149_) & _199_);
assign _202_ = _201_ ^ _198_;
assign _203_ = _202_ ^ _188_;
assign _204_ = _203_ ^ _187_;
assign _205_ = _204_ ^ _186_;
assign _206_ = _137_ & _108_;
assign _207_ = ~((_168_ & _206_) | _090_);
assign _208_ = _207_ ^ _205_;
assign _209_ = ~(_208_ ^ _185_);
assign _210_ = _209_ | _182_;
assign _212_ = _204_ & _186_;
assign _213_ = ~((_207_ & _205_) | _212_);
assign _214_ = ~(_202_ & _188_);
assign _215_ = ~(_203_ & _187_);
assign _216_ = ~(_215_ & _214_);
assign _217_ = ~(_163_ | _149_);
assign _218_ = ~(_198_ & _217_);
assign _219_ = ~(_162_ | _150_);
assign _220_ = ~(_195_ | _193_);
assign _221_ = ~((_196_ & _191_) | _220_);
assign _223_ = ~((_197_ | _190_) & _221_);
assign _224_ = ~((_198_ & _219_) | _223_);
assign _225_ = ~(_224_ ^ _218_);
assign _226_ = _225_ ^ _216_;
assign _227_ = ~(_226_ | _213_);
assign _228_ = E ^ C;
assign _229_ = _228_ ^ H;
assign _230_ = _229_ ^ K;
assign _231_ = _230_ & L;
assign _232_ = D | C;
assign _234_ = _232_ & _154_;
assign _235_ = E ? _449_ : _234_;
assign _236_ = _235_ ^ G;
assign _237_ = _228_ & H;
assign _238_ = _229_ & K;
assign _239_ = ~(_238_ | _237_);
assign _240_ = ~(_239_ ^ _236_);
assign _241_ = _240_ ^ _231_;
assign _242_ = _241_ ^ _090_;
assign _243_ = _242_ ^ O;
assign _245_ = _230_ ^ L;
assign _246_ = _245_ ^ _039_;
assign _247_ = _236_ & _237_;
assign _248_ = ~G;
assign _249_ = _235_ | _248_;
assign _250_ = _194_ ^ A;
assign _251_ = _232_ & E;
assign _252_ = _251_ ^ _250_;
assign _253_ = _252_ ^ _211_;
assign _254_ = _253_ ^ _249_;
assign _256_ = _254_ ^ _247_;
assign _257_ = _256_ ^ I;
assign _258_ = ~K;
assign _259_ = _238_ & _236_;
assign _260_ = ~(_259_ | _258_);
assign _261_ = _260_ ^ _257_;
assign _262_ = _240_ & _231_;
assign _263_ = ~(_262_ | _408_);
assign _264_ = _263_ ^ _261_;
assign _265_ = ~(_241_ | _090_);
assign _267_ = ~((_242_ & O) | _265_);
assign _268_ = _267_ ^ _264_;
assign _269_ = _268_ ^ _032_;
assign _270_ = ~_264_;
assign _271_ = ~((_242_ & _270_) | _077_);
assign _272_ = ~((_257_ & K) | _259_);
assign _273_ = ~_235_;
assign _274_ = _253_ & _273_;
assign _275_ = _274_ | _248_;
assign _276_ = _252_ | _211_;
assign _278_ = _251_ & _250_;
assign _279_ = _278_ | _427_;
assign _280_ = _429_ & C;
assign _281_ = _280_ ^ _078_;
assign _282_ = _281_ ^ _279_;
assign _283_ = _282_ ^ _276_;
assign _284_ = _283_ ^ _275_;
assign _285_ = _254_ & _247_;
assign _286_ = ~((_256_ & I) | _285_);
assign _287_ = _286_ ^ _284_;
assign _289_ = _287_ ^ _272_;
assign _290_ = _289_ ^ _408_;
assign _291_ = ~((_261_ & L) | _262_);
assign _292_ = ~(_291_ ^ _290_);
assign _293_ = _292_ ^ M;
assign _294_ = _265_ & _270_;
assign _295_ = _294_ ^ _293_;
assign _296_ = ~(_295_ ^ _271_);
assign _297_ = _268_ & P;
assign _298_ = ~(_297_ ^ _296_);
assign _300_ = ~_243_;
assign _301_ = ~(_245_ | _300_);
assign _302_ = _269_ & Q;
assign _303_ = ~((_302_ | _298_) & (_301_ | _039_));
assign _304_ = _301_ & Q;
assign _305_ = ~((_304_ | _269_) & _303_);
assign _306_ = ~((_246_ & _243_) | _305_);
assign _307_ = ~_268_;
assign _308_ = ~((_307_ | _296_) & P);
assign _309_ = ~(_292_ | _088_);
assign _311_ = ~_262_;
assign _312_ = _311_ | _261_;
assign _313_ = ~((_289_ | _261_) & L);
assign _314_ = ~((_312_ | _290_) & _313_);
assign _315_ = ~(_287_ | _272_);
assign _316_ = _284_ & _285_;
assign _317_ = _283_ | _275_;
assign _318_ = _282_ | _276_;
assign _319_ = ~(_281_ | _427_);
assign _320_ = _319_ | _278_;
assign _321_ = ~A;
assign _322_ = B & _321_;
assign _323_ = B | _321_;
assign _324_ = ~((_323_ & _094_) | _322_);
assign _325_ = _324_ ^ D;
assign _326_ = ~((_011_ & C) | _325_);
assign _327_ = _326_ ^ _427_;
assign _328_ = _327_ ^ _320_;
assign _329_ = _328_ ^ _318_;
assign _330_ = _329_ ^ _317_;
assign _333_ = ~(_330_ ^ _316_);
assign _334_ = ~(_284_ & _256_);
assign _335_ = ~(_334_ & I);
assign _336_ = _335_ ^ _333_;
assign _337_ = _336_ ^ _315_;
assign _338_ = _337_ ^ _314_;
assign _339_ = _338_ ^ _309_;
assign _340_ = ~(_241_ | _264_);
assign _341_ = ~((_340_ & _293_) | _090_);
assign _342_ = ~(_341_ ^ _339_);
assign _344_ = ~_295_;
assign _345_ = ~(_344_ & _271_);
assign _346_ = _345_ & O;
assign _347_ = _346_ ^ _342_;
assign _348_ = ~(_347_ | _308_);
assign _349_ = _348_ | Q;
assign _350_ = _349_ | _306_;
assign _351_ = ~((_342_ | _077_) & _345_);
assign _352_ = _337_ & _314_;
assign _353_ = _336_ & _315_;
assign _355_ = ~((_334_ & _333_) | _101_);
assign _356_ = _330_ & _316_;
assign _357_ = ~(_329_ | _317_);
assign _358_ = _282_ | _252_;
assign _359_ = ~((_328_ | _358_) & F);
assign _360_ = ~((_326_ & _281_) | _279_);
assign _361_ = ~(_324_ & D);
assign _362_ = ~(_450_ | C);
assign _363_ = ~((_362_ | _083_) & _361_);
assign _364_ = ~((_194_ & A) | _278_);
assign _366_ = ~((_364_ & _363_) | _360_);
assign _367_ = _366_ ^ _359_;
assign _368_ = ~(_367_ ^ _357_);
assign _369_ = ~(_368_ | _356_);
assign _370_ = _369_ ^ _355_;
assign _371_ = _370_ ^ _353_;
assign _372_ = ~(_371_ ^ _352_);
assign _373_ = _338_ & _309_;
assign _374_ = ~((_341_ & _339_) | _373_);
assign _375_ = _374_ ^ _372_;
assign _377_ = _375_ | _351_;
assign _378_ = ~(_347_ & _308_);
assign _379_ = _378_ & _377_;
assign _380_ = ~((_379_ & _350_) | _227_);
assign _381_ = ~((_184_ | _183_) & _208_);
assign _382_ = ~_301_;
assign _383_ = ~((_269_ | _382_) & Q);
assign _384_ = ~(_383_ | _298_);
assign _385_ = _306_ & Q;
assign _386_ = ~((_385_ | _384_) & (_377_ | _348_));
assign _388_ = _226_ ^ _213_;
assign _389_ = _375_ & _351_;
assign _390_ = _367_ & _357_;
assign _391_ = _390_ | _356_;
assign _392_ = _366_ | _359_;
assign _393_ = _392_ ^ _364_;
assign _394_ = _393_ | _391_;
assign _395_ = _369_ & _355_;
assign _396_ = ~((_370_ & _353_) | _395_);
assign _397_ = _396_ ^ _394_;
assign _398_ = _371_ & _352_;
assign _399_ = _371_ | _352_;
assign _400_ = ~((_398_ | _373_) & _399_);
assign _401_ = ~(_400_ & _397_);
assign _402_ = ~(_341_ & _339_);
assign _403_ = _225_ | _215_;
assign _404_ = _225_ | _214_;
assign _405_ = ~((_392_ | _364_) & (_224_ | _218_));
assign _406_ = ~((_394_ & _395_) | _405_);
assign _407_ = _406_ & _404_;
assign _410_ = _407_ & _403_;
assign _411_ = ~((_372_ | _402_) & _410_);
assign _412_ = ~(_370_ & _353_);
assign _413_ = ~_394_;
assign _414_ = ~((_400_ | _397_) & (_413_ | _412_));
assign _415_ = _414_ | _411_;
assign _416_ = _415_ | _401_;
assign _417_ = _416_ | _389_;
assign _418_ = ~((_388_ & _381_) | _417_);
assign _419_ = _418_ & _386_;
assign _421_ = _419_ & _381_;
assign _422_ = _421_ & _380_;
assign _423_ = _422_ & _210_;
assign valid = _423_ & _076_;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_regfile_reg1 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 31: 0] in_port;
input reset_n;
wire clk_en;
wire [ 31: 0] data_in;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:18:18 10/17/2016
// Design Name:
// Module Name: num_6
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module num_6(
input [2:0] in_row,
output reg [4:0] out_code
);
parameter [4:0] d_0 = 5'b01110; // XXX
parameter [4:0] d_1 = 5'b00001; // X
parameter [4:0] d_2 = 5'b01111; // XXXX
parameter [4:0] d_3 = 5'b10001; // X X
always @ *
begin
case (in_row)
3'b000:
out_code = d_0;
3'b001:
out_code = d_1;
3'b010:
out_code = d_2;
3'b011:
out_code = d_3;
3'b100:
out_code = d_3;
3'b101:
out_code = d_0;
default:
out_code = 5'b0;
endcase
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/14.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2014/10/06 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
`timescale 10ns/10ns
module test;
wire button;
reg clk;
/* camera signal generator */
reg href;
reg vsync;
reg pclk;
reg [7:0] data;
parameter Tline = 786 * 2;
reg spi_clk,
spi_mosi,
cs;
initial begin
forever begin
spi_clk = 0;
spi_mosi = 0;
cs = 1;
//start
#50 spi_mosi = 1;
#10 cs = 0;
#40 spi_clk = 1;
#50 spi_clk = 0;
//2nd bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//3rd bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//4th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//5th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//6th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//7th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//8th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
#20 cs = 1;
//=========//
spi_clk = 0;
spi_mosi = 0;
cs = 1;
//start
#50 spi_mosi = 0;
#10 cs = 0;
#40 spi_clk = 1;
#50 spi_clk = 0;
//2nd bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//3rd bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//4th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//5th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//6th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
//7th bit
spi_mosi = 0;
#50 spi_clk = 1;
#50 spi_clk = 0;
//8th bit
spi_mosi = 1;
#50 spi_clk = 1;
#50 spi_clk = 0;
#20 cs = 1;
end
end
initial begin
clk = 0;
data = 0;
forever begin
#1 clk = ~clk;
end
end
initial begin
pclk = 1;
forever begin
#16 pclk = ~pclk;
end
end
always @(negedge pclk) begin
data <= data + 8'b1;
end
always @(posedge href) begin
data <= 8'h00;
end
always @(negedge href) begin
data <= 8'hxx;
end
initial begin
$dumpfile("test.vcd");
$dumpvars(0, test);
#10
repeat (10) begin
vsync = 1;
href = 0;
repeat (1 * Tline) @(negedge pclk);
vsync <= 0;
repeat (3 * Tline) @(negedge pclk);
repeat (480) begin
href <= 1;
repeat (640 * 2) @(negedge pclk);
href <= 0;
repeat (144 * 2) @(negedge pclk);
end
repeat (10 * Tline) @(negedge pclk);
end
#100 $stop;
end
wire capture;
wire [7:0] led;
wire busy;
wire locked;
balldetector bd0 (
.inclk(clk),
.ahref(href),
.avsync(vsync),
.apclk(pclk),
.xclk(xclk),
.adata(data),
.spi_clk(spi_clk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.cs(cs),
.led(led),
.i2c_clk(i2c_clk),
.i2c_sda(i2c_sda),
.busy(busy),
.pwm0(pwm)
);
endmodule
|
(** * MoreCoq: More About Coq *)
Require Export Poly.
(** This chapter introduces several more Coq tactics that,
together, allow us to prove many more theorems about the
functional programs we are writing. *)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
intros. apply H. apply H0. Qed.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will perform simplification first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
intros. rewrite H. symmetry. apply rev_involutive.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
Rewrite uses a hypothesis to rewrite (part of) the goal.
Apply replaces a goal that matches the conclusion of a hypothesis
with the premises of that hypothesis.
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
intros. rewrite H0. apply H.
Qed.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
intros. inversion H0. reflexivity.
Qed.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
intros. inversion H. Qed.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
intros. destruct n. reflexivity. inversion H. Qed.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
intros. destruct n. reflexivity. inversion H. Qed.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_zero : forall n, n + n = 0 -> n = 0.
intros. induction n. reflexivity. inversion H. Qed.
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
(* Hint: use the plus_n_Sm lemma *)
destruct m. reflexivity. intros H. inversion H.
destruct m.
intros H. inversion H.
simpl. rewrite <- plus_n_Sm, <- plus_n_Sm. intros H. inversion H.
apply IHn' in H1. rewrite H1. reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem (left as an exercise) has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
intros n. induction n.
destruct m. reflexivity. intros. inversion H.
destruct m. intros. inversion H.
intros. apply f_equal. inversion H. apply IHn. apply H.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(* nope *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []".
intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'".
intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
Case "l = []".
rewrite <- eq. reflexivity.
Case "l = v' :: l'".
simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. Abort. (* apply IHl'. *) (* The IH doesn't apply! *)
(** As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
intros n X l. generalize dependent n. induction l.
reflexivity.
destruct n. intros H. inversion H.
intros H. inversion H. rewrite H1. simpl. apply IHl. apply H1.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
nope
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
intros n X v l. generalize dependent n. induction l.
intros n H. rewrite <- H. reflexivity.
intros n H. rewrite <- H. simpl. apply f_equal. apply IHl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
intros X l1. induction l1.
intros l2 x n H. apply H.
intros l2 x0 n H. destruct n.
inversion H.
simpl. apply f_equal. apply IHl1 with x0. inversion H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
intros X n l. generalize dependent n. induction l.
intros n H. inversion H. reflexivity.
intros n H. destruct n.
inversion H.
inversion H. simpl. rewrite H1. apply f_equal. rewrite <- plus_n_Sm.
replace (length (l ++ x :: l)) with (S (length (l ++ l))).
apply f_equal. apply IHl. apply H1.
apply app_length_cons with x. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (double_induction) *)
(** Prove the following principle of induction over two naturals. *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof.
intros P H Hm Hn Hmn.
induction m.
induction n.
apply H.
apply Hn. apply IHn.
induction n.
apply Hm. apply IHm.
apply Hmn. apply IHm.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
intros. unfold override.
destruct (beq_nat k1 k2). reflexivity. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
intros X Y l. induction l.
intros l1 l2 H. inversion H. reflexivity.
intros l1 l2 H. simpl in H. destruct x. destruct (split l).
inversion H. simpl. apply f_equal. apply IHl. reflexivity.
Qed.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
intros. destruct b.
destruct (f true) eqn:Hft.
rewrite Hft. apply Hft.
destruct (f false) eqn:Hff.
rewrite Hft. reflexivity. apply Hff.
destruct (f false) eqn:Hff.
destruct (f true) eqn:Hft.
apply Hft. apply Hff. rewrite Hff. apply Hff.
Qed.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
intros. unfold override. destruct (beq_nat k1 k2) eqn:Hk.
inversion H. apply f_equal. apply beq_nat_true. apply Hk.
reflexivity.
Qed.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
intros n. induction n. destruct m. reflexivity. reflexivity.
destruct m. reflexivity. simpl. apply IHn.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
nope
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
intros n m p H1 H2.
apply beq_nat_true in H1. rewrite H1. apply H2.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
forall X Y (l : list (X * Y)) l1 l2,
length l1 = length l2
-> combine l1 l2 = l
-> split l = (l1, l2).
Theorem split_combine : split_combine_statement.
Proof.
intros X Y l. induction l.
destruct l1, l2.
reflexivity.
intros Hlen. inversion Hlen.
intros Hlen. inversion Hlen.
intros Hlen H. inversion H.
destruct l1, l2.
intros Hlen H. inversion H.
intros Hlen. inversion Hlen.
intros Hlen. inversion Hlen.
intros Hlen H. inversion Hlen. inversion H.
apply IHl in H1.
rewrite H3. simpl. rewrite H1. reflexivity. apply H3.
Qed.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
intros. unfold override.
destruct (beq_nat k1 k3) eqn:Hk1k3.
destruct (beq_nat k2 k3) eqn:Hk2k3.
apply beq_nat_true in Hk1k3.
apply beq_nat_true in Hk2k3.
rewrite Hk1k3, Hk2k3 in H. rewrite <- beq_nat_refl in H. inversion H.
reflexivity.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
intros X p x l. induction l.
intros lf H. inversion H.
intros lf H. simpl in H. destruct (p x0) eqn:Hpx0.
inversion H. rewrite <- H1. apply Hpx0.
apply IHl with lf. apply H.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove that [existsb'] and [existsb] have the same behavior.
*)
Fixpoint forallb {X} (p : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| h :: t => andb (p h) (forallb p t)
end.
Fixpoint existsb {X} (p : X -> bool) (l : list X) : bool :=
match l with
| [] => false
| h :: t => orb (p h) (existsb p t)
end.
Definition existsb' {X} (p : X -> bool) l : bool :=
negb (forallb (fun x => negb (p x)) l).
Theorem existsb'_correct : forall X (p : X -> bool) l,
existsb' p l = existsb p l.
Proof.
intros. induction l.
reflexivity.
simpl. rewrite <- IHl. unfold existsb', forallb.
destruct (p x). reflexivity. reflexivity.
Qed.
(** [] *)
(* $Date: 2014-02-04 07:15:43 -0500 (Tue, 04 Feb 2014) $ *) |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:37:11 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_intc_0_0_sim_netlist.v
// Design : design_1_axi_intc_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(p_15_in,
p_17_in,
\mer_int_reg[1] ,
D,
ip2bus_wrack_prev2,
ip2bus_rdack_prev2,
Or128_vec2stdlogic19_out,
\mer_int_reg[1]_0 ,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
\mer_int_reg[0] ,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
ip2bus_wrack_int_d1_reg,
Q,
s_axi_aclk,
is_write_reg,
ip2bus_wrack,
s_axi_aresetn,
ip2bus_rdack,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
\bus2ip_addr_i_reg[8] ,
\IVR_GEN.ivr_reg[0] ,
\REG_GEN[0].ier_reg[0] ,
\bus2ip_addr_i_reg[5] ,
\IVR_GEN.ivr_reg[0]_0 ,
ip2bus_wrack_int_d1,
ip2bus_rdack_int_d1,
s_axi_wdata,
p_0_in_0,
sie,
cie,
mer,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ,
bus2ip_rnw_i_reg);
output p_15_in;
output p_17_in;
output \mer_int_reg[1] ;
output [2:0]D;
output ip2bus_wrack_prev2;
output ip2bus_rdack_prev2;
output Or128_vec2stdlogic19_out;
output \mer_int_reg[1]_0 ;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
output \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
output \mer_int_reg[0] ;
output \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
output ip2bus_wrack_int_d1_reg;
input Q;
input s_axi_aclk;
input is_write_reg;
input ip2bus_wrack;
input s_axi_aresetn;
input ip2bus_rdack;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input [6:0]\bus2ip_addr_i_reg[8] ;
input \IVR_GEN.ivr_reg[0] ;
input \REG_GEN[0].ier_reg[0] ;
input \bus2ip_addr_i_reg[5] ;
input \IVR_GEN.ivr_reg[0]_0 ;
input ip2bus_wrack_int_d1;
input ip2bus_rdack_int_d1;
input [1:0]s_axi_wdata;
input p_0_in_0;
input sie;
input cie;
input mer;
input \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
input bus2ip_rnw_i_reg;
wire Bus_RNW_reg_i_1_n_0;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
wire [2:0]D;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1_n_0 ;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \IVR_GEN.ivr_reg[0] ;
wire \IVR_GEN.ivr_reg[0]_0 ;
wire Or128_vec2stdlogic19_out;
wire Q;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire \REG_GEN[0].ier_reg[0] ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
wire \bus2ip_addr_i_reg[5] ;
wire [6:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire cie;
wire cs_ce_clr;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_int_d1_i_2_n_0;
wire ip2bus_wrack_int_d1_i_3_n_0;
wire ip2bus_wrack_int_d1_reg;
wire ip2bus_wrack_prev2;
wire is_read;
wire is_write_reg;
wire mer;
wire \mer_int_reg[0] ;
wire \mer_int_reg[1] ;
wire \mer_int_reg[1]_0 ;
wire p_0_in_0;
wire p_10_in;
wire p_11_in;
wire p_12_in;
wire p_12_out;
wire p_13_in;
wire p_13_out;
wire p_14_in;
wire p_15_in;
wire p_15_out;
wire p_16_in;
wire p_17_in;
wire p_2_in;
wire p_2_out;
wire p_3_in;
wire p_3_out;
wire p_4_in;
wire p_4_out;
wire p_5_in;
wire p_5_out;
wire p_6_in;
wire p_6_out;
wire p_7_in;
wire p_7_out;
wire p_8_in;
wire p_9_in;
wire pselect_hit_i_0;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata_i[0]_i_2_n_0 ;
wire \s_axi_rdata_i[31]_i_3_n_0 ;
wire \s_axi_rdata_i[31]_i_4_n_0 ;
wire [1:0]s_axi_wdata;
wire sie;
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(Q),
.I2(\mer_int_reg[1] ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\mer_int_reg[1] ),
.R(1'b0));
LUT5 #(
.INIT(32'h02000000))
\CIE_GEN.CIE_BIT_GEN[0].cie[0]_i_1
(.I0(s_axi_aresetn),
.I1(cie),
.I2(\mer_int_reg[1] ),
.I3(p_12_in),
.I4(s_axi_wdata[0]),
.O(\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00000010))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0 ),
.Q(p_17_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00200000))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_5_out));
FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
(.C(s_axi_aclk),
.CE(Q),
.D(p_5_out),
.Q(p_7_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h20000000))
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.O(p_4_out));
FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]
(.C(s_axi_aclk),
.CE(Q),
.D(p_4_out),
.Q(p_6_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00400000))
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_3_out));
FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]
(.C(s_axi_aclk),
.CE(Q),
.D(p_3_out),
.Q(p_5_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h40000000))
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.O(p_2_out));
FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]
(.C(s_axi_aclk),
.CE(Q),
.D(p_2_out),
.Q(p_4_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00800000))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1_n_0 ),
.Q(p_3_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h80000000))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.O(p_15_out));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0002))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2
(.I0(Q),
.I1(\bus2ip_addr_i_reg[8] [5]),
.I2(\bus2ip_addr_i_reg[8] [4]),
.I3(\bus2ip_addr_i_reg[8] [6]),
.O(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]
(.C(s_axi_aclk),
.CE(Q),
.D(p_15_out),
.Q(p_2_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFFCFFFFFFFCFFFEF))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1
(.I0(is_write_reg),
.I1(ip2bus_wrack),
.I2(s_axi_aresetn),
.I3(ip2bus_rdack),
.I4(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ),
.I5(is_read),
.O(cs_ce_clr));
LUT3 #(
.INIT(8'h08))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_2
(.I0(Q),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [5]),
.O(pselect_hit_i_0));
LUT4 #(
.INIT(16'hFFFD))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.O(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]
(.C(s_axi_aclk),
.CE(Q),
.D(pselect_hit_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00000040))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0 ),
.Q(p_16_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00001000))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(p_13_out));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(p_13_out),
.Q(p_15_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00004000))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(p_12_out));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi_aclk),
.CE(Q),
.D(p_12_out),
.Q(p_14_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00100000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
.Q(p_13_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00400000))
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0 ),
.Q(p_12_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h10000000))
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1_n_0 ),
.Q(p_11_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h40000000))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [2]),
.O(\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(Q),
.D(\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1_n_0 ),
.Q(p_10_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00100000))
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(p_7_out));
FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
(.C(s_axi_aclk),
.CE(Q),
.D(p_7_out),
.Q(p_9_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h02000000))
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.O(p_6_out));
FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]
(.C(s_axi_aclk),
.CE(Q),
.D(p_6_out),
.Q(p_8_in),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h00004000))
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar[0]_i_1
(.I0(\mer_int_reg[1] ),
.I1(s_axi_wdata[0]),
.I2(p_14_in),
.I3(s_axi_aresetn),
.I4(\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
.O(\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ));
LUT5 #(
.INIT(32'h00004000))
\SIE_GEN.SIE_BIT_GEN[0].sie[0]_i_1
(.I0(\mer_int_reg[1] ),
.I1(p_13_in),
.I2(s_axi_wdata[0]),
.I3(s_axi_aresetn),
.I4(sie),
.O(\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ));
LUT6 #(
.INIT(64'h00000000FFFB0000))
ip2bus_rdack_i_1
(.I0(\s_axi_rdata_i[31]_i_4_n_0 ),
.I1(\s_axi_rdata_i[0]_i_2_n_0 ),
.I2(ip2bus_wrack_int_d1_i_3_n_0),
.I3(ip2bus_wrack_int_d1_i_2_n_0),
.I4(\mer_int_reg[1] ),
.I5(ip2bus_rdack_int_d1),
.O(ip2bus_rdack_prev2));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hAAAAA8AA))
ip2bus_rdack_int_d1_i_1
(.I0(\mer_int_reg[1] ),
.I1(ip2bus_wrack_int_d1_i_2_n_0),
.I2(ip2bus_wrack_int_d1_i_3_n_0),
.I3(\s_axi_rdata_i[0]_i_2_n_0 ),
.I4(\s_axi_rdata_i[31]_i_4_n_0 ),
.O(Or128_vec2stdlogic19_out));
LUT6 #(
.INIT(64'h000000000000FFFB))
ip2bus_wrack_i_1
(.I0(\s_axi_rdata_i[31]_i_4_n_0 ),
.I1(\s_axi_rdata_i[0]_i_2_n_0 ),
.I2(ip2bus_wrack_int_d1_i_3_n_0),
.I3(ip2bus_wrack_int_d1_i_2_n_0),
.I4(\mer_int_reg[1] ),
.I5(ip2bus_wrack_int_d1),
.O(ip2bus_wrack_prev2));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h55555455))
ip2bus_wrack_int_d1_i_1
(.I0(\mer_int_reg[1] ),
.I1(ip2bus_wrack_int_d1_i_2_n_0),
.I2(ip2bus_wrack_int_d1_i_3_n_0),
.I3(\s_axi_rdata_i[0]_i_2_n_0 ),
.I4(\s_axi_rdata_i[31]_i_4_n_0 ),
.O(ip2bus_wrack_int_d1_reg));
LUT4 #(
.INIT(16'hFFFE))
ip2bus_wrack_int_d1_i_2
(.I0(p_4_in),
.I1(p_3_in),
.I2(p_6_in),
.I3(p_2_in),
.O(ip2bus_wrack_int_d1_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
ip2bus_wrack_int_d1_i_3
(.I0(p_12_in),
.I1(p_14_in),
.I2(p_13_in),
.I3(p_7_in),
.I4(\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16] ),
.I5(p_5_in),
.O(ip2bus_wrack_int_d1_i_3_n_0));
LUT4 #(
.INIT(16'hFB08))
\mer_int[0]_i_1
(.I0(s_axi_wdata[0]),
.I1(p_10_in),
.I2(\mer_int_reg[1] ),
.I3(mer),
.O(\mer_int_reg[0] ));
LUT4 #(
.INIT(16'hFF20))
\mer_int[1]_i_1
(.I0(s_axi_wdata[1]),
.I1(\mer_int_reg[1] ),
.I2(p_10_in),
.I3(p_0_in_0),
.O(\mer_int_reg[1]_0 ));
LUT6 #(
.INIT(64'h0051515151515151))
\s_axi_rdata_i[0]_i_1
(.I0(\s_axi_rdata_i[31]_i_3_n_0 ),
.I1(\s_axi_rdata_i[0]_i_2_n_0 ),
.I2(\s_axi_rdata_i[31]_i_4_n_0 ),
.I3(\IVR_GEN.ivr_reg[0] ),
.I4(\REG_GEN[0].ier_reg[0] ),
.I5(\bus2ip_addr_i_reg[5] ),
.O(D[0]));
LUT3 #(
.INIT(8'h01))
\s_axi_rdata_i[0]_i_2
(.I0(p_8_in),
.I1(p_11_in),
.I2(p_9_in),
.O(\s_axi_rdata_i[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000055555554))
\s_axi_rdata_i[1]_i_1
(.I0(\s_axi_rdata_i[31]_i_3_n_0 ),
.I1(p_9_in),
.I2(p_11_in),
.I3(p_8_in),
.I4(\s_axi_rdata_i[31]_i_4_n_0 ),
.I5(\IVR_GEN.ivr_reg[0]_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'h0000000055555554))
\s_axi_rdata_i[31]_i_2
(.I0(\s_axi_rdata_i[31]_i_3_n_0 ),
.I1(p_9_in),
.I2(p_11_in),
.I3(p_8_in),
.I4(\s_axi_rdata_i[31]_i_4_n_0 ),
.I5(\IVR_GEN.ivr_reg[0] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hFEFF))
\s_axi_rdata_i[31]_i_3
(.I0(\bus2ip_addr_i_reg[8] [5]),
.I1(\bus2ip_addr_i_reg[8] [4]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\mer_int_reg[1] ),
.O(\s_axi_rdata_i[31]_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\s_axi_rdata_i[31]_i_4
(.I0(p_15_in),
.I1(p_17_in),
.I2(p_16_in),
.I3(p_10_in),
.O(\s_axi_rdata_i[31]_i_4_n_0 ));
endmodule
(* C_ASYNC_INTR = "-2" *) (* C_CASCADE_MASTER = "0" *) (* C_DISABLE_SYNCHRONIZERS = "0" *)
(* C_ENABLE_ASYNC = "0" *) (* C_EN_CASCADE_MODE = "0" *) (* C_FAMILY = "zynq" *)
(* C_HAS_CIE = "1" *) (* C_HAS_FAST = "0" *) (* C_HAS_ILR = "0" *)
(* C_HAS_IPR = "1" *) (* C_HAS_IVR = "1" *) (* C_HAS_SIE = "1" *)
(* C_INSTANCE = "design_1_axi_intc_0_0" *) (* C_IRQ_ACTIVE = "1'b1" *) (* C_IRQ_IS_LEVEL = "1" *)
(* C_IVAR_RESET_VALUE = "16" *) (* C_KIND_OF_EDGE = "-1" *) (* C_KIND_OF_INTR = "-2" *)
(* C_KIND_OF_LVL = "-1" *) (* C_MB_CLK_NOT_CONNECTED = "1" *) (* C_NUM_INTR_INPUTS = "1" *)
(* C_NUM_SW_INTR = "0" *) (* C_NUM_SYNC_FF = "2" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* hdl = "VHDL" *) (* imp_netlist = "TRUE" *)
(* ip_group = "LOGICORE" *) (* iptype = "PERIPHERAL" *) (* run_ngcbuild = "TRUE" *)
(* style = "HDL" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_intc
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
intr,
processor_clk,
processor_rst,
irq,
processor_ack,
interrupt_address,
irq_in,
interrupt_address_in,
processor_ack_out);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rstn" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* BUFFER_TYPE = "none" *) input [0:0]intr;
input processor_clk;
input processor_rst;
output irq;
input [1:0]processor_ack;
output [31:0]interrupt_address;
input irq_in;
input [31:0]interrupt_address_in;
output [1:0]processor_ack_out;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire AXI_LITE_IPIF_I_n_15;
wire AXI_LITE_IPIF_I_n_16;
wire AXI_LITE_IPIF_I_n_17;
wire INTC_CORE_I_n_4;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ;
wire Or128_vec2stdlogic19_out;
wire cie;
wire ier;
wire [0:0]intr;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_prev2;
wire [0:0]ipr;
wire irq;
wire isr;
wire ivr;
wire mer;
wire p_0_in;
wire p_0_in_0;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rstn" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:1]\^s_axi_bresp ;
wire s_axi_bvalid;
wire [30:0]\^s_axi_rdata ;
wire s_axi_rready;
wire [1:1]\^s_axi_rresp ;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sie;
assign interrupt_address[31] = \<const0> ;
assign interrupt_address[30] = \<const0> ;
assign interrupt_address[29] = \<const0> ;
assign interrupt_address[28] = \<const0> ;
assign interrupt_address[27] = \<const0> ;
assign interrupt_address[26] = \<const0> ;
assign interrupt_address[25] = \<const0> ;
assign interrupt_address[24] = \<const0> ;
assign interrupt_address[23] = \<const0> ;
assign interrupt_address[22] = \<const0> ;
assign interrupt_address[21] = \<const0> ;
assign interrupt_address[20] = \<const0> ;
assign interrupt_address[19] = \<const0> ;
assign interrupt_address[18] = \<const0> ;
assign interrupt_address[17] = \<const0> ;
assign interrupt_address[16] = \<const0> ;
assign interrupt_address[15] = \<const0> ;
assign interrupt_address[14] = \<const0> ;
assign interrupt_address[13] = \<const0> ;
assign interrupt_address[12] = \<const0> ;
assign interrupt_address[11] = \<const0> ;
assign interrupt_address[10] = \<const0> ;
assign interrupt_address[9] = \<const0> ;
assign interrupt_address[8] = \<const0> ;
assign interrupt_address[7] = \<const0> ;
assign interrupt_address[6] = \<const0> ;
assign interrupt_address[5] = \<const0> ;
assign interrupt_address[4] = \<const0> ;
assign interrupt_address[3] = \<const0> ;
assign interrupt_address[2] = \<const0> ;
assign interrupt_address[1] = \<const0> ;
assign interrupt_address[0] = \<const0> ;
assign processor_ack_out[1] = \<const0> ;
assign processor_ack_out[0] = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \^s_axi_bresp [1];
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [30];
assign s_axi_rdata[30] = \^s_axi_rdata [30];
assign s_axi_rdata[29] = \^s_axi_rdata [30];
assign s_axi_rdata[28] = \^s_axi_rdata [30];
assign s_axi_rdata[27] = \^s_axi_rdata [30];
assign s_axi_rdata[26] = \^s_axi_rdata [30];
assign s_axi_rdata[25] = \^s_axi_rdata [30];
assign s_axi_rdata[24] = \^s_axi_rdata [30];
assign s_axi_rdata[23] = \^s_axi_rdata [30];
assign s_axi_rdata[22] = \^s_axi_rdata [30];
assign s_axi_rdata[21] = \^s_axi_rdata [30];
assign s_axi_rdata[20] = \^s_axi_rdata [30];
assign s_axi_rdata[19] = \^s_axi_rdata [30];
assign s_axi_rdata[18] = \^s_axi_rdata [30];
assign s_axi_rdata[17] = \^s_axi_rdata [30];
assign s_axi_rdata[16] = \^s_axi_rdata [30];
assign s_axi_rdata[15] = \^s_axi_rdata [30];
assign s_axi_rdata[14] = \^s_axi_rdata [30];
assign s_axi_rdata[13] = \^s_axi_rdata [30];
assign s_axi_rdata[12] = \^s_axi_rdata [30];
assign s_axi_rdata[11] = \^s_axi_rdata [30];
assign s_axi_rdata[10] = \^s_axi_rdata [30];
assign s_axi_rdata[9] = \^s_axi_rdata [30];
assign s_axi_rdata[8] = \^s_axi_rdata [30];
assign s_axi_rdata[7] = \^s_axi_rdata [30];
assign s_axi_rdata[6] = \^s_axi_rdata [30];
assign s_axi_rdata[5] = \^s_axi_rdata [30];
assign s_axi_rdata[4] = \^s_axi_rdata [30];
assign s_axi_rdata[3] = \^s_axi_rdata [30];
assign s_axi_rdata[2] = \^s_axi_rdata [30];
assign s_axi_rdata[1:0] = \^s_axi_rdata [1:0];
assign s_axi_rresp[1] = \^s_axi_rresp [1];
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (AXI_LITE_IPIF_I_n_14),
.Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (AXI_LITE_IPIF_I_n_16),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (INTC_CORE_I_n_4),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (AXI_LITE_IPIF_I_n_13),
.cie(cie),
.ier(ier),
.ip2bus_rdack(ip2bus_rdack),
.ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
.ip2bus_rdack_prev2(ip2bus_rdack_prev2),
.ip2bus_wrack(ip2bus_wrack),
.ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
.ip2bus_wrack_int_d1_reg(AXI_LITE_IPIF_I_n_17),
.ip2bus_wrack_prev2(ip2bus_wrack_prev2),
.ipr(ipr),
.isr(isr),
.ivr(ivr),
.mer(mer),
.\mer_int_reg[0] (AXI_LITE_IPIF_I_n_15),
.\mer_int_reg[1] (AXI_LITE_IPIF_I_n_12),
.p_0_in(p_0_in),
.p_0_in_0(p_0_in_0),
.p_15_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ),
.p_17_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[8:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[8:2]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(\^s_axi_bresp ),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [30],\^s_axi_rdata [1:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(\^s_axi_rresp ),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata[1:0]),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.sie(sie));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_intc_core INTC_CORE_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.Bus_RNW_reg_reg(AXI_LITE_IPIF_I_n_16),
.Bus_RNW_reg_reg_0(AXI_LITE_IPIF_I_n_12),
.Bus_RNW_reg_reg_1(AXI_LITE_IPIF_I_n_13),
.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 (AXI_LITE_IPIF_I_n_14),
.\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] (AXI_LITE_IPIF_I_n_15),
.\REG_GEN[0].isr_reg[0]_0 (INTC_CORE_I_n_4),
.cie(cie),
.ier(ier),
.intr(intr),
.ipr(ipr),
.irq(irq),
.isr(isr),
.ivr(ivr),
.mer(mer),
.p_0_in(p_0_in),
.p_0_in_0(p_0_in_0),
.p_15_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_15_in ),
.p_17_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_17_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata[0]),
.sie(sie));
FDRE ip2bus_rdack_int_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Or128_vec2stdlogic19_out),
.Q(ip2bus_rdack_int_d1),
.R(p_0_in));
FDRE ip2bus_rdack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_prev2),
.Q(ip2bus_rdack),
.R(p_0_in));
FDRE ip2bus_wrack_int_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_17),
.Q(ip2bus_wrack_int_d1),
.R(p_0_in));
FDRE ip2bus_wrack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_wrack_prev2),
.Q(ip2bus_wrack),
.R(p_0_in));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(p_15_in,
p_17_in,
s_axi_rresp,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
s_axi_wready,
s_axi_arready,
ip2bus_wrack_prev2,
ip2bus_rdack_prev2,
Or128_vec2stdlogic19_out,
\mer_int_reg[1] ,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
\mer_int_reg[0] ,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
ip2bus_wrack_int_d1_reg,
s_axi_rdata,
p_0_in,
s_axi_aclk,
s_axi_arvalid,
ip2bus_wrack,
s_axi_aresetn,
ip2bus_rdack,
s_axi_rready,
s_axi_bready,
s_axi_wvalid,
s_axi_awvalid,
s_axi_araddr,
s_axi_awaddr,
ier,
ipr,
ivr,
p_0_in_0,
mer,
isr,
ip2bus_wrack_int_d1,
ip2bus_rdack_int_d1,
s_axi_wstrb,
s_axi_wdata,
sie,
cie,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 );
output p_15_in;
output p_17_in;
output [0:0]s_axi_rresp;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output s_axi_wready;
output s_axi_arready;
output ip2bus_wrack_prev2;
output ip2bus_rdack_prev2;
output Or128_vec2stdlogic19_out;
output \mer_int_reg[1] ;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
output \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
output \mer_int_reg[0] ;
output \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
output ip2bus_wrack_int_d1_reg;
output [2:0]s_axi_rdata;
input p_0_in;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_wrack;
input s_axi_aresetn;
input ip2bus_rdack;
input s_axi_rready;
input s_axi_bready;
input s_axi_wvalid;
input s_axi_awvalid;
input [6:0]s_axi_araddr;
input [6:0]s_axi_awaddr;
input ier;
input [0:0]ipr;
input ivr;
input p_0_in_0;
input mer;
input isr;
input ip2bus_wrack_int_d1;
input ip2bus_rdack_int_d1;
input [3:0]s_axi_wstrb;
input [1:0]s_axi_wdata;
input sie;
input cie;
input \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire Bus_RNW_reg;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
wire Or128_vec2stdlogic19_out;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
wire cie;
wire ier;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_int_d1_reg;
wire ip2bus_wrack_prev2;
wire [0:0]ipr;
wire isr;
wire ivr;
wire mer;
wire \mer_int_reg[0] ;
wire \mer_int_reg[1] ;
wire p_0_in;
wire p_0_in_0;
wire p_15_in;
wire p_17_in;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire s_axi_bvalid;
wire [2:0]s_axi_rdata;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire [1:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sie;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
.Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.cie(cie),
.ier(ier),
.ip2bus_rdack(ip2bus_rdack),
.ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
.ip2bus_rdack_prev2(ip2bus_rdack_prev2),
.ip2bus_wrack(ip2bus_wrack),
.ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
.ip2bus_wrack_int_d1_reg(ip2bus_wrack_int_d1_reg),
.ip2bus_wrack_prev2(ip2bus_wrack_prev2),
.ipr(ipr),
.isr(isr),
.ivr(ivr),
.mer(mer),
.\mer_int_reg[0] (\mer_int_reg[0] ),
.\mer_int_reg[1] (Bus_RNW_reg),
.\mer_int_reg[1]_0 (\mer_int_reg[1] ),
.p_0_in(p_0_in),
.p_0_in_0(p_0_in_0),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.sie(sie));
endmodule
(* CHECK_LICENSE_TYPE = "design_1_axi_intc_0_0,axi_intc,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_intc,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
intr,
irq);
(* x_interface_info = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 s_resetn RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT" *) input [0:0]intr;
(* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT" *) output irq;
wire [0:0]intr;
wire irq;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [31:0]NLW_U0_interrupt_address_UNCONNECTED;
wire [1:0]NLW_U0_processor_ack_out_UNCONNECTED;
(* C_ASYNC_INTR = "-2" *)
(* C_CASCADE_MASTER = "0" *)
(* C_DISABLE_SYNCHRONIZERS = "0" *)
(* C_ENABLE_ASYNC = "0" *)
(* C_EN_CASCADE_MODE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_CIE = "1" *)
(* C_HAS_FAST = "0" *)
(* C_HAS_ILR = "0" *)
(* C_HAS_IPR = "1" *)
(* C_HAS_IVR = "1" *)
(* C_HAS_SIE = "1" *)
(* C_INSTANCE = "design_1_axi_intc_0_0" *)
(* C_IRQ_ACTIVE = "1'b1" *)
(* C_IRQ_IS_LEVEL = "1" *)
(* C_IVAR_RESET_VALUE = "16" *)
(* C_KIND_OF_EDGE = "-1" *)
(* C_KIND_OF_INTR = "-2" *)
(* C_KIND_OF_LVL = "-1" *)
(* C_MB_CLK_NOT_CONNECTED = "1" *)
(* C_NUM_INTR_INPUTS = "1" *)
(* C_NUM_SW_INTR = "0" *)
(* C_NUM_SYNC_FF = "2" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* hdl = "VHDL" *)
(* imp_netlist = "TRUE" *)
(* ip_group = "LOGICORE" *)
(* iptype = "PERIPHERAL" *)
(* run_ngcbuild = "TRUE" *)
(* style = "HDL" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_intc U0
(.interrupt_address(NLW_U0_interrupt_address_UNCONNECTED[31:0]),
.interrupt_address_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.intr(intr),
.irq(irq),
.irq_in(1'b0),
.processor_ack({1'b0,1'b0}),
.processor_ack_out(NLW_U0_processor_ack_out_UNCONNECTED[1:0]),
.processor_clk(1'b0),
.processor_rst(1'b0),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_intc_core
(ier,
ipr,
p_0_in,
ivr,
\REG_GEN[0].isr_reg[0]_0 ,
p_0_in_0,
isr,
sie,
cie,
mer,
irq,
s_axi_aclk,
Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ,
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ,
s_axi_aresetn,
s_axi_wdata,
p_15_in,
Bus_RNW_reg,
p_17_in,
intr);
output ier;
output [0:0]ipr;
output p_0_in;
output ivr;
output \REG_GEN[0].isr_reg[0]_0 ;
output p_0_in_0;
output isr;
output sie;
output cie;
output mer;
output irq;
input s_axi_aclk;
input Bus_RNW_reg_reg;
input Bus_RNW_reg_reg_0;
input Bus_RNW_reg_reg_1;
input \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
input \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
input s_axi_aresetn;
input [0:0]s_axi_wdata;
input p_15_in;
input Bus_RNW_reg;
input p_17_in;
input [0:0]intr;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ;
wire \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ;
wire \IPR_GEN.ipr[0]_i_1_n_0 ;
wire \IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_i_1_n_0 ;
wire \REG_GEN[0].ier[0]_i_2_n_0 ;
wire \REG_GEN[0].isr[0]_i_1_n_0 ;
wire \REG_GEN[0].isr[0]_i_2_n_0 ;
wire \REG_GEN[0].isr_reg[0]_0 ;
wire cie;
wire hw_intr;
wire ier;
wire [0:0]intr;
wire [0:0]ipr;
wire irq;
wire isr;
wire ivr;
wire mer;
wire p_0_in;
wire p_0_in_0;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire p_8_out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [0:0]s_axi_wdata;
wire sie;
FDRE \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0 ),
.Q(cie),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h00E0))
\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1
(.I0(hw_intr),
.I1(intr),
.I2(s_axi_aresetn),
.I3(\REG_GEN[0].isr_reg[0]_0 ),
.O(\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ));
FDRE \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0 ),
.Q(hw_intr),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
\IPR_GEN.ipr[0]_i_1
(.I0(ier),
.I1(isr),
.O(\IPR_GEN.ipr[0]_i_1_n_0 ));
FDRE \IPR_GEN.ipr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IPR_GEN.ipr[0]_i_1_n_0 ),
.Q(ipr),
.R(p_0_in));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hE000))
\IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_i_1
(.I0(irq),
.I1(mer),
.I2(ipr),
.I3(s_axi_aresetn),
.O(\IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_i_1_n_0 ));
FDRE \IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\IRQ_LEVEL_GEN.IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN.Irq_i_1_n_0 ),
.Q(irq),
.R(1'b0));
LUT2 #(
.INIT(4'h7))
\IVR_GEN.ivr[0]_i_1
(.I0(isr),
.I1(ier),
.O(p_1_in));
FDSE \IVR_GEN.ivr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(ivr),
.S(p_0_in));
FDRE \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg),
.Q(\REG_GEN[0].isr_reg[0]_0 ),
.R(1'b0));
LUT6 #(
.INIT(64'hAAAAAAAAAA8A0080))
\REG_GEN[0].ier[0]_i_1
(.I0(\REG_GEN[0].ier[0]_i_2_n_0 ),
.I1(s_axi_wdata),
.I2(p_15_in),
.I3(Bus_RNW_reg),
.I4(ier),
.I5(sie),
.O(p_8_out));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h2))
\REG_GEN[0].ier[0]_i_2
(.I0(s_axi_aresetn),
.I1(cie),
.O(\REG_GEN[0].ier[0]_i_2_n_0 ));
FDRE \REG_GEN[0].ier_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_8_out),
.Q(ier),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h08))
\REG_GEN[0].isr[0]_i_1
(.I0(\REG_GEN[0].isr[0]_i_2_n_0 ),
.I1(s_axi_aresetn),
.I2(\REG_GEN[0].isr_reg[0]_0 ),
.O(\REG_GEN[0].isr[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFACAFAFA0ACA0A0))
\REG_GEN[0].isr[0]_i_2
(.I0(hw_intr),
.I1(s_axi_wdata),
.I2(p_0_in_0),
.I3(Bus_RNW_reg),
.I4(p_17_in),
.I5(isr),
.O(\REG_GEN[0].isr[0]_i_2_n_0 ));
FDRE \REG_GEN[0].isr_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\REG_GEN[0].isr[0]_i_1_n_0 ),
.Q(isr),
.R(1'b0));
FDRE \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_1),
.Q(sie),
.R(1'b0));
FDRE \mer_int_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7] ),
.Q(mer),
.R(p_0_in));
FDRE \mer_int_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_reg_0),
.Q(p_0_in_0),
.R(p_0_in));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_0_in));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(p_15_in,
p_17_in,
s_axi_rresp,
\mer_int_reg[1] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
s_axi_wready,
s_axi_arready,
ip2bus_wrack_prev2,
ip2bus_rdack_prev2,
Or128_vec2stdlogic19_out,
\mer_int_reg[1]_0 ,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ,
\mer_int_reg[0] ,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ,
ip2bus_wrack_int_d1_reg,
s_axi_rdata,
p_0_in,
s_axi_aclk,
s_axi_arvalid,
ip2bus_wrack,
s_axi_aresetn,
ip2bus_rdack,
s_axi_rready,
s_axi_bready,
s_axi_wvalid,
s_axi_awvalid,
s_axi_araddr,
s_axi_awaddr,
ier,
ipr,
ivr,
p_0_in_0,
mer,
isr,
ip2bus_wrack_int_d1,
ip2bus_rdack_int_d1,
s_axi_wstrb,
s_axi_wdata,
sie,
cie,
\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 );
output p_15_in;
output p_17_in;
output [0:0]s_axi_rresp;
output \mer_int_reg[1] ;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output s_axi_wready;
output s_axi_arready;
output ip2bus_wrack_prev2;
output ip2bus_rdack_prev2;
output Or128_vec2stdlogic19_out;
output \mer_int_reg[1]_0 ;
output \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
output \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
output \mer_int_reg[0] ;
output \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
output ip2bus_wrack_int_d1_reg;
output [2:0]s_axi_rdata;
input p_0_in;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_wrack;
input s_axi_aresetn;
input ip2bus_rdack;
input s_axi_rready;
input s_axi_bready;
input s_axi_wvalid;
input s_axi_awvalid;
input [6:0]s_axi_araddr;
input [6:0]s_axi_awaddr;
input ier;
input [0:0]ipr;
input ivr;
input p_0_in_0;
input mer;
input isr;
input ip2bus_wrack_int_d1;
input ip2bus_rdack_int_d1;
input [3:0]s_axi_wstrb;
input [1:0]s_axi_wdata;
input sie;
input cie;
input \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire [31:0]IP2Bus_Data;
wire Or128_vec2stdlogic19_out;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ;
wire \REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ;
wire \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ;
wire [8:2]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[4]_i_1_n_0 ;
wire \bus2ip_addr_i[5]_i_1_n_0 ;
wire \bus2ip_addr_i[6]_i_1_n_0 ;
wire \bus2ip_addr_i[7]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire bus2ip_rnw_i06_out;
wire bus2ip_rnw_i_reg_n_0;
wire cie;
wire ier;
wire ip2bus_error;
wire ip2bus_rdack;
wire ip2bus_rdack_int_d1;
wire ip2bus_rdack_prev2;
wire ip2bus_wrack;
wire ip2bus_wrack_int_d1;
wire ip2bus_wrack_int_d1_reg;
wire ip2bus_wrack_prev2;
wire [0:0]ipr;
wire is_read;
wire is_read_i_1_n_0;
wire is_read_i_2_n_0;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire isr;
wire ivr;
wire mer;
wire \mer_int_reg[0] ;
wire \mer_int_reg[1] ;
wire \mer_int_reg[1]_0 ;
wire p_0_in;
wire p_0_in_0;
wire p_15_in;
wire p_17_in;
wire [3:0]plusOp;
wire rst;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire \s_axi_bresp_i[1]_i_1_n_0 ;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [2:0]s_axi_rdata;
wire s_axi_rdata_i;
wire \s_axi_rdata_i[0]_i_3_n_0 ;
wire \s_axi_rdata_i[0]_i_4_n_0 ;
wire \s_axi_rdata_i[1]_i_2_n_0 ;
wire \s_axi_rdata_i[31]_i_5_n_0 ;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [1:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sie;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[0]_i_1_n_0 ;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h6AAA))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] (\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0] ),
.D({IP2Bus_Data[31],IP2Bus_Data[1:0]}),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\IVR_GEN.ivr_reg[0] (\s_axi_rdata_i[31]_i_5_n_0 ),
.\IVR_GEN.ivr_reg[0]_0 (\s_axi_rdata_i[1]_i_2_n_0 ),
.Or128_vec2stdlogic19_out(Or128_vec2stdlogic19_out),
.Q(start2),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] (\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0] ),
.\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 (\REG_GEN[0].IAR_NORMAL_MODE_GEN.iar_reg[0]_0 ),
.\REG_GEN[0].ier_reg[0] (\s_axi_rdata_i[0]_i_3_n_0 ),
.\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] (\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0] ),
.\bus2ip_addr_i_reg[5] (\s_axi_rdata_i[0]_i_4_n_0 ),
.\bus2ip_addr_i_reg[8] (bus2ip_addr),
.bus2ip_rnw_i_reg(bus2ip_rnw_i_reg_n_0),
.cie(cie),
.ip2bus_rdack(ip2bus_rdack),
.ip2bus_rdack_int_d1(ip2bus_rdack_int_d1),
.ip2bus_rdack_prev2(ip2bus_rdack_prev2),
.ip2bus_wrack(ip2bus_wrack),
.ip2bus_wrack_int_d1(ip2bus_wrack_int_d1),
.ip2bus_wrack_int_d1_reg(ip2bus_wrack_int_d1_reg),
.ip2bus_wrack_prev2(ip2bus_wrack_prev2),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.mer(mer),
.\mer_int_reg[0] (\mer_int_reg[0] ),
.\mer_int_reg[1] (\mer_int_reg[1] ),
.\mer_int_reg[1]_0 (\mer_int_reg[1]_0 ),
.p_0_in_0(p_0_in_0),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata),
.sie(sie));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[0]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[1]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_araddr[2]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[2]),
.O(\bus2ip_addr_i[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[5]_i_1
(.I0(s_axi_araddr[3]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[3]),
.O(\bus2ip_addr_i[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[6]_i_1
(.I0(s_axi_araddr[4]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[4]),
.O(\bus2ip_addr_i[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[7]_i_1
(.I0(s_axi_araddr[5]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[5]),
.O(\bus2ip_addr_i[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFEF0020))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[6]),
.I1(state[1]),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(s_axi_awaddr[6]),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[2]),
.R(rst));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[3]),
.R(rst));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[4]_i_1_n_0 ),
.Q(bus2ip_addr[4]),
.R(rst));
FDRE \bus2ip_addr_i_reg[5]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[5]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(rst));
FDRE \bus2ip_addr_i_reg[6]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[6]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(rst));
FDRE \bus2ip_addr_i_reg[7]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[7]_i_1_n_0 ),
.Q(bus2ip_addr[7]),
.R(rst));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[8]),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h04))
bus2ip_rnw_i_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(state[0]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(bus2ip_rnw_i_reg_n_0),
.R(rst));
LUT4 #(
.INIT(16'h2F20))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state[1]),
.I2(is_read_i_2_n_0),
.I3(is_read),
.O(is_read_i_1_n_0));
LUT6 #(
.INIT(64'hAA80808055555555))
is_read_i_2
(.I0(state[0]),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(state[1]),
.O(is_read_i_2_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(rst));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(s_axi_arvalid),
.I4(is_read_i_2_n_0),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(rst));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_in),
.Q(rst),
.R(1'b0));
LUT6 #(
.INIT(64'hAAAAAAAEAAAAAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I5(is_read),
.O(s_axi_arready));
LUT4 #(
.INIT(16'hFB08))
\s_axi_bresp_i[1]_i_1
(.I0(ip2bus_error),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bresp),
.O(\s_axi_bresp_i[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_bresp_i_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\s_axi_bresp_i[1]_i_1_n_0 ),
.Q(s_axi_bresp),
.R(rst));
LUT5 #(
.INIT(32'h5D550C00))
s_axi_bvalid_i_i_1
(.I0(s_axi_bready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_wready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(rst));
LUT6 #(
.INIT(64'hFFFFFFDDFFFF0FFF))
\s_axi_rdata_i[0]_i_3
(.I0(ier),
.I1(bus2ip_addr[5]),
.I2(ipr),
.I3(bus2ip_addr[2]),
.I4(bus2ip_addr[4]),
.I5(bus2ip_addr[3]),
.O(\s_axi_rdata_i[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hBFFFFEFEBFFFFFFF))
\s_axi_rdata_i[0]_i_4
(.I0(bus2ip_addr[5]),
.I1(bus2ip_addr[3]),
.I2(bus2ip_addr[4]),
.I3(mer),
.I4(bus2ip_addr[2]),
.I5(isr),
.O(\s_axi_rdata_i[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCDFDFFFFFFFF3F3F))
\s_axi_rdata_i[1]_i_2
(.I0(ivr),
.I1(bus2ip_addr[5]),
.I2(bus2ip_addr[2]),
.I3(p_0_in_0),
.I4(bus2ip_addr[3]),
.I5(bus2ip_addr[4]),
.O(\s_axi_rdata_i[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
LUT5 #(
.INIT(32'hFCFFFF7F))
\s_axi_rdata_i[31]_i_5
(.I0(ivr),
.I1(bus2ip_addr[3]),
.I2(bus2ip_addr[4]),
.I3(bus2ip_addr[2]),
.I4(bus2ip_addr[5]),
.O(\s_axi_rdata_i[31]_i_5_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[0]),
.Q(s_axi_rdata[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[1]),
.Q(s_axi_rdata[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[31]),
.Q(s_axi_rdata[2]),
.R(rst));
LUT5 #(
.INIT(32'h070F0F0F))
\s_axi_rresp_i[1]_i_1
(.I0(s_axi_wstrb[1]),
.I1(s_axi_wstrb[2]),
.I2(bus2ip_rnw_i_reg_n_0),
.I3(s_axi_wstrb[0]),
.I4(s_axi_wstrb[3]),
.O(ip2bus_error));
FDRE #(
.INIT(1'b0))
\s_axi_rresp_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(ip2bus_error),
.Q(s_axi_rresp),
.R(rst));
LUT5 #(
.INIT(32'h5D550C00))
s_axi_rvalid_i_i_1
(.I0(s_axi_rready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_arready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(rst));
LUT6 #(
.INIT(64'hAAAAAAAEAAAAAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I5(is_write_reg_n_0),
.O(s_axi_wready));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h00000F08))
start2_i_1
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(rst));
LUT5 #(
.INIT(32'hF4F4FFF0))
\state[0]_i_1
(.I0(state[0]),
.I1(s_axi_wready),
.I2(\state[0]_i_2_n_0 ),
.I3(s_axi_arvalid),
.I4(state[1]),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h557F7F7F00000000))
\state[0]_i_2
(.I0(state[1]),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(s_axi_bvalid),
.I4(s_axi_bready),
.I5(state[0]),
.O(\state[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h22CFEECF))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(state[0]),
.I4(\state[1]_i_3_n_0 ),
.O(\state[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hBF))
\state[1]_i_2
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.O(\state[1]_i_2_n_0 ));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_3
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(state[1]),
.R(rst));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module lj24tx(
input wire clk,
input wire reset_n,
output reg fifo_rdreq,
input wire fifo_empty,
input wire [31:0] fifo_data,
output wire lrck,
output wire bck,
output wire data);
reg [5:0] tx_cnt;
reg [31:0] audio_buf_a, audio_buf_b;
assign bck = ~clk & reset_n;
assign lrck = ~tx_cnt[4] & reset_n;
assign data = (tx_cnt[5] == 0)? audio_buf_a[31] : audio_buf_b[31];
always @(posedge clk, negedge reset_n)
begin
if(!reset_n)
begin
audio_buf_a <= 0;
audio_buf_b <= 0;
tx_cnt <= 0;
fifo_rdreq <= 0;
end
else if(tx_cnt[5] == 0)
begin
audio_buf_a <= {audio_buf_a[30:0], 1'b0};
tx_cnt <= tx_cnt + 1;
if(tx_cnt == 6'b010000 && fifo_empty == 0) fifo_rdreq <= 1;
else if(tx_cnt == 6'b010001 && fifo_empty == 0) fifo_rdreq <= 0;
else if(tx_cnt == 6'b010010) audio_buf_b <= fifo_data;
else audio_buf_b <= audio_buf_b;
end
else if(tx_cnt[5] == 1)
begin
audio_buf_b <= {audio_buf_b[30:0], 1'b0};
tx_cnt <= tx_cnt + 1;
if(tx_cnt == 6'b110000 && fifo_empty == 0) fifo_rdreq <= 1;
else if(tx_cnt == 6'b110001 && fifo_empty == 0) fifo_rdreq <= 0;
else if(tx_cnt == 6'b110010) audio_buf_a <= fifo_data;
else audio_buf_a <= audio_buf_a;
end
else
begin
tx_cnt <= tx_cnt + 1;
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_TB_V
`define SKY130_FD_SC_LS__SDFSBP_TB_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfsbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__sdfsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/24/2016 03:17:47 PM
// Design Name:
// Module Name: Problem2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Problem2(
input [7:0] Input,
input Ein,
output reg Eout,
output reg GS,
output reg [2:0] Number
);
always @ (Input, Ein)
begin
if (Ein == 0) // Everything turned off
begin
Eout = 0;
GS = 0;
Number = 3'b000;
end
else
begin
if (Input == 8'b00000000) // Ein = 1 and every input line at 0
begin
GS = 0;
Eout = 1;
Number = 3'b000;
end
else
begin
GS = 1;
Eout = 0; // Group Signal on if code reaches this point
if (Input[7] == 1) // Priority is accomplished by order of if statements
Number = 3'b111;
else if (Input[6] == 1)
Number = 3'b110;
else if (Input[5] == 1)
Number = 3'b101;
else if (Input[4] == 1)
Number = 3'b100;
else if (Input[3] == 1)
Number = 3'b011;
else if (Input[2] == 1)
Number = 3'b010;
else if (Input[1] == 1)
Number = 3'b001;
else
Number = 3'b000;
end
end
end
endmodule
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_onchip_memory2_1 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 9: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 1024,
the_altsyncram.numwords_a = 1024,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 10;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_FUNCTIONAL_V
`define SKY130_FD_SC_MS__OR4_FUNCTIONAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_FUNCTIONAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:29:19 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_vga_nmsuppression_1_0 -prefix
// system_vga_nmsuppression_1_0_ system_vga_nmsuppression_1_0_stub.v
// Design : system_vga_nmsuppression_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_nmsuppression,Vivado 2016.4" *)
module system_vga_nmsuppression_1_0(clk, enable, active, x_addr_in, y_addr_in,
hessian_in, x_addr_out, y_addr_out, hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk,enable,active,x_addr_in[9:0],y_addr_in[9:0],hessian_in[31:0],x_addr_out[9:0],y_addr_out[9:0],hessian_out[31:0]" */;
input clk;
input enable;
input active;
input [9:0]x_addr_in;
input [9:0]y_addr_in;
input [31:0]hessian_in;
output [9:0]x_addr_out;
output [9:0]y_addr_out;
output [31:0]hessian_out;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_dipsw_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_PP_SYMBOL_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_PP_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvpwrvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// serialInterface.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Perform all serial to parallel, and parallel
//// to serial conversions. Perform device address matching
//// Handle arbitrary length I2C reads terminated by NAK
//// from host, and arbitrary length I2C writes terminated
//// by STOP from host
//// The second byte of a I2C write is always interpreted
//// as a register address, and becomes the base register address
//// for all read and write transactions.
//// I2C WRITE: devAddr, regAddr, data[regAddr], data[regAddr+1], ..... data[regAddr+N]
//// I2C READ: data[regAddr], data[regAddr+1], ..... data[regAddr+N]
//// Note that when regAddR reaches 255 it will automatically wrap round to 0
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"
module serialInterface (clearStartStopDet, clk, dataIn, dataOut, regAddr, rst, scl, sdaIn, sdaOut, startStopDetState, writeEn);
input clk;
input [7:0]dataIn;
input rst;
input scl;
input sdaIn;
input [1:0]startStopDetState;
output clearStartStopDet;
output [7:0]dataOut;
output [7:0]regAddr;
output sdaOut;
output writeEn;
reg clearStartStopDet, next_clearStartStopDet;
wire clk;
wire [7:0]dataIn;
reg [7:0]dataOut, next_dataOut;
reg [7:0]regAddr, next_regAddr;
wire rst;
wire scl;
wire sdaIn;
reg sdaOut, next_sdaOut;
wire [1:0]startStopDetState;
reg writeEn, next_writeEn;
// diagram signals declarations
reg [2:0]bitCnt, next_bitCnt;
reg [7:0]rxData, next_rxData;
reg [1:0]streamSt, next_streamSt;
reg [7:0]txData, next_txData;
// BINARY ENCODED state machine: SISt
// State codes definitions:
`define START 4'b0000
`define CHK_RD_WR 4'b0001
`define READ_RD_LOOP 4'b0010
`define READ_WT_HI 4'b0011
`define READ_CHK_LOOP_FIN 4'b0100
`define READ_WT_LO 4'b0101
`define READ_WT_ACK 4'b0110
`define WRITE_WT_LO 4'b0111
`define WRITE_WT_HI 4'b1000
`define WRITE_CHK_LOOP_FIN 4'b1001
`define WRITE_LOOP_WT_LO 4'b1010
`define WRITE_ST_LOOP 4'b1011
`define WRITE_WT_LO2 4'b1100
`define WRITE_WT_HI2 4'b1101
`define WRITE_CLR_WR 4'b1110
`define WRITE_CLR_ST_STOP 4'b1111
reg [3:0]CurrState_SISt, NextState_SISt;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
// Machine: SISt
// NextState logic (combinatorial)
always @ (startStopDetState or streamSt or scl or txData or bitCnt or rxData or sdaIn or regAddr or dataIn or sdaOut or writeEn or dataOut or clearStartStopDet or CurrState_SISt)
begin
NextState_SISt <= CurrState_SISt;
// Set default values for outputs and signals
next_streamSt <= streamSt;
next_txData <= txData;
next_rxData <= rxData;
next_sdaOut <= sdaOut;
next_writeEn <= writeEn;
next_dataOut <= dataOut;
next_bitCnt <= bitCnt;
next_clearStartStopDet <= clearStartStopDet;
next_regAddr <= regAddr;
case (CurrState_SISt) // synopsys parallel_case full_case
`START:
begin
next_streamSt <= `STREAM_IDLE;
next_txData <= 8'h00;
next_rxData <= 8'h00;
next_sdaOut <= 1'b1;
next_writeEn <= 1'b0;
next_dataOut <= 8'h00;
next_bitCnt <= 3'b000;
next_clearStartStopDet <= 1'b0;
NextState_SISt <= `CHK_RD_WR;
end
`CHK_RD_WR:
begin
if (streamSt == `STREAM_READ)
begin
NextState_SISt <= `READ_RD_LOOP;
next_txData <= dataIn;
next_regAddr <= regAddr + 1'b1;
next_bitCnt <= 3'b001;
end
else
begin
NextState_SISt <= `WRITE_WT_HI;
next_rxData <= 8'h00;
end
end
`READ_RD_LOOP:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `READ_WT_HI;
next_sdaOut <= txData [7];
next_txData <= {txData [6:0], 1'b0};
end
end
`READ_WT_HI:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `READ_CHK_LOOP_FIN;
end
end
`READ_CHK_LOOP_FIN:
begin
if (bitCnt == 3'b000)
begin
NextState_SISt <= `READ_WT_LO;
end
else
begin
NextState_SISt <= `READ_RD_LOOP;
next_bitCnt <= bitCnt + 1'b1;
end
end
`READ_WT_LO:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `READ_WT_ACK;
next_sdaOut <= 1'b1;
end
end
`READ_WT_ACK:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `CHK_RD_WR;
if (sdaIn == `I2C_NAK)
next_streamSt <= `STREAM_IDLE;
end
end
`WRITE_WT_LO:
begin
if ((scl == 1'b0) && (startStopDetState == `STOP_DET ||
(streamSt == `STREAM_IDLE && startStopDetState == `NULL_DET)))
begin
NextState_SISt <= `WRITE_CLR_ST_STOP;
case (startStopDetState)
`NULL_DET:
next_bitCnt <= bitCnt + 1'b1;
`START_DET: begin
next_streamSt <= `STREAM_IDLE;
next_rxData <= 8'h00;
end
default: ;
endcase
next_streamSt <= `STREAM_IDLE;
next_clearStartStopDet <= 1'b1;
end
else if (scl == 1'b0)
begin
NextState_SISt <= `WRITE_ST_LOOP;
case (startStopDetState)
`NULL_DET:
next_bitCnt <= bitCnt + 1'b1;
`START_DET: begin
next_streamSt <= `STREAM_IDLE;
next_rxData <= 8'h00;
end
default: ;
endcase
end
end
`WRITE_WT_HI:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_WT_LO;
next_rxData <= {rxData [6:0], sdaIn};
next_bitCnt <= 3'b000;
end
end
`WRITE_CHK_LOOP_FIN:
begin
if (bitCnt == 3'b111)
begin
NextState_SISt <= `WRITE_CLR_WR;
next_sdaOut <= `I2C_ACK;
case (streamSt)
`STREAM_IDLE: begin
if (rxData[7:1] == `I2C_ADDRESS &&
startStopDetState == `START_DET) begin
if (rxData[0] == 1'b1)
next_streamSt <= `STREAM_READ;
else
next_streamSt <= `STREAM_WRITE_ADDR;
end
else
next_sdaOut <= `I2C_NAK;
end
`STREAM_WRITE_ADDR: begin
next_streamSt <= `STREAM_WRITE_DATA;
next_regAddr <= rxData;
end
`STREAM_WRITE_DATA: begin
next_dataOut <= rxData;
next_writeEn <= 1'b1;
end
default:
next_streamSt <= streamSt;
endcase
end
else
begin
NextState_SISt <= `WRITE_ST_LOOP;
next_bitCnt <= bitCnt + 1'b1;
end
end
`WRITE_LOOP_WT_LO:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `WRITE_CHK_LOOP_FIN;
end
end
`WRITE_ST_LOOP:
begin
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_LOOP_WT_LO;
next_rxData <= {rxData [6:0], sdaIn};
end
end
`WRITE_WT_LO2:
begin
if (scl == 1'b0)
begin
NextState_SISt <= `CHK_RD_WR;
next_sdaOut <= 1'b1;
end
end
`WRITE_WT_HI2:
begin
next_clearStartStopDet <= 1'b0;
if (scl == 1'b1)
begin
NextState_SISt <= `WRITE_WT_LO2;
end
end
`WRITE_CLR_WR:
begin
if (writeEn == 1'b1)
next_regAddr <= regAddr + 1'b1;
next_writeEn <= 1'b0;
next_clearStartStopDet <= 1'b1;
NextState_SISt <= `WRITE_WT_HI2;
end
`WRITE_CLR_ST_STOP:
begin
next_clearStartStopDet <= 1'b0;
NextState_SISt <= `CHK_RD_WR;
end
endcase
end
// Current State Logic (sequential)
always @ (posedge clk)
begin
if (rst == 1'b1)
CurrState_SISt <= `START;
else
CurrState_SISt <= NextState_SISt;
end
// Registered outputs logic
always @ (posedge clk)
begin
if (rst == 1'b1)
begin
sdaOut <= 1'b1;
writeEn <= 1'b0;
dataOut <= 8'h00;
clearStartStopDet <= 1'b0;
// regAddr <= // Initialization in the reset state or default value required!!
streamSt <= `STREAM_IDLE;
txData <= 8'h00;
rxData <= 8'h00;
bitCnt <= 3'b000;
end
else
begin
sdaOut <= next_sdaOut;
writeEn <= next_writeEn;
dataOut <= next_dataOut;
clearStartStopDet <= next_clearStartStopDet;
regAddr <= next_regAddr;
streamSt <= next_streamSt;
txData <= next_txData;
rxData <= next_rxData;
bitCnt <= next_bitCnt;
end
end
endmodule |
/*******************************************************************************
* Module: simul_axi_master_wraddr
* Date:2014-03-24
* Author: Andrey Filippov
* Description: Simulation model for AXI write address channel
*
* Copyright (c) 2014 Elphel, Inc..
* simul_axi_master_wraddr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_axi_master_wraddr.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module simul_axi_master_wraddr
#(
parameter integer ID_WIDTH=12,
parameter integer ADDRESS_WIDTH=32,
parameter integer LATENCY=0, // minimal delay between inout and output ( 0 - next cycle)
parameter integer DEPTH=8, // maximal number of commands in FIFO
parameter DATA_DELAY = 3.5,
parameter VALID_DELAY = 4.0
)(
input clk,
input reset,
input [ID_WIDTH-1:0] awid_in,
input [ADDRESS_WIDTH-1:0] awaddr_in,
input [3:0] awlen_in,
input [1:0] awsize_in,
input [1:0] awburst_in,
input [3:0] awcache_in,
input [2:0] awprot_in,
output [ID_WIDTH-1:0] awid,
output [ADDRESS_WIDTH-1:0] awaddr,
output [3:0] awlen,
output [1:0] awsize,
output [1:0] awburst,
output [3:0] awcache,
output [2:0] awprot,
output awvalid,
input awready,
input set_cmd, // latch all other input data at posedge of clock
output ready // command/data FIFO can accept command
);
wire [ID_WIDTH-1:0] awid_out;
wire [ADDRESS_WIDTH-1:0] awaddr_out;
wire [3:0] awlen_out;
wire [1:0] awsize_out;
wire [1:0] awburst_out;
wire [3:0] awcache_out;
wire [2:0] awprot_out;
wire awvalid_out;
assign #(DATA_DELAY) awid= awid_out;
assign #(DATA_DELAY) awaddr= awaddr_out;
assign #(DATA_DELAY) awlen= awlen_out;
assign #(DATA_DELAY) awsize= awsize_out;
assign #(DATA_DELAY) awburst= awburst_out;
assign #(DATA_DELAY) awcache= awcache_out;
assign #(DATA_DELAY) awprot= awprot_out;
assign #(VALID_DELAY) awvalid= awvalid_out;
simul_axi_fifo
#(
.WIDTH(ID_WIDTH+ADDRESS_WIDTH+15), // total number of output bits
.LATENCY(LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(DEPTH) // maximal number of commands in FIFO
// parameter OUT_DELAY = 3.5,
) simul_axi_fifo_i (
.clk(clk), // input clk,
.reset(reset), // input reset,
.data_in({awid_in,awaddr_in,awlen_in,awsize_in,awburst_in,awcache_in,awprot_in}), // input [WIDTH-1:0] data_in,
.load(set_cmd), // input load,
.input_ready(ready), // output input_ready,
.data_out({awid_out,awaddr_out,awlen_out,awsize_out,awburst_out,awcache_out,awprot_out}), // output [WIDTH-1:0] data_out,
.valid(awvalid_out), // output valid,
.ready(awready)); // input ready);
endmodule
|
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Synchronous Fifo
//
// Revision Information:
// Date Description
//
//
// SVN Revision Information:
// SVN $Revision: 21608 $
// SVN $Date: 2013-12-02 16:03:36 -0800 (Mon, 02 Dec 2013) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// Sept 5th. Fix for reading empty fifo.
//
// *********************************************************************/
module spi_fifo( pclk,
presetn,
fiforst,
//fifosize,
data_in,
flag_in,
data_out,
flag_out,
read_in,
write_in,
full_out,
empty_out,
full_next_out,
empty_next_out,
overflow_out,
fifo_count
);
parameter CFG_FRAME_SIZE = 4; // 4-32
parameter FIFO_DEPTH = 4; // 2,4,8,16,32
input pclk;
input presetn;
input fiforst;
//input [1:0] fifosize;
input [CFG_FRAME_SIZE-1:0] data_in;
input read_in;
input write_in;
input flag_in;
output [CFG_FRAME_SIZE-1:0] data_out;
output empty_out;
output full_out;
output empty_next_out;
output full_next_out;
output overflow_out;
output flag_out;
output [5:0] fifo_count;
reg [4:0] rd_pointer_d;
reg [4:0] rd_pointer_q; //read pointer address
reg [4:0] wr_pointer_d;
reg [4:0] wr_pointer_q; //write pointer address
reg [5:0] counter_d;
reg [5:0] counter_q; //counter 5 bits
reg [CFG_FRAME_SIZE:0] fifo_mem_d[0:FIFO_DEPTH-1]; //FIFO has extra flag bit (CFG_FRAME_SIZE + 1)
reg [CFG_FRAME_SIZE:0] fifo_mem_q[0:FIFO_DEPTH-1];
reg [CFG_FRAME_SIZE:0] data_out_dx;
reg [CFG_FRAME_SIZE:0] data_out_d;
reg full_out;
reg empty_out;
reg full_next_out;
reg empty_next_out;
// -----------------------------
// AS: replaced with fixed width
// -----------------------------
//localparam [1:0] FS4 = 2'b00;
//localparam [1:0] FS8 = 2'b01;
//localparam [1:0] FS16 = 2'b10;
//localparam [1:0] FS32 = 2'b11;
//
//
//// AS: replaced with parameter
////reg [5:0] FIFO_DEPTH;
//
//always @(posedge pclk or negedge presetn) // Register as this feeds into lots of logic
//begin
// if (~presetn)
// FIFO_DEPTH <= 4;
// else
// begin
// case (fifosize)
// FS8 : FIFO_DEPTH <= 8;
// FS16 : FIFO_DEPTH <= 16;
// FS32 : FIFO_DEPTH <= 32;
// default : FIFO_DEPTH <= 4;
// endcase
// end
//end
wire [CFG_FRAME_SIZE-1:0] data_out = data_out_d[CFG_FRAME_SIZE-1:0];
wire flag_out = data_out_d[CFG_FRAME_SIZE];
assign overflow_out = (write_in && (counter_q == FIFO_DEPTH)); /* write and fifo full */
integer i;
//------------------------------------------------------------------------------------------------------------
//infer the FIFO - no reset required
always @(posedge pclk)
begin
for (i=0; i<FIFO_DEPTH; i=i+1)
begin
fifo_mem_q[i] <= fifo_mem_d[i];
end
end
//infer the registers and register the flags
always @(posedge pclk or negedge presetn)
begin
if (~presetn)
begin
rd_pointer_q <= 0;
wr_pointer_q <= 0;
counter_q <= 0;
full_out <= 0;
empty_out <= 1;
full_next_out <= 0;
empty_next_out <= 0;
end
else
begin
rd_pointer_q <= rd_pointer_d;
wr_pointer_q <= wr_pointer_d;
counter_q <= counter_d;
full_out <= (counter_d == FIFO_DEPTH); //is next pointer equal to fifo length
empty_out <= (counter_d == 0);
full_next_out <= (counter_q == FIFO_DEPTH-1);
empty_next_out <= (counter_q == 1);
end
end
integer j;
always @(*)
begin
for (j=0; j<FIFO_DEPTH; j=j+1) // Hold old values
begin
fifo_mem_d[j] = fifo_mem_q[j];
end
if (write_in)
begin
if (counter_q != FIFO_DEPTH)
begin
// -----------------------------------------
// AS: replaced with fixed size (CFG_FRAME_SIZE)
// -----------------------------------------
fifo_mem_d[wr_pointer_q[4:0]][CFG_FRAME_SIZE-1:0] = data_in[CFG_FRAME_SIZE-1:0];
fifo_mem_d[wr_pointer_q[4:0]][CFG_FRAME_SIZE] = flag_in;
end
end
//Read - data out always available
data_out_dx = fifo_mem_q[rd_pointer_q[4:0]];
end
// Perform extra read mux on Byte/Half wide reads
always @(*)
begin
// AS: removed Byte/Half wide read option
// flag bits are zero if count zero
data_out_d = data_out_dx[CFG_FRAME_SIZE:0];
if (counter_q == 0) data_out_d[CFG_FRAME_SIZE] = 1'b0;
end
// Pointers and Flags
always @(*)
begin
if (fiforst==1'b1)
begin
wr_pointer_d = 5'b00000;
rd_pointer_d = 5'b00000;
counter_d = 6'b000000;
end
else
begin
//defaults
counter_d = counter_q;
rd_pointer_d = rd_pointer_q;
wr_pointer_d = wr_pointer_q;
if (read_in)
begin
if (counter_q != 0) // ignore read when empty
begin
if (~write_in) //if not writing decrement count of the number of objects in fifo else count stays the same
begin
counter_d = counter_q - 1'b1;
end
// AS: Added limits for wrap-around
if (rd_pointer_q == FIFO_DEPTH - 1)
rd_pointer_d = 5'b00000;
else
rd_pointer_d = rd_pointer_q + 1'b1;
end
end //~read_n
if (write_in)
begin
if (counter_q != FIFO_DEPTH) // ignore write when full
begin
if (~read_in)
begin
counter_d = counter_q + 1'b1;
end
// AS: Added limits for wrap-around
if (wr_pointer_q == FIFO_DEPTH-1)
wr_pointer_d = 5'b00000;
else
wr_pointer_d = wr_pointer_q + 1'b1;
end //~write_n
end
end
end
wire [5:0] fifo_count = counter_q;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_SYMBOL_V
`define SKY130_FD_SC_MS__A221O_SYMBOL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a221o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_PP_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_FUNCTIONAL_PP_V |
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma_gige.v,v $
//
// $Revision: #1 $
// $Date: 2011/08/15 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs_pma_gige /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
gxb_cal_blk_clk,
gxb_pwrdn_in,
magic_sleep_n,
mdio_in,
read,
reconfig_clk,
reconfig_togxb,
reconfig_busy,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
pcs_pwrdn_out,
readdata,
reconfig_fromgxb,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
rx_recovclkout,
waitrequest
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output pcs_pwrdn_out;
output [31: 0] readdata;
output [16:0] reconfig_fromgxb;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output rx_recovclkout;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input gxb_cal_blk_clk;
input gxb_pwrdn_in;
input magic_sleep_n;
input mdio_in;
input read;
input reconfig_clk;
input [3:0] reconfig_togxb;
input reconfig_busy;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire gige_pma_reset;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire rx_pcs_clk;
wire tx_pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire rx_char_err_gx;
wire rx_disp_err;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire sd_loopback;
wire tx_ff_uflow;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire rx_recovclkout;
wire waitrequest;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_carrierdetected;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
wire [16:0] reconfig_fromgxb;
wire reset_ref_clk;
wire reset_rx_pcs_clk_int;
wire pll_powerdown_sqcnr,tx_digitalreset_sqcnr,rx_analogreset_sqcnr,rx_digitalreset_sqcnr,gxb_powerdown_sqcnr,pll_locked;
wire locked_signal;
wire rx_freqlocked;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_strx_gx_ena altera_tse_mac_pcs_pma_strx_gx_ena_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (reset),
.rx_clkout (rx_pcs_clk),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frame (pcs_rx_frame),
.rx_frm_type (rx_frm_type),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.tx_clkout (tx_pcs_clk),
.tx_ff_uflow (tx_ff_uflow),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
reg reset_p1, reset_p2;
reg reset_posedge;
always@(posedge clk)
begin
reset_p1 <= reset;
reset_p2 <= reset_p1;
reset_posedge <= reset_p1 & ~reset_p2;
end
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_d1, gxb_pwrdn_in_sig_clk;
generate if (EXPORT_PWRDN == 1)
begin
always @(posedge clk or posedge gxb_pwrdn_in)
begin
if (gxb_pwrdn_in == 1) begin
data_in_d1 <= 1;
gxb_pwrdn_in_sig_clk <= 1;
end else begin
data_in_d1 <= 1'b0;
gxb_pwrdn_in_sig_clk <= data_in_d1;
end
end
assign gxb_pwrdn_in_sig = gxb_pwrdn_in;
assign pcs_pwrdn_out = pcs_pwrdn_out_sig;
end
else
begin
assign gxb_pwrdn_in_sig = pcs_pwrdn_out_sig;
assign pcs_pwrdn_out = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk = gxb_pwrdn_in_sig;
end
end
endgenerate
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst(
// User inputs and outputs
.clock(clk),
.reset_all(reset | gxb_pwrdn_in_sig_clk),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr),// output
.tx_digitalreset(tx_digitalreset_sqcnr),// output
.rx_analogreset(rx_analogreset_sqcnr),// output
.rx_digitalreset(rx_digitalreset_sqcnr),// output
.gxb_powerdown(gxb_powerdown_sqcnr),// output
.pll_is_locked(locked_signal),
.rx_is_lockedtodata(rx_freqlocked),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy)
);
assign locked_signal = (reset? 1'b0: pll_locked);
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
altera_tse_reset_synchronizer ch_0_reset_sync_0 (
.clk(rx_pcs_clk),
.reset_in(rx_digitalreset_sqcnr),
.reset_out(reset_rx_pcs_clk_int)
);
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(rx_pcs_clk),
.reset(reset_rx_pcs_clk_int),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig),
.pll_inclk (ref_clk),
.reconfig_clk(reconfig_clk),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb),
.rx_analogreset (rx_analogreset_sqcnr),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar),
.rx_clkout (rx_pcs_clk),
.rx_datain (rxp),
.rx_dataout (rx_frame),
.rx_digitalreset (rx_digitalreset_sqcnr),
.rx_disperr (rx_disp_err),
.rx_errdetect (rx_char_err_gx),
.rx_patterndetect (rx_patterndetect),
.rx_rlv (rx_runlengthviolation),
.rx_seriallpbken (sd_loopback),
.rx_syncstatus (rx_syncstatus),
.tx_clkout (tx_pcs_clk),
.tx_ctrlenable (tx_kchar),
.tx_datain (tx_frame),
.rx_freqlocked (rx_freqlocked),
.tx_dataout (txp),
.tx_digitalreset (tx_digitalreset_sqcnr),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.rx_runningdisp(rx_runningdisp),
.pll_powerdown(gxb_pwrdn_in_sig),
.pll_locked(pll_locked)
);
defparam
the_altera_tse_gxb_gige_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst.DEVICE_FAMILY = DEVICE_FAMILY,
the_altera_tse_gxb_gige_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_4_V
`define SKY130_FD_SC_LS__O221A_4_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221a_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__HA_FUNCTIONAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_FUNCTIONAL_PP_V |
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: gshare branch predictor
This predictor is based on array of FSMs with 4 states: strongly not taken,
weakly not taken, weakly taken, strongly taken. Check saturation predictor.
Index to the array of FSMs is built using xor of global history and lower bits of PC.
Copyright (C) 2016 Alexey Baturo <[email protected]>
******************************************************************************/
`include "mor1kx-defines.v"
module mor1kx_branch_predictor_gshare
#(
parameter GSHARE_BITS_NUM = 10,
parameter OPTION_OPERAND_WIDTH = 32
)
(
input clk,
input rst,
// Signals belonging to the stage where the branch is predicted.
output predicted_flag_o, //result of predictor
input execute_op_bf_i, // prev insn was bf
input execute_op_bnf_i, // prev insn was bnf
input op_bf_i, // cur insn is bf
input op_bnf_i, // cur insn is bnf
input padv_decode_i, // pipeline is moved
input flag_i, // prev predicted flag
// Signals belonging to the stage where the branch is resolved.
input prev_op_brcond_i, // prev op was cond brn
input branch_mispredict_i, // prev brn was mispredicted
input [OPTION_OPERAND_WIDTH-1:0] brn_pc_i
);
localparam [1:0]
STATE_STRONGLY_NOT_TAKEN = 2'b00,
STATE_WEAKLY_NOT_TAKEN = 2'b01,
STATE_WEAKLY_TAKEN = 2'b10,
STATE_STRONGLY_TAKEN = 2'b11;
localparam FSM_NUM = 2 ** GSHARE_BITS_NUM;
integer i = 0;
reg [1:0] state [0:FSM_NUM];
reg [GSHARE_BITS_NUM:0] brn_hist_reg = 0;
reg [GSHARE_BITS_NUM - 1:0] prev_idx = 0;
// +2 bits for alignement
wire [GSHARE_BITS_NUM - 1:0] state_index = brn_hist_reg[GSHARE_BITS_NUM - 1:0] ^ brn_pc_i[GSHARE_BITS_NUM + 1:2];
assign predicted_flag_o = (state[state_index][1] && op_bf_i) ||
(!state[state_index][1] && op_bnf_i);
wire brn_taken = (execute_op_bf_i && flag_i) || (execute_op_bnf_i && !flag_i);
always @(posedge clk) begin
if (rst) begin
brn_hist_reg <= 0;
prev_idx <= 0;
for(i = 0; i < FSM_NUM; i = i + 1) begin
state[i] = STATE_WEAKLY_TAKEN;
end
end else begin
if (op_bf_i || op_bnf_i) begin
// store prev index
prev_idx <= state_index;
end
if (prev_op_brcond_i && padv_decode_i) begin
brn_hist_reg <= {brn_hist_reg[GSHARE_BITS_NUM - 1 : 0], brn_taken};
if (!brn_taken) begin
// change fsm state:
// STATE_STRONGLY_TAKEN -> STATE_WEAKLY_TAKEN
// STATE_WEAKLY_TAKEN -> STATE_WEAKLY_NOT_TAKEN
// STATE_WEAKLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
// STATE_STRONGLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
case (state[prev_idx])
STATE_STRONGLY_TAKEN:
state[prev_idx] <= STATE_WEAKLY_TAKEN;
STATE_WEAKLY_TAKEN:
state[prev_idx] <= STATE_WEAKLY_NOT_TAKEN;
STATE_WEAKLY_NOT_TAKEN:
state[prev_idx] <= STATE_STRONGLY_NOT_TAKEN;
STATE_STRONGLY_NOT_TAKEN:
state[prev_idx] <= STATE_STRONGLY_NOT_TAKEN;
endcase
end else begin
// change fsm state:
// STATE_STRONGLY_NOT_TAKEN -> STATE_WEAKLY_NOT_TAKEN
// STATE_WEAKLY_NOT_TAKEN -> STATE_WEAKLY_TAKEN
// STATE_WEAKLY_TAKEN -> STATE_STRONGLY_TAKEN
// STATE_STRONGLY_TAKEN -> STATE_STRONGLY_TAKEN
case (state[prev_idx])
STATE_STRONGLY_NOT_TAKEN:
state[prev_idx] <= STATE_WEAKLY_NOT_TAKEN;
STATE_WEAKLY_NOT_TAKEN:
state[prev_idx] <= STATE_WEAKLY_TAKEN;
STATE_WEAKLY_TAKEN:
state[prev_idx] <= STATE_STRONGLY_TAKEN;
STATE_STRONGLY_TAKEN:
state[prev_idx] <= STATE_STRONGLY_TAKEN;
endcase
end
end
end
end
endmodule
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : debug_unit
// Author : Caleb Fangmeier
// Description : This is a simple debugger to allow single stepping through
// the execution of the firmware.
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module debug_unit #(parameter SIZE=1)(
input wire clk,
input wire reset,
input wire [32*SIZE-1:0] debug_wireout,
input wire okClk,
input wire [112:0] okHE,
output wire [64:0] okEH
);
//----------------------------------------------------------------------------
// Wires
//----------------------------------------------------------------------------
wire [SIZE-1:0] output_buffer_rdreq;
wire [31:0] output_buffer_q [SIZE-1:0];
wire [12:0] output_buffer_wrusedw [SIZE-1:0];
wire [12:0] output_buffer_rdusedw [SIZE-1:0];
wire [SIZE-1:0] buffer_space_ok;
wire [SIZE*65-1:0] okEHx;
//----------------------------------------------------------------------------
// REGISTERS
//----------------------------------------------------------------------------
reg [10:0] write_count;
reg output_buffer_wrreq;
reg [32*SIZE-1:0] output_buffer_data;
//----------------------------------------------------------------------------
// Assignments
//----------------------------------------------------------------------------
generate
genvar i;
for ( i=0; i<SIZE; i=i+1 ) begin: my_loop_1
assign buffer_space_ok[i] = (output_buffer_wrusedw[i] <= 13'd3072);
end
endgenerate
integer j;
always @( posedge clk ) begin
output_buffer_wrreq <= 0;
if ( reset ) begin
write_count <= 0;
end
else begin
if ( write_count == 0 ) begin
if ( & buffer_space_ok ) begin
write_count <= 11'd1024;
end
end
else if ( write_count == 1 ) begin
for ( j=0; j<SIZE; j=j+1 ) begin: my_loop_3
output_buffer_data[32*j +: 32] <= 32'hFFFF_FFFF;
end
output_buffer_wrreq <= 1;
write_count <= write_count - 11'd1;
end
else begin
output_buffer_data <= debug_wireout;
output_buffer_wrreq <= 1;
write_count <= write_count - 11'd1;
end
end
end
okWireOR #( .N(SIZE) ) wireOR (
.okEH ( okEH ),
.okEHx ( okEHx )
);
generate
for ( i=0; i<SIZE; i=i+1 ) begin: my_loop_2
fifo32_clk_crossing_with_usage output_buffer (
.wrclk ( clk ),
.rdclk ( okClk ),
.aclr ( reset ),
.data ( output_buffer_data[32*i +: 32] ),
.q ( output_buffer_q[i] ),
.wrreq ( output_buffer_wrreq ),
.rdreq ( output_buffer_rdreq[i] ),
.wrusedw ( output_buffer_wrusedw[i] ),
.rdusedw ( output_buffer_rdusedw[i] )
);
okBTPipeOut pipeout_inst(
.okHE ( okHE ),
.okEH ( okEHx[65*i +: 65] ),
.ep_addr ( 8'hB0+i ),
.ep_datain ( output_buffer_q[i] ),
.ep_read ( output_buffer_rdreq[i] ),
.ep_blockstrobe ( ),
.ep_ready ( output_buffer_rdusedw[i] >= 13'd1024 )
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:58:36 04/14/2015
// Design Name: main
// Module Name: E:/Adventure/Adventure/MainTest.v
// Project Name: Adventure
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module MainTest;
// Inputs
reg clk_50MHz;
reg [3:0] SWITCH;
reg [3:0] BUTTON;
reg xin;
reg yin;
// Outputs
wire vs_vga;
wire hs_vga;
wire [2:0] RED;
wire [2:0] GREEN;
wire [1:0] BLUE;
// Instantiate the Unit Under Test (UUT)
main uut (
.clk_50MHz(clk_50MHz),
.vs_vga(xin),
.hs_vga(yin),
.RED(RED),
.GREEN(GREEN),
.BLUE(BLUE),
.SWITCH(SWITCH),
.BUTTON(BUTTON)
);
initial begin
clk_50MHz = 0;
forever
#5 clk_50MHz = ~clk_50MHz;
xin = ~xin;
yin = ~yin;
end
initial begin
// Initialize Inputs
// Wait 100 ns for global reset to finish
#100;
//640x480
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
integer p_i;
reg [7*8:1] p_str;
string sv_str;
reg [7*8:1] p_in;
string sv_in;
initial begin
if ($test$plusargs("PLUS")!==1) $stop;
if ($test$plusargs("PLUSNOT")!==0) $stop;
if ($test$plusargs("PL")!==1) $stop;
//if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer
if ($test$plusargs("NOTTHERE")!==0) $stop;
p_i = 10;
if ($value$plusargs("NOTTHERE%d", p_i)!==0) $stop;
if (p_i !== 10) $stop;
p_i = 0;
if ($value$plusargs("INT=%d", p_i)!==1) $stop;
if (p_i !== 32'd1234) $stop;
p_i = 0;
if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also
if (p_i !== 32'h1234) $stop;
p_i = 0;
// Check octal and WIDTH
if (!$value$plusargs("INT=%o", p_i)) $stop;
if (p_i !== 32'o1234) $stop;
p_str = "none";
if ($value$plusargs("IN%s", p_str)!==1) $stop;
$display("str='%s'",p_str);
if (p_str !== "T=1234") $stop;
sv_str = "none";
if ($value$plusargs("IN%s", sv_str)!==1) $stop;
$display("str='%s'",sv_str);
if (sv_str != "T=1234") $stop;
sv_str = "none";
$value$plusargs("IN%s", sv_str);
$display("str='%s'",sv_str);
if (sv_str != "T=1234") $stop;
p_in = "IN%s";
`ifdef VERILATOR
p_in = $c(p_in); // Prevent constant propagation
`endif
sv_str = "none";
if ($value$plusargs(p_in, sv_str)!==1) $stop;
$display("str='%s'",sv_str);
if (sv_str != "T=1234") $stop;
sv_in = "INT=%d";
`ifdef VERILATOR
if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation
`endif
p_i = 0;
if ($value$plusargs(sv_in, p_i)!==1) $stop;
$display("i='%d'",p_i);
if (p_i !== 32'd1234) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/******************************************************************************
* File Name : smul.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 3/Apr/2008
* Type of file : Verilog source code
* Synopsis : This file contains the module for scalar
* multiplication on the curve
* y^2 + xy = x^3 + a.x^2 + b
* where a = 1
******************************************************************************/
`timescale 1ns / 1ps
`ifndef __ECSMUL_V__
`define __ECSMUL_V__
//`include "regbank.v"
//`include "ec_alu.v"
//`include "counter.v"
/* Basepoint for the curve, taken from FIPS 186-2 */
`define BASEPOINT_X 233'h0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b
`define BASEPOINT_Y 233'h1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052
/* The constant b for the curve, from FIPS 186-2 again */
`define CURVECONSTANT_B 233'h066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad
`define KEYMSB 31
/*---------------------------------------------------------------------------
* Module Name : ecsmul
* Synopsis : Elliptic Curve scalar multiplier. This is the top module.
* Instances of the following are made here
* 1. regfile -> used for registers
* 2. ecalu -> the ec alu
* 3. counter -> used to find the number of interations to be done
*--------------------------------------------------------------------------*/
module ecsmul(clk, nrst, key, sx, sy, done);
input wire clk;
input wire nrst; /* asynchronous active low reset */
input wire [`KEYMSB:0] key; /* The secret key */
output wire [232:0] sx, sy; /* Contains final result after multiplication */
output wire done; /* Sets to one when multiplication is complete */
reg [22:0] cwh; /* Control Word for Registers*/
reg [9:0] cwl; /* Control word for ALU */
reg [`KEYMSB:0] k; /* The copy of the secret key */
reg [5:0] state, nextstate; /* state and next state registers */
reg start; /* set when the first 1 is detected in the key */
wire [232:0] a0, a1, a2, a3; /* ALU Inputs */
wire [232:0] c0r, c1r; /* Register File inputs */
wire [232:0] c0a, c1a; /* ALU Outputs */
wire [232:0] yconstants; /* Could be either basepoint_y or curveconstant_b */
wire tstart; /* see start */
/* Counter variables */
reg cck; /* Clock for the counter, toggles every time the state is 1*/
wire mainclk; /* Takes either the cck or the clk depending on start */
wire ef; /* Goes low for one cck clock cycle when counter reaches 0 */
/* Instantiantions */
regbank regs(clk, cwh, c0r, c1r, a0, a1, a2, a3);
ec_alu alu(cwl, a0, a1, a2, a3, c0a, c1a);
counter iterations(mainclk, nrst, ef);
/* The input to regbank is either constants or the results from ALU */
assign c0r = (cwh[22] == 1'b0) ? c0a : `BASEPOINT_X;
assign c1r = (cwh[22] == 1'b0) ? c1a : yconstants;
assign yconstants = (state != 6'd2) ? `BASEPOINT_Y : `CURVECONSTANT_B;
/* Store the results after converting back into affine coordinates */
assign sx = (key != 233'b1) ? a0 : `BASEPOINT_X;
assign sy = (key != 233'b1) ? a2 : `BASEPOINT_Y;
assign done = (state == 6'd38) ? 1 : 0; /* Set done to 1 if multiplication is complete */
/* the next state logic */
always @(state) begin
case(state)
/* Init states */
6'd0: nextstate <= 6'd1;
6'd1: nextstate <= 6'd2;
6'd2: nextstate <= 6'd3;
/* Double States */
6'd3: nextstate <= 6'd4;
6'd4: nextstate <= 6'd5;
6'd5: nextstate <= 6'd6;
6'd6: begin
if(k[`KEYMSB] == 1'b1)
nextstate <= 6'd7; /* Do Addition and doubling if K0 is 1 */
else if (ef == 1'b0)
nextstate <= 6'd15; /* k[0]=0 and we are in the last iteration, goto end */
else
nextstate <= 6'd3; /* Skip addition and do next doubling */
end
/* Addition States */
6'd7: nextstate <= 6'd8;
6'd8: nextstate <= 6'd9;
6'd9: nextstate <= 6'd10;
6'd10: nextstate <= 6'd11;
6'd11: nextstate <= 6'd12;
6'd12: nextstate <= 6'd13;
6'd13: nextstate <= 6'd14;
6'd14: begin
if(ef == 1'b1)
nextstate <= 6'd3;
else
nextstate <= 6'd15;
end
/* The Itoh Tsujii States */
6'd15: nextstate <= 6'd16;
6'd16: nextstate <= 6'd17;
6'd17: nextstate <= 6'd18;
6'd18: nextstate <= 6'd19;
6'd19: nextstate <= 6'd20;
6'd20: nextstate <= 6'd21;
6'd21: nextstate <= 6'd22;
6'd22: nextstate <= 6'd23;
6'd23: nextstate <= 6'd24;
6'd24: nextstate <= 6'd25;
6'd25: nextstate <= 6'd26;
6'd26: nextstate <= 6'd27;
6'd27: nextstate <= 6'd28;
6'd28: nextstate <= 6'd29;
6'd29: nextstate <= 6'd30;
6'd30: nextstate <= 6'd31;
6'd31: nextstate <= 6'd32;
6'd32: nextstate <= 6'd33;
6'd33: nextstate <= 6'd34;
6'd34: nextstate <= 6'd35;
6'd35: nextstate <= 6'd36;
6'd36: nextstate <= 6'd37;
6'd37: nextstate <= 6'd38;
6'd38: nextstate <= 6'd38;
default: nextstate <= 6'bx;
endcase
end
/* FSM */
always @(posedge clk) begin
if(nrst == 1'b0)
state <= 6'd0;
else if(start == 1'b0)
state <= 6'd1;
else
state <= nextstate;
end
/* Output Logic */
always @(state) begin
case(state)
6'd0: begin
cwl <= 10'h000; /* Init L2R Step 1 */
cwh <= 23'h4x8484;
end
6'd1: begin
cwl <= 10'h000;
cwh <= 23'h4x808D; /* Init L2R Step 2 */
end
6'd2: begin
cwl <= 10'hx; /* Init L2R Step 3 */
cwh <= 23'h4xx098;
end
/* The Doubling*/
6'd3: begin /* Double Step 1 */
cwl <= 10'h209;
cwh <= 23'h0x8490;
end
6'd4: begin /* Double Step 1a */
cwl <= 10'h002;
cwh <= 23'h0x20F0;
end
6'd5: begin /* Double Step 2 */
cwl <= 10'h324;
cwh <= 23'h0x6544;
end
6'd6: begin /* Double Step 3 */
cwl <= 10'hxC0;
cwh <= 23'h0x0ac0;
end
/* The Addition States */
6'd7: begin /* Addition Step 1 */
cwl <= 10'h048;
cwh <= 23'h0x08a0;
end
6'd8: begin /* Addition Step 2 */
cwl <= 10'h002;
cwh <= 23'h0x5006;
end
6'd9: begin /* Addition Step 3 */
cwl <= 10'h028;
cwh <= 23'h0x0090;
end
6'd10: begin /* Addition Step 4 */
cwl <= 10'h011;
cwh <= 23'h0x0214;
end
6'd11: begin /* Addition Step 5 */
cwl <= 10'h102;
cwh <= 23'h0x6544;
end
6'd12: begin /* Addition Step 6 */
cwl <= 10'h08A;
cwh <= 23'h0xB4D2;
end
6'd13: begin /* Addition Step 7 */
cwl <= 10'h00B;
cwh <= 23'h0x18A2;
end
6'd14: begin /* Addition Step 8 */
cwl <= 10'h058;
cwh <= 23'h0x0ac0;
end
/* The final Inverse : Starting the Itoh Tsujii here*/
6'd15: begin /* Inv 1 */
cwl <= 10'hx0D;
cwh <= 23'h0x04x0; /* The first a=a^3 */
end
6'd16: begin /* Inv 2 */
cwl <= 10'hx06;
cwh <= 23'h0x0090;
end
6'd17: begin /* Inv 3 */
cwl <= 10'hx35;
cwh <= 23'h0x0090;
end
6'd18: begin /* Inv 4-1 */
cwl <= 10'hx;
cwh <= 23'h130510;
end
6'd19: begin /* Inv 4-2 */
cwl <= 10'hx02;
cwh <= 23'h0x0190;
end
6'd20: begin /* Inv 5 */
cwl <= 10'hx35;
cwh <= 23'h0x0090;
end
6'd21: begin /* Inv 6-1 */
cwl <= 10'hx;
cwh <= 23'h170510;
end
6'd22: begin /* Inv 6-2 */
cwl <= 10'hx02;
cwh <= 23'h0x0190;
end
6'd23: begin /* Inv 7-1 */
cwl <= 10'hx;
cwh <= 23'h1E0510;
end
6'd24: begin /* Inv 7-2 */
cwl <= 10'hx02;
cwh <= 23'h0x0190;
end
6'd25: begin /* Inv 8 */
cwl <= 10'hx35;
cwh <= 23'h0x0090;
end
6'd26: begin /* Inv 9-1 */
cwl <= 10'hx;
cwh <= 23'h1E0510;
end
6'd27: begin /* Inv 9-2 */
cwl <= 10'hx;
cwh <= 23'h3E0500;
end
6'd28: begin
cwl <= 10'hx3A; /* Inv 9-3 */
cwh <= 23'h0x0190;
end
6'd29: begin /* Inv 10-1 */
cwl <= 10'hx;
cwh <= 23'h1E0510;
end
6'd30: begin /* Inv 10-2 */
cwl <= 10'hx;
cwh <= 23'h3E0500;
end
6'd31: begin /* Inv 10-3 */
cwl <= 10'hx;
cwh <= 23'h3E0500;
end
6'd32: begin /* Inv 10-4 */
cwl <= 10'hx;
cwh <= 23'h3E0500;
end
6'd33: begin /* Inv 10-5 */
cwl <= 10'hx;
cwh <= 23'h320500;
end
6'd34: begin /* Inv 10-6 */
cwl <= 10'hx02;
cwh <= 23'h0x0190;
end
6'd35: begin /* Final Square */
cwl <= 10'hx8x;
cwh <= 23'h0x2440;
end
6'd36: begin /* Convert to affine (x/z) */
cwl <= 10'hx00;
cwh <= 23'h0x0004;
end
6'd37: begin /* Convert to affine (x/z^2) */
cwl <= 10'hx08;
cwh <= 23'h0x0880;
end
6'd38: begin /* Completion State */
cwl <= 10'hx;
cwh <= 23'h0x0000;
end
default: begin
cwl <= 10'bx;
cwh <= 23'hx;
end
endcase
end
/* Shift register for the key. The current bit is always the MSB */
always @(posedge clk) begin
if (nrst == 1'b0)
k <= key;
else if (start == 1'b0) /* if start=0, shift every clock cycle */
k[`KEYMSB:0] <= {k[(`KEYMSB-1):0], 1'b0};
else if (state == 6'd4) /* if start=1, shift once very iteration of multiplier */
k[`KEYMSB:0] <= {k[(`KEYMSB-1):0], 1'b0};
else /* else, don't shift */
k[`KEYMSB:0] <= k[`KEYMSB:0];
end
/* Detect the first 1 */
assign tstart = start;
/* The counter clock is either a fast clock (clk) used during
* leading 1 detection, or a slow clock used during multiplication
*/
assign mainclk = (start == 1'b0) ? clk : cck;
always @(posedge clk) begin
if (nrst == 1'b0)
start <= key[`KEYMSB];
else
start <= tstart | k[(`KEYMSB - 1)];
end
/* Generate clock signal for counter */
always @(posedge clk) begin
if (nrst == 1'b0) begin
cck <= 1'b0;
end
else begin
case(state)
6'd3: cck <= ~cck;
6'd4: cck <= ~cck;
default: cck <= cck;
endcase
end
end
endmodule
`endif
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("f32.reinterpret-i32.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("f32.reinterpret-i32_tb.vcd");
$dumpvars(0, cpu_tb);
#30
`assert(result, 32'hc0000000);
`assert(result_type, `f32);
`assert(result_empty, 0);
$finish;
end
endmodule
|
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
// CREATED "Wed Nov 06 13:54:26 2013"
module HalfAdder(
A,
Cin,
Cout,
Sum
);
input wire A;
input wire Cin;
output wire Cout;
output wire Sum;
assign Cout = A & Cin;
assign Sum = A ^ Cin;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 14:41:49 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_system_ila_0_0_stub.v
// Design : zqynq_lab_1_design_system_ila_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "bd_1a88,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0]" */;
input clk;
input [0:0]probe0;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: in_arb_regs.v 5077 2009-02-22 20:17:46Z grg $
//
// Module: in_arb_regs.v
// Project: NF2.1
// Description: Demultiplexes, stores and serves register requests
//
///////////////////////////////////////////////////////////////////////////////
////include "NF_2.1_defines.v"
////include "reg_defines_reference_router.v"
////include "registers.v"
module in_arb_regs
#( parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2
)
(
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
input state,
input out_wr,
input [CTRL_WIDTH-1:0] out_ctrl,
input [DATA_WIDTH-1:0] out_data,
input out_rdy,
input eop,
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
localparam NUM_REGS_USED = 8; /* don't forget to update this when adding regs */
localparam ADDR_WIDTH = log2(NUM_REGS_USED);
// ------------- Wires/reg ------------------
wire [ADDR_WIDTH-1:0] addr;
wire [`IN_ARB_REG_ADDR_WIDTH - 1:0] reg_addr;
wire [((`UDP_REG_ADDR_WIDTH-`IN_ARB_REG_ADDR_WIDTH) - 1):0] tag_addr;
wire addr_good;
wire tag_hit;
reg in_pkt;
reg second_word;
reg state_latched;
reg out_rdy_latched;
reg [CTRL_WIDTH-1:0] last_pkt_ctrl_0;
reg [DATA_WIDTH-1:0] last_pkt_data_0;
reg [CTRL_WIDTH-1:0] last_pkt_ctrl_1;
reg [DATA_WIDTH-1:0] last_pkt_data_1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] eop_cnt;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data;
wire first_word;
// -------------- Logic --------------------
assign addr = reg_addr_in[ADDR_WIDTH-1:0];
assign reg_addr = reg_addr_in[`IN_ARB_REG_ADDR_WIDTH-1:0];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`IN_ARB_REG_ADDR_WIDTH];
assign addr_good = reg_addr[`IN_ARB_REG_ADDR_WIDTH-1:ADDR_WIDTH] == 'h0 &&
addr < NUM_REGS_USED;
assign tag_hit = tag_addr == `IN_ARB_BLOCK_ADDR;
// Record the various inputs for later output
always @(posedge clk)
begin
// EOP -- resets on read (or write)
if (reset || (reg_req_in && tag_hit && addr == `IN_ARB_NUM_PKTS_SENT))
eop_cnt <= 'h0;
else if (eop)
eop_cnt <= eop_cnt + 'h1;
if (reset) begin
state_latched <= 0;
out_rdy_latched <= 0;
last_pkt_ctrl_0 <= 'h0;
last_pkt_data_0 <= 'h0;
last_pkt_ctrl_1 <= 'h0;
last_pkt_data_1 <= 'h0;
end
else begin
state_latched <= state;
out_rdy_latched <= out_rdy;
if (first_word && out_wr) begin
last_pkt_ctrl_0 <= out_ctrl;
last_pkt_data_0 <= out_data;
end
if (second_word && out_wr) begin
last_pkt_ctrl_1 <= out_ctrl;
last_pkt_data_1 <= out_data;
end
end // else: !if(reset)
end // always @ (posedge clk)
// Location tracking
assign first_word = !in_pkt && !(|out_ctrl);
always @(posedge clk)
begin
if (reset) begin
in_pkt <= 0;
second_word <= 0;
end
else begin
if (first_word && out_wr)
in_pkt <= 1'b1;
else if (in_pkt && |out_ctrl && out_wr)
in_pkt <= 1'b0;
if(first_word && out_wr) begin
second_word <= 1;
end
else if(second_word==1 && out_wr) begin
second_word <= 0;
end
end
end
// Select the register data for output
always @*
begin
if (reset) begin
reg_data = 'h0;
end
else begin
case (addr)
`IN_ARB_NUM_PKTS_SENT: reg_data = eop_cnt;
`IN_ARB_STATE: reg_data = {{(`CPCI_NF2_DATA_WIDTH-2){1'b0}}, out_rdy_latched, state_latched};
`IN_ARB_LAST_PKT_WORD_0_LO: reg_data = last_pkt_data_0[31:0];
`IN_ARB_LAST_PKT_WORD_0_HI: reg_data = last_pkt_data_0[63:32];
`IN_ARB_LAST_PKT_CTRL_0: reg_data = last_pkt_ctrl_0;
`IN_ARB_LAST_PKT_WORD_1_LO: reg_data = last_pkt_data_1[31:0];
`IN_ARB_LAST_PKT_WORD_1_HI: reg_data = last_pkt_data_1[63:32];
`IN_ARB_LAST_PKT_CTRL_1: reg_data = last_pkt_ctrl_1;
endcase // case (reg_cnt)
end
end
// Register I/O
always @(posedge clk) begin
// Never modify the address/src
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_src_out <= reg_src_in;
if( reset ) begin
reg_req_out <= 1'b0;
reg_ack_out <= 1'b0;
reg_data_out <= 'h0;
end
else begin
if(reg_req_in && tag_hit) begin
if(addr_good) begin
reg_data_out <= reg_data;
end
else begin
reg_data_out <= 32'hdead_beef;
end
// requests complete after one cycle
reg_ack_out <= 1'b1;
end
else begin
reg_ack_out <= reg_ack_in;
reg_data_out <= reg_data_in;
end
reg_req_out <= reg_req_in;
end // else: !if( reset )
end // always @ (posedge clk)
endmodule // in_arb_regs
|
/*
Copyright (C) 2016 [email protected]
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//-------------------------------------------------------------------------
// https://github.com/balanx/laotzu
//
// Description : asynchronous stream fifo controller
//
// Attention :
// 1) FIFODEPTH should be even number.
// 2) Frame duration of write-side (include idle)
// should be at least 6 clock periods of read-side.
//
//-------------------------------------------------------------------------
// History :
// 10/15/2016
// initial draft
//
//-------------------------------------------------------------------------
module stream_asyn_fifo_controller #(
parameter FWFTEN = 1, // 0 : disable
parameter ADDRWIDTH = 6,
parameter [ADDRWIDTH:0] FIFODEPTH = 44, // should be even number.
parameter [ADDRWIDTH:0] HEADSIZE = 0
) (
// write-side
input w_rst_n ,
input w_clk ,
input [2:0] w_ctrl , // 0: nop, 1: write, ...
output w_full ,
output w_error ,
output [ADDRWIDTH:0] w_counter ,
// read-side
input r_rst_n ,
input r_clk ,
input r_en ,
output r_valid ,
output r_error ,
output [ADDRWIDTH:0] r_counter ,
// interface to ram
output [ADDRWIDTH-1:0] w_ram_addr ,
output w_ram_en ,
output [ADDRWIDTH-1:0] r_ram_addr ,
output r_ram_en
);
localparam [ADDRWIDTH:0] MINBIN2 = (1'b1<<ADDRWIDTH) - FIFODEPTH;
localparam [ADDRWIDTH:0] MINGRAY2 = (MINBIN2>>1) ^ MINBIN2;
localparam [ADDRWIDTH:0] MAXBIN2 = (1'b1<<ADDRWIDTH) + FIFODEPTH - 1'b1;
wire [ADDRWIDTH:0] w2r_ptr ;
wire [ADDRWIDTH:0] r2w_ptr ;
wire [ADDRWIDTH:0] rptr ;
wire [ADDRWIDTH:0] wptr ;
stream_asyn_fifo_write #(
.ADDRWIDTH ( ADDRWIDTH ),
.FIFODEPTH ( FIFODEPTH ),
.HEADSIZE ( HEADSIZE ),
.MINBIN2 ( MINBIN2 ),
.MAXBIN2 ( MAXBIN2 )
) write_inst (
.w_clk ( w_clk ),
.w_rst_n ( w_rst_n ),
.w_ctrl ( w_ctrl ),
.r2w_ptr ( r2w_ptr ),
.wbin ( w_ram_addr ),
.wptr ( wptr ),
.inc ( w_ram_en ),
.w_full ( w_full ),
.w_error ( w_error ),
.w_counter ( w_counter )
);
LTZ_CDCF #(
.WIDTH ( ADDRWIDTH + 1 ),
.INITVAL ( MINBIN2 )
) w2r_inst (
.rst_n ( r_rst_n ), // I
.clk ( r_clk ), // I
.din ( wptr ), // I [WIDTH -1:0]
.dout ( w2r_ptr ) // O [WIDTH -1:0]
); // instantiation of LTZ_CDCB
stream_asyn_fifo_read #(
.FWFTEN ( FWFTEN ),
.ADDRWIDTH ( ADDRWIDTH ),
.FIFODEPTH ( FIFODEPTH ),
.MINBIN2 ( MINBIN2 ),
.MAXBIN2 ( MAXBIN2 )
) read_inst (
.r_clk ( r_clk ),
.r_rst_n ( r_rst_n ),
.r_en ( r_en ),
.w2r_ptr ( w2r_ptr ),
.rbin ( r_ram_addr ),
.rptr ( rptr ),
.inc ( r_ram_en ),
.r_valid ( r_valid ),
.r_error ( r_error ),
.r_counter ( r_counter )
);
LTZ_CDCB #(
.WIDTH ( ADDRWIDTH + 1 ),
.INITVAL ( MINGRAY2 )
) r2w_inst (
.rst_n ( w_rst_n ), // I
.clk ( w_clk ), // I
.din ( rptr ), // I [WIDTH -1:0]
.dout ( r2w_ptr ) // O [WIDTH -1:0]
); // instantiation of LTZ_CDCB
//
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_TB_V
`define SKY130_FD_SC_LP__A211OI_TB_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__a211oi dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_TB_V
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.