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/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:30:25 2016
/////////////////////////////////////////////////////////////
module RegisterAdd_W32_1 ( clk, rst, load, D, Q );
input [31:0] D;
output [31:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n65, n97, n84, n85, n86, n87, n88, n89, n90,
n91, n92, n93;
DFFRX2TS \Q_reg[31] ( .D(n65), .CK(clk), .RN(n84), .Q(Q[31]), .QN(n32) );
DFFRX2TS \Q_reg[29] ( .D(n62), .CK(clk), .RN(n84), .Q(Q[29]), .QN(n30) );
DFFRX2TS \Q_reg[26] ( .D(n59), .CK(clk), .RN(n84), .Q(Q[26]), .QN(n27) );
DFFRX2TS \Q_reg[30] ( .D(n63), .CK(clk), .RN(n84), .Q(Q[30]), .QN(n31) );
DFFRX2TS \Q_reg[28] ( .D(n61), .CK(clk), .RN(n84), .Q(Q[28]), .QN(n29) );
DFFRX2TS \Q_reg[27] ( .D(n60), .CK(clk), .RN(n84), .Q(Q[27]), .QN(n28) );
DFFRX2TS \Q_reg[25] ( .D(n58), .CK(clk), .RN(n84), .Q(Q[25]), .QN(n26) );
DFFRX2TS \Q_reg[24] ( .D(n57), .CK(clk), .RN(n84), .Q(Q[24]), .QN(n25) );
DFFRX2TS \Q_reg[23] ( .D(n56), .CK(clk), .RN(n84), .Q(Q[23]), .QN(n24) );
DFFRX2TS \Q_reg[19] ( .D(n52), .CK(clk), .RN(n85), .Q(Q[19]), .QN(n20) );
DFFRX2TS \Q_reg[17] ( .D(n50), .CK(clk), .RN(n85), .Q(Q[17]), .QN(n18) );
DFFRX2TS \Q_reg[22] ( .D(n55), .CK(clk), .RN(n84), .Q(Q[22]), .QN(n23) );
DFFRX2TS \Q_reg[21] ( .D(n54), .CK(clk), .RN(n85), .Q(Q[21]), .QN(n22) );
DFFRX2TS \Q_reg[20] ( .D(n53), .CK(clk), .RN(n85), .Q(Q[20]), .QN(n21) );
DFFRX2TS \Q_reg[18] ( .D(n51), .CK(clk), .RN(n85), .Q(Q[18]), .QN(n19) );
DFFRX2TS \Q_reg[16] ( .D(n49), .CK(clk), .RN(n85), .Q(Q[16]), .QN(n17) );
DFFRX2TS \Q_reg[15] ( .D(n48), .CK(clk), .RN(n85), .Q(Q[15]), .QN(n16) );
DFFRX2TS \Q_reg[13] ( .D(n46), .CK(clk), .RN(n85), .Q(Q[13]), .QN(n14) );
DFFRX2TS \Q_reg[11] ( .D(n44), .CK(clk), .RN(n86), .Q(Q[11]), .QN(n12) );
DFFRX2TS \Q_reg[4] ( .D(n37), .CK(clk), .RN(n86), .Q(Q[4]), .QN(n5) );
DFFRX2TS \Q_reg[6] ( .D(n39), .CK(clk), .RN(n86), .Q(Q[6]), .QN(n7) );
DFFRX2TS \Q_reg[3] ( .D(n36), .CK(clk), .RN(n86), .Q(Q[3]), .QN(n4) );
DFFRX2TS \Q_reg[14] ( .D(n47), .CK(clk), .RN(n85), .Q(Q[14]), .QN(n15) );
DFFRX2TS \Q_reg[12] ( .D(n45), .CK(clk), .RN(n85), .Q(Q[12]), .QN(n13) );
DFFRX2TS \Q_reg[7] ( .D(n40), .CK(clk), .RN(n86), .Q(Q[7]), .QN(n8) );
DFFRX2TS \Q_reg[5] ( .D(n38), .CK(clk), .RN(n86), .Q(Q[5]), .QN(n6) );
DFFRX2TS \Q_reg[9] ( .D(n42), .CK(clk), .RN(n86), .Q(Q[9]), .QN(n10) );
DFFRX2TS \Q_reg[8] ( .D(n41), .CK(clk), .RN(n86), .Q(Q[8]), .QN(n9) );
DFFRX2TS \Q_reg[2] ( .D(n35), .CK(clk), .RN(n86), .Q(Q[2]), .QN(n3) );
DFFRX2TS \Q_reg[1] ( .D(n34), .CK(clk), .RN(n97), .Q(Q[1]), .QN(n2) );
DFFRX2TS \Q_reg[0] ( .D(n33), .CK(clk), .RN(n97), .Q(Q[0]), .QN(n1) );
DFFRX2TS \Q_reg[10] ( .D(n43), .CK(clk), .RN(n86), .Q(Q[10]), .QN(n11) );
CLKBUFX2TS U2 ( .A(n92), .Y(n87) );
CLKBUFX2TS U3 ( .A(n93), .Y(n88) );
CLKBUFX2TS U4 ( .A(n91), .Y(n89) );
CLKBUFX2TS U5 ( .A(n91), .Y(n90) );
CLKBUFX2TS U6 ( .A(n97), .Y(n86) );
CLKBUFX2TS U7 ( .A(n97), .Y(n85) );
CLKBUFX2TS U8 ( .A(n97), .Y(n84) );
OAI2BB2XLTS U9 ( .B0(n1), .B1(n90), .A0N(D[0]), .A1N(n90), .Y(n33) );
OAI2BB2XLTS U10 ( .B0(n2), .B1(n87), .A0N(D[1]), .A1N(n90), .Y(n34) );
OAI2BB2XLTS U11 ( .B0(n3), .B1(n90), .A0N(D[2]), .A1N(n89), .Y(n35) );
OAI2BB2XLTS U12 ( .B0(n4), .B1(n87), .A0N(D[3]), .A1N(n89), .Y(n36) );
OAI2BB2XLTS U13 ( .B0(n5), .B1(n87), .A0N(D[4]), .A1N(n89), .Y(n37) );
OAI2BB2XLTS U14 ( .B0(n6), .B1(n87), .A0N(D[5]), .A1N(n88), .Y(n38) );
OAI2BB2XLTS U15 ( .B0(n7), .B1(n87), .A0N(D[6]), .A1N(n88), .Y(n39) );
OAI2BB2XLTS U16 ( .B0(n8), .B1(n87), .A0N(D[7]), .A1N(n88), .Y(n40) );
OAI2BB2XLTS U17 ( .B0(n9), .B1(n87), .A0N(D[8]), .A1N(n90), .Y(n41) );
OAI2BB2XLTS U18 ( .B0(n10), .B1(n87), .A0N(D[9]), .A1N(n88), .Y(n42) );
OAI2BB2XLTS U19 ( .B0(n11), .B1(n87), .A0N(D[10]), .A1N(n90), .Y(n43) );
OAI2BB2XLTS U20 ( .B0(n12), .B1(n91), .A0N(D[11]), .A1N(n91), .Y(n44) );
OAI2BB2XLTS U21 ( .B0(n13), .B1(n92), .A0N(D[12]), .A1N(n91), .Y(n45) );
OAI2BB2XLTS U22 ( .B0(n14), .B1(n91), .A0N(D[13]), .A1N(n91), .Y(n46) );
OAI2BB2XLTS U23 ( .B0(n15), .B1(n92), .A0N(D[14]), .A1N(load), .Y(n47) );
OAI2BB2XLTS U24 ( .B0(n16), .B1(n87), .A0N(D[15]), .A1N(n88), .Y(n48) );
OAI2BB2XLTS U25 ( .B0(n17), .B1(n92), .A0N(D[16]), .A1N(n91), .Y(n49) );
OAI2BB2XLTS U26 ( .B0(n18), .B1(n91), .A0N(D[17]), .A1N(n91), .Y(n50) );
OAI2BB2XLTS U27 ( .B0(n19), .B1(n92), .A0N(D[18]), .A1N(n88), .Y(n51) );
OAI2BB2XLTS U28 ( .B0(n20), .B1(n92), .A0N(D[19]), .A1N(n88), .Y(n52) );
OAI2BB2XLTS U29 ( .B0(n21), .B1(n92), .A0N(D[20]), .A1N(n88), .Y(n53) );
OAI2BB2XLTS U30 ( .B0(n22), .B1(n93), .A0N(D[21]), .A1N(n89), .Y(n54) );
OAI2BB2XLTS U31 ( .B0(n23), .B1(n93), .A0N(D[22]), .A1N(n88), .Y(n55) );
OAI2BB2XLTS U32 ( .B0(n24), .B1(n93), .A0N(D[23]), .A1N(n88), .Y(n56) );
OAI2BB2XLTS U33 ( .B0(n25), .B1(n93), .A0N(D[24]), .A1N(n89), .Y(n57) );
OAI2BB2XLTS U34 ( .B0(n26), .B1(n93), .A0N(D[25]), .A1N(n89), .Y(n58) );
OAI2BB2XLTS U35 ( .B0(n27), .B1(n93), .A0N(D[26]), .A1N(n89), .Y(n59) );
OAI2BB2XLTS U36 ( .B0(n28), .B1(n93), .A0N(D[27]), .A1N(n89), .Y(n60) );
OAI2BB2XLTS U37 ( .B0(n29), .B1(n93), .A0N(D[28]), .A1N(n89), .Y(n61) );
OAI2BB2XLTS U38 ( .B0(n30), .B1(n92), .A0N(D[29]), .A1N(n89), .Y(n62) );
OAI2BB2XLTS U39 ( .B0(n31), .B1(n93), .A0N(D[30]), .A1N(n90), .Y(n63) );
OAI2BB2XLTS U40 ( .B0(n32), .B1(n92), .A0N(n90), .A1N(D[31]), .Y(n65) );
CLKBUFX2TS U41 ( .A(load), .Y(n91) );
CLKBUFX2TS U42 ( .A(load), .Y(n92) );
CLKBUFX2TS U43 ( .A(load), .Y(n93) );
INVX2TS U44 ( .A(rst), .Y(n97) );
endmodule
module RegisterAdd_W1_1 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4, n2;
DFFRX2TS \Q_reg[0] ( .D(n3), .CK(clk), .RN(n2), .Q(Q[0]), .QN(n4) );
OAI2BB2XLTS U2 ( .B0(n4), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
INVX2TS U3 ( .A(rst), .Y(n2) );
endmodule
module Comparator_W31 ( Data_X_i, Data_Y_i, gtXY_o, eqXY_o );
input [30:0] Data_X_i;
input [30:0] Data_Y_i;
output gtXY_o, eqXY_o;
wire N0, N1, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14,
n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28,
n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42,
n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56,
n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70,
n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84,
n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98,
n99, n100, n101, n102, n103;
assign gtXY_o = N0;
assign eqXY_o = N1;
XOR2X1TS U1 ( .A(Data_X_i[2]), .B(n31), .Y(n56) );
XOR2X1TS U2 ( .A(Data_X_i[7]), .B(Data_Y_i[7]), .Y(n59) );
XOR2X1TS U3 ( .A(Data_X_i[16]), .B(Data_Y_i[16]), .Y(n58) );
XOR2X1TS U4 ( .A(Data_X_i[18]), .B(Data_Y_i[18]), .Y(n57) );
NOR4BBX1TS U5 ( .AN(n68), .BN(n64), .C(n67), .D(n70), .Y(n39) );
NOR3BX1TS U6 ( .AN(n51), .B(n52), .C(n53), .Y(n50) );
NAND3X1TS U7 ( .A(n54), .B(n55), .C(n56), .Y(n52) );
NOR3X1TS U8 ( .A(n57), .B(n58), .C(n59), .Y(n49) );
NOR2BX1TS U9 ( .AN(n45), .B(n46), .Y(n43) );
NOR3X1TS U10 ( .A(n32), .B(n33), .C(n34), .Y(N1) );
NAND4BX1TS U11 ( .AN(n41), .B(n42), .C(n43), .D(n44), .Y(n33) );
NAND4BBX1TS U12 ( .AN(n47), .BN(n48), .C(n49), .D(n50), .Y(n32) );
NAND4BBX1TS U13 ( .AN(n35), .BN(n36), .C(n37), .D(n38), .Y(n34) );
XNOR2X1TS U14 ( .A(Data_X_i[9]), .B(Data_Y_i[9]), .Y(n93) );
XNOR2X1TS U15 ( .A(n18), .B(Data_Y_i[1]), .Y(n41) );
OAI22X1TS U16 ( .A0(Data_Y_i[12]), .A1(n13), .B0(n87), .B1(n88), .Y(n86) );
INVX2TS U17 ( .A(Data_X_i[12]), .Y(n13) );
AOI22X1TS U18 ( .A0(n89), .A1(n90), .B0(Data_X_i[11]), .B1(n26), .Y(n87) );
INVX2TS U19 ( .A(Data_Y_i[11]), .Y(n26) );
OAI22X1TS U20 ( .A0(Data_Y_i[10]), .A1(n14), .B0(n91), .B1(n92), .Y(n90) );
INVX2TS U21 ( .A(Data_X_i[10]), .Y(n14) );
AOI32X1TS U22 ( .A0(Data_X_i[8]), .A1(n28), .A2(n93), .B0(Data_X_i[9]), .B1(
n27), .Y(n91) );
INVX2TS U23 ( .A(Data_Y_i[9]), .Y(n27) );
OAI22X1TS U24 ( .A0(Data_Y_i[30]), .A1(n1), .B0(n60), .B1(n47), .Y(N0) );
AOI22X1TS U25 ( .A0(n55), .A1(n61), .B0(Data_X_i[29]), .B1(n20), .Y(n60) );
OAI21X1TS U26 ( .A0(Data_Y_i[28]), .A1(n2), .B0(n62), .Y(n61) );
AOI32X1TS U27 ( .A0(n54), .A1(n63), .A2(n39), .B0(n64), .B1(n65), .Y(n62) );
AOI22X1TS U28 ( .A0(n51), .A1(n97), .B0(Data_X_i[4]), .B1(n30), .Y(n96) );
INVX2TS U29 ( .A(Data_Y_i[4]), .Y(n30) );
OAI22X1TS U30 ( .A0(Data_Y_i[3]), .A1(n17), .B0(n98), .B1(n35), .Y(n97) );
AOI22X1TS U31 ( .A0(n56), .A1(n99), .B0(Data_X_i[2]), .B1(n31), .Y(n98) );
AOI22X1TS U32 ( .A0(n44), .A1(n78), .B0(Data_X_i[17]), .B1(n23), .Y(n77) );
OAI22X1TS U33 ( .A0(Data_Y_i[16]), .A1(n11), .B0(n79), .B1(n58), .Y(n78) );
INVX2TS U34 ( .A(Data_X_i[16]), .Y(n11) );
AOI222XLTS U35 ( .A0(Data_X_i[15]), .A1(n24), .B0(n37), .B1(n80), .C0(n81),
.C1(n82), .Y(n79) );
OAI22X1TS U36 ( .A0(Data_Y_i[7]), .A1(n15), .B0(n94), .B1(n59), .Y(n80) );
INVX2TS U37 ( .A(Data_X_i[7]), .Y(n15) );
AOI22X1TS U38 ( .A0(n42), .A1(n95), .B0(Data_X_i[6]), .B1(n29), .Y(n94) );
OAI22X1TS U39 ( .A0(Data_Y_i[5]), .A1(n16), .B0(n96), .B1(n53), .Y(n95) );
OAI22X1TS U40 ( .A0(Data_Y_i[14]), .A1(n12), .B0(n83), .B1(n84), .Y(n82) );
INVX2TS U41 ( .A(Data_X_i[14]), .Y(n12) );
AOI22X1TS U42 ( .A0(n85), .A1(n86), .B0(Data_X_i[13]), .B1(n25), .Y(n83) );
INVX2TS U43 ( .A(Data_Y_i[13]), .Y(n25) );
OAI22X1TS U44 ( .A0(Data_Y_i[23]), .A1(n6), .B0(n71), .B1(n48), .Y(n63) );
NOR2X1TS U45 ( .A(n72), .B(n73), .Y(n71) );
OAI32X1TS U46 ( .A0(n74), .A1(Data_Y_i[21]), .A2(n8), .B0(Data_Y_i[22]),
.B1(n7), .Y(n73) );
OAI33XLTS U47 ( .A0(n36), .A1(Data_Y_i[20]), .A2(n9), .B0(n36), .B1(n75),
.B2(n46), .Y(n72) );
AOI22X1TS U48 ( .A0(n45), .A1(n76), .B0(Data_X_i[19]), .B1(n22), .Y(n75) );
INVX2TS U49 ( .A(Data_Y_i[19]), .Y(n22) );
OAI22X1TS U50 ( .A0(Data_Y_i[18]), .A1(n10), .B0(n77), .B1(n57), .Y(n76) );
INVX2TS U51 ( .A(Data_X_i[18]), .Y(n10) );
XOR2X1TS U52 ( .A(Data_X_i[10]), .B(Data_Y_i[10]), .Y(n92) );
OAI32X1TS U53 ( .A0(n41), .A1(Data_Y_i[0]), .A2(n19), .B0(Data_Y_i[1]), .B1(
n18), .Y(n99) );
INVX2TS U54 ( .A(Data_X_i[0]), .Y(n19) );
INVX2TS U55 ( .A(Data_Y_i[2]), .Y(n31) );
INVX2TS U56 ( .A(Data_X_i[1]), .Y(n18) );
INVX2TS U57 ( .A(Data_Y_i[8]), .Y(n28) );
XNOR2X1TS U58 ( .A(Data_X_i[11]), .B(Data_Y_i[11]), .Y(n89) );
XNOR2X1TS U59 ( .A(Data_X_i[13]), .B(Data_Y_i[13]), .Y(n85) );
XNOR2X1TS U60 ( .A(Data_X_i[4]), .B(Data_Y_i[4]), .Y(n51) );
XNOR2X1TS U61 ( .A(n17), .B(Data_Y_i[3]), .Y(n35) );
XNOR2X1TS U62 ( .A(Data_X_i[15]), .B(Data_Y_i[15]), .Y(n81) );
NOR2BX1TS U63 ( .AN(n100), .B(n101), .Y(n37) );
NAND4BX1TS U64 ( .AN(n102), .B(n85), .C(n89), .D(n93), .Y(n101) );
NOR4BX1TS U65 ( .AN(n81), .B(n92), .C(n88), .D(n84), .Y(n100) );
XOR2X1TS U66 ( .A(Data_Y_i[8]), .B(Data_X_i[8]), .Y(n102) );
XOR2X1TS U67 ( .A(Data_X_i[14]), .B(Data_Y_i[14]), .Y(n84) );
XOR2X1TS U68 ( .A(Data_X_i[12]), .B(Data_Y_i[12]), .Y(n88) );
XOR2X1TS U69 ( .A(Data_X_i[6]), .B(n29), .Y(n42) );
XOR2X1TS U70 ( .A(Data_X_i[5]), .B(Data_Y_i[5]), .Y(n53) );
INVX2TS U71 ( .A(Data_Y_i[6]), .Y(n29) );
INVX2TS U72 ( .A(Data_X_i[3]), .Y(n17) );
INVX2TS U73 ( .A(Data_X_i[5]), .Y(n16) );
XNOR2X1TS U74 ( .A(Data_X_i[19]), .B(Data_Y_i[19]), .Y(n45) );
XNOR2X1TS U75 ( .A(n7), .B(Data_Y_i[22]), .Y(n74) );
XOR2X1TS U76 ( .A(Data_X_i[17]), .B(n23), .Y(n44) );
XOR2X1TS U77 ( .A(Data_X_i[20]), .B(Data_Y_i[20]), .Y(n46) );
NAND2BX1TS U78 ( .AN(n74), .B(n103), .Y(n36) );
XOR2X1TS U79 ( .A(n8), .B(Data_Y_i[21]), .Y(n103) );
INVX2TS U80 ( .A(Data_Y_i[17]), .Y(n23) );
INVX2TS U81 ( .A(Data_X_i[21]), .Y(n8) );
INVX2TS U82 ( .A(Data_X_i[22]), .Y(n7) );
INVX2TS U83 ( .A(Data_Y_i[15]), .Y(n24) );
XNOR2X1TS U84 ( .A(n3), .B(Data_Y_i[27]), .Y(n67) );
XNOR2X1TS U85 ( .A(n4), .B(Data_Y_i[25]), .Y(n70) );
XNOR2X1TS U86 ( .A(n1), .B(Data_Y_i[30]), .Y(n47) );
XNOR2X1TS U87 ( .A(n6), .B(Data_Y_i[23]), .Y(n48) );
NOR2BX1TS U88 ( .AN(n39), .B(n40), .Y(n38) );
XOR2X1TS U89 ( .A(Data_Y_i[0]), .B(Data_X_i[0]), .Y(n40) );
OAI22X1TS U90 ( .A0(Data_Y_i[27]), .A1(n3), .B0(n66), .B1(n67), .Y(n65) );
AOI22X1TS U91 ( .A0(n68), .A1(n69), .B0(Data_X_i[26]), .B1(n21), .Y(n66) );
OAI32X1TS U92 ( .A0(n5), .A1(Data_Y_i[24]), .A2(n70), .B0(Data_Y_i[25]),
.B1(n4), .Y(n69) );
XOR2X1TS U93 ( .A(Data_X_i[29]), .B(n20), .Y(n55) );
XOR2X1TS U94 ( .A(n5), .B(Data_Y_i[24]), .Y(n54) );
XOR2X1TS U95 ( .A(Data_X_i[26]), .B(n21), .Y(n68) );
XOR2X1TS U96 ( .A(n2), .B(Data_Y_i[28]), .Y(n64) );
INVX2TS U97 ( .A(Data_X_i[28]), .Y(n2) );
INVX2TS U98 ( .A(Data_Y_i[26]), .Y(n21) );
INVX2TS U99 ( .A(Data_Y_i[29]), .Y(n20) );
INVX2TS U100 ( .A(Data_X_i[27]), .Y(n3) );
INVX2TS U101 ( .A(Data_X_i[23]), .Y(n6) );
INVX2TS U102 ( .A(Data_X_i[30]), .Y(n1) );
INVX2TS U103 ( .A(Data_X_i[24]), .Y(n5) );
INVX2TS U104 ( .A(Data_X_i[25]), .Y(n4) );
INVX2TS U105 ( .A(Data_X_i[20]), .Y(n9) );
endmodule
module xor_tri_W32 ( A_i, B_i, C_i, Z_o );
input A_i, B_i, C_i;
output Z_o;
wire n1;
XOR2X1TS U1 ( .A(A_i), .B(n1), .Y(Z_o) );
XOR2X1TS U2 ( .A(C_i), .B(B_i), .Y(n1) );
endmodule
module sgn_result ( Add_Subt_i, sgn_X_i, sgn_Y_i, gtXY_i, eqXY_i, sgn_result_o
);
input Add_Subt_i, sgn_X_i, sgn_Y_i, gtXY_i, eqXY_i;
output sgn_result_o;
wire n1, n2, n3;
OAI31X1TS U1 ( .A0(n2), .A1(gtXY_i), .A2(eqXY_i), .B0(n3), .Y(sgn_result_o)
);
OAI21X1TS U2 ( .A0(gtXY_i), .A1(n1), .B0(sgn_X_i), .Y(n3) );
INVX2TS U3 ( .A(n2), .Y(n1) );
XNOR2X1TS U4 ( .A(sgn_Y_i), .B(Add_Subt_i), .Y(n2) );
endmodule
module MultiplexTxT_W31 ( select, D0_i, D1_i, S0_o, S1_o );
input [30:0] D0_i;
input [30:0] D1_i;
output [30:0] S0_o;
output [30:0] S1_o;
input select;
wire n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90;
INVX2TS U1 ( .A(n83), .Y(n78) );
INVX2TS U2 ( .A(n87), .Y(n79) );
INVX2TS U3 ( .A(n88), .Y(n80) );
INVX2TS U4 ( .A(n90), .Y(n81) );
INVX2TS U5 ( .A(n90), .Y(n82) );
CLKBUFX2TS U6 ( .A(n88), .Y(n85) );
CLKBUFX2TS U7 ( .A(n89), .Y(n84) );
CLKBUFX2TS U8 ( .A(n88), .Y(n86) );
CLKBUFX2TS U9 ( .A(n89), .Y(n83) );
CLKBUFX2TS U10 ( .A(n90), .Y(n89) );
CLKBUFX2TS U11 ( .A(n90), .Y(n88) );
CLKBUFX2TS U12 ( .A(n90), .Y(n87) );
INVX2TS U13 ( .A(n77), .Y(n90) );
CLKBUFX2TS U14 ( .A(select), .Y(n77) );
OAI22X1TS U15 ( .A0(n86), .A1(n63), .B0(n80), .B1(n32), .Y(S1_o[0]) );
OAI22X1TS U16 ( .A0(n85), .A1(n62), .B0(n81), .B1(n31), .Y(S1_o[1]) );
OAI22X1TS U17 ( .A0(n83), .A1(n60), .B0(n82), .B1(n29), .Y(S1_o[3]) );
OAI22X1TS U18 ( .A0(n83), .A1(n59), .B0(n82), .B1(n28), .Y(S1_o[4]) );
OAI22X1TS U19 ( .A0(n83), .A1(n58), .B0(n82), .B1(n27), .Y(S1_o[5]) );
OAI22X1TS U20 ( .A0(n83), .A1(n56), .B0(n82), .B1(n25), .Y(S1_o[7]) );
OAI22X1TS U21 ( .A0(n54), .A1(n84), .B0(n77), .B1(n23), .Y(S1_o[9]) );
OAI22X1TS U22 ( .A0(n86), .A1(n53), .B0(n80), .B1(n22), .Y(S1_o[10]) );
OAI22X1TS U23 ( .A0(n86), .A1(n52), .B0(n80), .B1(n21), .Y(S1_o[11]) );
OAI22X1TS U24 ( .A0(n86), .A1(n51), .B0(n80), .B1(n20), .Y(S1_o[12]) );
OAI22X1TS U25 ( .A0(n86), .A1(n50), .B0(n80), .B1(n19), .Y(S1_o[13]) );
OAI22X1TS U26 ( .A0(n86), .A1(n49), .B0(n80), .B1(n18), .Y(S1_o[14]) );
OAI22X1TS U27 ( .A0(n85), .A1(n48), .B0(n80), .B1(n17), .Y(S1_o[15]) );
OAI22X1TS U28 ( .A0(n85), .A1(n47), .B0(n80), .B1(n16), .Y(S1_o[16]) );
OAI22X1TS U29 ( .A0(n85), .A1(n45), .B0(n81), .B1(n14), .Y(S1_o[18]) );
OAI22X1TS U30 ( .A0(n85), .A1(n44), .B0(n81), .B1(n13), .Y(S1_o[19]) );
OAI22X1TS U31 ( .A0(n85), .A1(n41), .B0(n81), .B1(n10), .Y(S1_o[22]) );
OAI22X1TS U32 ( .A0(n84), .A1(n40), .B0(n81), .B1(n9), .Y(S1_o[23]) );
OAI22X1TS U33 ( .A0(n84), .A1(n38), .B0(n81), .B1(n7), .Y(S1_o[25]) );
OAI22X1TS U34 ( .A0(n84), .A1(n36), .B0(n82), .B1(n5), .Y(S1_o[27]) );
OAI22X1TS U35 ( .A0(n84), .A1(n35), .B0(n82), .B1(n4), .Y(S1_o[28]) );
OAI22X1TS U36 ( .A0(n84), .A1(n33), .B0(n82), .B1(n2), .Y(S1_o[30]) );
OAI22X1TS U37 ( .A0(n78), .A1(n63), .B0(n86), .B1(n32), .Y(S0_o[0]) );
OAI22X1TS U38 ( .A0(n79), .A1(n62), .B0(n87), .B1(n31), .Y(S0_o[1]) );
OAI22X1TS U39 ( .A0(n77), .A1(n60), .B0(n87), .B1(n29), .Y(S0_o[3]) );
OAI22X1TS U40 ( .A0(n77), .A1(n59), .B0(n88), .B1(n28), .Y(S0_o[4]) );
OAI22X1TS U41 ( .A0(select), .A1(n58), .B0(n87), .B1(n27), .Y(S0_o[5]) );
OAI22X1TS U42 ( .A0(select), .A1(n56), .B0(n83), .B1(n25), .Y(S0_o[7]) );
OAI22X1TS U43 ( .A0(n80), .A1(n54), .B0(n23), .B1(n85), .Y(S0_o[9]) );
OAI22X1TS U44 ( .A0(n78), .A1(n53), .B0(n83), .B1(n22), .Y(S0_o[10]) );
OAI22X1TS U45 ( .A0(n78), .A1(n52), .B0(n90), .B1(n21), .Y(S0_o[11]) );
OAI22X1TS U46 ( .A0(n78), .A1(n51), .B0(n90), .B1(n20), .Y(S0_o[12]) );
OAI22X1TS U47 ( .A0(n78), .A1(n50), .B0(n90), .B1(n19), .Y(S0_o[13]) );
OAI22X1TS U48 ( .A0(n78), .A1(n49), .B0(n90), .B1(n18), .Y(S0_o[14]) );
OAI22X1TS U49 ( .A0(n78), .A1(n48), .B0(n86), .B1(n17), .Y(S0_o[15]) );
OAI22X1TS U50 ( .A0(n78), .A1(n47), .B0(n87), .B1(n16), .Y(S0_o[16]) );
OAI22X1TS U51 ( .A0(n78), .A1(n45), .B0(n86), .B1(n14), .Y(S0_o[18]) );
OAI22X1TS U52 ( .A0(n79), .A1(n44), .B0(n90), .B1(n13), .Y(S0_o[19]) );
OAI22X1TS U53 ( .A0(n79), .A1(n41), .B0(n87), .B1(n10), .Y(S0_o[22]) );
OAI22X1TS U54 ( .A0(n79), .A1(n40), .B0(n87), .B1(n9), .Y(S0_o[23]) );
OAI22X1TS U55 ( .A0(n79), .A1(n38), .B0(n87), .B1(n7), .Y(S0_o[25]) );
OAI22X1TS U56 ( .A0(n79), .A1(n36), .B0(n88), .B1(n5), .Y(S0_o[27]) );
OAI22X1TS U57 ( .A0(select), .A1(n35), .B0(n87), .B1(n4), .Y(S0_o[28]) );
OAI22X1TS U58 ( .A0(select), .A1(n33), .B0(n88), .B1(n2), .Y(S0_o[30]) );
OAI22X1TS U59 ( .A0(n83), .A1(n55), .B0(n77), .B1(n24), .Y(S1_o[8]) );
OAI22X1TS U60 ( .A0(select), .A1(n61), .B0(n89), .B1(n30), .Y(S0_o[2]) );
OAI22X1TS U61 ( .A0(select), .A1(n57), .B0(n87), .B1(n26), .Y(S0_o[6]) );
OAI22X1TS U62 ( .A0(n77), .A1(n55), .B0(n86), .B1(n24), .Y(S0_o[8]) );
OAI22X1TS U63 ( .A0(n78), .A1(n46), .B0(n89), .B1(n15), .Y(S0_o[17]) );
OAI22X1TS U64 ( .A0(n79), .A1(n43), .B0(n83), .B1(n12), .Y(S0_o[20]) );
OAI22X1TS U65 ( .A0(n79), .A1(n42), .B0(n89), .B1(n11), .Y(S0_o[21]) );
OAI22X1TS U66 ( .A0(n79), .A1(n39), .B0(n88), .B1(n8), .Y(S0_o[24]) );
OAI22X1TS U67 ( .A0(n79), .A1(n37), .B0(n89), .B1(n6), .Y(S0_o[26]) );
OAI22X1TS U68 ( .A0(select), .A1(n34), .B0(n88), .B1(n3), .Y(S0_o[29]) );
OAI22X1TS U69 ( .A0(n84), .A1(n61), .B0(n82), .B1(n30), .Y(S1_o[2]) );
OAI22X1TS U70 ( .A0(n83), .A1(n57), .B0(n82), .B1(n26), .Y(S1_o[6]) );
OAI22X1TS U71 ( .A0(n85), .A1(n46), .B0(n80), .B1(n15), .Y(S1_o[17]) );
OAI22X1TS U72 ( .A0(n85), .A1(n42), .B0(n81), .B1(n11), .Y(S1_o[21]) );
OAI22X1TS U73 ( .A0(n84), .A1(n39), .B0(n81), .B1(n8), .Y(S1_o[24]) );
OAI22X1TS U74 ( .A0(n84), .A1(n37), .B0(n81), .B1(n6), .Y(S1_o[26]) );
OAI22X1TS U75 ( .A0(n84), .A1(n34), .B0(n82), .B1(n3), .Y(S1_o[29]) );
OAI22X1TS U76 ( .A0(n85), .A1(n43), .B0(n81), .B1(n12), .Y(S1_o[20]) );
INVX2TS U77 ( .A(D1_i[8]), .Y(n55) );
INVX2TS U78 ( .A(D1_i[9]), .Y(n54) );
INVX2TS U79 ( .A(D1_i[4]), .Y(n59) );
INVX2TS U80 ( .A(D1_i[11]), .Y(n52) );
INVX2TS U81 ( .A(D1_i[13]), .Y(n50) );
INVX2TS U82 ( .A(D1_i[15]), .Y(n48) );
INVX2TS U83 ( .A(D1_i[19]), .Y(n44) );
INVX2TS U84 ( .A(D0_i[5]), .Y(n27) );
INVX2TS U85 ( .A(D0_i[7]), .Y(n25) );
INVX2TS U86 ( .A(D0_i[10]), .Y(n22) );
INVX2TS U87 ( .A(D0_i[12]), .Y(n20) );
INVX2TS U88 ( .A(D0_i[14]), .Y(n18) );
INVX2TS U89 ( .A(D0_i[16]), .Y(n16) );
INVX2TS U90 ( .A(D0_i[18]), .Y(n14) );
INVX2TS U91 ( .A(D0_i[20]), .Y(n12) );
INVX2TS U92 ( .A(D0_i[0]), .Y(n32) );
INVX2TS U93 ( .A(D1_i[2]), .Y(n61) );
INVX2TS U94 ( .A(D1_i[6]), .Y(n57) );
INVX2TS U95 ( .A(D1_i[17]), .Y(n46) );
INVX2TS U96 ( .A(D1_i[26]), .Y(n37) );
INVX2TS U97 ( .A(D1_i[29]), .Y(n34) );
INVX2TS U98 ( .A(D1_i[5]), .Y(n58) );
INVX2TS U99 ( .A(D1_i[7]), .Y(n56) );
INVX2TS U100 ( .A(D1_i[10]), .Y(n53) );
INVX2TS U101 ( .A(D1_i[12]), .Y(n51) );
INVX2TS U102 ( .A(D1_i[14]), .Y(n49) );
INVX2TS U103 ( .A(D1_i[16]), .Y(n47) );
INVX2TS U104 ( .A(D1_i[18]), .Y(n45) );
INVX2TS U105 ( .A(D1_i[3]), .Y(n60) );
INVX2TS U106 ( .A(D1_i[23]), .Y(n40) );
INVX2TS U107 ( .A(D1_i[27]), .Y(n36) );
INVX2TS U108 ( .A(D1_i[30]), .Y(n33) );
INVX2TS U109 ( .A(D1_i[28]), .Y(n35) );
INVX2TS U110 ( .A(D0_i[1]), .Y(n31) );
INVX2TS U111 ( .A(D0_i[3]), .Y(n29) );
INVX2TS U112 ( .A(D0_i[21]), .Y(n11) );
INVX2TS U113 ( .A(D0_i[22]), .Y(n10) );
INVX2TS U114 ( .A(D0_i[23]), .Y(n9) );
INVX2TS U115 ( .A(D0_i[24]), .Y(n8) );
INVX2TS U116 ( .A(D0_i[25]), .Y(n7) );
INVX2TS U117 ( .A(D0_i[27]), .Y(n5) );
INVX2TS U118 ( .A(D0_i[28]), .Y(n4) );
INVX2TS U119 ( .A(D0_i[30]), .Y(n2) );
INVX2TS U120 ( .A(D0_i[2]), .Y(n30) );
INVX2TS U121 ( .A(D0_i[6]), .Y(n26) );
INVX2TS U122 ( .A(D0_i[17]), .Y(n15) );
INVX2TS U123 ( .A(D0_i[26]), .Y(n6) );
INVX2TS U124 ( .A(D0_i[29]), .Y(n3) );
INVX2TS U125 ( .A(D0_i[4]), .Y(n28) );
INVX2TS U126 ( .A(D0_i[11]), .Y(n21) );
INVX2TS U127 ( .A(D0_i[13]), .Y(n19) );
INVX2TS U128 ( .A(D0_i[19]), .Y(n13) );
INVX2TS U129 ( .A(D1_i[0]), .Y(n63) );
INVX2TS U130 ( .A(D1_i[20]), .Y(n43) );
INVX2TS U131 ( .A(D1_i[21]), .Y(n42) );
INVX2TS U132 ( .A(D1_i[24]), .Y(n39) );
INVX2TS U133 ( .A(D1_i[1]), .Y(n62) );
INVX2TS U134 ( .A(D1_i[22]), .Y(n41) );
INVX2TS U135 ( .A(D1_i[25]), .Y(n38) );
INVX2TS U136 ( .A(D0_i[8]), .Y(n24) );
INVX2TS U137 ( .A(D0_i[9]), .Y(n23) );
INVX2TS U138 ( .A(D0_i[15]), .Y(n17) );
endmodule
module RegisterAdd_W31_1 ( clk, rst, load, D, Q );
input [30:0] D;
output [30:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73;
OAI2BB2XLTS U2 ( .B0(n1), .B1(n67), .A0N(n70), .A1N(D[0]), .Y(n32) );
OAI2BB2XLTS U3 ( .B0(n2), .B1(n67), .A0N(D[1]), .A1N(n70), .Y(n33) );
OAI2BB2XLTS U4 ( .B0(n3), .B1(n67), .A0N(D[2]), .A1N(n69), .Y(n34) );
OAI2BB2XLTS U5 ( .B0(n4), .B1(n67), .A0N(D[3]), .A1N(n69), .Y(n35) );
OAI2BB2XLTS U6 ( .B0(n5), .B1(n67), .A0N(D[4]), .A1N(n69), .Y(n36) );
OAI2BB2XLTS U7 ( .B0(n6), .B1(n67), .A0N(D[5]), .A1N(n69), .Y(n37) );
OAI2BB2XLTS U8 ( .B0(n7), .B1(n72), .A0N(D[6]), .A1N(n69), .Y(n38) );
OAI2BB2XLTS U9 ( .B0(n8), .B1(n72), .A0N(D[7]), .A1N(n69), .Y(n39) );
OAI2BB2XLTS U10 ( .B0(n9), .B1(n73), .A0N(D[8]), .A1N(n69), .Y(n40) );
OAI2BB2XLTS U11 ( .B0(n10), .B1(n72), .A0N(D[9]), .A1N(n69), .Y(n41) );
OAI2BB2XLTS U12 ( .B0(n11), .B1(n71), .A0N(D[10]), .A1N(n69), .Y(n42) );
OAI2BB2XLTS U13 ( .B0(n12), .B1(n73), .A0N(D[11]), .A1N(n69), .Y(n43) );
OAI2BB2XLTS U14 ( .B0(n13), .B1(n68), .A0N(D[12]), .A1N(n70), .Y(n44) );
OAI2BB2XLTS U15 ( .B0(n14), .B1(n68), .A0N(D[13]), .A1N(n70), .Y(n45) );
OAI2BB2XLTS U16 ( .B0(n15), .B1(n72), .A0N(D[14]), .A1N(n70), .Y(n46) );
OAI2BB2XLTS U17 ( .B0(n16), .B1(n68), .A0N(D[15]), .A1N(n70), .Y(n47) );
OAI2BB2XLTS U18 ( .B0(n17), .B1(n68), .A0N(D[16]), .A1N(n70), .Y(n48) );
OAI2BB2XLTS U19 ( .B0(n18), .B1(n68), .A0N(D[17]), .A1N(n70), .Y(n49) );
OAI2BB2XLTS U20 ( .B0(n19), .B1(n68), .A0N(D[18]), .A1N(n70), .Y(n50) );
OAI2BB2XLTS U21 ( .B0(n20), .B1(n71), .A0N(D[19]), .A1N(n71), .Y(n51) );
OAI2BB2XLTS U22 ( .B0(n21), .B1(n68), .A0N(D[20]), .A1N(n73), .Y(n52) );
OAI2BB2XLTS U23 ( .B0(n22), .B1(n68), .A0N(D[21]), .A1N(load), .Y(n53) );
OAI2BB2XLTS U24 ( .B0(n23), .B1(n68), .A0N(D[22]), .A1N(n70), .Y(n54) );
OAI2BB2XLTS U25 ( .B0(n24), .B1(n68), .A0N(D[23]), .A1N(n71), .Y(n55) );
OAI2BB2XLTS U26 ( .B0(n25), .B1(n73), .A0N(D[24]), .A1N(n71), .Y(n56) );
OAI2BB2XLTS U27 ( .B0(n26), .B1(n71), .A0N(D[25]), .A1N(n73), .Y(n57) );
OAI2BB2XLTS U28 ( .B0(n27), .B1(n72), .A0N(D[26]), .A1N(n72), .Y(n58) );
OAI2BB2XLTS U29 ( .B0(n28), .B1(n67), .A0N(D[27]), .A1N(n71), .Y(n59) );
OAI2BB2XLTS U30 ( .B0(n29), .B1(n67), .A0N(D[28]), .A1N(n73), .Y(n60) );
OAI2BB2XLTS U31 ( .B0(n30), .B1(n67), .A0N(D[29]), .A1N(n72), .Y(n61) );
CLKINVX1TS U32 ( .A(rst), .Y(n62) );
OAI2BB2XLTS U33 ( .B0(n31), .B1(n67), .A0N(D[30]), .A1N(n71), .Y(n63) );
DFFRX2TS \Q_reg[30] ( .D(n63), .CK(clk), .RN(n62), .Q(Q[30]), .QN(n31) );
DFFRX2TS \Q_reg[29] ( .D(n61), .CK(clk), .RN(n62), .Q(Q[29]), .QN(n30) );
DFFRX2TS \Q_reg[28] ( .D(n60), .CK(clk), .RN(n62), .Q(Q[28]), .QN(n29) );
DFFRX2TS \Q_reg[27] ( .D(n59), .CK(clk), .RN(n62), .Q(Q[27]), .QN(n28) );
DFFRX2TS \Q_reg[26] ( .D(n58), .CK(clk), .RN(n62), .Q(Q[26]), .QN(n27) );
DFFRX2TS \Q_reg[25] ( .D(n57), .CK(clk), .RN(n62), .Q(Q[25]), .QN(n26) );
DFFRX2TS \Q_reg[24] ( .D(n56), .CK(clk), .RN(n62), .Q(Q[24]), .QN(n25) );
DFFRX2TS \Q_reg[23] ( .D(n55), .CK(clk), .RN(n62), .Q(Q[23]), .QN(n24) );
DFFRX2TS \Q_reg[22] ( .D(n54), .CK(clk), .RN(n62), .Q(Q[22]), .QN(n23) );
DFFRX2TS \Q_reg[21] ( .D(n53), .CK(clk), .RN(n66), .Q(Q[21]), .QN(n22) );
DFFRX2TS \Q_reg[20] ( .D(n52), .CK(clk), .RN(n66), .Q(Q[20]), .QN(n21) );
DFFRX2TS \Q_reg[19] ( .D(n51), .CK(clk), .RN(n65), .Q(Q[19]), .QN(n20) );
DFFRX2TS \Q_reg[18] ( .D(n50), .CK(clk), .RN(n65), .Q(Q[18]), .QN(n19) );
DFFRX2TS \Q_reg[17] ( .D(n49), .CK(clk), .RN(n65), .Q(Q[17]), .QN(n18) );
DFFRX2TS \Q_reg[16] ( .D(n48), .CK(clk), .RN(n65), .Q(Q[16]), .QN(n17) );
DFFRX2TS \Q_reg[15] ( .D(n47), .CK(clk), .RN(n65), .Q(Q[15]), .QN(n16) );
DFFRX2TS \Q_reg[14] ( .D(n46), .CK(clk), .RN(n65), .Q(Q[14]), .QN(n15) );
DFFRX2TS \Q_reg[13] ( .D(n45), .CK(clk), .RN(n65), .Q(Q[13]), .QN(n14) );
DFFRX2TS \Q_reg[12] ( .D(n44), .CK(clk), .RN(n65), .Q(Q[12]), .QN(n13) );
DFFRX2TS \Q_reg[11] ( .D(n43), .CK(clk), .RN(n65), .Q(Q[11]), .QN(n12) );
DFFRX2TS \Q_reg[10] ( .D(n42), .CK(clk), .RN(n65), .Q(Q[10]), .QN(n11) );
DFFRX2TS \Q_reg[9] ( .D(n41), .CK(clk), .RN(n64), .Q(Q[9]), .QN(n10) );
DFFRX2TS \Q_reg[8] ( .D(n40), .CK(clk), .RN(n64), .Q(Q[8]), .QN(n9) );
DFFRX2TS \Q_reg[7] ( .D(n39), .CK(clk), .RN(n64), .Q(Q[7]), .QN(n8) );
DFFRX2TS \Q_reg[6] ( .D(n38), .CK(clk), .RN(n64), .Q(Q[6]), .QN(n7) );
DFFRX2TS \Q_reg[5] ( .D(n37), .CK(clk), .RN(n64), .Q(Q[5]), .QN(n6) );
DFFRX2TS \Q_reg[4] ( .D(n36), .CK(clk), .RN(n64), .Q(Q[4]), .QN(n5) );
DFFRX2TS \Q_reg[3] ( .D(n35), .CK(clk), .RN(n64), .Q(Q[3]), .QN(n4) );
DFFRX2TS \Q_reg[2] ( .D(n34), .CK(clk), .RN(n64), .Q(Q[2]), .QN(n3) );
DFFRX2TS \Q_reg[1] ( .D(n33), .CK(clk), .RN(n64), .Q(Q[1]), .QN(n2) );
DFFRX2TS \Q_reg[0] ( .D(n32), .CK(clk), .RN(n64), .Q(Q[0]), .QN(n1) );
CLKBUFX2TS U34 ( .A(n66), .Y(n64) );
CLKBUFX2TS U35 ( .A(n66), .Y(n65) );
CLKBUFX2TS U36 ( .A(n72), .Y(n68) );
CLKBUFX2TS U37 ( .A(n71), .Y(n69) );
CLKBUFX2TS U38 ( .A(n71), .Y(n70) );
CLKBUFX2TS U39 ( .A(n62), .Y(n66) );
CLKBUFX2TS U40 ( .A(load), .Y(n71) );
CLKBUFX2TS U41 ( .A(load), .Y(n72) );
CLKBUFX2TS U42 ( .A(n73), .Y(n67) );
CLKBUFX2TS U43 ( .A(load), .Y(n73) );
endmodule
module RegisterAdd_W32_0 ( clk, rst, load, D, Q );
input [31:0] D;
output [31:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n65, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94;
DFFRX2TS \Q_reg[31] ( .D(n65), .CK(clk), .RN(n84), .Q(Q[31]), .QN(n32) );
DFFRX2TS \Q_reg[25] ( .D(n58), .CK(clk), .RN(n84), .Q(Q[25]), .QN(n26) );
DFFRX2TS \Q_reg[24] ( .D(n57), .CK(clk), .RN(n84), .Q(Q[24]), .QN(n25) );
DFFRX2TS \Q_reg[28] ( .D(n61), .CK(clk), .RN(n84), .Q(Q[28]), .QN(n29) );
DFFRX2TS \Q_reg[30] ( .D(n63), .CK(clk), .RN(n84), .Q(Q[30]), .QN(n31) );
DFFRX2TS \Q_reg[27] ( .D(n60), .CK(clk), .RN(n84), .Q(Q[27]), .QN(n28) );
DFFRX2TS \Q_reg[23] ( .D(n56), .CK(clk), .RN(n84), .Q(Q[23]), .QN(n24) );
DFFRX2TS \Q_reg[29] ( .D(n62), .CK(clk), .RN(n84), .Q(Q[29]), .QN(n30) );
DFFRX2TS \Q_reg[26] ( .D(n59), .CK(clk), .RN(n84), .Q(Q[26]), .QN(n27) );
DFFRX2TS \Q_reg[22] ( .D(n55), .CK(clk), .RN(n84), .Q(Q[22]), .QN(n23) );
DFFRX2TS \Q_reg[21] ( .D(n54), .CK(clk), .RN(n94), .Q(Q[21]), .QN(n22) );
DFFRX2TS \Q_reg[20] ( .D(n53), .CK(clk), .RN(n94), .Q(Q[20]), .QN(n21) );
DFFRX2TS \Q_reg[18] ( .D(n51), .CK(clk), .RN(n86), .Q(Q[18]), .QN(n19) );
DFFRX2TS \Q_reg[16] ( .D(n49), .CK(clk), .RN(n86), .Q(Q[16]), .QN(n17) );
DFFRX2TS \Q_reg[17] ( .D(n50), .CK(clk), .RN(n86), .Q(Q[17]), .QN(n18) );
DFFRX2TS \Q_reg[19] ( .D(n52), .CK(clk), .RN(n86), .Q(Q[19]), .QN(n20) );
DFFRX2TS \Q_reg[3] ( .D(n36), .CK(clk), .RN(n85), .Q(Q[3]), .QN(n4) );
DFFRX2TS \Q_reg[14] ( .D(n47), .CK(clk), .RN(n86), .Q(Q[14]), .QN(n15) );
DFFRX2TS \Q_reg[12] ( .D(n45), .CK(clk), .RN(n86), .Q(Q[12]), .QN(n13) );
DFFRX2TS \Q_reg[7] ( .D(n40), .CK(clk), .RN(n85), .Q(Q[7]), .QN(n8) );
DFFRX2TS \Q_reg[5] ( .D(n38), .CK(clk), .RN(n85), .Q(Q[5]), .QN(n6) );
DFFRX2TS \Q_reg[6] ( .D(n39), .CK(clk), .RN(n85), .Q(Q[6]), .QN(n7) );
DFFRX2TS \Q_reg[15] ( .D(n48), .CK(clk), .RN(n86), .Q(Q[15]), .QN(n16) );
DFFRX2TS \Q_reg[13] ( .D(n46), .CK(clk), .RN(n86), .Q(Q[13]), .QN(n14) );
DFFRX2TS \Q_reg[11] ( .D(n44), .CK(clk), .RN(n85), .Q(Q[11]), .QN(n12) );
DFFRX2TS \Q_reg[4] ( .D(n37), .CK(clk), .RN(n85), .Q(Q[4]), .QN(n5) );
DFFRX2TS \Q_reg[1] ( .D(n34), .CK(clk), .RN(n86), .Q(Q[1]), .QN(n2) );
DFFRX2TS \Q_reg[0] ( .D(n33), .CK(clk), .RN(n86), .Q(Q[0]), .QN(n1) );
DFFRX2TS \Q_reg[10] ( .D(n43), .CK(clk), .RN(n85), .Q(Q[10]), .QN(n11) );
DFFRX2TS \Q_reg[2] ( .D(n35), .CK(clk), .RN(n85), .Q(Q[2]), .QN(n3) );
DFFRX2TS \Q_reg[9] ( .D(n42), .CK(clk), .RN(n85), .Q(Q[9]), .QN(n10) );
DFFRX2TS \Q_reg[8] ( .D(n41), .CK(clk), .RN(n85), .Q(Q[8]), .QN(n9) );
CLKBUFX2TS U2 ( .A(n92), .Y(n88) );
CLKBUFX2TS U3 ( .A(n92), .Y(n87) );
CLKBUFX2TS U4 ( .A(n91), .Y(n89) );
CLKBUFX2TS U5 ( .A(n91), .Y(n90) );
CLKBUFX2TS U6 ( .A(n94), .Y(n85) );
CLKBUFX2TS U7 ( .A(n94), .Y(n84) );
CLKBUFX2TS U8 ( .A(n94), .Y(n86) );
OAI2BB2XLTS U9 ( .B0(n1), .B1(n93), .A0N(D[0]), .A1N(n90), .Y(n33) );
OAI2BB2XLTS U10 ( .B0(n2), .B1(n88), .A0N(D[1]), .A1N(n90), .Y(n34) );
OAI2BB2XLTS U11 ( .B0(n3), .B1(load), .A0N(D[2]), .A1N(n89), .Y(n35) );
OAI2BB2XLTS U12 ( .B0(n4), .B1(n88), .A0N(D[3]), .A1N(n89), .Y(n36) );
OAI2BB2XLTS U13 ( .B0(n5), .B1(n88), .A0N(D[4]), .A1N(n89), .Y(n37) );
OAI2BB2XLTS U14 ( .B0(n6), .B1(n88), .A0N(D[5]), .A1N(n90), .Y(n38) );
OAI2BB2XLTS U15 ( .B0(n7), .B1(n88), .A0N(D[6]), .A1N(n90), .Y(n39) );
OAI2BB2XLTS U16 ( .B0(n8), .B1(n88), .A0N(D[7]), .A1N(n90), .Y(n40) );
OAI2BB2XLTS U17 ( .B0(n9), .B1(n88), .A0N(D[8]), .A1N(n93), .Y(n41) );
OAI2BB2XLTS U18 ( .B0(n10), .B1(n88), .A0N(D[9]), .A1N(n90), .Y(n42) );
OAI2BB2XLTS U19 ( .B0(n11), .B1(n88), .A0N(D[10]), .A1N(n91), .Y(n43) );
OAI2BB2XLTS U20 ( .B0(n12), .B1(n87), .A0N(D[11]), .A1N(n92), .Y(n44) );
OAI2BB2XLTS U21 ( .B0(n13), .B1(n87), .A0N(D[12]), .A1N(n93), .Y(n45) );
OAI2BB2XLTS U22 ( .B0(n14), .B1(n87), .A0N(D[13]), .A1N(n91), .Y(n46) );
OAI2BB2XLTS U23 ( .B0(n15), .B1(n87), .A0N(D[14]), .A1N(n92), .Y(n47) );
OAI2BB2XLTS U24 ( .B0(n16), .B1(n88), .A0N(D[15]), .A1N(n90), .Y(n48) );
OAI2BB2XLTS U25 ( .B0(n17), .B1(n87), .A0N(D[16]), .A1N(n93), .Y(n49) );
OAI2BB2XLTS U26 ( .B0(n18), .B1(n87), .A0N(D[17]), .A1N(n91), .Y(n50) );
OAI2BB2XLTS U27 ( .B0(n19), .B1(n87), .A0N(D[18]), .A1N(n90), .Y(n51) );
OAI2BB2XLTS U28 ( .B0(n20), .B1(n87), .A0N(D[19]), .A1N(n91), .Y(n52) );
OAI2BB2XLTS U29 ( .B0(n21), .B1(n87), .A0N(D[20]), .A1N(n91), .Y(n53) );
OAI2BB2XLTS U30 ( .B0(n22), .B1(n93), .A0N(D[21]), .A1N(n89), .Y(n54) );
OAI2BB2XLTS U31 ( .B0(n23), .B1(n93), .A0N(D[22]), .A1N(n91), .Y(n55) );
OAI2BB2XLTS U32 ( .B0(n24), .B1(n93), .A0N(D[23]), .A1N(n91), .Y(n56) );
OAI2BB2XLTS U33 ( .B0(n25), .B1(n93), .A0N(D[24]), .A1N(n89), .Y(n57) );
OAI2BB2XLTS U34 ( .B0(n26), .B1(n93), .A0N(D[25]), .A1N(n89), .Y(n58) );
OAI2BB2XLTS U35 ( .B0(n27), .B1(n93), .A0N(D[26]), .A1N(n89), .Y(n59) );
OAI2BB2XLTS U36 ( .B0(n28), .B1(n92), .A0N(D[27]), .A1N(n89), .Y(n60) );
OAI2BB2XLTS U37 ( .B0(n29), .B1(n92), .A0N(D[28]), .A1N(n89), .Y(n61) );
OAI2BB2XLTS U38 ( .B0(n30), .B1(n92), .A0N(D[29]), .A1N(n89), .Y(n62) );
OAI2BB2XLTS U39 ( .B0(n31), .B1(n91), .A0N(D[30]), .A1N(n90), .Y(n63) );
OAI2BB2XLTS U40 ( .B0(n32), .B1(n87), .A0N(n90), .A1N(D[31]), .Y(n65) );
CLKBUFX2TS U41 ( .A(load), .Y(n91) );
CLKBUFX2TS U42 ( .A(load), .Y(n92) );
CLKBUFX2TS U43 ( .A(load), .Y(n93) );
INVX2TS U44 ( .A(rst), .Y(n94) );
endmodule
module RegisterAdd_W1_0 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4, n6;
DFFRX2TS \Q_reg[0] ( .D(n3), .CK(clk), .RN(n6), .Q(Q[0]), .QN(n4) );
OAI2BB2XLTS U2 ( .B0(n4), .B1(load), .A0N(load), .A1N(D[0]), .Y(n3) );
INVX2TS U3 ( .A(rst), .Y(n6) );
endmodule
module RegisterAdd_W31_0 ( clk, rst, load, D, Q );
input [30:0] D;
output [30:0] Q;
input clk, rst, load;
wire n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115,
n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136;
OAI2BB2XLTS U2 ( .B0(n136), .B1(n67), .A0N(n71), .A1N(D[0]), .Y(n105) );
OAI2BB2XLTS U3 ( .B0(n135), .B1(n67), .A0N(D[1]), .A1N(n71), .Y(n104) );
OAI2BB2XLTS U4 ( .B0(n134), .B1(n67), .A0N(D[2]), .A1N(n70), .Y(n103) );
OAI2BB2XLTS U5 ( .B0(n133), .B1(n67), .A0N(D[3]), .A1N(n70), .Y(n102) );
OAI2BB2XLTS U6 ( .B0(n132), .B1(n67), .A0N(D[4]), .A1N(n70), .Y(n101) );
OAI2BB2XLTS U7 ( .B0(n131), .B1(n67), .A0N(D[5]), .A1N(n70), .Y(n100) );
OAI2BB2XLTS U8 ( .B0(n130), .B1(n68), .A0N(D[6]), .A1N(n70), .Y(n99) );
OAI2BB2XLTS U9 ( .B0(n129), .B1(n68), .A0N(D[7]), .A1N(n70), .Y(n98) );
OAI2BB2XLTS U10 ( .B0(n128), .B1(n68), .A0N(D[8]), .A1N(n70), .Y(n97) );
OAI2BB2XLTS U11 ( .B0(n127), .B1(n68), .A0N(D[9]), .A1N(n70), .Y(n96) );
OAI2BB2XLTS U12 ( .B0(n126), .B1(n68), .A0N(D[10]), .A1N(n70), .Y(n95) );
OAI2BB2XLTS U13 ( .B0(n125), .B1(n68), .A0N(D[11]), .A1N(n70), .Y(n94) );
OAI2BB2XLTS U14 ( .B0(n124), .B1(n69), .A0N(D[12]), .A1N(n71), .Y(n93) );
OAI2BB2XLTS U15 ( .B0(n123), .B1(n69), .A0N(D[13]), .A1N(n71), .Y(n92) );
OAI2BB2XLTS U16 ( .B0(n122), .B1(n68), .A0N(D[14]), .A1N(n71), .Y(n91) );
OAI2BB2XLTS U17 ( .B0(n121), .B1(n69), .A0N(D[15]), .A1N(n71), .Y(n90) );
OAI2BB2XLTS U18 ( .B0(n120), .B1(n69), .A0N(D[16]), .A1N(n71), .Y(n89) );
OAI2BB2XLTS U19 ( .B0(n119), .B1(n69), .A0N(D[17]), .A1N(n71), .Y(n88) );
OAI2BB2XLTS U20 ( .B0(n118), .B1(n69), .A0N(D[18]), .A1N(n71), .Y(n87) );
OAI2BB2XLTS U21 ( .B0(n117), .B1(n72), .A0N(D[19]), .A1N(n72), .Y(n86) );
OAI2BB2XLTS U22 ( .B0(n116), .B1(n69), .A0N(D[20]), .A1N(n72), .Y(n85) );
OAI2BB2XLTS U23 ( .B0(n115), .B1(n69), .A0N(D[21]), .A1N(n72), .Y(n84) );
OAI2BB2XLTS U24 ( .B0(n114), .B1(n69), .A0N(D[22]), .A1N(n71), .Y(n83) );
OAI2BB2XLTS U25 ( .B0(n113), .B1(n69), .A0N(D[23]), .A1N(load), .Y(n82) );
OAI2BB2XLTS U26 ( .B0(n112), .B1(n68), .A0N(D[24]), .A1N(n72), .Y(n81) );
OAI2BB2XLTS U27 ( .B0(n111), .B1(n68), .A0N(D[25]), .A1N(n73), .Y(n80) );
OAI2BB2XLTS U28 ( .B0(n110), .B1(n68), .A0N(D[26]), .A1N(n73), .Y(n79) );
OAI2BB2XLTS U29 ( .B0(n109), .B1(n67), .A0N(D[27]), .A1N(n73), .Y(n78) );
OAI2BB2XLTS U30 ( .B0(n108), .B1(n67), .A0N(D[28]), .A1N(n72), .Y(n77) );
OAI2BB2XLTS U31 ( .B0(n107), .B1(n67), .A0N(D[29]), .A1N(n72), .Y(n76) );
CLKINVX1TS U32 ( .A(rst), .Y(n75) );
OAI2BB2XLTS U33 ( .B0(n106), .B1(n67), .A0N(D[30]), .A1N(n72), .Y(n74) );
DFFRX2TS \Q_reg[30] ( .D(n74), .CK(clk), .RN(n75), .Q(Q[30]), .QN(n106) );
DFFRX2TS \Q_reg[29] ( .D(n76), .CK(clk), .RN(n75), .Q(Q[29]), .QN(n107) );
DFFRX2TS \Q_reg[28] ( .D(n77), .CK(clk), .RN(n75), .Q(Q[28]), .QN(n108) );
DFFRX2TS \Q_reg[27] ( .D(n78), .CK(clk), .RN(n75), .Q(Q[27]), .QN(n109) );
DFFRX2TS \Q_reg[26] ( .D(n79), .CK(clk), .RN(n75), .Q(Q[26]), .QN(n110) );
DFFRX2TS \Q_reg[25] ( .D(n80), .CK(clk), .RN(n75), .Q(Q[25]), .QN(n111) );
DFFRX2TS \Q_reg[24] ( .D(n81), .CK(clk), .RN(n75), .Q(Q[24]), .QN(n112) );
DFFRX2TS \Q_reg[23] ( .D(n82), .CK(clk), .RN(n75), .Q(Q[23]), .QN(n113) );
DFFRX2TS \Q_reg[22] ( .D(n83), .CK(clk), .RN(n75), .Q(Q[22]), .QN(n114) );
DFFRX2TS \Q_reg[21] ( .D(n84), .CK(clk), .RN(n66), .Q(Q[21]), .QN(n115) );
DFFRX2TS \Q_reg[20] ( .D(n85), .CK(clk), .RN(n66), .Q(Q[20]), .QN(n116) );
DFFRX2TS \Q_reg[19] ( .D(n86), .CK(clk), .RN(n65), .Q(Q[19]), .QN(n117) );
DFFRX2TS \Q_reg[18] ( .D(n87), .CK(clk), .RN(n65), .Q(Q[18]), .QN(n118) );
DFFRX2TS \Q_reg[17] ( .D(n88), .CK(clk), .RN(n65), .Q(Q[17]), .QN(n119) );
DFFRX2TS \Q_reg[16] ( .D(n89), .CK(clk), .RN(n65), .Q(Q[16]), .QN(n120) );
DFFRX2TS \Q_reg[15] ( .D(n90), .CK(clk), .RN(n65), .Q(Q[15]), .QN(n121) );
DFFRX2TS \Q_reg[14] ( .D(n91), .CK(clk), .RN(n65), .Q(Q[14]), .QN(n122) );
DFFRX2TS \Q_reg[13] ( .D(n92), .CK(clk), .RN(n65), .Q(Q[13]), .QN(n123) );
DFFRX2TS \Q_reg[12] ( .D(n93), .CK(clk), .RN(n65), .Q(Q[12]), .QN(n124) );
DFFRX2TS \Q_reg[11] ( .D(n94), .CK(clk), .RN(n65), .Q(Q[11]), .QN(n125) );
DFFRX2TS \Q_reg[10] ( .D(n95), .CK(clk), .RN(n65), .Q(Q[10]), .QN(n126) );
DFFRX2TS \Q_reg[9] ( .D(n96), .CK(clk), .RN(n64), .Q(Q[9]), .QN(n127) );
DFFRX2TS \Q_reg[8] ( .D(n97), .CK(clk), .RN(n64), .Q(Q[8]), .QN(n128) );
DFFRX2TS \Q_reg[7] ( .D(n98), .CK(clk), .RN(n64), .Q(Q[7]), .QN(n129) );
DFFRX2TS \Q_reg[6] ( .D(n99), .CK(clk), .RN(n64), .Q(Q[6]), .QN(n130) );
DFFRX2TS \Q_reg[5] ( .D(n100), .CK(clk), .RN(n64), .Q(Q[5]), .QN(n131) );
DFFRX2TS \Q_reg[4] ( .D(n101), .CK(clk), .RN(n64), .Q(Q[4]), .QN(n132) );
DFFRX2TS \Q_reg[3] ( .D(n102), .CK(clk), .RN(n64), .Q(Q[3]), .QN(n133) );
DFFRX2TS \Q_reg[2] ( .D(n103), .CK(clk), .RN(n64), .Q(Q[2]), .QN(n134) );
DFFRX2TS \Q_reg[1] ( .D(n104), .CK(clk), .RN(n64), .Q(Q[1]), .QN(n135) );
DFFRX2TS \Q_reg[0] ( .D(n105), .CK(clk), .RN(n64), .Q(Q[0]), .QN(n136) );
CLKBUFX2TS U34 ( .A(n66), .Y(n64) );
CLKBUFX2TS U35 ( .A(n66), .Y(n65) );
CLKBUFX2TS U36 ( .A(n73), .Y(n69) );
CLKBUFX2TS U37 ( .A(n73), .Y(n68) );
CLKBUFX2TS U38 ( .A(n72), .Y(n70) );
CLKBUFX2TS U39 ( .A(n72), .Y(n71) );
CLKBUFX2TS U40 ( .A(n75), .Y(n66) );
CLKBUFX2TS U41 ( .A(load), .Y(n72) );
CLKBUFX2TS U42 ( .A(load), .Y(n73) );
CLKBUFX2TS U43 ( .A(load), .Y(n67) );
endmodule
module Oper_Start_In ( clk, rst, load_a_i, load_b_i, add_subt_i, Data_X_i,
Data_Y_i, DMP_o, DmP_o, zero_flag_o, real_op_o, sign_final_result_o );
input [31:0] Data_X_i;
input [31:0] Data_Y_i;
output [30:0] DMP_o;
output [30:0] DmP_o;
input clk, rst, load_a_i, load_b_i, add_subt_i;
output zero_flag_o, real_op_o, sign_final_result_o;
wire intAS, gtXY, eqXY, sign_result;
wire [31:0] intDX;
wire [31:0] intDY;
wire [30:0] intM;
wire [30:0] intm;
RegisterAdd_W32_1 XRegister ( .clk(clk), .rst(rst), .load(load_a_i), .D(
Data_X_i), .Q(intDX) );
RegisterAdd_W32_0 YRegister ( .clk(clk), .rst(rst), .load(load_a_i), .D(
Data_Y_i), .Q(intDY) );
RegisterAdd_W1_1 ASRegister ( .clk(clk), .rst(rst), .load(load_a_i), .D(
add_subt_i), .Q(intAS) );
Comparator_W31 Magnitude_Comparator ( .Data_X_i(intDX[30:0]), .Data_Y_i(
intDY[30:0]), .gtXY_o(gtXY), .eqXY_o(eqXY) );
xor_tri_W32 Op_verification ( .A_i(intDX[31]), .B_i(intDY[31]), .C_i(intAS),
.Z_o(real_op_o) );
sgn_result result_sign_bit ( .Add_Subt_i(intAS), .sgn_X_i(intDX[31]),
.sgn_Y_i(intDY[31]), .gtXY_i(gtXY), .eqXY_i(eqXY), .sgn_result_o(
sign_result) );
MultiplexTxT_W31 MuxXY ( .select(gtXY), .D0_i(intDX[30:0]), .D1_i(
intDY[30:0]), .S0_o(intM), .S1_o(intm) );
RegisterAdd_W31_1 MRegister ( .clk(clk), .rst(rst), .load(load_b_i), .D(intM), .Q(DMP_o) );
RegisterAdd_W31_0 mRegister ( .clk(clk), .rst(rst), .load(load_b_i), .D(intm), .Q(DmP_o) );
RegisterAdd_W1_0 SignRegister ( .clk(clk), .rst(rst), .load(load_b_i), .D(
sign_result), .Q(sign_final_result_o) );
AND2X2TS U2 ( .A(real_op_o), .B(eqXY), .Y(zero_flag_o) );
endmodule
|
module bridge (
// EC/LIMB data bus
inout [7:0] limb_d,
input limb_start,
input limb_clk,
input limb_nrd,
output limb_nwait,
output limb_nreq,
// CPU bus
inout [31:0] cpu_d,
output cpu_nwait,
input cpu_naddr,
input cpu_nwr,
input [1:0] cpu_nreq,
output [1:0] cpu_nack,
output [1:0] cpu_nint,
output cpu_clk_out,
input cpu_clk_in,
// PCI bus
inout [31:0] pci_ad,
input [3:0] pci_nreq,
output [3:0] pci_ngnt,
input [3:0] pci_nint,
output [3:0] pci_cbe,
output pci_nframe,
input pci_ntrdy,
output pci_nirdy,
output pci_ndevsel,
input pci_nstop,
inout pci_nserr,
inout pci_nperr,
inout pci_nlock,
inout pci_parity,
output pci_clk,
// DDR3 SDRAM
inout [7:0] ddr_ndqs,
inout [7:0] ddr_pdqs,
output [2:0] ddr_ba,
output [15:0] ddr_addr,
output [7:0] ddr_dm,
output [1:0] ddr_nck,
output [1:0] ddr_pck,
output [1:0] ddr_cke,
output ddr_nwe,
output ddr_ncas,
output ddr_nras,
output [1:0] ddr_ns,
output [1:0] ddr_odt,
inout [63:0] ddr_dq,
input ddr_clk_in
);
assign pci_ad = 32'hZZZZZZZZ;
assign pci_nserr = 1'bZ;
assign pci_nperr = 1'bZ;
assign pci_nlock = 1'bZ;
assign pci_parity = 1'bZ;
assign pci_clk = 1'b0;
assign pci_ngnt = 4'hF;
assign pci_cbe = 4'hF;
assign pci_nframe = 1'b1;
assign pci_nirdy = 1'b1;
assign pci_ndevsel = 1'b1;
assign cpu_d = 32'hZZZZZZZZ;
assign cpu_nwait = 1'b1;
assign cpu_nack = 2'b11;
assign cpu_nint = 2'b11;
assign cpu_clk_out = 1'b0;
assign limb_nreq = 1'b0;
wire [31:0] gpio_in;
wire [31:0] gpio_out;
wire clk150;
wire clk75;
wire[2:0] ddr_cmd;
wire reset;
`define DEF_WISHBONE_WIRES(name) \
wire [35:0] wb_adr_``name; \
wire wb_we_``name; \
wire [3:0] wb_sel_``name; \
wire wb_stb_``name; \
wire wb_cyc_``name; \
wire [31:0] wb_dat_to_``name; \
wire [31:0] wb_dat_from_``name; \
wire wb_ack_``name;
`define DEF_WISHBONE_UNUSED(n) \
wire wb_ack_stb_``n;
`define CONNECT_MASTER(n, name) \
.m``n``_data_i(wb_dat_from_``name), \
.m``n``_data_o(wb_dat_to_``name), \
.m``n``_addr_i(wb_adr_``name), \
.m``n``_sel_i(wb_sel_``name), \
.m``n``_we_i(wb_we_``name), \
.m``n``_cyc_i(wb_cyc_``name), \
.m``n``_stb_i(wb_stb_``name), \
.m``n``_ack_o(wb_ack_``name)
`define UNUSED_MASTER(n) \
.m``n``_data_i(32'h00000000), \
.m``n``_addr_i(36'h000000000), \
.m``n``_sel_i(4'h0), \
.m``n``_we_i(1'b0), \
.m``n``_cyc_i(1'b0), \
.m``n``_stb_i(1'b0)
`define CONNECT_SLAVE(n, name) \
.s``n``_data_i(wb_dat_from_``name), \
.s``n``_data_o(wb_dat_to_``name), \
.s``n``_addr_o(wb_adr_``name), \
.s``n``_sel_o(wb_sel_``name), \
.s``n``_we_o(wb_we_``name), \
.s``n``_cyc_o(wb_cyc_``name), \
.s``n``_stb_o(wb_stb_``name), \
.s``n``_ack_i(wb_ack_``name), \
.s``n``_err_i(1'b0), \
.s``n``_rty_i(1'b0)
`define UNUSED_SLAVE(n) \
.s``n``_data_i(32'h00000000), \
.s``n``_ack_i(wb_ack_stb_``n), \
.s``n``_stb_o(wb_ack_stb_``n), \
.s``n``_err_i(1'b0), \
.s``n``_rty_i(1'b0)
`DEF_WISHBONE_WIRES(limb)
`DEF_WISHBONE_WIRES(blockram)
`DEF_WISHBONE_WIRES(dram)
`DEF_WISHBONE_WIRES(gpio)
`DEF_WISHBONE_UNUSED(1)
`DEF_WISHBONE_UNUSED(2)
`DEF_WISHBONE_UNUSED(3)
`DEF_WISHBONE_UNUSED(4)
`DEF_WISHBONE_UNUSED(5)
`DEF_WISHBONE_UNUSED(6)
`DEF_WISHBONE_UNUSED(7)
`DEF_WISHBONE_UNUSED(8)
`DEF_WISHBONE_UNUSED(9)
`DEF_WISHBONE_UNUSED(10)
`DEF_WISHBONE_UNUSED(11)
`DEF_WISHBONE_UNUSED(12)
`DEF_WISHBONE_UNUSED(13)
`DEF_WISHBONE_UNUSED(15)
wire [7:0] limb_d_out;
wire limb_d_oe;
//assign wb_adr = {wb_adr_full[3:0], 2'b00};
assign limb_d = limb_d_oe ? limb_d_out : 8'bZZZZZZZZ;
limb_interface limb_interface_inst (
.limb_d_in(limb_d),
.limb_d_out(limb_d_out),
.limb_d_oe(limb_d_oe),
.limb_clk(limb_clk),
.limb_nrd(limb_nrd),
.limb_start(limb_start),
.limb_nwait(limb_nwait),
.wb_adr_o(wb_adr_limb),
.wb_we_o(wb_we_limb),
.wb_sel_o(wb_sel_limb),
.wb_stb_o(wb_stb_limb),
.wb_cyc_o(wb_cyc_limb),
.wb_dat_o(wb_dat_from_limb),
.wb_dat_i(wb_dat_to_limb),
.wb_ack_i(wb_ack_limb),
.clk(clk75) );
wb_ram #( .ADDR_WIDTH(6) ) wb_ram_inst (
.clk(clk75),
.adr_i({wb_adr_blockram[3:0], 2'b00}),
.dat_i(wb_dat_to_blockram),
.dat_o(wb_dat_from_blockram),
.we_i(wb_we_blockram),
.sel_i(wb_sel_blockram),
.stb_i(wb_stb_blockram),
.ack_o(wb_ack_blockram),
.cyc_i(wb_cyc_blockram) );
wb_conmax_top #( .dw(32), .aw(36) ) wb_conmax_inst (
.clk_i(clk75),
.rst_i(1'b0),
`CONNECT_MASTER(0, limb),
`UNUSED_MASTER(1),
`UNUSED_MASTER(2),
`UNUSED_MASTER(3),
`UNUSED_MASTER(4),
`UNUSED_MASTER(5),
`UNUSED_MASTER(6),
`UNUSED_MASTER(7),
`CONNECT_SLAVE(0, blockram),
`CONNECT_SLAVE(1, gpio),
`UNUSED_SLAVE(2),
`UNUSED_SLAVE(3),
`UNUSED_SLAVE(4),
`UNUSED_SLAVE(5),
`UNUSED_SLAVE(6),
`UNUSED_SLAVE(7),
`UNUSED_SLAVE(8),
`UNUSED_SLAVE(9),
`UNUSED_SLAVE(10),
`UNUSED_SLAVE(11),
`UNUSED_SLAVE(12),
`UNUSED_SLAVE(13),
`CONNECT_SLAVE(14, dram),
`UNUSED_SLAVE(15)
);
wire drac_srd;
wire drac_swr;
wire [33:5] drac_sa;
wire [255:0] drac_swdat;
wire [31:0] drac_smsk;
wire [255:0] drac_srdat;
wire drac_srdy;
wire [2:0] drac_dbg_in;
wire [7:0] drac_dbg_out;
assign ddr_nras = ddr_cmd[2];
assign ddr_ncas = ddr_cmd[1];
assign ddr_nwe = ddr_cmd[0];
drac_wb_adapter drac_wb (
.drac_srd_o (drac_srd),
.drac_swr_o (drac_swr),
.drac_sa_o (drac_sa),
.drac_swdat_o (drac_swdat),
.drac_smsk_o (drac_smsk),
.drac_srdat_i (drac_srdat),
.drac_srdy_i (drac_srdy),
.clk150 (clk150),
.wb_adr_i (wb_adr_dram),
.wb_we_i (wb_we_dram),
.wb_sel_i (wb_sel_dram),
.wb_stb_i (wb_stb_dram),
.wb_cyc_i (wb_cyc_dram),
.wb_dat_i (wb_dat_to_dram),
.wb_dat_o (wb_dat_from_dram),
.wb_ack_o (wb_ack_dram),
.clk75 (clk75),
.reset (reset)
);
drac_ddr3 drac (
.ckin (ddr_clk_in), // should be 62.5 MHz
.ckout (clk150),
.ckouthalf (clk75),
.reset (reset),
.ddq (ddr_dq),
.dqsp (ddr_pdqs),
.dqsn (ddr_ndqs),
.ddm (ddr_dm),
.da (ddr_addr),
.dba (ddr_ba),
.dcmd (ddr_cmd),
.dce (ddr_cke),
.dcs (ddr_ns),
.dckp (ddr_pck),
.dckn (ddr_nck),
.dodt (ddr_odt),
.srd(drac_srd),
.swr(drac_swr),
.sa(drac_sa),
.swdat(drac_swdat),
.smsk(drac_smsk),
.srdat(drac_srdat),
.srdy(drac_srdy),
.dbg_out(drac_dbg_in),
.dbg_in(drac_dbg_out)
);
wb_simple_gpio gpio (
.wb_adr_i (wb_adr_gpio),
.wb_we_i (wb_we_gpio),
.wb_sel_i (wb_sel_gpio),
.wb_stb_i (wb_stb_gpio),
.wb_cyc_i (wb_cyc_gpio),
.wb_dat_i (wb_dat_to_gpio),
.wb_dat_o (wb_dat_from_gpio),
.wb_ack_o (wb_ack_gpio),
.gpio_in (gpio_in),
.gpio_out (gpio_out),
.clk (clk75)
);
assign gpio_in[7:0] = drac_dbg_out;
assign gpio_in[8] = reset;
assign drac_dbg_in = gpio_out[2:0];
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_2_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_2_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_2_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_2_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`timescale 1 ns / 100 ps
module helloonechar_tb #(parameter CLOCK_FREQ = 4800, parameter BAUD_RATE = 1200) ();
reg ext_clock;
wire uart_tx_pin;
wire uart_tx_led;
wire uart_clock_led;
wire reset;
/* uart tx */
wire uart_ready;
reg [7:0] uart_data;
reg uart_clock_enable;
reg [7:0] count;
wire uart_clock;
power_on_reset POR(
.clock(ext_clock),
.reset(reset));
always
#2 ext_clock = ~ext_clock;
initial begin
#500000 $finish;
end
initial begin
$dumpfile ("helloonechar_tb.vcd");
$dumpvars (0, helloonechar_tb);
ext_clock = 0;
end
initial begin
uart_data = 8'h60;
end
always @(negedge uart_ready or negedge reset) begin
if (~reset) begin
uart_clock_enable <= 1;
count <= 16;
end else begin
if (count == 0)
uart_clock_enable <= 0;
else
count <= count - 1;
end
end
uart_tx #(.CLOCK_FREQ(CLOCK_FREQ), .BAUD_RATE(BAUD_RATE))
SERIAL (.read_data(uart_data),
.read_clock_enable(uart_clock_enable),
.reset(reset),
.ready(uart_ready),
.tx(uart_tx_pin),
.clock(ext_clock),
.uart_clock(uart_clock));
assign uart_tx_led = uart_tx_pin;
assign uart_clock_led = uart_clock;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_dmul_64ns_64ns_64_6_max_dsp
#(parameter
ID = 6,
NUM_STAGE = 6,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
HLS_accel_ap_dmul_4_max_dsp_64 HLS_accel_ap_dmul_4_max_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
// pcie_hip_s4gx_gen2_x4_128_wrapper - a hand-written Verilog wrapper that instances the core and some convieniences
// Copyright (c) 2011 Atomic Rules LLC - ALL RIGHTS RESERVED
// derrived from the (level:2) _plus level of the megafunction example,
// add/including elements from the (level:1) and (level:0) megafunction example
module pcie_hip_s4gx_gen2_x4_128_wrapper (
input wire sys0_clk, // System 200 MHz sys0_clk
input wire sys0_rstn, // System Active-Low sys0 Reset
input wire pcie_clk, // PCIe 100 MHz reference
input wire pcie_rstn, // PCIe Active-Low Reset
input wire [3:0] pcie_rx_in, // PCIe RX SERDES
output wire [3:0] pcie_tx_out, // PCIe TX SERDES
output wire ava_core_clk_out, // Avalon 125 MHz clock out
output wire ava_srstn, // Avalon Active-Low Reset
output wire ava_alive, // Avalon Alive
output wire ava_lnk_up, // Avalon Link-Up
output wire [31:0] ava_debug, // 32b of Debug Info
output wire [3:0] tl_cfg_add, // Altera Multiplexed Configuration...
output wire [31:0] tl_cfg_ctl,
output wire tl_cfg_ctl_wr,
output wire [52:0] tl_cfg_sts, // Altera Status...
output wire tl_cfg_sts_wr,
input wire rx_st_mask0, // Avalon RX signalling...
input wire rx_st_ready0, // downstream traffic
output wire rx_st_valid0,
output wire [7:0] rx_st_bardec0,
output wire [15:0] rx_st_be0,
output wire [127:0] rx_st_data0,
output wire rx_st_sop0,
output wire rx_st_eop0,
output wire rx_st_empty0,
output wire rx_st_err0,
input wire [127:0] tx_st_data0, // Avalon TX signalling...
input wire tx_st_sop0, // upstream traffic
input wire tx_st_eop0,
input wire tx_st_empty0,
input wire tx_st_valid0,
input wire tx_st_err0,
output wire tx_st_ready0,
output wire [35:0] tx_cred0,
output wire tx_fifo_empty0
);
// 32b of Debug Info
assign ava_debug = { 11'h000, // 31:21
any_rstn_rr, // 20
local_rstn, // 19
pcie_rstn, // 18
pll_powerdown, // 16
npor_serdes_pll_locked, // 16
rc_pll_locked, // 15
busy_altgxb_reconfig, // 14
ltssm, // 13:9
test_out }; // 8:0
// (level:0) wire declarations...
reg L0_led;
reg [ 24: 0] alive_cnt;
reg alive_led;
wire any_rstn;
reg any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */;
reg any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */;
wire local_rstn = sys0_rstn;
wire refclk = pcie_clk;
assign pcie_tx_out = {tx_out3, tx_out2, tx_out1, tx_out0};
wire rx_in0 = pcie_rx_in[0];
wire rx_in1 = pcie_rx_in[1];
wire rx_in2 = pcie_rx_in[2];
wire rx_in3 = pcie_rx_in[3];
wire core_clk_out;
wire pld_clk = core_clk_out; //TODO: Check that pld_clk can be the 125 MHz output clock
assign ava_core_clk_out = core_clk_out;
assign ava_alive = alive_led;
assign ava_lnk_up = L0_led;
//assign test_in = 40'h0000000000; // All zeros provdes the "default behavior"
assign test_in = 40'h00_0000_00A8; // b7="safe_mode", b5=hip, b3=what altera does
//assign test_in = 40'h00000000A8; // Undocumented change suggested by Altera "CW" 2011-06-03
wire pclk_in = clk500_out; // For Gen2, drive pclk_in with clk500_out
wire phystatus_ext;
wire req_compliance_soft_ctrl;
wire [ 7: 0] rxdata0_ext;
wire [ 7: 0] rxdata1_ext;
wire [ 7: 0] rxdata2_ext;
wire [ 7: 0] rxdata3_ext;
wire rxdatak0_ext;
wire rxdatak1_ext;
wire rxdatak2_ext;
wire rxdatak3_ext;
wire rxelecidle0_ext;
wire rxelecidle1_ext;
wire rxelecidle2_ext;
wire rxelecidle3_ext;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire [ 2: 0] rxstatus0_ext;
wire [ 2: 0] rxstatus1_ext;
wire [ 2: 0] rxstatus2_ext;
wire [ 2: 0] rxstatus3_ext;
wire rxvalid0_ext;
wire rxvalid1_ext;
wire rxvalid2_ext;
wire rxvalid3_ext;
wire safe_mode;
wire set_compliance_mode;
wire [ 39: 0] test_in;
wire [ 8: 0] test_out_icm;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdetectrx_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
// (level:1) wire declarations...
wire [ 6: 0] cpl_err = 7'b0000000;
wire cpl_pending = 1'b0;
wire cpl_pending_icm;
wire fixedclk_serdes;
wire [ 11: 0] lmi_addr = 12'h000;
wire [ 31: 0] lmi_din = 32'h0000_0000;
wire lmi_rden = 1'b0;
wire lmi_wren = 1'b0;
wire lmi_ack;
wire [ 31: 0] lmi_dout;
wire [ 4: 0] open_aer_msi_num;
wire [ 7: 0] open_msi_stream_data0;
wire open_msi_stream_valid0;
wire [ 9: 0] open_pm_data;
wire open_rx_st_err0;
wire [ 4: 0] pex_msi_num = 5'b00000;
wire [ 4: 0] pex_msi_num_icm;
wire reconfig_clk;
wire reconfig_clk_locked;
wire rx_mask0;
wire rx_stream_ready0;
wire rx_stream_valid0;
wire [ 8: 0] test_out_int;
wire [ 35: 0] tx_stream_cred0;
wire [ 74: 0] tx_stream_data0 = 0;
wire [ 74: 0] tx_stream_data0_1 = 0;
wire tx_stream_ready0;
wire tx_stream_valid0;
wire pm_auxpwr = 1'b0;
wire [9:0] pm_data = 9'b000000000;
wire pm_event = 1'b0;
wire pme_to_cr = 1'b0;
// (level:2) wire declarations...
wire app_int_ack;
wire app_int_sts = 1'b0;
wire [4:0] app_msi_num = 5'b00000;
wire app_msi_req = 1'b0;
wire [2:0] app_msi_tc = 3'b000;
wire app_msi_ack;
wire busy_altgxb_reconfig;
wire clk250_out;
wire clk500_out;
wire crst;
wire data_valid;
wire dlup_exit;
wire [ 4: 0] gnd_hpg_ctrler;
wire gxb_powerdown;
wire hotrst_exit;
wire hotrst_exit_altr;
wire l2_exit;
wire [ 3: 0] lane_act;
wire [ 4: 0] ltssm;
wire npor;
wire npor_serdes_pll_locked;
wire offset_cancellation_reset;
wire open_rx_fifo_empty0;
wire open_rx_fifo_full0;
wire open_tx_fifo_full0;
wire [ 3: 0] open_tx_fifo_rdptr0;
wire [ 3: 0] open_tx_fifo_wrptr0;
wire otb0;
wire otb1;
wire pll_powerdown;
wire pme_to_sr;
wire [ 1: 0] powerdown_ext;
wire rate_ext;
wire rc_pll_locked;
wire [ 33: 0] reconfig_fromgxb;
wire [ 3: 0] reconfig_togxb;
wire [ 3: 0] rx_eqctrl_out;
wire [ 2: 0] rx_eqdcgain_out;
wire srst;
wire [ 8: 0] test_out;
wire [ 4: 0] tx_preemp_0t_out;
wire [ 4: 0] tx_preemp_1t_out;
wire [ 4: 0] tx_preemp_2t_out;
wire [ 2: 0] tx_vodctrl_out;
// (level:0) assignments...
assign any_rstn = pcie_rstn & local_rstn;
// (level:0) codes...
always @(posedge core_clk_out or negedge any_rstn)
begin
if (any_rstn == 0) begin
any_rstn_r <= 0;
any_rstn_rr <= 0;
end else begin
any_rstn_r <= 1;
any_rstn_rr <= any_rstn_r;
if (any_rstn_rr==0) begin
alive_cnt <= 0;
alive_led <= 0;
L0_led <= 0;
end else begin
alive_cnt <= alive_cnt +1;
alive_led <= alive_cnt[24];
L0_led <= (test_out_icm[4 : 0] == 5'b01111);
end
end
end
// (level:1) assignments...
assign otb0 = 1'b0;
assign otb1 = 1'b1;
assign test_out_icm = test_out_int;
assign test_out_int = test_out;
// These next three modules have been copied into the local dir and may be edited
// (level:1) codes...
pll1 reconfig_pll (
.c0 (reconfig_clk), // 50 MHz
.c1 (fixedclk_serdes), // 125 MHz
.inclk0 (sys0_clk), // 200 MHz in
.locked (reconfig_clk_locked)
);
// (level:2) assignments...
wire pipe_mode = 1'b0;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
assign offset_cancellation_reset = ~reconfig_clk_locked;
assign reconfig_fromgxb[33 : 17] = 0;
assign gnd_hpg_ctrler = 0;
assign gxb_powerdown = ~npor;
assign hotrst_exit_altr = hotrst_exit;
assign pll_powerdown = ~npor;
assign npor_serdes_pll_locked = pcie_rstn & local_rstn & rc_pll_locked;
assign npor = pcie_rstn & local_rstn;
// This next core has been copied into the local dir and may be edited
pcie_hip_s4gx_gen2_x4_128_rs_hip rs_hip (
.dlup_exit (dlup_exit),
.hotrst_exit (hotrst_exit_altr),
.l2_exit (l2_exit),
.ltssm (ltssm),
.npor (npor_serdes_pll_locked),
.pld_clk (pld_clk),
.test_sim (test_in[0]),
.app_rstn (ava_srstn), // out: Avalon application reset (active-low)
.crst (crst), // out: config reset to hard core...
.srst (srst) // out: sync reset to hard core...
);
// This next cores is from the core's pci_express_compiler-library...
// support IP from _plus (level:2)...
altpcie_reconfig_4sgx reconfig (
.busy (busy_altgxb_reconfig),
.data_valid (data_valid),
.logical_channel_address (3'b000),
.offset_cancellation_reset (offset_cancellation_reset),
.read (1'b0),
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb),
.reconfig_togxb (reconfig_togxb),
.rx_eqctrl (4'b0000),
.rx_eqctrl_out (rx_eqctrl_out),
.rx_eqdcgain (3'b000),
.rx_eqdcgain_out (rx_eqdcgain_out),
.tx_preemp_0t (5'b00000),
.tx_preemp_0t_out (tx_preemp_0t_out),
.tx_preemp_1t (5'b00000),
.tx_preemp_1t_out (tx_preemp_1t_out),
.tx_preemp_2t (5'b00000),
.tx_preemp_2t_out (tx_preemp_2t_out),
.tx_vodctrl (3'b000),
.tx_vodctrl_out (tx_vodctrl_out),
.write_all (1'b0)
);
// Instantiation of the unedited (level:3) core...
pcie_hip_s4gx_gen2_x4_128 epmap (
.app_int_ack (app_int_ack), .app_int_sts (app_int_sts), .app_msi_ack (app_msi_ack), .app_msi_num (app_msi_num), .app_msi_req (app_msi_req), .app_msi_tc (app_msi_tc),
.busy_altgxb_reconfig (busy_altgxb_reconfig), .cal_blk_clk (reconfig_clk), .clk250_out (clk250_out), .clk500_out (clk500_out), .core_clk_out (core_clk_out), .cpl_err (cpl_err),
.cpl_pending (cpl_pending), .crst (crst), .dlup_exit (dlup_exit), .fixedclk_serdes (fixedclk_serdes), .gxb_powerdown (gxb_powerdown), .hotrst_exit (hotrst_exit),
.hpg_ctrler (gnd_hpg_ctrler), .l2_exit (l2_exit), .lane_act (lane_act), .lmi_ack (lmi_ack), .lmi_addr (lmi_addr), .lmi_din (lmi_din),
.lmi_dout (lmi_dout), .lmi_rden (lmi_rden), .lmi_wren (lmi_wren), .ltssm (ltssm), .npor (npor), .pclk_in (pclk_in),
.pex_msi_num (pex_msi_num), .phystatus_ext (phystatus_ext), .pipe_mode (pipe_mode), .pld_clk (pld_clk), .pll_powerdown (pll_powerdown), .pm_auxpwr (pm_auxpwr),
.pm_data (pm_data), .pm_event (pm_event), .pme_to_cr (pme_to_cr), .pme_to_sr (pme_to_sr), .powerdown_ext (powerdown_ext), .rate_ext (rate_ext),
.rc_pll_locked (rc_pll_locked), .reconfig_clk (reconfig_clk), .reconfig_fromgxb (reconfig_fromgxb[16 : 0]), .reconfig_togxb (reconfig_togxb), .refclk (refclk), .rx_fifo_empty0 (open_rx_fifo_empty0),
.rx_fifo_full0 (open_rx_fifo_full0), .rx_in0 (rx_in0), .rx_in1 (rx_in1), .rx_in2 (rx_in2), .rx_in3 (rx_in3), .rx_st_bardec0 (rx_st_bardec0),
.rx_st_be0 (rx_st_be0), .rx_st_data0 (rx_st_data0), .rx_st_empty0 (rx_st_empty0), .rx_st_eop0 (rx_st_eop0), .rx_st_err0 (rx_st_err0), .rx_st_mask0 (rx_st_mask0),
.rx_st_ready0 (rx_st_ready0), .rx_st_sop0 (rx_st_sop0), .rx_st_valid0 (rx_st_valid0), .rxdata0_ext (rxdata0_ext), .rxdata1_ext (rxdata1_ext), .rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext), .rxdatak0_ext (rxdatak0_ext), .rxdatak1_ext (rxdatak1_ext), .rxdatak2_ext (rxdatak2_ext), .rxdatak3_ext (rxdatak3_ext), .rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext), .rxelecidle2_ext (rxelecidle2_ext), .rxelecidle3_ext (rxelecidle3_ext), .rxpolarity0_ext (rxpolarity0_ext), .rxpolarity1_ext (rxpolarity1_ext), .rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext), .rxstatus0_ext (rxstatus0_ext), .rxstatus1_ext (rxstatus1_ext), .rxstatus2_ext (rxstatus2_ext), .rxstatus3_ext (rxstatus3_ext), .rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext), .rxvalid2_ext (rxvalid2_ext), .rxvalid3_ext (rxvalid3_ext), .srst (srst), .test_in (test_in), .test_out (test_out),
.tl_cfg_add (tl_cfg_add), .tl_cfg_ctl (tl_cfg_ctl), .tl_cfg_ctl_wr (tl_cfg_ctl_wr), .tl_cfg_sts (tl_cfg_sts), .tl_cfg_sts_wr (tl_cfg_sts_wr), .tx_cred0 (tx_cred0),
.tx_fifo_empty0 (tx_fifo_empty0), .tx_fifo_full0 (open_tx_fifo_full0), .tx_fifo_rdptr0 (open_tx_fifo_rdptr0), .tx_fifo_wrptr0 (open_tx_fifo_wrptr0), .tx_out0 (tx_out0), .tx_out1 (tx_out1),
.tx_out2 (tx_out2), .tx_out3 (tx_out3), .tx_st_data0 (tx_st_data0), .tx_st_empty0 (tx_st_empty0), .tx_st_eop0 (tx_st_eop0), .tx_st_err0 (tx_st_err0),
.tx_st_ready0 (tx_st_ready0), .tx_st_sop0 (tx_st_sop0), .tx_st_valid0 (tx_st_valid0), .txcompl0_ext (txcompl0_ext), .txcompl1_ext (txcompl1_ext), .txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext), .txdata0_ext (txdata0_ext), .txdata1_ext (txdata1_ext), .txdata2_ext (txdata2_ext), .txdata3_ext (txdata3_ext), .txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext), .txdatak2_ext (txdatak2_ext), .txdatak3_ext (txdatak3_ext), .txdetectrx_ext (txdetectrx_ext), .txelecidle0_ext (txelecidle0_ext), .txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext), .txelecidle3_ext (txelecidle3_ext)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCIN_1_V
`define SKY130_FD_SC_MS__FAHCIN_1_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog wrapper for fahcin with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fahcin.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCIN_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_SYMBOL_V
`define SKY130_FD_SC_LS__FILL_DIODE_SYMBOL_V
/**
* fill_diode: Fill diode.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fill_diode ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_FUNCTIONAL_V
`define SKY130_FD_SC_HS__CLKINV_FUNCTIONAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkinv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDLCLKP_1_V
`define SKY130_FD_SC_MS__SDLCLKP_1_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdlclkp_1 (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdlclkp base (
.GCLK(GCLK),
.SCE(SCE),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDLCLKP_1_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_rfifo.v (Modified from uart_fifo.v) ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_rfifo.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.4 2003/07/11 18:20:26 gorban
// added clearing the receiver fifo statuses on resets
//
// Revision 1.3 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
// flags FIFO
reg [2:0] fifo[fifo_depth-1:0];
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
fifo[0] <= #1 0;
fifo[1] <= #1 0;
fifo[2] <= #1 0;
fifo[3] <= #1 0;
fifo[4] <= #1 0;
fifo[5] <= #1 0;
fifo[6] <= #1 0;
fifo[7] <= #1 0;
fifo[8] <= #1 0;
fifo[9] <= #1 0;
fifo[10] <= #1 0;
fifo[11] <= #1 0;
fifo[12] <= #1 0;
fifo[13] <= #1 0;
fifo[14] <= #1 0;
fifo[15] <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
fifo[0] <= #1 0;
fifo[1] <= #1 0;
fifo[2] <= #1 0;
fifo[3] <= #1 0;
fifo[4] <= #1 0;
fifo[5] <= #1 0;
fifo[6] <= #1 0;
fifo[7] <= #1 0;
fifo[8] <= #1 0;
fifo[9] <= #1 0;
fifo[10] <= #1 0;
fifo[11] <= #1 0;
fifo[12] <= #1 0;
fifo[13] <= #1 0;
fifo[14] <= #1 0;
fifo[15] <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
fifo[top] <= #1 data_in[2:0];
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= #1 0;
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
fifo[top] <= #1 data_in[2:0];
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
// please note though that data_out is only valid one clock after pop signal
assign data_out = {data8_out,fifo[bottom]};
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
// a 1 is returned if any of the error bits in the fifo is 1
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_4_V
`define SKY130_FD_SC_MS__FILL_DIODE_4_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_diode_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_diode_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_4_V
|
`include "bsg_defines.v"
module bsg_mux #(parameter `BSG_INV_PARAM(width_p)
, els_p=1
, harden_p = 0
, balanced_p = 0
, lg_els_lp=`BSG_SAFE_CLOG2(els_p)
)
(
input [els_p-1:0][width_p-1:0] data_i
,input [lg_els_lp-1:0] sel_i
,output [width_p-1:0] data_o
);
genvar j;
if ((els_p == 4) && (harden_p == 1) && (balanced_p))
begin : fi
for (j = 0; j < width_p; j=j+1)
begin: rof
// fast, but not too extreme
SC7P5T_MUX4X4_SSC16L BSG_BAL41MUX_BSG_DONT_TOUCH (.D0(data_i[0][j]), .D1(data_i[1][j]), .D2(data_i[2][j]), .D3(data_i[3][j]), .S0(sel_i[0]), .S1(sel_i[1]), .Z(data_o[j]));
end
end
else
begin : nofi
if (els_p == 1) begin
assign data_o = data_i;
wire unused = sel_i;
end
else begin
assign data_o = data_i[sel_i];
end
// synopsys translate_off
initial
assert(balanced_p == 0)
else $error("%m warning: synthesizable implementation of bsg_mux does not support balanced_p");
// synopsys translate_on
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_mux)
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_tx_channel (
// dac interface
dac_clk,
dac_rst,
dac_dds_data,
// processor interface
dac_dds_enable,
dac_dds_data_enable,
dac_dds_format,
dac_dds_pattenb,
dac_lb_enb,
dac_pn_enb,
// bus interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
output [15:0] dac_dds_data;
// processor interface
input dac_dds_enable;
input dac_dds_data_enable;
input dac_dds_format;
input dac_dds_pattenb;
output dac_lb_enb;
output dac_pn_enb;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal signals
wire [15:0] dac_dds_patt_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [ 3:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_patt_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [ 3:0] dac_dds_scale_2_s;
// single channel dds
axi_ad9361_tx_dds #(.DP_DISABLE(DP_DISABLE)) i_tx_dds (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_data (dac_dds_data),
.dac_dds_enable (dac_dds_enable),
.dac_dds_data_enable (dac_dds_data_enable),
.dac_dds_format (dac_dds_format),
.dac_dds_pattenb (dac_dds_pattenb),
.dac_dds_patt_1 (dac_dds_patt_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_patt_2 (dac_dds_patt_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_dds_scale_2 (dac_dds_scale_2_s));
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_dds_patt_1 (dac_dds_patt_1_s),
.dac_dds_patt_2 (dac_dds_patt_2_s),
.dac_lb_enb (dac_lb_enb),
.dac_pn_enb (dac_pn_enb),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`default_nettype none
module sdi_debugger(
//Clock
input wire iCLOCK,
input wire inRESET,
//To Core
output wire oDEBUG_CMD_REQ,
input wire iDEBUG_CMD_BUSY,
output wire [3:0] oDEBUG_CMD_COMMAND,
output wire [7:0] oDEBUG_CMD_TARGET,
output wire [31:0] oDEBUG_CMD_DATA,
input wire iDEBUG_CMD_VALID,
input wire iDEBUG_CMD_ERROR,
input wire [31:0] iDEBUG_CMD_DATA,
//To Uart
input wire iDEBUG_UART_RXD,
output wire oDEBUG_UART_TXD,
input wire iDEBUG_PARA_REQ,
output wire oDEBUG_PARA_BUSY,
input wire [7:0] iDEBUG_PARA_CMD,
input wire [31:0] iDEBUG_PARA_DATA,
output wire oDEBUG_PARA_VALID,
input wire iDEBUG_PARA_BUSY,
output wire oDEBUG_PARA_ERROR,
output wire [31:0] oDEBUG_PARA_DATA
);
//Command(ToCore Debugger Unit)
localparam CORE_DEBUG_CMD_READ_REG = 4'h0;
localparam CORE_DEBUG_CMD_WRITE_REG = 4'h1;
localparam CORE_DEBUG_CMD_GO_CORE = 4'h8;
localparam CORE_DEBUG_CMD_INTGO_CORE = 4'h9;
localparam CORE_DEBUG_CMD_SINGLESTEP_CORE = 4'hA;
localparam CORE_DEBUG_CMD_STOP_CORE = 4'hF;
//Target Register
localparam CORE_DEBUG_TARGET_GR0 = 8'd0;
localparam CORE_DEBUG_TARGET_GR1 = 8'd1;
localparam CORE_DEBUG_TARGET_GR2 = 8'd2;
localparam CORE_DEBUG_TARGET_GR3 = 8'd3;
localparam CORE_DEBUG_TARGET_GR4 = 8'd4;
localparam CORE_DEBUG_TARGET_GR5 = 8'd5;
localparam CORE_DEBUG_TARGET_GR6 = 8'd6;
localparam CORE_DEBUG_TARGET_GR7 = 8'd7;
localparam CORE_DEBUG_TARGET_GR8 = 8'd8;
localparam CORE_DEBUG_TARGET_GR9 = 8'd9;
localparam CORE_DEBUG_TARGET_GR10 = 8'd10;
localparam CORE_DEBUG_TARGET_GR11 = 8'd11;
localparam CORE_DEBUG_TARGET_GR12 = 8'd12;
localparam CORE_DEBUG_TARGET_GR13 = 8'd13;
localparam CORE_DEBUG_TARGET_GR14 = 8'd14;
localparam CORE_DEBUG_TARGET_GR15 = 8'd15;
localparam CORE_DEBUG_TARGET_GR16 = 8'd16;
localparam CORE_DEBUG_TARGET_GR17 = 8'd17;
localparam CORE_DEBUG_TARGET_GR18 = 8'd18;
localparam CORE_DEBUG_TARGET_GR19 = 8'd19;
localparam CORE_DEBUG_TARGET_GR20 = 8'd20;
localparam CORE_DEBUG_TARGET_GR21 = 8'd21;
localparam CORE_DEBUG_TARGET_GR22 = 8'd22;
localparam CORE_DEBUG_TARGET_GR23 = 8'd23;
localparam CORE_DEBUG_TARGET_GR24 = 8'd24;
localparam CORE_DEBUG_TARGET_GR25 = 8'd25;
localparam CORE_DEBUG_TARGET_GR26 = 8'd26;
localparam CORE_DEBUG_TARGET_GR27 = 8'd27;
localparam CORE_DEBUG_TARGET_GR28 = 8'd28;
localparam CORE_DEBUG_TARGET_GR29 = 8'd29;
localparam CORE_DEBUG_TARGET_GR30 = 8'd30;
localparam CORE_DEBUG_TARGET_GR31 = 8'd31;
localparam CORE_DEBUG_TARGET_CPUIDR = 8'd64;
localparam CORE_DEBUG_TARGET_TIDR = 8'd65;
localparam CORE_DEBUG_TARGET_FLAGR = 8'd66;
localparam CORE_DEBUG_TARGET_PCR = 8'd67;
localparam CORE_DEBUG_TARGET_SPR = 8'd68;
localparam CORE_DEBUG_TARGET_PSR = 8'd69;
localparam CORE_DEBUG_TARGET_IOSAR = 8'd70;
localparam CORE_DEBUG_TARGET_PDTR = 8'd71;
localparam CORE_DEBUG_TARGET_KPDTR = 8'd72;
localparam CORE_DEBUG_TARGET_TISR = 8'd73;
localparam CORE_DEBUG_TARGET_IDTR = 8'd74;
localparam CORE_DEBUG_TARGET_FI0R = 8'd75;
localparam CORE_DEBUG_TARGET_FI1R = 8'd76;
localparam CORE_DEBUG_TARGET_FRCLR = 8'd77;
localparam CORE_DEBUG_TARGET_FRCHR = 8'd78;
localparam CORE_DEBUG_TARGET_PTIDR = 8'd128;
localparam CORE_DEBUG_TARGET_PFLAGR = 8'd129;
localparam CORE_DEBUG_TARGET_PPCR = 8'd130;
localparam CORE_DEBUG_TARGET_PPSR = 8'd131;
localparam CORE_DEBUG_TARGET_PPDTR = 8'd132;
//Debugger Native Command
localparam L_PARAM_CMDCODE_ID = 8'h49;
localparam L_PARAM_CMDCODE_AC = 8'h41;
localparam L_PARAM_CMDCODE_NP = 8'h4e;
localparam L_PARAM_CMDCODE_RR = 8'h52;
localparam L_PARAM_CMDCODE_RW = 8'h57;
localparam L_PARAM_CMDCODE_SE = 8'h53;
localparam L_PARAM_CMDCODE_BE = 8'h42;
localparam L_PARAM_CMDCODE_SB = 8'h50;
localparam L_PARAM_MAIN_STT_IDLE = 4'h0;
localparam L_PARAM_MAIN_STT_ACTIVE = 4'h1;
localparam L_PARAM_MAIN_STT_NOP = 4'h2;
localparam L_PARAM_MAIN_STT_REGISTER_READ = 4'h3;
localparam L_PARAM_MAIN_STT_REGISTER_WRITE = 4'h4;
localparam L_PARAM_MAIN_STT_STEP_EXECUTE = 4'h5;
localparam L_PARAM_MAIN_STT_BREAK_EXECUTE = 4'h6;
localparam L_PARAM_MAIN_STT_SET_BREAK_POINT = 4'h7;
localparam L_PARAM_MAIN_STT_ERROR = 4'h8;
localparam L_PARAM_CORE_ACK_STT_IDLE = 2'h0;
localparam L_PARAM_CORE_ACK_STT_WAIT = 2'h1;
localparam L_PARAM_CORE_ACK_STT_IF_ACK = 2'h2;
//Interface
wire if2ctrl_req;
wire ctrl2if_busy;
wire [7:0] if2ctrl_cmd;
wire [31:0] if2ctrl_data;
wire ctrl2if_valid;
wire if2ctrl_busy;
wire ctrl2if_error;
wire [31:0] ctrl2if_data;
reg [31:0] b_if_req_data;
reg [3:0] b_cmd_state;
reg [1:0] b_ack_state;
reg core_buff_error;
reg [31:0] core_buff_data;
reg core_req_req;
reg [3:0] core_req_cmd;
reg [31:0] core_req_data;
wire interface_req_condition = if2ctrl_req && !ctrl2if_busy && !iDEBUG_CMD_BUSY;
wire ack_state_start_condition = (b_cmd_state != L_PARAM_MAIN_STT_IDLE) && (b_cmd_state != L_PARAM_MAIN_STT_ACTIVE) && (b_cmd_state != L_PARAM_MAIN_STT_NOP) && (b_cmd_state != L_PARAM_MAIN_STT_ERROR);
/****************************************************************
Interface Select
****************************************************************/
sdi_interface_control INTERFACE_CONTROL(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Interface Select
.iIF_SELECT(1'b1), //(0)UART | (1)PARALLEL
//UART
.iDEBUG_UART_RXD(iDEBUG_UART_RXD),
.oDEBUG_UART_TXD(oDEBUG_UART_TXD),
//Parallel
.iDEBUG_PARA_REQ(iDEBUG_PARA_REQ),
.oDEBUG_PARA_BUSY(oDEBUG_PARA_BUSY),
.iDEBUG_PARA_CMD(iDEBUG_PARA_CMD),
.iDEBUG_PARA_DATA(iDEBUG_PARA_DATA),
.oDEBUG_PARA_VALID(oDEBUG_PARA_VALID),
.iDEBUG_PARA_BUSY(iDEBUG_PARA_BUSY),
.oDEBUG_PARA_ERROR(oDEBUG_PARA_ERROR),
.oDEBUG_PARA_DATA(oDEBUG_PARA_DATA),
//Output Common Interface
.oDEBUG_COM_REQ(if2ctrl_req),
.iDEBUG_COM_BUSY(ctrl2if_busy),
.oDEBUG_COM_CMD(if2ctrl_cmd),
.oDEBUG_COM_DATA(if2ctrl_data),
.iDEBUG_COM_VALID(ctrl2if_valid),
.oDEBUG_COM_BUSY(if2ctrl_busy),
.iDEBUG_COM_ERROR(ctrl2if_error),
.iDEBUG_COM_DATA(ctrl2if_data)
);
assign ctrl2if_busy = !(b_cmd_state == L_PARAM_MAIN_STT_IDLE || b_cmd_state == L_PARAM_MAIN_STT_ACTIVE) || b_ack_state != L_PARAM_CORE_ACK_STT_IDLE;
assign ctrl2if_valid = b_ack_state == L_PARAM_CORE_ACK_STT_IF_ACK;
assign ctrl2if_error = 1'b0;
assign ctrl2if_data = core_buff_data;
/****************************************************************
Uart Command Check
****************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_if_req_data <= 32'h0;
end
else begin
if(b_cmd_state == L_PARAM_MAIN_STT_ACTIVE && !(iDEBUG_CMD_VALID && iDEBUG_CMD_ERROR) && interface_req_condition)begin
b_if_req_data <= if2ctrl_data;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
if(!inRESET)begin
b_cmd_state <= L_PARAM_MAIN_STT_IDLE;
end
else begin
case(b_cmd_state)
L_PARAM_MAIN_STT_IDLE:
begin
if(interface_req_condition && if2ctrl_cmd == L_PARAM_CMDCODE_AC)begin
b_cmd_state <= L_PARAM_MAIN_STT_ACTIVE;
end
end
L_PARAM_MAIN_STT_ACTIVE:
begin
//Error Check
if(iDEBUG_CMD_VALID && iDEBUG_CMD_ERROR)begin
b_cmd_state <= L_PARAM_MAIN_STT_ERROR;
end
//Request Check
else if(interface_req_condition)begin
if(if2ctrl_cmd == L_PARAM_MAIN_STT_IDLE)begin
b_cmd_state <= L_PARAM_MAIN_STT_IDLE;
end
else if(if2ctrl_cmd == L_PARAM_CMDCODE_NP)begin
b_cmd_state <= L_PARAM_MAIN_STT_NOP;
end
else if(if2ctrl_cmd == L_PARAM_CMDCODE_RR)begin
b_cmd_state <= L_PARAM_MAIN_STT_REGISTER_READ;
end
else if(if2ctrl_cmd == L_PARAM_CMDCODE_RW)begin
b_cmd_state <= L_PARAM_MAIN_STT_REGISTER_WRITE;
end
else if(if2ctrl_cmd == L_PARAM_CMDCODE_SE)begin
b_cmd_state <= L_PARAM_MAIN_STT_STEP_EXECUTE;
end
else if(if2ctrl_cmd == L_PARAM_CMDCODE_BE)begin
b_cmd_state <= L_PARAM_MAIN_STT_BREAK_EXECUTE;
end
else if(if2ctrl_cmd == L_PARAM_CMDCODE_SB)begin
b_cmd_state <= L_PARAM_MAIN_STT_SET_BREAK_POINT;
end
end
end
L_PARAM_MAIN_STT_NOP:
begin
b_cmd_state <= L_PARAM_MAIN_STT_ACTIVE;
end
L_PARAM_MAIN_STT_REGISTER_READ:
begin
if(!iDEBUG_CMD_BUSY)begin
b_cmd_state <= L_PARAM_MAIN_STT_ACTIVE;
end
end
L_PARAM_MAIN_STT_REGISTER_WRITE:
begin
if(!iDEBUG_CMD_BUSY)begin
b_cmd_state <= L_PARAM_MAIN_STT_ACTIVE;
end
end
L_PARAM_MAIN_STT_STEP_EXECUTE:
begin
if(!iDEBUG_CMD_BUSY)begin
b_cmd_state <= L_PARAM_MAIN_STT_ACTIVE;
end
end
L_PARAM_MAIN_STT_BREAK_EXECUTE:
begin
if(!iDEBUG_CMD_BUSY)begin
b_cmd_state <= L_PARAM_MAIN_STT_ACTIVE;
end
end
L_PARAM_MAIN_STT_SET_BREAK_POINT:
begin
if(!iDEBUG_CMD_BUSY)begin
b_cmd_state <= L_PARAM_MAIN_STT_ACTIVE;
end
end
L_PARAM_MAIN_STT_ERROR:
begin
b_cmd_state <= L_PARAM_MAIN_STT_IDLE;
end
default:
begin
b_cmd_state <= L_PARAM_MAIN_STT_IDLE;
end
endcase
end
end
end //CMD State
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ack_state <= L_PARAM_CORE_ACK_STT_IDLE;
end
else begin
case(b_ack_state)
L_PARAM_CORE_ACK_STT_IDLE:
begin
if(ack_state_start_condition)begin
b_ack_state <= L_PARAM_CORE_ACK_STT_WAIT;
end
end
L_PARAM_CORE_ACK_STT_WAIT:
begin
if(iDEBUG_CMD_VALID)begin
b_ack_state <= L_PARAM_CORE_ACK_STT_IF_ACK;
end
end
L_PARAM_CORE_ACK_STT_IF_ACK:
begin
b_ack_state <= L_PARAM_CORE_ACK_STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
core_buff_error <= 1'b0;
core_buff_data <= 32'h0;
end
else begin
if(iDEBUG_CMD_VALID)begin
core_buff_error <= iDEBUG_CMD_ERROR;
core_buff_data <= iDEBUG_CMD_DATA;
end
end
end
always @* begin
if(!iDEBUG_CMD_BUSY)begin
case(b_cmd_state)
L_PARAM_MAIN_STT_REGISTER_READ:
begin
core_req_req = 1'b1;
core_req_cmd = CORE_DEBUG_CMD_READ_REG;
core_req_data = b_if_req_data;
end
L_PARAM_MAIN_STT_REGISTER_WRITE:
begin
core_req_req = 1'b1;
core_req_cmd = CORE_DEBUG_CMD_WRITE_REG;
core_req_data = b_if_req_data;
end
L_PARAM_MAIN_STT_STEP_EXECUTE:
begin
core_req_req = 1'b1;
core_req_cmd = CORE_DEBUG_CMD_SINGLESTEP_CORE;
core_req_data = b_if_req_data;
end
L_PARAM_MAIN_STT_BREAK_EXECUTE:
begin
core_req_req = 1'b1;
core_req_cmd = CORE_DEBUG_CMD_GO_CORE;
core_req_data = b_if_req_data;
end
L_PARAM_MAIN_STT_SET_BREAK_POINT:
begin
core_req_req = 1'b1;
core_req_cmd = CORE_DEBUG_CMD_GO_CORE;
core_req_data = b_if_req_data;
end
default:
begin
core_req_req = 1'b0;
core_req_cmd = 4'h0;
core_req_data = 32'h0;
end
endcase
end
else begin
core_req_req = 1'b0;
core_req_cmd = 4'h0;
core_req_data = 32'h0;
end
end
assign oDEBUG_CMD_REQ = core_req_req;
assign oDEBUG_CMD_COMMAND = core_req_cmd;
assign oDEBUG_CMD_TARGET = core_req_data[7:0];//b_main_counter;
assign oDEBUG_CMD_DATA = 32'h0;
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BAI_TB_V
`define SKY130_FD_SC_MS__O21BAI_TB_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21bai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ms__o21bai dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BAI_TB_V
|
// part of NeoGS flash programmer project (c) 2014 lvd^NedoPC
//
// rom controller
//
// !!!!!!!!!!!enables addr bus as soon as reset is removed!!!!!!!
module rom
(
input wire clk,
input wire rst_n,
input wire wr_addr,
input wire wr_data,
input wire rd_data,
input wire [ 7:0] wr_buffer,
output reg [ 7:0] rd_buffer,
input wire autoinc_ena,
output wire [18:0] rom_a,
inout wire [ 7:0] rom_d,
output reg rom_cs_n,
output reg rom_oe_n,
output reg rom_we_n
);
reg [7:0] wrdata;
wire [7:0] rddata;
reg enadata;
reg [18:0] addr;
reg [18:0] next_addr;
reg enaaddr;
reg [2:0] addr_phase;
reg rnw;
reg [6:0] rw_phase;
// dbus control
assign rom_d = enadata ? wrdata : 8'bZZZZ_ZZZZ;
assign rddata = rom_d;
// abus control
assign rom_a = enaaddr ? addr : {19{1'bZ}};
// enaaddr control
always @(posedge clk, negedge rst_n)
if( !rst_n )
enaaddr <= 1'b0;
else
enaaddr <= 1'b1;
// address phase (points which one of 3byte address to write into)
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
addr_phase <= 3'b001;
end
else
case( {wr_addr, wr_data, rd_data} )
3'b100: addr_phase <= {addr_phase[1:0], addr_phase[2] };
3'b010,3'b001: addr_phase <= 3'b001;
default: addr_phase <= addr_phase;
endcase
// address control
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
next_addr <= 19'd0;
end
else
case( {wr_addr, wr_data, rd_data} )
3'b100: begin
next_addr[ 7:0 ] <= addr_phase[0] ? wr_buffer[7:0] : next_addr[ 7:0 ];
next_addr[15:8 ] <= addr_phase[1] ? wr_buffer[7:0] : next_addr[15:8 ];
next_addr[18:16] <= addr_phase[2] ? wr_buffer[2:0] : next_addr[18:16];
end
3'b010, 3'b001: if( autoinc_ena ) next_addr <= next_addr + 19'd1;
default: next_addr <= next_addr;
endcase
// address output register
always @(posedge clk)
if( wr_data || rd_data )
addr <= next_addr;
// read/write sequence
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
rw_phase <= 'd0;
rnw <= 1'b1;
end
else if( rd_data || wr_data )
begin
rw_phase <= 'd1;
rnw <= rd_data;
end
else
begin
rw_phase <= rw_phase<<1;
end
// output control
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
enadata <= 1'b0;
end
else if( rw_phase[0] )
begin
enadata <= !rnw;
end
else if( rw_phase[6] )
begin
enadata <= 1'b0;
end
//
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
rom_cs_n <= 1'b1;
rom_oe_n <= 1'b1;
rom_we_n <= 1'b1;
end
else if( rw_phase[1] )
begin
rom_cs_n <= 1'b0;
rom_oe_n <= !rnw;
rom_we_n <= rnw;
end
else if( rw_phase[6] )
begin
rom_cs_n <= 1'b1;
rom_oe_n <= 1'b1;
rom_we_n <= 1'b1;
end
//
always @(posedge clk)
if( wr_data )
wrdata <= wr_buffer;
// input control
always @(posedge clk)
if( rw_phase[6] && rnw )
rd_buffer <= rddata;
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions: Reset_Delay
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
input iCLK;
input iRST;
output reg oRST_0;
output reg oRST_1;
output reg oRST_2;
reg [31:0] Cont;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
Cont <= 0;
oRST_0 <= 0;
oRST_1 <= 0;
oRST_2 <= 0;
end
else
begin
if(Cont!=32'h114FFFF)
Cont <= Cont+1;
if(Cont>=32'h1FFFFF)
oRST_0 <= 1;
if(Cont>=32'h2FFFFF)
oRST_1 <= 1;
if(Cont>=32'h114FFFF)
oRST_2 <= 1;
end
end
endmodule |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* *** NOT FOR SYNTHESIS ***
*
* Traffic Sink
*
* Collects incoming packets and produces statistics.
*
* - check flit id's are sequential
*
*/
//`include "parameters.v"
module LAG_traffic_sink (flit_in, cntrl_out, rec_count, stats, clk, rst_n);
parameter xdim = 4;
parameter ydim = 4;
parameter xpos = 0;
parameter ypos = 0;
parameter warmup_packets = 100;
parameter measurement_packets = 1000;
parameter router_num_pls_on_exit = 1;
input flit_t flit_in [router_num_pls_on_exit-1:0];
output chan_cntrl_t cntrl_out;
output sim_stats_t stats;
input clk, rst_n;
output integer rec_count;
integer expected_flit_id [router_num_pls_on_exit-1:0];
integer head_injection_time [router_num_pls_on_exit-1:0];
integer latency, sys_time;
integer j, i;
genvar ch;
for (ch=0; ch<router_num_pls; ch++) begin:flow_control
always@(posedge clk) begin
if (!rst_n) begin
cntrl_out.credits[ch] <= 0;
end else begin
if (flit_in[ch].control.valid) begin
if (ch < router_num_pls_on_exit) begin
cntrl_out.credits[ch] <= 1;
end else begin
$display ("%m: Error: Flit Channel ID is out-of-range for exit from network!");
$display ("Channel ID = %1d (router_num_pls_on_exit=%1d)", ch, router_num_pls_on_exit);
$finish;
end
end else begin
cntrl_out.credits[ch] <= 0;
end
end
end
end
always@(posedge clk) begin
if (!rst_n) begin
rec_count=0;
stats.total_latency=0;
stats.total_hops=0;
stats.max_hops=0;
stats.min_hops=MAXINT;
stats.max_latency=0;
stats.min_latency=MAXINT;
stats.measure_start=-1;
stats.measure_end=-1;
stats.flit_count=0;
for (j=0; j<router_num_pls_on_exit; j++) begin
expected_flit_id[j]=1;
head_injection_time[j]=-1;
end
for (j=0; j<(xdim+ydim); j++) begin
stats.total_lat_for_hop_count[j]=0;
stats.total_packets_with_hop_count[j]=0;
end
for (j=0; j<=100; j++) begin
stats.lat_freq[j]=0;
end
sys_time = 0;
end else begin // if (!rst_n)
sys_time++;
for (i=0; i<router_num_pls_on_exit; i++) begin
if (flit_in[i].control.valid) begin
//$display ("%m: Packet %d arrived!!!", rec_count);
//
// check flit was destined for this node!
//
if ((flit_in[i].debug.xdest!=xpos)||(flit_in[i].debug.ydest!=ypos)) begin
$display ("%m: Error: Flit arrived at wrong destination!");
$finish;
end
//
// check flit didn't originate at this node
//
if ((flit_in[i].debug.xdest==flit_in[i].debug.xsrc)&&
(flit_in[i].debug.ydest==flit_in[i].debug.ysrc)) begin
$display ("%m: Error: Received flit originated from this node?");
$finish;
end
//
// check flits for each packet are received in order
//
if (flit_in[i].debug.flit_id != expected_flit_id[i]) begin
$display ("%m: Error: Out of sequence flit received? (packet generated at %1d,%1d)",
flit_in[i].debug.xsrc, flit_in[i].debug.ysrc);
$display ("-- Flit ID = %1d, Expected = %1d", flit_in[i].debug.flit_id, expected_flit_id[i]);
$display ("-- Packet ID = %1d", flit_in[i].debug.packet_id);
$finish;
end else begin
// $display ("%m: Rec: Flit ID = %1d, Packet ID = %1d, PL ID=%1d",
// flit_in.debug.flit_id, flit_in.debug.packet_id, flit_in.control.pl_id);
end
expected_flit_id[i]++;
// $display ("rec flit");
// #####################################################################
// Head of new packet has arrived
// #####################################################################
if (flit_in[i].debug.flit_id==1) begin
// $display ("%m: new head, current_pl=%1d, inject_time=%1d", current_pl, flit_in.debug.inject_time);
head_injection_time[i] = flit_in[i].debug.inject_time;
end
// count all flits received in measurement period
if ((flit_in[i].debug.packet_id>warmup_packets) && (stats.measure_start==-1)) stats.measure_start= sys_time;
if (flit_in[i].debug.packet_id<=warmup_packets+measurement_packets)
if (stats.measure_start!=-1) stats.flit_count++;
// #####################################################################
// Tail of packet has arrived
// Remember, latency = (tail arrival time) - (head injection time)
// #####################################################################
if (flit_in[i].control.tail) begin
// $display ("%m: Tail Rec, Expected = 1");
expected_flit_id[i]=1;
if ((flit_in[i].debug.packet_id>warmup_packets) &&
(flit_in[i].debug.packet_id<=warmup_packets+measurement_packets)) begin
rec_count++;
// time last measurement packet was received
stats.measure_end = sys_time;
//
// gather latency stats.
//
latency = sys_time - head_injection_time[i];
stats.total_latency = stats.total_latency + latency;
stats.min_latency = min (stats.min_latency, latency);
stats.max_latency = max (stats.max_latency, latency);
// $display ("%m: latency=%1d, sys_time=%1d, head_time[%1d]=%1d", latency, sys_time,
// current_pl, head_injection_time[current_pl]);
//
// display progress estimate
//
if (rec_count%(measurement_packets/100)==0)
$display ("%1d: %m: %1.2f%% complete (this packet's latency was %1d)", sys_time,
$itor(rec_count*100)/$itor(measurement_packets),
latency);
//
// sum latencies for different packet distances (and keep total distance travelled by all packets)
//
// $display ("This packet travelled %1d hops", flit_in.debug.hops);
stats.total_hops = stats.total_hops + flit_in[i].debug.hops;
stats.min_hops = min (stats.min_hops, flit_in[i].debug.hops);
stats.max_hops = max (stats.max_hops, flit_in[i].debug.hops);
stats.total_lat_for_hop_count[flit_in[i].debug.hops]=
stats.total_lat_for_hop_count[flit_in[i].debug.hops]+latency;
stats.total_packets_with_hop_count[flit_in[i].debug.hops]++;
//
// bin latencies
//
stats.lat_freq[min(latency, 100)]++;
end
end // if (flit_in.control.tail)
end // if flit valid
end //for
end //if(!rst_n)
end //always
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
// module, then calculates a CRC on the Test module's outputs.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by ____YOUR_NAME_HERE____.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [31:0] in;
output reg [31:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Ethernet demultiplexer
*/
module eth_demux #
(
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire [ID_WIDTH-1:0] s_eth_payload_axis_tid,
input wire [DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
input wire [USER_WIDTH-1:0] s_eth_payload_axis_tuser,
/*
* Ethernet frame outputs
*/
output wire [M_COUNT-1:0] m_eth_hdr_valid,
input wire [M_COUNT-1:0] m_eth_hdr_ready,
output wire [M_COUNT*48-1:0] m_eth_dest_mac,
output wire [M_COUNT*48-1:0] m_eth_src_mac,
output wire [M_COUNT*16-1:0] m_eth_type,
output wire [M_COUNT*DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire [M_COUNT-1:0] m_eth_payload_axis_tvalid,
input wire [M_COUNT-1:0] m_eth_payload_axis_tready,
output wire [M_COUNT-1:0] m_eth_payload_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_eth_payload_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_eth_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire drop,
input wire [$clog2(M_COUNT)-1:0] select
);
parameter CL_M_COUNT = $clog2(M_COUNT);
reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
reg drop_reg = 1'b0, drop_ctl, drop_next;
reg frame_reg = 1'b0, frame_ctl, frame_next;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg [M_COUNT-1:0] m_eth_hdr_valid_reg = 0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg [M_COUNT-1:0] m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg && enable;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg && enable;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = {M_COUNT{m_eth_dest_mac_reg}};
assign m_eth_src_mac = {M_COUNT{m_eth_src_mac_reg}};
assign m_eth_type = {M_COUNT{m_eth_type_reg}};
integer i;
always @* begin
select_next = select_reg;
select_ctl = select_reg;
drop_next = drop_reg;
drop_ctl = drop_reg;
frame_next = frame_reg;
frame_ctl = frame_reg;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg & ~m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
if (s_eth_payload_axis_tvalid && s_eth_payload_axis_tready) begin
// end of frame detection
if (s_eth_payload_axis_tlast) begin
frame_next = 1'b0;
drop_next = 1'b0;
end
end
if (!frame_reg && s_eth_hdr_valid && s_eth_hdr_ready) begin
// start of frame, grab select value
select_ctl = select;
drop_ctl = drop;
frame_ctl = 1'b1;
select_next = select_ctl;
drop_next = drop_ctl;
frame_next = frame_ctl;
s_eth_hdr_ready_next = 1'b0;
m_eth_hdr_valid_next = (!drop_ctl) << select_ctl;
m_eth_dest_mac_next = s_eth_dest_mac;
m_eth_src_mac_next = s_eth_src_mac;
m_eth_type_next = s_eth_type;
end
s_eth_hdr_ready_next = !frame_next && !m_eth_hdr_valid_next;
s_eth_payload_axis_tready_next = (m_eth_payload_axis_tready_int_early || drop_ctl) && frame_ctl;
m_eth_payload_axis_tdata_int = s_eth_payload_axis_tdata;
m_eth_payload_axis_tkeep_int = s_eth_payload_axis_tkeep;
m_eth_payload_axis_tvalid_int = (s_eth_payload_axis_tvalid && s_eth_payload_axis_tready && !drop_ctl) << select_ctl;
m_eth_payload_axis_tlast_int = s_eth_payload_axis_tlast;
m_eth_payload_axis_tid_int = s_eth_payload_axis_tid;
m_eth_payload_axis_tdest_int = s_eth_payload_axis_tdest;
m_eth_payload_axis_tuser_int = s_eth_payload_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
drop_reg <= 1'b0;
frame_reg <= 1'b0;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 0;
end else begin
select_reg <= select_next;
drop_reg <= drop_next;
frame_reg <= frame_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_eth_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] temp_m_eth_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = {M_COUNT{m_eth_payload_axis_tdata_reg}};
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_eth_payload_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = {M_COUNT{m_eth_payload_axis_tlast_reg}};
assign m_eth_payload_axis_tid = ID_ENABLE ? {M_COUNT{m_eth_payload_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_eth_payload_axis_tdest = DEST_ENABLE ? {M_COUNT{m_eth_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_eth_payload_axis_tuser = USER_ENABLE ? {M_COUNT{m_eth_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if ((m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || !m_eth_payload_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
|
Require Export Coq.Program.Tactics.
Require Export Coq.Setoids.Setoid.
Require Export Coq.Classes.Morphisms.
Require Export Coq.Arith.Arith_base.
Require Export Coq.Relations.Relations.
Require Export Coq.Lists.List.
Import EqNotations.
Import ListNotations.
(***
*** Ordered Types = Types with a PreOrder
***)
Record OType : Type :=
{
ot_Type :> Type;
ot_R : relation ot_Type;
ot_PreOrder : PreOrder ot_R
}.
Arguments ot_R {_} _ _.
Instance OType_Reflexive (A:OType) : Reflexive (@ot_R A).
Proof.
destruct A; auto with typeclass_instances.
Qed.
Instance OType_Transitive (A:OType) : Transitive (@ot_R A).
Proof.
destruct A; auto with typeclass_instances.
Qed.
(* The equivalence relation for an OrderedType *)
Definition ot_equiv (A:OType) : relation (ot_Type A) :=
fun x y => ot_R x y /\ ot_R y x.
Arguments ot_equiv {_} _ _.
Instance ot_equiv_Equivalence A : Equivalence (@ot_equiv A).
Proof.
constructor; intro; intros.
{ split; reflexivity. }
{ destruct H; split; assumption. }
{ destruct H; destruct H0; split; transitivity y; assumption. }
Qed.
(***
*** Commonly-Used Ordered Types
***)
(* The ordered type of propositions *)
Program Definition OTProp : OType :=
{|
ot_Type := Prop;
ot_R := Basics.impl;
|}.
Next Obligation.
constructor; auto with typeclass_instances.
Qed.
(* The discrete ordered type, where things are only related to themselves *)
Program Definition OTdiscrete (A:Type) : OType :=
{|
ot_Type := A;
ot_R := eq;
|}.
(* The only ordered type over unit is the discrete one *)
Definition OTunit : OType := OTdiscrete unit.
(* The ordered type of natural numbers using <= *)
Program Definition OTnat : OType :=
{|
ot_Type := nat;
ot_R := le;
|}.
(* Flip the ordering of an OType *)
Program Definition OTflip (A:OType) : OType :=
{|
ot_Type := ot_Type A;
ot_R := fun x y => ot_R y x
|}.
Next Obligation.
constructor.
{ intro x. reflexivity. }
{ intros x y z; transitivity y; assumption. }
Qed.
(* The pointwise relation on pairs *)
Definition pairR {A B} (RA:relation A) (RB:relation B) : relation (A*B) :=
fun p1 p2 => RA (fst p1) (fst p2) /\ RB (snd p1) (snd p2).
Instance PreOrder_pairR A B RA RB
`(PreOrder A RA) `(PreOrder B RB) : PreOrder (pairR RA RB).
Proof.
constructor.
{ intro p; split; reflexivity. }
{ intros p1 p2 p3 R12 R23; destruct R12; destruct R23; split.
- transitivity (fst p2); assumption.
- transitivity (snd p2); assumption. }
Qed.
(* The non-dependent product ordered type, where pairs are related pointwise *)
Definition OTpair (A B:OType) : OType :=
{|
ot_Type := ot_Type A * ot_Type B;
ot_R := pairR (@ot_R A) (@ot_R B);
ot_PreOrder := PreOrder_pairR _ _ _ _ (ot_PreOrder A) (ot_PreOrder B)
|}.
(* The sort-of pointwise relation on sum types *)
Inductive sumR {A B} (RA:relation A) (RB:relation B) : A+B -> A+B -> Prop :=
| sumR_inl a1 a2 : RA a1 a2 -> sumR RA RB (inl a1) (inl a2)
| sumR_inr b1 b2 : RB b1 b2 -> sumR RA RB (inr b1) (inr b2).
Instance PreOrder_sumR A B RA RB
`(PreOrder A RA) `(PreOrder B RB) : PreOrder (sumR RA RB).
Proof.
constructor.
{ intro s; destruct s; constructor; reflexivity. }
{ intros s1 s2 s3 R12 R23. destruct R12; inversion R23.
- constructor; transitivity a2; assumption.
- constructor; transitivity b2; assumption. }
Qed.
(*
Definition sumR {A B} (RA:relation A) (RB:relation B) : relation (A+B) :=
fun sum1 sum2 =>
match sum1, sum2 with
| inl x, inl y => RA x y
| inl x, inr y => False
| inr x, inl y => False
| inr x, inr y => RB x y
end.
Instance PreOrder_sumR A B RA RB
`(PreOrder A RA) `(PreOrder B RB) : PreOrder (sumR RA RB).
Proof.
constructor.
{ intro s; destruct s; simpl; reflexivity. }
{ intros s1 s2 s3 R12 R23.
destruct s1; destruct s2; destruct s3;
try (elimtype False; assumption); simpl.
- transitivity a0; assumption.
- transitivity b0; assumption. }
Qed.
*)
(* The non-dependent sum ordered type, where objects are only related if they
are both "left"s or both "right"s *)
Definition OTsum (A B : OType) : OType :=
{|
ot_Type := ot_Type A + ot_Type B;
ot_R := sumR (@ot_R A) (@ot_R B);
ot_PreOrder := PreOrder_sumR _ _ _ _ (ot_PreOrder A) (ot_PreOrder B)
|}.
(* NOTE: the following definition requires everything above to be polymorphic *)
(* NOTE: The definition we choose for OTType is actually deep: instead of
requiring ot_Type A = ot_Type B, we could just require a coercion function from
ot_Type A to ot_Type B, which would yield something more like HoTT... though
maybe it wouldn't work unless we assumed the HoTT axiom? As it is, we might need
UIP to hold if we want to use the definition given here... *)
(*
Program Definition OTType : OType :=
{|
ot_Type := OType;
ot_R := (fun A B =>
exists (e:ot_Type A = ot_Type B),
forall (x y:A),
ot_R A x y ->
ot_R B (rew [fun A => A] e in x)
(rew [fun A => A] e in y));
|}.
*)
(***
*** The Ordered Type for Functions
***)
(* The type of continuous, i.e. Proper, functions between ordered types *)
Record Pfun (A B:OType) :=
{
pfun_app : ot_Type A -> ot_Type B;
pfun_Proper : Proper (ot_R ==> ot_R) pfun_app
}.
Arguments pfun_app [_ _] _ _.
Arguments pfun_Proper [_ _] _ _ _ _.
(* The identity pfun *)
Definition idPfun A : Pfun A A :=
{| pfun_app := fun x => x; pfun_Proper := fun x1 x2 Rx => Rx |}.
(* The identity pfun *)
Program Definition composePfun A B C (f:Pfun A B) (g:Pfun B C) :=
{| pfun_app := fun x => pfun_app g (pfun_app f x);
pfun_Proper := _ |}.
Next Obligation.
intros x1 x2 Rx. apply pfun_Proper. apply pfun_Proper. assumption.
Qed.
(* The non-dependent function ordered type *)
Definition OTarrow_R (A B : OType) : relation (Pfun A B) :=
fun f g =>
forall a1 a2, ot_R a1 a2 -> ot_R (pfun_app f a1) (pfun_app g a2).
Program Definition OTarrow (A B:OType) : OType :=
{|
ot_Type := Pfun A B;
ot_R := OTarrow_R A B;
|}.
Next Obligation.
constructor.
{ intros f; apply (pfun_Proper f). }
{ intros f g h Rfg Rgh a1 a2 Ra. transitivity (pfun_app g a1).
- apply (Rfg a1 a1). reflexivity.
- apply Rgh; assumption. }
Qed.
(* Curry a Pfun *)
Program Definition pfun_curry {A B C} (pfun : Pfun (OTpair A B) C)
: Pfun A (OTarrow B C) :=
{| pfun_app :=
fun a =>
{| pfun_app := fun b => pfun_app pfun (a,b);
pfun_Proper := _ |};
pfun_Proper := _ |}.
Next Obligation.
Proof.
intros b1 b2 Rb. apply pfun_Proper.
split; [ reflexivity | assumption ].
Qed.
Next Obligation.
Proof.
intros a1 a2 Ra b1 b2 Rb; simpl.
apply pfun_Proper; split; assumption.
Qed.
(* Uncrry a Pfun *)
Program Definition pfun_uncurry {A B C} (pfun : Pfun A (OTarrow B C))
: Pfun (OTpair A B) C :=
{| pfun_app :=
fun ab => pfun_app (pfun_app pfun (fst ab)) (snd ab);
pfun_Proper := _ |}.
Next Obligation.
Proof.
intros ab1 ab2 Rab. destruct Rab as [ Ra Rb ].
exact (pfun_Proper pfun (fst ab1) (fst ab2) Ra (snd ab1) (snd ab2) Rb).
Qed.
(* Currying and uncurrying of pfuns form an adjunction *)
(* FIXME: figure out the simplest way of stating this adjunction *)
(* OTarrow is right adjoint to OTpair, meaning that (OTarrow (OTpair A B) C) is
isomorphic to (OTarrow A (OTarrow B C)). The following is the first part of this
isomorphism, mapping left-to-right. *)
(* FIXME: could also do a forall type, but need the second type argument, B, to
itself be proper, i.e., to be an element of OTarrow A OType. Would also need a
dependent version of OTContext, below. *)
(* FIXME: maybe these the following two instances are no longer needed...? *)
(* pfun_app is always Proper *)
Instance Proper_pfun_app A B :
Proper (@ot_R (OTarrow A B) ==> @ot_R A ==> @ot_R B) (@pfun_app A B).
Proof.
intros f1 f2 Rf a1 a2 Ra. apply Rf; assumption.
Qed.
(* pfun_app is always Proper w.r.t. ot_equiv *)
Instance Proper_pfun_app_equiv A B :
Proper (@ot_equiv (OTarrow A B) ==> @ot_equiv A ==> @ot_equiv B) (@pfun_app A B).
Proof.
intros f1 f2 Rf a1 a2 Ra; destruct Rf; destruct Ra.
split; apply Proper_pfun_app; assumption.
Qed.
(***
*** Notations
***)
(*
Notation "x <o= y" :=
(ot_R x y) (no associativity, at level 70).
Notation "x =o= y" :=
(ot_equiv x y) (no associativity, at level 70).
*)
Notation "A '*o*' B" :=
(OTpair A B) (left associativity, at level 40).
Notation "A '+o+' B" :=
(OTsum A B) (left associativity, at level 50).
Notation "'~o~' A" :=
(OTflip A) (right associativity, at level 35).
Notation "A '-o>' B" :=
(OTarrow A B) (right associativity, at level 99).
(***
*** Ordered Expressions
***)
(* An ordered type context is a list of ordered types *)
Definition OTCtx := list OType.
(* Heterogeneous lists of things indexed by contexts *)
Inductive hlist F : OTCtx -> Type :=
| hnil : hlist F []
| hcons A (x:F A) ctx (xs:hlist F ctx) : hlist F (A::ctx)
.
(* The type of names in expressions *)
Axiom Name : OType -> Type.
Definition names ctx := hlist Name ctx.
(* The type of name-bindings, and its constructor *)
Axiom nabla : forall ctx:OTCtx, (names ctx -> Type) -> Type.
Axiom nu : forall ctx A, (forall names, A names) -> nabla ctx A.
FIXME HERE NOW: old stuff below!
(***
*** Ordered Type Contexts
***)
(* An ordered type context is a list of ordered types *)
Definition OTCtx := list OType.
(* The ordered type of context elements *)
Fixpoint OTCtxElem (ctx:OTCtx) : OType :=
match ctx with
| [] => OTunit
| A::ctx' => OTCtxElem ctx' *o* A
end.
(* A version of In that is in Type instead of in Prop *)
Inductive OTInCtx B : OTCtx -> Type :=
| OTInCtx_base ctx : OTInCtx B (B::ctx)
| OTInCtx_step ctx A : OTInCtx B ctx -> OTInCtx B (A::ctx)
.
(* Projecting an element out of an OTCtxElem *)
Fixpoint lookupOTInCtx B ctx (pf:OTInCtx B ctx) : OTCtxElem ctx -> B :=
match pf in OTInCtx _ ctx return OTCtxElem ctx -> B with
| OTInCtx_base _ _ => fun celem => snd celem
| OTInCtx_step _ ctx' _ pf' => fun celem => lookupOTInCtx B ctx' pf' (fst celem)
end.
Instance Proper_lookupOTInCtx B ctx pf :
Proper (ot_R ==> ot_R) (lookupOTInCtx B ctx pf).
Proof.
induction pf; intros c1 c2 Rc; destruct Rc.
assumption.
apply IHpf; assumption.
Qed.
(* Weaken a context by inserting an ordered type after n steps *)
Fixpoint weakenOTCtx (W:OType) n (ctx:OTCtx) : OTCtx :=
match n with
| 0 => W::ctx
| S n' =>
match ctx with
| [] => [W]
| B::ctx' => B::(weakenOTCtx W n' ctx')
end
end.
(* Weakening an OTCtxElem *)
Fixpoint weakenOTCtxElem W n : forall ctx, OTCtxElem (weakenOTCtx W n ctx) -> OTCtxElem ctx :=
match n return forall ctx, OTCtxElem (weakenOTCtx W n ctx) -> OTCtxElem ctx with
| 0 => fun _ celem => fst celem
| S n' =>
fun ctx =>
match ctx return OTCtxElem (weakenOTCtx W (S n') ctx) -> OTCtxElem ctx with
| [] => fun _ => tt
| A::ctx' =>
fun celem => (weakenOTCtxElem W n' ctx' (fst celem), snd celem)
end
end.
Instance Proper_weakenOTCtxElem W n ctx :
Proper (ot_R ==> ot_R) (weakenOTCtxElem W n ctx).
Proof.
revert ctx; induction n; intro ctx.
intros c1 c2 Rc; destruct Rc; assumption.
destruct ctx; intros c1 c2 Rc.
reflexivity.
destruct Rc; split; [ apply IHn | ]; assumption.
Qed.
(* Weaken an OTInCtx proof *)
Fixpoint weakenOTInCtx W n B : forall ctx, OTInCtx B ctx -> OTInCtx B (weakenOTCtx W n ctx) :=
match n return forall ctx, OTInCtx B ctx -> OTInCtx B (weakenOTCtx W n ctx) with
| 0 => fun _ pf => OTInCtx_step _ _ _ pf
| S n' =>
fun ctx pf =>
match pf in OTInCtx _ ctx return OTInCtx B (weakenOTCtx W (S n') ctx) with
| OTInCtx_base _ _ => OTInCtx_base _ _
| OTInCtx_step _ ctx' _ pf' =>
OTInCtx_step _ _ _ (weakenOTInCtx W n' B ctx' pf')
end
end.
(***
*** Ordered Expressions
***)
(* Ordered expressions *)
Inductive OExpr : OTCtx -> OType -> Type :=
| OVar ctx A : OTInCtx A ctx -> OExpr ctx A
| OEmbed ctx A : ot_Type A -> OExpr ctx A
| OApp ctx A B : OExpr ctx (A -o> B) -> OExpr ctx A -> OExpr ctx B
| OLam ctx A B : OExpr (A::ctx) B -> OExpr ctx (A -o> B)
.
(* Weakening of ordered expressions *)
Fixpoint weakenOExpr W n ctx A (e:OExpr ctx A) :
OExpr (weakenOTCtx W n ctx) A :=
match e with
| OVar ctx A pf => OVar _ A (weakenOTInCtx W n A ctx pf)
| OEmbed ctx A x => OEmbed (weakenOTCtx W n ctx) A x
| OApp ctx A B f arg =>
OApp (weakenOTCtx W n ctx) A B (weakenOExpr W n ctx (A -o> B) f)
(weakenOExpr W n ctx A arg)
| OLam ctx A B f =>
OLam (weakenOTCtx W n ctx) A B
(weakenOExpr W (S n) (A::ctx) B f)
end.
(* A substitution for all the elements of a context *)
Fixpoint OSubst (ctx_from ctx_to:OTCtx) : Type :=
match ctx_from with
| [] => unit
| A::ctx_from' => OSubst ctx_from' ctx_to * OExpr ctx_to A
end.
(* Weaken a substitution *)
Fixpoint weakenOSubst W n ctx_from ctx_to :
OSubst ctx_from ctx_to -> OSubst ctx_from (weakenOTCtx W n ctx_to) :=
match ctx_from return
OSubst ctx_from ctx_to -> OSubst ctx_from (weakenOTCtx W n ctx_to)
with
| [] => fun _ => tt
| A::ctx_from' =>
fun s => (weakenOSubst W n ctx_from' ctx_to (fst s),
weakenOExpr W n _ A (snd s))
end.
(* Substitution into an ordered expression variable *)
Fixpoint substOVar ctx A (v:OTInCtx A ctx) ctx_to : OSubst ctx ctx_to ->
OExpr ctx_to A :=
match v in OTInCtx _ ctx return OSubst ctx ctx_to -> OExpr ctx_to A with
| OTInCtx_base _ _ =>
fun s => snd s
| OTInCtx_step _ ctx' _ v' =>
fun s => substOVar ctx' A v' ctx_to (fst s)
end.
(* Substitute into an expression *)
Fixpoint substOExpr ctx A (e:OExpr ctx A) :
forall ctx_to (s:OSubst ctx ctx_to), OExpr ctx_to A :=
match e with
| OVar ctx A pf => fun ctx_to s => substOVar ctx A pf ctx_to s
| OEmbed ctx A a => fun ctx_to _ => OEmbed ctx_to A a
| OApp ctx A B e1 e2 =>
fun ctx_to s =>
OApp ctx_to A B (substOExpr ctx (A -o> B) e1 ctx_to s)
(substOExpr ctx A e2 ctx_to s)
| OLam ctx A B e =>
fun ctx_to s =>
OLam ctx_to A B (substOExpr (A::ctx) B e (A::ctx_to)
(weakenOSubst A 0 ctx ctx_to s,
OVar _ _ (OTInCtx_base A ctx_to)))
end.
(* The identity substitution *)
Fixpoint idSubst ctx : OSubst ctx ctx :=
match ctx with
| [] => tt
| A::ctx' =>
(weakenOSubst A 0 ctx' ctx' (idSubst ctx'),
OVar _ _ (OTInCtx_base A ctx'))
end.
(***
*** Semantics of Ordered Expressions
***)
(* The type of the semantics of an OExpr *)
Definition OTSemantics (ctx:OTCtx) (B:OType) : OType := OTCtxElem ctx -o> B.
(* Embedding into OTSemantics (return / unit for the applicative functor) *)
Definition embedSemantics ctx B (x:ot_Type B) : OTSemantics ctx B :=
{| pfun_app := fun _ => x;
pfun_Proper := ltac:(intro; intros; reflexivity) |}.
(* Proper instance for embedding *)
Instance Proper_embedSemantics ctx A :
Proper (ot_R ==> ot_R) (embedSemantics ctx A).
Proof.
intros x y Rxy a1 a2 Ra. assumption.
Qed.
(* Weakening for semantics *)
Program Definition weakenSemantics W n ctx B
(sem:OTSemantics ctx B) : OTSemantics (weakenOTCtx W n ctx) B :=
{| pfun_app := fun celem => pfun_app sem (weakenOTCtxElem W n ctx celem);
pfun_Proper := _ |}.
Next Obligation.
intros c1 c2 Rc. apply pfun_Proper. apply Proper_weakenOTCtxElem. assumption.
Qed.
(* Proper instance for weakening *)
Instance Proper_weakenSemantics W n ctx B :
Proper (ot_R ==> ot_R) (weakenSemantics W n ctx B).
Proof.
intros c1 c2 Rc a1 a2 Ra. simpl. apply Proper_pfun_app.
- assumption.
- apply Proper_weakenOTCtxElem; assumption.
Qed.
(* The semantics of a variable *)
Definition ovarSemantics ctx B (pf:OTInCtx B ctx) : OTSemantics ctx B :=
{| pfun_app := lookupOTInCtx B ctx pf;
pfun_Proper := _ |}.
(* Application in OTSemantics (this is <*> for the Applicative functor) *)
Program Definition applySemantics ctx A B (f : OTSemantics ctx (A -o> B))
(arg : OTSemantics ctx A) : OTSemantics ctx B :=
{| pfun_app := fun celem => pfun_app (pfun_app f celem) (pfun_app arg celem);
pfun_Proper := _ |}.
Next Obligation.
intros c1 c2 Rc. apply Proper_pfun_app; apply pfun_Proper; assumption.
Qed.
Lemma applySemantics_Proper ctx A B :
Proper (ot_R ==> ot_R ==> ot_R) (applySemantics ctx A B).
intros f1 f2 Rf a1 a2 Ra c1 c2 Rc.
apply Rf; [ assumption | ]. apply Ra; assumption.
Qed.
(* Lambda in OTSemantics: this is just currying for Pfuns *)
Definition lambdaSemantics ctx A B (f : OTSemantics (A::ctx) B) :
OTSemantics ctx (A -o> B) := pfun_curry f.
(* The semantics for any ordered expression *)
Fixpoint exprSemantics ctx A (e:OExpr ctx A) : OTSemantics ctx A :=
match e in OExpr ctx A return OTSemantics ctx A with
| OVar ctx A pf => ovarSemantics ctx A pf
| OEmbed ctx A a => embedSemantics ctx A a
| OApp ctx A B e1 e2 =>
applySemantics ctx A B (exprSemantics ctx (A -o> B) e1)
(exprSemantics ctx A e2)
| OLam ctx A B e => lambdaSemantics ctx A B (exprSemantics (A::ctx) B e)
end.
(* The ordered type over expressions *)
(* FIXME: need to make OType polymorphic to write this...
Program Definition OExprOType ctx A : OType :=
{|
ot_Type := OExpr ctx A;
ot_R := fun e1 e2 => ot_R (exprSemantics ctx A e1) (exprSemantics ctx A e2);
|}.
*)
Definition oexpr_R {ctx A} : relation (OExpr ctx A) :=
fun e1 e2 => ot_R (exprSemantics ctx A e1) (exprSemantics ctx A e2).
Definition oexpr_equiv {ctx A} : relation (OExpr ctx A) :=
fun e1 e2 => oexpr_R e1 e2 /\ oexpr_R e2 e1.
Instance oexpr_R_PreOrder ctx A : PreOrder (@oexpr_R ctx A).
Proof.
unfold oexpr_R; constructor; intro; intros.
{ reflexivity. }
{ transitivity (exprSemantics ctx A y); assumption. }
Qed.
Instance oexpr_equiv_Equivalence ctx A : Equivalence (@oexpr_equiv ctx A).
Proof.
constructor; intro; intros.
{ split; reflexivity. }
{ destruct H; split; assumption. }
{ destruct H; destruct H0; split; transitivity y; assumption. }
Qed.
Notation "x <o= y" :=
(oexpr_R x y) (no associativity, at level 70).
Notation "x =o= y" :=
(oexpr_equiv x y) (no associativity, at level 70).
(***
*** Rewriting Automation for Expressions
***)
Instance oexpr_equiv_expr_R_subrelation ctx A :
subrelation (@oexpr_equiv ctx A) (@oexpr_R ctx A).
Proof.
intros x y Rxy; destruct Rxy; assumption.
Qed.
Instance OEmbed_Proper_R ctx A : Proper (ot_R ==> oexpr_R) (OEmbed ctx A).
Proof.
intros a1 a2 Ra c1 c2 Rc. apply Ra.
Qed.
Instance OEmbed_Proper_equiv ctx A :
Proper (ot_equiv ==> oexpr_equiv) (OEmbed ctx A).
Proof.
intros a1 a2 Ra; split; intros c1 c2 Rc; apply Ra.
Qed.
Instance OEmbed_Proper_equiv_R ctx A :
Proper (ot_equiv ==> oexpr_R) (OEmbed ctx A).
Proof.
intros a1 a2 Ra; intros c1 c2 Rc; apply Ra.
Qed.
Instance OApp_Proper_R ctx A B :
Proper (oexpr_R ==> oexpr_R ==> oexpr_R) (OApp ctx A B).
Proof.
intros f1 f2 Rf e1 e2 Re c1 c2 Rc. simpl.
apply Rf; [ assumption | ].
apply Re; assumption.
Qed.
Instance OApp_Proper_equiv ctx A B :
Proper (oexpr_equiv ==> oexpr_equiv ==> oexpr_equiv) (OApp ctx A B).
Proof.
intros f1 f2 Rf e1 e2 Re; simpl.
destruct Rf; destruct Re; split.
- rewrite H; rewrite H1; reflexivity.
- rewrite H0; rewrite H2; reflexivity.
Qed.
Instance OLam_Proper_R ctx A B : Proper (oexpr_R ==> oexpr_R) (OLam ctx A B).
Proof.
intros e1 e2 Re c1 c2 Rc a1 a2 Ra. simpl.
apply Re. split; assumption.
Qed.
Instance OLam_Proper_equiv ctx A B :
Proper (oexpr_equiv ==> oexpr_equiv) (OLam ctx A B).
Proof.
intros e1 e2 Re. destruct Re.
split; [ rewrite H | rewrite H0]; reflexivity.
Qed.
(***
*** Beta Rules
***)
Fixpoint substSemantics_fun ctx_from ctx_to :
OSubst ctx_from ctx_to -> OTCtxElem ctx_to -> OTCtxElem ctx_from :=
match ctx_from return
OSubst ctx_from ctx_to -> OTCtxElem ctx_to -> OTCtxElem ctx_from
with
| [] => fun _ _ => tt
| A::ctx_from' =>
fun s celem =>
(substSemantics_fun ctx_from' ctx_to (fst s) celem,
pfun_app (exprSemantics _ _ (snd s)) celem)
end.
Lemma substSemantics_Proper ctx_from ctx_to s :
Proper (ot_R ==> ot_R) (substSemantics_fun ctx_from ctx_to s).
induction ctx_from; intros c1 c2 Rc.
- constructor.
- split.
+ apply IHctx_from; assumption.
+ apply pfun_Proper; assumption.
Qed.
Definition substSemantics ctx_from ctx_to s :
OTCtxElem ctx_to -o> OTCtxElem ctx_from :=
{| pfun_app := substSemantics_fun ctx_from ctx_to s;
pfun_Proper := substSemantics_Proper ctx_from ctx_to s |}.
|
`timescale 1 ns / 1 ps
`include "vga_axi_mem_buffer_v1_0_tb_include.vh"
// Burst Size Defines
`define BURST_SIZE_4_BYTES 3'b010
// Lock Type Defines
`define LOCK_TYPE_NORMAL 1'b0
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA S_AXI AXI4 Range Constants
`define S_AXI_MAX_BURST_LENGTH 8'b1111_1111
`define S_AXI_MAX_DATA_SIZE (`S_AXI_DATA_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))/8
`define S_AXI_DATA_BUS_WIDTH 32
`define S_AXI_ADDRESS_BUS_WIDTH 32
`define S_AXI_RUSER_BUS_WIDTH 1
`define S_AXI_WUSER_BUS_WIDTH 1
module vga_axi_mem_buffer_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S_AXI AXI4 Local Reg
reg [(`S_AXI_DATA_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S_AXI_rd_data;
reg [(`S_AXI_DATA_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1)/16)-1:0] S_AXI_test_data [2:0];
reg [(`RESP_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))-1:0] S_AXI_vresponse;
reg [`S_AXI_ADDRESS_BUS_WIDTH-1:0] S_AXI_mtestAddress;
reg [(`S_AXI_RUSER_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))-1:0] S_AXI_v_ruser;
reg [(`S_AXI_WUSER_BUS_WIDTH*(`S_AXI_MAX_BURST_LENGTH+1))-1:0] S_AXI_v_wuser;
reg [`RESP_BUS_WIDTH-1:0] S_AXI_response;
integer S_AXI_mtestID; // Master side testID
integer S_AXI_mtestBurstLength;
integer S_AXI_mtestvector; // Master side testvector
integer S_AXI_mtestdatasize;
integer S_AXI_mtestCacheType = 0;
integer S_AXI_mtestProtectionType = 0;
integer S_AXI_mtestRegion = 0;
integer S_AXI_mtestQOS = 0;
integer S_AXI_mtestAWUSER = 0;
integer S_AXI_mtestARUSER = 0;
integer S_AXI_mtestBUSER = 0;
integer result_slave_full;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
`define S_AXI_BURST_LENGTH 16
task automatic COMPARE_DATA;
input [(`S_AXI_DATA_BUS_WIDTH*`S_AXI_BURST_LENGTH)-1:0]expected;
input [(`S_AXI_DATA_BUS_WIDTH*`S_AXI_BURST_LENGTH)-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_full = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
result_slave_full = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S_AXI_TEST;
begin
//---------------------------------------------------------------------
// EXAMPLE TEST 1:
// Simple sequential write and read burst transfers example
// DESCRIPTION:
// The following master code does a simple write and read burst for
// each burst transfer type.
//---------------------------------------------------------------------
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S_AXI:");
$display("Simple sequential write and read burst transfers example");
$display("---------------------------------------------------------");
S_AXI_mtestID = 1;
S_AXI_mtestvector = 0;
S_AXI_mtestBurstLength = 15;
S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS;
S_AXI_mtestCacheType = 0;
S_AXI_mtestProtectionType = 0;
S_AXI_mtestdatasize = `S_AXI_MAX_DATA_SIZE;
S_AXI_mtestRegion = 0;
S_AXI_mtestQOS = 0;
S_AXI_mtestAWUSER = 0;
S_AXI_mtestARUSER = 0;
result_slave_full = 1;
dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.WRITE_BURST_CONCURRENT(S_AXI_mtestID,
S_AXI_mtestAddress,
S_AXI_mtestBurstLength,
`BURST_SIZE_4_BYTES,
`BURST_TYPE_INCR,
`LOCK_TYPE_NORMAL,
S_AXI_mtestCacheType,
S_AXI_mtestProtectionType,
S_AXI_test_data[S_AXI_mtestvector],
S_AXI_mtestdatasize,
S_AXI_mtestRegion,
S_AXI_mtestQOS,
S_AXI_mtestAWUSER,
S_AXI_v_wuser,
S_AXI_response,
S_AXI_mtestBUSER);
$display("EXAMPLE TEST 1 : DATA = 0x%h, response = 0x%h",S_AXI_test_data[S_AXI_mtestvector],S_AXI_response);
CHECK_RESPONSE_OKAY(S_AXI_response);
S_AXI_mtestID = S_AXI_mtestID+1;
dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.READ_BURST(S_AXI_mtestID,
S_AXI_mtestAddress,
S_AXI_mtestBurstLength,
`BURST_SIZE_4_BYTES,
`BURST_TYPE_WRAP,
`LOCK_TYPE_NORMAL,
S_AXI_mtestCacheType,
S_AXI_mtestProtectionType,
S_AXI_mtestRegion,
S_AXI_mtestQOS,
S_AXI_mtestARUSER,
S_AXI_rd_data,
S_AXI_vresponse,
S_AXI_v_ruser);
$display("EXAMPLE TEST 1 : DATA = 0x%h, vresponse = 0x%h",S_AXI_rd_data,S_AXI_vresponse);
CHECK_RESPONSE_OKAY(S_AXI_vresponse);
// Check that the data received by the master is the same as the test
// vector supplied by the slave.
COMPARE_DATA(S_AXI_test_data[S_AXI_mtestvector],S_AXI_rd_data);
$display("EXAMPLE TEST 1 : Sequential write and read FIXED burst transfers complete from the master side.");
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_full ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S_AXI_test_data[1] = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
S_AXI_test_data[0] = 512'h00abcdef111111112222222233333333444444445555555566666666777777778888888899999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF;
S_AXI_test_data[2] = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
S_AXI_v_ruser = 0;
S_AXI_v_wuser = 0;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S_AXI_TEST();
end
endmodule
|
module simple_test(
input rst,
input clk,
input [30:0]a,
input [30:0]b,
output reg [31:0]adder_result,
output [15:0]counter,
output [96:0]_97bit_round,
output counter_rdy,
output clk_echo
);
wire [74:0]hidden_mem[0:99]/*verilator public*/;
wire [74:0]hidden_signal/*verilator public*/;
wire [12:0]short_hidden_signal/*verilator public*/;
assign clk_echo=clk;
reg [30:0]a_s;
reg [30:0]b_s;
always @(posedge clk, posedge rst)
if(rst)
{a_s,b_s} <= 0;
else
{a_s,b_s} <= {a,b};
always @(posedge clk, posedge rst)
if(rst)
adder_result <= 0;
else
adder_result <= {a_s[30],a_s} + {b_s[30],b_s};
reg [15:0]cnt;
always @(posedge clk, posedge rst)
if(rst)
cnt <= 0;
else
cnt <= cnt + 1;
assign counter_rdy = (cnt==0);
assign counter=cnt;
reg [96:0]shift;
always @(posedge clk, posedge rst)
if(rst)
shift <= 1;
else
shift <= {shift[95:0],shift[96]};
assign _97bit_round = shift;
endmodule |
module uart(
clk32,
reset_,
rx,
tx,
txdata,
rxdata,
rx_enable,
tx_enable,
tx_ready);
input clk32; // 32 Mhz clock input
input reset_; // Reset
input rx; // Serial RX from FTDI USB chip
output tx; // Serial TX from FTDI USB chip
input [7:0] txdata; // Byte to be transmitted
output [7:0] rxdata; // Byte received
output rx_enable; // When high, rxdata is ready
input tx_enable; // Set high to tell transmitter to send txdata, no affect when !tx_ready
output tx_ready; // When high, device is ready to transmit
wire baud;
wire sample;
reg [8:0] baud_ctr;
reg [4:0] sample_ctr;
// Serial transmission baud rate
parameter BAUD_FREQ = 115_200;
// Incoming clock frequency
parameter CLK32_FREQ = 32_000_000;
// Serial input is sampled at 16x the baud rate
parameter SAMPLE_FREQ = 16;
// Accumulator/counter max values to create sample/baud pulse
parameter BAUD_MAX = CLK32_FREQ / BAUD_FREQ;
parameter SAMPLE_MAX = CLK32_FREQ / (BAUD_FREQ * SAMPLE_FREQ);
assign baud = baud_ctr == BAUD_MAX; // Pulse at baud frequency
assign sample = sample_ctr == SAMPLE_MAX; // Pulse at sample frequency
// Serial transmitter
tx transmit (
.clk(clk32),
.reset_(reset_),
.baud(baud),
.txdata(txdata),
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.tx(tx));
// Serial receiver
rx receive(
.clk(clk32),
.reset_(reset_),
.sample(sample),
.rx(rx),
.rx_enable(rx_enable),
.rxdata(rxdata));
// Baud frequency counter
always@ (posedge clk32 or negedge reset_)
if (!reset_)
baud_ctr <= 9'd0;
else if (baud_ctr == BAUD_MAX)
baud_ctr <= 9'd0;
else
baud_ctr <= baud_ctr + 9'd1;
// Input sample frequency counter
always@ (posedge clk32 or negedge reset_)
if (!reset_)
sample_ctr <= 5'd0;
else if (sample_ctr == SAMPLE_MAX)
sample_ctr <= 5'd0;
else
sample_ctr <= sample_ctr + 5'd1;
endmodule
|
`timescale 1ns / 1ps
/*
* File : uart_tx.v
* Creator(s) : Grant Ayers ([email protected])
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 25-Mar-2010 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Transmits bytes of data from the serial port. Capable of back-to-back
* transmission of data for full bandwidth utilization.
* 'TxD_start' must only pulse with a 'uart_tick' pulse. 8N1.
*/
module uart_tx (
input clock,
input reset,
input uart_tick,
input [7:0] TxD_data,
input TxD_start, // Must happen with a uart_tick
output ready,
output reg TxD
);
localparam [3:0] IDLE=0, START=1, BIT_0=2, BIT_1=3, BIT_2=4, BIT_3=5,
BIT_4=6, BIT_5=7, BIT_6=8, BIT_7=9, STOP=10;
reg [3:0] tx_state = IDLE;
reg [7:0] TxD_data_r = 8'h00; // Registered input data so it doesn't need to be held
assign ready = (tx_state == IDLE) || (tx_state == STOP);
always @(posedge clock) begin
TxD_data_r <= (ready & TxD_start) ? TxD_data : TxD_data_r;
end
always @(posedge clock) begin
if (reset) tx_state <= IDLE;
else begin
case (tx_state)
IDLE: if (TxD_start) tx_state <= START;
START: if (uart_tick) tx_state <= BIT_0;
BIT_0: if (uart_tick) tx_state <= BIT_1;
BIT_1: if (uart_tick) tx_state <= BIT_2;
BIT_2: if (uart_tick) tx_state <= BIT_3;
BIT_3: if (uart_tick) tx_state <= BIT_4;
BIT_4: if (uart_tick) tx_state <= BIT_5;
BIT_5: if (uart_tick) tx_state <= BIT_6;
BIT_6: if (uart_tick) tx_state <= BIT_7;
BIT_7: if (uart_tick) tx_state <= STOP;
STOP: if (uart_tick) tx_state <= (TxD_start) ? START : IDLE;
default: tx_state <= 4'bxxxx;
endcase
end
end
always @(tx_state, TxD_data_r) begin
case (tx_state)
IDLE: TxD <= 1'b1;
START: TxD <= 1'b0;
BIT_0: TxD <= TxD_data_r[0];
BIT_1: TxD <= TxD_data_r[1];
BIT_2: TxD <= TxD_data_r[2];
BIT_3: TxD <= TxD_data_r[3];
BIT_4: TxD <= TxD_data_r[4];
BIT_5: TxD <= TxD_data_r[5];
BIT_6: TxD <= TxD_data_r[6];
BIT_7: TxD <= TxD_data_r[7];
STOP: TxD <= 1'b1;
default: TxD <= 1'bx;
endcase
end
endmodule
|
`timescale 1ns/1ps
module SensorFSM #(
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// top level
input Enable_i,
output reg CpuIntr_o,
output [2*DataWidth-1:0] SensorValue_o,
// to/from Measure-FSM
output reg MeasureFSM_Start_o,
input MeasureFSM_Done_i,
input MeasureFSM_Error_i,
input [DataWidth-1:0] MeasureFSM_Byte0_i,
input [DataWidth-1:0] MeasureFSM_Byte1_i,
// parameters
input [2*DataWidth-1:0] ParamThreshold_i,
input [2*DataWidth-1:0] ParamCounterPreset_i
);
// Sensor FSM
localparam stDisabled = 3'b000;
localparam stIdle = 3'b001;
localparam stXfer = 3'b010;
localparam stNotify = 3'b011;
localparam stError = 3'b100;
reg [2:0] SensorFSM_State;
reg [2:0] SensorFSM_NextState;
wire SensorFSM_TimerOvfl;
reg SensorFSM_TimerPreset;
reg SensorFSM_TimerEnable;
wire SensorFSM_DiffTooLarge;
reg SensorFSM_StoreNewValue;
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic
// interconnecting signals
wire [2*DataWidth-1:0] SensorValue;
reg [2*DataWidth-1:0] Word0;
wire [2*DataWidth-1:0] AbsDiffResult;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_State <= stDisabled;
end
else
begin
SensorFSM_State <= SensorFSM_NextState;
end
end
always @(SensorFSM_State, Enable_i, SensorFSM_TimerOvfl, MeasureFSM_Done_i, MeasureFSM_Error_i, SensorFSM_DiffTooLarge)
begin // process SensorFSM_CombProc
SensorFSM_NextState = SensorFSM_State;
// control signal default values
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0;
MeasureFSM_Start_o = 1'b0;
SensorFSM_StoreNewValue = 1'b0;
CpuIntr_o = 1'b0;
// next state and output logic
case (SensorFSM_State)
stDisabled: begin
if (Enable_i == 1'b1)
begin
SensorFSM_NextState = stIdle;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // start timer
end
end
stIdle: begin
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
else
if (SensorFSM_TimerOvfl == 1'b1)
begin
SensorFSM_NextState = stXfer;
MeasureFSM_Start_o = 1'b1;
end
end
stXfer: begin
if (MeasureFSM_Error_i == 1'b1)
begin
// on I2C Error go to state "stError" and notify the CPU
SensorFSM_NextState = stError;
CpuIntr_o = 1'b1; // notify CPU
end
else if (MeasureFSM_Done_i == 1'b1)
begin
if (SensorFSM_DiffTooLarge == 1'b1)
begin
SensorFSM_NextState = stNotify;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
SensorFSM_StoreNewValue = 1'b1; // store new value
end
else
begin
SensorFSM_NextState = stIdle;
end
end
end
stNotify: begin
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0; // preset timer
SensorFSM_NextState = stIdle;
CpuIntr_o = 1'b1; // notify CPU
end
stError: begin
// stay in this error state until the FSM is disabled
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [2*DataWidth-1:0] SensorFSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_Timer <= 16'd0;
end
else
begin
if (SensorFSM_TimerPreset)
begin
SensorFSM_Timer <= ParamCounterPreset_i;
end
else if (SensorFSM_TimerEnable)
begin
SensorFSM_Timer <= SensorFSM_Timer - 1'b1;
end
end
end
assign SensorFSM_TimerOvfl = (SensorFSM_Timer == 0) ? 1'b1 : 1'b0;
assign SensorValue = {MeasureFSM_Byte1_i, MeasureFSM_Byte0_i};
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Word0 <= 16'd0;
end
else
begin
if (SensorFSM_StoreNewValue)
begin
Word0 <= SensorValue;
end
end
end
wire [2*DataWidth : 0] DiffAB;
wire [2*DataWidth-1 : 0] DiffBA;
assign DiffAB = {1'b0, SensorValue} - {1'b0, Word0};
assign DiffBA = Word0 - SensorValue;
assign AbsDiffResult = DiffAB[2*DataWidth] ? DiffBA : DiffAB[2*DataWidth-1 : 0];
assign SensorFSM_DiffTooLarge = (AbsDiffResult > ParamThreshold_i) ? 1'b1 : 1'b0;
assign SensorValue_o = Word0;
endmodule // SensorFSM
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dll_img_ram (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [15 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("dll_img_ram.mif"),
.C_INIT_FILE("dll_img_ram.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(65536),
.C_READ_DEPTH_A(65536),
.C_ADDRA_WIDTH(16),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(65536),
.C_READ_DEPTH_B(65536),
.C_ADDRB_WIDTH(16),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("NONE"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(1),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(1),
.C_COUNT_36K_BRAM("16"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 16.114201 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(16'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 21:40:37 09/26/2015
// Design Name: Multiplication
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/MultiplicationUnit/MultiplicationTest.v
// Project Name: DataUnit
////////////////////////////////////////////////////////////////////////////////
module MultiplicationTest;
reg Clock, Reset, Start;
reg [3:0] Multiplicant;
reg [3:0] Multiplier;
wire [7:0] Product;
Multiplication uut(Clock, Reset, Start, Multiplicant, Multiplier, Product);
always #5 Clock = ~Clock;
initial begin
Clock = 0; Reset = 0; Start = 0; Multiplicant = 13; Multiplier = 13; #10;
Reset = 1; #10;
Start = 1; #150;
Multiplicant = 9; Multiplier = 11; Reset = 0; #10;
Reset = 1; #10;
Start = 1; #150;
Multiplicant = 2; Multiplier = 2; Reset = 0; #10;
Reset = 1; #10;
Start = 1; #150;
Multiplicant = 5; Multiplier = 8; Reset = 0; #10;
Reset = 1; #10;
Start = 1; #150;
Multiplicant = 3; Multiplier = 14; Reset = 0; #10;
Reset = 1; #10;
Start = 1; #150;
$stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_SYMBOL_V
`define SKY130_FD_SC_MS__DFXBP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_SYMBOL_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_p0_acv_hard_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
pll_afi_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_avl_clk,
avl_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_write_clk,
pll_dqs_ena_clk,
pll_addr_cmd_clk,
phy_mem_dq,
phy_mem_dm,
phy_mem_ck,
phy_mem_ck_n,
mem_dqs,
mem_dqs_n,
dll_phy_delayctrl,
scc_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
seq_read_latency_counter,
seq_read_increment_vfifo_fr,
seq_read_increment_vfifo_hr,
phy_ddio_dmdout,
phy_ddio_dqdout,
phy_ddio_dqs_oe,
phy_ddio_dqsdout,
phy_ddio_dqsb_oe,
phy_ddio_dqslogic_oct,
phy_ddio_dqslogic_fiforeset,
phy_ddio_dqslogic_aclr_pstamble,
phy_ddio_dqslogic_aclr_fifoctrl,
phy_ddio_dqslogic_incwrptr,
phy_ddio_dqslogic_readlatency,
ddio_phy_dqslogic_rdatavalid,
ddio_phy_dqdin,
phy_ddio_dqslogic_incrdataen,
phy_ddio_dqslogic_dqsena,
phy_ddio_dqoe,
capture_strobe_tracking
);
parameter DEVICE_FAMILY = "";
parameter FAST_SIM_MODEL = 0;
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
localparam AFI_ADDRESS_WIDTH = 64;
localparam AFI_BANK_WIDTH = 12;
localparam AFI_CHIP_SELECT_WIDTH = 8;
localparam AFI_CLK_EN_WIDTH = 8;
localparam AFI_ODT_WIDTH = 8;
localparam AFI_DATA_MASK_WIDTH = 20;
localparam AFI_CONTROL_WIDTH = 4;
input reset_n_afi_clk;
input reset_n_addr_cmd_clk;
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
input pll_afi_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
input pll_avl_clk;
input avl_clk;
input pll_mem_clk;
input pll_mem_phy_clk;
input pll_write_clk;
input pll_dqs_ena_clk;
input pll_addr_cmd_clk;
inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
output [MEM_DM_WIDTH-1:0] phy_mem_dm;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
input scc_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
input [4:0] seq_read_latency_counter;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr;
input scc_upd;
output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
input [24 : 0] phy_ddio_dmdout;
input [179 : 0] phy_ddio_dqdout;
input [9 : 0] phy_ddio_dqs_oe;
input [19 : 0] phy_ddio_dqsdout;
input [9 : 0] phy_ddio_dqsb_oe;
input [9 : 0] phy_ddio_dqslogic_oct;
input [4 : 0] phy_ddio_dqslogic_fiforeset;
input [4 : 0] phy_ddio_dqslogic_aclr_pstamble;
input [4 : 0] phy_ddio_dqslogic_aclr_fifoctrl;
input [9 : 0] phy_ddio_dqslogic_incwrptr;
input [24 : 0] phy_ddio_dqslogic_readlatency;
output [4 : 0] ddio_phy_dqslogic_rdatavalid;
output [179 : 0] ddio_phy_dqdin;
input [9 : 0] phy_ddio_dqslogic_incrdataen;
input [9 : 0] phy_ddio_dqslogic_dqsena;
input [89 : 0] phy_ddio_dqoe;
wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
wire dqs_busout;
wire hr_clk = pll_avl_clk;
wire core_clk = pll_afi_clk;
wire reset_n_core_clk = reset_n_afi_clk;
lpddr2_cntrlr_p0_acv_hard_addr_cmd_pads uaddr_cmd_pads(
/*
.config_data_in(config_data_in),
.config_clock_in(config_clock_in),
.config_io_ena(config_io_ena),
.config_update(config_update),
*/
.reset_n (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk),
.pll_afi_clk (pll_afi_phy_clk),
.pll_mem_clk (pll_mem_phy_clk),
.pll_hr_clk (hr_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_phy_delayctrl),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (phy_mem_address),
.phy_mem_bank (phy_mem_bank),
.phy_mem_cs_n (phy_mem_cs_n),
.phy_mem_cke (phy_mem_cke),
.phy_mem_odt (phy_mem_odt),
.phy_mem_we_n (phy_mem_we_n),
.phy_mem_ras_n (phy_mem_ras_n),
.phy_mem_cas_n (phy_mem_cas_n),
.phy_mem_reset_n (phy_mem_reset_n),
.phy_mem_ck (phy_mem_ck),
.phy_mem_ck_n (phy_mem_ck_n)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = MEM_BANK_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = MEM_ODT_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = MEM_CONTROL_WIDTH * 4;
defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
defparam uaddr_cmd_pads.ADC_PHASE_SETTING = ADC_PHASE_SETTING;
defparam uaddr_cmd_pads.ADC_INVERT_PHASE = ADC_INVERT_PHASE;
defparam uaddr_cmd_pads.IS_HHP_HPS = IS_HHP_HPS;
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam NATIVE_GROUP_SIZE =
(DQDQS_DATA_WIDTH == 8) ? 9 : DQDQS_DATA_WIDTH;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
lpddr2_cntrlr_p0_altdqdqs ubidir_dq_dqs (
.write_strobe_clock_in (pll_mem_phy_clk),
.reset_n_core_clock_in (reset_n_core_clk),
.core_clock_in (core_clk),
.fr_clock_in (pll_write_clk),
.hr_clock_in (pll_avl_phy_clk),
.parallelterminationcontrol_in(oct_ctl_rt_value),
.seriesterminationcontrol_in(oct_ctl_rs_value),
.strobe_ena_hr_clock_in (hr_clk),
.capture_strobe_tracking (capture_strobe_tracking[i]),
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.read_data_out (ddio_phy_dqdin[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
.capture_strobe_out(dqs_busout),
.extra_write_data_in (phy_ddio_dmdout[(i + 1) * 4 - 1 : (i * 4)]),
.write_data_in (phy_ddio_dqdout[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
.write_oe_in (phy_ddio_dqoe[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*2-1) : (NATIVE_GROUP_SIZE*i*2)]),
.strobe_io (mem_dqs[i]),
.strobe_n_io (mem_dqs_n[i]),
.output_strobe_ena(phy_ddio_dqs_oe[(i + 1) * 2 - 1 : (i * 2)]),
.write_strobe(phy_ddio_dqsdout[(i + 1) * 4 - 1 : (i * 4)]),
.oct_ena_in(phy_ddio_dqslogic_oct[(i + 1) * 2 - 1 : (i * 2)]),
.extra_write_data_out (phy_mem_dm[i]),
.config_data_in (scc_data),
.config_dqs_ena (scc_dqs_ena[i]),
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.config_dqs_io_ena (scc_dqs_io_ena[i]),
.config_update (scc_upd),
.config_clock_in (scc_clk),
.config_extra_io_ena (scc_dm_ena[i]),
.lfifo_rdata_en(phy_ddio_dqslogic_incrdataen[(i + 1) * 2 - 1 : (i * 2)]),
.lfifo_rdata_en_full(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
.lfifo_rd_latency(phy_ddio_dqslogic_readlatency[(i + 1) * 5 - 1 : (i * 5)]),
.lfifo_reset_n (phy_ddio_dqslogic_aclr_fifoctrl[i]),
.lfifo_rdata_valid(ddio_phy_dqslogic_rdatavalid[i]),
.vfifo_qvld(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
.vfifo_inc_wr_ptr(phy_ddio_dqslogic_incwrptr[(i + 1) * 2 - 1 : (i * 2)]),
.vfifo_reset_n (phy_ddio_dqslogic_aclr_pstamble[i]),
.dll_delayctrl_in (dll_phy_delayctrl),
.rfifo_reset_n(phy_ddio_dqslogic_fiforeset[i])
);
end
endgenerate
generate
genvar j;
for (j = NUM_OF_DQDQS; j < 5; j=j+1)
begin: to_vcc
assign ddio_phy_dqslogic_rdatavalid[j] = 1'b1;
end
endgenerate
endmodule
|
/* Generated by Yosys 0.11+10 (git sha1 4871d8f19, clang 10.0.0-4ubuntu1 -fPIC -Os) */
(* \nmigen.hierarchy = "Cfu" *)
(* top = 1 *)
(* generator = "nMigen" *)
module Cfu(cmd_ready, cmd_payload_function_id, cmd_payload_inputs_0, cmd_payload_inputs_1, rsp_valid, rsp_ready, rsp_payload_outputs_0, reset, clk, rst, cmd_valid);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:199" *)
wire [32:0] \$27 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:199" *)
wire [32:0] \$28 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:229" *)
wire [31:0] \$signal ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:230" *)
wire \$signal$30 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:231" *)
reg \$signal$31 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:229" *)
wire [31:0] \$signal$32 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:230" *)
wire \$signal$33 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:231" *)
reg \$signal$34 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:229" *)
wire [31:0] \$signal$35 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:230" *)
wire \$signal$36 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:231" *)
reg \$signal$37 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:229" *)
wire [31:0] \$signal$38 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:230" *)
wire \$signal$39 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:231" *)
reg \$signal$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:229" *)
wire [31:0] \$signal$41 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:230" *)
wire \$signal$42 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:231" *)
reg \$signal$44 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:229" *)
wire [31:0] \$signal$45 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:230" *)
wire \$signal$46 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:231" *)
reg \$signal$48 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:229" *)
wire [31:0] \$signal$49 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:230" *)
wire \$signal$50 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:231" *)
reg \$signal$52 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:229" *)
wire [31:0] \$signal$53 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:230" *)
wire \$signal$54 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:231" *)
reg \$signal$55 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire [31:0] add_one_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire add_one_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire add_one_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire [31:0] add_one_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire add_one_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire add_one_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:172" *)
input [9:0] cmd_payload_function_id;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:174" *)
input [31:0] cmd_payload_inputs_0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:175" *)
input [31:0] cmd_payload_inputs_1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:171" *)
output cmd_ready;
reg cmd_ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:170" *)
input cmd_valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:225" *)
reg current_function_done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:224" *)
reg [2:0] current_function_id;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
wire fallback3_done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
wire [31:0] fallback3_in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
wire [31:0] fallback3_in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
wire [31:0] fallback3_output;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
wire fallback4_done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
wire [31:0] fallback4_in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
wire [31:0] fallback4_in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
wire [31:0] fallback4_output;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
wire fallback5_done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
wire [31:0] fallback5_in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
wire [31:0] fallback5_in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
wire [31:0] fallback5_output;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
wire fallback6_done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
wire [31:0] fallback6_in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
wire [31:0] fallback6_in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
wire [31:0] fallback6_output;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire [127:0] filter_flow_restrictor_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire filter_flow_restrictor_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire filter_flow_restrictor_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire [127:0] filter_flow_restrictor_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire filter_flow_restrictor_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire filter_flow_restrictor_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
wire [31:0] filter_flow_restrictor_release__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
wire filter_flow_restrictor_release__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:60" *)
wire [31:0] filter_store_data_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:60" *)
wire filter_store_data_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:60" *)
wire filter_store_data_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:62" *)
wire [127:0] filter_store_data_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:62" *)
wire filter_store_data_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:62" *)
wire filter_store_data_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:61" *)
wire [31:0] filter_store_num_words_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:61" *)
wire filter_store_num_words_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:61" *)
wire filter_store_num_words_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
reg [1:0] fsm_state = 2'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
reg [1:0] \fsm_state$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:217" *)
wire [2:0] funct3;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:218" *)
wire [6:0] funct7;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
wire [6:0] \funct7$56 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
wire [6:0] \funct7$57 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
wire [6:0] \funct7$58 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
wire [6:0] \funct7$59 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
wire [6:0] \funct7$60 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
wire get_done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
wire [6:0] get_funct7;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
wire [31:0] get_in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
wire [31:0] get_in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
wire [31:0] get_output;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
wire [31:0] get_sink_30__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
wire get_sink_30__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
wire get_sink_30__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
wire [31:0] get_sink_44__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
wire get_sink_44__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
wire get_sink_44__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
wire [31:0] get_sink_70__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
wire get_sink_70__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
wire get_sink_70__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
wire get_start;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire [127:0] input_flow_restrictor_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire input_flow_restrictor_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire input_flow_restrictor_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire [127:0] input_flow_restrictor_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire input_flow_restrictor_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire input_flow_restrictor_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
wire [31:0] input_flow_restrictor_release__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
wire input_flow_restrictor_release__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:52" *)
wire [31:0] input_store_data_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:52" *)
wire input_store_data_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:52" *)
wire input_store_data_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:54" *)
wire [127:0] input_store_data_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:54" *)
wire input_store_data_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:54" *)
wire input_store_data_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:53" *)
wire [31:0] input_store_num_words_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:53" *)
wire input_store_num_words_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:53" *)
wire input_store_num_words_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:56" *)
wire macc_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:57" *)
wire [8:0] macc_offset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:58" *)
wire [127:0] macc_operands__payload__filters;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:58" *)
wire [127:0] macc_operands__payload__inputs;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:58" *)
wire macc_operands__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:58" *)
wire macc_operands__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:60" *)
wire [31:0] macc_result__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:60" *)
wire macc_result__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:60" *)
wire macc_result__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:172" *)
wire [15:0] op_store_read_data__bias;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:172" *)
wire [31:0] op_store_read_data__multiplier;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:172" *)
wire [3:0] op_store_read_data__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:171" *)
wire op_store_read_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:168" *)
wire op_store_reset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:170" *)
wire [15:0] op_store_write_data__bias;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:170" *)
wire [31:0] op_store_write_data__multiplier;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:170" *)
wire [3:0] op_store_write_data__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:169" *)
reg op_store_write_enable = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:169" *)
reg \op_store_write_enable$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:123" *)
wire [127:0] operands_buffer_output__payload__filters;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:123" *)
wire [127:0] operands_buffer_output__payload__inputs;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:123" *)
wire operands_buffer_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:123" *)
wire operands_buffer_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
wire [127:0] operands_buffer_payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
wire [127:0] \operands_buffer_payload$25 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
wire operands_buffer_ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
wire \operands_buffer_ready$26 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
wire operands_buffer_valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
wire \operands_buffer_valid$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
wire [31:0] \output ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
wire ping_done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
wire [31:0] ping_in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
wire [31:0] ping_in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
wire [31:0] ping_output;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
wire ping_start;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:368" *)
wire [7:0] pp_activation_max;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:367" *)
wire [7:0] pp_activation_min;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
wire pp_done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
wire [6:0] pp_funct7;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
wire [31:0] pp_in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
wire [31:0] pp_in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:366" *)
wire [8:0] pp_offset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
wire [31:0] pp_output;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:369" *)
wire [15:0] pp_read_data__bias;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:369" *)
wire [31:0] pp_read_data__multiplier;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:369" *)
wire [3:0] pp_read_data__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:370" *)
wire pp_read_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:371" *)
wire [31:0] pp_result__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:371" *)
wire pp_result__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:371" *)
wire pp_result__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
wire pp_start;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:179" *)
input reset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:83" *)
wire [31:0] result_accumulator_accumulated__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:83" *)
wire result_accumulator_accumulated__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:83" *)
wire result_accumulator_accumulated__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:81" *)
wire [31:0] result_accumulator_num_results__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:81" *)
wire result_accumulator_num_results__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:82" *)
wire [31:0] result_accumulator_results__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:82" *)
wire result_accumulator_results__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:82" *)
wire result_accumulator_results__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:178" *)
output [31:0] rsp_payload_outputs_0;
reg [31:0] rsp_payload_outputs_0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:177" *)
input rsp_ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:176" *)
output rsp_valid;
reg rsp_valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
output rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \set_$signal ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \set_$signal$16 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \set_$signal$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \set_$signal$18 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
wire \set_$signal$19 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
wire \set_$signal$20 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \set_$signal$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \set_$signal$22 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \set_$signal$23 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
wire set_done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
wire [6:0] set_funct7;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
wire [31:0] set_in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
wire [31:0] set_in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] set_payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \set_payload$11 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \set_payload$13 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \set_payload$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \set_payload$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \set_payload$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire set_ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_ready$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_ready$15 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_ready$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_ready$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_ready$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
wire set_start;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire set_valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_valid$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_valid$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_valid$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_valid$4 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \set_valid$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
wire start;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
wire \start$43 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
wire \start$47 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
wire \start$51 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:223" *)
reg [2:0] stored_function_id = 3'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:223" *)
reg [2:0] \stored_function_id$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:226" *)
reg [31:0] stored_output = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:226" *)
reg [31:0] \stored_output$next ;
assign \$28 = - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:199" *) \set_$signal$18 ;
always @(posedge clk)
stored_output <= \stored_output$next ;
always @(posedge clk)
fsm_state <= \fsm_state$next ;
always @(posedge clk)
stored_function_id <= \stored_function_id$next ;
always @(posedge clk)
op_store_write_enable <= \op_store_write_enable$next ;
add_one add_one (
.input__payload(add_one_input__payload),
.input__ready(add_one_input__ready),
.input__valid(add_one_input__valid),
.output__payload(add_one_output__payload),
.output__ready(add_one_output__ready),
.output__valid(add_one_output__valid)
);
fallback3 fallback3 (
.done(fallback3_done),
.in0(fallback3_in0),
.in1(fallback3_in1),
.\output (fallback3_output)
);
fallback4 fallback4 (
.done(fallback4_done),
.in0(fallback4_in0),
.in1(fallback4_in1),
.\output (fallback4_output)
);
fallback5 fallback5 (
.done(fallback5_done),
.in0(fallback5_in0),
.in1(fallback5_in1),
.\output (fallback5_output)
);
fallback6 fallback6 (
.done(fallback6_done),
.in0(fallback6_in0),
.in1(fallback6_in1),
.\output (fallback6_output)
);
filter_flow_restrictor filter_flow_restrictor (
.clk(clk),
.input__payload(filter_flow_restrictor_input__payload),
.input__ready(filter_flow_restrictor_input__ready),
.input__valid(filter_flow_restrictor_input__valid),
.output__payload(filter_flow_restrictor_output__payload),
.output__ready(filter_flow_restrictor_output__ready),
.output__valid(filter_flow_restrictor_output__valid),
.release__payload(filter_flow_restrictor_release__payload),
.release__valid(filter_flow_restrictor_release__valid),
.rst(rst)
);
filter_store filter_store (
.clk(clk),
.data_input__payload(filter_store_data_input__payload),
.data_input__ready(filter_store_data_input__ready),
.data_input__valid(filter_store_data_input__valid),
.data_output__payload(filter_store_data_output__payload),
.data_output__ready(filter_store_data_output__ready),
.data_output__valid(filter_store_data_output__valid),
.num_words_input__payload(filter_store_num_words_input__payload),
.num_words_input__ready(filter_store_num_words_input__ready),
.num_words_input__valid(filter_store_num_words_input__valid),
.rst(rst)
);
get get (
.clk(clk),
.done(get_done),
.funct7(get_funct7),
.in0(get_in0),
.in1(get_in1),
.\output (get_output),
.rst(rst),
.sink_30__payload(get_sink_30__payload),
.sink_30__ready(get_sink_30__ready),
.sink_30__valid(get_sink_30__valid),
.sink_44__payload(get_sink_44__payload),
.sink_44__ready(get_sink_44__ready),
.sink_44__valid(get_sink_44__valid),
.sink_70__payload(get_sink_70__payload),
.sink_70__ready(get_sink_70__ready),
.sink_70__valid(get_sink_70__valid),
.start(get_start)
);
input_flow_restrictor input_flow_restrictor (
.clk(clk),
.input__payload(input_flow_restrictor_input__payload),
.input__ready(input_flow_restrictor_input__ready),
.input__valid(input_flow_restrictor_input__valid),
.output__payload(input_flow_restrictor_output__payload),
.output__ready(input_flow_restrictor_output__ready),
.output__valid(input_flow_restrictor_output__valid),
.release__payload(input_flow_restrictor_release__payload),
.release__valid(input_flow_restrictor_release__valid),
.rst(rst)
);
input_store input_store (
.clk(clk),
.data_input__payload(input_store_data_input__payload),
.data_input__ready(input_store_data_input__ready),
.data_input__valid(input_store_data_input__valid),
.data_output__payload(input_store_data_output__payload),
.data_output__ready(input_store_data_output__ready),
.data_output__valid(input_store_data_output__valid),
.num_words_input__payload(input_store_num_words_input__payload),
.num_words_input__ready(input_store_num_words_input__ready),
.num_words_input__valid(input_store_num_words_input__valid),
.rst(rst)
);
macc macc (
.clk(clk),
.enable(1'h1),
.offset(macc_offset),
.operands__payload__filters(macc_operands__payload__filters),
.operands__payload__inputs(macc_operands__payload__inputs),
.operands__ready(macc_operands__ready),
.operands__valid(macc_operands__valid),
.result__payload(macc_result__payload),
.result__ready(macc_result__ready),
.result__valid(macc_result__valid),
.rst(rst)
);
op_store op_store (
.clk(clk),
.read_data__bias(op_store_read_data__bias),
.read_data__multiplier(op_store_read_data__multiplier),
.read_data__shift(op_store_read_data__shift),
.read_enable(op_store_read_enable),
.reset(op_store_reset),
.rst(rst),
.write_data__bias(op_store_write_data__bias),
.write_data__multiplier(op_store_write_data__multiplier),
.write_data__shift(op_store_write_data__shift),
.write_enable(op_store_write_enable)
);
operands_buffer operands_buffer (
.clk(clk),
.output__payload__filters(operands_buffer_output__payload__filters),
.output__payload__inputs(operands_buffer_output__payload__inputs),
.output__ready(operands_buffer_output__ready),
.output__valid(operands_buffer_output__valid),
.payload(operands_buffer_payload),
.\payload$2 (\operands_buffer_payload$25 ),
.ready(operands_buffer_ready),
.\ready$3 (\operands_buffer_ready$26 ),
.rst(rst),
.valid(operands_buffer_valid),
.\valid$1 (\operands_buffer_valid$24 )
);
ping ping (
.clk(clk),
.done(ping_done),
.in0(ping_in0),
.in1(ping_in1),
.\output (ping_output),
.rst(rst),
.start(ping_start)
);
pp pp (
.activation_max(pp_activation_max),
.activation_min(pp_activation_min),
.clk(clk),
.done(pp_done),
.funct7(pp_funct7),
.in0(pp_in0),
.in1(pp_in1),
.offset(pp_offset),
.\output (pp_output),
.read_data__bias(pp_read_data__bias),
.read_data__multiplier(pp_read_data__multiplier),
.read_data__shift(pp_read_data__shift),
.read_enable(pp_read_enable),
.result__payload(pp_result__payload),
.result__ready(pp_result__ready),
.result__valid(pp_result__valid),
.rst(rst),
.start(pp_start)
);
result_accumulator result_accumulator (
.accumulated__payload(result_accumulator_accumulated__payload),
.accumulated__ready(result_accumulator_accumulated__ready),
.accumulated__valid(result_accumulator_accumulated__valid),
.clk(clk),
.num_results__payload(result_accumulator_num_results__payload),
.num_results__valid(result_accumulator_num_results__valid),
.results__payload(result_accumulator_results__payload),
.results__ready(result_accumulator_results__ready),
.results__valid(result_accumulator_results__valid),
.rst(rst)
);
set set (
.\$signal (\set_$signal ),
.\$signal$16 (\set_$signal$16 ),
.\$signal$17 (\set_$signal$17 ),
.\$signal$18 (\set_$signal$18 ),
.\$signal$19 (\set_$signal$19 ),
.\$signal$20 (\set_$signal$20 ),
.\$signal$21 (\set_$signal$21 ),
.\$signal$22 (\set_$signal$22 ),
.\$signal$23 (\set_$signal$23 ),
.clk(clk),
.done(set_done),
.funct7(set_funct7),
.in0(set_in0),
.in1(set_in1),
.payload(set_payload),
.\payload$11 (\set_payload$11 ),
.\payload$13 (\set_payload$13 ),
.\payload$2 (\set_payload$2 ),
.\payload$5 (\set_payload$5 ),
.\payload$8 (\set_payload$8 ),
.ready(set_ready),
.\ready$12 (\set_ready$12 ),
.\ready$15 (1'h1),
.\ready$3 (\set_ready$3 ),
.\ready$6 (\set_ready$6 ),
.\ready$9 (\set_ready$9 ),
.rst(rst),
.start(set_start),
.valid(set_valid),
.\valid$1 (\set_valid$1 ),
.\valid$10 (\set_valid$10 ),
.\valid$14 (\set_valid$14 ),
.\valid$4 (\set_valid$4 ),
.\valid$7 (\set_valid$7 )
);
always @* begin
if (\initial ) begin end
rsp_valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_CMD/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:252" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" *)
casez (cmd_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" *)
casez (current_function_done)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" */
1'h1:
rsp_valid = 1'h1;
endcase
endcase
/* \nmigen.decoding = "WAIT_INSTRUCTION/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:263" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" *)
casez (current_function_done)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" */
1'h1:
rsp_valid = 1'h1;
endcase
/* \nmigen.decoding = "WAIT_TRANSFER/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:270" */
2'h1:
rsp_valid = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
rsp_payload_outputs_0 = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_CMD/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:252" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" *)
casez (cmd_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" *)
casez (current_function_done)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:241" *)
casez (current_function_id)
3'h0:
rsp_payload_outputs_0 = \$signal ;
3'h1:
rsp_payload_outputs_0 = \$signal$32 ;
3'h2:
rsp_payload_outputs_0 = \$signal$35 ;
3'h3:
rsp_payload_outputs_0 = \$signal$38 ;
3'h4:
rsp_payload_outputs_0 = \$signal$41 ;
3'h5:
rsp_payload_outputs_0 = \$signal$45 ;
3'h6:
rsp_payload_outputs_0 = \$signal$49 ;
3'h?:
rsp_payload_outputs_0 = \$signal$53 ;
endcase
endcase
endcase
/* \nmigen.decoding = "WAIT_INSTRUCTION/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:263" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" *)
casez (current_function_done)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:241" *)
casez (current_function_id)
3'h0:
rsp_payload_outputs_0 = \$signal ;
3'h1:
rsp_payload_outputs_0 = \$signal$32 ;
3'h2:
rsp_payload_outputs_0 = \$signal$35 ;
3'h3:
rsp_payload_outputs_0 = \$signal$38 ;
3'h4:
rsp_payload_outputs_0 = \$signal$41 ;
3'h5:
rsp_payload_outputs_0 = \$signal$45 ;
3'h6:
rsp_payload_outputs_0 = \$signal$49 ;
3'h?:
rsp_payload_outputs_0 = \$signal$53 ;
endcase
endcase
/* \nmigen.decoding = "WAIT_TRANSFER/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:270" */
2'h1:
rsp_payload_outputs_0 = stored_output;
endcase
end
always @* begin
if (\initial ) begin end
\fsm_state$next = fsm_state;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_CMD/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:252" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" *)
casez (cmd_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" *)
casez (current_function_done)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:242" *)
casez (rsp_ready)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:242" */
1'h1:
\fsm_state$next = 2'h0;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:244" */
default:
\fsm_state$next = 2'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:248" */
default:
\fsm_state$next = 2'h2;
endcase
endcase
/* \nmigen.decoding = "WAIT_INSTRUCTION/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:263" */
2'h2:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" *)
casez (current_function_done)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:242" *)
casez (rsp_ready)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:242" */
1'h1:
\fsm_state$next = 2'h0;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:244" */
default:
\fsm_state$next = 2'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:248" */
default:
\fsm_state$next = 2'h2;
endcase
/* \nmigen.decoding = "WAIT_TRANSFER/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:270" */
2'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:275" *)
casez (rsp_ready)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:275" */
1'h1:
\fsm_state$next = 2'h0;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\fsm_state$next = 2'h0;
endcase
end
always @* begin
if (\initial ) begin end
\stored_output$next = stored_output;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_CMD/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:252" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" *)
casez (cmd_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" *)
casez (current_function_done)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:242" *)
casez (rsp_ready)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:242" */
1'h1:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:244" */
default:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:246" *)
casez (current_function_id)
3'h0:
\stored_output$next = \$signal ;
3'h1:
\stored_output$next = \$signal$32 ;
3'h2:
\stored_output$next = \$signal$35 ;
3'h3:
\stored_output$next = \$signal$38 ;
3'h4:
\stored_output$next = \$signal$41 ;
3'h5:
\stored_output$next = \$signal$45 ;
3'h6:
\stored_output$next = \$signal$49 ;
3'h?:
\stored_output$next = \$signal$53 ;
endcase
endcase
endcase
endcase
/* \nmigen.decoding = "WAIT_INSTRUCTION/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:263" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" *)
casez (current_function_done)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:238" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:242" *)
casez (rsp_ready)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:242" */
1'h1:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:244" */
default:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:246" *)
casez (current_function_id)
3'h0:
\stored_output$next = \$signal ;
3'h1:
\stored_output$next = \$signal$32 ;
3'h2:
\stored_output$next = \$signal$35 ;
3'h3:
\stored_output$next = \$signal$38 ;
3'h4:
\stored_output$next = \$signal$41 ;
3'h5:
\stored_output$next = \$signal$45 ;
3'h6:
\stored_output$next = \$signal$49 ;
3'h?:
\stored_output$next = \$signal$53 ;
endcase
endcase
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\stored_output$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\op_store_write_enable$next = \set_$signal$19 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\op_store_write_enable$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
current_function_id = 3'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_CMD/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:252" */
2'h0:
current_function_id = funct3;
/* \nmigen.decoding = "WAIT_INSTRUCTION/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:263" */
2'h2:
current_function_id = stored_function_id;
endcase
end
always @* begin
if (\initial ) begin end
current_function_done = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_CMD/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:252" */
2'h0:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:256" *)
casez (current_function_id)
3'h0:
current_function_done = \$signal$30 ;
3'h1:
current_function_done = \$signal$33 ;
3'h2:
current_function_done = \$signal$36 ;
3'h3:
current_function_done = \$signal$39 ;
3'h4:
current_function_done = \$signal$42 ;
3'h5:
current_function_done = \$signal$46 ;
3'h6:
current_function_done = \$signal$50 ;
3'h?:
current_function_done = \$signal$54 ;
endcase
/* \nmigen.decoding = "WAIT_INSTRUCTION/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:263" */
2'h2:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:268" *)
casez (current_function_id)
3'h0:
current_function_done = \$signal$30 ;
3'h1:
current_function_done = \$signal$33 ;
3'h2:
current_function_done = \$signal$36 ;
3'h3:
current_function_done = \$signal$39 ;
3'h4:
current_function_done = \$signal$42 ;
3'h5:
current_function_done = \$signal$46 ;
3'h6:
current_function_done = \$signal$50 ;
3'h?:
current_function_done = \$signal$54 ;
endcase
endcase
end
always @* begin
if (\initial ) begin end
cmd_ready = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_CMD/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:252" */
2'h0:
cmd_ready = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
\stored_function_id$next = stored_function_id;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_CMD/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:252" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" *)
casez (cmd_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" */
1'h1:
\stored_function_id$next = cmd_payload_function_id[2:0];
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\stored_function_id$next = 3'h0;
endcase
end
always @* begin
if (\initial ) begin end
\$signal$31 = 1'h0;
\$signal$34 = 1'h0;
\$signal$37 = 1'h0;
\$signal$40 = 1'h0;
\$signal$44 = 1'h0;
\$signal$48 = 1'h0;
\$signal$52 = 1'h0;
\$signal$55 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:251" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_CMD/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:252" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" *)
casez (cmd_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:258" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:261" *)
casez (current_function_id)
3'h0:
\$signal$31 = 1'h1;
3'h1:
\$signal$34 = 1'h1;
3'h2:
\$signal$37 = 1'h1;
3'h3:
\$signal$40 = 1'h1;
3'h4:
\$signal$44 = 1'h1;
3'h5:
\$signal$48 = 1'h1;
3'h6:
\$signal$52 = 1'h1;
3'h?:
\$signal$55 = 1'h1;
endcase
endcase
endcase
end
assign \$27 = \$28 ;
assign \output = 32'd0;
assign rst = reset;
assign \funct7$60 = funct7;
assign ping_in1 = cmd_payload_inputs_1;
assign ping_in0 = cmd_payload_inputs_0;
assign \funct7$59 = funct7;
assign fallback6_in1 = cmd_payload_inputs_1;
assign fallback6_in0 = cmd_payload_inputs_0;
assign \funct7$58 = funct7;
assign fallback5_in1 = cmd_payload_inputs_1;
assign fallback5_in0 = cmd_payload_inputs_0;
assign \funct7$57 = funct7;
assign fallback4_in1 = cmd_payload_inputs_1;
assign fallback4_in0 = cmd_payload_inputs_0;
assign \funct7$56 = funct7;
assign fallback3_in1 = cmd_payload_inputs_1;
assign fallback3_in0 = cmd_payload_inputs_0;
assign pp_funct7 = funct7;
assign pp_in1 = cmd_payload_inputs_1;
assign pp_in0 = cmd_payload_inputs_0;
assign get_funct7 = funct7;
assign get_in1 = cmd_payload_inputs_1;
assign get_in0 = cmd_payload_inputs_0;
assign set_funct7 = funct7;
assign set_in1 = cmd_payload_inputs_1;
assign set_in0 = cmd_payload_inputs_0;
assign ping_start = \$signal$55 ;
assign \$signal$54 = ping_done;
assign \$signal$53 = ping_output;
assign \start$51 = \$signal$52 ;
assign \$signal$50 = fallback6_done;
assign \$signal$49 = fallback6_output;
assign \start$47 = \$signal$48 ;
assign \$signal$46 = fallback5_done;
assign \$signal$45 = fallback5_output;
assign \start$43 = \$signal$44 ;
assign \$signal$42 = fallback4_done;
assign \$signal$41 = fallback4_output;
assign start = \$signal$40 ;
assign \$signal$39 = fallback3_done;
assign \$signal$38 = fallback3_output;
assign pp_start = \$signal$37 ;
assign \$signal$36 = pp_done;
assign \$signal$35 = pp_output;
assign get_start = \$signal$34 ;
assign \$signal$33 = get_done;
assign \$signal$32 = get_output;
assign set_start = \$signal$31 ;
assign \$signal$30 = set_done;
assign \$signal = 32'd0;
assign pp_result__ready = get_sink_44__ready;
assign get_sink_44__payload = pp_result__payload;
assign get_sink_44__valid = pp_result__valid;
assign op_store_read_enable = pp_read_enable;
assign { pp_read_data__shift, pp_read_data__multiplier, pp_read_data__bias } = { op_store_read_data__shift, op_store_read_data__multiplier, op_store_read_data__bias };
assign pp_activation_max = \set_$signal$23 [7:0];
assign pp_activation_min = \set_$signal$22 [7:0];
assign pp_offset = \set_$signal$21 [8:0];
assign op_store_reset = \set_$signal$20 ;
assign op_store_write_data__shift = \$28 [3:0];
assign op_store_write_data__multiplier = \set_$signal$17 ;
assign op_store_write_data__bias = \set_$signal$16 [15:0];
assign result_accumulator_accumulated__ready = get_sink_30__ready;
assign get_sink_30__payload = result_accumulator_accumulated__payload;
assign get_sink_30__valid = result_accumulator_accumulated__valid;
assign result_accumulator_num_results__valid = \set_valid$14 ;
assign result_accumulator_num_results__payload = \set_payload$13 ;
assign macc_result__ready = result_accumulator_results__ready;
assign result_accumulator_results__payload = macc_result__payload;
assign result_accumulator_results__valid = macc_result__valid;
assign operands_buffer_output__ready = macc_operands__ready;
assign { macc_operands__payload__filters, macc_operands__payload__inputs } = { operands_buffer_output__payload__filters, operands_buffer_output__payload__inputs };
assign macc_operands__valid = operands_buffer_output__valid;
assign filter_flow_restrictor_output__ready = \operands_buffer_ready$26 ;
assign \operands_buffer_payload$25 = filter_flow_restrictor_output__payload;
assign \operands_buffer_valid$24 = filter_flow_restrictor_output__valid;
assign input_flow_restrictor_output__ready = operands_buffer_ready;
assign operands_buffer_payload = input_flow_restrictor_output__payload;
assign operands_buffer_valid = input_flow_restrictor_output__valid;
assign filter_flow_restrictor_release__valid = \set_valid$14 ;
assign filter_flow_restrictor_release__payload = \set_payload$13 ;
assign filter_store_data_output__ready = filter_flow_restrictor_input__ready;
assign filter_flow_restrictor_input__payload = filter_store_data_output__payload;
assign filter_flow_restrictor_input__valid = filter_store_data_output__valid;
assign \set_ready$15 = 1'h1;
assign input_flow_restrictor_release__valid = \set_valid$14 ;
assign input_flow_restrictor_release__payload = \set_payload$13 ;
assign input_store_data_output__ready = input_flow_restrictor_input__ready;
assign input_flow_restrictor_input__payload = input_store_data_output__payload;
assign input_flow_restrictor_input__valid = input_store_data_output__valid;
assign macc_offset = \set_$signal [8:0];
assign macc_enable = 1'h1;
assign \set_ready$12 = filter_store_data_input__ready;
assign filter_store_data_input__payload = \set_payload$11 ;
assign filter_store_data_input__valid = \set_valid$10 ;
assign \set_ready$9 = filter_store_num_words_input__ready;
assign filter_store_num_words_input__payload = \set_payload$8 ;
assign filter_store_num_words_input__valid = \set_valid$7 ;
assign \set_ready$6 = input_store_data_input__ready;
assign input_store_data_input__payload = \set_payload$5 ;
assign input_store_data_input__valid = \set_valid$4 ;
assign \set_ready$3 = input_store_num_words_input__ready;
assign input_store_num_words_input__payload = \set_payload$2 ;
assign input_store_num_words_input__valid = \set_valid$1 ;
assign add_one_output__ready = get_sink_70__ready;
assign get_sink_70__payload = add_one_output__payload;
assign get_sink_70__valid = add_one_output__valid;
assign set_ready = add_one_input__ready;
assign add_one_input__payload = set_payload;
assign add_one_input__valid = set_valid;
assign funct7 = cmd_payload_function_id[9:3];
assign funct3 = cmd_payload_function_id[2:0];
endmodule
(* \nmigen.hierarchy = "Cfu.add_one" *)
(* generator = "nMigen" *)
module add_one(input__payload, input__ready, output__valid, output__payload, output__ready, input__valid);
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:59" *)
wire [32:0] \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:59" *)
wire [32:0] \$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input [31:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
output input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output [31:0] output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output output__valid;
assign \$2 = input__payload + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:59" *) 1'h1;
assign \$1 = \$2 ;
assign output__payload = \$2 [31:0];
assign output__valid = input__valid;
assign input__ready = output__ready;
endmodule
(* \nmigen.hierarchy = "Cfu.fallback3" *)
(* generator = "nMigen" *)
module fallback3(done, in0, in1, \output );
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
output done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
input [31:0] in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:54" *)
wire [31:0] in0s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
input [31:0] in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:55" *)
wire [31:0] in1s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
output [31:0] \output ;
assign in1s = in1;
assign in0s = in0;
assign done = 1'h1;
assign \output = in0;
endmodule
(* \nmigen.hierarchy = "Cfu.fallback4" *)
(* generator = "nMigen" *)
module fallback4(done, in0, in1, \output );
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
output done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
input [31:0] in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:54" *)
wire [31:0] in0s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
input [31:0] in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:55" *)
wire [31:0] in1s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
output [31:0] \output ;
assign in1s = in1;
assign in0s = in0;
assign done = 1'h1;
assign \output = in0;
endmodule
(* \nmigen.hierarchy = "Cfu.fallback5" *)
(* generator = "nMigen" *)
module fallback5(done, in0, in1, \output );
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
output done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
input [31:0] in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:54" *)
wire [31:0] in0s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
input [31:0] in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:55" *)
wire [31:0] in1s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
output [31:0] \output ;
assign in1s = in1;
assign in0s = in0;
assign done = 1'h1;
assign \output = in0;
endmodule
(* \nmigen.hierarchy = "Cfu.fallback6" *)
(* generator = "nMigen" *)
module fallback6(done, in0, in1, \output );
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
output done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
input [31:0] in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:54" *)
wire [31:0] in0s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
input [31:0] in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:55" *)
wire [31:0] in1s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
output [31:0] \output ;
assign in1s = in1;
assign in0s = in0;
assign done = 1'h1;
assign \output = in0;
endmodule
(* \nmigen.hierarchy = "Cfu.pp.fifo" *)
(* generator = "nMigen" *)
module fifo(clk, input__valid, input__payload, input__ready, output__valid, output__payload, output__ready, rst);
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:49" *)
input [31:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:49" *)
output input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:49" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:50" *)
output [31:0] output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:50" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:50" *)
output output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:83" *)
wire [31:0] wrapped_r_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:85" *)
wire wrapped_r_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:84" *)
wire wrapped_r_rdy;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:78" *)
wire [31:0] wrapped_w_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:80" *)
wire wrapped_w_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:79" *)
wire wrapped_w_rdy;
wrapped wrapped (
.clk(clk),
.r_data(wrapped_r_data),
.r_en(wrapped_r_en),
.r_rdy(wrapped_r_rdy),
.rst(rst),
.w_data(wrapped_w_data),
.w_en(wrapped_w_en),
.w_rdy(wrapped_w_rdy)
);
assign wrapped_r_en = output__ready;
assign output__payload = wrapped_r_data;
assign output__valid = wrapped_r_rdy;
assign input__ready = wrapped_w_rdy;
assign wrapped_w_data = input__payload;
assign wrapped_w_en = input__valid;
endmodule
(* \nmigen.hierarchy = "Cfu.filter_flow_restrictor" *)
(* generator = "nMigen" *)
module filter_flow_restrictor(input__payload, input__ready, release__payload, release__valid, output__valid, output__payload, output__ready, rst, clk, input__valid);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:61" *)
wire [32:0] \$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
wire \$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
wire \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:61" *)
wire [32:0] \$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input [127:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
output input__ready;
reg input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output [127:0] output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output output__valid;
reg output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
input [31:0] release__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
reg release__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
input release__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:56" *)
reg [31:0] release_counter = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:56" *)
reg [31:0] \release_counter$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$10 = release_counter - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:61" *) 1'h1;
assign \$12 = release__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) release__ready;
assign \$14 = release_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *) 1'h0;
assign \$1 = release_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *) 1'h0;
assign \$3 = release_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *) 1'h0;
assign \$5 = release_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *) 1'h0;
assign \$7 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
release_counter <= \release_counter$next ;
always @* begin
if (\initial ) begin end
input__ready = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" */
1'h1:
input__ready = output__ready;
endcase
end
always @* begin
if (\initial ) begin end
output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" */
1'h1:
output__valid = input__valid;
endcase
end
always @* begin
if (\initial ) begin end
\release_counter$next = release_counter;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
casez (\$5 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:60" *)
casez (\$7 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:60" */
1'h1:
\release_counter$next = \$10 [31:0];
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:62" */
default:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:64" *)
casez (\$12 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:64" */
1'h1:
\release_counter$next = release__payload;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\release_counter$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
release__ready = 1'h0;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
casez (\$14 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" */
1'h1:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:62" */
default:
release__ready = 1'h1;
endcase
end
assign \$9 = \$10 ;
assign output__payload = input__payload;
endmodule
(* \nmigen.hierarchy = "Cfu.filter_store" *)
(* generator = "nMigen" *)
module filter_store(num_words_input__payload, num_words_input__ready, data_input__valid, data_input__payload, data_input__ready, data_output__valid, data_output__payload, data_output__ready, rst, clk, num_words_input__valid);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *)
wire \$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:78" *)
wire [12:0] \$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:78" *)
wire [12:0] \$13 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *)
wire \$15 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *)
wire \$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *)
wire \$19 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:94" *)
wire [11:0] \$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:94" *)
wire [11:0] \$22 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:94" *)
wire [11:0] \$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:94" *)
wire [12:0] \$25 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:94" *)
wire \$27 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *)
wire \$30 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$32 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *)
wire \$34 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$36 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$38 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *)
wire [12:0] \$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *)
wire \$42 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *)
wire \$44 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$46 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *)
wire \$48 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:76" *)
wire [11:0] \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *)
wire \$50 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$52 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *)
wire \$54 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *)
wire \$56 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *)
wire \$58 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:76" *)
wire [11:0] \$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *)
wire \$60 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *)
wire [12:0] \$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:60" *)
input [31:0] data_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:60" *)
output data_input__ready;
reg data_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:60" *)
input data_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:62" *)
output [127:0] data_output__payload;
reg [127:0] data_output__payload = 128'h00000000000000000000000000000000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:62" *)
reg [127:0] \data_output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:62" *)
input data_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:62" *)
output data_output__valid;
reg data_output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:62" *)
reg \data_output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
reg [1:0] fsm_state = 2'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
reg [1:0] \fsm_state$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:109" *)
reg [10:0] index = 11'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:109" *)
reg [10:0] \index$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:54" *)
reg [8:0] memory_read_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:55" *)
wire [127:0] memory_read_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:51" *)
reg [10:0] memory_write_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:52" *)
reg [31:0] memory_write_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:53" *)
reg memory_write_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:108" *)
reg [11:0] num_words = 12'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:108" *)
reg [11:0] \num_words$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:61" *)
input [31:0] num_words_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:61" *)
output num_words_input__ready;
reg num_words_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:61" *)
input num_words_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:85" *)
reg read_port_valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:85" *)
reg \read_port_valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:86" *)
reg read_started = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:86" *)
reg \read_started$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:110" *)
wire reset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$10 = index == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *) \$8 ;
assign \$13 = num_words - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:78" *) 3'h4;
assign \$15 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *) read_port_valid;
assign \$17 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *) read_started;
assign \$1 = num_words_input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) num_words_input__ready;
assign \$19 = \$15 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *) \$17 ;
assign \$22 = index + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:94" *) 3'h4;
assign \$25 = num_words - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:94" *) 3'h4;
assign \$27 = index == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:94" *) \$25 ;
assign \$24 = \$27 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:94" *) 12'h000 : \$22 ;
assign \$30 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *) data_output__valid;
assign \$32 = data_output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_output__ready;
assign \$34 = \$30 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *) \$32 ;
assign \$36 = num_words_input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) num_words_input__ready;
assign \$38 = data_input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_input__ready;
assign \$3 = data_input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_input__ready;
assign \$40 = num_words - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *) 1'h1;
assign \$42 = index == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *) \$40 ;
assign \$44 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *) data_output__valid;
assign \$46 = data_output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_output__ready;
assign \$48 = \$44 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *) \$46 ;
assign \$50 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *) data_output__valid;
assign \$52 = data_output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_output__ready;
assign \$54 = \$50 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *) \$52 ;
assign \$56 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *) read_port_valid;
assign \$58 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *) read_started;
assign \$60 = \$56 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *) \$58 ;
assign \$6 = index + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:76" *) 1'h1;
assign \$8 = num_words - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *) 1'h1;
always @(posedge clk)
read_started <= \read_started$next ;
always @(posedge clk)
read_port_valid <= \read_port_valid$next ;
always @(posedge clk)
data_output__payload <= \data_output__payload$next ;
always @(posedge clk)
fsm_state <= \fsm_state$next ;
always @(posedge clk)
data_output__valid <= \data_output__valid$next ;
always @(posedge clk)
index <= \index$next ;
always @(posedge clk)
num_words <= \num_words$next ;
\memory$2 memory (
.clk(clk),
.read_addr(memory_read_addr),
.read_data(memory_read_data),
.write_addr(memory_write_addr),
.write_data(memory_write_data),
.write_enable(memory_write_enable)
);
always @* begin
if (\initial ) begin end
\num_words$next = num_words;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
\num_words$next = 12'h000;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:123" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:123" */
1'h1:
\num_words$next = num_words_input__payload[11:0];
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\num_words$next = 12'h000;
endcase
end
always @* begin
if (\initial ) begin end
memory_read_addr = 9'h000;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:130" */
2'h3:
memory_read_addr = index[10:2];
endcase
end
always @* begin
if (\initial ) begin end
\data_output__payload$next = data_output__payload;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:130" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *)
casez (\$48 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" */
1'h1:
\data_output__payload$next = memory_read_data;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\data_output__payload$next = 128'h00000000000000000000000000000000;
endcase
end
always @* begin
if (\initial ) begin end
\read_port_valid$next = read_port_valid;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:130" */
2'h3:
begin
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *)
casez (\$54 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" */
1'h1:
\read_port_valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:99" *)
casez (read_started)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:99" */
1'h1:
\read_port_valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:103" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:103" */
1'h1:
\read_port_valid$next = 1'h0;
endcase
end
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_port_valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\read_started$next = read_started;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:130" */
2'h3:
begin
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *)
casez (\$60 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" */
1'h1:
\read_started$next = 1'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:96" */
default:
\read_started$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:103" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:103" */
1'h1:
\read_started$next = 1'h0;
endcase
end
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_started$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\index$next = index;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
\index$next = 11'h000;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:75" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:75" */
1'h1:
begin
\index$next = \$6 [10:0];
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *)
casez (\$10 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" */
1'h1:
\index$next = \$13 [10:0];
endcase
end
endcase
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:130" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" *)
casez (\$19 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:93" */
1'h1:
\index$next = \$24 [10:0];
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\index$next = 11'h000;
endcase
end
always @* begin
if (\initial ) begin end
\data_output__valid$next = data_output__valid;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
\data_output__valid$next = 1'h0;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:130" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" *)
casez (\$34 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:88" */
1'h1:
\data_output__valid$next = read_port_valid;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\data_output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\fsm_state$next = fsm_state;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
\fsm_state$next = 2'h1;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:123" *)
casez (\$36 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:123" */
1'h1:
\fsm_state$next = 2'h2;
endcase
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
begin
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:75" *)
casez (\$38 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:75" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" *)
casez (\$42 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:77" */
1'h1:
\fsm_state$next = 2'h3;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:128" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:128" */
1'h1:
\fsm_state$next = 2'h0;
endcase
end
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:130" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:132" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:132" */
1'h1:
\fsm_state$next = 2'h0;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\fsm_state$next = 2'h0;
endcase
end
always @* begin
if (\initial ) begin end
num_words_input__ready = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
num_words_input__ready = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
memory_write_addr = 11'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
memory_write_addr = index;
endcase
end
always @* begin
if (\initial ) begin end
memory_write_data = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
memory_write_data = data_input__payload;
endcase
end
always @* begin
if (\initial ) begin end
memory_write_enable = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
memory_write_enable = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
data_input__ready = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:115" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:116" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:121" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/filter_store.py:126" */
2'h2:
data_input__ready = 1'h1;
endcase
end
assign \$5 = \$6 ;
assign \$12 = \$13 ;
assign \$21 = \$24 ;
assign reset = num_words_input__valid;
endmodule
(* \nmigen.hierarchy = "Cfu.pp.gearbox" *)
(* generator = "nMigen" *)
module gearbox(clk, input__valid, input__payload, input__ready, output__valid, output__payload, output__ready, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:64" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$13 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$15 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:47" *)
reg [1:0] fsm_state = 2'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:47" *)
reg [1:0] \fsm_state$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:37" *)
input [7:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:37" *)
output input__ready;
reg input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:37" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:38" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:38" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:38" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:38" *)
output output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:43" *)
reg [7:0] \register{i} = 8'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:43" *)
reg [7:0] \register{i}$11 = 8'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:43" *)
reg [7:0] \register{i}$11$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:43" *)
reg [7:0] \register{i}$12 = 8'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:43" *)
reg [7:0] \register{i}$12$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:43" *)
reg [7:0] \register{i}$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:44" *)
reg waiting_to_send = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:44" *)
reg \waiting_to_send$next ;
assign \$9 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
assign \$13 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
assign \$15 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$17 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
assign \$1 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:64" *) waiting_to_send;
assign \$3 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
assign \$5 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
assign \$7 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
waiting_to_send <= \waiting_to_send$next ;
always @(posedge clk)
\register{i}$12 <= \register{i}$12$next ;
always @(posedge clk)
\register{i}$11 <= \register{i}$11$next ;
always @(posedge clk)
fsm_state <= \fsm_state$next ;
always @(posedge clk)
\register{i} <= \register{i}$next ;
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:47" *)
casez (fsm_state)
/* \nmigen.decoding = "BYTE_0/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:48" */
2'h0:
input__ready = 1'h1;
/* \nmigen.decoding = "BYTE_1/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:53" */
2'h1:
input__ready = 1'h1;
/* \nmigen.decoding = "BYTE_2/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:58" */
2'h2:
input__ready = 1'h1;
/* \nmigen.decoding = "BYTE_3/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:63" */
2'h3:
input__ready = \$1 ;
endcase
end
always @* begin
if (\initial ) begin end
\register{i}$next = \register{i} ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:47" *)
casez (fsm_state)
/* \nmigen.decoding = "BYTE_0/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:48" */
2'h0:
\register{i}$next = input__payload;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\register{i}$next = 8'h00;
endcase
end
always @* begin
if (\initial ) begin end
\fsm_state$next = fsm_state;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:47" *)
casez (fsm_state)
/* \nmigen.decoding = "BYTE_0/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:48" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:51" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:51" */
1'h1:
\fsm_state$next = 2'h1;
endcase
/* \nmigen.decoding = "BYTE_1/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:53" */
2'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:56" *)
casez (\$5 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:56" */
1'h1:
\fsm_state$next = 2'h2;
endcase
/* \nmigen.decoding = "BYTE_2/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:58" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:61" *)
casez (\$7 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:61" */
1'h1:
\fsm_state$next = 2'h3;
endcase
/* \nmigen.decoding = "BYTE_3/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:63" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:65" *)
casez (\$9 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:65" */
1'h1:
\fsm_state$next = 2'h0;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\fsm_state$next = 2'h0;
endcase
end
always @* begin
if (\initial ) begin end
\register{i}$11$next = \register{i}$11 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:47" *)
casez (fsm_state)
/* \nmigen.decoding = "BYTE_0/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:48" */
2'h0:
/* empty */;
/* \nmigen.decoding = "BYTE_1/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:53" */
2'h1:
\register{i}$11$next = input__payload;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\register{i}$11$next = 8'h00;
endcase
end
always @* begin
if (\initial ) begin end
\register{i}$12$next = \register{i}$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:47" *)
casez (fsm_state)
/* \nmigen.decoding = "BYTE_0/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:48" */
2'h0:
/* empty */;
/* \nmigen.decoding = "BYTE_1/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:53" */
2'h1:
/* empty */;
/* \nmigen.decoding = "BYTE_2/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:58" */
2'h2:
\register{i}$12$next = input__payload;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\register{i}$12$next = 8'h00;
endcase
end
always @* begin
if (\initial ) begin end
\waiting_to_send$next = waiting_to_send;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:47" *)
casez (fsm_state)
/* \nmigen.decoding = "BYTE_0/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:48" */
2'h0:
/* empty */;
/* \nmigen.decoding = "BYTE_1/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:53" */
2'h1:
/* empty */;
/* \nmigen.decoding = "BYTE_2/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:58" */
2'h2:
/* empty */;
/* \nmigen.decoding = "BYTE_3/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:63" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:65" *)
casez (\$13 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:65" */
1'h1:
\waiting_to_send$next = 1'h1;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:73" *)
casez (\$15 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:73" */
1'h1:
\waiting_to_send$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\waiting_to_send$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:47" *)
casez (fsm_state)
/* \nmigen.decoding = "BYTE_0/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:48" */
2'h0:
/* empty */;
/* \nmigen.decoding = "BYTE_1/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:53" */
2'h1:
/* empty */;
/* \nmigen.decoding = "BYTE_2/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:58" */
2'h2:
/* empty */;
/* \nmigen.decoding = "BYTE_3/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:63" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:65" *)
casez (\$17 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:65" */
1'h1:
\output__payload$next = { input__payload, \register{i}$12 , \register{i}$11 , \register{i} };
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
assign output__valid = waiting_to_send;
endmodule
(* \nmigen.hierarchy = "Cfu.get" *)
(* generator = "nMigen" *)
module get(sink_70__payload, sink_70__ready, sink_30__valid, sink_30__payload, sink_30__ready, sink_44__valid, sink_44__payload, sink_44__ready, \output , done, start, in0, in1, funct7, rst, clk, sink_70__valid);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:154" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:154" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:122" *)
wire clear_30;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:122" *)
wire clear_44;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:122" *)
wire clear_70;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
output done;
reg done = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
reg \done$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:161" *)
reg [6:0] f7_buf = 7'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:161" *)
reg [6:0] \f7_buf$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:162" *)
reg [1:0] fsm_state = 2'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:162" *)
reg [1:0] \fsm_state$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
input [6:0] funct7;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
input [31:0] in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:54" *)
wire [31:0] in0s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
input [31:0] in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:55" *)
wire [31:0] in1s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
output [31:0] \output ;
reg [31:0] \output = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
reg [31:0] \output$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:123" *)
reg read_strobe_30 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:123" *)
reg \read_strobe_30$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:123" *)
reg read_strobe_44 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:123" *)
reg \read_strobe_44$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:123" *)
reg read_strobe_70 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:123" *)
reg \read_strobe_70$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
wire [31:0] reg_30_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
wire reg_30_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
wire reg_30_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:64" *)
wire reg_30_invalidate;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:65" *)
wire reg_30_valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:66" *)
wire [31:0] reg_30_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
wire [31:0] reg_44_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
wire reg_44_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
wire reg_44_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:64" *)
wire reg_44_invalidate;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:65" *)
wire reg_44_valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:66" *)
wire [31:0] reg_44_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
wire [31:0] reg_70_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
wire reg_70_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
wire reg_70_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:64" *)
wire reg_70_invalidate;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:65" *)
wire reg_70_valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:66" *)
wire [31:0] reg_70_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
input [31:0] sink_30__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
output sink_30__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
input sink_30__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
input [31:0] sink_44__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
output sink_44__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
input sink_44__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
input [31:0] sink_70__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
output sink_70__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:121" *)
input sink_70__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
input start;
always @(posedge clk)
done <= \done$next ;
always @(posedge clk)
\output <= \output$next ;
always @(posedge clk)
f7_buf <= \f7_buf$next ;
always @(posedge clk)
read_strobe_70 <= \read_strobe_70$next ;
always @(posedge clk)
read_strobe_44 <= \read_strobe_44$next ;
always @(posedge clk)
read_strobe_30 <= \read_strobe_30$next ;
always @(posedge clk)
fsm_state <= \fsm_state$next ;
reg_30 reg_30 (
.clk(clk),
.input__payload(reg_30_input__payload),
.input__ready(reg_30_input__ready),
.input__valid(reg_30_input__valid),
.invalidate(reg_30_invalidate),
.rst(rst),
.valid(reg_30_valid),
.value(reg_30_value)
);
reg_44 reg_44 (
.clk(clk),
.input__payload(reg_44_input__payload),
.input__ready(reg_44_input__ready),
.input__valid(reg_44_input__valid),
.invalidate(reg_44_invalidate),
.rst(rst),
.valid(reg_44_valid),
.value(reg_44_value)
);
\reg_70$1 reg_70 (
.clk(clk),
.input__payload(reg_70_input__payload),
.input__ready(reg_70_input__ready),
.input__valid(reg_70_input__valid),
.invalidate(1'h0),
.rst(rst),
.valid(reg_70_valid),
.value(reg_70_value)
);
always @* begin
if (\initial ) begin end
\read_strobe_70$next = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:162" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_START/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:163" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h70:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_70_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\read_strobe_70$next = 1'h1;
endcase
endcase
endcase
/* \nmigen.decoding = "GETTING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:167" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (f7_buf)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h70:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_70_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\read_strobe_70$next = 1'h1;
endcase
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_strobe_70$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\f7_buf$next = f7_buf;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:162" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_START/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:163" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" */
1'h1:
\f7_buf$next = funct7;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f7_buf$next = 7'h00;
endcase
end
always @* begin
if (\initial ) begin end
\output$next = \output ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:162" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_START/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:163" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_30_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\output$next = reg_30_value;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_44_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\output$next = reg_44_value;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h70:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_70_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\output$next = reg_70_value;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:138" */
default:
\output$next = 32'd0;
endcase
endcase
/* \nmigen.decoding = "GETTING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:167" */
2'h2:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (f7_buf)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_30_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\output$next = reg_30_value;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_44_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\output$next = reg_44_value;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h70:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_70_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\output$next = reg_70_value;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:138" */
default:
\output$next = 32'd0;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\done$next = done;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:162" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_START/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:163" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_30_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\done$next = 1'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_44_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\done$next = 1'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h70:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_70_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\done$next = 1'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:138" */
default:
\done$next = 1'h1;
endcase
endcase
/* \nmigen.decoding = "GETTING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:167" */
2'h2:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (f7_buf)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_30_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\done$next = 1'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_44_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\done$next = 1'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h70:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_70_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\done$next = 1'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:138" */
default:
\done$next = 1'h1;
endcase
/* \nmigen.decoding = "DONE/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:169" */
2'h1:
\done$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\done$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\fsm_state$next = fsm_state;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:162" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_START/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:163" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_30_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\fsm_state$next = 2'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:136" */
default:
\fsm_state$next = 2'h2;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_44_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\fsm_state$next = 2'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:136" */
default:
\fsm_state$next = 2'h2;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h70:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_70_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\fsm_state$next = 2'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:136" */
default:
\fsm_state$next = 2'h2;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:138" */
default:
\fsm_state$next = 2'h1;
endcase
endcase
/* \nmigen.decoding = "GETTING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:167" */
2'h2:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (f7_buf)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_30_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\fsm_state$next = 2'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:136" */
default:
\fsm_state$next = 2'h2;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_44_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\fsm_state$next = 2'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:136" */
default:
\fsm_state$next = 2'h2;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h70:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_70_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\fsm_state$next = 2'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:136" */
default:
\fsm_state$next = 2'h2;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:138" */
default:
\fsm_state$next = 2'h1;
endcase
/* \nmigen.decoding = "DONE/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:169" */
2'h1:
\fsm_state$next = 2'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\fsm_state$next = 2'h0;
endcase
end
always @* begin
if (\initial ) begin end
\read_strobe_30$next = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:162" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_START/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:163" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_30_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\read_strobe_30$next = 1'h1;
endcase
endcase
endcase
/* \nmigen.decoding = "GETTING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:167" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (f7_buf)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_30_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\read_strobe_30$next = 1'h1;
endcase
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_strobe_30$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\read_strobe_44$next = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:162" *)
casez (fsm_state)
/* \nmigen.decoding = "WAIT_START/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:163" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:164" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_44_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\read_strobe_44$next = 1'h1;
endcase
endcase
endcase
/* \nmigen.decoding = "GETTING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:167" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:127" *)
casez (f7_buf)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h30:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:129" */
7'h44:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" *)
casez (reg_44_valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:130" */
1'h1:
\read_strobe_44$next = 1'h1;
endcase
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_strobe_44$next = 1'h0;
endcase
end
assign clear_30 = 1'h0;
assign clear_44 = 1'h0;
assign clear_70 = 1'h0;
assign in1s = in1;
assign in0s = in0;
assign reg_70_invalidate = 1'h0;
assign sink_70__ready = reg_70_input__ready;
assign reg_70_input__payload = sink_70__payload;
assign reg_70_input__valid = sink_70__valid;
assign reg_44_invalidate = \$3 ;
assign sink_44__ready = reg_44_input__ready;
assign reg_44_input__payload = sink_44__payload;
assign reg_44_input__valid = sink_44__valid;
assign reg_30_invalidate = \$1 ;
assign sink_30__ready = reg_30_input__ready;
assign reg_30_input__payload = sink_30__payload;
assign reg_30_input__valid = sink_30__valid;
assign \$1 = read_strobe_30;
assign \$3 = read_strobe_44;
endmodule
(* \nmigen.hierarchy = "Cfu.input_flow_restrictor" *)
(* generator = "nMigen" *)
module input_flow_restrictor(input__payload, input__ready, release__payload, release__valid, output__valid, output__payload, output__ready, rst, clk, input__valid);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:61" *)
wire [32:0] \$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
wire \$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
wire \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:61" *)
wire [32:0] \$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input [127:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
output input__ready;
reg input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output [127:0] output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output output__valid;
reg output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
input [31:0] release__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
reg release__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:53" *)
input release__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:56" *)
reg [31:0] release_counter = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:56" *)
reg [31:0] \release_counter$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$10 = release_counter - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:61" *) 1'h1;
assign \$12 = release__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) release__ready;
assign \$14 = release_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *) 1'h0;
assign \$1 = release_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *) 1'h0;
assign \$3 = release_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *) 1'h0;
assign \$5 = release_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *) 1'h0;
assign \$7 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
release_counter <= \release_counter$next ;
always @* begin
if (\initial ) begin end
input__ready = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" */
1'h1:
input__ready = output__ready;
endcase
end
always @* begin
if (\initial ) begin end
output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" */
1'h1:
output__valid = input__valid;
endcase
end
always @* begin
if (\initial ) begin end
\release_counter$next = release_counter;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
casez (\$5 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:60" *)
casez (\$7 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:60" */
1'h1:
\release_counter$next = \$10 [31:0];
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:62" */
default:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:64" *)
casez (\$12 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:64" */
1'h1:
\release_counter$next = release__payload;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\release_counter$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
release__ready = 1'h0;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" *)
casez (\$14 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:57" */
1'h1:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/flow.py:62" */
default:
release__ready = 1'h1;
endcase
end
assign \$9 = \$10 ;
assign output__payload = input__payload;
endmodule
(* \nmigen.hierarchy = "Cfu.input_store" *)
(* generator = "nMigen" *)
module input_store(num_words_input__payload, num_words_input__ready, data_input__valid, data_input__payload, data_input__ready, data_output__valid, data_output__payload, data_output__ready, rst, clk, num_words_input__valid);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *)
wire \$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:70" *)
wire [9:0] \$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:70" *)
wire [9:0] \$13 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *)
wire \$15 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *)
wire \$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *)
wire \$19 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:86" *)
wire [8:0] \$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:86" *)
wire [8:0] \$22 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:86" *)
wire [8:0] \$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:86" *)
wire [9:0] \$25 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:86" *)
wire \$27 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *)
wire \$30 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$32 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *)
wire \$34 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$36 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$38 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *)
wire [9:0] \$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *)
wire \$42 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *)
wire \$44 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$46 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *)
wire \$48 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:68" *)
wire [8:0] \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *)
wire \$50 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$52 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *)
wire \$54 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *)
wire \$56 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *)
wire \$58 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:68" *)
wire [8:0] \$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *)
wire \$60 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *)
wire [9:0] \$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:52" *)
input [31:0] data_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:52" *)
output data_input__ready;
reg data_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:52" *)
input data_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:54" *)
output [127:0] data_output__payload;
reg [127:0] data_output__payload = 128'h00000000000000000000000000000000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:54" *)
reg [127:0] \data_output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:54" *)
input data_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:54" *)
output data_output__valid;
reg data_output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:54" *)
reg \data_output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
reg [1:0] fsm_state = 2'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
reg [1:0] \fsm_state$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:101" *)
reg [7:0] index = 8'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:101" *)
reg [7:0] \index$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:54" *)
reg [5:0] memory_read_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:55" *)
wire [127:0] memory_read_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:51" *)
reg [7:0] memory_write_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:52" *)
reg [31:0] memory_write_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:53" *)
reg memory_write_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:100" *)
reg [8:0] num_words = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:100" *)
reg [8:0] \num_words$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:53" *)
input [31:0] num_words_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:53" *)
output num_words_input__ready;
reg num_words_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:53" *)
input num_words_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:77" *)
reg read_port_valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:77" *)
reg \read_port_valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:78" *)
reg read_started = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:78" *)
reg \read_started$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:102" *)
wire reset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$10 = index == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *) \$8 ;
assign \$13 = num_words - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:70" *) 3'h4;
assign \$15 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *) read_port_valid;
assign \$17 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *) read_started;
assign \$1 = num_words_input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) num_words_input__ready;
assign \$19 = \$15 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *) \$17 ;
assign \$22 = index + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:86" *) 3'h4;
assign \$25 = num_words - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:86" *) 3'h4;
assign \$27 = index == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:86" *) \$25 ;
assign \$24 = \$27 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:86" *) 9'h000 : \$22 ;
assign \$30 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *) data_output__valid;
assign \$32 = data_output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_output__ready;
assign \$34 = \$30 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *) \$32 ;
assign \$36 = num_words_input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) num_words_input__ready;
assign \$38 = data_input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_input__ready;
assign \$3 = data_input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_input__ready;
assign \$40 = num_words - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *) 1'h1;
assign \$42 = index == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *) \$40 ;
assign \$44 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *) data_output__valid;
assign \$46 = data_output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_output__ready;
assign \$48 = \$44 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *) \$46 ;
assign \$50 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *) data_output__valid;
assign \$52 = data_output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) data_output__ready;
assign \$54 = \$50 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *) \$52 ;
assign \$56 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *) read_port_valid;
assign \$58 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *) read_started;
assign \$60 = \$56 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *) \$58 ;
assign \$6 = index + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:68" *) 1'h1;
assign \$8 = num_words - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *) 1'h1;
always @(posedge clk)
read_started <= \read_started$next ;
always @(posedge clk)
read_port_valid <= \read_port_valid$next ;
always @(posedge clk)
data_output__payload <= \data_output__payload$next ;
always @(posedge clk)
fsm_state <= \fsm_state$next ;
always @(posedge clk)
data_output__valid <= \data_output__valid$next ;
always @(posedge clk)
index <= \index$next ;
always @(posedge clk)
num_words <= \num_words$next ;
memory memory (
.clk(clk),
.read_addr(memory_read_addr),
.read_data(memory_read_data),
.write_addr(memory_write_addr),
.write_data(memory_write_data),
.write_enable(memory_write_enable)
);
always @* begin
if (\initial ) begin end
\num_words$next = num_words;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
\num_words$next = 9'h000;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:115" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:115" */
1'h1:
\num_words$next = num_words_input__payload[8:0];
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\num_words$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
memory_read_addr = 6'h00;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:122" */
2'h3:
memory_read_addr = index[7:2];
endcase
end
always @* begin
if (\initial ) begin end
\data_output__payload$next = data_output__payload;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:122" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *)
casez (\$48 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" */
1'h1:
\data_output__payload$next = memory_read_data;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\data_output__payload$next = 128'h00000000000000000000000000000000;
endcase
end
always @* begin
if (\initial ) begin end
\read_port_valid$next = read_port_valid;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:122" */
2'h3:
begin
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *)
casez (\$54 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" */
1'h1:
\read_port_valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:91" *)
casez (read_started)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:91" */
1'h1:
\read_port_valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:95" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:95" */
1'h1:
\read_port_valid$next = 1'h0;
endcase
end
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_port_valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\read_started$next = read_started;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:122" */
2'h3:
begin
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *)
casez (\$60 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" */
1'h1:
\read_started$next = 1'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:88" */
default:
\read_started$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:95" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:95" */
1'h1:
\read_started$next = 1'h0;
endcase
end
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_started$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\index$next = index;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
\index$next = 8'h00;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:67" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:67" */
1'h1:
begin
\index$next = \$6 [7:0];
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *)
casez (\$10 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" */
1'h1:
\index$next = \$13 [7:0];
endcase
end
endcase
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:122" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" *)
casez (\$19 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:85" */
1'h1:
\index$next = \$24 [7:0];
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\index$next = 8'h00;
endcase
end
always @* begin
if (\initial ) begin end
\data_output__valid$next = data_output__valid;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
\data_output__valid$next = 1'h0;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
/* empty */;
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:122" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" *)
casez (\$34 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:80" */
1'h1:
\data_output__valid$next = read_port_valid;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\data_output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\fsm_state$next = fsm_state;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
\fsm_state$next = 2'h1;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:115" *)
casez (\$36 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:115" */
1'h1:
\fsm_state$next = 2'h2;
endcase
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
begin
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:67" *)
casez (\$38 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:67" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" *)
casez (\$42 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:69" */
1'h1:
\fsm_state$next = 2'h3;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:120" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:120" */
1'h1:
\fsm_state$next = 2'h0;
endcase
end
/* \nmigen.decoding = "READING/3" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:122" */
2'h3:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:124" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:124" */
1'h1:
\fsm_state$next = 2'h0;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\fsm_state$next = 2'h0;
endcase
end
always @* begin
if (\initial ) begin end
num_words_input__ready = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
num_words_input__ready = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
memory_write_addr = 8'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
memory_write_addr = index;
endcase
end
always @* begin
if (\initial ) begin end
memory_write_data = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
memory_write_data = data_input__payload;
endcase
end
always @* begin
if (\initial ) begin end
memory_write_enable = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
memory_write_enable = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
data_input__ready = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:107" *)
casez (fsm_state)
/* \nmigen.decoding = "RESET/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:108" */
2'h0:
/* empty */;
/* \nmigen.decoding = "NUM_WORDS/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:113" */
2'h1:
/* empty */;
/* \nmigen.decoding = "WRITING/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/input_store.py:118" */
2'h2:
data_input__ready = 1'h1;
endcase
end
assign \$5 = \$6 ;
assign \$12 = \$13 ;
assign \$21 = \$24 ;
assign reset = num_words_input__valid;
endmodule
(* \nmigen.hierarchy = "Cfu.macc" *)
(* generator = "nMigen" *)
module macc(offset, operands__valid, operands__payload__inputs, operands__payload__filters, operands__ready, result__valid, result__payload, result__ready, rst, clk, enable);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:76" *)
wire \$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$101 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$104 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$105 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$107 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$108 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$111 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$114 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$115 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$117 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$118 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$121 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$124 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$125 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$127 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$128 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$131 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$134 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$135 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$137 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$138 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$141 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$144 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$145 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$147 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$148 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$15 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$151 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$154 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$155 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$157 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$158 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$161 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$164 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$165 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$167 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$168 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [31:0] \$170 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [17:0] \$171 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [17:0] \$173 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [18:0] \$175 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [17:0] \$177 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [17:0] \$179 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$18 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [18:0] \$181 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [19:0] \$183 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [17:0] \$185 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [17:0] \$187 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [18:0] \$189 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [17:0] \$191 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [17:0] \$193 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [18:0] \$195 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [19:0] \$197 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *)
wire [20:0] \$199 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:73" *)
wire \$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$25 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$27 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$28 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$31 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$34 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$35 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$37 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$38 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$4 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$41 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$44 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$45 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$47 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$48 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$51 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$54 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$55 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$57 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$58 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:77" *)
wire \$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$61 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$64 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$65 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$67 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$68 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$71 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$74 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$75 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$77 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$78 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:77" *)
wire \$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$81 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$84 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$85 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$87 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$88 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *)
wire [8:0] \$91 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$94 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *)
wire [9:0] \$95 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$97 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *)
wire [17:0] \$98 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:56" *)
input enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] f_tmp = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$100 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$100$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$110 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$110$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$120 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$120$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$130 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$130$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$140 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$140$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$150 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$150$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$160 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$160$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$20 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$20$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$30 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$30$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$40 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$40$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$50 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$50$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$60 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$60$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$70 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$70$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$80 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$80$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$90 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$90$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:96" *)
reg [8:0] \f_tmp$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] i_tmp = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$103 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$103$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$113 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$113$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$123 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$123$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$133 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$133$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$143 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$143$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$153 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$153$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$163 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$163$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$23 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$23$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$33 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$33$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$43 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$43$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$53 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$53$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$63 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$63$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$73 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$73$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$83 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$83$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$93 = 9'h000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$93$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:98" *)
reg [8:0] \i_tmp$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:69" *)
reg next_valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:69" *)
reg \next_valid$1 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:69" *)
reg \next_valid$1$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:69" *)
reg \next_valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:57" *)
input [8:0] offset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:58" *)
input [127:0] operands__payload__filters;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:58" *)
input [127:0] operands__payload__inputs;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:58" *)
output operands__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:58" *)
input operands__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:64" *)
wire pipe_flowing;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_01;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_02;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_03;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_04;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_05;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_06;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_07;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_08;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_09;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_0a;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_0b;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_0c;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_0d;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_0e;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:90" *)
reg [16:0] product_0f;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:60" *)
output [31:0] result__payload;
reg [31:0] result__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:60" *)
reg [31:0] \result__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:60" *)
input result__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:60" *)
output result__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$101 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[79:72]);
assign \$105 = $signed(operands__payload__inputs[79:72]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$108 = $signed(\i_tmp$103 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$100 );
assign \$10 = enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:76" *) \$8 ;
assign \$111 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[87:80]);
assign \$115 = $signed(operands__payload__inputs[87:80]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$118 = $signed(\i_tmp$113 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$110 );
assign \$121 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[95:88]);
assign \$125 = $signed(operands__payload__inputs[95:88]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$128 = $signed(\i_tmp$123 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$120 );
assign \$12 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[7:0]);
assign \$131 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[103:96]);
assign \$135 = $signed(operands__payload__inputs[103:96]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$138 = $signed(\i_tmp$133 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$130 );
assign \$141 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[111:104]);
assign \$145 = $signed(operands__payload__inputs[111:104]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$148 = $signed(\i_tmp$143 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$140 );
assign \$151 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[119:112]);
assign \$155 = $signed(operands__payload__inputs[119:112]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$158 = $signed(\i_tmp$153 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$150 );
assign \$15 = $signed(operands__payload__inputs[7:0]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$161 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[127:120]);
assign \$165 = $signed(operands__payload__inputs[127:120]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$168 = $signed(\i_tmp$163 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$160 );
assign \$171 = $signed(product_00) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(product_01);
assign \$173 = $signed(product_02) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(product_03);
assign \$175 = $signed(\$171 ) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(\$173 );
assign \$177 = $signed(product_04) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(product_05);
assign \$179 = $signed(product_06) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(product_07);
assign \$181 = $signed(\$177 ) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(\$179 );
assign \$183 = $signed(\$175 ) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(\$181 );
assign \$185 = $signed(product_08) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(product_09);
assign \$187 = $signed(product_0a) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(product_0b);
assign \$18 = $signed(i_tmp) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(f_tmp);
assign \$189 = $signed(\$185 ) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(\$187 );
assign \$191 = $signed(product_0c) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(product_0d);
assign \$193 = $signed(product_0e) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(product_0f);
assign \$195 = $signed(\$191 ) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(\$193 );
assign \$197 = $signed(\$189 ) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(\$195 );
assign \$199 = $signed(\$183 ) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(\$197 );
assign \$170 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/util.py:44" *) $signed(\$199 );
assign \$21 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[15:8]);
assign \$25 = $signed(operands__payload__inputs[15:8]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$28 = $signed(\i_tmp$23 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$20 );
assign \$2 = enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:73" *) \next_valid$1 ;
assign \$31 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[23:16]);
assign \$35 = $signed(operands__payload__inputs[23:16]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$38 = $signed(\i_tmp$33 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$30 );
assign \$41 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[31:24]);
assign \$45 = $signed(operands__payload__inputs[31:24]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$48 = $signed(\i_tmp$43 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$40 );
assign \$4 = result__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) result__ready;
assign \$51 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[39:32]);
assign \$55 = $signed(operands__payload__inputs[39:32]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$58 = $signed(\i_tmp$53 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$50 );
assign \$61 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[47:40]);
assign \$65 = $signed(operands__payload__inputs[47:40]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$68 = $signed(\i_tmp$63 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$60 );
assign \$6 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:77" *) \next_valid$1 ;
assign \$71 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[55:48]);
assign \$75 = $signed(operands__payload__inputs[55:48]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$78 = $signed(\i_tmp$73 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$70 );
assign \$81 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[63:56]);
assign \$85 = $signed(operands__payload__inputs[63:56]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$88 = $signed(\i_tmp$83 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$80 );
assign \$8 = \$4 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:77" *) \$6 ;
assign \$91 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:85" *) $signed(operands__payload__filters[71:64]);
assign \$95 = $signed(operands__payload__inputs[71:64]) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:99" *) $signed(offset);
assign \$98 = $signed(\i_tmp$93 ) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:101" *) $signed(\f_tmp$90 );
always @(posedge clk)
result__payload <= \result__payload$next ;
always @(posedge clk)
\i_tmp$163 <= \i_tmp$163$next ;
always @(posedge clk)
\f_tmp$160 <= \f_tmp$160$next ;
always @(posedge clk)
\i_tmp$153 <= \i_tmp$153$next ;
always @(posedge clk)
\f_tmp$150 <= \f_tmp$150$next ;
always @(posedge clk)
\i_tmp$143 <= \i_tmp$143$next ;
always @(posedge clk)
\f_tmp$140 <= \f_tmp$140$next ;
always @(posedge clk)
\i_tmp$133 <= \i_tmp$133$next ;
always @(posedge clk)
\f_tmp$130 <= \f_tmp$130$next ;
always @(posedge clk)
\i_tmp$123 <= \i_tmp$123$next ;
always @(posedge clk)
\f_tmp$120 <= \f_tmp$120$next ;
always @(posedge clk)
\i_tmp$113 <= \i_tmp$113$next ;
always @(posedge clk)
\f_tmp$110 <= \f_tmp$110$next ;
always @(posedge clk)
\i_tmp$103 <= \i_tmp$103$next ;
always @(posedge clk)
\f_tmp$100 <= \f_tmp$100$next ;
always @(posedge clk)
\i_tmp$93 <= \i_tmp$93$next ;
always @(posedge clk)
\f_tmp$90 <= \f_tmp$90$next ;
always @(posedge clk)
\i_tmp$83 <= \i_tmp$83$next ;
always @(posedge clk)
\f_tmp$80 <= \f_tmp$80$next ;
always @(posedge clk)
\i_tmp$73 <= \i_tmp$73$next ;
always @(posedge clk)
\f_tmp$70 <= \f_tmp$70$next ;
always @(posedge clk)
\i_tmp$63 <= \i_tmp$63$next ;
always @(posedge clk)
\f_tmp$60 <= \f_tmp$60$next ;
always @(posedge clk)
\i_tmp$53 <= \i_tmp$53$next ;
always @(posedge clk)
\f_tmp$50 <= \f_tmp$50$next ;
always @(posedge clk)
\i_tmp$43 <= \i_tmp$43$next ;
always @(posedge clk)
\f_tmp$40 <= \f_tmp$40$next ;
always @(posedge clk)
\i_tmp$33 <= \i_tmp$33$next ;
always @(posedge clk)
\f_tmp$30 <= \f_tmp$30$next ;
always @(posedge clk)
\i_tmp$23 <= \i_tmp$23$next ;
always @(posedge clk)
\f_tmp$20 <= \f_tmp$20$next ;
always @(posedge clk)
i_tmp <= \i_tmp$next ;
always @(posedge clk)
f_tmp <= \f_tmp$next ;
always @(posedge clk)
\next_valid$1 <= \next_valid$1$next ;
always @(posedge clk)
next_valid <= \next_valid$next ;
always @* begin
if (\initial ) begin end
\next_valid$next = next_valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:70" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:70" */
1'h1:
\next_valid$next = operands__valid;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\next_valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\next_valid$1$next = \next_valid$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:70" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:70" */
1'h1:
\next_valid$1$next = next_valid;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\next_valid$1$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
product_01 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_01 = \$28 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$30$next = \f_tmp$30 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$30$next = \$31 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$30$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$33$next = \i_tmp$33 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$33$next = \$35 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$33$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_02 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_02 = \$38 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$40$next = \f_tmp$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$40$next = \$41 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$40$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$43$next = \i_tmp$43 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$43$next = \$45 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$43$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_03 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_03 = \$48 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$50$next = \f_tmp$50 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$50$next = \$51 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$50$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$53$next = \i_tmp$53 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$53$next = \$55 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$53$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_04 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_04 = \$58 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$60$next = \f_tmp$60 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$60$next = \$61 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$60$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$63$next = \i_tmp$63 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$63$next = \$65 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$63$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_05 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_05 = \$68 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$70$next = \f_tmp$70 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$70$next = \$71 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$70$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$73$next = \i_tmp$73 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$73$next = \$75 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$73$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_06 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_06 = \$78 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$80$next = \f_tmp$80 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$80$next = \$81 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$80$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$83$next = \i_tmp$83 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$83$next = \$85 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$83$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_07 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_07 = \$88 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$90$next = \f_tmp$90 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$90$next = \$91 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$90$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$93$next = \i_tmp$93 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$93$next = \$95 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$93$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_08 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_08 = \$98 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$100$next = \f_tmp$100 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$100$next = \$101 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$100$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$103$next = \i_tmp$103 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$103$next = \$105 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$103$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_09 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_09 = \$108 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$110$next = \f_tmp$110 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$110$next = \$111 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$110$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$113$next = \i_tmp$113 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$113$next = \$115 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$113$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_0a = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_0a = \$118 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$120$next = \f_tmp$120 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$120$next = \$121 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$120$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$123$next = \i_tmp$123 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$123$next = \$125 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$123$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_0b = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_0b = \$128 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$130$next = \f_tmp$130 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$130$next = \$131 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$130$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$133$next = \i_tmp$133 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$133$next = \$135 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$133$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_0c = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_0c = \$138 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$140$next = \f_tmp$140 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$140$next = \$141 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$140$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$143$next = \i_tmp$143 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$143$next = \$145 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$143$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_0d = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_0d = \$148 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$150$next = \f_tmp$150 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$150$next = \$151 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$150$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$153$next = \i_tmp$153 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$153$next = \$155 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$153$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_0e = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_0e = \$158 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$next = f_tmp;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$next = \$12 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$160$next = \f_tmp$160 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$160$next = \$161 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$160$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$163$next = \i_tmp$163 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$163$next = \$165 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$163$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_0f = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_0f = \$168 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\result__payload$next = result__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\result__payload$next = \$170 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\result__payload$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$next = i_tmp;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$next = \$15 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
product_00 = 17'h00000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
product_00 = \$18 [16:0];
endcase
end
always @* begin
if (\initial ) begin end
\f_tmp$20$next = \f_tmp$20 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\f_tmp$20$next = \$21 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\f_tmp$20$next = 9'h000;
endcase
end
always @* begin
if (\initial ) begin end
\i_tmp$23$next = \i_tmp$23 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" *)
casez (pipe_flowing)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/macc.py:94" */
1'h1:
\i_tmp$23$next = \$25 [8:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\i_tmp$23$next = 9'h000;
endcase
end
assign \$14 = \$15 ;
assign \$17 = \$18 ;
assign \$24 = \$25 ;
assign \$27 = \$28 ;
assign \$34 = \$35 ;
assign \$37 = \$38 ;
assign \$44 = \$45 ;
assign \$47 = \$48 ;
assign \$54 = \$55 ;
assign \$57 = \$58 ;
assign \$64 = \$65 ;
assign \$67 = \$68 ;
assign \$74 = \$75 ;
assign \$77 = \$78 ;
assign \$84 = \$85 ;
assign \$87 = \$88 ;
assign \$94 = \$95 ;
assign \$97 = \$98 ;
assign \$104 = \$105 ;
assign \$107 = \$108 ;
assign \$114 = \$115 ;
assign \$117 = \$118 ;
assign \$124 = \$125 ;
assign \$127 = \$128 ;
assign \$134 = \$135 ;
assign \$137 = \$138 ;
assign \$144 = \$145 ;
assign \$147 = \$148 ;
assign \$154 = \$155 ;
assign \$157 = \$158 ;
assign \$164 = \$165 ;
assign \$167 = \$168 ;
assign operands__ready = pipe_flowing;
assign pipe_flowing = \$10 ;
assign result__valid = \$2 ;
endmodule
(* \nmigen.hierarchy = "Cfu.input_store.memory" *)
(* generator = "nMigen" *)
module memory(write_addr, write_data, write_enable, read_addr, read_data, clk);
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *)
wire \$26 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *)
wire \$28 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *)
wire \$30 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *)
wire \$32 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *)
wire \$34 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *)
wire \$36 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *)
wire \$38 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *)
wire \$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *)
wire \$42 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *)
wire \$44 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *)
wire \$46 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *)
wire \$48 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [5:0] mem_r_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [5:0] \mem_r_addr$13 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [5:0] \mem_r_addr$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [5:0] \mem_r_addr$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [31:0] mem_r_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [31:0] \mem_r_data$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [31:0] \mem_r_data$22 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [31:0] \mem_r_data$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire mem_r_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire \mem_r_en$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire \mem_r_en$20 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire \mem_r_en$4 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [5:0] mem_w_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [5:0] \mem_w_addr$16 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [5:0] \mem_w_addr$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [5:0] \mem_w_addr$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [31:0] mem_w_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [31:0] \mem_w_data$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [31:0] \mem_w_data$25 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [31:0] \mem_w_data$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire mem_w_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire \mem_w_en$15 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire \mem_w_en$23 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire \mem_w_en$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:54" *)
input [5:0] read_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:55" *)
output [127:0] read_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:51" *)
input [7:0] write_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:52" *)
input [31:0] write_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:53" *)
input write_enable;
reg [31:0] mem [63:0];
initial begin
mem[0] = 32'd0;
mem[1] = 32'd0;
mem[2] = 32'd0;
mem[3] = 32'd0;
mem[4] = 32'd0;
mem[5] = 32'd0;
mem[6] = 32'd0;
mem[7] = 32'd0;
mem[8] = 32'd0;
mem[9] = 32'd0;
mem[10] = 32'd0;
mem[11] = 32'd0;
mem[12] = 32'd0;
mem[13] = 32'd0;
mem[14] = 32'd0;
mem[15] = 32'd0;
mem[16] = 32'd0;
mem[17] = 32'd0;
mem[18] = 32'd0;
mem[19] = 32'd0;
mem[20] = 32'd0;
mem[21] = 32'd0;
mem[22] = 32'd0;
mem[23] = 32'd0;
mem[24] = 32'd0;
mem[25] = 32'd0;
mem[26] = 32'd0;
mem[27] = 32'd0;
mem[28] = 32'd0;
mem[29] = 32'd0;
mem[30] = 32'd0;
mem[31] = 32'd0;
mem[32] = 32'd0;
mem[33] = 32'd0;
mem[34] = 32'd0;
mem[35] = 32'd0;
mem[36] = 32'd0;
mem[37] = 32'd0;
mem[38] = 32'd0;
mem[39] = 32'd0;
mem[40] = 32'd0;
mem[41] = 32'd0;
mem[42] = 32'd0;
mem[43] = 32'd0;
mem[44] = 32'd0;
mem[45] = 32'd0;
mem[46] = 32'd0;
mem[47] = 32'd0;
mem[48] = 32'd0;
mem[49] = 32'd0;
mem[50] = 32'd0;
mem[51] = 32'd0;
mem[52] = 32'd0;
mem[53] = 32'd0;
mem[54] = 32'd0;
mem[55] = 32'd0;
mem[56] = 32'd0;
mem[57] = 32'd0;
mem[58] = 32'd0;
mem[59] = 32'd0;
mem[60] = 32'd0;
mem[61] = 32'd0;
mem[62] = 32'd0;
mem[63] = 32'd0;
end
always @(posedge clk) begin
if (mem_w_en)
mem[mem_w_addr] <= mem_w_data;
end
reg [31:0] _0_;
always @(posedge clk) begin
if (mem_r_en) begin
_0_ <= mem[mem_r_addr];
end
end
assign mem_r_data = _0_;
reg [31:0] \mem$10 [63:0];
initial begin
\mem$10 [0] = 32'd0;
\mem$10 [1] = 32'd0;
\mem$10 [2] = 32'd0;
\mem$10 [3] = 32'd0;
\mem$10 [4] = 32'd0;
\mem$10 [5] = 32'd0;
\mem$10 [6] = 32'd0;
\mem$10 [7] = 32'd0;
\mem$10 [8] = 32'd0;
\mem$10 [9] = 32'd0;
\mem$10 [10] = 32'd0;
\mem$10 [11] = 32'd0;
\mem$10 [12] = 32'd0;
\mem$10 [13] = 32'd0;
\mem$10 [14] = 32'd0;
\mem$10 [15] = 32'd0;
\mem$10 [16] = 32'd0;
\mem$10 [17] = 32'd0;
\mem$10 [18] = 32'd0;
\mem$10 [19] = 32'd0;
\mem$10 [20] = 32'd0;
\mem$10 [21] = 32'd0;
\mem$10 [22] = 32'd0;
\mem$10 [23] = 32'd0;
\mem$10 [24] = 32'd0;
\mem$10 [25] = 32'd0;
\mem$10 [26] = 32'd0;
\mem$10 [27] = 32'd0;
\mem$10 [28] = 32'd0;
\mem$10 [29] = 32'd0;
\mem$10 [30] = 32'd0;
\mem$10 [31] = 32'd0;
\mem$10 [32] = 32'd0;
\mem$10 [33] = 32'd0;
\mem$10 [34] = 32'd0;
\mem$10 [35] = 32'd0;
\mem$10 [36] = 32'd0;
\mem$10 [37] = 32'd0;
\mem$10 [38] = 32'd0;
\mem$10 [39] = 32'd0;
\mem$10 [40] = 32'd0;
\mem$10 [41] = 32'd0;
\mem$10 [42] = 32'd0;
\mem$10 [43] = 32'd0;
\mem$10 [44] = 32'd0;
\mem$10 [45] = 32'd0;
\mem$10 [46] = 32'd0;
\mem$10 [47] = 32'd0;
\mem$10 [48] = 32'd0;
\mem$10 [49] = 32'd0;
\mem$10 [50] = 32'd0;
\mem$10 [51] = 32'd0;
\mem$10 [52] = 32'd0;
\mem$10 [53] = 32'd0;
\mem$10 [54] = 32'd0;
\mem$10 [55] = 32'd0;
\mem$10 [56] = 32'd0;
\mem$10 [57] = 32'd0;
\mem$10 [58] = 32'd0;
\mem$10 [59] = 32'd0;
\mem$10 [60] = 32'd0;
\mem$10 [61] = 32'd0;
\mem$10 [62] = 32'd0;
\mem$10 [63] = 32'd0;
end
always @(posedge clk) begin
if (\mem_w_en$15 )
\mem$10 [\mem_w_addr$16 ] <= \mem_w_data$17 ;
end
reg [31:0] _1_;
always @(posedge clk) begin
if (\mem_r_en$12 ) begin
_1_ <= \mem$10 [\mem_r_addr$13 ];
end
end
assign \mem_r_data$14 = _1_;
reg [31:0] \mem$18 [63:0];
initial begin
\mem$18 [0] = 32'd0;
\mem$18 [1] = 32'd0;
\mem$18 [2] = 32'd0;
\mem$18 [3] = 32'd0;
\mem$18 [4] = 32'd0;
\mem$18 [5] = 32'd0;
\mem$18 [6] = 32'd0;
\mem$18 [7] = 32'd0;
\mem$18 [8] = 32'd0;
\mem$18 [9] = 32'd0;
\mem$18 [10] = 32'd0;
\mem$18 [11] = 32'd0;
\mem$18 [12] = 32'd0;
\mem$18 [13] = 32'd0;
\mem$18 [14] = 32'd0;
\mem$18 [15] = 32'd0;
\mem$18 [16] = 32'd0;
\mem$18 [17] = 32'd0;
\mem$18 [18] = 32'd0;
\mem$18 [19] = 32'd0;
\mem$18 [20] = 32'd0;
\mem$18 [21] = 32'd0;
\mem$18 [22] = 32'd0;
\mem$18 [23] = 32'd0;
\mem$18 [24] = 32'd0;
\mem$18 [25] = 32'd0;
\mem$18 [26] = 32'd0;
\mem$18 [27] = 32'd0;
\mem$18 [28] = 32'd0;
\mem$18 [29] = 32'd0;
\mem$18 [30] = 32'd0;
\mem$18 [31] = 32'd0;
\mem$18 [32] = 32'd0;
\mem$18 [33] = 32'd0;
\mem$18 [34] = 32'd0;
\mem$18 [35] = 32'd0;
\mem$18 [36] = 32'd0;
\mem$18 [37] = 32'd0;
\mem$18 [38] = 32'd0;
\mem$18 [39] = 32'd0;
\mem$18 [40] = 32'd0;
\mem$18 [41] = 32'd0;
\mem$18 [42] = 32'd0;
\mem$18 [43] = 32'd0;
\mem$18 [44] = 32'd0;
\mem$18 [45] = 32'd0;
\mem$18 [46] = 32'd0;
\mem$18 [47] = 32'd0;
\mem$18 [48] = 32'd0;
\mem$18 [49] = 32'd0;
\mem$18 [50] = 32'd0;
\mem$18 [51] = 32'd0;
\mem$18 [52] = 32'd0;
\mem$18 [53] = 32'd0;
\mem$18 [54] = 32'd0;
\mem$18 [55] = 32'd0;
\mem$18 [56] = 32'd0;
\mem$18 [57] = 32'd0;
\mem$18 [58] = 32'd0;
\mem$18 [59] = 32'd0;
\mem$18 [60] = 32'd0;
\mem$18 [61] = 32'd0;
\mem$18 [62] = 32'd0;
\mem$18 [63] = 32'd0;
end
always @(posedge clk) begin
if (\mem_w_en$23 )
\mem$18 [\mem_w_addr$24 ] <= \mem_w_data$25 ;
end
reg [31:0] _2_;
always @(posedge clk) begin
if (\mem_r_en$20 ) begin
_2_ <= \mem$18 [\mem_r_addr$21 ];
end
end
assign \mem_r_data$22 = _2_;
reg [31:0] \mem$2 [63:0];
initial begin
\mem$2 [0] = 32'd0;
\mem$2 [1] = 32'd0;
\mem$2 [2] = 32'd0;
\mem$2 [3] = 32'd0;
\mem$2 [4] = 32'd0;
\mem$2 [5] = 32'd0;
\mem$2 [6] = 32'd0;
\mem$2 [7] = 32'd0;
\mem$2 [8] = 32'd0;
\mem$2 [9] = 32'd0;
\mem$2 [10] = 32'd0;
\mem$2 [11] = 32'd0;
\mem$2 [12] = 32'd0;
\mem$2 [13] = 32'd0;
\mem$2 [14] = 32'd0;
\mem$2 [15] = 32'd0;
\mem$2 [16] = 32'd0;
\mem$2 [17] = 32'd0;
\mem$2 [18] = 32'd0;
\mem$2 [19] = 32'd0;
\mem$2 [20] = 32'd0;
\mem$2 [21] = 32'd0;
\mem$2 [22] = 32'd0;
\mem$2 [23] = 32'd0;
\mem$2 [24] = 32'd0;
\mem$2 [25] = 32'd0;
\mem$2 [26] = 32'd0;
\mem$2 [27] = 32'd0;
\mem$2 [28] = 32'd0;
\mem$2 [29] = 32'd0;
\mem$2 [30] = 32'd0;
\mem$2 [31] = 32'd0;
\mem$2 [32] = 32'd0;
\mem$2 [33] = 32'd0;
\mem$2 [34] = 32'd0;
\mem$2 [35] = 32'd0;
\mem$2 [36] = 32'd0;
\mem$2 [37] = 32'd0;
\mem$2 [38] = 32'd0;
\mem$2 [39] = 32'd0;
\mem$2 [40] = 32'd0;
\mem$2 [41] = 32'd0;
\mem$2 [42] = 32'd0;
\mem$2 [43] = 32'd0;
\mem$2 [44] = 32'd0;
\mem$2 [45] = 32'd0;
\mem$2 [46] = 32'd0;
\mem$2 [47] = 32'd0;
\mem$2 [48] = 32'd0;
\mem$2 [49] = 32'd0;
\mem$2 [50] = 32'd0;
\mem$2 [51] = 32'd0;
\mem$2 [52] = 32'd0;
\mem$2 [53] = 32'd0;
\mem$2 [54] = 32'd0;
\mem$2 [55] = 32'd0;
\mem$2 [56] = 32'd0;
\mem$2 [57] = 32'd0;
\mem$2 [58] = 32'd0;
\mem$2 [59] = 32'd0;
\mem$2 [60] = 32'd0;
\mem$2 [61] = 32'd0;
\mem$2 [62] = 32'd0;
\mem$2 [63] = 32'd0;
end
always @(posedge clk) begin
if (\mem_w_en$7 )
\mem$2 [\mem_w_addr$8 ] <= \mem_w_data$9 ;
end
reg [31:0] _3_;
always @(posedge clk) begin
if (\mem_r_en$4 ) begin
_3_ <= \mem$2 [\mem_r_addr$5 ];
end
end
assign \mem_r_data$6 = _3_;
assign \$26 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *) write_enable;
assign \$28 = ! (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *) write_addr[1:0];
assign \$30 = write_enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *) \$28 ;
assign \$32 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *) write_enable;
assign \$34 = write_addr[1:0] == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *) 1'h1;
assign \$36 = write_enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *) \$34 ;
assign \$38 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *) write_enable;
assign \$40 = write_addr[1:0] == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *) 2'h2;
assign \$42 = write_enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *) \$40 ;
assign \$44 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *) write_enable;
assign \$46 = write_addr[1:0] == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *) 2'h3;
assign \$48 = write_enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *) \$46 ;
assign read_data = { \mem_r_data$22 , \mem_r_data$14 , \mem_r_data$6 , mem_r_data };
assign \mem_w_en$23 = \$48 ;
assign \mem_w_data$25 = write_data;
assign \mem_w_addr$24 = write_addr[7:2];
assign \mem_r_en$20 = \$44 ;
assign \mem_r_addr$21 = read_addr;
assign \mem_w_en$15 = \$42 ;
assign \mem_w_data$17 = write_data;
assign \mem_w_addr$16 = write_addr[7:2];
assign \mem_r_en$12 = \$38 ;
assign \mem_r_addr$13 = read_addr;
assign \mem_w_en$7 = \$36 ;
assign \mem_w_data$9 = write_data;
assign \mem_w_addr$8 = write_addr[7:2];
assign \mem_r_en$4 = \$32 ;
assign \mem_r_addr$5 = read_addr;
assign mem_w_en = \$30 ;
assign mem_w_data = write_data;
assign mem_w_addr = write_addr[7:2];
assign mem_r_en = \$26 ;
assign mem_r_addr = read_addr;
endmodule
(* \nmigen.hierarchy = "Cfu.filter_store.memory" *)
(* generator = "nMigen" *)
module \memory$2 (write_addr, write_data, write_enable, read_addr, read_data, clk);
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *)
wire \$26 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *)
wire \$28 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *)
wire \$30 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *)
wire \$32 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *)
wire \$34 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *)
wire \$36 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *)
wire \$38 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *)
wire \$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *)
wire \$42 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *)
wire \$44 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *)
wire \$46 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *)
wire \$48 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [8:0] mem_r_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [8:0] \mem_r_addr$13 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [8:0] \mem_r_addr$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [8:0] \mem_r_addr$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [31:0] mem_r_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [31:0] \mem_r_data$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [31:0] \mem_r_data$22 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire [31:0] \mem_r_data$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire mem_r_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire \mem_r_en$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire \mem_r_en$20 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:62" *)
wire \mem_r_en$4 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [8:0] mem_w_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [8:0] \mem_w_addr$16 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [8:0] \mem_w_addr$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [8:0] \mem_w_addr$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [31:0] mem_w_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [31:0] \mem_w_data$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [31:0] \mem_w_data$25 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire [31:0] \mem_w_data$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire mem_w_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire \mem_w_en$15 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire \mem_w_en$23 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:68" *)
wire \mem_w_en$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:54" *)
input [8:0] read_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:55" *)
output [127:0] read_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:51" *)
input [10:0] write_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:52" *)
input [31:0] write_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:53" *)
input write_enable;
reg [31:0] mem [511:0];
initial begin
mem[0] = 32'd0;
mem[1] = 32'd0;
mem[2] = 32'd0;
mem[3] = 32'd0;
mem[4] = 32'd0;
mem[5] = 32'd0;
mem[6] = 32'd0;
mem[7] = 32'd0;
mem[8] = 32'd0;
mem[9] = 32'd0;
mem[10] = 32'd0;
mem[11] = 32'd0;
mem[12] = 32'd0;
mem[13] = 32'd0;
mem[14] = 32'd0;
mem[15] = 32'd0;
mem[16] = 32'd0;
mem[17] = 32'd0;
mem[18] = 32'd0;
mem[19] = 32'd0;
mem[20] = 32'd0;
mem[21] = 32'd0;
mem[22] = 32'd0;
mem[23] = 32'd0;
mem[24] = 32'd0;
mem[25] = 32'd0;
mem[26] = 32'd0;
mem[27] = 32'd0;
mem[28] = 32'd0;
mem[29] = 32'd0;
mem[30] = 32'd0;
mem[31] = 32'd0;
mem[32] = 32'd0;
mem[33] = 32'd0;
mem[34] = 32'd0;
mem[35] = 32'd0;
mem[36] = 32'd0;
mem[37] = 32'd0;
mem[38] = 32'd0;
mem[39] = 32'd0;
mem[40] = 32'd0;
mem[41] = 32'd0;
mem[42] = 32'd0;
mem[43] = 32'd0;
mem[44] = 32'd0;
mem[45] = 32'd0;
mem[46] = 32'd0;
mem[47] = 32'd0;
mem[48] = 32'd0;
mem[49] = 32'd0;
mem[50] = 32'd0;
mem[51] = 32'd0;
mem[52] = 32'd0;
mem[53] = 32'd0;
mem[54] = 32'd0;
mem[55] = 32'd0;
mem[56] = 32'd0;
mem[57] = 32'd0;
mem[58] = 32'd0;
mem[59] = 32'd0;
mem[60] = 32'd0;
mem[61] = 32'd0;
mem[62] = 32'd0;
mem[63] = 32'd0;
mem[64] = 32'd0;
mem[65] = 32'd0;
mem[66] = 32'd0;
mem[67] = 32'd0;
mem[68] = 32'd0;
mem[69] = 32'd0;
mem[70] = 32'd0;
mem[71] = 32'd0;
mem[72] = 32'd0;
mem[73] = 32'd0;
mem[74] = 32'd0;
mem[75] = 32'd0;
mem[76] = 32'd0;
mem[77] = 32'd0;
mem[78] = 32'd0;
mem[79] = 32'd0;
mem[80] = 32'd0;
mem[81] = 32'd0;
mem[82] = 32'd0;
mem[83] = 32'd0;
mem[84] = 32'd0;
mem[85] = 32'd0;
mem[86] = 32'd0;
mem[87] = 32'd0;
mem[88] = 32'd0;
mem[89] = 32'd0;
mem[90] = 32'd0;
mem[91] = 32'd0;
mem[92] = 32'd0;
mem[93] = 32'd0;
mem[94] = 32'd0;
mem[95] = 32'd0;
mem[96] = 32'd0;
mem[97] = 32'd0;
mem[98] = 32'd0;
mem[99] = 32'd0;
mem[100] = 32'd0;
mem[101] = 32'd0;
mem[102] = 32'd0;
mem[103] = 32'd0;
mem[104] = 32'd0;
mem[105] = 32'd0;
mem[106] = 32'd0;
mem[107] = 32'd0;
mem[108] = 32'd0;
mem[109] = 32'd0;
mem[110] = 32'd0;
mem[111] = 32'd0;
mem[112] = 32'd0;
mem[113] = 32'd0;
mem[114] = 32'd0;
mem[115] = 32'd0;
mem[116] = 32'd0;
mem[117] = 32'd0;
mem[118] = 32'd0;
mem[119] = 32'd0;
mem[120] = 32'd0;
mem[121] = 32'd0;
mem[122] = 32'd0;
mem[123] = 32'd0;
mem[124] = 32'd0;
mem[125] = 32'd0;
mem[126] = 32'd0;
mem[127] = 32'd0;
mem[128] = 32'd0;
mem[129] = 32'd0;
mem[130] = 32'd0;
mem[131] = 32'd0;
mem[132] = 32'd0;
mem[133] = 32'd0;
mem[134] = 32'd0;
mem[135] = 32'd0;
mem[136] = 32'd0;
mem[137] = 32'd0;
mem[138] = 32'd0;
mem[139] = 32'd0;
mem[140] = 32'd0;
mem[141] = 32'd0;
mem[142] = 32'd0;
mem[143] = 32'd0;
mem[144] = 32'd0;
mem[145] = 32'd0;
mem[146] = 32'd0;
mem[147] = 32'd0;
mem[148] = 32'd0;
mem[149] = 32'd0;
mem[150] = 32'd0;
mem[151] = 32'd0;
mem[152] = 32'd0;
mem[153] = 32'd0;
mem[154] = 32'd0;
mem[155] = 32'd0;
mem[156] = 32'd0;
mem[157] = 32'd0;
mem[158] = 32'd0;
mem[159] = 32'd0;
mem[160] = 32'd0;
mem[161] = 32'd0;
mem[162] = 32'd0;
mem[163] = 32'd0;
mem[164] = 32'd0;
mem[165] = 32'd0;
mem[166] = 32'd0;
mem[167] = 32'd0;
mem[168] = 32'd0;
mem[169] = 32'd0;
mem[170] = 32'd0;
mem[171] = 32'd0;
mem[172] = 32'd0;
mem[173] = 32'd0;
mem[174] = 32'd0;
mem[175] = 32'd0;
mem[176] = 32'd0;
mem[177] = 32'd0;
mem[178] = 32'd0;
mem[179] = 32'd0;
mem[180] = 32'd0;
mem[181] = 32'd0;
mem[182] = 32'd0;
mem[183] = 32'd0;
mem[184] = 32'd0;
mem[185] = 32'd0;
mem[186] = 32'd0;
mem[187] = 32'd0;
mem[188] = 32'd0;
mem[189] = 32'd0;
mem[190] = 32'd0;
mem[191] = 32'd0;
mem[192] = 32'd0;
mem[193] = 32'd0;
mem[194] = 32'd0;
mem[195] = 32'd0;
mem[196] = 32'd0;
mem[197] = 32'd0;
mem[198] = 32'd0;
mem[199] = 32'd0;
mem[200] = 32'd0;
mem[201] = 32'd0;
mem[202] = 32'd0;
mem[203] = 32'd0;
mem[204] = 32'd0;
mem[205] = 32'd0;
mem[206] = 32'd0;
mem[207] = 32'd0;
mem[208] = 32'd0;
mem[209] = 32'd0;
mem[210] = 32'd0;
mem[211] = 32'd0;
mem[212] = 32'd0;
mem[213] = 32'd0;
mem[214] = 32'd0;
mem[215] = 32'd0;
mem[216] = 32'd0;
mem[217] = 32'd0;
mem[218] = 32'd0;
mem[219] = 32'd0;
mem[220] = 32'd0;
mem[221] = 32'd0;
mem[222] = 32'd0;
mem[223] = 32'd0;
mem[224] = 32'd0;
mem[225] = 32'd0;
mem[226] = 32'd0;
mem[227] = 32'd0;
mem[228] = 32'd0;
mem[229] = 32'd0;
mem[230] = 32'd0;
mem[231] = 32'd0;
mem[232] = 32'd0;
mem[233] = 32'd0;
mem[234] = 32'd0;
mem[235] = 32'd0;
mem[236] = 32'd0;
mem[237] = 32'd0;
mem[238] = 32'd0;
mem[239] = 32'd0;
mem[240] = 32'd0;
mem[241] = 32'd0;
mem[242] = 32'd0;
mem[243] = 32'd0;
mem[244] = 32'd0;
mem[245] = 32'd0;
mem[246] = 32'd0;
mem[247] = 32'd0;
mem[248] = 32'd0;
mem[249] = 32'd0;
mem[250] = 32'd0;
mem[251] = 32'd0;
mem[252] = 32'd0;
mem[253] = 32'd0;
mem[254] = 32'd0;
mem[255] = 32'd0;
mem[256] = 32'd0;
mem[257] = 32'd0;
mem[258] = 32'd0;
mem[259] = 32'd0;
mem[260] = 32'd0;
mem[261] = 32'd0;
mem[262] = 32'd0;
mem[263] = 32'd0;
mem[264] = 32'd0;
mem[265] = 32'd0;
mem[266] = 32'd0;
mem[267] = 32'd0;
mem[268] = 32'd0;
mem[269] = 32'd0;
mem[270] = 32'd0;
mem[271] = 32'd0;
mem[272] = 32'd0;
mem[273] = 32'd0;
mem[274] = 32'd0;
mem[275] = 32'd0;
mem[276] = 32'd0;
mem[277] = 32'd0;
mem[278] = 32'd0;
mem[279] = 32'd0;
mem[280] = 32'd0;
mem[281] = 32'd0;
mem[282] = 32'd0;
mem[283] = 32'd0;
mem[284] = 32'd0;
mem[285] = 32'd0;
mem[286] = 32'd0;
mem[287] = 32'd0;
mem[288] = 32'd0;
mem[289] = 32'd0;
mem[290] = 32'd0;
mem[291] = 32'd0;
mem[292] = 32'd0;
mem[293] = 32'd0;
mem[294] = 32'd0;
mem[295] = 32'd0;
mem[296] = 32'd0;
mem[297] = 32'd0;
mem[298] = 32'd0;
mem[299] = 32'd0;
mem[300] = 32'd0;
mem[301] = 32'd0;
mem[302] = 32'd0;
mem[303] = 32'd0;
mem[304] = 32'd0;
mem[305] = 32'd0;
mem[306] = 32'd0;
mem[307] = 32'd0;
mem[308] = 32'd0;
mem[309] = 32'd0;
mem[310] = 32'd0;
mem[311] = 32'd0;
mem[312] = 32'd0;
mem[313] = 32'd0;
mem[314] = 32'd0;
mem[315] = 32'd0;
mem[316] = 32'd0;
mem[317] = 32'd0;
mem[318] = 32'd0;
mem[319] = 32'd0;
mem[320] = 32'd0;
mem[321] = 32'd0;
mem[322] = 32'd0;
mem[323] = 32'd0;
mem[324] = 32'd0;
mem[325] = 32'd0;
mem[326] = 32'd0;
mem[327] = 32'd0;
mem[328] = 32'd0;
mem[329] = 32'd0;
mem[330] = 32'd0;
mem[331] = 32'd0;
mem[332] = 32'd0;
mem[333] = 32'd0;
mem[334] = 32'd0;
mem[335] = 32'd0;
mem[336] = 32'd0;
mem[337] = 32'd0;
mem[338] = 32'd0;
mem[339] = 32'd0;
mem[340] = 32'd0;
mem[341] = 32'd0;
mem[342] = 32'd0;
mem[343] = 32'd0;
mem[344] = 32'd0;
mem[345] = 32'd0;
mem[346] = 32'd0;
mem[347] = 32'd0;
mem[348] = 32'd0;
mem[349] = 32'd0;
mem[350] = 32'd0;
mem[351] = 32'd0;
mem[352] = 32'd0;
mem[353] = 32'd0;
mem[354] = 32'd0;
mem[355] = 32'd0;
mem[356] = 32'd0;
mem[357] = 32'd0;
mem[358] = 32'd0;
mem[359] = 32'd0;
mem[360] = 32'd0;
mem[361] = 32'd0;
mem[362] = 32'd0;
mem[363] = 32'd0;
mem[364] = 32'd0;
mem[365] = 32'd0;
mem[366] = 32'd0;
mem[367] = 32'd0;
mem[368] = 32'd0;
mem[369] = 32'd0;
mem[370] = 32'd0;
mem[371] = 32'd0;
mem[372] = 32'd0;
mem[373] = 32'd0;
mem[374] = 32'd0;
mem[375] = 32'd0;
mem[376] = 32'd0;
mem[377] = 32'd0;
mem[378] = 32'd0;
mem[379] = 32'd0;
mem[380] = 32'd0;
mem[381] = 32'd0;
mem[382] = 32'd0;
mem[383] = 32'd0;
mem[384] = 32'd0;
mem[385] = 32'd0;
mem[386] = 32'd0;
mem[387] = 32'd0;
mem[388] = 32'd0;
mem[389] = 32'd0;
mem[390] = 32'd0;
mem[391] = 32'd0;
mem[392] = 32'd0;
mem[393] = 32'd0;
mem[394] = 32'd0;
mem[395] = 32'd0;
mem[396] = 32'd0;
mem[397] = 32'd0;
mem[398] = 32'd0;
mem[399] = 32'd0;
mem[400] = 32'd0;
mem[401] = 32'd0;
mem[402] = 32'd0;
mem[403] = 32'd0;
mem[404] = 32'd0;
mem[405] = 32'd0;
mem[406] = 32'd0;
mem[407] = 32'd0;
mem[408] = 32'd0;
mem[409] = 32'd0;
mem[410] = 32'd0;
mem[411] = 32'd0;
mem[412] = 32'd0;
mem[413] = 32'd0;
mem[414] = 32'd0;
mem[415] = 32'd0;
mem[416] = 32'd0;
mem[417] = 32'd0;
mem[418] = 32'd0;
mem[419] = 32'd0;
mem[420] = 32'd0;
mem[421] = 32'd0;
mem[422] = 32'd0;
mem[423] = 32'd0;
mem[424] = 32'd0;
mem[425] = 32'd0;
mem[426] = 32'd0;
mem[427] = 32'd0;
mem[428] = 32'd0;
mem[429] = 32'd0;
mem[430] = 32'd0;
mem[431] = 32'd0;
mem[432] = 32'd0;
mem[433] = 32'd0;
mem[434] = 32'd0;
mem[435] = 32'd0;
mem[436] = 32'd0;
mem[437] = 32'd0;
mem[438] = 32'd0;
mem[439] = 32'd0;
mem[440] = 32'd0;
mem[441] = 32'd0;
mem[442] = 32'd0;
mem[443] = 32'd0;
mem[444] = 32'd0;
mem[445] = 32'd0;
mem[446] = 32'd0;
mem[447] = 32'd0;
mem[448] = 32'd0;
mem[449] = 32'd0;
mem[450] = 32'd0;
mem[451] = 32'd0;
mem[452] = 32'd0;
mem[453] = 32'd0;
mem[454] = 32'd0;
mem[455] = 32'd0;
mem[456] = 32'd0;
mem[457] = 32'd0;
mem[458] = 32'd0;
mem[459] = 32'd0;
mem[460] = 32'd0;
mem[461] = 32'd0;
mem[462] = 32'd0;
mem[463] = 32'd0;
mem[464] = 32'd0;
mem[465] = 32'd0;
mem[466] = 32'd0;
mem[467] = 32'd0;
mem[468] = 32'd0;
mem[469] = 32'd0;
mem[470] = 32'd0;
mem[471] = 32'd0;
mem[472] = 32'd0;
mem[473] = 32'd0;
mem[474] = 32'd0;
mem[475] = 32'd0;
mem[476] = 32'd0;
mem[477] = 32'd0;
mem[478] = 32'd0;
mem[479] = 32'd0;
mem[480] = 32'd0;
mem[481] = 32'd0;
mem[482] = 32'd0;
mem[483] = 32'd0;
mem[484] = 32'd0;
mem[485] = 32'd0;
mem[486] = 32'd0;
mem[487] = 32'd0;
mem[488] = 32'd0;
mem[489] = 32'd0;
mem[490] = 32'd0;
mem[491] = 32'd0;
mem[492] = 32'd0;
mem[493] = 32'd0;
mem[494] = 32'd0;
mem[495] = 32'd0;
mem[496] = 32'd0;
mem[497] = 32'd0;
mem[498] = 32'd0;
mem[499] = 32'd0;
mem[500] = 32'd0;
mem[501] = 32'd0;
mem[502] = 32'd0;
mem[503] = 32'd0;
mem[504] = 32'd0;
mem[505] = 32'd0;
mem[506] = 32'd0;
mem[507] = 32'd0;
mem[508] = 32'd0;
mem[509] = 32'd0;
mem[510] = 32'd0;
mem[511] = 32'd0;
end
always @(posedge clk) begin
if (mem_w_en)
mem[mem_w_addr] <= mem_w_data;
end
reg [31:0] _0_;
always @(posedge clk) begin
if (mem_r_en) begin
_0_ <= mem[mem_r_addr];
end
end
assign mem_r_data = _0_;
reg [31:0] \mem$10 [511:0];
initial begin
\mem$10 [0] = 32'd0;
\mem$10 [1] = 32'd0;
\mem$10 [2] = 32'd0;
\mem$10 [3] = 32'd0;
\mem$10 [4] = 32'd0;
\mem$10 [5] = 32'd0;
\mem$10 [6] = 32'd0;
\mem$10 [7] = 32'd0;
\mem$10 [8] = 32'd0;
\mem$10 [9] = 32'd0;
\mem$10 [10] = 32'd0;
\mem$10 [11] = 32'd0;
\mem$10 [12] = 32'd0;
\mem$10 [13] = 32'd0;
\mem$10 [14] = 32'd0;
\mem$10 [15] = 32'd0;
\mem$10 [16] = 32'd0;
\mem$10 [17] = 32'd0;
\mem$10 [18] = 32'd0;
\mem$10 [19] = 32'd0;
\mem$10 [20] = 32'd0;
\mem$10 [21] = 32'd0;
\mem$10 [22] = 32'd0;
\mem$10 [23] = 32'd0;
\mem$10 [24] = 32'd0;
\mem$10 [25] = 32'd0;
\mem$10 [26] = 32'd0;
\mem$10 [27] = 32'd0;
\mem$10 [28] = 32'd0;
\mem$10 [29] = 32'd0;
\mem$10 [30] = 32'd0;
\mem$10 [31] = 32'd0;
\mem$10 [32] = 32'd0;
\mem$10 [33] = 32'd0;
\mem$10 [34] = 32'd0;
\mem$10 [35] = 32'd0;
\mem$10 [36] = 32'd0;
\mem$10 [37] = 32'd0;
\mem$10 [38] = 32'd0;
\mem$10 [39] = 32'd0;
\mem$10 [40] = 32'd0;
\mem$10 [41] = 32'd0;
\mem$10 [42] = 32'd0;
\mem$10 [43] = 32'd0;
\mem$10 [44] = 32'd0;
\mem$10 [45] = 32'd0;
\mem$10 [46] = 32'd0;
\mem$10 [47] = 32'd0;
\mem$10 [48] = 32'd0;
\mem$10 [49] = 32'd0;
\mem$10 [50] = 32'd0;
\mem$10 [51] = 32'd0;
\mem$10 [52] = 32'd0;
\mem$10 [53] = 32'd0;
\mem$10 [54] = 32'd0;
\mem$10 [55] = 32'd0;
\mem$10 [56] = 32'd0;
\mem$10 [57] = 32'd0;
\mem$10 [58] = 32'd0;
\mem$10 [59] = 32'd0;
\mem$10 [60] = 32'd0;
\mem$10 [61] = 32'd0;
\mem$10 [62] = 32'd0;
\mem$10 [63] = 32'd0;
\mem$10 [64] = 32'd0;
\mem$10 [65] = 32'd0;
\mem$10 [66] = 32'd0;
\mem$10 [67] = 32'd0;
\mem$10 [68] = 32'd0;
\mem$10 [69] = 32'd0;
\mem$10 [70] = 32'd0;
\mem$10 [71] = 32'd0;
\mem$10 [72] = 32'd0;
\mem$10 [73] = 32'd0;
\mem$10 [74] = 32'd0;
\mem$10 [75] = 32'd0;
\mem$10 [76] = 32'd0;
\mem$10 [77] = 32'd0;
\mem$10 [78] = 32'd0;
\mem$10 [79] = 32'd0;
\mem$10 [80] = 32'd0;
\mem$10 [81] = 32'd0;
\mem$10 [82] = 32'd0;
\mem$10 [83] = 32'd0;
\mem$10 [84] = 32'd0;
\mem$10 [85] = 32'd0;
\mem$10 [86] = 32'd0;
\mem$10 [87] = 32'd0;
\mem$10 [88] = 32'd0;
\mem$10 [89] = 32'd0;
\mem$10 [90] = 32'd0;
\mem$10 [91] = 32'd0;
\mem$10 [92] = 32'd0;
\mem$10 [93] = 32'd0;
\mem$10 [94] = 32'd0;
\mem$10 [95] = 32'd0;
\mem$10 [96] = 32'd0;
\mem$10 [97] = 32'd0;
\mem$10 [98] = 32'd0;
\mem$10 [99] = 32'd0;
\mem$10 [100] = 32'd0;
\mem$10 [101] = 32'd0;
\mem$10 [102] = 32'd0;
\mem$10 [103] = 32'd0;
\mem$10 [104] = 32'd0;
\mem$10 [105] = 32'd0;
\mem$10 [106] = 32'd0;
\mem$10 [107] = 32'd0;
\mem$10 [108] = 32'd0;
\mem$10 [109] = 32'd0;
\mem$10 [110] = 32'd0;
\mem$10 [111] = 32'd0;
\mem$10 [112] = 32'd0;
\mem$10 [113] = 32'd0;
\mem$10 [114] = 32'd0;
\mem$10 [115] = 32'd0;
\mem$10 [116] = 32'd0;
\mem$10 [117] = 32'd0;
\mem$10 [118] = 32'd0;
\mem$10 [119] = 32'd0;
\mem$10 [120] = 32'd0;
\mem$10 [121] = 32'd0;
\mem$10 [122] = 32'd0;
\mem$10 [123] = 32'd0;
\mem$10 [124] = 32'd0;
\mem$10 [125] = 32'd0;
\mem$10 [126] = 32'd0;
\mem$10 [127] = 32'd0;
\mem$10 [128] = 32'd0;
\mem$10 [129] = 32'd0;
\mem$10 [130] = 32'd0;
\mem$10 [131] = 32'd0;
\mem$10 [132] = 32'd0;
\mem$10 [133] = 32'd0;
\mem$10 [134] = 32'd0;
\mem$10 [135] = 32'd0;
\mem$10 [136] = 32'd0;
\mem$10 [137] = 32'd0;
\mem$10 [138] = 32'd0;
\mem$10 [139] = 32'd0;
\mem$10 [140] = 32'd0;
\mem$10 [141] = 32'd0;
\mem$10 [142] = 32'd0;
\mem$10 [143] = 32'd0;
\mem$10 [144] = 32'd0;
\mem$10 [145] = 32'd0;
\mem$10 [146] = 32'd0;
\mem$10 [147] = 32'd0;
\mem$10 [148] = 32'd0;
\mem$10 [149] = 32'd0;
\mem$10 [150] = 32'd0;
\mem$10 [151] = 32'd0;
\mem$10 [152] = 32'd0;
\mem$10 [153] = 32'd0;
\mem$10 [154] = 32'd0;
\mem$10 [155] = 32'd0;
\mem$10 [156] = 32'd0;
\mem$10 [157] = 32'd0;
\mem$10 [158] = 32'd0;
\mem$10 [159] = 32'd0;
\mem$10 [160] = 32'd0;
\mem$10 [161] = 32'd0;
\mem$10 [162] = 32'd0;
\mem$10 [163] = 32'd0;
\mem$10 [164] = 32'd0;
\mem$10 [165] = 32'd0;
\mem$10 [166] = 32'd0;
\mem$10 [167] = 32'd0;
\mem$10 [168] = 32'd0;
\mem$10 [169] = 32'd0;
\mem$10 [170] = 32'd0;
\mem$10 [171] = 32'd0;
\mem$10 [172] = 32'd0;
\mem$10 [173] = 32'd0;
\mem$10 [174] = 32'd0;
\mem$10 [175] = 32'd0;
\mem$10 [176] = 32'd0;
\mem$10 [177] = 32'd0;
\mem$10 [178] = 32'd0;
\mem$10 [179] = 32'd0;
\mem$10 [180] = 32'd0;
\mem$10 [181] = 32'd0;
\mem$10 [182] = 32'd0;
\mem$10 [183] = 32'd0;
\mem$10 [184] = 32'd0;
\mem$10 [185] = 32'd0;
\mem$10 [186] = 32'd0;
\mem$10 [187] = 32'd0;
\mem$10 [188] = 32'd0;
\mem$10 [189] = 32'd0;
\mem$10 [190] = 32'd0;
\mem$10 [191] = 32'd0;
\mem$10 [192] = 32'd0;
\mem$10 [193] = 32'd0;
\mem$10 [194] = 32'd0;
\mem$10 [195] = 32'd0;
\mem$10 [196] = 32'd0;
\mem$10 [197] = 32'd0;
\mem$10 [198] = 32'd0;
\mem$10 [199] = 32'd0;
\mem$10 [200] = 32'd0;
\mem$10 [201] = 32'd0;
\mem$10 [202] = 32'd0;
\mem$10 [203] = 32'd0;
\mem$10 [204] = 32'd0;
\mem$10 [205] = 32'd0;
\mem$10 [206] = 32'd0;
\mem$10 [207] = 32'd0;
\mem$10 [208] = 32'd0;
\mem$10 [209] = 32'd0;
\mem$10 [210] = 32'd0;
\mem$10 [211] = 32'd0;
\mem$10 [212] = 32'd0;
\mem$10 [213] = 32'd0;
\mem$10 [214] = 32'd0;
\mem$10 [215] = 32'd0;
\mem$10 [216] = 32'd0;
\mem$10 [217] = 32'd0;
\mem$10 [218] = 32'd0;
\mem$10 [219] = 32'd0;
\mem$10 [220] = 32'd0;
\mem$10 [221] = 32'd0;
\mem$10 [222] = 32'd0;
\mem$10 [223] = 32'd0;
\mem$10 [224] = 32'd0;
\mem$10 [225] = 32'd0;
\mem$10 [226] = 32'd0;
\mem$10 [227] = 32'd0;
\mem$10 [228] = 32'd0;
\mem$10 [229] = 32'd0;
\mem$10 [230] = 32'd0;
\mem$10 [231] = 32'd0;
\mem$10 [232] = 32'd0;
\mem$10 [233] = 32'd0;
\mem$10 [234] = 32'd0;
\mem$10 [235] = 32'd0;
\mem$10 [236] = 32'd0;
\mem$10 [237] = 32'd0;
\mem$10 [238] = 32'd0;
\mem$10 [239] = 32'd0;
\mem$10 [240] = 32'd0;
\mem$10 [241] = 32'd0;
\mem$10 [242] = 32'd0;
\mem$10 [243] = 32'd0;
\mem$10 [244] = 32'd0;
\mem$10 [245] = 32'd0;
\mem$10 [246] = 32'd0;
\mem$10 [247] = 32'd0;
\mem$10 [248] = 32'd0;
\mem$10 [249] = 32'd0;
\mem$10 [250] = 32'd0;
\mem$10 [251] = 32'd0;
\mem$10 [252] = 32'd0;
\mem$10 [253] = 32'd0;
\mem$10 [254] = 32'd0;
\mem$10 [255] = 32'd0;
\mem$10 [256] = 32'd0;
\mem$10 [257] = 32'd0;
\mem$10 [258] = 32'd0;
\mem$10 [259] = 32'd0;
\mem$10 [260] = 32'd0;
\mem$10 [261] = 32'd0;
\mem$10 [262] = 32'd0;
\mem$10 [263] = 32'd0;
\mem$10 [264] = 32'd0;
\mem$10 [265] = 32'd0;
\mem$10 [266] = 32'd0;
\mem$10 [267] = 32'd0;
\mem$10 [268] = 32'd0;
\mem$10 [269] = 32'd0;
\mem$10 [270] = 32'd0;
\mem$10 [271] = 32'd0;
\mem$10 [272] = 32'd0;
\mem$10 [273] = 32'd0;
\mem$10 [274] = 32'd0;
\mem$10 [275] = 32'd0;
\mem$10 [276] = 32'd0;
\mem$10 [277] = 32'd0;
\mem$10 [278] = 32'd0;
\mem$10 [279] = 32'd0;
\mem$10 [280] = 32'd0;
\mem$10 [281] = 32'd0;
\mem$10 [282] = 32'd0;
\mem$10 [283] = 32'd0;
\mem$10 [284] = 32'd0;
\mem$10 [285] = 32'd0;
\mem$10 [286] = 32'd0;
\mem$10 [287] = 32'd0;
\mem$10 [288] = 32'd0;
\mem$10 [289] = 32'd0;
\mem$10 [290] = 32'd0;
\mem$10 [291] = 32'd0;
\mem$10 [292] = 32'd0;
\mem$10 [293] = 32'd0;
\mem$10 [294] = 32'd0;
\mem$10 [295] = 32'd0;
\mem$10 [296] = 32'd0;
\mem$10 [297] = 32'd0;
\mem$10 [298] = 32'd0;
\mem$10 [299] = 32'd0;
\mem$10 [300] = 32'd0;
\mem$10 [301] = 32'd0;
\mem$10 [302] = 32'd0;
\mem$10 [303] = 32'd0;
\mem$10 [304] = 32'd0;
\mem$10 [305] = 32'd0;
\mem$10 [306] = 32'd0;
\mem$10 [307] = 32'd0;
\mem$10 [308] = 32'd0;
\mem$10 [309] = 32'd0;
\mem$10 [310] = 32'd0;
\mem$10 [311] = 32'd0;
\mem$10 [312] = 32'd0;
\mem$10 [313] = 32'd0;
\mem$10 [314] = 32'd0;
\mem$10 [315] = 32'd0;
\mem$10 [316] = 32'd0;
\mem$10 [317] = 32'd0;
\mem$10 [318] = 32'd0;
\mem$10 [319] = 32'd0;
\mem$10 [320] = 32'd0;
\mem$10 [321] = 32'd0;
\mem$10 [322] = 32'd0;
\mem$10 [323] = 32'd0;
\mem$10 [324] = 32'd0;
\mem$10 [325] = 32'd0;
\mem$10 [326] = 32'd0;
\mem$10 [327] = 32'd0;
\mem$10 [328] = 32'd0;
\mem$10 [329] = 32'd0;
\mem$10 [330] = 32'd0;
\mem$10 [331] = 32'd0;
\mem$10 [332] = 32'd0;
\mem$10 [333] = 32'd0;
\mem$10 [334] = 32'd0;
\mem$10 [335] = 32'd0;
\mem$10 [336] = 32'd0;
\mem$10 [337] = 32'd0;
\mem$10 [338] = 32'd0;
\mem$10 [339] = 32'd0;
\mem$10 [340] = 32'd0;
\mem$10 [341] = 32'd0;
\mem$10 [342] = 32'd0;
\mem$10 [343] = 32'd0;
\mem$10 [344] = 32'd0;
\mem$10 [345] = 32'd0;
\mem$10 [346] = 32'd0;
\mem$10 [347] = 32'd0;
\mem$10 [348] = 32'd0;
\mem$10 [349] = 32'd0;
\mem$10 [350] = 32'd0;
\mem$10 [351] = 32'd0;
\mem$10 [352] = 32'd0;
\mem$10 [353] = 32'd0;
\mem$10 [354] = 32'd0;
\mem$10 [355] = 32'd0;
\mem$10 [356] = 32'd0;
\mem$10 [357] = 32'd0;
\mem$10 [358] = 32'd0;
\mem$10 [359] = 32'd0;
\mem$10 [360] = 32'd0;
\mem$10 [361] = 32'd0;
\mem$10 [362] = 32'd0;
\mem$10 [363] = 32'd0;
\mem$10 [364] = 32'd0;
\mem$10 [365] = 32'd0;
\mem$10 [366] = 32'd0;
\mem$10 [367] = 32'd0;
\mem$10 [368] = 32'd0;
\mem$10 [369] = 32'd0;
\mem$10 [370] = 32'd0;
\mem$10 [371] = 32'd0;
\mem$10 [372] = 32'd0;
\mem$10 [373] = 32'd0;
\mem$10 [374] = 32'd0;
\mem$10 [375] = 32'd0;
\mem$10 [376] = 32'd0;
\mem$10 [377] = 32'd0;
\mem$10 [378] = 32'd0;
\mem$10 [379] = 32'd0;
\mem$10 [380] = 32'd0;
\mem$10 [381] = 32'd0;
\mem$10 [382] = 32'd0;
\mem$10 [383] = 32'd0;
\mem$10 [384] = 32'd0;
\mem$10 [385] = 32'd0;
\mem$10 [386] = 32'd0;
\mem$10 [387] = 32'd0;
\mem$10 [388] = 32'd0;
\mem$10 [389] = 32'd0;
\mem$10 [390] = 32'd0;
\mem$10 [391] = 32'd0;
\mem$10 [392] = 32'd0;
\mem$10 [393] = 32'd0;
\mem$10 [394] = 32'd0;
\mem$10 [395] = 32'd0;
\mem$10 [396] = 32'd0;
\mem$10 [397] = 32'd0;
\mem$10 [398] = 32'd0;
\mem$10 [399] = 32'd0;
\mem$10 [400] = 32'd0;
\mem$10 [401] = 32'd0;
\mem$10 [402] = 32'd0;
\mem$10 [403] = 32'd0;
\mem$10 [404] = 32'd0;
\mem$10 [405] = 32'd0;
\mem$10 [406] = 32'd0;
\mem$10 [407] = 32'd0;
\mem$10 [408] = 32'd0;
\mem$10 [409] = 32'd0;
\mem$10 [410] = 32'd0;
\mem$10 [411] = 32'd0;
\mem$10 [412] = 32'd0;
\mem$10 [413] = 32'd0;
\mem$10 [414] = 32'd0;
\mem$10 [415] = 32'd0;
\mem$10 [416] = 32'd0;
\mem$10 [417] = 32'd0;
\mem$10 [418] = 32'd0;
\mem$10 [419] = 32'd0;
\mem$10 [420] = 32'd0;
\mem$10 [421] = 32'd0;
\mem$10 [422] = 32'd0;
\mem$10 [423] = 32'd0;
\mem$10 [424] = 32'd0;
\mem$10 [425] = 32'd0;
\mem$10 [426] = 32'd0;
\mem$10 [427] = 32'd0;
\mem$10 [428] = 32'd0;
\mem$10 [429] = 32'd0;
\mem$10 [430] = 32'd0;
\mem$10 [431] = 32'd0;
\mem$10 [432] = 32'd0;
\mem$10 [433] = 32'd0;
\mem$10 [434] = 32'd0;
\mem$10 [435] = 32'd0;
\mem$10 [436] = 32'd0;
\mem$10 [437] = 32'd0;
\mem$10 [438] = 32'd0;
\mem$10 [439] = 32'd0;
\mem$10 [440] = 32'd0;
\mem$10 [441] = 32'd0;
\mem$10 [442] = 32'd0;
\mem$10 [443] = 32'd0;
\mem$10 [444] = 32'd0;
\mem$10 [445] = 32'd0;
\mem$10 [446] = 32'd0;
\mem$10 [447] = 32'd0;
\mem$10 [448] = 32'd0;
\mem$10 [449] = 32'd0;
\mem$10 [450] = 32'd0;
\mem$10 [451] = 32'd0;
\mem$10 [452] = 32'd0;
\mem$10 [453] = 32'd0;
\mem$10 [454] = 32'd0;
\mem$10 [455] = 32'd0;
\mem$10 [456] = 32'd0;
\mem$10 [457] = 32'd0;
\mem$10 [458] = 32'd0;
\mem$10 [459] = 32'd0;
\mem$10 [460] = 32'd0;
\mem$10 [461] = 32'd0;
\mem$10 [462] = 32'd0;
\mem$10 [463] = 32'd0;
\mem$10 [464] = 32'd0;
\mem$10 [465] = 32'd0;
\mem$10 [466] = 32'd0;
\mem$10 [467] = 32'd0;
\mem$10 [468] = 32'd0;
\mem$10 [469] = 32'd0;
\mem$10 [470] = 32'd0;
\mem$10 [471] = 32'd0;
\mem$10 [472] = 32'd0;
\mem$10 [473] = 32'd0;
\mem$10 [474] = 32'd0;
\mem$10 [475] = 32'd0;
\mem$10 [476] = 32'd0;
\mem$10 [477] = 32'd0;
\mem$10 [478] = 32'd0;
\mem$10 [479] = 32'd0;
\mem$10 [480] = 32'd0;
\mem$10 [481] = 32'd0;
\mem$10 [482] = 32'd0;
\mem$10 [483] = 32'd0;
\mem$10 [484] = 32'd0;
\mem$10 [485] = 32'd0;
\mem$10 [486] = 32'd0;
\mem$10 [487] = 32'd0;
\mem$10 [488] = 32'd0;
\mem$10 [489] = 32'd0;
\mem$10 [490] = 32'd0;
\mem$10 [491] = 32'd0;
\mem$10 [492] = 32'd0;
\mem$10 [493] = 32'd0;
\mem$10 [494] = 32'd0;
\mem$10 [495] = 32'd0;
\mem$10 [496] = 32'd0;
\mem$10 [497] = 32'd0;
\mem$10 [498] = 32'd0;
\mem$10 [499] = 32'd0;
\mem$10 [500] = 32'd0;
\mem$10 [501] = 32'd0;
\mem$10 [502] = 32'd0;
\mem$10 [503] = 32'd0;
\mem$10 [504] = 32'd0;
\mem$10 [505] = 32'd0;
\mem$10 [506] = 32'd0;
\mem$10 [507] = 32'd0;
\mem$10 [508] = 32'd0;
\mem$10 [509] = 32'd0;
\mem$10 [510] = 32'd0;
\mem$10 [511] = 32'd0;
end
always @(posedge clk) begin
if (\mem_w_en$15 )
\mem$10 [\mem_w_addr$16 ] <= \mem_w_data$17 ;
end
reg [31:0] _1_;
always @(posedge clk) begin
if (\mem_r_en$12 ) begin
_1_ <= \mem$10 [\mem_r_addr$13 ];
end
end
assign \mem_r_data$14 = _1_;
reg [31:0] \mem$18 [511:0];
initial begin
\mem$18 [0] = 32'd0;
\mem$18 [1] = 32'd0;
\mem$18 [2] = 32'd0;
\mem$18 [3] = 32'd0;
\mem$18 [4] = 32'd0;
\mem$18 [5] = 32'd0;
\mem$18 [6] = 32'd0;
\mem$18 [7] = 32'd0;
\mem$18 [8] = 32'd0;
\mem$18 [9] = 32'd0;
\mem$18 [10] = 32'd0;
\mem$18 [11] = 32'd0;
\mem$18 [12] = 32'd0;
\mem$18 [13] = 32'd0;
\mem$18 [14] = 32'd0;
\mem$18 [15] = 32'd0;
\mem$18 [16] = 32'd0;
\mem$18 [17] = 32'd0;
\mem$18 [18] = 32'd0;
\mem$18 [19] = 32'd0;
\mem$18 [20] = 32'd0;
\mem$18 [21] = 32'd0;
\mem$18 [22] = 32'd0;
\mem$18 [23] = 32'd0;
\mem$18 [24] = 32'd0;
\mem$18 [25] = 32'd0;
\mem$18 [26] = 32'd0;
\mem$18 [27] = 32'd0;
\mem$18 [28] = 32'd0;
\mem$18 [29] = 32'd0;
\mem$18 [30] = 32'd0;
\mem$18 [31] = 32'd0;
\mem$18 [32] = 32'd0;
\mem$18 [33] = 32'd0;
\mem$18 [34] = 32'd0;
\mem$18 [35] = 32'd0;
\mem$18 [36] = 32'd0;
\mem$18 [37] = 32'd0;
\mem$18 [38] = 32'd0;
\mem$18 [39] = 32'd0;
\mem$18 [40] = 32'd0;
\mem$18 [41] = 32'd0;
\mem$18 [42] = 32'd0;
\mem$18 [43] = 32'd0;
\mem$18 [44] = 32'd0;
\mem$18 [45] = 32'd0;
\mem$18 [46] = 32'd0;
\mem$18 [47] = 32'd0;
\mem$18 [48] = 32'd0;
\mem$18 [49] = 32'd0;
\mem$18 [50] = 32'd0;
\mem$18 [51] = 32'd0;
\mem$18 [52] = 32'd0;
\mem$18 [53] = 32'd0;
\mem$18 [54] = 32'd0;
\mem$18 [55] = 32'd0;
\mem$18 [56] = 32'd0;
\mem$18 [57] = 32'd0;
\mem$18 [58] = 32'd0;
\mem$18 [59] = 32'd0;
\mem$18 [60] = 32'd0;
\mem$18 [61] = 32'd0;
\mem$18 [62] = 32'd0;
\mem$18 [63] = 32'd0;
\mem$18 [64] = 32'd0;
\mem$18 [65] = 32'd0;
\mem$18 [66] = 32'd0;
\mem$18 [67] = 32'd0;
\mem$18 [68] = 32'd0;
\mem$18 [69] = 32'd0;
\mem$18 [70] = 32'd0;
\mem$18 [71] = 32'd0;
\mem$18 [72] = 32'd0;
\mem$18 [73] = 32'd0;
\mem$18 [74] = 32'd0;
\mem$18 [75] = 32'd0;
\mem$18 [76] = 32'd0;
\mem$18 [77] = 32'd0;
\mem$18 [78] = 32'd0;
\mem$18 [79] = 32'd0;
\mem$18 [80] = 32'd0;
\mem$18 [81] = 32'd0;
\mem$18 [82] = 32'd0;
\mem$18 [83] = 32'd0;
\mem$18 [84] = 32'd0;
\mem$18 [85] = 32'd0;
\mem$18 [86] = 32'd0;
\mem$18 [87] = 32'd0;
\mem$18 [88] = 32'd0;
\mem$18 [89] = 32'd0;
\mem$18 [90] = 32'd0;
\mem$18 [91] = 32'd0;
\mem$18 [92] = 32'd0;
\mem$18 [93] = 32'd0;
\mem$18 [94] = 32'd0;
\mem$18 [95] = 32'd0;
\mem$18 [96] = 32'd0;
\mem$18 [97] = 32'd0;
\mem$18 [98] = 32'd0;
\mem$18 [99] = 32'd0;
\mem$18 [100] = 32'd0;
\mem$18 [101] = 32'd0;
\mem$18 [102] = 32'd0;
\mem$18 [103] = 32'd0;
\mem$18 [104] = 32'd0;
\mem$18 [105] = 32'd0;
\mem$18 [106] = 32'd0;
\mem$18 [107] = 32'd0;
\mem$18 [108] = 32'd0;
\mem$18 [109] = 32'd0;
\mem$18 [110] = 32'd0;
\mem$18 [111] = 32'd0;
\mem$18 [112] = 32'd0;
\mem$18 [113] = 32'd0;
\mem$18 [114] = 32'd0;
\mem$18 [115] = 32'd0;
\mem$18 [116] = 32'd0;
\mem$18 [117] = 32'd0;
\mem$18 [118] = 32'd0;
\mem$18 [119] = 32'd0;
\mem$18 [120] = 32'd0;
\mem$18 [121] = 32'd0;
\mem$18 [122] = 32'd0;
\mem$18 [123] = 32'd0;
\mem$18 [124] = 32'd0;
\mem$18 [125] = 32'd0;
\mem$18 [126] = 32'd0;
\mem$18 [127] = 32'd0;
\mem$18 [128] = 32'd0;
\mem$18 [129] = 32'd0;
\mem$18 [130] = 32'd0;
\mem$18 [131] = 32'd0;
\mem$18 [132] = 32'd0;
\mem$18 [133] = 32'd0;
\mem$18 [134] = 32'd0;
\mem$18 [135] = 32'd0;
\mem$18 [136] = 32'd0;
\mem$18 [137] = 32'd0;
\mem$18 [138] = 32'd0;
\mem$18 [139] = 32'd0;
\mem$18 [140] = 32'd0;
\mem$18 [141] = 32'd0;
\mem$18 [142] = 32'd0;
\mem$18 [143] = 32'd0;
\mem$18 [144] = 32'd0;
\mem$18 [145] = 32'd0;
\mem$18 [146] = 32'd0;
\mem$18 [147] = 32'd0;
\mem$18 [148] = 32'd0;
\mem$18 [149] = 32'd0;
\mem$18 [150] = 32'd0;
\mem$18 [151] = 32'd0;
\mem$18 [152] = 32'd0;
\mem$18 [153] = 32'd0;
\mem$18 [154] = 32'd0;
\mem$18 [155] = 32'd0;
\mem$18 [156] = 32'd0;
\mem$18 [157] = 32'd0;
\mem$18 [158] = 32'd0;
\mem$18 [159] = 32'd0;
\mem$18 [160] = 32'd0;
\mem$18 [161] = 32'd0;
\mem$18 [162] = 32'd0;
\mem$18 [163] = 32'd0;
\mem$18 [164] = 32'd0;
\mem$18 [165] = 32'd0;
\mem$18 [166] = 32'd0;
\mem$18 [167] = 32'd0;
\mem$18 [168] = 32'd0;
\mem$18 [169] = 32'd0;
\mem$18 [170] = 32'd0;
\mem$18 [171] = 32'd0;
\mem$18 [172] = 32'd0;
\mem$18 [173] = 32'd0;
\mem$18 [174] = 32'd0;
\mem$18 [175] = 32'd0;
\mem$18 [176] = 32'd0;
\mem$18 [177] = 32'd0;
\mem$18 [178] = 32'd0;
\mem$18 [179] = 32'd0;
\mem$18 [180] = 32'd0;
\mem$18 [181] = 32'd0;
\mem$18 [182] = 32'd0;
\mem$18 [183] = 32'd0;
\mem$18 [184] = 32'd0;
\mem$18 [185] = 32'd0;
\mem$18 [186] = 32'd0;
\mem$18 [187] = 32'd0;
\mem$18 [188] = 32'd0;
\mem$18 [189] = 32'd0;
\mem$18 [190] = 32'd0;
\mem$18 [191] = 32'd0;
\mem$18 [192] = 32'd0;
\mem$18 [193] = 32'd0;
\mem$18 [194] = 32'd0;
\mem$18 [195] = 32'd0;
\mem$18 [196] = 32'd0;
\mem$18 [197] = 32'd0;
\mem$18 [198] = 32'd0;
\mem$18 [199] = 32'd0;
\mem$18 [200] = 32'd0;
\mem$18 [201] = 32'd0;
\mem$18 [202] = 32'd0;
\mem$18 [203] = 32'd0;
\mem$18 [204] = 32'd0;
\mem$18 [205] = 32'd0;
\mem$18 [206] = 32'd0;
\mem$18 [207] = 32'd0;
\mem$18 [208] = 32'd0;
\mem$18 [209] = 32'd0;
\mem$18 [210] = 32'd0;
\mem$18 [211] = 32'd0;
\mem$18 [212] = 32'd0;
\mem$18 [213] = 32'd0;
\mem$18 [214] = 32'd0;
\mem$18 [215] = 32'd0;
\mem$18 [216] = 32'd0;
\mem$18 [217] = 32'd0;
\mem$18 [218] = 32'd0;
\mem$18 [219] = 32'd0;
\mem$18 [220] = 32'd0;
\mem$18 [221] = 32'd0;
\mem$18 [222] = 32'd0;
\mem$18 [223] = 32'd0;
\mem$18 [224] = 32'd0;
\mem$18 [225] = 32'd0;
\mem$18 [226] = 32'd0;
\mem$18 [227] = 32'd0;
\mem$18 [228] = 32'd0;
\mem$18 [229] = 32'd0;
\mem$18 [230] = 32'd0;
\mem$18 [231] = 32'd0;
\mem$18 [232] = 32'd0;
\mem$18 [233] = 32'd0;
\mem$18 [234] = 32'd0;
\mem$18 [235] = 32'd0;
\mem$18 [236] = 32'd0;
\mem$18 [237] = 32'd0;
\mem$18 [238] = 32'd0;
\mem$18 [239] = 32'd0;
\mem$18 [240] = 32'd0;
\mem$18 [241] = 32'd0;
\mem$18 [242] = 32'd0;
\mem$18 [243] = 32'd0;
\mem$18 [244] = 32'd0;
\mem$18 [245] = 32'd0;
\mem$18 [246] = 32'd0;
\mem$18 [247] = 32'd0;
\mem$18 [248] = 32'd0;
\mem$18 [249] = 32'd0;
\mem$18 [250] = 32'd0;
\mem$18 [251] = 32'd0;
\mem$18 [252] = 32'd0;
\mem$18 [253] = 32'd0;
\mem$18 [254] = 32'd0;
\mem$18 [255] = 32'd0;
\mem$18 [256] = 32'd0;
\mem$18 [257] = 32'd0;
\mem$18 [258] = 32'd0;
\mem$18 [259] = 32'd0;
\mem$18 [260] = 32'd0;
\mem$18 [261] = 32'd0;
\mem$18 [262] = 32'd0;
\mem$18 [263] = 32'd0;
\mem$18 [264] = 32'd0;
\mem$18 [265] = 32'd0;
\mem$18 [266] = 32'd0;
\mem$18 [267] = 32'd0;
\mem$18 [268] = 32'd0;
\mem$18 [269] = 32'd0;
\mem$18 [270] = 32'd0;
\mem$18 [271] = 32'd0;
\mem$18 [272] = 32'd0;
\mem$18 [273] = 32'd0;
\mem$18 [274] = 32'd0;
\mem$18 [275] = 32'd0;
\mem$18 [276] = 32'd0;
\mem$18 [277] = 32'd0;
\mem$18 [278] = 32'd0;
\mem$18 [279] = 32'd0;
\mem$18 [280] = 32'd0;
\mem$18 [281] = 32'd0;
\mem$18 [282] = 32'd0;
\mem$18 [283] = 32'd0;
\mem$18 [284] = 32'd0;
\mem$18 [285] = 32'd0;
\mem$18 [286] = 32'd0;
\mem$18 [287] = 32'd0;
\mem$18 [288] = 32'd0;
\mem$18 [289] = 32'd0;
\mem$18 [290] = 32'd0;
\mem$18 [291] = 32'd0;
\mem$18 [292] = 32'd0;
\mem$18 [293] = 32'd0;
\mem$18 [294] = 32'd0;
\mem$18 [295] = 32'd0;
\mem$18 [296] = 32'd0;
\mem$18 [297] = 32'd0;
\mem$18 [298] = 32'd0;
\mem$18 [299] = 32'd0;
\mem$18 [300] = 32'd0;
\mem$18 [301] = 32'd0;
\mem$18 [302] = 32'd0;
\mem$18 [303] = 32'd0;
\mem$18 [304] = 32'd0;
\mem$18 [305] = 32'd0;
\mem$18 [306] = 32'd0;
\mem$18 [307] = 32'd0;
\mem$18 [308] = 32'd0;
\mem$18 [309] = 32'd0;
\mem$18 [310] = 32'd0;
\mem$18 [311] = 32'd0;
\mem$18 [312] = 32'd0;
\mem$18 [313] = 32'd0;
\mem$18 [314] = 32'd0;
\mem$18 [315] = 32'd0;
\mem$18 [316] = 32'd0;
\mem$18 [317] = 32'd0;
\mem$18 [318] = 32'd0;
\mem$18 [319] = 32'd0;
\mem$18 [320] = 32'd0;
\mem$18 [321] = 32'd0;
\mem$18 [322] = 32'd0;
\mem$18 [323] = 32'd0;
\mem$18 [324] = 32'd0;
\mem$18 [325] = 32'd0;
\mem$18 [326] = 32'd0;
\mem$18 [327] = 32'd0;
\mem$18 [328] = 32'd0;
\mem$18 [329] = 32'd0;
\mem$18 [330] = 32'd0;
\mem$18 [331] = 32'd0;
\mem$18 [332] = 32'd0;
\mem$18 [333] = 32'd0;
\mem$18 [334] = 32'd0;
\mem$18 [335] = 32'd0;
\mem$18 [336] = 32'd0;
\mem$18 [337] = 32'd0;
\mem$18 [338] = 32'd0;
\mem$18 [339] = 32'd0;
\mem$18 [340] = 32'd0;
\mem$18 [341] = 32'd0;
\mem$18 [342] = 32'd0;
\mem$18 [343] = 32'd0;
\mem$18 [344] = 32'd0;
\mem$18 [345] = 32'd0;
\mem$18 [346] = 32'd0;
\mem$18 [347] = 32'd0;
\mem$18 [348] = 32'd0;
\mem$18 [349] = 32'd0;
\mem$18 [350] = 32'd0;
\mem$18 [351] = 32'd0;
\mem$18 [352] = 32'd0;
\mem$18 [353] = 32'd0;
\mem$18 [354] = 32'd0;
\mem$18 [355] = 32'd0;
\mem$18 [356] = 32'd0;
\mem$18 [357] = 32'd0;
\mem$18 [358] = 32'd0;
\mem$18 [359] = 32'd0;
\mem$18 [360] = 32'd0;
\mem$18 [361] = 32'd0;
\mem$18 [362] = 32'd0;
\mem$18 [363] = 32'd0;
\mem$18 [364] = 32'd0;
\mem$18 [365] = 32'd0;
\mem$18 [366] = 32'd0;
\mem$18 [367] = 32'd0;
\mem$18 [368] = 32'd0;
\mem$18 [369] = 32'd0;
\mem$18 [370] = 32'd0;
\mem$18 [371] = 32'd0;
\mem$18 [372] = 32'd0;
\mem$18 [373] = 32'd0;
\mem$18 [374] = 32'd0;
\mem$18 [375] = 32'd0;
\mem$18 [376] = 32'd0;
\mem$18 [377] = 32'd0;
\mem$18 [378] = 32'd0;
\mem$18 [379] = 32'd0;
\mem$18 [380] = 32'd0;
\mem$18 [381] = 32'd0;
\mem$18 [382] = 32'd0;
\mem$18 [383] = 32'd0;
\mem$18 [384] = 32'd0;
\mem$18 [385] = 32'd0;
\mem$18 [386] = 32'd0;
\mem$18 [387] = 32'd0;
\mem$18 [388] = 32'd0;
\mem$18 [389] = 32'd0;
\mem$18 [390] = 32'd0;
\mem$18 [391] = 32'd0;
\mem$18 [392] = 32'd0;
\mem$18 [393] = 32'd0;
\mem$18 [394] = 32'd0;
\mem$18 [395] = 32'd0;
\mem$18 [396] = 32'd0;
\mem$18 [397] = 32'd0;
\mem$18 [398] = 32'd0;
\mem$18 [399] = 32'd0;
\mem$18 [400] = 32'd0;
\mem$18 [401] = 32'd0;
\mem$18 [402] = 32'd0;
\mem$18 [403] = 32'd0;
\mem$18 [404] = 32'd0;
\mem$18 [405] = 32'd0;
\mem$18 [406] = 32'd0;
\mem$18 [407] = 32'd0;
\mem$18 [408] = 32'd0;
\mem$18 [409] = 32'd0;
\mem$18 [410] = 32'd0;
\mem$18 [411] = 32'd0;
\mem$18 [412] = 32'd0;
\mem$18 [413] = 32'd0;
\mem$18 [414] = 32'd0;
\mem$18 [415] = 32'd0;
\mem$18 [416] = 32'd0;
\mem$18 [417] = 32'd0;
\mem$18 [418] = 32'd0;
\mem$18 [419] = 32'd0;
\mem$18 [420] = 32'd0;
\mem$18 [421] = 32'd0;
\mem$18 [422] = 32'd0;
\mem$18 [423] = 32'd0;
\mem$18 [424] = 32'd0;
\mem$18 [425] = 32'd0;
\mem$18 [426] = 32'd0;
\mem$18 [427] = 32'd0;
\mem$18 [428] = 32'd0;
\mem$18 [429] = 32'd0;
\mem$18 [430] = 32'd0;
\mem$18 [431] = 32'd0;
\mem$18 [432] = 32'd0;
\mem$18 [433] = 32'd0;
\mem$18 [434] = 32'd0;
\mem$18 [435] = 32'd0;
\mem$18 [436] = 32'd0;
\mem$18 [437] = 32'd0;
\mem$18 [438] = 32'd0;
\mem$18 [439] = 32'd0;
\mem$18 [440] = 32'd0;
\mem$18 [441] = 32'd0;
\mem$18 [442] = 32'd0;
\mem$18 [443] = 32'd0;
\mem$18 [444] = 32'd0;
\mem$18 [445] = 32'd0;
\mem$18 [446] = 32'd0;
\mem$18 [447] = 32'd0;
\mem$18 [448] = 32'd0;
\mem$18 [449] = 32'd0;
\mem$18 [450] = 32'd0;
\mem$18 [451] = 32'd0;
\mem$18 [452] = 32'd0;
\mem$18 [453] = 32'd0;
\mem$18 [454] = 32'd0;
\mem$18 [455] = 32'd0;
\mem$18 [456] = 32'd0;
\mem$18 [457] = 32'd0;
\mem$18 [458] = 32'd0;
\mem$18 [459] = 32'd0;
\mem$18 [460] = 32'd0;
\mem$18 [461] = 32'd0;
\mem$18 [462] = 32'd0;
\mem$18 [463] = 32'd0;
\mem$18 [464] = 32'd0;
\mem$18 [465] = 32'd0;
\mem$18 [466] = 32'd0;
\mem$18 [467] = 32'd0;
\mem$18 [468] = 32'd0;
\mem$18 [469] = 32'd0;
\mem$18 [470] = 32'd0;
\mem$18 [471] = 32'd0;
\mem$18 [472] = 32'd0;
\mem$18 [473] = 32'd0;
\mem$18 [474] = 32'd0;
\mem$18 [475] = 32'd0;
\mem$18 [476] = 32'd0;
\mem$18 [477] = 32'd0;
\mem$18 [478] = 32'd0;
\mem$18 [479] = 32'd0;
\mem$18 [480] = 32'd0;
\mem$18 [481] = 32'd0;
\mem$18 [482] = 32'd0;
\mem$18 [483] = 32'd0;
\mem$18 [484] = 32'd0;
\mem$18 [485] = 32'd0;
\mem$18 [486] = 32'd0;
\mem$18 [487] = 32'd0;
\mem$18 [488] = 32'd0;
\mem$18 [489] = 32'd0;
\mem$18 [490] = 32'd0;
\mem$18 [491] = 32'd0;
\mem$18 [492] = 32'd0;
\mem$18 [493] = 32'd0;
\mem$18 [494] = 32'd0;
\mem$18 [495] = 32'd0;
\mem$18 [496] = 32'd0;
\mem$18 [497] = 32'd0;
\mem$18 [498] = 32'd0;
\mem$18 [499] = 32'd0;
\mem$18 [500] = 32'd0;
\mem$18 [501] = 32'd0;
\mem$18 [502] = 32'd0;
\mem$18 [503] = 32'd0;
\mem$18 [504] = 32'd0;
\mem$18 [505] = 32'd0;
\mem$18 [506] = 32'd0;
\mem$18 [507] = 32'd0;
\mem$18 [508] = 32'd0;
\mem$18 [509] = 32'd0;
\mem$18 [510] = 32'd0;
\mem$18 [511] = 32'd0;
end
always @(posedge clk) begin
if (\mem_w_en$23 )
\mem$18 [\mem_w_addr$24 ] <= \mem_w_data$25 ;
end
reg [31:0] _2_;
always @(posedge clk) begin
if (\mem_r_en$20 ) begin
_2_ <= \mem$18 [\mem_r_addr$21 ];
end
end
assign \mem_r_data$22 = _2_;
reg [31:0] \mem$2 [511:0];
initial begin
\mem$2 [0] = 32'd0;
\mem$2 [1] = 32'd0;
\mem$2 [2] = 32'd0;
\mem$2 [3] = 32'd0;
\mem$2 [4] = 32'd0;
\mem$2 [5] = 32'd0;
\mem$2 [6] = 32'd0;
\mem$2 [7] = 32'd0;
\mem$2 [8] = 32'd0;
\mem$2 [9] = 32'd0;
\mem$2 [10] = 32'd0;
\mem$2 [11] = 32'd0;
\mem$2 [12] = 32'd0;
\mem$2 [13] = 32'd0;
\mem$2 [14] = 32'd0;
\mem$2 [15] = 32'd0;
\mem$2 [16] = 32'd0;
\mem$2 [17] = 32'd0;
\mem$2 [18] = 32'd0;
\mem$2 [19] = 32'd0;
\mem$2 [20] = 32'd0;
\mem$2 [21] = 32'd0;
\mem$2 [22] = 32'd0;
\mem$2 [23] = 32'd0;
\mem$2 [24] = 32'd0;
\mem$2 [25] = 32'd0;
\mem$2 [26] = 32'd0;
\mem$2 [27] = 32'd0;
\mem$2 [28] = 32'd0;
\mem$2 [29] = 32'd0;
\mem$2 [30] = 32'd0;
\mem$2 [31] = 32'd0;
\mem$2 [32] = 32'd0;
\mem$2 [33] = 32'd0;
\mem$2 [34] = 32'd0;
\mem$2 [35] = 32'd0;
\mem$2 [36] = 32'd0;
\mem$2 [37] = 32'd0;
\mem$2 [38] = 32'd0;
\mem$2 [39] = 32'd0;
\mem$2 [40] = 32'd0;
\mem$2 [41] = 32'd0;
\mem$2 [42] = 32'd0;
\mem$2 [43] = 32'd0;
\mem$2 [44] = 32'd0;
\mem$2 [45] = 32'd0;
\mem$2 [46] = 32'd0;
\mem$2 [47] = 32'd0;
\mem$2 [48] = 32'd0;
\mem$2 [49] = 32'd0;
\mem$2 [50] = 32'd0;
\mem$2 [51] = 32'd0;
\mem$2 [52] = 32'd0;
\mem$2 [53] = 32'd0;
\mem$2 [54] = 32'd0;
\mem$2 [55] = 32'd0;
\mem$2 [56] = 32'd0;
\mem$2 [57] = 32'd0;
\mem$2 [58] = 32'd0;
\mem$2 [59] = 32'd0;
\mem$2 [60] = 32'd0;
\mem$2 [61] = 32'd0;
\mem$2 [62] = 32'd0;
\mem$2 [63] = 32'd0;
\mem$2 [64] = 32'd0;
\mem$2 [65] = 32'd0;
\mem$2 [66] = 32'd0;
\mem$2 [67] = 32'd0;
\mem$2 [68] = 32'd0;
\mem$2 [69] = 32'd0;
\mem$2 [70] = 32'd0;
\mem$2 [71] = 32'd0;
\mem$2 [72] = 32'd0;
\mem$2 [73] = 32'd0;
\mem$2 [74] = 32'd0;
\mem$2 [75] = 32'd0;
\mem$2 [76] = 32'd0;
\mem$2 [77] = 32'd0;
\mem$2 [78] = 32'd0;
\mem$2 [79] = 32'd0;
\mem$2 [80] = 32'd0;
\mem$2 [81] = 32'd0;
\mem$2 [82] = 32'd0;
\mem$2 [83] = 32'd0;
\mem$2 [84] = 32'd0;
\mem$2 [85] = 32'd0;
\mem$2 [86] = 32'd0;
\mem$2 [87] = 32'd0;
\mem$2 [88] = 32'd0;
\mem$2 [89] = 32'd0;
\mem$2 [90] = 32'd0;
\mem$2 [91] = 32'd0;
\mem$2 [92] = 32'd0;
\mem$2 [93] = 32'd0;
\mem$2 [94] = 32'd0;
\mem$2 [95] = 32'd0;
\mem$2 [96] = 32'd0;
\mem$2 [97] = 32'd0;
\mem$2 [98] = 32'd0;
\mem$2 [99] = 32'd0;
\mem$2 [100] = 32'd0;
\mem$2 [101] = 32'd0;
\mem$2 [102] = 32'd0;
\mem$2 [103] = 32'd0;
\mem$2 [104] = 32'd0;
\mem$2 [105] = 32'd0;
\mem$2 [106] = 32'd0;
\mem$2 [107] = 32'd0;
\mem$2 [108] = 32'd0;
\mem$2 [109] = 32'd0;
\mem$2 [110] = 32'd0;
\mem$2 [111] = 32'd0;
\mem$2 [112] = 32'd0;
\mem$2 [113] = 32'd0;
\mem$2 [114] = 32'd0;
\mem$2 [115] = 32'd0;
\mem$2 [116] = 32'd0;
\mem$2 [117] = 32'd0;
\mem$2 [118] = 32'd0;
\mem$2 [119] = 32'd0;
\mem$2 [120] = 32'd0;
\mem$2 [121] = 32'd0;
\mem$2 [122] = 32'd0;
\mem$2 [123] = 32'd0;
\mem$2 [124] = 32'd0;
\mem$2 [125] = 32'd0;
\mem$2 [126] = 32'd0;
\mem$2 [127] = 32'd0;
\mem$2 [128] = 32'd0;
\mem$2 [129] = 32'd0;
\mem$2 [130] = 32'd0;
\mem$2 [131] = 32'd0;
\mem$2 [132] = 32'd0;
\mem$2 [133] = 32'd0;
\mem$2 [134] = 32'd0;
\mem$2 [135] = 32'd0;
\mem$2 [136] = 32'd0;
\mem$2 [137] = 32'd0;
\mem$2 [138] = 32'd0;
\mem$2 [139] = 32'd0;
\mem$2 [140] = 32'd0;
\mem$2 [141] = 32'd0;
\mem$2 [142] = 32'd0;
\mem$2 [143] = 32'd0;
\mem$2 [144] = 32'd0;
\mem$2 [145] = 32'd0;
\mem$2 [146] = 32'd0;
\mem$2 [147] = 32'd0;
\mem$2 [148] = 32'd0;
\mem$2 [149] = 32'd0;
\mem$2 [150] = 32'd0;
\mem$2 [151] = 32'd0;
\mem$2 [152] = 32'd0;
\mem$2 [153] = 32'd0;
\mem$2 [154] = 32'd0;
\mem$2 [155] = 32'd0;
\mem$2 [156] = 32'd0;
\mem$2 [157] = 32'd0;
\mem$2 [158] = 32'd0;
\mem$2 [159] = 32'd0;
\mem$2 [160] = 32'd0;
\mem$2 [161] = 32'd0;
\mem$2 [162] = 32'd0;
\mem$2 [163] = 32'd0;
\mem$2 [164] = 32'd0;
\mem$2 [165] = 32'd0;
\mem$2 [166] = 32'd0;
\mem$2 [167] = 32'd0;
\mem$2 [168] = 32'd0;
\mem$2 [169] = 32'd0;
\mem$2 [170] = 32'd0;
\mem$2 [171] = 32'd0;
\mem$2 [172] = 32'd0;
\mem$2 [173] = 32'd0;
\mem$2 [174] = 32'd0;
\mem$2 [175] = 32'd0;
\mem$2 [176] = 32'd0;
\mem$2 [177] = 32'd0;
\mem$2 [178] = 32'd0;
\mem$2 [179] = 32'd0;
\mem$2 [180] = 32'd0;
\mem$2 [181] = 32'd0;
\mem$2 [182] = 32'd0;
\mem$2 [183] = 32'd0;
\mem$2 [184] = 32'd0;
\mem$2 [185] = 32'd0;
\mem$2 [186] = 32'd0;
\mem$2 [187] = 32'd0;
\mem$2 [188] = 32'd0;
\mem$2 [189] = 32'd0;
\mem$2 [190] = 32'd0;
\mem$2 [191] = 32'd0;
\mem$2 [192] = 32'd0;
\mem$2 [193] = 32'd0;
\mem$2 [194] = 32'd0;
\mem$2 [195] = 32'd0;
\mem$2 [196] = 32'd0;
\mem$2 [197] = 32'd0;
\mem$2 [198] = 32'd0;
\mem$2 [199] = 32'd0;
\mem$2 [200] = 32'd0;
\mem$2 [201] = 32'd0;
\mem$2 [202] = 32'd0;
\mem$2 [203] = 32'd0;
\mem$2 [204] = 32'd0;
\mem$2 [205] = 32'd0;
\mem$2 [206] = 32'd0;
\mem$2 [207] = 32'd0;
\mem$2 [208] = 32'd0;
\mem$2 [209] = 32'd0;
\mem$2 [210] = 32'd0;
\mem$2 [211] = 32'd0;
\mem$2 [212] = 32'd0;
\mem$2 [213] = 32'd0;
\mem$2 [214] = 32'd0;
\mem$2 [215] = 32'd0;
\mem$2 [216] = 32'd0;
\mem$2 [217] = 32'd0;
\mem$2 [218] = 32'd0;
\mem$2 [219] = 32'd0;
\mem$2 [220] = 32'd0;
\mem$2 [221] = 32'd0;
\mem$2 [222] = 32'd0;
\mem$2 [223] = 32'd0;
\mem$2 [224] = 32'd0;
\mem$2 [225] = 32'd0;
\mem$2 [226] = 32'd0;
\mem$2 [227] = 32'd0;
\mem$2 [228] = 32'd0;
\mem$2 [229] = 32'd0;
\mem$2 [230] = 32'd0;
\mem$2 [231] = 32'd0;
\mem$2 [232] = 32'd0;
\mem$2 [233] = 32'd0;
\mem$2 [234] = 32'd0;
\mem$2 [235] = 32'd0;
\mem$2 [236] = 32'd0;
\mem$2 [237] = 32'd0;
\mem$2 [238] = 32'd0;
\mem$2 [239] = 32'd0;
\mem$2 [240] = 32'd0;
\mem$2 [241] = 32'd0;
\mem$2 [242] = 32'd0;
\mem$2 [243] = 32'd0;
\mem$2 [244] = 32'd0;
\mem$2 [245] = 32'd0;
\mem$2 [246] = 32'd0;
\mem$2 [247] = 32'd0;
\mem$2 [248] = 32'd0;
\mem$2 [249] = 32'd0;
\mem$2 [250] = 32'd0;
\mem$2 [251] = 32'd0;
\mem$2 [252] = 32'd0;
\mem$2 [253] = 32'd0;
\mem$2 [254] = 32'd0;
\mem$2 [255] = 32'd0;
\mem$2 [256] = 32'd0;
\mem$2 [257] = 32'd0;
\mem$2 [258] = 32'd0;
\mem$2 [259] = 32'd0;
\mem$2 [260] = 32'd0;
\mem$2 [261] = 32'd0;
\mem$2 [262] = 32'd0;
\mem$2 [263] = 32'd0;
\mem$2 [264] = 32'd0;
\mem$2 [265] = 32'd0;
\mem$2 [266] = 32'd0;
\mem$2 [267] = 32'd0;
\mem$2 [268] = 32'd0;
\mem$2 [269] = 32'd0;
\mem$2 [270] = 32'd0;
\mem$2 [271] = 32'd0;
\mem$2 [272] = 32'd0;
\mem$2 [273] = 32'd0;
\mem$2 [274] = 32'd0;
\mem$2 [275] = 32'd0;
\mem$2 [276] = 32'd0;
\mem$2 [277] = 32'd0;
\mem$2 [278] = 32'd0;
\mem$2 [279] = 32'd0;
\mem$2 [280] = 32'd0;
\mem$2 [281] = 32'd0;
\mem$2 [282] = 32'd0;
\mem$2 [283] = 32'd0;
\mem$2 [284] = 32'd0;
\mem$2 [285] = 32'd0;
\mem$2 [286] = 32'd0;
\mem$2 [287] = 32'd0;
\mem$2 [288] = 32'd0;
\mem$2 [289] = 32'd0;
\mem$2 [290] = 32'd0;
\mem$2 [291] = 32'd0;
\mem$2 [292] = 32'd0;
\mem$2 [293] = 32'd0;
\mem$2 [294] = 32'd0;
\mem$2 [295] = 32'd0;
\mem$2 [296] = 32'd0;
\mem$2 [297] = 32'd0;
\mem$2 [298] = 32'd0;
\mem$2 [299] = 32'd0;
\mem$2 [300] = 32'd0;
\mem$2 [301] = 32'd0;
\mem$2 [302] = 32'd0;
\mem$2 [303] = 32'd0;
\mem$2 [304] = 32'd0;
\mem$2 [305] = 32'd0;
\mem$2 [306] = 32'd0;
\mem$2 [307] = 32'd0;
\mem$2 [308] = 32'd0;
\mem$2 [309] = 32'd0;
\mem$2 [310] = 32'd0;
\mem$2 [311] = 32'd0;
\mem$2 [312] = 32'd0;
\mem$2 [313] = 32'd0;
\mem$2 [314] = 32'd0;
\mem$2 [315] = 32'd0;
\mem$2 [316] = 32'd0;
\mem$2 [317] = 32'd0;
\mem$2 [318] = 32'd0;
\mem$2 [319] = 32'd0;
\mem$2 [320] = 32'd0;
\mem$2 [321] = 32'd0;
\mem$2 [322] = 32'd0;
\mem$2 [323] = 32'd0;
\mem$2 [324] = 32'd0;
\mem$2 [325] = 32'd0;
\mem$2 [326] = 32'd0;
\mem$2 [327] = 32'd0;
\mem$2 [328] = 32'd0;
\mem$2 [329] = 32'd0;
\mem$2 [330] = 32'd0;
\mem$2 [331] = 32'd0;
\mem$2 [332] = 32'd0;
\mem$2 [333] = 32'd0;
\mem$2 [334] = 32'd0;
\mem$2 [335] = 32'd0;
\mem$2 [336] = 32'd0;
\mem$2 [337] = 32'd0;
\mem$2 [338] = 32'd0;
\mem$2 [339] = 32'd0;
\mem$2 [340] = 32'd0;
\mem$2 [341] = 32'd0;
\mem$2 [342] = 32'd0;
\mem$2 [343] = 32'd0;
\mem$2 [344] = 32'd0;
\mem$2 [345] = 32'd0;
\mem$2 [346] = 32'd0;
\mem$2 [347] = 32'd0;
\mem$2 [348] = 32'd0;
\mem$2 [349] = 32'd0;
\mem$2 [350] = 32'd0;
\mem$2 [351] = 32'd0;
\mem$2 [352] = 32'd0;
\mem$2 [353] = 32'd0;
\mem$2 [354] = 32'd0;
\mem$2 [355] = 32'd0;
\mem$2 [356] = 32'd0;
\mem$2 [357] = 32'd0;
\mem$2 [358] = 32'd0;
\mem$2 [359] = 32'd0;
\mem$2 [360] = 32'd0;
\mem$2 [361] = 32'd0;
\mem$2 [362] = 32'd0;
\mem$2 [363] = 32'd0;
\mem$2 [364] = 32'd0;
\mem$2 [365] = 32'd0;
\mem$2 [366] = 32'd0;
\mem$2 [367] = 32'd0;
\mem$2 [368] = 32'd0;
\mem$2 [369] = 32'd0;
\mem$2 [370] = 32'd0;
\mem$2 [371] = 32'd0;
\mem$2 [372] = 32'd0;
\mem$2 [373] = 32'd0;
\mem$2 [374] = 32'd0;
\mem$2 [375] = 32'd0;
\mem$2 [376] = 32'd0;
\mem$2 [377] = 32'd0;
\mem$2 [378] = 32'd0;
\mem$2 [379] = 32'd0;
\mem$2 [380] = 32'd0;
\mem$2 [381] = 32'd0;
\mem$2 [382] = 32'd0;
\mem$2 [383] = 32'd0;
\mem$2 [384] = 32'd0;
\mem$2 [385] = 32'd0;
\mem$2 [386] = 32'd0;
\mem$2 [387] = 32'd0;
\mem$2 [388] = 32'd0;
\mem$2 [389] = 32'd0;
\mem$2 [390] = 32'd0;
\mem$2 [391] = 32'd0;
\mem$2 [392] = 32'd0;
\mem$2 [393] = 32'd0;
\mem$2 [394] = 32'd0;
\mem$2 [395] = 32'd0;
\mem$2 [396] = 32'd0;
\mem$2 [397] = 32'd0;
\mem$2 [398] = 32'd0;
\mem$2 [399] = 32'd0;
\mem$2 [400] = 32'd0;
\mem$2 [401] = 32'd0;
\mem$2 [402] = 32'd0;
\mem$2 [403] = 32'd0;
\mem$2 [404] = 32'd0;
\mem$2 [405] = 32'd0;
\mem$2 [406] = 32'd0;
\mem$2 [407] = 32'd0;
\mem$2 [408] = 32'd0;
\mem$2 [409] = 32'd0;
\mem$2 [410] = 32'd0;
\mem$2 [411] = 32'd0;
\mem$2 [412] = 32'd0;
\mem$2 [413] = 32'd0;
\mem$2 [414] = 32'd0;
\mem$2 [415] = 32'd0;
\mem$2 [416] = 32'd0;
\mem$2 [417] = 32'd0;
\mem$2 [418] = 32'd0;
\mem$2 [419] = 32'd0;
\mem$2 [420] = 32'd0;
\mem$2 [421] = 32'd0;
\mem$2 [422] = 32'd0;
\mem$2 [423] = 32'd0;
\mem$2 [424] = 32'd0;
\mem$2 [425] = 32'd0;
\mem$2 [426] = 32'd0;
\mem$2 [427] = 32'd0;
\mem$2 [428] = 32'd0;
\mem$2 [429] = 32'd0;
\mem$2 [430] = 32'd0;
\mem$2 [431] = 32'd0;
\mem$2 [432] = 32'd0;
\mem$2 [433] = 32'd0;
\mem$2 [434] = 32'd0;
\mem$2 [435] = 32'd0;
\mem$2 [436] = 32'd0;
\mem$2 [437] = 32'd0;
\mem$2 [438] = 32'd0;
\mem$2 [439] = 32'd0;
\mem$2 [440] = 32'd0;
\mem$2 [441] = 32'd0;
\mem$2 [442] = 32'd0;
\mem$2 [443] = 32'd0;
\mem$2 [444] = 32'd0;
\mem$2 [445] = 32'd0;
\mem$2 [446] = 32'd0;
\mem$2 [447] = 32'd0;
\mem$2 [448] = 32'd0;
\mem$2 [449] = 32'd0;
\mem$2 [450] = 32'd0;
\mem$2 [451] = 32'd0;
\mem$2 [452] = 32'd0;
\mem$2 [453] = 32'd0;
\mem$2 [454] = 32'd0;
\mem$2 [455] = 32'd0;
\mem$2 [456] = 32'd0;
\mem$2 [457] = 32'd0;
\mem$2 [458] = 32'd0;
\mem$2 [459] = 32'd0;
\mem$2 [460] = 32'd0;
\mem$2 [461] = 32'd0;
\mem$2 [462] = 32'd0;
\mem$2 [463] = 32'd0;
\mem$2 [464] = 32'd0;
\mem$2 [465] = 32'd0;
\mem$2 [466] = 32'd0;
\mem$2 [467] = 32'd0;
\mem$2 [468] = 32'd0;
\mem$2 [469] = 32'd0;
\mem$2 [470] = 32'd0;
\mem$2 [471] = 32'd0;
\mem$2 [472] = 32'd0;
\mem$2 [473] = 32'd0;
\mem$2 [474] = 32'd0;
\mem$2 [475] = 32'd0;
\mem$2 [476] = 32'd0;
\mem$2 [477] = 32'd0;
\mem$2 [478] = 32'd0;
\mem$2 [479] = 32'd0;
\mem$2 [480] = 32'd0;
\mem$2 [481] = 32'd0;
\mem$2 [482] = 32'd0;
\mem$2 [483] = 32'd0;
\mem$2 [484] = 32'd0;
\mem$2 [485] = 32'd0;
\mem$2 [486] = 32'd0;
\mem$2 [487] = 32'd0;
\mem$2 [488] = 32'd0;
\mem$2 [489] = 32'd0;
\mem$2 [490] = 32'd0;
\mem$2 [491] = 32'd0;
\mem$2 [492] = 32'd0;
\mem$2 [493] = 32'd0;
\mem$2 [494] = 32'd0;
\mem$2 [495] = 32'd0;
\mem$2 [496] = 32'd0;
\mem$2 [497] = 32'd0;
\mem$2 [498] = 32'd0;
\mem$2 [499] = 32'd0;
\mem$2 [500] = 32'd0;
\mem$2 [501] = 32'd0;
\mem$2 [502] = 32'd0;
\mem$2 [503] = 32'd0;
\mem$2 [504] = 32'd0;
\mem$2 [505] = 32'd0;
\mem$2 [506] = 32'd0;
\mem$2 [507] = 32'd0;
\mem$2 [508] = 32'd0;
\mem$2 [509] = 32'd0;
\mem$2 [510] = 32'd0;
\mem$2 [511] = 32'd0;
end
always @(posedge clk) begin
if (\mem_w_en$7 )
\mem$2 [\mem_w_addr$8 ] <= \mem_w_data$9 ;
end
reg [31:0] _3_;
always @(posedge clk) begin
if (\mem_r_en$4 ) begin
_3_ <= \mem$2 [\mem_r_addr$5 ];
end
end
assign \mem_r_data$6 = _3_;
assign \$26 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *) write_enable;
assign \$28 = ! (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *) write_addr[1:0];
assign \$30 = write_enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *) \$28 ;
assign \$32 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *) write_enable;
assign \$34 = write_addr[1:0] == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *) 1'h1;
assign \$36 = write_enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *) \$34 ;
assign \$38 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *) write_enable;
assign \$40 = write_addr[1:0] == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *) 2'h2;
assign \$42 = write_enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *) \$40 ;
assign \$44 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:65" *) write_enable;
assign \$46 = write_addr[1:0] == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:72" *) 2'h3;
assign \$48 = write_enable & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/mem.py:71" *) \$46 ;
assign read_data = { \mem_r_data$22 , \mem_r_data$14 , \mem_r_data$6 , mem_r_data };
assign \mem_w_en$23 = \$48 ;
assign \mem_w_data$25 = write_data;
assign \mem_w_addr$24 = write_addr[10:2];
assign \mem_r_en$20 = \$44 ;
assign \mem_r_addr$21 = read_addr;
assign \mem_w_en$15 = \$42 ;
assign \mem_w_data$17 = write_data;
assign \mem_w_addr$16 = write_addr[10:2];
assign \mem_r_en$12 = \$38 ;
assign \mem_r_addr$13 = read_addr;
assign \mem_w_en$7 = \$36 ;
assign \mem_w_data$9 = write_data;
assign \mem_w_addr$8 = write_addr[10:2];
assign \mem_r_en$4 = \$32 ;
assign \mem_r_addr$5 = read_addr;
assign mem_w_en = \$30 ;
assign mem_w_data = write_data;
assign mem_w_addr = write_addr[10:2];
assign mem_r_en = \$26 ;
assign mem_r_addr = read_addr;
endmodule
(* \nmigen.hierarchy = "Cfu.op_store" *)
(* generator = "nMigen" *)
module op_store(write_data__multiplier, write_data__shift, write_enable, reset, read_data__bias, read_data__multiplier, read_data__shift, read_enable, rst, clk, write_data__bias);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:199" *)
wire [6:0] \$11 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:199" *)
wire [6:0] \$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:189" *)
wire [6:0] \$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:189" *)
wire [6:0] \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:191" *)
wire \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:196" *)
wire [6:0] \$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:196" *)
wire \$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:179" *)
wire [5:0] memory_r_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:179" *)
wire [51:0] memory_r_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:179" *)
wire memory_r_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:178" *)
wire [5:0] memory_w_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:178" *)
wire [51:0] memory_w_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:178" *)
wire memory_w_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:172" *)
output [15:0] read_data__bias;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:172" *)
output [31:0] read_data__multiplier;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:172" *)
output [3:0] read_data__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:171" *)
input read_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:183" *)
reg [5:0] read_index = 6'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:183" *)
reg [5:0] \read_index$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:168" *)
input reset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:170" *)
input [15:0] write_data__bias;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:170" *)
input [31:0] write_data__multiplier;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:170" *)
input [3:0] write_data__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:169" *)
input write_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:182" *)
reg [5:0] write_index = 6'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:182" *)
reg [5:0] \write_index$next ;
reg [51:0] memory [63:0];
initial begin
memory[0] = 52'h0000000000000;
memory[1] = 52'h0000000000000;
memory[2] = 52'h0000000000000;
memory[3] = 52'h0000000000000;
memory[4] = 52'h0000000000000;
memory[5] = 52'h0000000000000;
memory[6] = 52'h0000000000000;
memory[7] = 52'h0000000000000;
memory[8] = 52'h0000000000000;
memory[9] = 52'h0000000000000;
memory[10] = 52'h0000000000000;
memory[11] = 52'h0000000000000;
memory[12] = 52'h0000000000000;
memory[13] = 52'h0000000000000;
memory[14] = 52'h0000000000000;
memory[15] = 52'h0000000000000;
memory[16] = 52'h0000000000000;
memory[17] = 52'h0000000000000;
memory[18] = 52'h0000000000000;
memory[19] = 52'h0000000000000;
memory[20] = 52'h0000000000000;
memory[21] = 52'h0000000000000;
memory[22] = 52'h0000000000000;
memory[23] = 52'h0000000000000;
memory[24] = 52'h0000000000000;
memory[25] = 52'h0000000000000;
memory[26] = 52'h0000000000000;
memory[27] = 52'h0000000000000;
memory[28] = 52'h0000000000000;
memory[29] = 52'h0000000000000;
memory[30] = 52'h0000000000000;
memory[31] = 52'h0000000000000;
memory[32] = 52'h0000000000000;
memory[33] = 52'h0000000000000;
memory[34] = 52'h0000000000000;
memory[35] = 52'h0000000000000;
memory[36] = 52'h0000000000000;
memory[37] = 52'h0000000000000;
memory[38] = 52'h0000000000000;
memory[39] = 52'h0000000000000;
memory[40] = 52'h0000000000000;
memory[41] = 52'h0000000000000;
memory[42] = 52'h0000000000000;
memory[43] = 52'h0000000000000;
memory[44] = 52'h0000000000000;
memory[45] = 52'h0000000000000;
memory[46] = 52'h0000000000000;
memory[47] = 52'h0000000000000;
memory[48] = 52'h0000000000000;
memory[49] = 52'h0000000000000;
memory[50] = 52'h0000000000000;
memory[51] = 52'h0000000000000;
memory[52] = 52'h0000000000000;
memory[53] = 52'h0000000000000;
memory[54] = 52'h0000000000000;
memory[55] = 52'h0000000000000;
memory[56] = 52'h0000000000000;
memory[57] = 52'h0000000000000;
memory[58] = 52'h0000000000000;
memory[59] = 52'h0000000000000;
memory[60] = 52'h0000000000000;
memory[61] = 52'h0000000000000;
memory[62] = 52'h0000000000000;
memory[63] = 52'h0000000000000;
end
always @(posedge clk) begin
if (memory_w_en)
memory[memory_w_addr] <= memory_w_data;
end
reg [51:0] _0_;
always @(posedge clk) begin
if (memory_r_en) begin
_0_ <= memory[memory_r_addr];
end
end
assign memory_r_data = _0_;
assign \$9 = read_index == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:196" *) \$7 ;
assign \$12 = read_index + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:199" *) 1'h1;
assign \$3 = write_index + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:189" *) 1'h1;
assign \$5 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:191" *) write_enable;
assign \$7 = write_index - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:196" *) 1'h1;
always @(posedge clk)
read_index <= \read_index$next ;
always @(posedge clk)
write_index <= \write_index$next ;
always @* begin
if (\initial ) begin end
\write_index$next = write_index;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:188" *)
casez (write_enable)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:188" */
1'h1:
\write_index$next = \$3 [5:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:201" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:201" */
1'h1:
\write_index$next = 6'h00;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\write_index$next = 6'h00;
endcase
end
always @* begin
if (\initial ) begin end
\read_index$next = read_index;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:195" *)
casez (read_enable)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:195" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:196" *)
casez (\$9 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:196" */
1'h1:
\read_index$next = 6'h00;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:198" */
default:
\read_index$next = \$12 [5:0];
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:201" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:201" */
1'h1:
\read_index$next = 6'h00;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_index$next = 6'h00;
endcase
end
assign \$2 = \$3 ;
assign \$11 = \$12 ;
assign { read_data__shift, read_data__multiplier, read_data__bias } = memory_r_data;
assign memory_r_addr = read_index;
assign memory_r_en = \$5 ;
assign memory_w_data = { write_data__shift, write_data__multiplier, write_data__bias };
assign memory_w_addr = write_index;
assign memory_w_en = write_enable;
endmodule
(* \nmigen.hierarchy = "Cfu.operands_buffer" *)
(* generator = "nMigen" *)
module operands_buffer(payload, ready, \valid$1 , \payload$2 , \ready$3 , output__valid, output__payload__inputs, output__payload__filters, output__ready, rst, clk, valid);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:153" *)
wire \$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:153" *)
wire \$16 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$18 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$20 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$26 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$28 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$30 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$31 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$34 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$36 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:153" *)
wire \$38 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:140" *)
wire [127:0] \$4 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:153" *)
wire \$42 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$44 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$46 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$47 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$50 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$52 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$54 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$56 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$57 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:140" *)
wire [127:0] \$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
wire \$60 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$62 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:148" *)
wire \$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:146" *)
wire [1:0] \$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:133" *)
reg [127:0] buffered_filters = 128'h00000000000000000000000000000000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:133" *)
reg [127:0] \buffered_filters$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:133" *)
reg [127:0] buffered_inputs = 128'h00000000000000000000000000000000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:133" *)
reg [127:0] \buffered_inputs$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:129" *)
reg buffering_filters = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:129" *)
reg \buffering_filters$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:129" *)
reg buffering_inputs = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:129" *)
reg \buffering_inputs$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:123" *)
output [127:0] output__payload__filters;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:123" *)
output [127:0] output__payload__inputs;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:123" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:123" *)
output output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
input [127:0] payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
input [127:0] \payload$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
output ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
output \ready$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:124" *)
wire reset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
input valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:122" *)
input \valid$1 ;
assign \$9 = { \valid$1 , valid } | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:146" *) { buffering_filters, buffering_inputs };
assign \$8 = & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:148" *) \$9 ;
assign \$12 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:153" *) buffering_inputs;
assign \$14 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$16 = \$12 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:153" *) \$14 ;
assign \$18 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) buffering_inputs;
assign \$21 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$20 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) \$21 ;
assign \$24 = \$18 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) \$20 ;
assign \$26 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$28 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) buffering_inputs;
assign \$31 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$30 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) \$31 ;
assign \$34 = \$28 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) \$30 ;
assign \$36 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$38 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:153" *) buffering_filters;
assign \$40 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$42 = \$38 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:153" *) \$40 ;
assign \$44 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) buffering_filters;
assign \$47 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$46 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) \$47 ;
assign \$4 = buffering_inputs ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:140" *) buffered_inputs : payload;
assign \$50 = \$44 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) \$46 ;
assign \$52 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$54 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) buffering_filters;
assign \$57 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$56 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) \$57 ;
assign \$60 = \$54 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *) \$56 ;
assign \$62 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
assign \$6 = buffering_filters ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:140" *) buffered_filters : \payload$2 ;
always @(posedge clk)
buffered_filters <= \buffered_filters$next ;
always @(posedge clk)
buffering_filters <= \buffering_filters$next ;
always @(posedge clk)
buffered_inputs <= \buffered_inputs$next ;
always @(posedge clk)
buffering_inputs <= \buffering_inputs$next ;
always @* begin
if (\initial ) begin end
\buffering_inputs$next = buffering_inputs;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:156" *)
casez (valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:156" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
casez (\$24 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" */
1'h1:
\buffering_inputs$next = 1'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:164" */
default:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:165" *)
casez (\$26 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:165" */
1'h1:
\buffering_inputs$next = 1'h0;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:169" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:169" */
1'h1:
\buffering_inputs$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\buffering_inputs$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\buffered_inputs$next = buffered_inputs;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:156" *)
casez (valid)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:156" */
1'h1:
begin
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
casez (\$34 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" */
1'h1:
\buffered_inputs$next = payload;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:162" *)
casez (\$36 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:162" */
1'h1:
\buffered_inputs$next = payload;
endcase
end
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:169" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:169" */
1'h1:
\buffered_inputs$next = 128'h00000000000000000000000000000000;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\buffered_inputs$next = 128'h00000000000000000000000000000000;
endcase
end
always @* begin
if (\initial ) begin end
\buffering_filters$next = buffering_filters;
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:156" *)
casez (\valid$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:156" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
casez (\$50 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" */
1'h1:
\buffering_filters$next = 1'h1;
endcase
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:164" */
default:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:165" *)
casez (\$52 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:165" */
1'h1:
\buffering_filters$next = 1'h0;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:169" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:169" */
1'h1:
\buffering_filters$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\buffering_filters$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\buffered_filters$next = buffered_filters;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:156" *)
casez (\valid$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:156" */
1'h1:
begin
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" *)
casez (\$60 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:158" */
1'h1:
\buffered_filters$next = \payload$2 ;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:162" *)
casez (\$62 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:162" */
1'h1:
\buffered_filters$next = \payload$2 ;
endcase
end
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:169" *)
casez (reset)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/buffer.py:169" */
1'h1:
\buffered_filters$next = 128'h00000000000000000000000000000000;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\buffered_filters$next = 128'h00000000000000000000000000000000;
endcase
end
assign reset = 1'h0;
assign \ready$3 = \$42 ;
assign ready = \$16 ;
assign output__valid = \$8 ;
assign output__payload__filters = \$6 ;
assign output__payload__inputs = \$4 ;
endmodule
(* \nmigen.hierarchy = "Cfu.ping" *)
(* generator = "nMigen" *)
module ping(done, start, in0, in1, rst, clk, \output );
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:41" *)
wire [32:0] \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:41" *)
wire [32:0] \$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
output done;
reg done = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
reg \done$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
input [31:0] in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:54" *)
wire [31:0] in0s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
input [31:0] in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:55" *)
wire [31:0] in1s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
output [31:0] \output ;
reg [31:0] \output = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
reg [31:0] \output$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
input start;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:38" *)
reg [31:0] stored_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:38" *)
reg [31:0] \stored_value$next ;
assign \$2 = in0 + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:41" *) in1;
always @(posedge clk)
done <= \done$next ;
always @(posedge clk)
\output <= \output$next ;
always @(posedge clk)
stored_value <= \stored_value$next ;
always @* begin
if (\initial ) begin end
\stored_value$next = stored_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:39" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:39" */
1'h1:
\stored_value$next = \$2 [31:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\stored_value$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\output$next = \output ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:39" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:39" */
1'h1:
\output$next = stored_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:39" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:39" */
1'h1:
\done$next = 1'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:45" */
default:
\done$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\done$next = 1'h0;
endcase
end
assign \$1 = \$2 ;
assign in1s = in1;
assign in0s = in0;
endmodule
(* \nmigen.hierarchy = "Cfu.pp" *)
(* generator = "nMigen" *)
module pp(activation_min, activation_max, read_data__bias, read_data__multiplier, read_data__shift, read_enable, result__valid, result__payload, result__ready, \output , done, start, in0, in1, funct7, rst, clk, offset);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:403" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:403" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:368" *)
input [7:0] activation_max;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:367" *)
input [7:0] activation_min;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
output done;
reg done = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
reg \done$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:49" *)
wire [31:0] fifo_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:49" *)
wire fifo_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:49" *)
wire fifo_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:50" *)
wire [31:0] fifo_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:50" *)
wire fifo_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/fifo.py:50" *)
wire fifo_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
input [6:0] funct7;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:37" *)
wire [7:0] gearbox_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:37" *)
wire gearbox_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:37" *)
wire gearbox_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:38" *)
wire [31:0] gearbox_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:38" *)
wire gearbox_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/gearbox.py:38" *)
wire gearbox_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
input [31:0] in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:54" *)
wire [31:0] in0s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
input [31:0] in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:55" *)
wire [31:0] in1s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:366" *)
input [8:0] offset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:51" *)
output [31:0] \output ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:299" *)
wire [7:0] ppp_activation_max;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:298" *)
wire [7:0] ppp_activation_min;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:295" *)
reg [31:0] ppp_input__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:295" *)
reg [31:0] \ppp_input__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:295" *)
reg ppp_input__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:295" *)
reg \ppp_input__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:297" *)
wire [8:0] ppp_offset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:296" *)
wire [7:0] ppp_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:296" *)
wire ppp_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:296" *)
wire ppp_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:300" *)
wire [15:0] ppp_read_data__bias;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:300" *)
wire [31:0] ppp_read_data__multiplier;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:300" *)
wire [3:0] ppp_read_data__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:301" *)
wire ppp_read_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:369" *)
input [15:0] read_data__bias;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:369" *)
input [31:0] read_data__multiplier;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:369" *)
input [3:0] read_data__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:370" *)
output read_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:371" *)
output [31:0] result__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:371" *)
input result__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:371" *)
output result__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
input start;
assign \$1 = funct7 == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:403" *) 2'h3;
assign \$3 = funct7 == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:403" *) 2'h3;
always @(posedge clk)
done <= \done$next ;
always @(posedge clk)
ppp_input__payload <= \ppp_input__payload$next ;
always @(posedge clk)
ppp_input__valid <= \ppp_input__valid$next ;
fifo fifo (
.clk(clk),
.input__payload(fifo_input__payload),
.input__ready(fifo_input__ready),
.input__valid(fifo_input__valid),
.output__payload(fifo_output__payload),
.output__ready(fifo_output__ready),
.output__valid(fifo_output__valid),
.rst(rst)
);
gearbox gearbox (
.clk(clk),
.input__payload(gearbox_input__payload),
.input__ready(gearbox_input__ready),
.input__valid(gearbox_input__valid),
.output__payload(gearbox_output__payload),
.output__ready(gearbox_output__ready),
.output__valid(gearbox_output__valid),
.rst(rst)
);
ppp ppp (
.activation_max(ppp_activation_max),
.activation_min(ppp_activation_min),
.clk(clk),
.input__payload(ppp_input__payload),
.input__valid(ppp_input__valid),
.offset(ppp_offset),
.output__payload(ppp_output__payload),
.output__ready(ppp_output__ready),
.output__valid(ppp_output__valid),
.read_data__bias(ppp_read_data__bias),
.read_data__multiplier(ppp_read_data__multiplier),
.read_data__shift(ppp_read_data__shift),
.read_enable(ppp_read_enable),
.rst(rst)
);
always @* begin
if (\initial ) begin end
\done$next = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:402" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:402" */
1'h1:
\done$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\done$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\ppp_input__valid$next = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:402" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:402" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:403" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:403" */
1'h1:
\ppp_input__valid$next = 1'h1;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\ppp_input__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\ppp_input__payload$next = ppp_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:402" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:402" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:403" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:403" */
1'h1:
\ppp_input__payload$next = in0s;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\ppp_input__payload$next = 32'd0;
endcase
end
assign in1s = in1;
assign in0s = in0;
assign \output = 32'd0;
assign fifo_output__ready = result__ready;
assign result__payload = fifo_output__payload;
assign result__valid = fifo_output__valid;
assign gearbox_output__ready = fifo_input__ready;
assign fifo_input__payload = gearbox_output__payload;
assign fifo_input__valid = gearbox_output__valid;
assign gearbox_input__payload = ppp_output__payload;
assign gearbox_input__valid = ppp_output__valid;
assign read_enable = ppp_read_enable;
assign { ppp_read_data__shift, ppp_read_data__multiplier, ppp_read_data__bias } = { read_data__shift, read_data__multiplier, read_data__bias };
assign ppp_activation_max = activation_max;
assign ppp_activation_min = activation_min;
assign ppp_offset = offset;
assign ppp_output__ready = gearbox_input__ready;
endmodule
(* \nmigen.hierarchy = "Cfu.pp.ppp" *)
(* generator = "nMigen" *)
module ppp(clk, output__ready, offset, activation_min, activation_max, read_data__bias, read_data__multiplier, read_data__shift, read_enable, output__valid, output__payload, input__valid, input__payload, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:316" *)
wire [32:0] \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:316" *)
wire [32:0] \$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:297" *)
wire [15:0] \$4 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:299" *)
input [7:0] activation_max;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:298" *)
input [7:0] activation_min;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:295" *)
input [31:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:295" *)
wire input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:295" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:297" *)
input [8:0] offset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:296" *)
output [7:0] output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:296" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:296" *)
output output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire [31:0] rdbpot_input__payload__dividend;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire [3:0] rdbpot_input__payload__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire rdbpot_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire rdbpot_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire [31:0] rdbpot_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire rdbpot_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire rdbpot_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:300" *)
input [15:0] read_data__bias;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:300" *)
input [31:0] read_data__multiplier;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:300" *)
input [3:0] read_data__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:258" *)
reg [3:0] read_data__shift_delay_0 = 4'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:258" *)
reg [3:0] \read_data__shift_delay_0$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:258" *)
reg [3:0] read_data__shift_delay_1 = 4'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:258" *)
reg [3:0] \read_data__shift_delay_1$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:258" *)
reg [3:0] read_data__shift_delay_2 = 4'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:258" *)
reg [3:0] \read_data__shift_delay_2$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:301" *)
output read_enable;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire [15:0] sap_input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire sap_input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire sap_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:230" *)
wire [7:0] sap_max;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:231" *)
wire [7:0] sap_min;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:229" *)
wire [15:0] sap_offset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire [7:0] sap_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire sap_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire sap_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire [31:0] srdhm_input__payload__a;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire [31:0] srdhm_input__payload__b;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire srdhm_input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire [31:0] srdhm_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire srdhm_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
wire srdhm_output__valid;
assign \$2 = $signed(input__payload) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:316" *) $signed(read_data__bias);
assign \$4 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:297" *) $signed(offset);
always @(posedge clk)
read_data__shift_delay_2 <= \read_data__shift_delay_2$next ;
always @(posedge clk)
read_data__shift_delay_1 <= \read_data__shift_delay_1$next ;
always @(posedge clk)
read_data__shift_delay_0 <= \read_data__shift_delay_0$next ;
rdbpot rdbpot (
.clk(clk),
.input__payload__dividend(rdbpot_input__payload__dividend),
.input__payload__shift(rdbpot_input__payload__shift),
.input__ready(rdbpot_input__ready),
.input__valid(rdbpot_input__valid),
.output__payload(rdbpot_output__payload),
.output__ready(rdbpot_output__ready),
.output__valid(rdbpot_output__valid),
.rst(rst)
);
sap sap (
.clk(clk),
.input__payload(sap_input__payload),
.input__ready(sap_input__ready),
.input__valid(sap_input__valid),
.max(sap_max),
.min(sap_min),
.offset(sap_offset),
.output__payload(sap_output__payload),
.output__ready(sap_output__ready),
.output__valid(sap_output__valid),
.rst(rst)
);
srdhm srdhm (
.clk(clk),
.input__payload__a(srdhm_input__payload__a),
.input__payload__b(srdhm_input__payload__b),
.input__valid(srdhm_input__valid),
.output__payload(srdhm_output__payload),
.output__ready(srdhm_output__ready),
.output__valid(srdhm_output__valid),
.rst(rst)
);
always @* begin
if (\initial ) begin end
\read_data__shift_delay_0$next = read_data__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_data__shift_delay_0$next = 4'h0;
endcase
end
always @* begin
if (\initial ) begin end
\read_data__shift_delay_1$next = read_data__shift_delay_0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_data__shift_delay_1$next = 4'h0;
endcase
end
always @* begin
if (\initial ) begin end
\read_data__shift_delay_2$next = read_data__shift_delay_1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\read_data__shift_delay_2$next = 4'h0;
endcase
end
assign \$1 = \$2 ;
assign sap_output__ready = output__ready;
assign output__payload = sap_output__payload;
assign output__valid = sap_output__valid;
assign sap_max = activation_max;
assign sap_min = activation_min;
assign sap_offset = \$4 ;
assign rdbpot_output__ready = sap_input__ready;
assign sap_input__payload = rdbpot_output__payload[15:0];
assign sap_input__valid = rdbpot_output__valid;
assign rdbpot_input__payload__shift = read_data__shift_delay_2;
assign rdbpot_input__payload__dividend = srdhm_output__payload;
assign rdbpot_input__valid = srdhm_output__valid;
assign srdhm_output__ready = rdbpot_input__ready;
assign read_enable = input__valid;
assign srdhm_input__payload__b = read_data__multiplier;
assign srdhm_input__payload__a = \$2 [31:0];
assign srdhm_input__valid = input__valid;
assign input__ready = 1'h1;
endmodule
(* \nmigen.hierarchy = "Cfu.pp.ppp.rdbpot" *)
(* generator = "nMigen" *)
module rdbpot(clk, input__ready, input__valid, input__payload__dividend, input__payload__shift, output__valid, output__payload, output__ready, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *)
wire [31:0] \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:131" *)
wire [31:0] \$101 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:131" *)
wire [31:0] \$103 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:131" *)
wire [31:0] \$105 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:131" *)
wire [31:0] \$107 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:132" *)
wire [32:0] \$109 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *)
wire [31:0] \$11 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:132" *)
wire [31:0] \$110 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:132" *)
wire \$111 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:132" *)
wire \$112 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:132" *)
wire [32:0] \$116 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *)
wire [31:0] \$13 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *)
wire [31:0] \$15 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *)
wire [31:0] \$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [31:0] \$19 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$20 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [2:0] \$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [31:0] \$27 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$28 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$29 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *)
wire [31:0] \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [3:0] \$32 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [31:0] \$35 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$36 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$37 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [4:0] \$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [31:0] \$43 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$44 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$45 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [5:0] \$48 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *)
wire [31:0] \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [31:0] \$51 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$52 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$53 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [6:0] \$56 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [31:0] \$59 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$60 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$61 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [7:0] \$64 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [31:0] \$67 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$68 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$69 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *)
wire [31:0] \$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [8:0] \$72 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [31:0] \$75 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$76 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$77 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [9:0] \$80 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [31:0] \$83 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$84 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *)
wire \$85 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *)
wire [10:0] \$88 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *)
wire [31:0] \$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:131" *)
wire [31:0] \$91 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:131" *)
wire [31:0] \$93 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:131" *)
wire [31:0] \$95 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:131" *)
wire [31:0] \$97 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:131" *)
wire [31:0] \$99 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:113" *)
reg [31:0] dividend = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:113" *)
reg [31:0] \dividend$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input [31:0] input__payload__dividend;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input [3:0] input__payload__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
output input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:122" *)
reg [31:0] quotient;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:120" *)
reg [31:0] remainder;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:119" *)
reg [31:0] result = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:119" *)
reg [31:0] \result$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:114" *)
reg [3:0] shift = 4'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:114" *)
reg [3:0] \shift$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:127" *)
reg [2:0] sr = 3'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:127" *)
reg [2:0] \sr$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:121" *)
reg [31:0] threshold;
assign \$9 = $signed(dividend) & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *) $signed(32'd127);
assign \$112 = $signed(remainder) > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:132" *) $signed(threshold);
assign \$111 = \$112 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:132" *) 1'h1 : 1'h0;
assign \$110 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:132" *) \$111 ;
assign \$116 = $signed(quotient) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:132" *) $signed(\$110 );
assign \$11 = $signed(dividend) & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *) $signed(32'd255);
assign \$13 = $signed(dividend) & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *) $signed(32'd511);
assign \$15 = $signed(dividend) & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *) $signed(32'd1023);
assign \$17 = $signed(dividend) & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *) $signed(32'd2047);
assign \$1 = $signed(dividend) & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *) $signed(32'd7);
assign \$21 = $signed(dividend) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) $signed(32'd0);
assign \$20 = \$21 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) 1'h1 : 1'h0;
assign \$24 = 2'h3 + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$20 ;
assign \$19 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$24 ;
assign \$29 = $signed(dividend) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) $signed(32'd0);
assign \$28 = \$29 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) 1'h1 : 1'h0;
assign \$32 = 3'h7 + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$28 ;
assign \$27 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$32 ;
assign \$37 = $signed(dividend) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) $signed(32'd0);
assign \$36 = \$37 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) 1'h1 : 1'h0;
assign \$3 = $signed(dividend) & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *) $signed(32'd15);
assign \$40 = 4'hf + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$36 ;
assign \$35 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$40 ;
assign \$45 = $signed(dividend) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) $signed(32'd0);
assign \$44 = \$45 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) 1'h1 : 1'h0;
assign \$48 = 5'h1f + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$44 ;
assign \$43 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$48 ;
assign \$53 = $signed(dividend) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) $signed(32'd0);
assign \$52 = \$53 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) 1'h1 : 1'h0;
assign \$56 = 6'h3f + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$52 ;
assign \$51 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$56 ;
assign \$5 = $signed(dividend) & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *) $signed(32'd31);
assign \$61 = $signed(dividend) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) $signed(32'd0);
assign \$60 = \$61 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) 1'h1 : 1'h0;
assign \$64 = 7'h7f + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$60 ;
assign \$59 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$64 ;
assign \$69 = $signed(dividend) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) $signed(32'd0);
assign \$68 = \$69 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) 1'h1 : 1'h0;
assign \$72 = 8'hff + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$68 ;
assign \$67 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$72 ;
assign \$77 = $signed(dividend) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) $signed(32'd0);
assign \$76 = \$77 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) 1'h1 : 1'h0;
assign \$7 = $signed(dividend) & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:128" *) $signed(32'd63);
assign \$80 = 9'h1ff + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$76 ;
assign \$75 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$80 ;
assign \$85 = $signed(dividend) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) $signed(32'd0);
assign \$84 = \$85 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:130" *) 1'h1 : 1'h0;
assign \$88 = 10'h3ff + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$84 ;
assign \$83 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:129" *) \$88 ;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
result <= \result$next ;
always @(posedge clk)
shift <= \shift$next ;
always @(posedge clk)
dividend <= \dividend$next ;
always @(posedge clk)
sr <= \sr$next ;
always @* begin
if (\initial ) begin end
\sr$next = { sr[1:0], input__valid };
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\sr$next = 3'h0;
endcase
end
always @* begin
if (\initial ) begin end
\dividend$next = input__payload__dividend;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\dividend$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\shift$next = input__payload__shift;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\shift$next = 4'h0;
endcase
end
always @* begin
if (\initial ) begin end
remainder = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:124" *)
casez (shift)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h3:
remainder = \$1 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h4:
remainder = \$3 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h5:
remainder = \$5 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h6:
remainder = \$7 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h7:
remainder = \$9 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h8:
remainder = \$11 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h9:
remainder = \$13 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'ha:
remainder = \$15 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'hb:
remainder = \$17 ;
endcase
end
always @* begin
if (\initial ) begin end
threshold = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:124" *)
casez (shift)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h3:
threshold = \$19 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h4:
threshold = \$27 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h5:
threshold = \$35 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h6:
threshold = \$43 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h7:
threshold = \$51 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h8:
threshold = \$59 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h9:
threshold = \$67 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'ha:
threshold = \$75 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'hb:
threshold = \$83 ;
endcase
end
always @* begin
if (\initial ) begin end
quotient = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:124" *)
casez (shift)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h3:
quotient = \$91 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h4:
quotient = \$93 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h5:
quotient = \$95 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h6:
quotient = \$97 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h7:
quotient = \$99 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h8:
quotient = \$101 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'h9:
quotient = \$103 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'ha:
quotient = \$105 ;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:126" */
4'hb:
quotient = \$107 ;
endcase
end
always @* begin
if (\initial ) begin end
\result$next = \$116 [31:0];
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\result$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = result;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
assign \$109 = \$116 ;
assign output__valid = sr[2];
assign input__ready = output__ready;
assign \$91 = { dividend[31], dividend[31], dividend[31], dividend[31:3] };
assign \$95 = { dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31:5] };
assign \$93 = { dividend[31], dividend[31], dividend[31], dividend[31], dividend[31:4] };
assign \$97 = { dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31:6] };
assign \$101 = { dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31:8] };
assign \$105 = { dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31:10] };
assign \$103 = { dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31:9] };
assign \$107 = { dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31:11] };
assign \$99 = { dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31], dividend[31:7] };
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_01" *)
(* generator = "nMigen" *)
module reg_01(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_02" *)
(* generator = "nMigen" *)
module reg_02(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_03" *)
(* generator = "nMigen" *)
module reg_03(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_04" *)
(* generator = "nMigen" *)
module reg_04(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_05" *)
(* generator = "nMigen" *)
module reg_05(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_06" *)
(* generator = "nMigen" *)
module reg_06(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_07" *)
(* generator = "nMigen" *)
module reg_07(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_08" *)
(* generator = "nMigen" *)
module reg_08(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_1f" *)
(* generator = "nMigen" *)
module reg_1f(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.get.reg_30" *)
(* generator = "nMigen" *)
module reg_30(clk, input__valid, input__payload, input__ready, invalidate, valid, value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:72" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
input [31:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
output input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:64" *)
input invalidate;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:65" *)
output valid;
reg valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:65" *)
reg \valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:66" *)
output [31:0] value;
reg [31:0] value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:66" *)
reg [31:0] \value$next ;
assign \$1 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:72" *) valid;
assign \$3 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
assign \$5 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
always @(posedge clk)
value <= \value$next ;
always @(posedge clk)
valid <= \valid$next ;
always @* begin
if (\initial ) begin end
\valid$next = valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:73" *)
casez (invalidate)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:73" */
1'h1:
\valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" */
1'h1:
\valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\value$next = value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" *)
casez (\$5 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" */
1'h1:
\value$next = input__payload;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\value$next = 32'd0;
endcase
end
assign input__ready = \$1 ;
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_40" *)
(* generator = "nMigen" *)
module reg_40(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_41" *)
(* generator = "nMigen" *)
module reg_41(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_42" *)
(* generator = "nMigen" *)
module reg_42(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_43" *)
(* generator = "nMigen" *)
module reg_43(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.get.reg_44" *)
(* generator = "nMigen" *)
module reg_44(clk, input__valid, input__payload, input__ready, invalidate, valid, value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:72" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
input [31:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
output input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:64" *)
input invalidate;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:65" *)
output valid;
reg valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:65" *)
reg \valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:66" *)
output [31:0] value;
reg [31:0] value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:66" *)
reg [31:0] \value$next ;
assign \$1 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:72" *) valid;
assign \$3 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
assign \$5 = input__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) input__ready;
always @(posedge clk)
value <= \value$next ;
always @(posedge clk)
valid <= \valid$next ;
always @* begin
if (\initial ) begin end
\valid$next = valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:73" *)
casez (invalidate)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:73" */
1'h1:
\valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" */
1'h1:
\valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\value$next = value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" *)
casez (\$5 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" */
1'h1:
\value$next = input__payload;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\value$next = 32'd0;
endcase
end
assign input__ready = \$1 ;
endmodule
(* \nmigen.hierarchy = "Cfu.set.reg_70" *)
(* generator = "nMigen" *)
module reg_70(clk, output__valid, output__payload, output__ready, new_en, new_value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
input new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
input [31:0] new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
output output__valid;
reg output__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
reg \output__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$1 = output__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) output__ready;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
output__valid <= \output__valid$next ;
always @* begin
if (\initial ) begin end
\output__valid$next = output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:53" */
1'h1:
\output__valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__valid$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" *)
casez (new_en)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:56" */
1'h1:
\output__payload$next = new_value;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
endmodule
(* \nmigen.hierarchy = "Cfu.get.reg_70" *)
(* generator = "nMigen" *)
module \reg_70$1 (clk, input__valid, input__payload, input__ready, invalidate, valid, value, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
input [31:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
output input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:63" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:64" *)
input invalidate;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:65" *)
output valid;
reg valid = 1'h1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:65" *)
reg \valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:66" *)
output [31:0] value;
reg [31:0] value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:66" *)
reg [31:0] \value$next ;
always @(posedge clk)
value <= \value$next ;
always @(posedge clk)
valid <= \valid$next ;
always @* begin
if (\initial ) begin end
\valid$next = valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:73" *)
casez (invalidate)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:73" */
1'h1:
\valid$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" */
1'h1:
\valid$next = 1'h1;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\valid$next = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
\value$next = value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/get.py:75" */
1'h1:
\value$next = input__payload;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\value$next = 32'd0;
endcase
end
assign input__ready = 1'h1;
assign \$1 = input__valid;
assign \$3 = input__valid;
endmodule
(* \nmigen.hierarchy = "Cfu.result_accumulator" *)
(* generator = "nMigen" *)
module result_accumulator(results__payload, results__ready, num_results__payload, num_results__valid, accumulated__valid, accumulated__payload, accumulated__ready, rst, clk, results__valid);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:99" *)
wire \$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$16 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$18 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:97" *)
wire [32:0] \$20 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:97" *)
wire [32:0] \$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$23 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:99" *)
wire \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:100" *)
wire [32:0] \$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:100" *)
wire [32:0] \$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:83" *)
output [31:0] accumulated__payload;
reg [31:0] accumulated__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:83" *)
reg [31:0] \accumulated__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:83" *)
input accumulated__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:83" *)
output accumulated__valid;
reg accumulated__valid = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:83" *)
reg \accumulated__valid$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:87" *)
reg [31:0] accumulator = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:87" *)
reg [31:0] \accumulator$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:88" *)
reg [1:0] fsm_state = 2'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:88" *)
reg [1:0] \fsm_state$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:81" *)
input [31:0] num_results__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:81" *)
reg num_results__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:81" *)
input num_results__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:82" *)
input [31:0] results__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:82" *)
output results__ready;
reg results__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:82" *)
input results__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:86" *)
reg [31:0] results_counter = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:86" *)
reg [31:0] \results_counter$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
assign \$10 = num_results__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) num_results__ready;
assign \$12 = results__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) results__ready;
assign \$14 = results_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:99" *) 1'h1;
assign \$16 = accumulated__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) accumulated__ready;
assign \$18 = results__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) results__ready;
assign \$1 = num_results__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) num_results__ready;
assign \$21 = $signed(accumulator) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:97" *) $signed(results__payload);
assign \$23 = accumulated__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) accumulated__ready;
assign \$3 = results__valid & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/stream.py:98" *) results__ready;
assign \$5 = results_counter > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:99" *) 1'h1;
assign \$8 = results_counter - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:100" *) 1'h1;
always @(posedge clk)
accumulated__valid <= \accumulated__valid$next ;
always @(posedge clk)
accumulated__payload <= \accumulated__payload$next ;
always @(posedge clk)
accumulator <= \accumulator$next ;
always @(posedge clk)
fsm_state <= \fsm_state$next ;
always @(posedge clk)
results_counter <= \results_counter$next ;
always @* begin
if (\initial ) begin end
num_results__ready = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:88" *)
casez (fsm_state)
/* \nmigen.decoding = "IDLE/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:89" */
2'h0:
num_results__ready = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
\results_counter$next = results_counter;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:88" *)
casez (fsm_state)
/* \nmigen.decoding = "IDLE/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:89" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:91" *)
casez (\$1 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:91" */
1'h1:
\results_counter$next = num_results__payload;
endcase
/* \nmigen.decoding = "ACCUMULATING/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:94" */
2'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:96" *)
casez (\$3 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:96" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:99" *)
casez (\$5 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:99" */
1'h1:
\results_counter$next = \$8 [31:0];
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:101" */
default:
\results_counter$next = 32'd0;
endcase
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\results_counter$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\fsm_state$next = fsm_state;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:88" *)
casez (fsm_state)
/* \nmigen.decoding = "IDLE/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:89" */
2'h0:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:91" *)
casez (\$10 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:91" */
1'h1:
\fsm_state$next = 2'h1;
endcase
/* \nmigen.decoding = "ACCUMULATING/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:94" */
2'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:96" *)
casez (\$12 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:96" */
1'h1:
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:99" *)
casez (\$14 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:99" */
1'h1:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:101" */
default:
\fsm_state$next = 2'h2;
endcase
endcase
/* \nmigen.decoding = "DONE/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:104" */
2'h2:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:108" *)
casez (\$16 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:108" */
1'h1:
\fsm_state$next = 2'h0;
endcase
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\fsm_state$next = 2'h0;
endcase
end
always @* begin
if (\initial ) begin end
results__ready = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:88" *)
casez (fsm_state)
/* \nmigen.decoding = "IDLE/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:89" */
2'h0:
/* empty */;
/* \nmigen.decoding = "ACCUMULATING/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:94" */
2'h1:
results__ready = 1'h1;
endcase
end
always @* begin
if (\initial ) begin end
\accumulator$next = accumulator;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:88" *)
casez (fsm_state)
/* \nmigen.decoding = "IDLE/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:89" */
2'h0:
/* empty */;
/* \nmigen.decoding = "ACCUMULATING/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:94" */
2'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:96" *)
casez (\$18 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:96" */
1'h1:
\accumulator$next = \$21 [31:0];
endcase
/* \nmigen.decoding = "DONE/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:104" */
2'h2:
\accumulator$next = 32'd0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\accumulator$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\accumulated__payload$next = accumulated__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:88" *)
casez (fsm_state)
/* \nmigen.decoding = "IDLE/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:89" */
2'h0:
/* empty */;
/* \nmigen.decoding = "ACCUMULATING/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:94" */
2'h1:
/* empty */;
/* \nmigen.decoding = "DONE/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:104" */
2'h2:
\accumulated__payload$next = accumulator;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\accumulated__payload$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\accumulated__valid$next = accumulated__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:88" *)
casez (fsm_state)
/* \nmigen.decoding = "IDLE/0" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:89" */
2'h0:
/* empty */;
/* \nmigen.decoding = "ACCUMULATING/1" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:94" */
2'h1:
/* empty */;
/* \nmigen.decoding = "DONE/2" */
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:104" */
2'h2:
begin
\accumulated__valid$next = 1'h1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:108" *)
casez (\$23 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/hps_cfu.py:108" */
1'h1:
\accumulated__valid$next = 1'h0;
endcase
end
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\accumulated__valid$next = 1'h0;
endcase
end
assign \$7 = \$8 ;
assign \$20 = \$21 ;
endmodule
(* \nmigen.hierarchy = "Cfu.pp.ppp.sap" *)
(* generator = "nMigen" *)
module sap(clk, input__valid, input__payload, input__ready, offset, min, max, output__valid, output__payload, output__ready, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:236" *)
wire [31:0] \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:236" *)
wire [16:0] \$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:237" *)
wire \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:239" *)
wire \$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input [15:0] input__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
output input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:230" *)
input [7:0] max;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:231" *)
input [7:0] min;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:229" *)
input [15:0] offset;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output [7:0] output__payload;
reg [7:0] output__payload = 8'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
reg [7:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:127" *)
reg sr = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:127" *)
reg \sr$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:235" *)
wire [31:0] with_offset;
assign \$2 = $signed(input__payload) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:236" *) $signed(offset);
assign \$1 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:236" *) $signed(\$2 );
assign \$5 = $signed(with_offset) > (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:237" *) $signed(max);
assign \$7 = $signed(with_offset) < (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:239" *) $signed(min);
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
sr <= \sr$next ;
always @* begin
if (\initial ) begin end
\sr$next = input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\sr$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:237" *)
casez ({ \$7 , \$5 })
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:237" */
2'b?1:
\output__payload$next = max;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:239" */
2'b1?:
\output__payload$next = min;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:241" */
default:
\output__payload$next = with_offset[7:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 8'h00;
endcase
end
assign with_offset = \$1 ;
assign output__valid = sr;
assign input__ready = output__ready;
endmodule
(* \nmigen.hierarchy = "Cfu.set" *)
(* generator = "nMigen" *)
module set(payload, ready, \valid$1 , \payload$2 , \ready$3 , \valid$4 , \payload$5 , \ready$6 , \valid$7 , \payload$8 , \ready$9 , \valid$10 , \payload$11 , \ready$12 , \$signal , \payload$13 , \valid$14 , \ready$15 , \$signal$16 , \$signal$17 , \$signal$18
, \$signal$19 , \$signal$20 , \$signal$21 , \$signal$22 , \$signal$23 , done, start, in0, in1, funct7, rst, clk, valid);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
output [31:0] \$signal ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
output [31:0] \$signal$16 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
output [31:0] \$signal$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
output [31:0] \$signal$18 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
output \$signal$19 ;
reg \$signal$19 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
output \$signal$20 ;
reg \$signal$20 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
output [31:0] \$signal$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
output [31:0] \$signal$22 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
output [31:0] \$signal$23 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \$signal$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$25 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \$signal$26 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$27 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$31 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \$signal$32 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$33 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \$signal$34 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$35 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$39 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$43 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$47 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \$signal$48 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$49 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \$signal$50 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$51 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:102" *)
wire [31:0] \$signal$55 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$59 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:103" *)
reg \$signal$63 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
output done;
reg done = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:53" *)
reg \done$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:50" *)
input [6:0] funct7;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:48" *)
input [31:0] in0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:54" *)
wire [31:0] in0s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:49" *)
input [31:0] in1;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:55" *)
wire [31:0] in1s;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output [31:0] payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output [31:0] \payload$11 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output [31:0] \payload$13 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output [31:0] \payload$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \payload$29 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \payload$37 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \payload$41 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \payload$45 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output [31:0] \payload$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \payload$53 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \payload$57 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \payload$61 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire [31:0] \payload$65 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output [31:0] \payload$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
input ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
input \ready$12 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
input \ready$15 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
input \ready$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \ready$30 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \ready$38 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \ready$42 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \ready$46 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \ready$54 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \ready$58 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
input \ready$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \ready$62 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \ready$66 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
input \ready$9 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_01_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_01_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_01_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_01_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_01_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_02_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_02_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_02_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_02_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_02_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_03_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_03_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_03_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_03_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_03_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_04_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_04_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_04_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_04_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_04_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_05_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_05_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_05_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_05_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_05_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_06_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_06_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_06_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_06_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_06_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_07_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_07_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_07_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_07_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_07_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_08_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_08_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_08_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_08_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_08_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_1f_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_1f_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_1f_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_1f_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_1f_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_40_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_40_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_40_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_40_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_40_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_41_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_41_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_41_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_41_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_41_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_42_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_42_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_42_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_42_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_42_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_43_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_43_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_43_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_43_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_43_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:49" *)
reg reg_70_new_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:50" *)
reg [31:0] reg_70_new_value;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire [31:0] reg_70_output__payload;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_70_output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:47" *)
wire reg_70_output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/python/nmigen_cfu/cfu.py:52" *)
input start;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output \valid$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output \valid$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output \valid$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \valid$28 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \valid$36 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output \valid$4 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \valid$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \valid$44 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \valid$52 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \valid$56 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \valid$60 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
wire \valid$64 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:100" *)
output \valid$7 ;
always @(posedge clk)
done <= \done$next ;
reg_01 reg_01 (
.clk(clk),
.new_en(reg_01_new_en),
.new_value(reg_01_new_value),
.output__payload(reg_01_output__payload),
.output__ready(reg_01_output__ready),
.output__valid(reg_01_output__valid),
.rst(rst)
);
reg_02 reg_02 (
.clk(clk),
.new_en(reg_02_new_en),
.new_value(reg_02_new_value),
.output__payload(reg_02_output__payload),
.output__ready(reg_02_output__ready),
.output__valid(reg_02_output__valid),
.rst(rst)
);
reg_03 reg_03 (
.clk(clk),
.new_en(reg_03_new_en),
.new_value(reg_03_new_value),
.output__payload(reg_03_output__payload),
.output__ready(1'h0),
.output__valid(reg_03_output__valid),
.rst(rst)
);
reg_04 reg_04 (
.clk(clk),
.new_en(reg_04_new_en),
.new_value(reg_04_new_value),
.output__payload(reg_04_output__payload),
.output__ready(reg_04_output__ready),
.output__valid(reg_04_output__valid),
.rst(rst)
);
reg_05 reg_05 (
.clk(clk),
.new_en(reg_05_new_en),
.new_value(reg_05_new_value),
.output__payload(reg_05_output__payload),
.output__ready(reg_05_output__ready),
.output__valid(reg_05_output__valid),
.rst(rst)
);
reg_06 reg_06 (
.clk(clk),
.new_en(reg_06_new_en),
.new_value(reg_06_new_value),
.output__payload(reg_06_output__payload),
.output__ready(1'h0),
.output__valid(reg_06_output__valid),
.rst(rst)
);
reg_07 reg_07 (
.clk(clk),
.new_en(reg_07_new_en),
.new_value(reg_07_new_value),
.output__payload(reg_07_output__payload),
.output__ready(1'h0),
.output__valid(reg_07_output__valid),
.rst(rst)
);
reg_08 reg_08 (
.clk(clk),
.new_en(reg_08_new_en),
.new_value(reg_08_new_value),
.output__payload(reg_08_output__payload),
.output__ready(1'h0),
.output__valid(reg_08_output__valid),
.rst(rst)
);
reg_1f reg_1f (
.clk(clk),
.new_en(reg_1f_new_en),
.new_value(reg_1f_new_value),
.output__payload(reg_1f_output__payload),
.output__ready(reg_1f_output__ready),
.output__valid(reg_1f_output__valid),
.rst(rst)
);
reg_40 reg_40 (
.clk(clk),
.new_en(reg_40_new_en),
.new_value(reg_40_new_value),
.output__payload(reg_40_output__payload),
.output__ready(1'h0),
.output__valid(reg_40_output__valid),
.rst(rst)
);
reg_41 reg_41 (
.clk(clk),
.new_en(reg_41_new_en),
.new_value(reg_41_new_value),
.output__payload(reg_41_output__payload),
.output__ready(1'h0),
.output__valid(reg_41_output__valid),
.rst(rst)
);
reg_42 reg_42 (
.clk(clk),
.new_en(reg_42_new_en),
.new_value(reg_42_new_value),
.output__payload(reg_42_output__payload),
.output__ready(1'h0),
.output__valid(reg_42_output__valid),
.rst(rst)
);
reg_43 reg_43 (
.clk(clk),
.new_en(reg_43_new_en),
.new_value(reg_43_new_value),
.output__payload(reg_43_output__payload),
.output__ready(1'h0),
.output__valid(reg_43_output__valid),
.rst(rst)
);
reg_70 reg_70 (
.clk(clk),
.new_en(reg_70_new_en),
.new_value(reg_70_new_value),
.output__payload(reg_70_output__payload),
.output__ready(reg_70_output__ready),
.output__valid(reg_70_output__valid),
.rst(rst)
);
always @* begin
if (\initial ) begin end
\$signal$31 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
\$signal$31 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$33 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
\$signal$33 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$35 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
\$signal$35 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$39 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
\$signal$39 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$43 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
\$signal$43 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$47 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
\$signal$47 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$25 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
\$signal$25 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$49 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
\$signal$49 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$51 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
\$signal$51 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$20 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
\$signal$20 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$59 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h41:
\$signal$59 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$63 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h41:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h42:
\$signal$63 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$19 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h41:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h42:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h43:
\$signal$19 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
\done$next = 1'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:122" */
default:
\done$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\done$next = 1'h0;
endcase
end
always @* begin
if (\initial ) begin end
reg_01_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
reg_01_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_01_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
reg_01_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_02_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
reg_02_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_02_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
reg_02_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_03_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
reg_03_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_03_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
reg_03_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_04_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
reg_04_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_04_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
reg_04_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_05_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
reg_05_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_05_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
reg_05_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_06_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
reg_06_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_06_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
reg_06_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_07_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
reg_07_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_07_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
reg_07_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_08_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
reg_08_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_08_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
reg_08_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_1f_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
reg_1f_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_1f_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
reg_1f_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_70_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
reg_70_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
\$signal$27 = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
\$signal$27 = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_70_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
reg_70_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_40_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
reg_40_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_40_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
reg_40_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_41_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h41:
reg_41_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_41_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h41:
reg_41_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_42_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h41:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h42:
reg_42_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_42_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h41:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h42:
reg_42_new_value = in0;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_43_new_en = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h41:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h42:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h43:
reg_43_new_en = 1'h1;
endcase
endcase
end
always @* begin
if (\initial ) begin end
reg_43_new_value = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" *)
casez (start)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:113" */
1'h1:
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:116" *)
casez (funct7)
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h01:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h02:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h03:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h04:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h05:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h06:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h07:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h08:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h1f:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h70:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h40:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h41:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h42:
/* empty */;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/set.py:118" */
7'h43:
reg_43_new_value = in0;
endcase
endcase
end
assign \ready$30 = 1'h0;
assign \ready$38 = 1'h0;
assign \ready$42 = 1'h0;
assign \ready$46 = 1'h0;
assign \ready$54 = 1'h0;
assign \ready$58 = 1'h0;
assign \ready$62 = 1'h0;
assign \ready$66 = 1'h0;
assign in1s = in1;
assign in0s = in0;
assign \$signal$18 = reg_43_output__payload;
assign reg_43_output__ready = 1'h0;
assign \payload$65 = reg_43_output__payload;
assign \valid$64 = reg_43_output__valid;
assign \$signal$17 = reg_42_output__payload;
assign reg_42_output__ready = 1'h0;
assign \payload$61 = reg_42_output__payload;
assign \valid$60 = reg_42_output__valid;
assign \$signal$16 = reg_41_output__payload;
assign reg_41_output__ready = 1'h0;
assign \payload$57 = reg_41_output__payload;
assign \valid$56 = reg_41_output__valid;
assign \$signal$55 = reg_40_output__payload;
assign reg_40_output__ready = 1'h0;
assign \payload$53 = reg_40_output__payload;
assign \valid$52 = reg_40_output__valid;
assign \$signal$50 = reg_70_output__payload;
assign reg_70_output__ready = ready;
assign payload = reg_70_output__payload;
assign valid = reg_70_output__valid;
assign \$signal$48 = reg_1f_output__payload;
assign reg_1f_output__ready = \ready$15 ;
assign \payload$13 = reg_1f_output__payload;
assign \valid$14 = reg_1f_output__valid;
assign \$signal$23 = reg_08_output__payload;
assign reg_08_output__ready = 1'h0;
assign \payload$45 = reg_08_output__payload;
assign \valid$44 = reg_08_output__valid;
assign \$signal$22 = reg_07_output__payload;
assign reg_07_output__ready = 1'h0;
assign \payload$41 = reg_07_output__payload;
assign \valid$40 = reg_07_output__valid;
assign \$signal$21 = reg_06_output__payload;
assign reg_06_output__ready = 1'h0;
assign \payload$37 = reg_06_output__payload;
assign \valid$36 = reg_06_output__valid;
assign \$signal$34 = reg_05_output__payload;
assign reg_05_output__ready = \ready$6 ;
assign \payload$5 = reg_05_output__payload;
assign \valid$4 = reg_05_output__valid;
assign \$signal$32 = reg_04_output__payload;
assign reg_04_output__ready = \ready$12 ;
assign \payload$11 = reg_04_output__payload;
assign \valid$10 = reg_04_output__valid;
assign \$signal = reg_03_output__payload;
assign reg_03_output__ready = 1'h0;
assign \payload$29 = reg_03_output__payload;
assign \valid$28 = reg_03_output__valid;
assign \$signal$26 = reg_02_output__payload;
assign reg_02_output__ready = \ready$3 ;
assign \payload$2 = reg_02_output__payload;
assign \valid$1 = reg_02_output__valid;
assign \$signal$24 = reg_01_output__payload;
assign reg_01_output__ready = \ready$9 ;
assign \payload$8 = reg_01_output__payload;
assign \valid$7 = reg_01_output__valid;
endmodule
(* \nmigen.hierarchy = "Cfu.pp.ppp.srdhm" *)
(* generator = "nMigen" *)
module srdhm(clk, input__valid, input__payload__a, input__payload__b, output__ready, output__valid, output__payload, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:69" *)
wire [32:0] \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:75" *)
wire [63:0] \$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:75" *)
wire [63:0] \$11 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:78" *)
wire \$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:79" *)
wire [63:0] \$16 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:79" *)
wire [62:0] \$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:79" *)
wire [30:0] \$18 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire [32:0] \$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:79" *)
wire [63:0] \$21 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:82" *)
wire [32:0] \$23 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:80" *)
wire [32:0] \$24 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:82" *)
wire [32:0] \$26 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:82" *)
wire [32:0] \$28 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:69" *)
wire [32:0] \$4 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:69" *)
wire [32:0] \$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:69" *)
wire \$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:80" *)
wire [31:0] high_bits;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input [31:0] input__payload__a;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input [31:0] input__payload__b;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
wire input__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *)
input input__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output [31:0] output__payload;
reg [31:0] output__payload = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
reg [31:0] \output__payload$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
input output__ready;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:49" *)
output output__valid;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:67" *)
reg [31:0] reg_a = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:67" *)
reg [31:0] \reg_a$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:74" *)
reg [62:0] reg_ab = 63'h0000000000000000;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:74" *)
reg [62:0] \reg_ab$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:68" *)
reg [31:0] reg_b = 32'd0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:68" *)
reg [31:0] \reg_b$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:127" *)
reg [2:0] sr = 3'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:127" *)
reg [1:0] \sr$13 = 2'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:127" *)
reg [1:0] \sr$13$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:127" *)
reg [2:0] \sr$next ;
assign \$11 = $signed(reg_a) * (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:75" *) $signed(reg_b);
assign \$14 = $signed(input__payload__a) >= (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:78" *) $signed(32'd0);
assign \$18 = \sr$13 [1] ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:79" *) 31'h40000000 : 31'h3fffffff;
assign \$17 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:79" *) \$18 ;
assign \$21 = $signed(reg_ab) + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:79" *) $signed(\$17 );
assign \$24 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:80" *) $signed(high_bits);
assign \$26 = - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:82" *) $signed(high_bits);
assign \$28 = \sr$13 [1] ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:82" *) \$24 : \$26 ;
assign \$2 = + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/stream/actor.py:48" *) $signed(input__payload__a);
assign \$4 = - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:69" *) $signed(input__payload__a);
assign \$7 = $signed(input__payload__a) >= (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:69" *) $signed(32'd0);
assign \$6 = \$7 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/proj/hps_accel/gateware/gen1/post_process.py:69" *) \$2 : \$4 ;
always @(posedge clk)
output__payload <= \output__payload$next ;
always @(posedge clk)
\sr$13 <= \sr$13$next ;
always @(posedge clk)
reg_ab <= \reg_ab$next ;
always @(posedge clk)
reg_b <= \reg_b$next ;
always @(posedge clk)
reg_a <= \reg_a$next ;
always @(posedge clk)
sr <= \sr$next ;
always @* begin
if (\initial ) begin end
\sr$next = { sr[1:0], input__valid };
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\sr$next = 3'h0;
endcase
end
always @* begin
if (\initial ) begin end
\reg_a$next = \$6 [31:0];
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\reg_a$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\reg_b$next = input__payload__b;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\reg_b$next = 32'd0;
endcase
end
always @* begin
if (\initial ) begin end
\reg_ab$next = \$11 [62:0];
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\reg_ab$next = 63'h0000000000000000;
endcase
end
always @* begin
if (\initial ) begin end
\sr$13$next = { \sr$13 [0], \$14 };
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\sr$13$next = 2'h0;
endcase
end
always @* begin
if (\initial ) begin end
\output__payload$next = \$28 [31:0];
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\output__payload$next = 32'd0;
endcase
end
assign \$1 = \$6 ;
assign \$10 = \$11 ;
assign \$16 = \$21 ;
assign \$23 = \$28 ;
assign high_bits = \$21 [62:31];
assign output__valid = sr[2];
assign input__ready = output__ready;
endmodule
(* \nmigen.hierarchy = "Cfu.pp.fifo.wrapped.unbuffered" *)
(* generator = "nMigen" *)
module unbuffered(clk, w_data, w_en, w_rdy, r_data, r_en, r_rdy, level, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *)
wire [6:0] \$10 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *)
wire [6:0] \$11 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *)
wire [6:0] \$13 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *)
wire \$14 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:139" *)
wire \$17 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *)
wire [6:0] \$19 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:133" *)
wire \$2 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *)
wire [6:0] \$20 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *)
wire [6:0] \$22 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *)
wire \$23 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:140" *)
wire \$26 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:166" *)
wire \$28 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:139" *)
wire \$29 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:166" *)
wire \$32 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:167" *)
wire [6:0] \$34 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:167" *)
wire [6:0] \$35 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:139" *)
wire \$37 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:168" *)
wire \$39 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:134" *)
wire \$4 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:140" *)
wire \$40 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:168" *)
wire \$43 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:169" *)
wire [6:0] \$45 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:169" *)
wire [6:0] \$46 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:152" *)
wire \$6 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:140" *)
wire \$8 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:147" *)
reg [5:0] consume = 6'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:147" *)
reg [5:0] \consume$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:121" *)
output [5:0] level;
reg [5:0] level = 6'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:121" *)
reg [5:0] \level$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:146" *)
reg [5:0] produce = 6'h00;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:146" *)
reg [5:0] \produce$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:83" *)
output [31:0] r_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:85" *)
input r_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:86" *)
wire [5:0] r_level;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:84" *)
output r_rdy;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:144" *)
wire [5:0] storage_r_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:144" *)
wire [31:0] storage_r_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:144" *)
wire storage_r_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:143" *)
wire [5:0] storage_w_addr;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:143" *)
wire [31:0] storage_w_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:143" *)
wire storage_w_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:78" *)
input [31:0] w_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:80" *)
input w_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:81" *)
wire [5:0] w_level;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:79" *)
output w_rdy;
reg [31:0] storage [62:0];
initial begin
storage[0] = 32'd0;
storage[1] = 32'd0;
storage[2] = 32'd0;
storage[3] = 32'd0;
storage[4] = 32'd0;
storage[5] = 32'd0;
storage[6] = 32'd0;
storage[7] = 32'd0;
storage[8] = 32'd0;
storage[9] = 32'd0;
storage[10] = 32'd0;
storage[11] = 32'd0;
storage[12] = 32'd0;
storage[13] = 32'd0;
storage[14] = 32'd0;
storage[15] = 32'd0;
storage[16] = 32'd0;
storage[17] = 32'd0;
storage[18] = 32'd0;
storage[19] = 32'd0;
storage[20] = 32'd0;
storage[21] = 32'd0;
storage[22] = 32'd0;
storage[23] = 32'd0;
storage[24] = 32'd0;
storage[25] = 32'd0;
storage[26] = 32'd0;
storage[27] = 32'd0;
storage[28] = 32'd0;
storage[29] = 32'd0;
storage[30] = 32'd0;
storage[31] = 32'd0;
storage[32] = 32'd0;
storage[33] = 32'd0;
storage[34] = 32'd0;
storage[35] = 32'd0;
storage[36] = 32'd0;
storage[37] = 32'd0;
storage[38] = 32'd0;
storage[39] = 32'd0;
storage[40] = 32'd0;
storage[41] = 32'd0;
storage[42] = 32'd0;
storage[43] = 32'd0;
storage[44] = 32'd0;
storage[45] = 32'd0;
storage[46] = 32'd0;
storage[47] = 32'd0;
storage[48] = 32'd0;
storage[49] = 32'd0;
storage[50] = 32'd0;
storage[51] = 32'd0;
storage[52] = 32'd0;
storage[53] = 32'd0;
storage[54] = 32'd0;
storage[55] = 32'd0;
storage[56] = 32'd0;
storage[57] = 32'd0;
storage[58] = 32'd0;
storage[59] = 32'd0;
storage[60] = 32'd0;
storage[61] = 32'd0;
storage[62] = 32'd0;
end
always @(posedge clk) begin
if (storage_w_en)
storage[storage_w_addr] <= storage_w_data;
end
reg [31:0] _0_;
always @(posedge clk) begin
if (storage_r_en) begin
_0_ <= storage[storage_r_addr];
end
end
assign storage_r_data = _0_;
assign \$11 = produce + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *) 1'h1;
assign \$14 = produce == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *) 6'h3e;
assign \$13 = \$14 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *) 7'h00 : \$11 ;
assign \$17 = r_rdy & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:139" *) r_en;
assign \$20 = consume + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *) 1'h1;
assign \$23 = consume == (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *) 6'h3e;
assign \$22 = \$23 ? (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:93" *) 7'h00 : \$20 ;
assign \$26 = w_rdy & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:140" *) w_en;
assign \$2 = level != (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:133" *) 6'h3f;
assign \$29 = r_rdy & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:139" *) r_en;
assign \$28 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:166" *) \$29 ;
assign \$32 = \$26 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:166" *) \$28 ;
assign \$35 = level + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:167" *) 1'h1;
assign \$37 = r_rdy & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:139" *) r_en;
assign \$40 = w_rdy & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:140" *) w_en;
assign \$39 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:168" *) \$40 ;
assign \$43 = \$37 & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:168" *) \$39 ;
assign \$46 = level - (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:169" *) 1'h1;
assign \$4 = | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:134" *) level;
assign \$6 = w_en & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:152" *) w_rdy;
assign \$8 = w_rdy & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:140" *) w_en;
always @(posedge clk)
level <= \level$next ;
always @(posedge clk)
consume <= \consume$next ;
always @(posedge clk)
produce <= \produce$next ;
always @* begin
if (\initial ) begin end
\consume$next = consume;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:163" *)
casez (\$17 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:163" */
1'h1:
\consume$next = \$22 [5:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\consume$next = 6'h00;
endcase
end
always @* begin
if (\initial ) begin end
\level$next = level;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:166" *)
casez (\$32 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:166" */
1'h1:
\level$next = \$35 [5:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:168" *)
casez (\$43 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:168" */
1'h1:
\level$next = \$46 [5:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\level$next = 6'h00;
endcase
end
always @* begin
if (\initial ) begin end
\produce$next = produce;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:154" *)
casez (\$8 )
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:154" */
1'h1:
\produce$next = \$13 [5:0];
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\produce$next = 6'h00;
endcase
end
assign \$10 = \$13 ;
assign \$19 = \$22 ;
assign \$34 = \$35 ;
assign \$45 = \$46 ;
assign storage_r_en = r_en;
assign r_data = storage_r_data;
assign storage_r_addr = consume;
assign storage_w_en = \$6 ;
assign storage_w_data = w_data;
assign storage_w_addr = produce;
assign r_level = level;
assign w_level = level;
assign r_rdy = \$4 ;
assign w_rdy = \$2 ;
endmodule
(* \nmigen.hierarchy = "Cfu.pp.fifo.wrapped" *)
(* generator = "nMigen" *)
module wrapped(clk, w_en, w_data, w_rdy, r_rdy, r_data, r_en, rst);
reg \initial = 0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:249" *)
wire \$1 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:249" *)
wire \$3 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:249" *)
wire \$5 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:257" *)
wire [6:0] \$7 ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input clk;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:225" *)
wire [6:0] level;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:83" *)
output [31:0] r_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:85" *)
input r_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:86" *)
wire [6:0] r_level;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:84" *)
output r_rdy;
reg r_rdy = 1'h0;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:84" *)
reg \r_rdy$next ;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/ir.py:524" *)
input rst;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:121" *)
wire [5:0] unbuffered_level;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:83" *)
wire [31:0] unbuffered_r_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:85" *)
wire unbuffered_r_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:84" *)
wire unbuffered_r_rdy;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:78" *)
wire [31:0] unbuffered_w_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:80" *)
wire unbuffered_w_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:79" *)
wire unbuffered_w_rdy;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:78" *)
input [31:0] w_data;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:80" *)
input w_en;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:81" *)
wire [6:0] w_level;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:79" *)
output w_rdy;
assign \$1 = ~ (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:249" *) r_rdy;
assign \$3 = \$1 | (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:249" *) r_en;
assign \$5 = unbuffered_r_rdy & (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:249" *) \$3 ;
assign \$7 = unbuffered_level + (* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:257" *) r_rdy;
always @(posedge clk)
r_rdy <= \r_rdy$next ;
unbuffered unbuffered (
.clk(clk),
.level(unbuffered_level),
.r_data(unbuffered_r_data),
.r_en(unbuffered_r_en),
.r_rdy(unbuffered_r_rdy),
.rst(rst),
.w_data(unbuffered_w_data),
.w_en(unbuffered_w_en),
.w_rdy(unbuffered_w_rdy)
);
always @* begin
if (\initial ) begin end
\r_rdy$next = r_rdy;
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:251" *)
casez ({ r_en, unbuffered_r_en })
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:251" */
2'b?1:
\r_rdy$next = 1'h1;
/* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/lib/fifo.py:253" */
2'b1?:
\r_rdy$next = 1'h0;
endcase
(* src = "/media/tim/GIT/tcal-x/CFU-Playground/third_party/python/nmigen/nmigen/hdl/xfrm.py:519" *)
casez (rst)
1'h1:
\r_rdy$next = 1'h0;
endcase
end
assign r_level = level;
assign w_level = level;
assign level = \$7 ;
assign unbuffered_r_en = \$5 ;
assign r_data = unbuffered_r_data;
assign w_rdy = unbuffered_w_rdy;
assign unbuffered_w_en = w_en;
assign unbuffered_w_data = w_data;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_PP_SYMBOL_V
`define SKY130_FD_SC_LP__HA_PP_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_PP_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: 6551rx.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ([email protected])
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
// [email protected]
////////////////////////////////////////////////////////////////////////////////
module uart51_rx(
RESET_N,
BAUD_CLK,
RX_DATA,
RX_BUFFER,
RX_WORD,
RX_PAR_DIS,
RX_PARITY,
PARITY_ERR,
FRAME,
READY
);
input RESET_N;
input BAUD_CLK;
input RX_DATA;
output [7:0] RX_BUFFER;
reg [7:0] RX_BUFFER;
input [1:0] RX_WORD;
input RX_PAR_DIS;
input [1:0] RX_PARITY;
output PARITY_ERR;
reg PARITY_ERR;
output FRAME;
reg FRAME;
output READY;
reg READY;
reg [5:0] STATE;
reg [2:0] BIT;
reg RX_DATA0;
reg RX_DATA1;
always @ (posedge BAUD_CLK or negedge RESET_N)
begin
if(!RESET_N)
begin
RX_BUFFER <= 8'h00;
STATE <= 6'b000000;
FRAME <= 1'b0;
BIT <= 3'b000;
RX_DATA0 <= 1'b1;
RX_DATA1 <= 1'b1;
READY <= 1'b0;
end
else
begin
RX_DATA0 <= RX_DATA;
RX_DATA1 <= RX_DATA0;
case (STATE)
6'b000000: // States 0-15 will be start bit
begin
BIT <= 3'b000;
if(~RX_DATA1)
STATE <= 6'b000001;
end
6'b001111: // End of start bit, flag data not ready
begin // If data is not retrieved before this, then overrun
READY <= 1'b0;
STATE <= 6'b010000;
end
6'b010111: // Each data bit is states 16-31, the middle is 23
begin
RX_BUFFER[BIT] <= RX_DATA1;
STATE <= 6'b011000;
end
6'b011111: // End of the data bits
begin
if(BIT == 3'b111)
begin
STATE <= 6'b100000;
end
else
begin
if((RX_WORD == 2'b01) && (BIT == 3'b110))
begin
STATE <= 6'b100000;
end
else
begin
if((RX_WORD == 2'b10) && (BIT == 3'b101))
begin
STATE <= 6'b100000;
end
else
begin
if((RX_WORD == 2'b11) && (BIT == 3'b100))
begin
STATE <= 6'b100000;
end
else
begin
BIT <= BIT + 1'b1;
STATE <= 6'b010000;
end
end
end
end
end
6'b100000: // First tick of Stop or Parity, Parity is 32 - 47
begin
if(RX_PAR_DIS)
STATE <= 6'b110001; // get stop
else
STATE <= 6'b100001; // get parity
end
6'b100111: // Middle of Parity is 39
begin
PARITY_ERR <= ~RX_PARITY[1] & // Get but do not check Parity if 1 is set
(((RX_BUFFER[0] ^ RX_BUFFER[1])
^ (RX_BUFFER[2] ^ RX_BUFFER[3]))
^((RX_BUFFER[4] ^ RX_BUFFER[5])
^ (RX_BUFFER[6] ^ RX_BUFFER[7])) // clear bit #8 if only 7 bits
^ (~RX_PARITY[0] ^ RX_DATA1));
STATE <= 6'b101000;
// 1 bit early for timing reasons
end
6'b110111: // first stop bit is 32 or 48 then 49 - 63
begin
FRAME <= !RX_DATA1; // if data != 1 then not stop bit
READY <= 1'b1;
STATE <= 6'b111000;
end
// In case of a framing error, wait until data is 1 then start over
// We skipped this check for 6 clock cycles so CPU speed is not a factor
// in the RX_READY state machine above
6'b111000:
begin
if(RX_DATA1)
STATE <= 6'b000000;
end
default: STATE <= STATE + 1'b1;
endcase
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_data_fifo:2.1
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_m00_data_fifo_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_data_fifo_v2_1_6_axi_data_fifo #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_WRITE_FIFO_DEPTH(512),
.C_AXI_WRITE_FIFO_TYPE("bram"),
.C_AXI_WRITE_FIFO_DELAY(1),
.C_AXI_READ_FIFO_DEPTH(512),
.C_AXI_READ_FIFO_TYPE("bram"),
.C_AXI_READ_FIFO_DELAY(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_LP2_V
`define SKY130_FD_SC_LP__AND2_LP2_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_lp2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_lp2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_LP2_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_axi_basic_rx.v
// Version : 1.11
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_11_0_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_11_0_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
pcie_7x_v1_11_0_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_SYMBOL_V
`define SKY130_FD_SC_HD__OR3B_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_G_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_G_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_G_SYMBOL_V
|
module incif_1uint32_CEtable__0x0759af78(input CLK, input CE, input [32:0] process_input, output [31:0] process_output);
parameter INSTANCE_NAME="INST";
wire [31:0] unnamedcast7797USEDMULTIPLEcast;assign unnamedcast7797USEDMULTIPLEcast = (process_input[31:0]);
assign process_output = (((process_input[32]))?({(unnamedcast7797USEDMULTIPLEcast+(32'd1))}):(unnamedcast7797USEDMULTIPLEcast));
// function: process pure=true delay=0
endmodule
module RegBy_incif_1uint32_CEtable__0x0759af78_CEtrue_initnil(input CLK, input set_valid, input CE, input [31:0] set_inp, input setby_valid, input setby_inp, output [31:0] SETBY_OUTPUT, output [31:0] GET_OUTPUT);
parameter INSTANCE_NAME="INST";
reg [31:0] R;
wire [31:0] regby_inner_process_output;
always @(posedge CLK) begin if(set_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(setby_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,set_valid})+({4'b0,setby_valid})) > 5'd1) begin $display("error, function 'set' on instance 'R' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [32:0] unnamedcallArbitrate7829USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate7829USEDMULTIPLEcallArbitrate = {(set_valid||setby_valid),((set_valid)?(set_inp):(regby_inner_process_output))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate7829USEDMULTIPLEcallArbitrate[32]) && CE) begin R <= (unnamedcallArbitrate7829USEDMULTIPLEcallArbitrate[31:0]); end end
assign SETBY_OUTPUT = regby_inner_process_output;
assign GET_OUTPUT = R;
// function: set pure=false ONLY WIRE
// function: setby pure=false ONLY WIRE
// function: get pure=true ONLY WIRE
incif_1uint32_CEtable__0x0759af78 #(.INSTANCE_NAME({INSTANCE_NAME,"_regby_inner"})) regby_inner(.CLK(CLK), .CE(CE), .process_input({setby_inp,R}), .process_output(regby_inner_process_output));
endmodule
module Underflow_A_null_null__count153600_cycles1874016_toosoon156168_UStrue(input CLK, input ready_downstream, output ready, input reset, input process_input, output process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire [31:0] cycleCount_GET_OUTPUT;
wire unnamedbinop8301USEDMULTIPLEbinop;assign unnamedbinop8301USEDMULTIPLEbinop = {((cycleCount_GET_OUTPUT)>((32'd1874016)))};
assign ready = {(ready_downstream||unnamedbinop8301USEDMULTIPLEbinop)};
wire unnamedbinop8303USEDMULTIPLEbinop;assign unnamedbinop8303USEDMULTIPLEbinop = {({(ready_downstream||reset)}||unnamedbinop8301USEDMULTIPLEbinop)};
wire [31:0] outputCount_GET_OUTPUT;
wire [31:0] unnamedcast8314USEDMULTIPLEcast;assign unnamedcast8314USEDMULTIPLEcast = (32'd153600);
wire unnamedcast8295USEDMULTIPLEcast;assign unnamedcast8295USEDMULTIPLEcast = process_input;
wire unnamedunary8320USEDMULTIPLEunary;assign unnamedunary8320USEDMULTIPLEunary = {(~reset)};
wire unnamedbinop8330USEDMULTIPLEbinop;assign unnamedbinop8330USEDMULTIPLEbinop = {({(cycleCount_GET_OUTPUT==(32'd156168))}&&{((outputCount_GET_OUTPUT)>=(unnamedcast8314USEDMULTIPLEcast))})};
wire [31:0] outputCount_SETBY_OUTPUT;
wire [31:0] cycleCount_SETBY_OUTPUT;
always @(posedge CLK) begin if({(~unnamedbinop8330USEDMULTIPLEbinop)} == 1'b0 && unnamedunary8320USEDMULTIPLEunary==1'b1 && unnamedbinop8303USEDMULTIPLEbinop==1'b1) begin $display("%s: pipeline completed eariler than expected",INSTANCE_NAME); end end
assign process_output = {{({({({(unnamedbinop8301USEDMULTIPLEbinop&&{((outputCount_GET_OUTPUT)<(unnamedcast8314USEDMULTIPLEcast))})}||{({(~unnamedbinop8301USEDMULTIPLEbinop)}&&unnamedcast8295USEDMULTIPLEcast)})}&&unnamedunary8320USEDMULTIPLEunary)}||unnamedbinop8330USEDMULTIPLEbinop)}};
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
RegBy_incif_1uint32_CEtable__0x0759af78_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_outputCount"})) outputCount(.CLK(CLK), .set_valid(reset), .CE(unnamedbinop8303USEDMULTIPLEbinop), .set_inp((32'd0)), .setby_valid(unnamedunary8320USEDMULTIPLEunary), .setby_inp({(ready_downstream&&{(unnamedcast8295USEDMULTIPLEcast||unnamedbinop8301USEDMULTIPLEbinop)})}), .SETBY_OUTPUT(outputCount_SETBY_OUTPUT), .GET_OUTPUT(outputCount_GET_OUTPUT));
RegBy_incif_1uint32_CEtable__0x0759af78_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_cycleCount"})) cycleCount(.CLK(CLK), .set_valid(reset), .CE((1'd1)), .set_inp((32'd0)), .setby_valid(unnamedunary8320USEDMULTIPLEunary), .setby_inp((1'd1)), .SETBY_OUTPUT(cycleCount_SETBY_OUTPUT), .GET_OUTPUT(cycleCount_GET_OUTPUT));
endmodule
module ShiftRegister_0_CEtrue_TY1(input CLK, input CE, input sr_input, output pushPop_out);
parameter INSTANCE_NAME="INST";
assign pushPop_out = sr_input;
// function: pushPop pure=true delay=0
// function: reset pure=true delay=0
endmodule
module index__null_null__0(input CLK, input process_CE);
parameter INSTANCE_NAME="INST";
// function: process pure=true delay=0
endmodule
module MakeHandshake_index__null_null__0(input CLK, input ready_downstream, output ready, input reset, input process_input, output process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
assign ready = ready_downstream;
wire unnamedbinop7895USEDMULTIPLEbinop;assign unnamedbinop7895USEDMULTIPLEbinop = {(ready_downstream||reset)};
wire unnamedcast7903USEDMULTIPLEcast;assign unnamedcast7903USEDMULTIPLEcast = process_input;
wire validBitDelay_index__null_null__0_pushPop_out;
always @(posedge CLK) begin if({(~{(unnamedcast7903USEDMULTIPLEcast===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: MakeHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign process_output = {validBitDelay_index__null_null__0_pushPop_out};
// function: ready pure=true ONLY WIRE
// function: reset pure=true ONLY WIRE
// function: process pure=false ONLY WIRE
ShiftRegister_0_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_validBitDelay_index__null_null__0"})) validBitDelay_index__null_null__0(.CLK(CLK), .CE(unnamedbinop7895USEDMULTIPLEbinop), .sr_input(unnamedcast7903USEDMULTIPLEcast), .pushPop_out(validBitDelay_index__null_null__0_pushPop_out));
index__null_null__0 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner"})) inner(.CLK(CLK), .process_CE(unnamedbinop7895USEDMULTIPLEbinop));
endmodule
module ShiftRegister_1_CEtrue_TY1(input CLK, input pushPop_valid, input CE, input sr_input, output pushPop_out, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'pushPop'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
reg SR1;
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR1' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR1' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR1' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate362USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate362USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(sr_input):((1'd0)))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate362USEDMULTIPLEcallArbitrate[1]) && CE) begin SR1 <= (unnamedcallArbitrate362USEDMULTIPLEcallArbitrate[0]); end end
assign pushPop_out = SR1;
// function: pushPop pure=false delay=0
// function: reset pure=false delay=0
endmodule
module freadSeq____ov7660_raw_dup(input CLK, input process_valid, input CE, output [63:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
reg [63:0] freadfile_out;
assign process_output = freadfile_out;
// function: process pure=false delay=1
// function: reset pure=false delay=0
integer freadfile_file,r;
initial begin freadfile_file = $fopen("../ov7660.raw.dup","r"); end
always @ (posedge CLK) begin
if (process_valid && CE) begin freadfile_out[7:0] <= $fgetc(freadfile_file); freadfile_out[15:8] <= $fgetc(freadfile_file); freadfile_out[23:16] <= $fgetc(freadfile_file); freadfile_out[31:24] <= $fgetc(freadfile_file); freadfile_out[39:32] <= $fgetc(freadfile_file); freadfile_out[47:40] <= $fgetc(freadfile_file); freadfile_out[55:48] <= $fgetc(freadfile_file); freadfile_out[63:56] <= $fgetc(freadfile_file); end
if (reset) begin r=$fseek(freadfile_file,0,0); end end
endmodule
module MakeHandshake_freadSeq____ov7660_raw_dup(input CLK, input ready_downstream, output ready, input reset, input process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
assign ready = ready_downstream;
wire unnamedbinop8359USEDMULTIPLEbinop;assign unnamedbinop8359USEDMULTIPLEbinop = {(ready_downstream||reset)};
wire unnamedcast8367USEDMULTIPLEcast;assign unnamedcast8367USEDMULTIPLEcast = process_input;
wire [63:0] inner_process_output;
wire validBitDelay_freadSeq____ov7660_raw_dup_pushPop_out;
always @(posedge CLK) begin if({(~{(unnamedcast8367USEDMULTIPLEcast===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: MakeHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign process_output = {validBitDelay_freadSeq____ov7660_raw_dup_pushPop_out,inner_process_output};
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
ShiftRegister_1_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_validBitDelay_freadSeq____ov7660_raw_dup"})) validBitDelay_freadSeq____ov7660_raw_dup(.CLK(CLK), .pushPop_valid({(~reset)}), .CE(unnamedbinop8359USEDMULTIPLEbinop), .sr_input(unnamedcast8367USEDMULTIPLEcast), .pushPop_out(validBitDelay_freadSeq____ov7660_raw_dup_pushPop_out), .reset(reset));
freadSeq____ov7660_raw_dup #(.INSTANCE_NAME({INSTANCE_NAME,"_inner"})) inner(.CLK(CLK), .process_valid(unnamedcast8367USEDMULTIPLEcast), .CE(unnamedbinop8359USEDMULTIPLEbinop), .process_output(inner_process_output), .reset(reset));
endmodule
module sumwrap_uint16_to1(input CLK, input CE, input [31:0] process_input, output [15:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] unnamedcast7518USEDMULTIPLEcast;assign unnamedcast7518USEDMULTIPLEcast = (process_input[15:0]);
assign process_output = (({(unnamedcast7518USEDMULTIPLEcast==(16'd1))})?((16'd0)):({(unnamedcast7518USEDMULTIPLEcast+(process_input[31:16]))}));
// function: process pure=true delay=0
endmodule
module RegBy_sumwrap_uint16_to1_CEtrue_initnil(input CLK, input set_valid, input CE, input [15:0] set_inp, input setby_valid, input [15:0] setby_inp, output [15:0] SETBY_OUTPUT, output [15:0] GET_OUTPUT);
parameter INSTANCE_NAME="INST";
reg [15:0] R;
wire [15:0] regby_inner_process_output;
always @(posedge CLK) begin if(set_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(setby_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,set_valid})+({4'b0,setby_valid})) > 5'd1) begin $display("error, function 'set' on instance 'R' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [16:0] unnamedcallArbitrate7558USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate7558USEDMULTIPLEcallArbitrate = {(set_valid||setby_valid),((set_valid)?(set_inp):(regby_inner_process_output))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate7558USEDMULTIPLEcallArbitrate[16]) && CE) begin R <= (unnamedcallArbitrate7558USEDMULTIPLEcallArbitrate[15:0]); end end
assign SETBY_OUTPUT = regby_inner_process_output;
assign GET_OUTPUT = R;
// function: set pure=false ONLY WIRE
// function: setby pure=false ONLY WIRE
// function: get pure=true ONLY WIRE
sumwrap_uint16_to1 #(.INSTANCE_NAME({INSTANCE_NAME,"_regby_inner"})) regby_inner(.CLK(CLK), .CE(CE), .process_input({setby_inp,R}), .process_output(regby_inner_process_output));
endmodule
module ChangeRate_uint8_2_1__from4_to2_H1(input CLK, output ready, input reset, input CE, input process_valid, input [63:0] process_input, output [32:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
wire [15:0] phase_GET_OUTPUT;
wire unnamedbinop7569_readingUSEDMULTIPLEbinop;assign unnamedbinop7569_readingUSEDMULTIPLEbinop = {(phase_GET_OUTPUT==(16'd0))};
assign ready = unnamedbinop7569_readingUSEDMULTIPLEbinop;
reg [31:0] SR_2;
wire [31:0] unnamedselect7579USEDMULTIPLEselect;assign unnamedselect7579USEDMULTIPLEselect = ((unnamedbinop7569_readingUSEDMULTIPLEbinop)?(({process_input[31:0]})):(SR_2));
reg [31:0] unnamedselect7579_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedselect7579_delay1_validunnamednull0_CECE <= unnamedselect7579USEDMULTIPLEselect; end end
reg [31:0] SR_1; always @ (posedge CLK) begin if (process_valid && CE) begin SR_1 <= unnamedselect7579USEDMULTIPLEselect; end end
always @ (posedge CLK) begin if (process_valid && CE) begin SR_2 <= ((unnamedbinop7569_readingUSEDMULTIPLEbinop)?(({process_input[63:32]})):(SR_1)); end end
wire [15:0] phase_SETBY_OUTPUT;
assign process_output = {(1'd1),unnamedselect7579_delay1_validunnamednull0_CECE};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
RegBy_sumwrap_uint16_to1_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_phase"})) phase(.CLK(CLK), .set_valid(reset), .CE(CE), .set_inp((16'd0)), .setby_valid(process_valid), .setby_inp((16'd1)), .SETBY_OUTPUT(phase_SETBY_OUTPUT), .GET_OUTPUT(phase_GET_OUTPUT));
endmodule
module WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1(input CLK, output ready, input reset, input CE, input process_valid, input [64:0] process_input, output [32:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
wire WaitOnInput_inner_ready;
assign ready = WaitOnInput_inner_ready;
wire unnamedbinop7657USEDMULTIPLEbinop;assign unnamedbinop7657USEDMULTIPLEbinop = {({({(~WaitOnInput_inner_ready)}||(process_input[64]))}&&process_valid)};
wire [32:0] WaitOnInput_inner_process_output;
reg unnamedbinop7657_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedbinop7657_delay1_validunnamednull0_CECE <= unnamedbinop7657USEDMULTIPLEbinop; end end
assign process_output = {{((WaitOnInput_inner_process_output[32])&&unnamedbinop7657_delay1_validunnamednull0_CECE)},(WaitOnInput_inner_process_output[31:0])};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
ChangeRate_uint8_2_1__from4_to2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_WaitOnInput_inner"})) WaitOnInput_inner(.CLK(CLK), .ready(WaitOnInput_inner_ready), .reset(reset), .CE(CE), .process_valid(unnamedbinop7657USEDMULTIPLEbinop), .process_input((process_input[63:0])), .process_output(WaitOnInput_inner_process_output));
endmodule
module LiftHandshake_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1(input CLK, input ready_downstream, output ready, input reset, input [64:0] process_input, output [32:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire inner_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_ready;
assign ready = {(inner_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_ready&&ready_downstream)};
wire unnamedbinop7692USEDMULTIPLEbinop;assign unnamedbinop7692USEDMULTIPLEbinop = {(reset||ready_downstream)};
wire unnamedunary7693USEDMULTIPLEunary;assign unnamedunary7693USEDMULTIPLEunary = {(~reset)};
wire [32:0] inner_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_process_output;
wire validBitDelay_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_pushPop_out;
wire [32:0] unnamedtuple7703USEDMULTIPLEtuple;assign unnamedtuple7703USEDMULTIPLEtuple = {{((inner_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_process_output[32])&&validBitDelay_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_pushPop_out)},(inner_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_process_output[31:0])};
always @(posedge CLK) begin if({(~{((unnamedtuple7703USEDMULTIPLEtuple[32])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: output valid bit should not be X!",INSTANCE_NAME); end end
always @(posedge CLK) begin if({(~{((process_input[64])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign process_output = unnamedtuple7703USEDMULTIPLEtuple;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1"})) inner_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1(.CLK(CLK), .ready(inner_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_ready), .reset(reset), .CE(unnamedbinop7692USEDMULTIPLEbinop), .process_valid(unnamedunary7693USEDMULTIPLEunary), .process_input(process_input), .process_output(inner_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_process_output));
ShiftRegister_1_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_validBitDelay_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1"})) validBitDelay_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1(.CLK(CLK), .pushPop_valid(unnamedunary7693USEDMULTIPLEunary), .CE(unnamedbinop7692USEDMULTIPLEbinop), .sr_input((1'd1)), .pushPop_out(validBitDelay_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1_pushPop_out), .reset(reset));
endmodule
module slice_typeuint8_2_1__xl0_xh0_yl0_yh0(input CLK, input process_CE, input [15:0] inp, output [7:0] process_output);
parameter INSTANCE_NAME="INST";
assign process_output = ({inp[7:0]});
// function: process pure=true delay=0
endmodule
module map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1(input CLK, input process_CE, input [31:0] process_input, output [15:0] process_output);
parameter INSTANCE_NAME="INST";
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output,inner0_0_process_output};
// function: process pure=true delay=0
slice_typeuint8_2_1__xl0_xh0_yl0_yh0 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_0"})) inner0_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[15:0]})), .process_output(inner0_0_process_output));
slice_typeuint8_2_1__xl0_xh0_yl0_yh0 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_0"})) inner1_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[31:16]})), .process_output(inner1_0_process_output));
endmodule
module MakeHandshake_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1(input CLK, input ready_downstream, output ready, input reset, input [32:0] process_input, output [16:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
assign ready = ready_downstream;
wire unnamedbinop7761USEDMULTIPLEbinop;assign unnamedbinop7761USEDMULTIPLEbinop = {(ready_downstream||reset)};
wire unnamedcast7769USEDMULTIPLEcast;assign unnamedcast7769USEDMULTIPLEcast = (process_input[32]);
wire [15:0] inner_process_output;
wire validBitDelay_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1_pushPop_out;
always @(posedge CLK) begin if({(~{(unnamedcast7769USEDMULTIPLEcast===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: MakeHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign process_output = {validBitDelay_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1_pushPop_out,inner_process_output};
// function: ready pure=true ONLY WIRE
// function: reset pure=true ONLY WIRE
// function: process pure=false ONLY WIRE
ShiftRegister_0_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_validBitDelay_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1"})) validBitDelay_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1(.CLK(CLK), .CE(unnamedbinop7761USEDMULTIPLEbinop), .sr_input(unnamedcast7769USEDMULTIPLEcast), .pushPop_out(validBitDelay_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1_pushPop_out));
map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner"})) inner(.CLK(CLK), .process_CE(unnamedbinop7761USEDMULTIPLEbinop), .process_input((process_input[31:0])), .process_output(inner_process_output));
endmodule
module incif_wrapuint8_127_incnil(input CLK, input CE, input [8:0] process_input, output [7:0] process_output);
parameter INSTANCE_NAME="INST";
wire [7:0] unnamedcast394USEDMULTIPLEcast;assign unnamedcast394USEDMULTIPLEcast = (process_input[7:0]);
assign process_output = (((process_input[8]))?((({(unnamedcast394USEDMULTIPLEcast==(8'd127))})?((8'd0)):({(unnamedcast394USEDMULTIPLEcast+(8'd1))}))):(unnamedcast394USEDMULTIPLEcast));
// function: process pure=true delay=0
endmodule
module RegBy_incif_wrapuint8_127_incnil_CEtrue_initnil(input CLK, input set_valid, input CE, input [7:0] set_inp, input setby_valid, input setby_inp, output [7:0] SETBY_OUTPUT, output [7:0] GET_OUTPUT);
parameter INSTANCE_NAME="INST";
reg [7:0] R;
wire [7:0] regby_inner_process_output;
always @(posedge CLK) begin if(set_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(setby_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,set_valid})+({4'b0,setby_valid})) > 5'd1) begin $display("error, function 'set' on instance 'R' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [8:0] unnamedcallArbitrate445USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate445USEDMULTIPLEcallArbitrate = {(set_valid||setby_valid),((set_valid)?(set_inp):(regby_inner_process_output))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate445USEDMULTIPLEcallArbitrate[8]) && CE) begin R <= (unnamedcallArbitrate445USEDMULTIPLEcallArbitrate[7:0]); end end
assign SETBY_OUTPUT = regby_inner_process_output;
assign GET_OUTPUT = R;
// function: set pure=false ONLY WIRE
// function: setby pure=false ONLY WIRE
// function: get pure=true ONLY WIRE
incif_wrapuint8_127_incnil #(.INSTANCE_NAME({INSTANCE_NAME,"_regby_inner"})) regby_inner(.CLK(CLK), .CE(CE), .process_input({setby_inp,R}), .process_output(regby_inner_process_output));
endmodule
module fifo_uint8_2_1__128(input CLK, input popFront_valid, input CE_pop, output [15:0] popFront, output [7:0] size, input pushBackReset_valid, input CE_push, output ready, input pushBack_valid, input [15:0] pushBack_input, input popFrontReset_valid, output hasData);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(popFront_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'popFront'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(pushBackReset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'pushBackReset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(pushBack_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'pushBack'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(popFrontReset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'popFrontReset'", INSTANCE_NAME); end end
wire [7:0] readAddr_GET_OUTPUT;
wire [6:0] unnamedcast561USEDMULTIPLEcast;assign unnamedcast561USEDMULTIPLEcast = readAddr_GET_OUTPUT[6:0];
wire fifo1_READ_OUTPUT;
wire fifo2_READ_OUTPUT;
wire fifo3_READ_OUTPUT;
wire fifo4_READ_OUTPUT;
wire fifo5_READ_OUTPUT;
wire fifo6_READ_OUTPUT;
wire fifo7_READ_OUTPUT;
wire fifo8_READ_OUTPUT;
wire fifo9_READ_OUTPUT;
wire fifo10_READ_OUTPUT;
wire fifo11_READ_OUTPUT;
wire fifo12_READ_OUTPUT;
wire fifo13_READ_OUTPUT;
wire fifo14_READ_OUTPUT;
wire fifo15_READ_OUTPUT;
wire fifo16_READ_OUTPUT;
wire [7:0] writeAddr_GET_OUTPUT;
wire unnamedunary468USEDMULTIPLEunary;assign unnamedunary468USEDMULTIPLEunary = {(~{(writeAddr_GET_OUTPUT==readAddr_GET_OUTPUT)})};
always @(posedge CLK) begin if(unnamedunary468USEDMULTIPLEunary == 1'b0 && popFront_valid==1'b1 && CE_pop==1'b1) begin $display("%s: attempting to pop from an empty fifo",INSTANCE_NAME);$finish(); end end
wire [7:0] readAddr_SETBY_OUTPUT;
assign popFront = {fifo16_READ_OUTPUT,fifo15_READ_OUTPUT,fifo14_READ_OUTPUT,fifo13_READ_OUTPUT,fifo12_READ_OUTPUT,fifo11_READ_OUTPUT,fifo10_READ_OUTPUT,fifo9_READ_OUTPUT,fifo8_READ_OUTPUT,fifo7_READ_OUTPUT,fifo6_READ_OUTPUT,fifo5_READ_OUTPUT,fifo4_READ_OUTPUT,fifo3_READ_OUTPUT,fifo2_READ_OUTPUT,fifo1_READ_OUTPUT};
wire [7:0] unnamedselect459USEDMULTIPLEselect;assign unnamedselect459USEDMULTIPLEselect = (({((writeAddr_GET_OUTPUT)<(readAddr_GET_OUTPUT))})?({({((8'd128)-readAddr_GET_OUTPUT)}+writeAddr_GET_OUTPUT)}):({(writeAddr_GET_OUTPUT-readAddr_GET_OUTPUT)}));
assign size = unnamedselect459USEDMULTIPLEselect;
reg readyReg;
always @ (posedge CLK) begin readyReg <= {((unnamedselect459USEDMULTIPLEselect)<((8'd125)))}; end
assign ready = readyReg;
always @(posedge CLK) begin if({((unnamedselect459USEDMULTIPLEselect)<((8'd126)))} == 1'b0 && pushBack_valid==1'b1 && CE_push==1'b1) begin $display("%s: attempting to push to a full fifo",INSTANCE_NAME);$finish(); end end
wire [7:0] writeAddr_SETBY_OUTPUT;
wire [6:0] unnamedcast476USEDMULTIPLEcast;assign unnamedcast476USEDMULTIPLEcast = writeAddr_GET_OUTPUT[6:0];
assign hasData = unnamedunary468USEDMULTIPLEunary;
// function: popFront pure=false delay=0
// function: size pure=true delay=0
// function: pushBackReset pure=false delay=0
// function: ready pure=true delay=0
// function: pushBack pure=false delay=0
// function: popFrontReset pure=false delay=0
// function: hasData pure=true delay=0
RegBy_incif_wrapuint8_127_incnil_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_writeAddr"})) writeAddr(.CLK(CLK), .set_valid(pushBackReset_valid), .CE(CE_push), .set_inp((8'd0)), .setby_valid(pushBack_valid), .setby_inp((1'd1)), .SETBY_OUTPUT(writeAddr_SETBY_OUTPUT), .GET_OUTPUT(writeAddr_GET_OUTPUT));
RegBy_incif_wrapuint8_127_incnil_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_readAddr"})) readAddr(.CLK(CLK), .set_valid(popFrontReset_valid), .CE(CE_pop), .set_inp((8'd0)), .setby_valid(popFront_valid), .setby_inp((1'd1)), .SETBY_OUTPUT(readAddr_SETBY_OUTPUT), .GET_OUTPUT(readAddr_GET_OUTPUT));
wire [7:0] fifo1_writeInput = {pushBack_input[0:0],unnamedcast476USEDMULTIPLEcast};
wire fifo1_writeOut;
RAM128X1D fifo1 (
.WCLK(CLK),
.D(fifo1_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo1_writeOut),
.DPO(fifo1_READ_OUTPUT),
.A(fifo1_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo2_writeInput = {pushBack_input[1:1],unnamedcast476USEDMULTIPLEcast};
wire fifo2_writeOut;
RAM128X1D fifo2 (
.WCLK(CLK),
.D(fifo2_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo2_writeOut),
.DPO(fifo2_READ_OUTPUT),
.A(fifo2_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo3_writeInput = {pushBack_input[2:2],unnamedcast476USEDMULTIPLEcast};
wire fifo3_writeOut;
RAM128X1D fifo3 (
.WCLK(CLK),
.D(fifo3_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo3_writeOut),
.DPO(fifo3_READ_OUTPUT),
.A(fifo3_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo4_writeInput = {pushBack_input[3:3],unnamedcast476USEDMULTIPLEcast};
wire fifo4_writeOut;
RAM128X1D fifo4 (
.WCLK(CLK),
.D(fifo4_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo4_writeOut),
.DPO(fifo4_READ_OUTPUT),
.A(fifo4_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo5_writeInput = {pushBack_input[4:4],unnamedcast476USEDMULTIPLEcast};
wire fifo5_writeOut;
RAM128X1D fifo5 (
.WCLK(CLK),
.D(fifo5_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo5_writeOut),
.DPO(fifo5_READ_OUTPUT),
.A(fifo5_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo6_writeInput = {pushBack_input[5:5],unnamedcast476USEDMULTIPLEcast};
wire fifo6_writeOut;
RAM128X1D fifo6 (
.WCLK(CLK),
.D(fifo6_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo6_writeOut),
.DPO(fifo6_READ_OUTPUT),
.A(fifo6_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo7_writeInput = {pushBack_input[6:6],unnamedcast476USEDMULTIPLEcast};
wire fifo7_writeOut;
RAM128X1D fifo7 (
.WCLK(CLK),
.D(fifo7_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo7_writeOut),
.DPO(fifo7_READ_OUTPUT),
.A(fifo7_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo8_writeInput = {pushBack_input[7:7],unnamedcast476USEDMULTIPLEcast};
wire fifo8_writeOut;
RAM128X1D fifo8 (
.WCLK(CLK),
.D(fifo8_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo8_writeOut),
.DPO(fifo8_READ_OUTPUT),
.A(fifo8_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo9_writeInput = {pushBack_input[8:8],unnamedcast476USEDMULTIPLEcast};
wire fifo9_writeOut;
RAM128X1D fifo9 (
.WCLK(CLK),
.D(fifo9_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo9_writeOut),
.DPO(fifo9_READ_OUTPUT),
.A(fifo9_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo10_writeInput = {pushBack_input[9:9],unnamedcast476USEDMULTIPLEcast};
wire fifo10_writeOut;
RAM128X1D fifo10 (
.WCLK(CLK),
.D(fifo10_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo10_writeOut),
.DPO(fifo10_READ_OUTPUT),
.A(fifo10_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo11_writeInput = {pushBack_input[10:10],unnamedcast476USEDMULTIPLEcast};
wire fifo11_writeOut;
RAM128X1D fifo11 (
.WCLK(CLK),
.D(fifo11_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo11_writeOut),
.DPO(fifo11_READ_OUTPUT),
.A(fifo11_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo12_writeInput = {pushBack_input[11:11],unnamedcast476USEDMULTIPLEcast};
wire fifo12_writeOut;
RAM128X1D fifo12 (
.WCLK(CLK),
.D(fifo12_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo12_writeOut),
.DPO(fifo12_READ_OUTPUT),
.A(fifo12_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo13_writeInput = {pushBack_input[12:12],unnamedcast476USEDMULTIPLEcast};
wire fifo13_writeOut;
RAM128X1D fifo13 (
.WCLK(CLK),
.D(fifo13_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo13_writeOut),
.DPO(fifo13_READ_OUTPUT),
.A(fifo13_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo14_writeInput = {pushBack_input[13:13],unnamedcast476USEDMULTIPLEcast};
wire fifo14_writeOut;
RAM128X1D fifo14 (
.WCLK(CLK),
.D(fifo14_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo14_writeOut),
.DPO(fifo14_READ_OUTPUT),
.A(fifo14_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo15_writeInput = {pushBack_input[14:14],unnamedcast476USEDMULTIPLEcast};
wire fifo15_writeOut;
RAM128X1D fifo15 (
.WCLK(CLK),
.D(fifo15_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo15_writeOut),
.DPO(fifo15_READ_OUTPUT),
.A(fifo15_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
wire [7:0] fifo16_writeInput = {pushBack_input[15:15],unnamedcast476USEDMULTIPLEcast};
wire fifo16_writeOut;
RAM128X1D fifo16 (
.WCLK(CLK),
.D(fifo16_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo16_writeOut),
.DPO(fifo16_READ_OUTPUT),
.A(fifo16_writeInput[6:0]),
.DPRA(unnamedcast561USEDMULTIPLEcast));
endmodule
module fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256(input CLK, input load_valid, input load_CE, output [16:0] load_output, input store_reset_valid, input store_CE, output store_ready, input load_reset_valid, input store_valid, input [15:0] store_input);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(load_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_reset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(load_reset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME); end end
wire FIFO_hasData;
wire [15:0] FIFO_popFront;
assign load_output = {FIFO_hasData,FIFO_popFront};
wire FIFO_ready;
assign store_ready = FIFO_ready;
// function: load pure=false delay=0
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_uint8_2_1__128 #(.INSTANCE_NAME({INSTANCE_NAME,"_FIFO"})) FIFO(.CLK(CLK), .popFront_valid({(FIFO_hasData&&load_valid)}), .CE_pop(load_CE), .popFront(FIFO_popFront), .size(FIFO_size), .pushBackReset_valid(store_reset_valid), .CE_push(store_CE), .ready(FIFO_ready), .pushBack_valid(store_valid), .pushBack_input(store_input), .popFrontReset_valid(load_reset_valid), .hasData(FIFO_hasData));
endmodule
module LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256(input CLK, input load_valid, input load_CE, input load_input, output [16:0] load_output, input store_reset_valid, input store_CE, output store_ready, output load_ready, input load_reset, input store_valid, input [15:0] store_input);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(load_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_reset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(load_reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME); end end
wire unnamedcast940USEDMULTIPLEcast;assign unnamedcast940USEDMULTIPLEcast = load_input;
wire [16:0] LiftDecimate_load_output;
reg [15:0] unnamedcast943_delay1_validunnamednull0_CEload_CE; always @ (posedge CLK) begin if (load_CE) begin unnamedcast943_delay1_validunnamednull0_CEload_CE <= (LiftDecimate_load_output[15:0]); end end
reg unnamedbinop948_delay1_validunnamednull0_CEload_CE; always @ (posedge CLK) begin if (load_CE) begin unnamedbinop948_delay1_validunnamednull0_CEload_CE <= {((LiftDecimate_load_output[16])&&unnamedcast940USEDMULTIPLEcast)}; end end
assign load_output = {unnamedbinop948_delay1_validunnamednull0_CEload_CE,unnamedcast943_delay1_validunnamednull0_CEload_CE};
wire LiftDecimate_store_ready;
assign store_ready = LiftDecimate_store_ready;
assign load_ready = (1'd1);
// function: load pure=false delay=1
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 #(.INSTANCE_NAME({INSTANCE_NAME,"_LiftDecimate"})) LiftDecimate(.CLK(CLK), .load_valid({(unnamedcast940USEDMULTIPLEcast&&load_valid)}), .load_CE(load_CE), .load_output(LiftDecimate_load_output), .store_reset_valid(store_reset_valid), .store_CE(store_CE), .store_ready(LiftDecimate_store_ready), .load_reset_valid(load_reset), .store_valid(store_valid), .store_input(store_input));
endmodule
module RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256(input CLK, input load_valid, input load_CE, input load_input, output [16:0] load_output, input store_reset, input CE, output store_ready, output load_ready, input load_reset, input store_valid, input [16:0] store_input, output store_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(load_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(load_reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME); end end
wire [16:0] RunIffReady_load_output;
assign load_output = RunIffReady_load_output;
wire RunIffReady_store_ready;
assign store_ready = RunIffReady_store_ready;
wire RunIffReady_load_ready;
assign load_ready = RunIffReady_load_ready;
wire unnamedbinop1019USEDMULTIPLEbinop;assign unnamedbinop1019USEDMULTIPLEbinop = {({(RunIffReady_store_ready&&(store_input[16]))}&&store_valid)};
assign store_output = {unnamedbinop1019USEDMULTIPLEbinop};
// function: load pure=false delay=1
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 #(.INSTANCE_NAME({INSTANCE_NAME,"_RunIffReady"})) RunIffReady(.CLK(CLK), .load_valid(load_valid), .load_CE(load_CE), .load_input(load_input), .load_output(RunIffReady_load_output), .store_reset_valid(store_reset), .store_CE(CE), .store_ready(RunIffReady_store_ready), .load_ready(RunIffReady_load_ready), .load_reset(load_reset), .store_valid(unnamedbinop1019USEDMULTIPLEbinop), .store_input((store_input[15:0])));
endmodule
module LiftHandshake_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256(input CLK, input load_input, output [16:0] load_output, input store_reset, input store_ready_downstream, output store_ready, input load_ready_downstream, output load_ready, input load_reset, input [16:0] store_input, output store_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire unnamedunary1056USEDMULTIPLEunary;assign unnamedunary1056USEDMULTIPLEunary = {(~load_reset)};
wire unnamedbinop1055USEDMULTIPLEbinop;assign unnamedbinop1055USEDMULTIPLEbinop = {(load_reset||load_ready_downstream)};
wire [16:0] inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_load_output;
wire load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_pushPop_out;
wire [16:0] unnamedtuple1066USEDMULTIPLEtuple;assign unnamedtuple1066USEDMULTIPLEtuple = {{((inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_load_output[16])&&load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_pushPop_out)},(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_load_output[15:0])};
always @(posedge CLK) begin if({(~{((unnamedtuple1066USEDMULTIPLEtuple[16])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: output valid bit should not be X!",INSTANCE_NAME); end end
always @(posedge CLK) begin if({(~{(load_input===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign load_output = unnamedtuple1066USEDMULTIPLEtuple;
wire unnamedbinop1084USEDMULTIPLEbinop;assign unnamedbinop1084USEDMULTIPLEbinop = {(store_reset||store_ready_downstream)};
wire inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_store_ready;
assign store_ready = {(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_store_ready&&store_ready_downstream)};
wire inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_load_ready;
assign load_ready = {(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_load_ready&&load_ready_downstream)};
wire unnamedunary1085USEDMULTIPLEunary;assign unnamedunary1085USEDMULTIPLEunary = {(~store_reset)};
wire [0:0] inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_store_output;
wire store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_pushPop_out;
wire [0:0] unnamedtuple1099USEDMULTIPLEtuple;assign unnamedtuple1099USEDMULTIPLEtuple = {{(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_store_output&&store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_pushPop_out)}};
always @(posedge CLK) begin if({(~{(unnamedtuple1099USEDMULTIPLEtuple===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: output valid bit should not be X!",INSTANCE_NAME); end end
always @(posedge CLK) begin if({(~{((store_input[16])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign store_output = unnamedtuple1099USEDMULTIPLEtuple;
// function: load pure=false ONLY WIRE
// function: store_reset pure=false ONLY WIRE
// function: store_ready pure=true ONLY WIRE
// function: load_ready pure=true ONLY WIRE
// function: load_reset pure=false ONLY WIRE
// function: store pure=false ONLY WIRE
RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256"})) inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256(.CLK(CLK), .load_valid(unnamedunary1056USEDMULTIPLEunary), .load_CE(unnamedbinop1055USEDMULTIPLEbinop), .load_input(load_input), .load_output(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_load_output), .store_reset(store_reset), .CE(unnamedbinop1084USEDMULTIPLEbinop), .store_ready(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_store_ready), .load_ready(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_load_ready), .load_reset(load_reset), .store_valid(unnamedunary1085USEDMULTIPLEunary), .store_input(store_input), .store_output(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_store_output));
ShiftRegister_1_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256"})) load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256(.CLK(CLK), .pushPop_valid(unnamedunary1056USEDMULTIPLEunary), .CE(unnamedbinop1055USEDMULTIPLEbinop), .sr_input((1'd1)), .pushPop_out(load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_pushPop_out), .reset(load_reset));
ShiftRegister_0_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256"})) store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256(.CLK(CLK), .CE(unnamedbinop1084USEDMULTIPLEbinop), .sr_input((1'd1)), .pushPop_out(store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256_pushPop_out));
endmodule
module fifo_uint8_4_1__2_1__128(input CLK, input popFront_valid, input CE_pop, output [63:0] popFront, output [7:0] size, input pushBackReset_valid, input CE_push, output ready, input pushBack_valid, input [63:0] pushBack_input, input popFrontReset_valid, output hasData);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(popFront_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'popFront'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(pushBackReset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'pushBackReset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(pushBack_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'pushBack'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(popFrontReset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'popFrontReset'", INSTANCE_NAME); end end
wire [7:0] readAddr_GET_OUTPUT;
wire [6:0] unnamedcast6180USEDMULTIPLEcast;assign unnamedcast6180USEDMULTIPLEcast = readAddr_GET_OUTPUT[6:0];
wire fifo1_READ_OUTPUT;
wire fifo2_READ_OUTPUT;
wire fifo3_READ_OUTPUT;
wire fifo4_READ_OUTPUT;
wire fifo5_READ_OUTPUT;
wire fifo6_READ_OUTPUT;
wire fifo7_READ_OUTPUT;
wire fifo8_READ_OUTPUT;
wire fifo9_READ_OUTPUT;
wire fifo10_READ_OUTPUT;
wire fifo11_READ_OUTPUT;
wire fifo12_READ_OUTPUT;
wire fifo13_READ_OUTPUT;
wire fifo14_READ_OUTPUT;
wire fifo15_READ_OUTPUT;
wire fifo16_READ_OUTPUT;
wire fifo17_READ_OUTPUT;
wire fifo18_READ_OUTPUT;
wire fifo19_READ_OUTPUT;
wire fifo20_READ_OUTPUT;
wire fifo21_READ_OUTPUT;
wire fifo22_READ_OUTPUT;
wire fifo23_READ_OUTPUT;
wire fifo24_READ_OUTPUT;
wire fifo25_READ_OUTPUT;
wire fifo26_READ_OUTPUT;
wire fifo27_READ_OUTPUT;
wire fifo28_READ_OUTPUT;
wire fifo29_READ_OUTPUT;
wire fifo30_READ_OUTPUT;
wire fifo31_READ_OUTPUT;
wire fifo32_READ_OUTPUT;
wire fifo33_READ_OUTPUT;
wire fifo34_READ_OUTPUT;
wire fifo35_READ_OUTPUT;
wire fifo36_READ_OUTPUT;
wire fifo37_READ_OUTPUT;
wire fifo38_READ_OUTPUT;
wire fifo39_READ_OUTPUT;
wire fifo40_READ_OUTPUT;
wire fifo41_READ_OUTPUT;
wire fifo42_READ_OUTPUT;
wire fifo43_READ_OUTPUT;
wire fifo44_READ_OUTPUT;
wire fifo45_READ_OUTPUT;
wire fifo46_READ_OUTPUT;
wire fifo47_READ_OUTPUT;
wire fifo48_READ_OUTPUT;
wire fifo49_READ_OUTPUT;
wire fifo50_READ_OUTPUT;
wire fifo51_READ_OUTPUT;
wire fifo52_READ_OUTPUT;
wire fifo53_READ_OUTPUT;
wire fifo54_READ_OUTPUT;
wire fifo55_READ_OUTPUT;
wire fifo56_READ_OUTPUT;
wire fifo57_READ_OUTPUT;
wire fifo58_READ_OUTPUT;
wire fifo59_READ_OUTPUT;
wire fifo60_READ_OUTPUT;
wire fifo61_READ_OUTPUT;
wire fifo62_READ_OUTPUT;
wire fifo63_READ_OUTPUT;
wire fifo64_READ_OUTPUT;
wire [7:0] writeAddr_GET_OUTPUT;
wire unnamedunary5847USEDMULTIPLEunary;assign unnamedunary5847USEDMULTIPLEunary = {(~{(writeAddr_GET_OUTPUT==readAddr_GET_OUTPUT)})};
always @(posedge CLK) begin if(unnamedunary5847USEDMULTIPLEunary == 1'b0 && popFront_valid==1'b1 && CE_pop==1'b1) begin $display("%s: attempting to pop from an empty fifo",INSTANCE_NAME);$finish(); end end
wire [7:0] readAddr_SETBY_OUTPUT;
assign popFront = {fifo64_READ_OUTPUT,fifo63_READ_OUTPUT,fifo62_READ_OUTPUT,fifo61_READ_OUTPUT,fifo60_READ_OUTPUT,fifo59_READ_OUTPUT,fifo58_READ_OUTPUT,fifo57_READ_OUTPUT,fifo56_READ_OUTPUT,fifo55_READ_OUTPUT,fifo54_READ_OUTPUT,fifo53_READ_OUTPUT,fifo52_READ_OUTPUT,fifo51_READ_OUTPUT,fifo50_READ_OUTPUT,fifo49_READ_OUTPUT,fifo48_READ_OUTPUT,fifo47_READ_OUTPUT,fifo46_READ_OUTPUT,fifo45_READ_OUTPUT,fifo44_READ_OUTPUT,fifo43_READ_OUTPUT,fifo42_READ_OUTPUT,fifo41_READ_OUTPUT,fifo40_READ_OUTPUT,fifo39_READ_OUTPUT,fifo38_READ_OUTPUT,fifo37_READ_OUTPUT,fifo36_READ_OUTPUT,fifo35_READ_OUTPUT,fifo34_READ_OUTPUT,fifo33_READ_OUTPUT,fifo32_READ_OUTPUT,fifo31_READ_OUTPUT,fifo30_READ_OUTPUT,fifo29_READ_OUTPUT,fifo28_READ_OUTPUT,fifo27_READ_OUTPUT,fifo26_READ_OUTPUT,fifo25_READ_OUTPUT,fifo24_READ_OUTPUT,fifo23_READ_OUTPUT,fifo22_READ_OUTPUT,fifo21_READ_OUTPUT,fifo20_READ_OUTPUT,fifo19_READ_OUTPUT,fifo18_READ_OUTPUT,fifo17_READ_OUTPUT,fifo16_READ_OUTPUT,fifo15_READ_OUTPUT,fifo14_READ_OUTPUT,fifo13_READ_OUTPUT,fifo12_READ_OUTPUT,fifo11_READ_OUTPUT,fifo10_READ_OUTPUT,fifo9_READ_OUTPUT,fifo8_READ_OUTPUT,fifo7_READ_OUTPUT,fifo6_READ_OUTPUT,fifo5_READ_OUTPUT,fifo4_READ_OUTPUT,fifo3_READ_OUTPUT,fifo2_READ_OUTPUT,fifo1_READ_OUTPUT};
wire [7:0] unnamedselect5838USEDMULTIPLEselect;assign unnamedselect5838USEDMULTIPLEselect = (({((writeAddr_GET_OUTPUT)<(readAddr_GET_OUTPUT))})?({({((8'd128)-readAddr_GET_OUTPUT)}+writeAddr_GET_OUTPUT)}):({(writeAddr_GET_OUTPUT-readAddr_GET_OUTPUT)}));
assign size = unnamedselect5838USEDMULTIPLEselect;
reg readyReg;
always @ (posedge CLK) begin readyReg <= {((unnamedselect5838USEDMULTIPLEselect)<((8'd125)))}; end
assign ready = readyReg;
always @(posedge CLK) begin if({((unnamedselect5838USEDMULTIPLEselect)<((8'd126)))} == 1'b0 && pushBack_valid==1'b1 && CE_push==1'b1) begin $display("%s: attempting to push to a full fifo",INSTANCE_NAME);$finish(); end end
wire [7:0] writeAddr_SETBY_OUTPUT;
wire [6:0] unnamedcast5855USEDMULTIPLEcast;assign unnamedcast5855USEDMULTIPLEcast = writeAddr_GET_OUTPUT[6:0];
assign hasData = unnamedunary5847USEDMULTIPLEunary;
// function: popFront pure=false delay=0
// function: size pure=true delay=0
// function: pushBackReset pure=false delay=0
// function: ready pure=true delay=0
// function: pushBack pure=false delay=0
// function: popFrontReset pure=false delay=0
// function: hasData pure=true delay=0
RegBy_incif_wrapuint8_127_incnil_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_writeAddr"})) writeAddr(.CLK(CLK), .set_valid(pushBackReset_valid), .CE(CE_push), .set_inp((8'd0)), .setby_valid(pushBack_valid), .setby_inp((1'd1)), .SETBY_OUTPUT(writeAddr_SETBY_OUTPUT), .GET_OUTPUT(writeAddr_GET_OUTPUT));
RegBy_incif_wrapuint8_127_incnil_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_readAddr"})) readAddr(.CLK(CLK), .set_valid(popFrontReset_valid), .CE(CE_pop), .set_inp((8'd0)), .setby_valid(popFront_valid), .setby_inp((1'd1)), .SETBY_OUTPUT(readAddr_SETBY_OUTPUT), .GET_OUTPUT(readAddr_GET_OUTPUT));
wire [7:0] fifo1_writeInput = {pushBack_input[0:0],unnamedcast5855USEDMULTIPLEcast};
wire fifo1_writeOut;
RAM128X1D fifo1 (
.WCLK(CLK),
.D(fifo1_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo1_writeOut),
.DPO(fifo1_READ_OUTPUT),
.A(fifo1_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo2_writeInput = {pushBack_input[1:1],unnamedcast5855USEDMULTIPLEcast};
wire fifo2_writeOut;
RAM128X1D fifo2 (
.WCLK(CLK),
.D(fifo2_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo2_writeOut),
.DPO(fifo2_READ_OUTPUT),
.A(fifo2_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo3_writeInput = {pushBack_input[2:2],unnamedcast5855USEDMULTIPLEcast};
wire fifo3_writeOut;
RAM128X1D fifo3 (
.WCLK(CLK),
.D(fifo3_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo3_writeOut),
.DPO(fifo3_READ_OUTPUT),
.A(fifo3_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo4_writeInput = {pushBack_input[3:3],unnamedcast5855USEDMULTIPLEcast};
wire fifo4_writeOut;
RAM128X1D fifo4 (
.WCLK(CLK),
.D(fifo4_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo4_writeOut),
.DPO(fifo4_READ_OUTPUT),
.A(fifo4_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo5_writeInput = {pushBack_input[4:4],unnamedcast5855USEDMULTIPLEcast};
wire fifo5_writeOut;
RAM128X1D fifo5 (
.WCLK(CLK),
.D(fifo5_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo5_writeOut),
.DPO(fifo5_READ_OUTPUT),
.A(fifo5_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo6_writeInput = {pushBack_input[5:5],unnamedcast5855USEDMULTIPLEcast};
wire fifo6_writeOut;
RAM128X1D fifo6 (
.WCLK(CLK),
.D(fifo6_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo6_writeOut),
.DPO(fifo6_READ_OUTPUT),
.A(fifo6_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo7_writeInput = {pushBack_input[6:6],unnamedcast5855USEDMULTIPLEcast};
wire fifo7_writeOut;
RAM128X1D fifo7 (
.WCLK(CLK),
.D(fifo7_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo7_writeOut),
.DPO(fifo7_READ_OUTPUT),
.A(fifo7_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo8_writeInput = {pushBack_input[7:7],unnamedcast5855USEDMULTIPLEcast};
wire fifo8_writeOut;
RAM128X1D fifo8 (
.WCLK(CLK),
.D(fifo8_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo8_writeOut),
.DPO(fifo8_READ_OUTPUT),
.A(fifo8_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo9_writeInput = {pushBack_input[8:8],unnamedcast5855USEDMULTIPLEcast};
wire fifo9_writeOut;
RAM128X1D fifo9 (
.WCLK(CLK),
.D(fifo9_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo9_writeOut),
.DPO(fifo9_READ_OUTPUT),
.A(fifo9_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo10_writeInput = {pushBack_input[9:9],unnamedcast5855USEDMULTIPLEcast};
wire fifo10_writeOut;
RAM128X1D fifo10 (
.WCLK(CLK),
.D(fifo10_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo10_writeOut),
.DPO(fifo10_READ_OUTPUT),
.A(fifo10_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo11_writeInput = {pushBack_input[10:10],unnamedcast5855USEDMULTIPLEcast};
wire fifo11_writeOut;
RAM128X1D fifo11 (
.WCLK(CLK),
.D(fifo11_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo11_writeOut),
.DPO(fifo11_READ_OUTPUT),
.A(fifo11_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo12_writeInput = {pushBack_input[11:11],unnamedcast5855USEDMULTIPLEcast};
wire fifo12_writeOut;
RAM128X1D fifo12 (
.WCLK(CLK),
.D(fifo12_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo12_writeOut),
.DPO(fifo12_READ_OUTPUT),
.A(fifo12_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo13_writeInput = {pushBack_input[12:12],unnamedcast5855USEDMULTIPLEcast};
wire fifo13_writeOut;
RAM128X1D fifo13 (
.WCLK(CLK),
.D(fifo13_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo13_writeOut),
.DPO(fifo13_READ_OUTPUT),
.A(fifo13_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo14_writeInput = {pushBack_input[13:13],unnamedcast5855USEDMULTIPLEcast};
wire fifo14_writeOut;
RAM128X1D fifo14 (
.WCLK(CLK),
.D(fifo14_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo14_writeOut),
.DPO(fifo14_READ_OUTPUT),
.A(fifo14_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo15_writeInput = {pushBack_input[14:14],unnamedcast5855USEDMULTIPLEcast};
wire fifo15_writeOut;
RAM128X1D fifo15 (
.WCLK(CLK),
.D(fifo15_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo15_writeOut),
.DPO(fifo15_READ_OUTPUT),
.A(fifo15_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo16_writeInput = {pushBack_input[15:15],unnamedcast5855USEDMULTIPLEcast};
wire fifo16_writeOut;
RAM128X1D fifo16 (
.WCLK(CLK),
.D(fifo16_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo16_writeOut),
.DPO(fifo16_READ_OUTPUT),
.A(fifo16_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo17_writeInput = {pushBack_input[16:16],unnamedcast5855USEDMULTIPLEcast};
wire fifo17_writeOut;
RAM128X1D fifo17 (
.WCLK(CLK),
.D(fifo17_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo17_writeOut),
.DPO(fifo17_READ_OUTPUT),
.A(fifo17_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo18_writeInput = {pushBack_input[17:17],unnamedcast5855USEDMULTIPLEcast};
wire fifo18_writeOut;
RAM128X1D fifo18 (
.WCLK(CLK),
.D(fifo18_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo18_writeOut),
.DPO(fifo18_READ_OUTPUT),
.A(fifo18_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo19_writeInput = {pushBack_input[18:18],unnamedcast5855USEDMULTIPLEcast};
wire fifo19_writeOut;
RAM128X1D fifo19 (
.WCLK(CLK),
.D(fifo19_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo19_writeOut),
.DPO(fifo19_READ_OUTPUT),
.A(fifo19_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo20_writeInput = {pushBack_input[19:19],unnamedcast5855USEDMULTIPLEcast};
wire fifo20_writeOut;
RAM128X1D fifo20 (
.WCLK(CLK),
.D(fifo20_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo20_writeOut),
.DPO(fifo20_READ_OUTPUT),
.A(fifo20_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo21_writeInput = {pushBack_input[20:20],unnamedcast5855USEDMULTIPLEcast};
wire fifo21_writeOut;
RAM128X1D fifo21 (
.WCLK(CLK),
.D(fifo21_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo21_writeOut),
.DPO(fifo21_READ_OUTPUT),
.A(fifo21_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo22_writeInput = {pushBack_input[21:21],unnamedcast5855USEDMULTIPLEcast};
wire fifo22_writeOut;
RAM128X1D fifo22 (
.WCLK(CLK),
.D(fifo22_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo22_writeOut),
.DPO(fifo22_READ_OUTPUT),
.A(fifo22_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo23_writeInput = {pushBack_input[22:22],unnamedcast5855USEDMULTIPLEcast};
wire fifo23_writeOut;
RAM128X1D fifo23 (
.WCLK(CLK),
.D(fifo23_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo23_writeOut),
.DPO(fifo23_READ_OUTPUT),
.A(fifo23_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo24_writeInput = {pushBack_input[23:23],unnamedcast5855USEDMULTIPLEcast};
wire fifo24_writeOut;
RAM128X1D fifo24 (
.WCLK(CLK),
.D(fifo24_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo24_writeOut),
.DPO(fifo24_READ_OUTPUT),
.A(fifo24_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo25_writeInput = {pushBack_input[24:24],unnamedcast5855USEDMULTIPLEcast};
wire fifo25_writeOut;
RAM128X1D fifo25 (
.WCLK(CLK),
.D(fifo25_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo25_writeOut),
.DPO(fifo25_READ_OUTPUT),
.A(fifo25_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo26_writeInput = {pushBack_input[25:25],unnamedcast5855USEDMULTIPLEcast};
wire fifo26_writeOut;
RAM128X1D fifo26 (
.WCLK(CLK),
.D(fifo26_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo26_writeOut),
.DPO(fifo26_READ_OUTPUT),
.A(fifo26_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo27_writeInput = {pushBack_input[26:26],unnamedcast5855USEDMULTIPLEcast};
wire fifo27_writeOut;
RAM128X1D fifo27 (
.WCLK(CLK),
.D(fifo27_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo27_writeOut),
.DPO(fifo27_READ_OUTPUT),
.A(fifo27_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo28_writeInput = {pushBack_input[27:27],unnamedcast5855USEDMULTIPLEcast};
wire fifo28_writeOut;
RAM128X1D fifo28 (
.WCLK(CLK),
.D(fifo28_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo28_writeOut),
.DPO(fifo28_READ_OUTPUT),
.A(fifo28_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo29_writeInput = {pushBack_input[28:28],unnamedcast5855USEDMULTIPLEcast};
wire fifo29_writeOut;
RAM128X1D fifo29 (
.WCLK(CLK),
.D(fifo29_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo29_writeOut),
.DPO(fifo29_READ_OUTPUT),
.A(fifo29_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo30_writeInput = {pushBack_input[29:29],unnamedcast5855USEDMULTIPLEcast};
wire fifo30_writeOut;
RAM128X1D fifo30 (
.WCLK(CLK),
.D(fifo30_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo30_writeOut),
.DPO(fifo30_READ_OUTPUT),
.A(fifo30_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo31_writeInput = {pushBack_input[30:30],unnamedcast5855USEDMULTIPLEcast};
wire fifo31_writeOut;
RAM128X1D fifo31 (
.WCLK(CLK),
.D(fifo31_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo31_writeOut),
.DPO(fifo31_READ_OUTPUT),
.A(fifo31_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo32_writeInput = {pushBack_input[31:31],unnamedcast5855USEDMULTIPLEcast};
wire fifo32_writeOut;
RAM128X1D fifo32 (
.WCLK(CLK),
.D(fifo32_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo32_writeOut),
.DPO(fifo32_READ_OUTPUT),
.A(fifo32_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo33_writeInput = {pushBack_input[32:32],unnamedcast5855USEDMULTIPLEcast};
wire fifo33_writeOut;
RAM128X1D fifo33 (
.WCLK(CLK),
.D(fifo33_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo33_writeOut),
.DPO(fifo33_READ_OUTPUT),
.A(fifo33_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo34_writeInput = {pushBack_input[33:33],unnamedcast5855USEDMULTIPLEcast};
wire fifo34_writeOut;
RAM128X1D fifo34 (
.WCLK(CLK),
.D(fifo34_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo34_writeOut),
.DPO(fifo34_READ_OUTPUT),
.A(fifo34_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo35_writeInput = {pushBack_input[34:34],unnamedcast5855USEDMULTIPLEcast};
wire fifo35_writeOut;
RAM128X1D fifo35 (
.WCLK(CLK),
.D(fifo35_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo35_writeOut),
.DPO(fifo35_READ_OUTPUT),
.A(fifo35_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo36_writeInput = {pushBack_input[35:35],unnamedcast5855USEDMULTIPLEcast};
wire fifo36_writeOut;
RAM128X1D fifo36 (
.WCLK(CLK),
.D(fifo36_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo36_writeOut),
.DPO(fifo36_READ_OUTPUT),
.A(fifo36_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo37_writeInput = {pushBack_input[36:36],unnamedcast5855USEDMULTIPLEcast};
wire fifo37_writeOut;
RAM128X1D fifo37 (
.WCLK(CLK),
.D(fifo37_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo37_writeOut),
.DPO(fifo37_READ_OUTPUT),
.A(fifo37_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo38_writeInput = {pushBack_input[37:37],unnamedcast5855USEDMULTIPLEcast};
wire fifo38_writeOut;
RAM128X1D fifo38 (
.WCLK(CLK),
.D(fifo38_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo38_writeOut),
.DPO(fifo38_READ_OUTPUT),
.A(fifo38_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo39_writeInput = {pushBack_input[38:38],unnamedcast5855USEDMULTIPLEcast};
wire fifo39_writeOut;
RAM128X1D fifo39 (
.WCLK(CLK),
.D(fifo39_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo39_writeOut),
.DPO(fifo39_READ_OUTPUT),
.A(fifo39_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo40_writeInput = {pushBack_input[39:39],unnamedcast5855USEDMULTIPLEcast};
wire fifo40_writeOut;
RAM128X1D fifo40 (
.WCLK(CLK),
.D(fifo40_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo40_writeOut),
.DPO(fifo40_READ_OUTPUT),
.A(fifo40_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo41_writeInput = {pushBack_input[40:40],unnamedcast5855USEDMULTIPLEcast};
wire fifo41_writeOut;
RAM128X1D fifo41 (
.WCLK(CLK),
.D(fifo41_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo41_writeOut),
.DPO(fifo41_READ_OUTPUT),
.A(fifo41_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo42_writeInput = {pushBack_input[41:41],unnamedcast5855USEDMULTIPLEcast};
wire fifo42_writeOut;
RAM128X1D fifo42 (
.WCLK(CLK),
.D(fifo42_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo42_writeOut),
.DPO(fifo42_READ_OUTPUT),
.A(fifo42_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo43_writeInput = {pushBack_input[42:42],unnamedcast5855USEDMULTIPLEcast};
wire fifo43_writeOut;
RAM128X1D fifo43 (
.WCLK(CLK),
.D(fifo43_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo43_writeOut),
.DPO(fifo43_READ_OUTPUT),
.A(fifo43_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo44_writeInput = {pushBack_input[43:43],unnamedcast5855USEDMULTIPLEcast};
wire fifo44_writeOut;
RAM128X1D fifo44 (
.WCLK(CLK),
.D(fifo44_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo44_writeOut),
.DPO(fifo44_READ_OUTPUT),
.A(fifo44_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo45_writeInput = {pushBack_input[44:44],unnamedcast5855USEDMULTIPLEcast};
wire fifo45_writeOut;
RAM128X1D fifo45 (
.WCLK(CLK),
.D(fifo45_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo45_writeOut),
.DPO(fifo45_READ_OUTPUT),
.A(fifo45_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo46_writeInput = {pushBack_input[45:45],unnamedcast5855USEDMULTIPLEcast};
wire fifo46_writeOut;
RAM128X1D fifo46 (
.WCLK(CLK),
.D(fifo46_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo46_writeOut),
.DPO(fifo46_READ_OUTPUT),
.A(fifo46_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo47_writeInput = {pushBack_input[46:46],unnamedcast5855USEDMULTIPLEcast};
wire fifo47_writeOut;
RAM128X1D fifo47 (
.WCLK(CLK),
.D(fifo47_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo47_writeOut),
.DPO(fifo47_READ_OUTPUT),
.A(fifo47_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo48_writeInput = {pushBack_input[47:47],unnamedcast5855USEDMULTIPLEcast};
wire fifo48_writeOut;
RAM128X1D fifo48 (
.WCLK(CLK),
.D(fifo48_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo48_writeOut),
.DPO(fifo48_READ_OUTPUT),
.A(fifo48_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo49_writeInput = {pushBack_input[48:48],unnamedcast5855USEDMULTIPLEcast};
wire fifo49_writeOut;
RAM128X1D fifo49 (
.WCLK(CLK),
.D(fifo49_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo49_writeOut),
.DPO(fifo49_READ_OUTPUT),
.A(fifo49_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo50_writeInput = {pushBack_input[49:49],unnamedcast5855USEDMULTIPLEcast};
wire fifo50_writeOut;
RAM128X1D fifo50 (
.WCLK(CLK),
.D(fifo50_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo50_writeOut),
.DPO(fifo50_READ_OUTPUT),
.A(fifo50_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo51_writeInput = {pushBack_input[50:50],unnamedcast5855USEDMULTIPLEcast};
wire fifo51_writeOut;
RAM128X1D fifo51 (
.WCLK(CLK),
.D(fifo51_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo51_writeOut),
.DPO(fifo51_READ_OUTPUT),
.A(fifo51_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo52_writeInput = {pushBack_input[51:51],unnamedcast5855USEDMULTIPLEcast};
wire fifo52_writeOut;
RAM128X1D fifo52 (
.WCLK(CLK),
.D(fifo52_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo52_writeOut),
.DPO(fifo52_READ_OUTPUT),
.A(fifo52_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo53_writeInput = {pushBack_input[52:52],unnamedcast5855USEDMULTIPLEcast};
wire fifo53_writeOut;
RAM128X1D fifo53 (
.WCLK(CLK),
.D(fifo53_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo53_writeOut),
.DPO(fifo53_READ_OUTPUT),
.A(fifo53_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo54_writeInput = {pushBack_input[53:53],unnamedcast5855USEDMULTIPLEcast};
wire fifo54_writeOut;
RAM128X1D fifo54 (
.WCLK(CLK),
.D(fifo54_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo54_writeOut),
.DPO(fifo54_READ_OUTPUT),
.A(fifo54_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo55_writeInput = {pushBack_input[54:54],unnamedcast5855USEDMULTIPLEcast};
wire fifo55_writeOut;
RAM128X1D fifo55 (
.WCLK(CLK),
.D(fifo55_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo55_writeOut),
.DPO(fifo55_READ_OUTPUT),
.A(fifo55_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo56_writeInput = {pushBack_input[55:55],unnamedcast5855USEDMULTIPLEcast};
wire fifo56_writeOut;
RAM128X1D fifo56 (
.WCLK(CLK),
.D(fifo56_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo56_writeOut),
.DPO(fifo56_READ_OUTPUT),
.A(fifo56_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo57_writeInput = {pushBack_input[56:56],unnamedcast5855USEDMULTIPLEcast};
wire fifo57_writeOut;
RAM128X1D fifo57 (
.WCLK(CLK),
.D(fifo57_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo57_writeOut),
.DPO(fifo57_READ_OUTPUT),
.A(fifo57_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo58_writeInput = {pushBack_input[57:57],unnamedcast5855USEDMULTIPLEcast};
wire fifo58_writeOut;
RAM128X1D fifo58 (
.WCLK(CLK),
.D(fifo58_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo58_writeOut),
.DPO(fifo58_READ_OUTPUT),
.A(fifo58_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo59_writeInput = {pushBack_input[58:58],unnamedcast5855USEDMULTIPLEcast};
wire fifo59_writeOut;
RAM128X1D fifo59 (
.WCLK(CLK),
.D(fifo59_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo59_writeOut),
.DPO(fifo59_READ_OUTPUT),
.A(fifo59_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo60_writeInput = {pushBack_input[59:59],unnamedcast5855USEDMULTIPLEcast};
wire fifo60_writeOut;
RAM128X1D fifo60 (
.WCLK(CLK),
.D(fifo60_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo60_writeOut),
.DPO(fifo60_READ_OUTPUT),
.A(fifo60_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo61_writeInput = {pushBack_input[60:60],unnamedcast5855USEDMULTIPLEcast};
wire fifo61_writeOut;
RAM128X1D fifo61 (
.WCLK(CLK),
.D(fifo61_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo61_writeOut),
.DPO(fifo61_READ_OUTPUT),
.A(fifo61_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo62_writeInput = {pushBack_input[61:61],unnamedcast5855USEDMULTIPLEcast};
wire fifo62_writeOut;
RAM128X1D fifo62 (
.WCLK(CLK),
.D(fifo62_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo62_writeOut),
.DPO(fifo62_READ_OUTPUT),
.A(fifo62_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo63_writeInput = {pushBack_input[62:62],unnamedcast5855USEDMULTIPLEcast};
wire fifo63_writeOut;
RAM128X1D fifo63 (
.WCLK(CLK),
.D(fifo63_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo63_writeOut),
.DPO(fifo63_READ_OUTPUT),
.A(fifo63_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
wire [7:0] fifo64_writeInput = {pushBack_input[63:63],unnamedcast5855USEDMULTIPLEcast};
wire fifo64_writeOut;
RAM128X1D fifo64 (
.WCLK(CLK),
.D(fifo64_writeInput[7]),
.WE(pushBack_valid && CE_push),
.SPO(fifo64_writeOut),
.DPO(fifo64_READ_OUTPUT),
.A(fifo64_writeInput[6:0]),
.DPRA(unnamedcast6180USEDMULTIPLEcast));
endmodule
module fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024(input CLK, input load_valid, input load_CE, output [64:0] load_output, input store_reset_valid, input store_CE, output store_ready, input load_reset_valid, input store_valid, input [63:0] store_input);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(load_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_reset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(load_reset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME); end end
wire FIFO_hasData;
wire [63:0] FIFO_popFront;
assign load_output = {FIFO_hasData,FIFO_popFront};
wire FIFO_ready;
assign store_ready = FIFO_ready;
// function: load pure=false delay=0
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_uint8_4_1__2_1__128 #(.INSTANCE_NAME({INSTANCE_NAME,"_FIFO"})) FIFO(.CLK(CLK), .popFront_valid({(FIFO_hasData&&load_valid)}), .CE_pop(load_CE), .popFront(FIFO_popFront), .size(FIFO_size), .pushBackReset_valid(store_reset_valid), .CE_push(store_CE), .ready(FIFO_ready), .pushBack_valid(store_valid), .pushBack_input(store_input), .popFrontReset_valid(load_reset_valid), .hasData(FIFO_hasData));
endmodule
module LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024(input CLK, input load_valid, input load_CE, input load_input, output [64:0] load_output, input store_reset_valid, input store_CE, output store_ready, output load_ready, input load_reset, input store_valid, input [63:0] store_input);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(load_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_reset_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(load_reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME); end end
wire unnamedcast7279USEDMULTIPLEcast;assign unnamedcast7279USEDMULTIPLEcast = load_input;
wire [64:0] LiftDecimate_load_output;
reg [63:0] unnamedcast7282_delay1_validunnamednull0_CEload_CE; always @ (posedge CLK) begin if (load_CE) begin unnamedcast7282_delay1_validunnamednull0_CEload_CE <= (LiftDecimate_load_output[63:0]); end end
reg unnamedbinop7287_delay1_validunnamednull0_CEload_CE; always @ (posedge CLK) begin if (load_CE) begin unnamedbinop7287_delay1_validunnamednull0_CEload_CE <= {((LiftDecimate_load_output[64])&&unnamedcast7279USEDMULTIPLEcast)}; end end
assign load_output = {unnamedbinop7287_delay1_validunnamednull0_CEload_CE,unnamedcast7282_delay1_validunnamednull0_CEload_CE};
wire LiftDecimate_store_ready;
assign store_ready = LiftDecimate_store_ready;
assign load_ready = (1'd1);
// function: load pure=false delay=1
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 #(.INSTANCE_NAME({INSTANCE_NAME,"_LiftDecimate"})) LiftDecimate(.CLK(CLK), .load_valid({(unnamedcast7279USEDMULTIPLEcast&&load_valid)}), .load_CE(load_CE), .load_output(LiftDecimate_load_output), .store_reset_valid(store_reset_valid), .store_CE(store_CE), .store_ready(LiftDecimate_store_ready), .load_reset_valid(load_reset), .store_valid(store_valid), .store_input(store_input));
endmodule
module RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024(input CLK, input load_valid, input load_CE, input load_input, output [64:0] load_output, input store_reset, input CE, output store_ready, output load_ready, input load_reset, input store_valid, input [64:0] store_input, output store_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(load_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(load_reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(store_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME); end end
wire [64:0] RunIffReady_load_output;
assign load_output = RunIffReady_load_output;
wire RunIffReady_store_ready;
assign store_ready = RunIffReady_store_ready;
wire RunIffReady_load_ready;
assign load_ready = RunIffReady_load_ready;
wire unnamedbinop7358USEDMULTIPLEbinop;assign unnamedbinop7358USEDMULTIPLEbinop = {({(RunIffReady_store_ready&&(store_input[64]))}&&store_valid)};
assign store_output = {unnamedbinop7358USEDMULTIPLEbinop};
// function: load pure=false delay=1
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 #(.INSTANCE_NAME({INSTANCE_NAME,"_RunIffReady"})) RunIffReady(.CLK(CLK), .load_valid(load_valid), .load_CE(load_CE), .load_input(load_input), .load_output(RunIffReady_load_output), .store_reset_valid(store_reset), .store_CE(CE), .store_ready(RunIffReady_store_ready), .load_ready(RunIffReady_load_ready), .load_reset(load_reset), .store_valid(unnamedbinop7358USEDMULTIPLEbinop), .store_input((store_input[63:0])));
endmodule
module LiftHandshake_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024(input CLK, input load_input, output [64:0] load_output, input store_reset, input store_ready_downstream, output store_ready, input load_ready_downstream, output load_ready, input load_reset, input [64:0] store_input, output store_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire unnamedunary7395USEDMULTIPLEunary;assign unnamedunary7395USEDMULTIPLEunary = {(~load_reset)};
wire unnamedbinop7394USEDMULTIPLEbinop;assign unnamedbinop7394USEDMULTIPLEbinop = {(load_reset||load_ready_downstream)};
wire [64:0] inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_load_output;
wire load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_pushPop_out;
wire [64:0] unnamedtuple7405USEDMULTIPLEtuple;assign unnamedtuple7405USEDMULTIPLEtuple = {{((inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_load_output[64])&&load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_pushPop_out)},(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_load_output[63:0])};
always @(posedge CLK) begin if({(~{((unnamedtuple7405USEDMULTIPLEtuple[64])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: output valid bit should not be X!",INSTANCE_NAME); end end
always @(posedge CLK) begin if({(~{(load_input===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign load_output = unnamedtuple7405USEDMULTIPLEtuple;
wire unnamedbinop7423USEDMULTIPLEbinop;assign unnamedbinop7423USEDMULTIPLEbinop = {(store_reset||store_ready_downstream)};
wire inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_store_ready;
assign store_ready = {(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_store_ready&&store_ready_downstream)};
wire inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_load_ready;
assign load_ready = {(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_load_ready&&load_ready_downstream)};
wire unnamedunary7424USEDMULTIPLEunary;assign unnamedunary7424USEDMULTIPLEunary = {(~store_reset)};
wire [0:0] inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_store_output;
wire store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_pushPop_out;
wire [0:0] unnamedtuple7434USEDMULTIPLEtuple;assign unnamedtuple7434USEDMULTIPLEtuple = {{(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_store_output&&store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_pushPop_out)}};
always @(posedge CLK) begin if({(~{(unnamedtuple7434USEDMULTIPLEtuple===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: output valid bit should not be X!",INSTANCE_NAME); end end
always @(posedge CLK) begin if({(~{((store_input[64])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign store_output = unnamedtuple7434USEDMULTIPLEtuple;
// function: load pure=false ONLY WIRE
// function: store_reset pure=false ONLY WIRE
// function: store_ready pure=true ONLY WIRE
// function: load_ready pure=true ONLY WIRE
// function: load_reset pure=false ONLY WIRE
// function: store pure=false ONLY WIRE
RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024"})) inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024(.CLK(CLK), .load_valid(unnamedunary7395USEDMULTIPLEunary), .load_CE(unnamedbinop7394USEDMULTIPLEbinop), .load_input(load_input), .load_output(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_load_output), .store_reset(store_reset), .CE(unnamedbinop7423USEDMULTIPLEbinop), .store_ready(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_store_ready), .load_ready(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_load_ready), .load_reset(load_reset), .store_valid(unnamedunary7424USEDMULTIPLEunary), .store_input(store_input), .store_output(inner_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_store_output));
ShiftRegister_1_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024"})) load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024(.CLK(CLK), .pushPop_valid(unnamedunary7395USEDMULTIPLEunary), .CE(unnamedbinop7394USEDMULTIPLEbinop), .sr_input((1'd1)), .pushPop_out(load_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_pushPop_out), .reset(load_reset));
ShiftRegister_0_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024"})) store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024(.CLK(CLK), .CE(unnamedbinop7423USEDMULTIPLEbinop), .sr_input((1'd1)), .pushPop_out(store_validBitDelay_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024_pushPop_out));
endmodule
module incif_wrapuint32_646_inc2(input CLK, input CE, input [32:0] process_input, output [31:0] process_output);
parameter INSTANCE_NAME="INST";
wire [31:0] unnamedcast61USEDMULTIPLEcast;assign unnamedcast61USEDMULTIPLEcast = (process_input[31:0]);
assign process_output = (((process_input[32]))?((({(unnamedcast61USEDMULTIPLEcast==(32'd646))})?((32'd0)):({(unnamedcast61USEDMULTIPLEcast+(32'd2))}))):(unnamedcast61USEDMULTIPLEcast));
// function: process pure=true delay=0
endmodule
module RegBy_incif_wrapuint32_646_inc2_CEtrue_init0(input CLK, input set_valid, input CE, input [31:0] set_inp, input setby_valid, input setby_inp, output [31:0] SETBY_OUTPUT, output [31:0] GET_OUTPUT);
parameter INSTANCE_NAME="INST";
reg [31:0] R = 32'd0;
wire [31:0] regby_inner_process_output;
always @(posedge CLK) begin if(set_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(setby_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,set_valid})+({4'b0,setby_valid})) > 5'd1) begin $display("error, function 'set' on instance 'R' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [32:0] unnamedcallArbitrate112USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate112USEDMULTIPLEcallArbitrate = {(set_valid||setby_valid),((set_valid)?(set_inp):(regby_inner_process_output))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate112USEDMULTIPLEcallArbitrate[32]) && CE) begin R <= (unnamedcallArbitrate112USEDMULTIPLEcallArbitrate[31:0]); end end
assign SETBY_OUTPUT = regby_inner_process_output;
assign GET_OUTPUT = R;
// function: set pure=false ONLY WIRE
// function: setby pure=false ONLY WIRE
// function: get pure=true ONLY WIRE
incif_wrapuint32_646_inc2 #(.INSTANCE_NAME({INSTANCE_NAME,"_regby_inner"})) regby_inner(.CLK(CLK), .CE(CE), .process_input({setby_inp,R}), .process_output(regby_inner_process_output));
endmodule
module incif_wrapuint16_481_incnil(input CLK, input CE, input [16:0] process_input, output [15:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] unnamedcast119USEDMULTIPLEcast;assign unnamedcast119USEDMULTIPLEcast = (process_input[15:0]);
assign process_output = (((process_input[16]))?((({(unnamedcast119USEDMULTIPLEcast==(16'd481))})?((16'd0)):({(unnamedcast119USEDMULTIPLEcast+(16'd1))}))):(unnamedcast119USEDMULTIPLEcast));
// function: process pure=true delay=0
endmodule
module RegBy_incif_wrapuint16_481_incnil_CEtrue_init0(input CLK, input set_valid, input CE, input [15:0] set_inp, input setby_valid, input setby_inp, output [15:0] SETBY_OUTPUT, output [15:0] GET_OUTPUT);
parameter INSTANCE_NAME="INST";
reg [15:0] R = 16'd0;
wire [15:0] regby_inner_process_output;
always @(posedge CLK) begin if(set_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(setby_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,set_valid})+({4'b0,setby_valid})) > 5'd1) begin $display("error, function 'set' on instance 'R' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [16:0] unnamedcallArbitrate170USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate170USEDMULTIPLEcallArbitrate = {(set_valid||setby_valid),((set_valid)?(set_inp):(regby_inner_process_output))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate170USEDMULTIPLEcallArbitrate[16]) && CE) begin R <= (unnamedcallArbitrate170USEDMULTIPLEcallArbitrate[15:0]); end end
assign SETBY_OUTPUT = regby_inner_process_output;
assign GET_OUTPUT = R;
// function: set pure=false ONLY WIRE
// function: setby pure=false ONLY WIRE
// function: get pure=true ONLY WIRE
incif_wrapuint16_481_incnil #(.INSTANCE_NAME({INSTANCE_NAME,"_regby_inner"})) regby_inner(.CLK(CLK), .CE(CE), .process_input({setby_inp,R}), .process_output(regby_inner_process_output));
endmodule
module PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22(input CLK, output ready, input reset, input CE, input process_valid, input [15:0] process_input, output [16:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
wire [31:0] posX_padSeq_GET_OUTPUT;
wire [15:0] posY_padSeq_GET_OUTPUT;
wire unnamedbinop194USEDMULTIPLEbinop;assign unnamedbinop194USEDMULTIPLEbinop = {({({((posX_padSeq_GET_OUTPUT)>=((32'd4)))}&&{((posX_padSeq_GET_OUTPUT)<((32'd644)))})}&&{({((posY_padSeq_GET_OUTPUT)>=((16'd1)))}&&{((posY_padSeq_GET_OUTPUT)<((16'd481)))})})};
assign ready = unnamedbinop194USEDMULTIPLEbinop;
reg [15:0] unnamedselect206_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedselect206_delay1_validunnamednull0_CECE <= ((unnamedbinop194USEDMULTIPLEbinop)?(process_input):({(8'd0),(8'd0)})); end end
wire [15:0] posY_padSeq_SETBY_OUTPUT;
wire [31:0] posX_padSeq_SETBY_OUTPUT;
assign process_output = {(1'd1),unnamedselect206_delay1_validunnamednull0_CECE};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
RegBy_incif_wrapuint32_646_inc2_CEtrue_init0 #(.INSTANCE_NAME({INSTANCE_NAME,"_posX_padSeq"})) posX_padSeq(.CLK(CLK), .set_valid(reset), .CE(CE), .set_inp((32'd0)), .setby_valid(process_valid), .setby_inp((1'd1)), .SETBY_OUTPUT(posX_padSeq_SETBY_OUTPUT), .GET_OUTPUT(posX_padSeq_GET_OUTPUT));
RegBy_incif_wrapuint16_481_incnil_CEtrue_init0 #(.INSTANCE_NAME({INSTANCE_NAME,"_posY_padSeq"})) posY_padSeq(.CLK(CLK), .set_valid(reset), .CE(CE), .set_inp((16'd0)), .setby_valid(process_valid), .setby_inp({(posX_padSeq_GET_OUTPUT==(32'd646))}), .SETBY_OUTPUT(posY_padSeq_SETBY_OUTPUT), .GET_OUTPUT(posY_padSeq_GET_OUTPUT));
endmodule
module WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22(input CLK, output ready, input reset, input CE, input process_valid, input [16:0] process_input, output [16:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
wire WaitOnInput_inner_ready;
assign ready = WaitOnInput_inner_ready;
wire unnamedbinop308USEDMULTIPLEbinop;assign unnamedbinop308USEDMULTIPLEbinop = {({({(~WaitOnInput_inner_ready)}||(process_input[16]))}&&process_valid)};
wire [16:0] WaitOnInput_inner_process_output;
reg unnamedbinop308_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedbinop308_delay1_validunnamednull0_CECE <= unnamedbinop308USEDMULTIPLEbinop; end end
assign process_output = {{((WaitOnInput_inner_process_output[16])&&unnamedbinop308_delay1_validunnamednull0_CECE)},(WaitOnInput_inner_process_output[15:0])};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22 #(.INSTANCE_NAME({INSTANCE_NAME,"_WaitOnInput_inner"})) WaitOnInput_inner(.CLK(CLK), .ready(WaitOnInput_inner_ready), .reset(reset), .CE(CE), .process_valid(unnamedbinop308USEDMULTIPLEbinop), .process_input((process_input[15:0])), .process_output(WaitOnInput_inner_process_output));
endmodule
module LiftHandshake_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22(input CLK, input ready_downstream, output ready, input reset, input [16:0] process_input, output [16:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire inner_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_ready;
assign ready = {(inner_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_ready&&ready_downstream)};
wire unnamedbinop343USEDMULTIPLEbinop;assign unnamedbinop343USEDMULTIPLEbinop = {(reset||ready_downstream)};
wire unnamedunary344USEDMULTIPLEunary;assign unnamedunary344USEDMULTIPLEunary = {(~reset)};
wire [16:0] inner_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_process_output;
wire validBitDelay_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_pushPop_out;
wire [16:0] unnamedtuple376USEDMULTIPLEtuple;assign unnamedtuple376USEDMULTIPLEtuple = {{((inner_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_process_output[16])&&validBitDelay_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_pushPop_out)},(inner_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_process_output[15:0])};
always @(posedge CLK) begin if({(~{((unnamedtuple376USEDMULTIPLEtuple[16])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: output valid bit should not be X!",INSTANCE_NAME); end end
always @(posedge CLK) begin if({(~{((process_input[16])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign process_output = unnamedtuple376USEDMULTIPLEtuple;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22"})) inner_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22(.CLK(CLK), .ready(inner_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_ready), .reset(reset), .CE(unnamedbinop343USEDMULTIPLEbinop), .process_valid(unnamedunary344USEDMULTIPLEunary), .process_input(process_input), .process_output(inner_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_process_output));
ShiftRegister_1_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_validBitDelay_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22"})) validBitDelay_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22(.CLK(CLK), .pushPop_valid(unnamedunary344USEDMULTIPLEunary), .CE(unnamedbinop343USEDMULTIPLEbinop), .sr_input((1'd1)), .pushPop_out(validBitDelay_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22_pushPop_out), .reset(reset));
endmodule
module ShiftRegister_32_CEtrue_TY1(input CLK, input pushPop_valid, input CE, input sr_input, output pushPop_out, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'pushPop'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
reg SR32;
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR1' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR1' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR1' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5284USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5284USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(sr_input):((1'd0)))};
reg SR1; always @ (posedge CLK) begin if ((unnamedcallArbitrate5284USEDMULTIPLEcallArbitrate[1]) && CE) begin SR1 <= (unnamedcallArbitrate5284USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR2' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR2' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR2' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5290USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5290USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR1):((1'd0)))};
reg SR2; always @ (posedge CLK) begin if ((unnamedcallArbitrate5290USEDMULTIPLEcallArbitrate[1]) && CE) begin SR2 <= (unnamedcallArbitrate5290USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR3' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR3' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR3' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5296USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5296USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR2):((1'd0)))};
reg SR3; always @ (posedge CLK) begin if ((unnamedcallArbitrate5296USEDMULTIPLEcallArbitrate[1]) && CE) begin SR3 <= (unnamedcallArbitrate5296USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR4' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR4' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR4' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5302USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5302USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR3):((1'd0)))};
reg SR4; always @ (posedge CLK) begin if ((unnamedcallArbitrate5302USEDMULTIPLEcallArbitrate[1]) && CE) begin SR4 <= (unnamedcallArbitrate5302USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR5' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR5' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR5' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5308USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5308USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR4):((1'd0)))};
reg SR5; always @ (posedge CLK) begin if ((unnamedcallArbitrate5308USEDMULTIPLEcallArbitrate[1]) && CE) begin SR5 <= (unnamedcallArbitrate5308USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR6' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR6' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR6' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5314USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5314USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR5):((1'd0)))};
reg SR6; always @ (posedge CLK) begin if ((unnamedcallArbitrate5314USEDMULTIPLEcallArbitrate[1]) && CE) begin SR6 <= (unnamedcallArbitrate5314USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR7' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR7' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR7' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5320USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5320USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR6):((1'd0)))};
reg SR7; always @ (posedge CLK) begin if ((unnamedcallArbitrate5320USEDMULTIPLEcallArbitrate[1]) && CE) begin SR7 <= (unnamedcallArbitrate5320USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR8' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR8' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR8' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5326USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5326USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR7):((1'd0)))};
reg SR8; always @ (posedge CLK) begin if ((unnamedcallArbitrate5326USEDMULTIPLEcallArbitrate[1]) && CE) begin SR8 <= (unnamedcallArbitrate5326USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR9' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR9' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR9' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5332USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5332USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR8):((1'd0)))};
reg SR9; always @ (posedge CLK) begin if ((unnamedcallArbitrate5332USEDMULTIPLEcallArbitrate[1]) && CE) begin SR9 <= (unnamedcallArbitrate5332USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR10' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR10' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR10' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5338USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5338USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR9):((1'd0)))};
reg SR10; always @ (posedge CLK) begin if ((unnamedcallArbitrate5338USEDMULTIPLEcallArbitrate[1]) && CE) begin SR10 <= (unnamedcallArbitrate5338USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR11' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR11' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR11' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5344USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5344USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR10):((1'd0)))};
reg SR11; always @ (posedge CLK) begin if ((unnamedcallArbitrate5344USEDMULTIPLEcallArbitrate[1]) && CE) begin SR11 <= (unnamedcallArbitrate5344USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR12' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR12' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR12' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5350USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5350USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR11):((1'd0)))};
reg SR12; always @ (posedge CLK) begin if ((unnamedcallArbitrate5350USEDMULTIPLEcallArbitrate[1]) && CE) begin SR12 <= (unnamedcallArbitrate5350USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR13' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR13' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR13' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5356USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5356USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR12):((1'd0)))};
reg SR13; always @ (posedge CLK) begin if ((unnamedcallArbitrate5356USEDMULTIPLEcallArbitrate[1]) && CE) begin SR13 <= (unnamedcallArbitrate5356USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR14' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR14' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR14' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5362USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5362USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR13):((1'd0)))};
reg SR14; always @ (posedge CLK) begin if ((unnamedcallArbitrate5362USEDMULTIPLEcallArbitrate[1]) && CE) begin SR14 <= (unnamedcallArbitrate5362USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR15' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR15' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR15' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5368USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5368USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR14):((1'd0)))};
reg SR15; always @ (posedge CLK) begin if ((unnamedcallArbitrate5368USEDMULTIPLEcallArbitrate[1]) && CE) begin SR15 <= (unnamedcallArbitrate5368USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR16' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR16' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR16' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5374USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5374USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR15):((1'd0)))};
reg SR16; always @ (posedge CLK) begin if ((unnamedcallArbitrate5374USEDMULTIPLEcallArbitrate[1]) && CE) begin SR16 <= (unnamedcallArbitrate5374USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR17' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR17' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR17' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5380USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5380USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR16):((1'd0)))};
reg SR17; always @ (posedge CLK) begin if ((unnamedcallArbitrate5380USEDMULTIPLEcallArbitrate[1]) && CE) begin SR17 <= (unnamedcallArbitrate5380USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR18' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR18' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR18' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5386USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5386USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR17):((1'd0)))};
reg SR18; always @ (posedge CLK) begin if ((unnamedcallArbitrate5386USEDMULTIPLEcallArbitrate[1]) && CE) begin SR18 <= (unnamedcallArbitrate5386USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR19' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR19' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR19' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5392USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5392USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR18):((1'd0)))};
reg SR19; always @ (posedge CLK) begin if ((unnamedcallArbitrate5392USEDMULTIPLEcallArbitrate[1]) && CE) begin SR19 <= (unnamedcallArbitrate5392USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR20' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR20' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR20' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5398USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5398USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR19):((1'd0)))};
reg SR20; always @ (posedge CLK) begin if ((unnamedcallArbitrate5398USEDMULTIPLEcallArbitrate[1]) && CE) begin SR20 <= (unnamedcallArbitrate5398USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR21' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR21' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR21' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5404USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5404USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR20):((1'd0)))};
reg SR21; always @ (posedge CLK) begin if ((unnamedcallArbitrate5404USEDMULTIPLEcallArbitrate[1]) && CE) begin SR21 <= (unnamedcallArbitrate5404USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR22' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR22' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR22' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5410USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5410USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR21):((1'd0)))};
reg SR22; always @ (posedge CLK) begin if ((unnamedcallArbitrate5410USEDMULTIPLEcallArbitrate[1]) && CE) begin SR22 <= (unnamedcallArbitrate5410USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR23' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR23' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR23' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5416USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5416USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR22):((1'd0)))};
reg SR23; always @ (posedge CLK) begin if ((unnamedcallArbitrate5416USEDMULTIPLEcallArbitrate[1]) && CE) begin SR23 <= (unnamedcallArbitrate5416USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR24' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR24' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR24' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5422USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5422USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR23):((1'd0)))};
reg SR24; always @ (posedge CLK) begin if ((unnamedcallArbitrate5422USEDMULTIPLEcallArbitrate[1]) && CE) begin SR24 <= (unnamedcallArbitrate5422USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR25' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR25' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR25' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5428USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5428USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR24):((1'd0)))};
reg SR25; always @ (posedge CLK) begin if ((unnamedcallArbitrate5428USEDMULTIPLEcallArbitrate[1]) && CE) begin SR25 <= (unnamedcallArbitrate5428USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR26' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR26' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR26' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5434USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5434USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR25):((1'd0)))};
reg SR26; always @ (posedge CLK) begin if ((unnamedcallArbitrate5434USEDMULTIPLEcallArbitrate[1]) && CE) begin SR26 <= (unnamedcallArbitrate5434USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR27' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR27' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR27' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5440USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5440USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR26):((1'd0)))};
reg SR27; always @ (posedge CLK) begin if ((unnamedcallArbitrate5440USEDMULTIPLEcallArbitrate[1]) && CE) begin SR27 <= (unnamedcallArbitrate5440USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR28' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR28' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR28' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5446USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5446USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR27):((1'd0)))};
reg SR28; always @ (posedge CLK) begin if ((unnamedcallArbitrate5446USEDMULTIPLEcallArbitrate[1]) && CE) begin SR28 <= (unnamedcallArbitrate5446USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR29' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR29' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR29' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5452USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5452USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR28):((1'd0)))};
reg SR29; always @ (posedge CLK) begin if ((unnamedcallArbitrate5452USEDMULTIPLEcallArbitrate[1]) && CE) begin SR29 <= (unnamedcallArbitrate5452USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR30' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR30' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR30' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5458USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5458USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR29):((1'd0)))};
reg SR30; always @ (posedge CLK) begin if ((unnamedcallArbitrate5458USEDMULTIPLEcallArbitrate[1]) && CE) begin SR30 <= (unnamedcallArbitrate5458USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR31' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR31' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR31' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5464USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5464USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR30):((1'd0)))};
reg SR31; always @ (posedge CLK) begin if ((unnamedcallArbitrate5464USEDMULTIPLEcallArbitrate[1]) && CE) begin SR31 <= (unnamedcallArbitrate5464USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR32' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR32' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR32' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5470USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5470USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR31):((1'd0)))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate5470USEDMULTIPLEcallArbitrate[1]) && CE) begin SR32 <= (unnamedcallArbitrate5470USEDMULTIPLEcallArbitrate[0]); end end
assign pushPop_out = SR32;
// function: pushPop pure=false delay=0
// function: reset pure=false delay=0
endmodule
module blackLevel(input CLK, input process_CE, input [7:0] blInput, output [7:0] process_output);
parameter INSTANCE_NAME="INST";
wire [8:0] unnamedcast1116;assign unnamedcast1116 = {1'b0,blInput}; // wire for int size extend (cast)
wire [8:0] unnamedcast1118;assign unnamedcast1118 = {1'b0,(8'd90)}; // wire for int size extend (cast)
wire [9:0] unnamedcast1119;assign unnamedcast1119 = { {1{unnamedcast1116[8]}},unnamedcast1116[8:0]}; // wire for $signed
wire [9:0] unnamedcast1120;assign unnamedcast1120 = { {1{unnamedcast1118[8]}},unnamedcast1118[8:0]}; // wire for $signed
reg [9:0] unnamedbinop1121_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1121_delay1_validunnamednull0_CEprocess_CE <= {($signed(unnamedcast1119)-$signed(unnamedcast1120))}; end end
wire [8:0] unnamedcast1123;assign unnamedcast1123 = {1'b0,(8'd197)}; // wire for int size extend (cast)
reg [18:0] unnamedcast1125_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1125_delay1_validunnamednull0_CEprocess_CE <= { {10{unnamedcast1123[8]}},unnamedcast1123[8:0]}; end end
wire [18:0] unnamedcast1124;assign unnamedcast1124 = { {9{unnamedbinop1121_delay1_validunnamednull0_CEprocess_CE[9]}},unnamedbinop1121_delay1_validunnamednull0_CEprocess_CE[9:0]}; // wire for $signed
reg [18:0] unnamedbinop1126_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1126_delay1_validunnamednull0_CEprocess_CE <= {($signed(unnamedcast1124)*$signed(unnamedcast1125_delay1_validunnamednull0_CEprocess_CE))}; end end
reg [18:0] unnamedunary1127_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedunary1127_delay1_validunnamednull0_CEprocess_CE <= {((unnamedbinop1126_delay1_validunnamednull0_CEprocess_CE[18])?(-unnamedbinop1126_delay1_validunnamednull0_CEprocess_CE):(unnamedbinop1126_delay1_validunnamednull0_CEprocess_CE))}; end end
reg [18:0] unnamedcast1130_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1130_delay1_validunnamednull0_CEprocess_CE <= (19'd7); end end
reg [18:0] unnamedcast1130_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1130_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1130_delay1_validunnamednull0_CEprocess_CE; end end
reg [18:0] unnamedcast1130_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1130_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1130_delay2_validunnamednull0_CEprocess_CE; end end
reg [18:0] unnamedbinop1131_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1131_delay1_validunnamednull0_CEprocess_CE <= {(unnamedunary1127_delay1_validunnamednull0_CEprocess_CE>>>unnamedcast1130_delay3_validunnamednull0_CEprocess_CE)}; end end
wire [11:0] unnamedcast1132USEDMULTIPLEcast;assign unnamedcast1132USEDMULTIPLEcast = unnamedbinop1131_delay1_validunnamednull0_CEprocess_CE[11:0];
reg [11:0] unnamedcast1134_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1134_delay1_validunnamednull0_CEprocess_CE <= {4'b0,(8'd255)}; end end
reg [11:0] unnamedcast1134_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1134_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1134_delay1_validunnamednull0_CEprocess_CE; end end
reg [11:0] unnamedcast1134_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1134_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1134_delay2_validunnamednull0_CEprocess_CE; end end
reg [11:0] unnamedcast1134_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1134_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1134_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop1135_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1135_delay1_validunnamednull0_CEprocess_CE <= {((unnamedcast1132USEDMULTIPLEcast)>(unnamedcast1134_delay4_validunnamednull0_CEprocess_CE))}; end end
reg [11:0] unnamedcast1137_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1137_delay1_validunnamednull0_CEprocess_CE <= (12'd255); end end
reg [11:0] unnamedcast1137_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1137_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1137_delay1_validunnamednull0_CEprocess_CE; end end
reg [11:0] unnamedcast1137_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1137_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1137_delay2_validunnamednull0_CEprocess_CE; end end
reg [11:0] unnamedcast1137_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1137_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1137_delay3_validunnamednull0_CEprocess_CE; end end
reg [11:0] unnamedcast1137_delay5_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1137_delay5_validunnamednull0_CEprocess_CE <= unnamedcast1137_delay4_validunnamednull0_CEprocess_CE; end end
reg [11:0] unnamedcast1132_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1132_delay1_validunnamednull0_CEprocess_CE <= unnamedcast1132USEDMULTIPLEcast; end end
reg [11:0] unnamedselect1138_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect1138_delay1_validunnamednull0_CEprocess_CE <= ((unnamedbinop1135_delay1_validunnamednull0_CEprocess_CE)?(unnamedcast1137_delay5_validunnamednull0_CEprocess_CE):(unnamedcast1132_delay1_validunnamednull0_CEprocess_CE)); end end
assign process_output = unnamedselect1138_delay1_validunnamednull0_CEprocess_CE[7:0];
// function: process pure=true delay=6
endmodule
module map_blackLevel_W2_H1(input CLK, input process_CE, input [15:0] process_input, output [15:0] process_output);
parameter INSTANCE_NAME="INST";
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output,inner0_0_process_output};
// function: process pure=true delay=6
blackLevel #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_0"})) inner0_0(.CLK(CLK), .process_CE(process_CE), .blInput(({process_input[7:0]})), .process_output(inner0_0_process_output));
blackLevel #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_0"})) inner1_0(.CLK(CLK), .process_CE(process_CE), .blInput(({process_input[15:8]})), .process_output(inner1_0_process_output));
endmodule
module incif_wrapuint16_323_incnil(input CLK, input CE, input [16:0] process_input, output [15:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] unnamedcast3810USEDMULTIPLEcast;assign unnamedcast3810USEDMULTIPLEcast = (process_input[15:0]);
assign process_output = (((process_input[16]))?((({(unnamedcast3810USEDMULTIPLEcast==(16'd323))})?((16'd0)):({(unnamedcast3810USEDMULTIPLEcast+(16'd1))}))):(unnamedcast3810USEDMULTIPLEcast));
// function: process pure=true delay=0
endmodule
module RegBy_incif_wrapuint16_323_incnil_CEtrue_initnil(input CLK, input set_valid, input CE, input [15:0] set_inp, input setby_valid, input setby_inp, output [15:0] SETBY_OUTPUT, output [15:0] GET_OUTPUT);
parameter INSTANCE_NAME="INST";
reg [15:0] R;
wire [15:0] regby_inner_process_output;
always @(posedge CLK) begin if(set_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(setby_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,set_valid})+({4'b0,setby_valid})) > 5'd1) begin $display("error, function 'set' on instance 'R' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [16:0] unnamedcallArbitrate3861USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate3861USEDMULTIPLEcallArbitrate = {(set_valid||setby_valid),((set_valid)?(set_inp):(regby_inner_process_output))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate3861USEDMULTIPLEcallArbitrate[16]) && CE) begin R <= (unnamedcallArbitrate3861USEDMULTIPLEcallArbitrate[15:0]); end end
assign SETBY_OUTPUT = regby_inner_process_output;
assign GET_OUTPUT = R;
// function: set pure=false ONLY WIRE
// function: setby pure=false ONLY WIRE
// function: get pure=true ONLY WIRE
incif_wrapuint16_323_incnil #(.INSTANCE_NAME({INSTANCE_NAME,"_regby_inner"})) regby_inner(.CLK(CLK), .CE(CE), .process_input({setby_inp,R}), .process_output(regby_inner_process_output));
endmodule
module bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil(input CLK, input writeAndReturnOriginal_valid, input writeAndReturnOriginal_CE, input [24:0] inp, output [15:0] WARO_OUT);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(writeAndReturnOriginal_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'writeAndReturnOriginal'", INSTANCE_NAME); end end
wire [15:0] unnamedcast3870;assign unnamedcast3870 = (inp[24:9]); // wire for bitslice
wire [15:0] bram_0_SET_AND_RETURN_ORIG_OUTPUT;
assign WARO_OUT = {bram_0_SET_AND_RETURN_ORIG_OUTPUT};
// function: writeAndReturnOriginal pure=false delay=1
reg [15:0] bram_0_DI_B;
reg [9:0] bram_0_addr_B;
wire [15:0] bram_0_DO_B;
wire [25:0] bram_0_INPUT;
assign bram_0_INPUT = {unnamedcast3870[15:0],{1'b0,(inp[8:0])}};
RAMB16_S18_S18 #(.WRITE_MODE_A("READ_FIRST"),.WRITE_MODE_B("READ_FIRST")) bram_0 (
.DIPA(2'b0),
.DIPB(2'b0),
.DIA(bram_0_INPUT[25:10]),
.DIB(bram_0_DI_B),
.DOA(bram_0_SET_AND_RETURN_ORIG_OUTPUT),
.DOB(bram_0_DO_B),
.ADDRA(bram_0_INPUT[9:0]),
.ADDRB(bram_0_addr_B),
.WEA(writeAndReturnOriginal_valid),
.WEB(1'd0),
.ENA(writeAndReturnOriginal_CE),
.ENB(writeAndReturnOriginal_CE),
.CLKA(CLK),
.CLKB(CLK),
.SSRA(1'b0),
.SSRB(1'b0)
);
endmodule
module linebuffer_w648_h482_T2_ymin_2_Auint8(input CLK, input process_valid, input CE, input [15:0] process_input, output [47:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
wire [15:0] addr_GET_OUTPUT;
wire [8:0] unnamedcast3912USEDMULTIPLEcast;assign unnamedcast3912USEDMULTIPLEcast = addr_GET_OUTPUT[8:0];
reg [8:0] unnamedcast3912_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast3912_delay1_validunnamednull0_CECE <= unnamedcast3912USEDMULTIPLEcast; end end
wire [15:0] lb_m0_WARO_OUT;
wire [15:0] unnamedcast3904USEDMULTIPLEcast;assign unnamedcast3904USEDMULTIPLEcast = lb_m0_WARO_OUT[15:0];
reg process_valid_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay1_validunnamednull0_CECE <= process_valid; end end
wire [15:0] lb_m1_WARO_OUT;
wire [15:0] unnamedcast3916USEDMULTIPLEcast;assign unnamedcast3916USEDMULTIPLEcast = lb_m1_WARO_OUT[15:0];
reg [7:0] unnamedcast3906_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast3906_delay1_validunnamednull0_CECE <= ({unnamedcast3904USEDMULTIPLEcast[7:0]}); end end
reg [7:0] unnamedcast3908_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast3908_delay1_validunnamednull0_CECE <= ({unnamedcast3904USEDMULTIPLEcast[15:8]}); end end
reg [7:0] unnamedcast3878_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast3878_delay1_validunnamednull0_CECE <= ({process_input[7:0]}); end end
reg [7:0] unnamedcast3878_delay2_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast3878_delay2_validunnamednull0_CECE <= unnamedcast3878_delay1_validunnamednull0_CECE; end end
reg [7:0] unnamedcast3880_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast3880_delay1_validunnamednull0_CECE <= ({process_input[15:8]}); end end
reg [7:0] unnamedcast3880_delay2_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast3880_delay2_validunnamednull0_CECE <= unnamedcast3880_delay1_validunnamednull0_CECE; end end
wire [15:0] addr_SETBY_OUTPUT;
assign process_output = {unnamedcast3880_delay2_validunnamednull0_CECE,unnamedcast3878_delay2_validunnamednull0_CECE,unnamedcast3908_delay1_validunnamednull0_CECE,unnamedcast3906_delay1_validunnamednull0_CECE,({unnamedcast3916USEDMULTIPLEcast[15:8]}),({unnamedcast3916USEDMULTIPLEcast[7:0]})};
// function: process pure=false delay=2
// function: reset pure=false delay=0
RegBy_incif_wrapuint16_323_incnil_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_addr"})) addr(.CLK(CLK), .set_valid(reset), .CE(CE), .set_inp((16'd0)), .setby_valid(process_valid), .setby_inp((1'd1)), .SETBY_OUTPUT(addr_SETBY_OUTPUT), .GET_OUTPUT(addr_GET_OUTPUT));
bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_lb_m0"})) lb_m0(.CLK(CLK), .writeAndReturnOriginal_valid(process_valid), .writeAndReturnOriginal_CE(CE), .inp({process_input,unnamedcast3912USEDMULTIPLEcast}), .WARO_OUT(lb_m0_WARO_OUT));
bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_lb_m1"})) lb_m1(.CLK(CLK), .writeAndReturnOriginal_valid(process_valid_delay1_validunnamednull0_CECE), .writeAndReturnOriginal_CE(CE), .inp({unnamedcast3904USEDMULTIPLEcast,unnamedcast3912_delay1_validunnamednull0_CECE}), .WARO_OUT(lb_m1_WARO_OUT));
endmodule
module SSR_W7_H3_T2_Auint8(input CLK, input process_valid, input process_CE, input [47:0] inp, output [191:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
reg [7:0] SR_x0_y0;
reg [7:0] SR_x1_y0;
reg [7:0] SR_x2_y0;
reg [7:0] SR_x3_y0;
reg [7:0] SR_x4_y0;
reg [7:0] SR_x5_y0;
wire [7:0] unnamedcast3738USEDMULTIPLEcast;assign unnamedcast3738USEDMULTIPLEcast = ({inp[7:0]});
wire [7:0] unnamedcast3736USEDMULTIPLEcast;assign unnamedcast3736USEDMULTIPLEcast = ({inp[15:8]});
reg [7:0] SR_x0_y1;
reg [7:0] SR_x1_y1;
reg [7:0] SR_x2_y1;
reg [7:0] SR_x3_y1;
reg [7:0] SR_x4_y1;
reg [7:0] SR_x5_y1;
wire [7:0] unnamedcast3762USEDMULTIPLEcast;assign unnamedcast3762USEDMULTIPLEcast = ({inp[23:16]});
wire [7:0] unnamedcast3760USEDMULTIPLEcast;assign unnamedcast3760USEDMULTIPLEcast = ({inp[31:24]});
reg [7:0] SR_x0_y2;
reg [7:0] SR_x1_y2;
reg [7:0] SR_x2_y2;
reg [7:0] SR_x3_y2;
reg [7:0] SR_x4_y2;
reg [7:0] SR_x5_y2;
wire [7:0] unnamedcast3786USEDMULTIPLEcast;assign unnamedcast3786USEDMULTIPLEcast = ({inp[39:32]});
wire [7:0] unnamedcast3784USEDMULTIPLEcast;assign unnamedcast3784USEDMULTIPLEcast = ({inp[47:40]});
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x5_y0 <= unnamedcast3736USEDMULTIPLEcast; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x4_y0 <= unnamedcast3738USEDMULTIPLEcast; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x3_y0 <= SR_x5_y0; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x2_y0 <= SR_x4_y0; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x1_y0 <= SR_x3_y0; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x0_y0 <= SR_x2_y0; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x5_y1 <= unnamedcast3760USEDMULTIPLEcast; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x4_y1 <= unnamedcast3762USEDMULTIPLEcast; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x3_y1 <= SR_x5_y1; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x2_y1 <= SR_x4_y1; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x1_y1 <= SR_x3_y1; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x0_y1 <= SR_x2_y1; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x5_y2 <= unnamedcast3784USEDMULTIPLEcast; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x4_y2 <= unnamedcast3786USEDMULTIPLEcast; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x3_y2 <= SR_x5_y2; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x2_y2 <= SR_x4_y2; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x1_y2 <= SR_x3_y2; end end
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x0_y2 <= SR_x2_y2; end end
assign process_output = {unnamedcast3784USEDMULTIPLEcast,unnamedcast3786USEDMULTIPLEcast,SR_x5_y2,SR_x4_y2,SR_x3_y2,SR_x2_y2,SR_x1_y2,SR_x0_y2,unnamedcast3760USEDMULTIPLEcast,unnamedcast3762USEDMULTIPLEcast,SR_x5_y1,SR_x4_y1,SR_x3_y1,SR_x2_y1,SR_x1_y1,SR_x0_y1,unnamedcast3736USEDMULTIPLEcast,unnamedcast3738USEDMULTIPLEcast,SR_x5_y0,SR_x4_y0,SR_x3_y0,SR_x2_y0,SR_x1_y0,SR_x0_y0};
// function: process pure=false delay=0
// function: reset pure=true delay=0
endmodule
module stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2(input CLK, input process_valid, input CE, input [15:0] process_input, output [191:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
wire [47:0] stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output;
reg process_valid_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay1_validunnamednull0_CECE <= process_valid; end end
reg process_valid_delay2_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay2_validunnamednull0_CECE <= process_valid_delay1_validunnamednull0_CECE; end end
wire [191:0] stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output;
assign process_output = stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output;
// function: process pure=false delay=2
// function: reset pure=false delay=0
linebuffer_w648_h482_T2_ymin_2_Auint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g"})) stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g(.CLK(CLK), .process_valid(process_valid), .CE(CE), .process_input(process_input), .process_output(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output), .reset(reset));
SSR_W7_H3_T2_Auint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f"})) stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f(.CLK(CLK), .process_valid(process_valid_delay2_validunnamednull0_CECE), .process_CE(CE), .inp(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output), .process_output(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output));
endmodule
module unpackStencil_uint8_W7_H3_T2(input CLK, input process_CE, input [191:0] inp, output [335:0] process_output);
parameter INSTANCE_NAME="INST";
wire [7:0] unnamedcast4148USEDMULTIPLEcast;assign unnamedcast4148USEDMULTIPLEcast = ({inp[15:8]});
wire [7:0] unnamedcast4150USEDMULTIPLEcast;assign unnamedcast4150USEDMULTIPLEcast = ({inp[23:16]});
wire [7:0] unnamedcast4152USEDMULTIPLEcast;assign unnamedcast4152USEDMULTIPLEcast = ({inp[31:24]});
wire [7:0] unnamedcast4154USEDMULTIPLEcast;assign unnamedcast4154USEDMULTIPLEcast = ({inp[39:32]});
wire [7:0] unnamedcast4156USEDMULTIPLEcast;assign unnamedcast4156USEDMULTIPLEcast = ({inp[47:40]});
wire [7:0] unnamedcast4158USEDMULTIPLEcast;assign unnamedcast4158USEDMULTIPLEcast = ({inp[55:48]});
wire [7:0] unnamedcast4162USEDMULTIPLEcast;assign unnamedcast4162USEDMULTIPLEcast = ({inp[79:72]});
wire [7:0] unnamedcast4164USEDMULTIPLEcast;assign unnamedcast4164USEDMULTIPLEcast = ({inp[87:80]});
wire [7:0] unnamedcast4166USEDMULTIPLEcast;assign unnamedcast4166USEDMULTIPLEcast = ({inp[95:88]});
wire [7:0] unnamedcast4168USEDMULTIPLEcast;assign unnamedcast4168USEDMULTIPLEcast = ({inp[103:96]});
wire [7:0] unnamedcast4170USEDMULTIPLEcast;assign unnamedcast4170USEDMULTIPLEcast = ({inp[111:104]});
wire [7:0] unnamedcast4172USEDMULTIPLEcast;assign unnamedcast4172USEDMULTIPLEcast = ({inp[119:112]});
wire [7:0] unnamedcast4176USEDMULTIPLEcast;assign unnamedcast4176USEDMULTIPLEcast = ({inp[143:136]});
wire [7:0] unnamedcast4178USEDMULTIPLEcast;assign unnamedcast4178USEDMULTIPLEcast = ({inp[151:144]});
wire [7:0] unnamedcast4180USEDMULTIPLEcast;assign unnamedcast4180USEDMULTIPLEcast = ({inp[159:152]});
wire [7:0] unnamedcast4182USEDMULTIPLEcast;assign unnamedcast4182USEDMULTIPLEcast = ({inp[167:160]});
wire [7:0] unnamedcast4184USEDMULTIPLEcast;assign unnamedcast4184USEDMULTIPLEcast = ({inp[175:168]});
wire [7:0] unnamedcast4186USEDMULTIPLEcast;assign unnamedcast4186USEDMULTIPLEcast = ({inp[183:176]});
assign process_output = {{({inp[191:184]}),unnamedcast4186USEDMULTIPLEcast,unnamedcast4184USEDMULTIPLEcast,unnamedcast4182USEDMULTIPLEcast,unnamedcast4180USEDMULTIPLEcast,unnamedcast4178USEDMULTIPLEcast,unnamedcast4176USEDMULTIPLEcast,({inp[127:120]}),unnamedcast4172USEDMULTIPLEcast,unnamedcast4170USEDMULTIPLEcast,unnamedcast4168USEDMULTIPLEcast,unnamedcast4166USEDMULTIPLEcast,unnamedcast4164USEDMULTIPLEcast,unnamedcast4162USEDMULTIPLEcast,({inp[63:56]}),unnamedcast4158USEDMULTIPLEcast,unnamedcast4156USEDMULTIPLEcast,unnamedcast4154USEDMULTIPLEcast,unnamedcast4152USEDMULTIPLEcast,unnamedcast4150USEDMULTIPLEcast,unnamedcast4148USEDMULTIPLEcast},{unnamedcast4186USEDMULTIPLEcast,unnamedcast4184USEDMULTIPLEcast,unnamedcast4182USEDMULTIPLEcast,unnamedcast4180USEDMULTIPLEcast,unnamedcast4178USEDMULTIPLEcast,unnamedcast4176USEDMULTIPLEcast,({inp[135:128]}),unnamedcast4172USEDMULTIPLEcast,unnamedcast4170USEDMULTIPLEcast,unnamedcast4168USEDMULTIPLEcast,unnamedcast4166USEDMULTIPLEcast,unnamedcast4164USEDMULTIPLEcast,unnamedcast4162USEDMULTIPLEcast,({inp[71:64]}),unnamedcast4158USEDMULTIPLEcast,unnamedcast4156USEDMULTIPLEcast,unnamedcast4154USEDMULTIPLEcast,unnamedcast4152USEDMULTIPLEcast,unnamedcast4150USEDMULTIPLEcast,unnamedcast4148USEDMULTIPLEcast,({inp[7:0]})}};
// function: process pure=true delay=0
endmodule
module incif_wrapuint16_646_inc2(input CLK, input CE, input [16:0] process_input, output [15:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] unnamedcast3597USEDMULTIPLEcast;assign unnamedcast3597USEDMULTIPLEcast = (process_input[15:0]);
assign process_output = (((process_input[16]))?((({(unnamedcast3597USEDMULTIPLEcast==(16'd646))})?((16'd0)):({(unnamedcast3597USEDMULTIPLEcast+(16'd2))}))):(unnamedcast3597USEDMULTIPLEcast));
// function: process pure=true delay=0
endmodule
module RegBy_incif_wrapuint16_646_inc2_CEtrue_init0(input CLK, input set_valid, input CE, input [15:0] set_inp, input setby_valid, input setby_inp, output [15:0] SETBY_OUTPUT, output [15:0] GET_OUTPUT);
parameter INSTANCE_NAME="INST";
reg [15:0] R = 16'd0;
wire [15:0] regby_inner_process_output;
always @(posedge CLK) begin if(set_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(setby_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,set_valid})+({4'b0,setby_valid})) > 5'd1) begin $display("error, function 'set' on instance 'R' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [16:0] unnamedcallArbitrate3648USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate3648USEDMULTIPLEcallArbitrate = {(set_valid||setby_valid),((set_valid)?(set_inp):(regby_inner_process_output))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate3648USEDMULTIPLEcallArbitrate[16]) && CE) begin R <= (unnamedcallArbitrate3648USEDMULTIPLEcallArbitrate[15:0]); end end
assign SETBY_OUTPUT = regby_inner_process_output;
assign GET_OUTPUT = R;
// function: set pure=false ONLY WIRE
// function: setby pure=false ONLY WIRE
// function: get pure=true ONLY WIRE
incif_wrapuint16_646_inc2 #(.INSTANCE_NAME({INSTANCE_NAME,"_regby_inner"})) regby_inner(.CLK(CLK), .CE(CE), .process_input({setby_inp,R}), .process_output(regby_inner_process_output));
endmodule
module PosSeq_W648_H482_T2(input CLK, input process_valid, input CE, output [63:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
wire [15:0] posX_posSeq_GET_OUTPUT;
wire [15:0] posY_posSeq_GET_OUTPUT;
reg [31:0] unnamedtuple3660_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedtuple3660_delay1_validunnamednull0_CECE <= {posY_posSeq_GET_OUTPUT,posX_posSeq_GET_OUTPUT}; end end
reg [15:0] unnamedbinop3664_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedbinop3664_delay1_validunnamednull0_CECE <= {(posX_posSeq_GET_OUTPUT+(16'd1))}; end end
reg [15:0] unnamedcall3659_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcall3659_delay1_validunnamednull0_CECE <= posY_posSeq_GET_OUTPUT; end end
wire [15:0] posX_posSeq_SETBY_OUTPUT;
wire [15:0] posY_posSeq_SETBY_OUTPUT;
assign process_output = {{unnamedcall3659_delay1_validunnamednull0_CECE,unnamedbinop3664_delay1_validunnamednull0_CECE},unnamedtuple3660_delay1_validunnamednull0_CECE};
// function: process pure=false delay=1
// function: reset pure=false delay=0
RegBy_incif_wrapuint16_646_inc2_CEtrue_init0 #(.INSTANCE_NAME({INSTANCE_NAME,"_posX_posSeq"})) posX_posSeq(.CLK(CLK), .set_valid(reset), .CE(CE), .set_inp((16'd0)), .setby_valid(process_valid), .setby_inp((1'd1)), .SETBY_OUTPUT(posX_posSeq_SETBY_OUTPUT), .GET_OUTPUT(posX_posSeq_GET_OUTPUT));
RegBy_incif_wrapuint16_481_incnil_CEtrue_init0 #(.INSTANCE_NAME({INSTANCE_NAME,"_posY_posSeq"})) posY_posSeq(.CLK(CLK), .set_valid(reset), .CE(CE), .set_inp((16'd0)), .setby_valid(process_valid), .setby_inp({(posX_posSeq_GET_OUTPUT==(16'd646))}), .SETBY_OUTPUT(posY_posSeq_SETBY_OUTPUT), .GET_OUTPUT(posY_posSeq_GET_OUTPUT));
endmodule
module packTupleArrays_table__0x0563bf80(input CLK, input process_CE, input [399:0] process_input, output [399:0] process_output);
parameter INSTANCE_NAME="INST";
wire [63:0] unnamedcast3515USEDMULTIPLEcast;assign unnamedcast3515USEDMULTIPLEcast = (process_input[63:0]);
wire [335:0] unnamedcast3519USEDMULTIPLEcast;assign unnamedcast3519USEDMULTIPLEcast = (process_input[399:64]);
assign process_output = {{({unnamedcast3519USEDMULTIPLEcast[335:168]}),({unnamedcast3515USEDMULTIPLEcast[63:32]})},{({unnamedcast3519USEDMULTIPLEcast[167:0]}),({unnamedcast3515USEDMULTIPLEcast[31:0]})}};
// function: process pure=true delay=0
endmodule
module index___uint16_uint16__uint8_7_3___1(input CLK, input process_CE, input [199:0] inp, output [167:0] process_output);
parameter INSTANCE_NAME="INST";
assign process_output = (inp[199:32]);
// function: process pure=true delay=0
endmodule
module index___uint16_uint16__uint8_7_3___0(input CLK, input process_CE, input [199:0] inp, output [31:0] process_output);
parameter INSTANCE_NAME="INST";
assign process_output = (inp[31:0]);
// function: process pure=true delay=0
endmodule
module kern1(input CLK, input process_CE, input [31:0] ksi, output [167:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] unnamedcast1214USEDMULTIPLEcast;assign unnamedcast1214USEDMULTIPLEcast = (16'd1);
reg [15:0] unnamedbinop1215_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1215_delay1_validunnamednull0_CEprocess_CE <= {((ksi[15:0])+unnamedcast1214USEDMULTIPLEcast)}; end end
reg [15:0] unnamedcast1214_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1214_delay1_validunnamednull0_CEprocess_CE <= unnamedcast1214USEDMULTIPLEcast; end end
reg [15:0] unnamedbinop1218_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1218_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1215_delay1_validunnamednull0_CEprocess_CE&unnamedcast1214_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedbinop1218_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1218_delay2_validunnamednull0_CEprocess_CE <= unnamedbinop1218_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedbinop1224_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1224_delay1_validunnamednull0_CEprocess_CE <= {((ksi[31:16])+unnamedcast1214USEDMULTIPLEcast)}; end end
reg [15:0] unnamedbinop1227_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1227_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1224_delay1_validunnamednull0_CEprocess_CE&unnamedcast1214_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedcast1229_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1229_delay1_validunnamednull0_CEprocess_CE <= (16'd2); end end
reg [15:0] unnamedcast1229_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1229_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1229_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedbinop1230_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1230_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1227_delay1_validunnamednull0_CEprocess_CE*unnamedcast1229_delay2_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedbinop1231_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1231_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1218_delay2_validunnamednull0_CEprocess_CE+unnamedbinop1230_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedcast1237_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1237_delay1_validunnamednull0_CEprocess_CE <= (16'd0); end end
reg [15:0] unnamedcast1237_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1237_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1237_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1237_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1237_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1237_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1237_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1237_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1237_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop1238_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1238_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1231_delay1_validunnamednull0_CEprocess_CE==unnamedcast1237_delay4_validunnamednull0_CEprocess_CE)}; end end
wire [168:0] unnamedtuple1239USEDMULTIPLEtuple;assign unnamedtuple1239USEDMULTIPLEtuple = {unnamedbinop1238_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd2, 8'd0, 8'd2, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0})};
reg [15:0] unnamedcast1214_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1214_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1214_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1214_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1214_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1214_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1214_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1214_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1214_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop1242_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1242_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1231_delay1_validunnamednull0_CEprocess_CE==unnamedcast1214_delay4_validunnamednull0_CEprocess_CE)}; end end
reg [168:0] unnamedselect1254_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect1254_delay1_validunnamednull0_CEprocess_CE <= (((unnamedtuple1239USEDMULTIPLEtuple[168]))?(unnamedtuple1239USEDMULTIPLEtuple):({unnamedbinop1242_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd4, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0})})); end end
reg [15:0] unnamedcast1229_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1229_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1229_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1229_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1229_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1229_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop1246_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1246_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1231_delay1_validunnamednull0_CEprocess_CE==unnamedcast1229_delay4_validunnamednull0_CEprocess_CE)}; end end
wire [168:0] unnamedtuple1247USEDMULTIPLEtuple;assign unnamedtuple1247USEDMULTIPLEtuple = {unnamedbinop1246_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd0, 8'd1, 8'd0, 8'd1, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd1, 8'd0, 8'd1})};
reg [15:0] unnamedcast1249_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1249_delay1_validunnamednull0_CEprocess_CE <= (16'd3); end end
reg [15:0] unnamedcast1249_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1249_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1249_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1249_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1249_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1249_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1249_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1249_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1249_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop1250_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1250_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1231_delay1_validunnamednull0_CEprocess_CE==unnamedcast1249_delay4_validunnamednull0_CEprocess_CE)}; end end
reg [168:0] unnamedselect1257_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect1257_delay1_validunnamednull0_CEprocess_CE <= (((unnamedtuple1247USEDMULTIPLEtuple[168]))?(unnamedtuple1247USEDMULTIPLEtuple):({unnamedbinop1250_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd2, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd2, 8'd0})})); end end
reg [168:0] unnamedselect1260_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect1260_delay1_validunnamednull0_CEprocess_CE <= (((unnamedselect1254_delay1_validunnamednull0_CEprocess_CE[168]))?(unnamedselect1254_delay1_validunnamednull0_CEprocess_CE):(unnamedselect1257_delay1_validunnamednull0_CEprocess_CE)); end end
assign process_output = (unnamedselect1260_delay1_validunnamednull0_CEprocess_CE[167:0]);
// function: process pure=true delay=7
endmodule
module packTupleArrays_table__0x059d9250(input CLK, input process_CE, input [335:0] process_input, output [335:0] process_output);
parameter INSTANCE_NAME="INST";
wire [167:0] unnamedcast1357USEDMULTIPLEcast;assign unnamedcast1357USEDMULTIPLEcast = (process_input[167:0]);
wire [167:0] unnamedcast1361USEDMULTIPLEcast;assign unnamedcast1361USEDMULTIPLEcast = (process_input[335:168]);
assign process_output = {{({unnamedcast1361USEDMULTIPLEcast[167:160]}),({unnamedcast1357USEDMULTIPLEcast[167:160]})},{({unnamedcast1361USEDMULTIPLEcast[159:152]}),({unnamedcast1357USEDMULTIPLEcast[159:152]})},{({unnamedcast1361USEDMULTIPLEcast[151:144]}),({unnamedcast1357USEDMULTIPLEcast[151:144]})},{({unnamedcast1361USEDMULTIPLEcast[143:136]}),({unnamedcast1357USEDMULTIPLEcast[143:136]})},{({unnamedcast1361USEDMULTIPLEcast[135:128]}),({unnamedcast1357USEDMULTIPLEcast[135:128]})},{({unnamedcast1361USEDMULTIPLEcast[127:120]}),({unnamedcast1357USEDMULTIPLEcast[127:120]})},{({unnamedcast1361USEDMULTIPLEcast[119:112]}),({unnamedcast1357USEDMULTIPLEcast[119:112]})},{({unnamedcast1361USEDMULTIPLEcast[111:104]}),({unnamedcast1357USEDMULTIPLEcast[111:104]})},{({unnamedcast1361USEDMULTIPLEcast[103:96]}),({unnamedcast1357USEDMULTIPLEcast[103:96]})},{({unnamedcast1361USEDMULTIPLEcast[95:88]}),({unnamedcast1357USEDMULTIPLEcast[95:88]})},{({unnamedcast1361USEDMULTIPLEcast[87:80]}),({unnamedcast1357USEDMULTIPLEcast[87:80]})},{({unnamedcast1361USEDMULTIPLEcast[79:72]}),({unnamedcast1357USEDMULTIPLEcast[79:72]})},{({unnamedcast1361USEDMULTIPLEcast[71:64]}),({unnamedcast1357USEDMULTIPLEcast[71:64]})},{({unnamedcast1361USEDMULTIPLEcast[63:56]}),({unnamedcast1357USEDMULTIPLEcast[63:56]})},{({unnamedcast1361USEDMULTIPLEcast[55:48]}),({unnamedcast1357USEDMULTIPLEcast[55:48]})},{({unnamedcast1361USEDMULTIPLEcast[47:40]}),({unnamedcast1357USEDMULTIPLEcast[47:40]})},{({unnamedcast1361USEDMULTIPLEcast[39:32]}),({unnamedcast1357USEDMULTIPLEcast[39:32]})},{({unnamedcast1361USEDMULTIPLEcast[31:24]}),({unnamedcast1357USEDMULTIPLEcast[31:24]})},{({unnamedcast1361USEDMULTIPLEcast[23:16]}),({unnamedcast1357USEDMULTIPLEcast[23:16]})},{({unnamedcast1361USEDMULTIPLEcast[15:8]}),({unnamedcast1357USEDMULTIPLEcast[15:8]})},{({unnamedcast1361USEDMULTIPLEcast[7:0]}),({unnamedcast1357USEDMULTIPLEcast[7:0]})}};
// function: process pure=true delay=0
endmodule
module partial_mult_Auint8_Buint8(input CLK, input process_CE, input [15:0] inp, output [15:0] process_output);
parameter INSTANCE_NAME="INST";
reg [15:0] unnamedbinop1553_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1553_delay1_validunnamednull0_CEprocess_CE <= {({8'b0,(inp[7:0])}*{8'b0,(inp[15:8])})}; end end
assign process_output = unnamedbinop1553_delay1_validunnamednull0_CEprocess_CE;
// function: process pure=true delay=1
endmodule
module map_partial_mult_Auint8_Buint8_W7_H3(input CLK, input process_CE, input [335:0] process_input, output [335:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] inner0_0_process_output;
wire [15:0] inner1_0_process_output;
wire [15:0] inner2_0_process_output;
wire [15:0] inner3_0_process_output;
wire [15:0] inner4_0_process_output;
wire [15:0] inner5_0_process_output;
wire [15:0] inner6_0_process_output;
wire [15:0] inner0_1_process_output;
wire [15:0] inner1_1_process_output;
wire [15:0] inner2_1_process_output;
wire [15:0] inner3_1_process_output;
wire [15:0] inner4_1_process_output;
wire [15:0] inner5_1_process_output;
wire [15:0] inner6_1_process_output;
wire [15:0] inner0_2_process_output;
wire [15:0] inner1_2_process_output;
wire [15:0] inner2_2_process_output;
wire [15:0] inner3_2_process_output;
wire [15:0] inner4_2_process_output;
wire [15:0] inner5_2_process_output;
wire [15:0] inner6_2_process_output;
assign process_output = {inner6_2_process_output,inner5_2_process_output,inner4_2_process_output,inner3_2_process_output,inner2_2_process_output,inner1_2_process_output,inner0_2_process_output,inner6_1_process_output,inner5_1_process_output,inner4_1_process_output,inner3_1_process_output,inner2_1_process_output,inner1_1_process_output,inner0_1_process_output,inner6_0_process_output,inner5_0_process_output,inner4_0_process_output,inner3_0_process_output,inner2_0_process_output,inner1_0_process_output,inner0_0_process_output};
// function: process pure=true delay=1
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_0"})) inner0_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[15:0]})), .process_output(inner0_0_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_0"})) inner1_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[31:16]})), .process_output(inner1_0_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner2_0"})) inner2_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[47:32]})), .process_output(inner2_0_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner3_0"})) inner3_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[63:48]})), .process_output(inner3_0_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner4_0"})) inner4_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[79:64]})), .process_output(inner4_0_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner5_0"})) inner5_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[95:80]})), .process_output(inner5_0_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner6_0"})) inner6_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[111:96]})), .process_output(inner6_0_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_1"})) inner0_1(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[127:112]})), .process_output(inner0_1_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_1"})) inner1_1(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[143:128]})), .process_output(inner1_1_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner2_1"})) inner2_1(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[159:144]})), .process_output(inner2_1_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner3_1"})) inner3_1(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[175:160]})), .process_output(inner3_1_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner4_1"})) inner4_1(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[191:176]})), .process_output(inner4_1_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner5_1"})) inner5_1(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[207:192]})), .process_output(inner5_1_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner6_1"})) inner6_1(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[223:208]})), .process_output(inner6_1_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_2"})) inner0_2(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[239:224]})), .process_output(inner0_2_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_2"})) inner1_2(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[255:240]})), .process_output(inner1_2_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner2_2"})) inner2_2(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[271:256]})), .process_output(inner2_2_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner3_2"})) inner3_2(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[287:272]})), .process_output(inner3_2_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner4_2"})) inner4_2(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[303:288]})), .process_output(inner4_2_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner5_2"})) inner5_2(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[319:304]})), .process_output(inner5_2_process_output));
partial_mult_Auint8_Buint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner6_2"})) inner6_2(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[335:320]})), .process_output(inner6_2_process_output));
endmodule
module sum_asyncfalse(input CLK, input process_CE, input [31:0] inp, output [15:0] process_output);
parameter INSTANCE_NAME="INST";
reg [15:0] unnamedbinop1637_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1637_delay1_validunnamednull0_CEprocess_CE <= {((inp[15:0])+(inp[31:16]))}; end end
assign process_output = unnamedbinop1637_delay1_validunnamednull0_CEprocess_CE;
// function: process pure=true delay=1
endmodule
module reduce_sum_asyncfalse_W7_H3(input CLK, input process_CE, input [335:0] process_input, output [15:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] inner0_process_output;
wire [15:0] inner1_process_output;
wire [15:0] inner10_process_output;
wire [15:0] inner2_process_output;
wire [15:0] inner3_process_output;
wire [15:0] inner11_process_output;
wire [15:0] inner15_process_output;
wire [15:0] inner4_process_output;
wire [15:0] inner5_process_output;
wire [15:0] inner12_process_output;
wire [15:0] inner6_process_output;
wire [15:0] inner7_process_output;
wire [15:0] inner13_process_output;
wire [15:0] inner16_process_output;
wire [15:0] inner18_process_output;
wire [15:0] inner8_process_output;
wire [15:0] inner9_process_output;
wire [15:0] inner14_process_output;
reg [15:0] unnamedcast1691_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1691_delay1_validunnamednull0_CEprocess_CE <= ({process_input[335:320]}); end end
reg [15:0] unnamedcast1691_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1691_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1691_delay1_validunnamednull0_CEprocess_CE; end end
wire [15:0] inner17_process_output;
reg [15:0] unnamedcall1727_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcall1727_delay1_validunnamednull0_CEprocess_CE <= inner17_process_output; end end
wire [15:0] inner19_process_output;
assign process_output = inner19_process_output;
// function: process pure=true delay=5
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0"})) inner0(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[31:16]}),({process_input[15:0]})}), .process_output(inner0_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1"})) inner1(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[63:48]}),({process_input[47:32]})}), .process_output(inner1_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner2"})) inner2(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[95:80]}),({process_input[79:64]})}), .process_output(inner2_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner3"})) inner3(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[127:112]}),({process_input[111:96]})}), .process_output(inner3_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner4"})) inner4(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[159:144]}),({process_input[143:128]})}), .process_output(inner4_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner5"})) inner5(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[191:176]}),({process_input[175:160]})}), .process_output(inner5_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner6"})) inner6(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[223:208]}),({process_input[207:192]})}), .process_output(inner6_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner7"})) inner7(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[255:240]}),({process_input[239:224]})}), .process_output(inner7_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner8"})) inner8(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[287:272]}),({process_input[271:256]})}), .process_output(inner8_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner9"})) inner9(.CLK(CLK), .process_CE(process_CE), .inp({({process_input[319:304]}),({process_input[303:288]})}), .process_output(inner9_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner10"})) inner10(.CLK(CLK), .process_CE(process_CE), .inp({inner1_process_output,inner0_process_output}), .process_output(inner10_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner11"})) inner11(.CLK(CLK), .process_CE(process_CE), .inp({inner3_process_output,inner2_process_output}), .process_output(inner11_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner12"})) inner12(.CLK(CLK), .process_CE(process_CE), .inp({inner5_process_output,inner4_process_output}), .process_output(inner12_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner13"})) inner13(.CLK(CLK), .process_CE(process_CE), .inp({inner7_process_output,inner6_process_output}), .process_output(inner13_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner14"})) inner14(.CLK(CLK), .process_CE(process_CE), .inp({inner9_process_output,inner8_process_output}), .process_output(inner14_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner15"})) inner15(.CLK(CLK), .process_CE(process_CE), .inp({inner11_process_output,inner10_process_output}), .process_output(inner15_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner16"})) inner16(.CLK(CLK), .process_CE(process_CE), .inp({inner13_process_output,inner12_process_output}), .process_output(inner16_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner17"})) inner17(.CLK(CLK), .process_CE(process_CE), .inp({unnamedcast1691_delay2_validunnamednull0_CEprocess_CE,inner14_process_output}), .process_output(inner17_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner18"})) inner18(.CLK(CLK), .process_CE(process_CE), .inp({inner16_process_output,inner15_process_output}), .process_output(inner18_process_output));
sum_asyncfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_inner19"})) inner19(.CLK(CLK), .process_CE(process_CE), .inp({unnamedcall1727_delay1_validunnamednull0_CEprocess_CE,inner18_process_output}), .process_output(inner19_process_output));
endmodule
module touint8(input CLK, input process_CE, input [15:0] inp, output [7:0] process_output);
parameter INSTANCE_NAME="INST";
reg [15:0] unnamedbinop1734_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1734_delay1_validunnamednull0_CEprocess_CE <= {(inp>>>(16'd2))}; end end
reg [15:0] unnamedcast1736_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1736_delay1_validunnamednull0_CEprocess_CE <= (16'd255); end end
reg unnamedbinop1737_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1737_delay1_validunnamednull0_CEprocess_CE <= {((unnamedbinop1734_delay1_validunnamednull0_CEprocess_CE)>(unnamedcast1736_delay1_validunnamednull0_CEprocess_CE))}; end end
reg [7:0] unnamedcast1740_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1740_delay1_validunnamednull0_CEprocess_CE <= (8'd255); end end
reg [7:0] unnamedcast1740_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1740_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1740_delay1_validunnamednull0_CEprocess_CE; end end
reg [7:0] unnamedcast1739_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1739_delay1_validunnamednull0_CEprocess_CE <= unnamedbinop1734_delay1_validunnamednull0_CEprocess_CE[7:0]; end end
reg [7:0] unnamedselect1741_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect1741_delay1_validunnamednull0_CEprocess_CE <= ((unnamedbinop1737_delay1_validunnamednull0_CEprocess_CE)?(unnamedcast1740_delay2_validunnamednull0_CEprocess_CE):(unnamedcast1739_delay1_validunnamednull0_CEprocess_CE)); end end
assign process_output = unnamedselect1741_delay1_validunnamednull0_CEprocess_CE;
// function: process pure=true delay=3
endmodule
module kern2(input CLK, input process_CE, input [31:0] ksi, output [167:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] unnamedcast1767USEDMULTIPLEcast;assign unnamedcast1767USEDMULTIPLEcast = (16'd1);
reg [15:0] unnamedbinop1768_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1768_delay1_validunnamednull0_CEprocess_CE <= {((ksi[15:0])+unnamedcast1767USEDMULTIPLEcast)}; end end
reg [15:0] unnamedcast1767_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1767_delay1_validunnamednull0_CEprocess_CE <= unnamedcast1767USEDMULTIPLEcast; end end
reg [15:0] unnamedbinop1771_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1771_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1768_delay1_validunnamednull0_CEprocess_CE&unnamedcast1767_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedbinop1771_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1771_delay2_validunnamednull0_CEprocess_CE <= unnamedbinop1771_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedbinop1777_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1777_delay1_validunnamednull0_CEprocess_CE <= {((ksi[31:16])+unnamedcast1767USEDMULTIPLEcast)}; end end
reg [15:0] unnamedbinop1780_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1780_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1777_delay1_validunnamednull0_CEprocess_CE&unnamedcast1767_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedcast1782_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1782_delay1_validunnamednull0_CEprocess_CE <= (16'd2); end end
reg [15:0] unnamedcast1782_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1782_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1782_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedbinop1783_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1783_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1780_delay1_validunnamednull0_CEprocess_CE*unnamedcast1782_delay2_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedbinop1784_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1784_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1771_delay2_validunnamednull0_CEprocess_CE+unnamedbinop1783_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedcast1790_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1790_delay1_validunnamednull0_CEprocess_CE <= (16'd0); end end
reg [15:0] unnamedcast1790_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1790_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1790_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1790_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1790_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1790_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1790_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1790_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1790_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop1791_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1791_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1784_delay1_validunnamednull0_CEprocess_CE==unnamedcast1790_delay4_validunnamednull0_CEprocess_CE)}; end end
wire [168:0] unnamedtuple1792USEDMULTIPLEtuple;assign unnamedtuple1792USEDMULTIPLEtuple = {unnamedbinop1791_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd4, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0})};
reg [15:0] unnamedcast1767_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1767_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1767_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1767_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1767_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1767_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1767_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1767_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1767_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop1795_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1795_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1784_delay1_validunnamednull0_CEprocess_CE==unnamedcast1767_delay4_validunnamednull0_CEprocess_CE)}; end end
reg [168:0] unnamedselect1807_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect1807_delay1_validunnamednull0_CEprocess_CE <= (((unnamedtuple1792USEDMULTIPLEtuple[168]))?(unnamedtuple1792USEDMULTIPLEtuple):({unnamedbinop1795_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd2, 8'd0, 8'd2, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0})})); end end
reg [15:0] unnamedcast1782_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1782_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1782_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1782_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1782_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1782_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop1799_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1799_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1784_delay1_validunnamednull0_CEprocess_CE==unnamedcast1782_delay4_validunnamednull0_CEprocess_CE)}; end end
wire [168:0] unnamedtuple1800USEDMULTIPLEtuple;assign unnamedtuple1800USEDMULTIPLEtuple = {unnamedbinop1799_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd2, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd2, 8'd0, 8'd0, 8'd0})};
reg [15:0] unnamedcast1802_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1802_delay1_validunnamednull0_CEprocess_CE <= (16'd3); end end
reg [15:0] unnamedcast1802_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1802_delay2_validunnamednull0_CEprocess_CE <= unnamedcast1802_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1802_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1802_delay3_validunnamednull0_CEprocess_CE <= unnamedcast1802_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast1802_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast1802_delay4_validunnamednull0_CEprocess_CE <= unnamedcast1802_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop1803_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop1803_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop1784_delay1_validunnamednull0_CEprocess_CE==unnamedcast1802_delay4_validunnamednull0_CEprocess_CE)}; end end
reg [168:0] unnamedselect1810_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect1810_delay1_validunnamednull0_CEprocess_CE <= (((unnamedtuple1800USEDMULTIPLEtuple[168]))?(unnamedtuple1800USEDMULTIPLEtuple):({unnamedbinop1803_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd1, 8'd0, 8'd1, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd1, 8'd0, 8'd1, 8'd0, 8'd0})})); end end
reg [168:0] unnamedselect1813_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect1813_delay1_validunnamednull0_CEprocess_CE <= (((unnamedselect1807_delay1_validunnamednull0_CEprocess_CE[168]))?(unnamedselect1807_delay1_validunnamednull0_CEprocess_CE):(unnamedselect1810_delay1_validunnamednull0_CEprocess_CE)); end end
assign process_output = (unnamedselect1813_delay1_validunnamednull0_CEprocess_CE[167:0]);
// function: process pure=true delay=7
endmodule
module packTupleArrays_table__0x04caecf8(input CLK, input process_CE, input [335:0] process_input, output [335:0] process_output);
parameter INSTANCE_NAME="INST";
wire [167:0] unnamedcast1910USEDMULTIPLEcast;assign unnamedcast1910USEDMULTIPLEcast = (process_input[167:0]);
wire [167:0] unnamedcast1914USEDMULTIPLEcast;assign unnamedcast1914USEDMULTIPLEcast = (process_input[335:168]);
assign process_output = {{({unnamedcast1914USEDMULTIPLEcast[167:160]}),({unnamedcast1910USEDMULTIPLEcast[167:160]})},{({unnamedcast1914USEDMULTIPLEcast[159:152]}),({unnamedcast1910USEDMULTIPLEcast[159:152]})},{({unnamedcast1914USEDMULTIPLEcast[151:144]}),({unnamedcast1910USEDMULTIPLEcast[151:144]})},{({unnamedcast1914USEDMULTIPLEcast[143:136]}),({unnamedcast1910USEDMULTIPLEcast[143:136]})},{({unnamedcast1914USEDMULTIPLEcast[135:128]}),({unnamedcast1910USEDMULTIPLEcast[135:128]})},{({unnamedcast1914USEDMULTIPLEcast[127:120]}),({unnamedcast1910USEDMULTIPLEcast[127:120]})},{({unnamedcast1914USEDMULTIPLEcast[119:112]}),({unnamedcast1910USEDMULTIPLEcast[119:112]})},{({unnamedcast1914USEDMULTIPLEcast[111:104]}),({unnamedcast1910USEDMULTIPLEcast[111:104]})},{({unnamedcast1914USEDMULTIPLEcast[103:96]}),({unnamedcast1910USEDMULTIPLEcast[103:96]})},{({unnamedcast1914USEDMULTIPLEcast[95:88]}),({unnamedcast1910USEDMULTIPLEcast[95:88]})},{({unnamedcast1914USEDMULTIPLEcast[87:80]}),({unnamedcast1910USEDMULTIPLEcast[87:80]})},{({unnamedcast1914USEDMULTIPLEcast[79:72]}),({unnamedcast1910USEDMULTIPLEcast[79:72]})},{({unnamedcast1914USEDMULTIPLEcast[71:64]}),({unnamedcast1910USEDMULTIPLEcast[71:64]})},{({unnamedcast1914USEDMULTIPLEcast[63:56]}),({unnamedcast1910USEDMULTIPLEcast[63:56]})},{({unnamedcast1914USEDMULTIPLEcast[55:48]}),({unnamedcast1910USEDMULTIPLEcast[55:48]})},{({unnamedcast1914USEDMULTIPLEcast[47:40]}),({unnamedcast1910USEDMULTIPLEcast[47:40]})},{({unnamedcast1914USEDMULTIPLEcast[39:32]}),({unnamedcast1910USEDMULTIPLEcast[39:32]})},{({unnamedcast1914USEDMULTIPLEcast[31:24]}),({unnamedcast1910USEDMULTIPLEcast[31:24]})},{({unnamedcast1914USEDMULTIPLEcast[23:16]}),({unnamedcast1910USEDMULTIPLEcast[23:16]})},{({unnamedcast1914USEDMULTIPLEcast[15:8]}),({unnamedcast1910USEDMULTIPLEcast[15:8]})},{({unnamedcast1914USEDMULTIPLEcast[7:0]}),({unnamedcast1910USEDMULTIPLEcast[7:0]})}};
// function: process pure=true delay=0
endmodule
module kern3(input CLK, input process_CE, input [31:0] ksi, output [167:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] unnamedcast2104USEDMULTIPLEcast;assign unnamedcast2104USEDMULTIPLEcast = (16'd1);
reg [15:0] unnamedbinop2105_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2105_delay1_validunnamednull0_CEprocess_CE <= {((ksi[15:0])+unnamedcast2104USEDMULTIPLEcast)}; end end
reg [15:0] unnamedcast2104_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2104_delay1_validunnamednull0_CEprocess_CE <= unnamedcast2104USEDMULTIPLEcast; end end
reg [15:0] unnamedbinop2108_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2108_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop2105_delay1_validunnamednull0_CEprocess_CE&unnamedcast2104_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedbinop2108_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2108_delay2_validunnamednull0_CEprocess_CE <= unnamedbinop2108_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedbinop2114_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2114_delay1_validunnamednull0_CEprocess_CE <= {((ksi[31:16])+unnamedcast2104USEDMULTIPLEcast)}; end end
reg [15:0] unnamedbinop2117_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2117_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop2114_delay1_validunnamednull0_CEprocess_CE&unnamedcast2104_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedcast2119_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2119_delay1_validunnamednull0_CEprocess_CE <= (16'd2); end end
reg [15:0] unnamedcast2119_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2119_delay2_validunnamednull0_CEprocess_CE <= unnamedcast2119_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedbinop2120_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2120_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop2117_delay1_validunnamednull0_CEprocess_CE*unnamedcast2119_delay2_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedbinop2121_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2121_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop2108_delay2_validunnamednull0_CEprocess_CE+unnamedbinop2120_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [15:0] unnamedcast2127_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2127_delay1_validunnamednull0_CEprocess_CE <= (16'd0); end end
reg [15:0] unnamedcast2127_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2127_delay2_validunnamednull0_CEprocess_CE <= unnamedcast2127_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast2127_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2127_delay3_validunnamednull0_CEprocess_CE <= unnamedcast2127_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast2127_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2127_delay4_validunnamednull0_CEprocess_CE <= unnamedcast2127_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop2128_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2128_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop2121_delay1_validunnamednull0_CEprocess_CE==unnamedcast2127_delay4_validunnamednull0_CEprocess_CE)}; end end
wire [168:0] unnamedtuple2129USEDMULTIPLEtuple;assign unnamedtuple2129USEDMULTIPLEtuple = {unnamedbinop2128_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd2, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd2, 8'd0, 8'd0, 8'd0})};
reg [15:0] unnamedcast2104_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2104_delay2_validunnamednull0_CEprocess_CE <= unnamedcast2104_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast2104_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2104_delay3_validunnamednull0_CEprocess_CE <= unnamedcast2104_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast2104_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2104_delay4_validunnamednull0_CEprocess_CE <= unnamedcast2104_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop2132_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2132_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop2121_delay1_validunnamednull0_CEprocess_CE==unnamedcast2104_delay4_validunnamednull0_CEprocess_CE)}; end end
reg [168:0] unnamedselect2144_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect2144_delay1_validunnamednull0_CEprocess_CE <= (((unnamedtuple2129USEDMULTIPLEtuple[168]))?(unnamedtuple2129USEDMULTIPLEtuple):({unnamedbinop2132_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd1, 8'd0, 8'd1, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd1, 8'd0, 8'd1, 8'd0, 8'd0})})); end end
reg [15:0] unnamedcast2119_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2119_delay3_validunnamednull0_CEprocess_CE <= unnamedcast2119_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast2119_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2119_delay4_validunnamednull0_CEprocess_CE <= unnamedcast2119_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop2136_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2136_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop2121_delay1_validunnamednull0_CEprocess_CE==unnamedcast2119_delay4_validunnamednull0_CEprocess_CE)}; end end
wire [168:0] unnamedtuple2137USEDMULTIPLEtuple;assign unnamedtuple2137USEDMULTIPLEtuple = {unnamedbinop2136_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd4, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0})};
reg [15:0] unnamedcast2139_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2139_delay1_validunnamednull0_CEprocess_CE <= (16'd3); end end
reg [15:0] unnamedcast2139_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2139_delay2_validunnamednull0_CEprocess_CE <= unnamedcast2139_delay1_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast2139_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2139_delay3_validunnamednull0_CEprocess_CE <= unnamedcast2139_delay2_validunnamednull0_CEprocess_CE; end end
reg [15:0] unnamedcast2139_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast2139_delay4_validunnamednull0_CEprocess_CE <= unnamedcast2139_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop2140_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop2140_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop2121_delay1_validunnamednull0_CEprocess_CE==unnamedcast2139_delay4_validunnamednull0_CEprocess_CE)}; end end
reg [168:0] unnamedselect2147_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect2147_delay1_validunnamednull0_CEprocess_CE <= (((unnamedtuple2137USEDMULTIPLEtuple[168]))?(unnamedtuple2137USEDMULTIPLEtuple):({unnamedbinop2140_delay1_validunnamednull0_CEprocess_CE,({8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd2, 8'd0, 8'd2, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0})})); end end
reg [168:0] unnamedselect2150_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect2150_delay1_validunnamednull0_CEprocess_CE <= (((unnamedselect2144_delay1_validunnamednull0_CEprocess_CE[168]))?(unnamedselect2144_delay1_validunnamednull0_CEprocess_CE):(unnamedselect2147_delay1_validunnamednull0_CEprocess_CE)); end end
assign process_output = (unnamedselect2150_delay1_validunnamednull0_CEprocess_CE[167:0]);
// function: process pure=true delay=7
endmodule
module packTupleArrays_table__0x057e92d0(input CLK, input process_CE, input [335:0] process_input, output [335:0] process_output);
parameter INSTANCE_NAME="INST";
wire [167:0] unnamedcast2247USEDMULTIPLEcast;assign unnamedcast2247USEDMULTIPLEcast = (process_input[167:0]);
wire [167:0] unnamedcast2251USEDMULTIPLEcast;assign unnamedcast2251USEDMULTIPLEcast = (process_input[335:168]);
assign process_output = {{({unnamedcast2251USEDMULTIPLEcast[167:160]}),({unnamedcast2247USEDMULTIPLEcast[167:160]})},{({unnamedcast2251USEDMULTIPLEcast[159:152]}),({unnamedcast2247USEDMULTIPLEcast[159:152]})},{({unnamedcast2251USEDMULTIPLEcast[151:144]}),({unnamedcast2247USEDMULTIPLEcast[151:144]})},{({unnamedcast2251USEDMULTIPLEcast[143:136]}),({unnamedcast2247USEDMULTIPLEcast[143:136]})},{({unnamedcast2251USEDMULTIPLEcast[135:128]}),({unnamedcast2247USEDMULTIPLEcast[135:128]})},{({unnamedcast2251USEDMULTIPLEcast[127:120]}),({unnamedcast2247USEDMULTIPLEcast[127:120]})},{({unnamedcast2251USEDMULTIPLEcast[119:112]}),({unnamedcast2247USEDMULTIPLEcast[119:112]})},{({unnamedcast2251USEDMULTIPLEcast[111:104]}),({unnamedcast2247USEDMULTIPLEcast[111:104]})},{({unnamedcast2251USEDMULTIPLEcast[103:96]}),({unnamedcast2247USEDMULTIPLEcast[103:96]})},{({unnamedcast2251USEDMULTIPLEcast[95:88]}),({unnamedcast2247USEDMULTIPLEcast[95:88]})},{({unnamedcast2251USEDMULTIPLEcast[87:80]}),({unnamedcast2247USEDMULTIPLEcast[87:80]})},{({unnamedcast2251USEDMULTIPLEcast[79:72]}),({unnamedcast2247USEDMULTIPLEcast[79:72]})},{({unnamedcast2251USEDMULTIPLEcast[71:64]}),({unnamedcast2247USEDMULTIPLEcast[71:64]})},{({unnamedcast2251USEDMULTIPLEcast[63:56]}),({unnamedcast2247USEDMULTIPLEcast[63:56]})},{({unnamedcast2251USEDMULTIPLEcast[55:48]}),({unnamedcast2247USEDMULTIPLEcast[55:48]})},{({unnamedcast2251USEDMULTIPLEcast[47:40]}),({unnamedcast2247USEDMULTIPLEcast[47:40]})},{({unnamedcast2251USEDMULTIPLEcast[39:32]}),({unnamedcast2247USEDMULTIPLEcast[39:32]})},{({unnamedcast2251USEDMULTIPLEcast[31:24]}),({unnamedcast2247USEDMULTIPLEcast[31:24]})},{({unnamedcast2251USEDMULTIPLEcast[23:16]}),({unnamedcast2247USEDMULTIPLEcast[23:16]})},{({unnamedcast2251USEDMULTIPLEcast[15:8]}),({unnamedcast2247USEDMULTIPLEcast[15:8]})},{({unnamedcast2251USEDMULTIPLEcast[7:0]}),({unnamedcast2247USEDMULTIPLEcast[7:0]})}};
// function: process pure=true delay=0
endmodule
module dem(input CLK, input CE, input [199:0] process_input, output [23:0] process_output);
parameter INSTANCE_NAME="INST";
wire [167:0] dat_process_output;
reg [167:0] unnamedcall2437_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcall2437_delay1_validunnamednull0_CECE <= dat_process_output; end end
reg [167:0] unnamedcall2437_delay2_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcall2437_delay2_validunnamednull0_CECE <= unnamedcall2437_delay1_validunnamednull0_CECE; end end
reg [167:0] unnamedcall2437_delay3_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcall2437_delay3_validunnamednull0_CECE <= unnamedcall2437_delay2_validunnamednull0_CECE; end end
reg [167:0] unnamedcall2437_delay4_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcall2437_delay4_validunnamednull0_CECE <= unnamedcall2437_delay3_validunnamednull0_CECE; end end
reg [167:0] unnamedcall2437_delay5_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcall2437_delay5_validunnamednull0_CECE <= unnamedcall2437_delay4_validunnamednull0_CECE; end end
reg [167:0] unnamedcall2437_delay6_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcall2437_delay6_validunnamednull0_CECE <= unnamedcall2437_delay5_validunnamednull0_CECE; end end
reg [167:0] unnamedcall2437_delay7_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcall2437_delay7_validunnamednull0_CECE <= unnamedcall2437_delay6_validunnamednull0_CECE; end end
wire [31:0] xy_process_output;
wire [167:0] k1_process_output;
wire [335:0] packedtup1_process_output;
wire [335:0] partialll1_process_output;
wire [15:0] sum1_process_output;
wire [7:0] touint81_process_output;
wire [167:0] k2_process_output;
wire [335:0] packedtup2_process_output;
wire [335:0] partialll2_process_output;
wire [15:0] sum2_process_output;
wire [7:0] touint82_process_output;
wire [167:0] k3_process_output;
wire [335:0] packedtup3_process_output;
wire [335:0] partialll3_process_output;
wire [15:0] sum3_process_output;
wire [7:0] touint83_process_output;
assign process_output = {touint83_process_output,touint82_process_output,touint81_process_output};
// function: process pure=true delay=16
// function: reset pure=true delay=0
index___uint16_uint16__uint8_7_3___1 #(.INSTANCE_NAME({INSTANCE_NAME,"_dat"})) dat(.CLK(CLK), .process_CE(CE), .inp(process_input), .process_output(dat_process_output));
index___uint16_uint16__uint8_7_3___0 #(.INSTANCE_NAME({INSTANCE_NAME,"_xy"})) xy(.CLK(CLK), .process_CE(CE), .inp(process_input), .process_output(xy_process_output));
kern1 #(.INSTANCE_NAME({INSTANCE_NAME,"_k1"})) k1(.CLK(CLK), .process_CE(CE), .ksi(xy_process_output), .process_output(k1_process_output));
packTupleArrays_table__0x059d9250 #(.INSTANCE_NAME({INSTANCE_NAME,"_packedtup1"})) packedtup1(.CLK(CLK), .process_CE(CE), .process_input({k1_process_output,unnamedcall2437_delay7_validunnamednull0_CECE}), .process_output(packedtup1_process_output));
map_partial_mult_Auint8_Buint8_W7_H3 #(.INSTANCE_NAME({INSTANCE_NAME,"_partialll1"})) partialll1(.CLK(CLK), .process_CE(CE), .process_input(packedtup1_process_output), .process_output(partialll1_process_output));
reduce_sum_asyncfalse_W7_H3 #(.INSTANCE_NAME({INSTANCE_NAME,"_sum1"})) sum1(.CLK(CLK), .process_CE(CE), .process_input(partialll1_process_output), .process_output(sum1_process_output));
touint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_touint81"})) touint81(.CLK(CLK), .process_CE(CE), .inp(sum1_process_output), .process_output(touint81_process_output));
kern2 #(.INSTANCE_NAME({INSTANCE_NAME,"_k2"})) k2(.CLK(CLK), .process_CE(CE), .ksi(xy_process_output), .process_output(k2_process_output));
packTupleArrays_table__0x04caecf8 #(.INSTANCE_NAME({INSTANCE_NAME,"_packedtup2"})) packedtup2(.CLK(CLK), .process_CE(CE), .process_input({k2_process_output,unnamedcall2437_delay7_validunnamednull0_CECE}), .process_output(packedtup2_process_output));
map_partial_mult_Auint8_Buint8_W7_H3 #(.INSTANCE_NAME({INSTANCE_NAME,"_partialll2"})) partialll2(.CLK(CLK), .process_CE(CE), .process_input(packedtup2_process_output), .process_output(partialll2_process_output));
reduce_sum_asyncfalse_W7_H3 #(.INSTANCE_NAME({INSTANCE_NAME,"_sum2"})) sum2(.CLK(CLK), .process_CE(CE), .process_input(partialll2_process_output), .process_output(sum2_process_output));
touint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_touint82"})) touint82(.CLK(CLK), .process_CE(CE), .inp(sum2_process_output), .process_output(touint82_process_output));
kern3 #(.INSTANCE_NAME({INSTANCE_NAME,"_k3"})) k3(.CLK(CLK), .process_CE(CE), .ksi(xy_process_output), .process_output(k3_process_output));
packTupleArrays_table__0x057e92d0 #(.INSTANCE_NAME({INSTANCE_NAME,"_packedtup3"})) packedtup3(.CLK(CLK), .process_CE(CE), .process_input({k3_process_output,unnamedcall2437_delay7_validunnamednull0_CECE}), .process_output(packedtup3_process_output));
map_partial_mult_Auint8_Buint8_W7_H3 #(.INSTANCE_NAME({INSTANCE_NAME,"_partialll3"})) partialll3(.CLK(CLK), .process_CE(CE), .process_input(packedtup3_process_output), .process_output(partialll3_process_output));
reduce_sum_asyncfalse_W7_H3 #(.INSTANCE_NAME({INSTANCE_NAME,"_sum3"})) sum3(.CLK(CLK), .process_CE(CE), .process_input(partialll3_process_output), .process_output(sum3_process_output));
touint8 #(.INSTANCE_NAME({INSTANCE_NAME,"_touint83"})) touint83(.CLK(CLK), .process_CE(CE), .inp(sum3_process_output), .process_output(touint83_process_output));
endmodule
module map_dem_W2_H1(input CLK, input process_CE, input [399:0] process_input, output [47:0] process_output);
parameter INSTANCE_NAME="INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output,inner0_0_process_output};
// function: process pure=true delay=16
dem #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_0"})) inner0_0(.CLK(CLK), .CE(process_CE), .process_input(({process_input[199:0]})), .process_output(inner0_0_process_output));
dem #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_0"})) inner1_0(.CLK(CLK), .CE(process_CE), .process_input(({process_input[399:200]})), .process_output(inner1_0_process_output));
endmodule
module liftXYSeqPointwise_lambda(input CLK, input CE, input [399:0] process_input, output [47:0] process_output);
parameter INSTANCE_NAME="INST";
wire [399:0] unp_process_output;
wire [47:0] f_process_output;
assign process_output = f_process_output;
// function: process pure=true delay=16
// function: reset pure=true delay=0
packTupleArrays_table__0x0563bf80 #(.INSTANCE_NAME({INSTANCE_NAME,"_unp"})) unp(.CLK(CLK), .process_CE(CE), .process_input(process_input), .process_output(unp_process_output));
map_dem_W2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_f"})) f(.CLK(CLK), .process_CE(CE), .process_input(unp_process_output), .process_output(f_process_output));
endmodule
module liftXYSeq_lambda(input CLK, input process_valid, input CE, input [335:0] process_input, output [47:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
wire [63:0] p_process_output;
reg [335:0] process_input_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_input_delay1_validunnamednull0_CECE <= process_input; end end
wire [47:0] m_process_output;
assign process_output = m_process_output;
// function: process pure=false delay=17
// function: reset pure=false delay=0
PosSeq_W648_H482_T2 #(.INSTANCE_NAME({INSTANCE_NAME,"_p"})) p(.CLK(CLK), .process_valid(process_valid), .CE(CE), .process_output(p_process_output), .reset(reset));
liftXYSeqPointwise_lambda #(.INSTANCE_NAME({INSTANCE_NAME,"_m"})) m(.CLK(CLK), .CE(CE), .process_input({process_input_delay1_validunnamednull0_CECE,p_process_output}), .process_output(m_process_output));
endmodule
module demtop(input CLK, input process_valid, input CE, input [15:0] process_input, output [47:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
wire [191:0] st_process_output;
wire [335:0] convstencils_process_output;
reg process_valid_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay1_validunnamednull0_CECE <= process_valid; end end
reg process_valid_delay2_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay2_validunnamednull0_CECE <= process_valid_delay1_validunnamednull0_CECE; end end
wire [47:0] dem_process_output;
assign process_output = dem_process_output;
// function: process pure=false delay=19
// function: reset pure=false delay=0
stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 #(.INSTANCE_NAME({INSTANCE_NAME,"_st"})) st(.CLK(CLK), .process_valid(process_valid), .CE(CE), .process_input(process_input), .process_output(st_process_output), .reset(reset));
unpackStencil_uint8_W7_H3_T2 #(.INSTANCE_NAME({INSTANCE_NAME,"_convstencils"})) convstencils(.CLK(CLK), .process_CE(CE), .inp(st_process_output), .process_output(convstencils_process_output));
liftXYSeq_lambda #(.INSTANCE_NAME({INSTANCE_NAME,"_dem"})) dem(.CLK(CLK), .process_valid(process_valid_delay2_validunnamednull0_CECE), .CE(CE), .process_input(convstencils_process_output), .process_output(dem_process_output), .reset(reset));
endmodule
module ccm(input CLK, input process_CE, input [23:0] ccminp, output [23:0] process_output);
parameter INSTANCE_NAME="INST";
wire [15:0] unnamedcast4399USEDMULTIPLEcast;assign unnamedcast4399USEDMULTIPLEcast = {8'b0,(8'd185)};
wire [15:0] unnamedcast4400USEDMULTIPLEcast;assign unnamedcast4400USEDMULTIPLEcast = {8'b0,({ccminp[7:0]})};
reg [15:0] unnamedbinop4401_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4401_delay1_validunnamednull0_CEprocess_CE <= {(unnamedcast4399USEDMULTIPLEcast*unnamedcast4400USEDMULTIPLEcast)}; end end
wire [15:0] unnamedcast4405USEDMULTIPLEcast;assign unnamedcast4405USEDMULTIPLEcast = {8'b0,(8'd0)};
wire [15:0] unnamedcast4406USEDMULTIPLEcast;assign unnamedcast4406USEDMULTIPLEcast = {8'b0,({ccminp[15:8]})};
reg [15:0] unnamedbinop4407_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4407_delay1_validunnamednull0_CEprocess_CE <= {(unnamedcast4405USEDMULTIPLEcast*unnamedcast4406USEDMULTIPLEcast)}; end end
wire [16:0] unnamedcast4409USEDMULTIPLEcast;assign unnamedcast4409USEDMULTIPLEcast = {1'b0,unnamedbinop4407_delay1_validunnamednull0_CEprocess_CE};
reg [16:0] unnamedbinop4410_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4410_delay1_validunnamednull0_CEprocess_CE <= {({1'b0,unnamedbinop4401_delay1_validunnamednull0_CEprocess_CE}+unnamedcast4409USEDMULTIPLEcast)}; end end
wire [15:0] unnamedcast4415USEDMULTIPLEcast;assign unnamedcast4415USEDMULTIPLEcast = {8'b0,({ccminp[23:16]})};
reg [15:0] unnamedbinop4416_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4416_delay1_validunnamednull0_CEprocess_CE <= {(unnamedcast4405USEDMULTIPLEcast*unnamedcast4415USEDMULTIPLEcast)}; end end
reg [17:0] unnamedcast4418_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4418_delay1_validunnamednull0_CEprocess_CE <= {2'b0,unnamedbinop4416_delay1_validunnamednull0_CEprocess_CE}; end end
reg [17:0] unnamedbinop4419_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4419_delay1_validunnamednull0_CEprocess_CE <= {({1'b0,unnamedbinop4410_delay1_validunnamednull0_CEprocess_CE}+unnamedcast4418_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [17:0] unnamedcast4421_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4421_delay1_validunnamednull0_CEprocess_CE <= (18'd7); end end
reg [17:0] unnamedcast4421_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4421_delay2_validunnamednull0_CEprocess_CE <= unnamedcast4421_delay1_validunnamednull0_CEprocess_CE; end end
reg [17:0] unnamedcast4421_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4421_delay3_validunnamednull0_CEprocess_CE <= unnamedcast4421_delay2_validunnamednull0_CEprocess_CE; end end
reg [17:0] unnamedbinop4422_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4422_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop4419_delay1_validunnamednull0_CEprocess_CE>>>unnamedcast4421_delay3_validunnamednull0_CEprocess_CE)}; end end
wire [10:0] unnamedcast4423USEDMULTIPLEcast;assign unnamedcast4423USEDMULTIPLEcast = unnamedbinop4422_delay1_validunnamednull0_CEprocess_CE[10:0];
reg [10:0] unnamedcast4425_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4425_delay1_validunnamednull0_CEprocess_CE <= {3'b0,(8'd255)}; end end
reg [10:0] unnamedcast4425_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4425_delay2_validunnamednull0_CEprocess_CE <= unnamedcast4425_delay1_validunnamednull0_CEprocess_CE; end end
reg [10:0] unnamedcast4425_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4425_delay3_validunnamednull0_CEprocess_CE <= unnamedcast4425_delay2_validunnamednull0_CEprocess_CE; end end
reg [10:0] unnamedcast4425_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4425_delay4_validunnamednull0_CEprocess_CE <= unnamedcast4425_delay3_validunnamednull0_CEprocess_CE; end end
reg unnamedbinop4426_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4426_delay1_validunnamednull0_CEprocess_CE <= {((unnamedcast4423USEDMULTIPLEcast)>(unnamedcast4425_delay4_validunnamednull0_CEprocess_CE))}; end end
reg [10:0] unnamedcast4428_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4428_delay1_validunnamednull0_CEprocess_CE <= (11'd255); end end
reg [10:0] unnamedcast4428_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4428_delay2_validunnamednull0_CEprocess_CE <= unnamedcast4428_delay1_validunnamednull0_CEprocess_CE; end end
reg [10:0] unnamedcast4428_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4428_delay3_validunnamednull0_CEprocess_CE <= unnamedcast4428_delay2_validunnamednull0_CEprocess_CE; end end
reg [10:0] unnamedcast4428_delay4_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4428_delay4_validunnamednull0_CEprocess_CE <= unnamedcast4428_delay3_validunnamednull0_CEprocess_CE; end end
reg [10:0] unnamedcast4428_delay5_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4428_delay5_validunnamednull0_CEprocess_CE <= unnamedcast4428_delay4_validunnamednull0_CEprocess_CE; end end
reg [10:0] unnamedcast4423_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4423_delay1_validunnamednull0_CEprocess_CE <= unnamedcast4423USEDMULTIPLEcast; end end
reg [10:0] unnamedselect4429_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect4429_delay1_validunnamednull0_CEprocess_CE <= ((unnamedbinop4426_delay1_validunnamednull0_CEprocess_CE)?(unnamedcast4428_delay5_validunnamednull0_CEprocess_CE):(unnamedcast4423_delay1_validunnamednull0_CEprocess_CE)); end end
reg [15:0] unnamedbinop4436_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4436_delay1_validunnamednull0_CEprocess_CE <= {(unnamedcast4405USEDMULTIPLEcast*unnamedcast4400USEDMULTIPLEcast)}; end end
wire [16:0] unnamedcast4443USEDMULTIPLEcast;assign unnamedcast4443USEDMULTIPLEcast = {1'b0,unnamedbinop4436_delay1_validunnamednull0_CEprocess_CE};
reg [15:0] unnamedbinop4442_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4442_delay1_validunnamednull0_CEprocess_CE <= {({8'b0,(8'd145)}*unnamedcast4406USEDMULTIPLEcast)}; end end
reg [16:0] unnamedbinop4445_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4445_delay1_validunnamednull0_CEprocess_CE <= {(unnamedcast4443USEDMULTIPLEcast+{1'b0,unnamedbinop4442_delay1_validunnamednull0_CEprocess_CE})}; end end
reg [17:0] unnamedbinop4454_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4454_delay1_validunnamednull0_CEprocess_CE <= {({1'b0,unnamedbinop4445_delay1_validunnamednull0_CEprocess_CE}+unnamedcast4418_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [17:0] unnamedbinop4457_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4457_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop4454_delay1_validunnamednull0_CEprocess_CE>>>unnamedcast4421_delay3_validunnamednull0_CEprocess_CE)}; end end
wire [10:0] unnamedcast4458USEDMULTIPLEcast;assign unnamedcast4458USEDMULTIPLEcast = unnamedbinop4457_delay1_validunnamednull0_CEprocess_CE[10:0];
reg unnamedbinop4461_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4461_delay1_validunnamednull0_CEprocess_CE <= {((unnamedcast4458USEDMULTIPLEcast)>(unnamedcast4425_delay4_validunnamednull0_CEprocess_CE))}; end end
reg [10:0] unnamedcast4458_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4458_delay1_validunnamednull0_CEprocess_CE <= unnamedcast4458USEDMULTIPLEcast; end end
reg [10:0] unnamedselect4464_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect4464_delay1_validunnamednull0_CEprocess_CE <= ((unnamedbinop4461_delay1_validunnamednull0_CEprocess_CE)?(unnamedcast4428_delay5_validunnamednull0_CEprocess_CE):(unnamedcast4458_delay1_validunnamednull0_CEprocess_CE)); end end
reg [16:0] unnamedbinop4480_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4480_delay1_validunnamednull0_CEprocess_CE <= {(unnamedcast4443USEDMULTIPLEcast+unnamedcast4409USEDMULTIPLEcast)}; end end
reg [15:0] unnamedbinop4486_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4486_delay1_validunnamednull0_CEprocess_CE <= {(unnamedcast4399USEDMULTIPLEcast*unnamedcast4415USEDMULTIPLEcast)}; end end
reg [17:0] unnamedcast4488_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4488_delay1_validunnamednull0_CEprocess_CE <= {2'b0,unnamedbinop4486_delay1_validunnamednull0_CEprocess_CE}; end end
reg [17:0] unnamedbinop4489_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4489_delay1_validunnamednull0_CEprocess_CE <= {({1'b0,unnamedbinop4480_delay1_validunnamednull0_CEprocess_CE}+unnamedcast4488_delay1_validunnamednull0_CEprocess_CE)}; end end
reg [17:0] unnamedbinop4492_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4492_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop4489_delay1_validunnamednull0_CEprocess_CE>>>unnamedcast4421_delay3_validunnamednull0_CEprocess_CE)}; end end
wire [10:0] unnamedcast4493USEDMULTIPLEcast;assign unnamedcast4493USEDMULTIPLEcast = unnamedbinop4492_delay1_validunnamednull0_CEprocess_CE[10:0];
reg unnamedbinop4496_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop4496_delay1_validunnamednull0_CEprocess_CE <= {((unnamedcast4493USEDMULTIPLEcast)>(unnamedcast4425_delay4_validunnamednull0_CEprocess_CE))}; end end
reg [10:0] unnamedcast4493_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast4493_delay1_validunnamednull0_CEprocess_CE <= unnamedcast4493USEDMULTIPLEcast; end end
reg [10:0] unnamedselect4499_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedselect4499_delay1_validunnamednull0_CEprocess_CE <= ((unnamedbinop4496_delay1_validunnamednull0_CEprocess_CE)?(unnamedcast4428_delay5_validunnamednull0_CEprocess_CE):(unnamedcast4493_delay1_validunnamednull0_CEprocess_CE)); end end
assign process_output = {unnamedselect4499_delay1_validunnamednull0_CEprocess_CE[7:0],unnamedselect4464_delay1_validunnamednull0_CEprocess_CE[7:0],unnamedselect4429_delay1_validunnamednull0_CEprocess_CE[7:0]};
// function: process pure=true delay=6
endmodule
module map_ccm_W2_H1(input CLK, input process_CE, input [47:0] process_input, output [47:0] process_output);
parameter INSTANCE_NAME="INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output,inner0_0_process_output};
// function: process pure=true delay=6
ccm #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_0"})) inner0_0(.CLK(CLK), .process_CE(process_CE), .ccminp(({process_input[23:0]})), .process_output(inner0_0_process_output));
ccm #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_0"})) inner1_0(.CLK(CLK), .process_CE(process_CE), .ccminp(({process_input[47:24]})), .process_output(inner1_0_process_output));
endmodule
module bramSDP_WAROtrue_size256_bw1_obw1_CEtrue_inittable__0x06567ce8(input CLK, input read_CE, input [7:0] inpRead, output [7:0] READ_OUT, input writeAndReturnOriginal_valid, input writeAndReturnOriginal_CE, input [15:0] inp, output [7:0] WARO_OUT);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(writeAndReturnOriginal_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'writeAndReturnOriginal'", INSTANCE_NAME); end end
wire [7:0] bram_0_READ_OUTPUT;
assign READ_OUT = {bram_0_READ_OUTPUT};
wire [7:0] unnamedcast4673;assign unnamedcast4673 = (inp[15:8]); // wire for bitslice
wire [7:0] bram_0_SET_AND_RETURN_ORIG_OUTPUT;
assign WARO_OUT = {bram_0_SET_AND_RETURN_ORIG_OUTPUT};
// function: read pure=true delay=1
// function: writeAndReturnOriginal pure=false delay=1
reg [7:0] bram_0_DI_B;
reg [10:0] bram_0_addr_B;
wire [7:0] bram_0_DO_B;
wire [18:0] bram_0_INPUT;
assign bram_0_INPUT = {unnamedcast4673[7:0],{3'b0,(inp[7:0])}};
RAMB16_S9_S9 #(.WRITE_MODE_A("READ_FIRST"),.WRITE_MODE_B("READ_FIRST"),.INIT_00(256'h2c2a29282726242322211f1e1d1b1a191816151312110f0e0c0b090706040200),.INIT_01(256'h4f4e4d4c4b4a4948474544434241403f3e3d3c3a3938373635343331302f2e2d),.INIT_02(256'h6f6f6e6d6c6b6a696867666564636261605f5e5c5b5a59585756555453525150),.INIT_03(256'h8e8d8c8b8a89898887868584838281807f7e7d7c7b7a79787776757473727170),.INIT_04(256'hacabaaa9a8a7a6a5a4a3a2a2a1a09f9e9d9c9b9a99989797969594939291908f),.INIT_05(256'hc8c7c6c5c4c4c3c2c1c0bfbebdbcbcbbbab9b8b7b6b5b4b4b3b2b1b0afaeadac),.INIT_06(256'he4e3e2e1e0dfdededddcdbdad9d8d8d7d6d5d4d3d2d1d1d0cfcecdcccbcbcac9),.INIT_07(256'hfffefdfcfbfaf9f9f8f7f6f5f4f4f3f2f1f0efefeeedecebeae9e9e8e7e6e5e4),.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)) bram_0 (
.DIPA(1'b0),
.DIPB(1'b0),
.DIA(bram_0_INPUT[18:11]),
.DIB(bram_0_DI_B),
.DOA(bram_0_SET_AND_RETURN_ORIG_OUTPUT),
.DOB(bram_0_READ_OUTPUT),
.ADDRA(bram_0_INPUT[10:0]),
.ADDRB({3'b0,inpRead}),
.WEA(writeAndReturnOriginal_valid),
.WEB(1'd0),
.ENA(writeAndReturnOriginal_CE),
.ENB(read_CE),
.CLKA(CLK),
.CLKB(CLK),
.SSRA(1'b0),
.SSRB(1'b0)
);
endmodule
module LUT(input CLK, input process_valid, input process_CE, input [7:0] process_input, output [7:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
wire [7:0] LUT_READ_OUT;
wire [7:0] LUT_WARO_OUT;
assign process_output = LUT_READ_OUT;
// function: process pure=false delay=1
bramSDP_WAROtrue_size256_bw1_obw1_CEtrue_inittable__0x06567ce8 #(.INSTANCE_NAME({INSTANCE_NAME,"_LUT"})) LUT(.CLK(CLK), .read_CE(process_CE), .inpRead(process_input), .READ_OUT(LUT_READ_OUT), .writeAndReturnOriginal_valid({((1'd0)&&process_valid)}), .writeAndReturnOriginal_CE(process_CE), .inp({(8'd0),process_input}), .WARO_OUT(LUT_WARO_OUT));
endmodule
module map_LUT_W3_H1(input CLK, input process_valid, input process_CE, input [23:0] process_input, output [23:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
wire [7:0] inner2_0_process_output;
assign process_output = {inner2_0_process_output,inner1_0_process_output,inner0_0_process_output};
// function: process pure=false delay=1
LUT #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_0"})) inner0_0(.CLK(CLK), .process_valid(process_valid), .process_CE(process_CE), .process_input(({process_input[7:0]})), .process_output(inner0_0_process_output));
LUT #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_0"})) inner1_0(.CLK(CLK), .process_valid(process_valid), .process_CE(process_CE), .process_input(({process_input[15:8]})), .process_output(inner1_0_process_output));
LUT #(.INSTANCE_NAME({INSTANCE_NAME,"_inner2_0"})) inner2_0(.CLK(CLK), .process_valid(process_valid), .process_CE(process_CE), .process_input(({process_input[23:16]})), .process_output(inner2_0_process_output));
endmodule
module map_map_LUT_W3_H1_W2_H1(input CLK, input process_valid, input process_CE, input [47:0] process_input, output [47:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output,inner0_0_process_output};
// function: process pure=false delay=1
map_LUT_W3_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_0"})) inner0_0(.CLK(CLK), .process_valid(process_valid), .process_CE(process_CE), .process_input(({process_input[23:0]})), .process_output(inner0_0_process_output));
map_LUT_W3_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_0"})) inner1_0(.CLK(CLK), .process_valid(process_valid), .process_CE(process_CE), .process_input(({process_input[47:24]})), .process_output(inner1_0_process_output));
endmodule
module addChan(input CLK, input process_CE, input [23:0] inp, output [31:0] process_output);
parameter INSTANCE_NAME="INST";
assign process_output = {(8'd0),({inp[23:16]}),({inp[15:8]}),({inp[7:0]})};
// function: process pure=true delay=0
endmodule
module map_addChan_W2_H1(input CLK, input process_CE, input [47:0] process_input, output [63:0] process_output);
parameter INSTANCE_NAME="INST";
wire [31:0] inner0_0_process_output;
wire [31:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output,inner0_0_process_output};
// function: process pure=true delay=0
addChan #(.INSTANCE_NAME({INSTANCE_NAME,"_inner0_0"})) inner0_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[23:0]})), .process_output(inner0_0_process_output));
addChan #(.INSTANCE_NAME({INSTANCE_NAME,"_inner1_0"})) inner1_0(.CLK(CLK), .process_CE(process_CE), .inp(({process_input[47:24]})), .process_output(inner1_0_process_output));
endmodule
module campipe(input CLK, input process_valid, input CE, input [15:0] process_input, output [63:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
wire [15:0] bl_process_output;
reg process_valid_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay1_validunnamednull0_CECE <= process_valid; end end
reg process_valid_delay2_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay2_validunnamednull0_CECE <= process_valid_delay1_validunnamednull0_CECE; end end
reg process_valid_delay3_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay3_validunnamednull0_CECE <= process_valid_delay2_validunnamednull0_CECE; end end
reg process_valid_delay4_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay4_validunnamednull0_CECE <= process_valid_delay3_validunnamednull0_CECE; end end
reg process_valid_delay5_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay5_validunnamednull0_CECE <= process_valid_delay4_validunnamednull0_CECE; end end
reg process_valid_delay6_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay6_validunnamednull0_CECE <= process_valid_delay5_validunnamednull0_CECE; end end
wire [47:0] dem_process_output;
wire [47:0] ccm_process_output;
reg process_valid_delay7_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay7_validunnamednull0_CECE <= process_valid_delay6_validunnamednull0_CECE; end end
reg process_valid_delay8_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay8_validunnamednull0_CECE <= process_valid_delay7_validunnamednull0_CECE; end end
reg process_valid_delay9_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay9_validunnamednull0_CECE <= process_valid_delay8_validunnamednull0_CECE; end end
reg process_valid_delay10_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay10_validunnamednull0_CECE <= process_valid_delay9_validunnamednull0_CECE; end end
reg process_valid_delay11_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay11_validunnamednull0_CECE <= process_valid_delay10_validunnamednull0_CECE; end end
reg process_valid_delay12_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay12_validunnamednull0_CECE <= process_valid_delay11_validunnamednull0_CECE; end end
reg process_valid_delay13_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay13_validunnamednull0_CECE <= process_valid_delay12_validunnamednull0_CECE; end end
reg process_valid_delay14_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay14_validunnamednull0_CECE <= process_valid_delay13_validunnamednull0_CECE; end end
reg process_valid_delay15_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay15_validunnamednull0_CECE <= process_valid_delay14_validunnamednull0_CECE; end end
reg process_valid_delay16_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay16_validunnamednull0_CECE <= process_valid_delay15_validunnamednull0_CECE; end end
reg process_valid_delay17_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay17_validunnamednull0_CECE <= process_valid_delay16_validunnamednull0_CECE; end end
reg process_valid_delay18_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay18_validunnamednull0_CECE <= process_valid_delay17_validunnamednull0_CECE; end end
reg process_valid_delay19_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay19_validunnamednull0_CECE <= process_valid_delay18_validunnamednull0_CECE; end end
reg process_valid_delay20_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay20_validunnamednull0_CECE <= process_valid_delay19_validunnamednull0_CECE; end end
reg process_valid_delay21_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay21_validunnamednull0_CECE <= process_valid_delay20_validunnamednull0_CECE; end end
reg process_valid_delay22_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay22_validunnamednull0_CECE <= process_valid_delay21_validunnamednull0_CECE; end end
reg process_valid_delay23_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay23_validunnamednull0_CECE <= process_valid_delay22_validunnamednull0_CECE; end end
reg process_valid_delay24_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay24_validunnamednull0_CECE <= process_valid_delay23_validunnamednull0_CECE; end end
reg process_valid_delay25_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay25_validunnamednull0_CECE <= process_valid_delay24_validunnamednull0_CECE; end end
reg process_valid_delay26_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay26_validunnamednull0_CECE <= process_valid_delay25_validunnamednull0_CECE; end end
reg process_valid_delay27_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay27_validunnamednull0_CECE <= process_valid_delay26_validunnamednull0_CECE; end end
reg process_valid_delay28_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay28_validunnamednull0_CECE <= process_valid_delay27_validunnamednull0_CECE; end end
reg process_valid_delay29_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay29_validunnamednull0_CECE <= process_valid_delay28_validunnamednull0_CECE; end end
reg process_valid_delay30_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay30_validunnamednull0_CECE <= process_valid_delay29_validunnamednull0_CECE; end end
reg process_valid_delay31_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_valid_delay31_validunnamednull0_CECE <= process_valid_delay30_validunnamednull0_CECE; end end
wire [47:0] gam_process_output;
wire [63:0] addchan_process_output;
assign process_output = addchan_process_output;
// function: process pure=false delay=32
// function: reset pure=false delay=0
map_blackLevel_W2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_bl"})) bl(.CLK(CLK), .process_CE(CE), .process_input(process_input), .process_output(bl_process_output));
demtop #(.INSTANCE_NAME({INSTANCE_NAME,"_dem"})) dem(.CLK(CLK), .process_valid(process_valid_delay6_validunnamednull0_CECE), .CE(CE), .process_input(bl_process_output), .process_output(dem_process_output), .reset(reset));
map_ccm_W2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_ccm"})) ccm(.CLK(CLK), .process_CE(CE), .process_input(dem_process_output), .process_output(ccm_process_output));
map_map_LUT_W3_H1_W2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_gam"})) gam(.CLK(CLK), .process_valid(process_valid_delay31_validunnamednull0_CECE), .process_CE(CE), .process_input(ccm_process_output), .process_output(gam_process_output));
map_addChan_W2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_addchan"})) addchan(.CLK(CLK), .process_CE(CE), .process_input(gam_process_output), .process_output(addchan_process_output));
endmodule
module MakeHandshake_campipe(input CLK, input ready_downstream, output ready, input reset, input [16:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
assign ready = ready_downstream;
wire unnamedbinop5482USEDMULTIPLEbinop;assign unnamedbinop5482USEDMULTIPLEbinop = {(ready_downstream||reset)};
wire unnamedcast5490USEDMULTIPLEcast;assign unnamedcast5490USEDMULTIPLEcast = (process_input[16]);
wire [63:0] inner_process_output;
wire validBitDelay_campipe_pushPop_out;
always @(posedge CLK) begin if({(~{(unnamedcast5490USEDMULTIPLEcast===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: MakeHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign process_output = {validBitDelay_campipe_pushPop_out,inner_process_output};
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
ShiftRegister_32_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_validBitDelay_campipe"})) validBitDelay_campipe(.CLK(CLK), .pushPop_valid({(~reset)}), .CE(unnamedbinop5482USEDMULTIPLEbinop), .sr_input(unnamedcast5490USEDMULTIPLEcast), .pushPop_out(validBitDelay_campipe_pushPop_out), .reset(reset));
campipe #(.INSTANCE_NAME({INSTANCE_NAME,"_inner"})) inner(.CLK(CLK), .process_valid(unnamedcast5490USEDMULTIPLEcast), .CE(unnamedbinop5482USEDMULTIPLEbinop), .process_input((process_input[15:0])), .process_output(inner_process_output), .reset(reset));
endmodule
module SSR_W2_H1_T2_Auint8_4_1_(input CLK, input process_valid, input process_CE, input [63:0] inp, output [95:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
reg [31:0] SR_x0_y0;
wire [31:0] unnamedcast5496USEDMULTIPLEcast;assign unnamedcast5496USEDMULTIPLEcast = ({inp[63:32]});
always @ (posedge CLK) begin if (process_valid && process_CE) begin SR_x0_y0 <= unnamedcast5496USEDMULTIPLEcast; end end
assign process_output = {unnamedcast5496USEDMULTIPLEcast,({inp[31:0]}),SR_x0_y0};
// function: process pure=false delay=0
// function: reset pure=true delay=0
endmodule
module slice_typeuint8_4_1__3_1__xl0_xh1_yl0_yh0(input CLK, input process_CE, input [95:0] inp, output [63:0] process_output);
parameter INSTANCE_NAME="INST";
assign process_output = {({inp[63:32]}),({inp[31:0]})};
// function: process pure=true delay=0
endmodule
module CropSeq_uint8_4_1__W648_H482_T2(input CLK, input process_CE, input [127:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
reg [63:0] unnamedcast5522_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast5522_delay1_validunnamednull0_CEprocess_CE <= (process_input[127:64]); end end
reg [63:0] unnamedcast5522_delay2_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast5522_delay2_validunnamednull0_CEprocess_CE <= unnamedcast5522_delay1_validunnamednull0_CEprocess_CE; end end
reg [63:0] unnamedcast5522_delay3_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedcast5522_delay3_validunnamednull0_CEprocess_CE <= unnamedcast5522_delay2_validunnamednull0_CEprocess_CE; end end
wire [63:0] unnamedcast5524;assign unnamedcast5524 = (process_input[63:0]); // wire for array index
wire [31:0] unnamedcast5526USEDMULTIPLEcast;assign unnamedcast5526USEDMULTIPLEcast = ({unnamedcast5524[31:0]});
wire [15:0] unnamedcast5528USEDMULTIPLEcast;assign unnamedcast5528USEDMULTIPLEcast = (unnamedcast5526USEDMULTIPLEcast[15:0]);
reg unnamedbinop5540_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop5540_delay1_validunnamednull0_CEprocess_CE <= {((unnamedcast5528USEDMULTIPLEcast)>=((16'd8)))}; end end
wire [15:0] unnamedcast5534USEDMULTIPLEcast;assign unnamedcast5534USEDMULTIPLEcast = (unnamedcast5526USEDMULTIPLEcast[31:16]);
reg unnamedbinop5542_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop5542_delay1_validunnamednull0_CEprocess_CE <= {((unnamedcast5534USEDMULTIPLEcast)>=((16'd2)))}; end end
reg unnamedbinop5543_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop5543_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop5540_delay1_validunnamednull0_CEprocess_CE&&unnamedbinop5542_delay1_validunnamednull0_CEprocess_CE)}; end end
reg unnamedbinop5545_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop5545_delay1_validunnamednull0_CEprocess_CE <= {((unnamedcast5528USEDMULTIPLEcast)<((16'd648)))}; end end
reg unnamedbinop5547_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop5547_delay1_validunnamednull0_CEprocess_CE <= {((unnamedcast5534USEDMULTIPLEcast)<((16'd482)))}; end end
reg unnamedbinop5548_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop5548_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop5545_delay1_validunnamednull0_CEprocess_CE&&unnamedbinop5547_delay1_validunnamednull0_CEprocess_CE)}; end end
reg unnamedbinop5549_delay1_validunnamednull0_CEprocess_CE; always @ (posedge CLK) begin if (process_CE) begin unnamedbinop5549_delay1_validunnamednull0_CEprocess_CE <= {(unnamedbinop5543_delay1_validunnamednull0_CEprocess_CE&&unnamedbinop5548_delay1_validunnamednull0_CEprocess_CE)}; end end
assign process_output = {unnamedbinop5549_delay1_validunnamednull0_CEprocess_CE,unnamedcast5522_delay3_validunnamednull0_CEprocess_CE};
// function: process pure=true delay=3
endmodule
module liftXYSeq_lift_CropSeq_uint8_4_1__W648_H482_T2(input CLK, input process_valid, input CE, input [63:0] process_input, output [64:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
wire [63:0] p_process_output;
reg [63:0] process_input_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_input_delay1_validunnamednull0_CECE <= process_input; end end
wire [64:0] m_process_output;
assign process_output = m_process_output;
// function: process pure=false delay=4
// function: reset pure=false delay=0
PosSeq_W648_H482_T2 #(.INSTANCE_NAME({INSTANCE_NAME,"_p"})) p(.CLK(CLK), .process_valid(process_valid), .CE(CE), .process_output(p_process_output), .reset(reset));
CropSeq_uint8_4_1__W648_H482_T2 #(.INSTANCE_NAME({INSTANCE_NAME,"_m"})) m(.CLK(CLK), .process_CE(CE), .process_input({process_input_delay1_validunnamednull0_CECE,p_process_output}), .process_output(m_process_output));
endmodule
module cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0(input CLK, input process_valid, input CE, input [63:0] process_input, output [64:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
wire [95:0] SSR_process_output;
wire [63:0] slice_process_output;
wire [64:0] crop_process_output;
assign process_output = crop_process_output;
// function: process pure=false delay=4
// function: reset pure=false delay=0
SSR_W2_H1_T2_Auint8_4_1_ #(.INSTANCE_NAME({INSTANCE_NAME,"_SSR"})) SSR(.CLK(CLK), .process_valid(process_valid), .process_CE(CE), .inp(process_input), .process_output(SSR_process_output));
slice_typeuint8_4_1__3_1__xl0_xh1_yl0_yh0 #(.INSTANCE_NAME({INSTANCE_NAME,"_slice"})) slice(.CLK(CLK), .process_CE(CE), .inp(SSR_process_output), .process_output(slice_process_output));
liftXYSeq_lift_CropSeq_uint8_4_1__W648_H482_T2 #(.INSTANCE_NAME({INSTANCE_NAME,"_crop"})) crop(.CLK(CLK), .process_valid(process_valid), .CE(CE), .process_input(slice_process_output), .process_output(crop_process_output), .reset(reset));
endmodule
module LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0(input CLK, output ready, input reset, input CE, input process_valid, input [64:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
assign ready = (1'd1);
wire unnamedcast5663USEDMULTIPLEcast;assign unnamedcast5663USEDMULTIPLEcast = (process_input[64]);
wire [64:0] LiftDecimate_process_output;
reg [63:0] unnamedcast5666_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast5666_delay1_validunnamednull0_CECE <= (LiftDecimate_process_output[63:0]); end end
reg unnamedcast5663_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast5663_delay1_validunnamednull0_CECE <= unnamedcast5663USEDMULTIPLEcast; end end
reg unnamedcast5663_delay2_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast5663_delay2_validunnamednull0_CECE <= unnamedcast5663_delay1_validunnamednull0_CECE; end end
reg unnamedcast5663_delay3_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast5663_delay3_validunnamednull0_CECE <= unnamedcast5663_delay2_validunnamednull0_CECE; end end
reg unnamedcast5663_delay4_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast5663_delay4_validunnamednull0_CECE <= unnamedcast5663_delay3_validunnamednull0_CECE; end end
reg unnamedbinop5671_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedbinop5671_delay1_validunnamednull0_CECE <= {((LiftDecimate_process_output[64])&&unnamedcast5663_delay4_validunnamednull0_CECE)}; end end
assign process_output = {unnamedbinop5671_delay1_validunnamednull0_CECE,unnamedcast5666_delay1_validunnamednull0_CECE};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=5
cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0 #(.INSTANCE_NAME({INSTANCE_NAME,"_LiftDecimate"})) LiftDecimate(.CLK(CLK), .process_valid({(unnamedcast5663USEDMULTIPLEcast&&process_valid)}), .CE(CE), .process_input((process_input[63:0])), .process_output(LiftDecimate_process_output), .reset(reset));
endmodule
module ShiftRegister_5_CEtrue_TY1(input CLK, input pushPop_valid, input CE, input sr_input, output pushPop_out, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'pushPop'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
reg SR5;
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR1' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR1' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR1' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5774USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5774USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(sr_input):((1'd0)))};
reg SR1; always @ (posedge CLK) begin if ((unnamedcallArbitrate5774USEDMULTIPLEcallArbitrate[1]) && CE) begin SR1 <= (unnamedcallArbitrate5774USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR2' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR2' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR2' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5780USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5780USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR1):((1'd0)))};
reg SR2; always @ (posedge CLK) begin if ((unnamedcallArbitrate5780USEDMULTIPLEcallArbitrate[1]) && CE) begin SR2 <= (unnamedcallArbitrate5780USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR3' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR3' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR3' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5786USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5786USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR2):((1'd0)))};
reg SR3; always @ (posedge CLK) begin if ((unnamedcallArbitrate5786USEDMULTIPLEcallArbitrate[1]) && CE) begin SR3 <= (unnamedcallArbitrate5786USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR4' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR4' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR4' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5792USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5792USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR3):((1'd0)))};
reg SR4; always @ (posedge CLK) begin if ((unnamedcallArbitrate5792USEDMULTIPLEcallArbitrate[1]) && CE) begin SR4 <= (unnamedcallArbitrate5792USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR5' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR5' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR5' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate5798USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate5798USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR4):((1'd0)))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate5798USEDMULTIPLEcallArbitrate[1]) && CE) begin SR5 <= (unnamedcallArbitrate5798USEDMULTIPLEcallArbitrate[0]); end end
assign pushPop_out = SR5;
// function: pushPop pure=false delay=0
// function: reset pure=false delay=0
endmodule
module LiftHandshake_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0(input CLK, input ready_downstream, output ready, input reset, input [64:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire inner_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_ready;
assign ready = {(inner_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_ready&&ready_downstream)};
wire unnamedbinop5711USEDMULTIPLEbinop;assign unnamedbinop5711USEDMULTIPLEbinop = {(reset||ready_downstream)};
wire unnamedunary5712USEDMULTIPLEunary;assign unnamedunary5712USEDMULTIPLEunary = {(~reset)};
wire [64:0] inner_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_process_output;
wire validBitDelay_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_pushPop_out;
wire [64:0] unnamedtuple5812USEDMULTIPLEtuple;assign unnamedtuple5812USEDMULTIPLEtuple = {{((inner_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_process_output[64])&&validBitDelay_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_pushPop_out)},(inner_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_process_output[63:0])};
always @(posedge CLK) begin if({(~{((unnamedtuple5812USEDMULTIPLEtuple[64])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: output valid bit should not be X!",INSTANCE_NAME); end end
always @(posedge CLK) begin if({(~{((process_input[64])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign process_output = unnamedtuple5812USEDMULTIPLEtuple;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0"})) inner_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0(.CLK(CLK), .ready(inner_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_ready), .reset(reset), .CE(unnamedbinop5711USEDMULTIPLEbinop), .process_valid(unnamedunary5712USEDMULTIPLEunary), .process_input(process_input), .process_output(inner_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_process_output));
ShiftRegister_5_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_validBitDelay_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0"})) validBitDelay_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0(.CLK(CLK), .pushPop_valid(unnamedunary5712USEDMULTIPLEunary), .CE(unnamedbinop5711USEDMULTIPLEbinop), .sr_input((1'd1)), .pushPop_out(validBitDelay_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0_pushPop_out), .reset(reset));
endmodule
module hsfn_uint8L3_R3_B1_T1_W640_H480function__0x05007498(input CLK, input ready_downstream, output ready, input reset, input [16:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire [2:0] unnamedtuple7497USEDMULTIPLEtuple;assign unnamedtuple7497USEDMULTIPLEtuple = {(1'd1),(1'd1),ready_downstream};
wire f1_store_ready;
wire pad_ready;
wire f2_store_ready;
wire crop_ready;
wire HH_ready;
wire f1_load_ready;
wire f2_load_ready;
assign ready = pad_ready;
wire [0:0] unnamedtuple7467USEDMULTIPLEtuple;assign unnamedtuple7467USEDMULTIPLEtuple = {(1'd1)};
wire [64:0] f2_load_output;
wire [16:0] pad_process_output;
wire [0:0] f1_store_output;
wire [16:0] f1_load_output;
wire [64:0] HH_process_output;
wire [64:0] crop_process_output;
wire [0:0] f2_store_output;
assign process_output = f2_load_output;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
LiftHandshake_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 #(.INSTANCE_NAME({INSTANCE_NAME,"_f1"})) f1(.CLK(CLK), .load_input(unnamedtuple7467USEDMULTIPLEtuple), .load_output(f1_load_output), .store_reset(reset), .store_ready_downstream((unnamedtuple7497USEDMULTIPLEtuple[1])), .store_ready(f1_store_ready), .load_ready_downstream(HH_ready), .load_ready(f1_load_ready), .load_reset(reset), .store_input(pad_process_output), .store_output(f1_store_output));
LiftHandshake_RunIffReady_LiftDecimate_fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 #(.INSTANCE_NAME({INSTANCE_NAME,"_f2"})) f2(.CLK(CLK), .load_input(unnamedtuple7467USEDMULTIPLEtuple), .load_output(f2_load_output), .store_reset(reset), .store_ready_downstream((unnamedtuple7497USEDMULTIPLEtuple[2])), .store_ready(f2_store_ready), .load_ready_downstream((unnamedtuple7497USEDMULTIPLEtuple[0])), .load_ready(f2_load_ready), .load_reset(reset), .store_input(crop_process_output), .store_output(f2_store_output));
LiftHandshake_WaitOnInput_PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22 #(.INSTANCE_NAME({INSTANCE_NAME,"_pad"})) pad(.CLK(CLK), .ready_downstream(f1_store_ready), .ready(pad_ready), .reset(reset), .process_input(process_input), .process_output(pad_process_output));
MakeHandshake_campipe #(.INSTANCE_NAME({INSTANCE_NAME,"_HH"})) HH(.CLK(CLK), .ready_downstream(crop_ready), .ready(HH_ready), .reset(reset), .process_input(f1_load_output), .process_output(HH_process_output));
LiftHandshake_LiftDecimate_cropHelperSeq_uint8_4_1__W648_H482_T2_L7_R1_B2_Top0 #(.INSTANCE_NAME({INSTANCE_NAME,"_crop"})) crop(.CLK(CLK), .ready_downstream(f2_store_ready), .ready(crop_ready), .reset(reset), .process_input(HH_process_output), .process_output(crop_process_output));
endmodule
module hsfn(input CLK, input ready_downstream, output ready, input reset, input [64:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire O1_ready;
wire idx_ready;
wire incrate_ready;
assign ready = incrate_ready;
wire [32:0] incrate_process_output;
wire [16:0] idx_process_output;
wire [64:0] O1_process_output;
assign process_output = O1_process_output;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
LiftHandshake_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_incrate"})) incrate(.CLK(CLK), .ready_downstream(idx_ready), .ready(incrate_ready), .reset(reset), .process_input(process_input), .process_output(incrate_process_output));
MakeHandshake_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1 #(.INSTANCE_NAME({INSTANCE_NAME,"_idx"})) idx(.CLK(CLK), .ready_downstream(O1_ready), .ready(idx_ready), .reset(reset), .process_input(incrate_process_output), .process_output(idx_process_output));
hsfn_uint8L3_R3_B1_T1_W640_H480function__0x05007498 #(.INSTANCE_NAME({INSTANCE_NAME,"_O1"})) O1(.CLK(CLK), .ready_downstream(ready_downstream), .ready(O1_ready), .reset(reset), .process_input(idx_process_output), .process_output(O1_process_output));
endmodule
module Overflow_307200(input CLK, input process_valid, input CE, input [63:0] process_input, output [64:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
reg [63:0] process_input_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin process_input_delay1_validunnamednull0_CECE <= process_input; end end
wire [31:0] cnt_GET_OUTPUT;
reg unnamedbinop8375_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedbinop8375_delay1_validunnamednull0_CECE <= {((cnt_GET_OUTPUT)<((32'd307200)))}; end end
wire [31:0] cnt_SETBY_OUTPUT;
assign process_output = {unnamedbinop8375_delay1_validunnamednull0_CECE,process_input_delay1_validunnamednull0_CECE};
// function: process pure=false delay=1
// function: reset pure=false delay=0
RegBy_incif_1uint32_CEtable__0x0759af78_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_cnt"})) cnt(.CLK(CLK), .set_valid(reset), .CE(CE), .set_inp((32'd0)), .setby_valid(process_valid), .setby_inp((1'd1)), .SETBY_OUTPUT(cnt_SETBY_OUTPUT), .GET_OUTPUT(cnt_GET_OUTPUT));
endmodule
module LiftDecimate_Overflow_307200(input CLK, output ready, input reset, input CE, input process_valid, input [64:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
assign ready = (1'd1);
wire unnamedcast8403USEDMULTIPLEcast;assign unnamedcast8403USEDMULTIPLEcast = (process_input[64]);
wire [64:0] LiftDecimate_process_output;
reg [63:0] unnamedcast8406_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast8406_delay1_validunnamednull0_CECE <= (LiftDecimate_process_output[63:0]); end end
reg unnamedcast8403_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedcast8403_delay1_validunnamednull0_CECE <= unnamedcast8403USEDMULTIPLEcast; end end
reg unnamedbinop8411_delay1_validunnamednull0_CECE; always @ (posedge CLK) begin if (CE) begin unnamedbinop8411_delay1_validunnamednull0_CECE <= {((LiftDecimate_process_output[64])&&unnamedcast8403_delay1_validunnamednull0_CECE)}; end end
assign process_output = {unnamedbinop8411_delay1_validunnamednull0_CECE,unnamedcast8406_delay1_validunnamednull0_CECE};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=2
Overflow_307200 #(.INSTANCE_NAME({INSTANCE_NAME,"_LiftDecimate"})) LiftDecimate(.CLK(CLK), .process_valid({(unnamedcast8403USEDMULTIPLEcast&&process_valid)}), .CE(CE), .process_input((process_input[63:0])), .process_output(LiftDecimate_process_output), .reset(reset));
endmodule
module ShiftRegister_2_CEtrue_TY1(input CLK, input pushPop_valid, input CE, input sr_input, output pushPop_out, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'pushPop'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
reg SR2;
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR1' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR1' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR1' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate8069USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate8069USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(sr_input):((1'd0)))};
reg SR1; always @ (posedge CLK) begin if ((unnamedcallArbitrate8069USEDMULTIPLEcallArbitrate[1]) && CE) begin SR1 <= (unnamedcallArbitrate8069USEDMULTIPLEcallArbitrate[0]); end end
always @(posedge CLK) begin if(pushPop_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR2' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'SR2' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,pushPop_valid})+({4'b0,reset})) > 5'd1) begin $display("error, function 'set' on instance 'SR2' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [1:0] unnamedcallArbitrate8075USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate8075USEDMULTIPLEcallArbitrate = {(pushPop_valid||reset),((pushPop_valid)?(SR1):((1'd0)))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate8075USEDMULTIPLEcallArbitrate[1]) && CE) begin SR2 <= (unnamedcallArbitrate8075USEDMULTIPLEcallArbitrate[0]); end end
assign pushPop_out = SR2;
// function: pushPop pure=false delay=0
// function: reset pure=false delay=0
endmodule
module LiftHandshake_LiftDecimate_Overflow_307200(input CLK, input ready_downstream, output ready, input reset, input [64:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire inner_LiftDecimate_Overflow_307200_ready;
assign ready = {(inner_LiftDecimate_Overflow_307200_ready&&ready_downstream)};
wire unnamedbinop8448USEDMULTIPLEbinop;assign unnamedbinop8448USEDMULTIPLEbinop = {(reset||ready_downstream)};
wire unnamedunary8449USEDMULTIPLEunary;assign unnamedunary8449USEDMULTIPLEunary = {(~reset)};
wire [64:0] inner_LiftDecimate_Overflow_307200_process_output;
wire validBitDelay_LiftDecimate_Overflow_307200_pushPop_out;
wire [64:0] unnamedtuple8459USEDMULTIPLEtuple;assign unnamedtuple8459USEDMULTIPLEtuple = {{((inner_LiftDecimate_Overflow_307200_process_output[64])&&validBitDelay_LiftDecimate_Overflow_307200_pushPop_out)},(inner_LiftDecimate_Overflow_307200_process_output[63:0])};
always @(posedge CLK) begin if({(~{((unnamedtuple8459USEDMULTIPLEtuple[64])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: output valid bit should not be X!",INSTANCE_NAME); end end
always @(posedge CLK) begin if({(~{((process_input[64])===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: LiftHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign process_output = unnamedtuple8459USEDMULTIPLEtuple;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
LiftDecimate_Overflow_307200 #(.INSTANCE_NAME({INSTANCE_NAME,"_inner_LiftDecimate_Overflow_307200"})) inner_LiftDecimate_Overflow_307200(.CLK(CLK), .ready(inner_LiftDecimate_Overflow_307200_ready), .reset(reset), .CE(unnamedbinop8448USEDMULTIPLEbinop), .process_valid(unnamedunary8449USEDMULTIPLEunary), .process_input(process_input), .process_output(inner_LiftDecimate_Overflow_307200_process_output));
ShiftRegister_2_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_validBitDelay_LiftDecimate_Overflow_307200"})) validBitDelay_LiftDecimate_Overflow_307200(.CLK(CLK), .pushPop_valid(unnamedunary8449USEDMULTIPLEunary), .CE(unnamedbinop8448USEDMULTIPLEbinop), .sr_input((1'd1)), .pushPop_out(validBitDelay_LiftDecimate_Overflow_307200_pushPop_out), .reset(reset));
endmodule
module Underflow_Auint8_4_1__2_1__count307200_cycles468504_toosoon156168_USfalse(input CLK, input ready_downstream, output ready, input reset, input [64:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
assign ready = ready_downstream;
wire unnamedbinop8485USEDMULTIPLEbinop;assign unnamedbinop8485USEDMULTIPLEbinop = {(ready_downstream||reset)};
wire [31:0] cycleCount_GET_OUTPUT;
wire unnamedbinop8484USEDMULTIPLEbinop;assign unnamedbinop8484USEDMULTIPLEbinop = {((cycleCount_GET_OUTPUT)>((32'd468504)))};
wire [31:0] outputCount_GET_OUTPUT;
wire [31:0] unnamedcast8498USEDMULTIPLEcast;assign unnamedcast8498USEDMULTIPLEcast = (32'd307200);
wire unnamedcast8478USEDMULTIPLEcast;assign unnamedcast8478USEDMULTIPLEcast = (process_input[64]);
wire unnamedunary8504USEDMULTIPLEunary;assign unnamedunary8504USEDMULTIPLEunary = {(~reset)};
wire unnamedbinop8514USEDMULTIPLEbinop;assign unnamedbinop8514USEDMULTIPLEbinop = {({(cycleCount_GET_OUTPUT==(32'd156168))}&&{((outputCount_GET_OUTPUT)>=(unnamedcast8498USEDMULTIPLEcast))})};
wire [31:0] outputCount_SETBY_OUTPUT;
wire [31:0] cycleCount_SETBY_OUTPUT;
always @(posedge CLK) begin if({(~unnamedbinop8514USEDMULTIPLEbinop)} == 1'b0 && unnamedunary8504USEDMULTIPLEunary==1'b1 && unnamedbinop8485USEDMULTIPLEbinop==1'b1) begin $display("%s: pipeline completed eariler than expected",INSTANCE_NAME); end end
assign process_output = {{({({({(unnamedbinop8484USEDMULTIPLEbinop&&{((outputCount_GET_OUTPUT)<(unnamedcast8498USEDMULTIPLEcast))})}||{({(~unnamedbinop8484USEDMULTIPLEbinop)}&&unnamedcast8478USEDMULTIPLEcast)})}&&unnamedunary8504USEDMULTIPLEunary)}||unnamedbinop8514USEDMULTIPLEbinop)},((unnamedbinop8484USEDMULTIPLEbinop)?((64'd3735928559)):((process_input[63:0])))};
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
RegBy_incif_1uint32_CEtable__0x0759af78_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_outputCount"})) outputCount(.CLK(CLK), .set_valid(reset), .CE(unnamedbinop8485USEDMULTIPLEbinop), .set_inp((32'd0)), .setby_valid(unnamedunary8504USEDMULTIPLEunary), .setby_inp({(ready_downstream&&{(unnamedcast8478USEDMULTIPLEcast||unnamedbinop8484USEDMULTIPLEbinop)})}), .SETBY_OUTPUT(outputCount_SETBY_OUTPUT), .GET_OUTPUT(outputCount_GET_OUTPUT));
RegBy_incif_1uint32_CEtable__0x0759af78_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_cycleCount"})) cycleCount(.CLK(CLK), .set_valid(reset), .CE(unnamedbinop8485USEDMULTIPLEbinop), .set_inp((32'd0)), .setby_valid(unnamedunary8504USEDMULTIPLEunary), .setby_inp((1'd1)), .SETBY_OUTPUT(cycleCount_SETBY_OUTPUT), .GET_OUTPUT(cycleCount_GET_OUTPUT));
endmodule
module incif_wrapuint32_153615_inc1(input CLK, input CE, input [32:0] process_input, output [31:0] process_output);
parameter INSTANCE_NAME="INST";
wire [31:0] unnamedcast8525USEDMULTIPLEcast;assign unnamedcast8525USEDMULTIPLEcast = (process_input[31:0]);
assign process_output = (((process_input[32]))?((({(unnamedcast8525USEDMULTIPLEcast==(32'd153615))})?((32'd0)):({(unnamedcast8525USEDMULTIPLEcast+(32'd1))}))):(unnamedcast8525USEDMULTIPLEcast));
// function: process pure=true delay=0
endmodule
module RegBy_incif_wrapuint32_153615_inc1_CEtrue_initnil(input CLK, input set_valid, input CE, input [31:0] set_inp, input setby_valid, input setby_inp, output [31:0] SETBY_OUTPUT, output [31:0] GET_OUTPUT);
parameter INSTANCE_NAME="INST";
reg [31:0] R;
wire [31:0] regby_inner_process_output;
always @(posedge CLK) begin if(set_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(setby_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,set_valid})+({4'b0,setby_valid})) > 5'd1) begin $display("error, function 'set' on instance 'R' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [32:0] unnamedcallArbitrate8576USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate8576USEDMULTIPLEcallArbitrate = {(set_valid||setby_valid),((set_valid)?(set_inp):(regby_inner_process_output))};
always @ (posedge CLK) begin if ((unnamedcallArbitrate8576USEDMULTIPLEcallArbitrate[32]) && CE) begin R <= (unnamedcallArbitrate8576USEDMULTIPLEcallArbitrate[31:0]); end end
assign SETBY_OUTPUT = regby_inner_process_output;
assign GET_OUTPUT = R;
// function: set pure=false ONLY WIRE
// function: setby pure=false ONLY WIRE
// function: get pure=true ONLY WIRE
incif_wrapuint32_153615_inc1 #(.INSTANCE_NAME({INSTANCE_NAME,"_regby_inner"})) regby_inner(.CLK(CLK), .CE(CE), .process_input({setby_inp,R}), .process_output(regby_inner_process_output));
endmodule
module incif_1uint32_CEnil(input CLK, input [32:0] process_input, output [31:0] process_output);
parameter INSTANCE_NAME="INST";
wire [31:0] unnamedcast8585USEDMULTIPLEcast;assign unnamedcast8585USEDMULTIPLEcast = (process_input[31:0]);
assign process_output = (((process_input[32]))?({(unnamedcast8585USEDMULTIPLEcast+(32'd1))}):(unnamedcast8585USEDMULTIPLEcast));
// function: process pure=true delay=0
endmodule
module RegBy_incif_1uint32_CEnil_CEfalse_initnil(input CLK, input set_valid, input [31:0] set_inp, input setby_valid, input setby_inp, output [31:0] SETBY_OUTPUT, output [31:0] GET_OUTPUT);
parameter INSTANCE_NAME="INST";
reg [31:0] R;
wire [31:0] regby_inner_process_output;
always @(posedge CLK) begin if(set_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(setby_valid===1'bx) begin $display("valid bit can't be x! Module '%s' instance 'R' function 'set'", INSTANCE_NAME); end end
always @(posedge CLK) begin if((({4'b0,set_valid})+({4'b0,setby_valid})) > 5'd1) begin $display("error, function 'set' on instance 'R' in module '%s' has multiple valid bits active in same cycle!",INSTANCE_NAME);$finish(); end end
wire [32:0] unnamedcallArbitrate8617USEDMULTIPLEcallArbitrate;assign unnamedcallArbitrate8617USEDMULTIPLEcallArbitrate = {(set_valid||setby_valid),((set_valid)?(set_inp):(regby_inner_process_output))};
always @ (posedge CLK) begin R <= (unnamedcallArbitrate8617USEDMULTIPLEcallArbitrate[31:0]); end
assign SETBY_OUTPUT = regby_inner_process_output;
assign GET_OUTPUT = R;
// function: set pure=false ONLY WIRE
// function: setby pure=false ONLY WIRE
// function: get pure=true ONLY WIRE
incif_1uint32_CEnil #(.INSTANCE_NAME({INSTANCE_NAME,"_regby_inner"})) regby_inner(.CLK(CLK), .process_input({setby_inp,R}), .process_output(regby_inner_process_output));
endmodule
module CycleCounter_Auint8_4_1__2_1__count153600(input CLK, input ready_downstream, output ready, input reset, input [64:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire [31:0] outputCount_GET_OUTPUT;
wire unnamedbinop8630USEDMULTIPLEbinop;assign unnamedbinop8630USEDMULTIPLEbinop = {((outputCount_GET_OUTPUT)>=((32'd153600)))};
wire unnamedunary8653USEDMULTIPLEunary;assign unnamedunary8653USEDMULTIPLEunary = {(~unnamedbinop8630USEDMULTIPLEbinop)};
assign ready = {(ready_downstream&&unnamedunary8653USEDMULTIPLEunary)};
wire unnamedbinop8631USEDMULTIPLEbinop;assign unnamedbinop8631USEDMULTIPLEbinop = {(ready_downstream||reset)};
wire [31:0] cycleCount_GET_OUTPUT;
wire unnamedcast8624USEDMULTIPLEcast;assign unnamedcast8624USEDMULTIPLEcast = (process_input[64]);
wire unnamedunary8646USEDMULTIPLEunary;assign unnamedunary8646USEDMULTIPLEunary = {(~reset)};
wire [31:0] outputCount_SETBY_OUTPUT;
wire [31:0] cycleCount_SETBY_OUTPUT;
assign process_output = {{({(unnamedbinop8630USEDMULTIPLEbinop||unnamedcast8624USEDMULTIPLEcast)}&&unnamedunary8646USEDMULTIPLEunary)},((unnamedbinop8630USEDMULTIPLEbinop)?({cycleCount_GET_OUTPUT,cycleCount_GET_OUTPUT}):((process_input[63:0])))};
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
RegBy_incif_wrapuint32_153615_inc1_CEtrue_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_outputCount"})) outputCount(.CLK(CLK), .set_valid(reset), .CE(unnamedbinop8631USEDMULTIPLEbinop), .set_inp((32'd0)), .setby_valid(unnamedunary8646USEDMULTIPLEunary), .setby_inp({(ready_downstream&&{(unnamedcast8624USEDMULTIPLEcast||unnamedbinop8630USEDMULTIPLEbinop)})}), .SETBY_OUTPUT(outputCount_SETBY_OUTPUT), .GET_OUTPUT(outputCount_GET_OUTPUT));
RegBy_incif_1uint32_CEnil_CEfalse_initnil #(.INSTANCE_NAME({INSTANCE_NAME,"_cycleCount"})) cycleCount(.CLK(CLK), .set_valid(reset), .set_inp((32'd0)), .setby_valid(unnamedunary8646USEDMULTIPLEunary), .setby_inp(unnamedunary8653USEDMULTIPLEunary), .SETBY_OUTPUT(cycleCount_SETBY_OUTPUT), .GET_OUTPUT(cycleCount_GET_OUTPUT));
endmodule
module fwriteSeq_campipe_ov7660_half_sim_raw(input CLK, input process_valid, input CE, input [63:0] process_input, output [63:0] process_output, input reset);
parameter INSTANCE_NAME="INST";
always @(posedge CLK) begin if(process_valid===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME); end end
always @(posedge CLK) begin if(reset===1'bx) begin $display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME); end end
assign process_output = process_input;
// function: process pure=false delay=0
// function: reset pure=false delay=0
integer fwritefile_file,r;
initial begin fwritefile_file = $fopen("campipe_ov7660_half.sim.raw","wb"); end
always @ (posedge CLK) begin
if (process_valid && CE) begin $fwrite(fwritefile_file, "%c", process_input[7:0] ); $fwrite(fwritefile_file, "%c", process_input[15:8] ); $fwrite(fwritefile_file, "%c", process_input[23:16] ); $fwrite(fwritefile_file, "%c", process_input[31:24] ); $fwrite(fwritefile_file, "%c", process_input[39:32] ); $fwrite(fwritefile_file, "%c", process_input[47:40] ); $fwrite(fwritefile_file, "%c", process_input[55:48] ); $fwrite(fwritefile_file, "%c", process_input[63:56] ); end
if (reset) begin r=$fseek(fwritefile_file,0,0); end end
endmodule
module MakeHandshake_fwriteSeq_campipe_ov7660_half_sim_raw(input CLK, input ready_downstream, output ready, input reset, input [64:0] process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
assign ready = ready_downstream;
wire unnamedbinop8757USEDMULTIPLEbinop;assign unnamedbinop8757USEDMULTIPLEbinop = {(ready_downstream||reset)};
wire unnamedcast8765USEDMULTIPLEcast;assign unnamedcast8765USEDMULTIPLEcast = (process_input[64]);
wire [63:0] inner_process_output;
wire validBitDelay_fwriteSeq_campipe_ov7660_half_sim_raw_pushPop_out;
always @(posedge CLK) begin if({(~{(unnamedcast8765USEDMULTIPLEcast===1'bx)})} == 1'b0 && (1'd1)==1'b1) begin $display("%s: MakeHandshake: input valid bit should not be X!",INSTANCE_NAME); end end
assign process_output = {validBitDelay_fwriteSeq_campipe_ov7660_half_sim_raw_pushPop_out,inner_process_output};
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
ShiftRegister_0_CEtrue_TY1 #(.INSTANCE_NAME({INSTANCE_NAME,"_validBitDelay_fwriteSeq_campipe_ov7660_half_sim_raw"})) validBitDelay_fwriteSeq_campipe_ov7660_half_sim_raw(.CLK(CLK), .CE(unnamedbinop8757USEDMULTIPLEbinop), .sr_input(unnamedcast8765USEDMULTIPLEcast), .pushPop_out(validBitDelay_fwriteSeq_campipe_ov7660_half_sim_raw_pushPop_out));
fwriteSeq_campipe_ov7660_half_sim_raw #(.INSTANCE_NAME({INSTANCE_NAME,"_inner"})) inner(.CLK(CLK), .process_valid(unnamedcast8765USEDMULTIPLEcast), .CE(unnamedbinop8757USEDMULTIPLEbinop), .process_input((process_input[63:0])), .process_output(inner_process_output), .reset(reset));
endmodule
module harness4(input CLK, input ready_downstream, output ready, input reset, input process_input, output [64:0] process_output);
parameter INSTANCE_NAME="INST";
parameter OUTPUT_COUNT=0;
parameter INPUT_COUNT=0;
wire fwrite_ready;
wire cycleCounter_ready;
wire underflow_ready;
wire overflow_ready;
wire HARNESS_inner_ready;
wire fread_ready;
wire inpdata_ready;
wire underflow_US_ready;
assign ready = underflow_US_ready;
wire [0:0] underflow_US_process_output;
wire [0:0] inpdata_process_output;
wire [64:0] fread_process_output;
wire [64:0] HARNESS_inner_process_output;
wire [64:0] overflow_process_output;
wire [64:0] underflow_process_output;
wire [64:0] cycleCounter_process_output;
wire [64:0] fwrite_process_output;
assign process_output = fwrite_process_output;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
Underflow_A_null_null__count153600_cycles1874016_toosoon156168_UStrue #(.INSTANCE_NAME({INSTANCE_NAME,"_underflow_US"})) underflow_US(.CLK(CLK), .ready_downstream(inpdata_ready), .ready(underflow_US_ready), .reset(reset), .process_input(process_input), .process_output(underflow_US_process_output));
MakeHandshake_index__null_null__0 #(.INSTANCE_NAME({INSTANCE_NAME,"_inpdata"})) inpdata(.CLK(CLK), .ready_downstream(fread_ready), .ready(inpdata_ready), .reset(reset), .process_input(underflow_US_process_output), .process_output(inpdata_process_output));
MakeHandshake_freadSeq____ov7660_raw_dup #(.INSTANCE_NAME({INSTANCE_NAME,"_fread"})) fread(.CLK(CLK), .ready_downstream(HARNESS_inner_ready), .ready(fread_ready), .reset(reset), .process_input(inpdata_process_output), .process_output(fread_process_output));
hsfn #(.INSTANCE_NAME({INSTANCE_NAME,"_HARNESS_inner"})) HARNESS_inner(.CLK(CLK), .ready_downstream(overflow_ready), .ready(HARNESS_inner_ready), .reset(reset), .process_input(fread_process_output), .process_output(HARNESS_inner_process_output));
LiftHandshake_LiftDecimate_Overflow_307200 #(.INSTANCE_NAME({INSTANCE_NAME,"_overflow"})) overflow(.CLK(CLK), .ready_downstream(underflow_ready), .ready(overflow_ready), .reset(reset), .process_input(HARNESS_inner_process_output), .process_output(overflow_process_output));
Underflow_Auint8_4_1__2_1__count307200_cycles468504_toosoon156168_USfalse #(.INSTANCE_NAME({INSTANCE_NAME,"_underflow"})) underflow(.CLK(CLK), .ready_downstream(cycleCounter_ready), .ready(underflow_ready), .reset(reset), .process_input(overflow_process_output), .process_output(underflow_process_output));
CycleCounter_Auint8_4_1__2_1__count153600 #(.INSTANCE_NAME({INSTANCE_NAME,"_cycleCounter"})) cycleCounter(.CLK(CLK), .ready_downstream(fwrite_ready), .ready(cycleCounter_ready), .reset(reset), .process_input(underflow_process_output), .process_output(cycleCounter_process_output));
MakeHandshake_fwriteSeq_campipe_ov7660_half_sim_raw #(.INSTANCE_NAME({INSTANCE_NAME,"_fwrite"})) fwrite(.CLK(CLK), .ready_downstream(ready_downstream), .ready(fwrite_ready), .reset(reset), .process_input(cycleCounter_process_output), .process_output(fwrite_process_output));
endmodule
module sim();
reg CLK = 0;
integer i = 0;
reg RST = 1;
wire valid;
reg [1:0] ready_downstream = 1;
reg [15:0] doneCnt = 0;
wire ready;
reg [31:0] totalClocks = 0;
wire [64:0] process_output;
harness4 #(.INPUT_COUNT(153600),.OUTPUT_COUNT(307232)) inst (.CLK(CLK),.process_input(valid),.reset(RST),.ready(ready),.ready_downstream(ready_downstream==1),.process_output(process_output));
initial begin
// clock in reset bit
while(i<100) begin CLK = 0; #10; CLK = 1; #10; i = i + 1; end
RST = 0;
//valid = 1;
totalClocks = 0;
while(1) begin CLK = 0; #10; CLK = 1; #10; end
end
reg [31:0] validInCnt = 0; // we should only drive W*H valid bits in
reg [31:0] validCnt = 0;
assign valid = (RST==0 && validInCnt < 153600);
always @(posedge CLK) begin
// we can't send more than W*H valid bits, or the AXI bus will lock up. Once we have W*H valid bits,
// keep simulating for N cycles to make sure we don't send any more
if(validCnt> 307232 ) begin $display("Too many valid bits!"); end // I think we have this _NOT_ finish so that it outputs an invalid file
if(validCnt>= 307232 && doneCnt==1024 ) begin $finish(); end
if(validCnt>= 307232 && ready_downstream==1) begin doneCnt <= doneCnt+1; end
if(RST==0 && ready) begin validInCnt <= validInCnt + 1; end
// ignore the output when we're in reset mode - output is probably bogus
if(ready_downstream==1 && process_output[64] && RST==1'b0) begin validCnt = validCnt + 1; end
ready_downstream <= ready_downstream + 1;
totalClocks <= totalClocks + 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_BLACKBOX_V
`define SKY130_FD_SC_LP__A2111OI_BLACKBOX_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:48 04/28/2015
// Design Name:
// Module Name: BlackInner
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BlackInner(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
always @(posedge clk_vga) begin
if(((CurrentY < 40) && (CurrentX < 260)) || ((CurrentY < 40) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
end
else if(CurrentX < 40) begin
mColor[7:0] <= wall;
end
else if(~(CurrentX < 600)) begin
mColor[7:0] <= wall;
end
else if((~(CurrentY < 440) && (CurrentX < 260)) || (~(CurrentY < 440) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
end else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_register_slice_v2_1_7_axi_register_slice,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_m01_regslice_0,axi_register_slice_v2_1_7_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "zc702_m01_regslice_0,axi_register_slice_v2_1_7_axi_register_slice,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=13,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=7,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=7}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_m01_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [12 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [12 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [12 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [12 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_7_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(13),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_phy(
input usb_clk,
input usb_rst,
output usba_spd,
output usba_oe_n,
input usba_rcv,
inout usba_vp,
inout usba_vm,
output usbb_spd,
output usbb_oe_n,
input usbb_rcv,
inout usbb_vp,
inout usbb_vm,
output usba_discon,
output usbb_discon,
output [1:0] line_state_a,
output [1:0] line_state_b,
input port_sel_rx,
input [1:0] port_sel_tx,
input [7:0] tx_data,
input tx_valid,
output tx_ready, /* data acknowledgment */
output tx_busy, /* busy generating EOP, sending data, etc. */
input [1:0] generate_reset,
output [7:0] rx_data,
output rx_valid,
output rx_active,
input tx_low_speed,
input [1:0] low_speed,
input generate_eop
);
/* RX synchronizer */
wire vp_s_a;
wire vm_s_a;
wire rcv_s_a;
softusb_filter filter_a(
.usb_clk(usb_clk),
.rcv(usba_rcv),
.vp(usba_vp),
.vm(usba_vm),
.rcv_s(rcv_s_a),
.vp_s(vp_s_a),
.vm_s(vm_s_a)
);
assign line_state_a = {vm_s_a, vp_s_a};
wire vp_s_b;
wire vm_s_b;
wire rcv_s_b;
softusb_filter filter_b(
.usb_clk(usb_clk),
.rcv(usbb_rcv),
.vp(usbb_vp),
.vm(usbb_vm),
.rcv_s(rcv_s_b),
.vp_s(vp_s_b),
.vm_s(vm_s_b)
);
assign line_state_b = {vm_s_b, vp_s_b};
/* TX section */
wire txp;
wire txm;
wire txoe;
softusb_tx tx(
.usb_clk(usb_clk),
.usb_rst(usb_rst),
.tx_data(tx_data),
.tx_valid(tx_valid),
.tx_ready(tx_ready),
.txp(txp),
.txm(txm),
.txoe(txoe),
.low_speed(tx_low_speed),
.generate_eop(generate_eop)
);
assign tx_busy = txoe;
/* RX section */
reg txoe0;
reg txoe1;
always @(posedge usb_clk) begin
txoe0 <= txoe;
txoe1 <= txoe0;
end
softusb_rx rx(
.usb_clk(usb_clk),
.rxreset(txoe1),
.rx(port_sel_rx ? rcv_s_b : rcv_s_a),
.rxp(port_sel_rx ? vp_s_b : vp_s_a),
.rxm(port_sel_rx ? vm_s_b : vm_s_a),
.rx_data(rx_data),
.rx_valid(rx_valid),
.rx_active(rx_active),
.low_speed(port_sel_rx ? low_speed[1] : low_speed[0])
);
/* Tri-state enables and drivers */
wire txoe_a = (txoe & port_sel_tx[0])|generate_reset[0];
wire txoe_b = (txoe & port_sel_tx[1])|generate_reset[1];
assign usba_oe_n = ~txoe_a;
assign usba_vp = txoe_a ? (generate_reset[0] ? 1'b0 : txp) : 1'bz;
assign usba_vm = txoe_a ? (generate_reset[0] ? 1'b0 : txm) : 1'bz;
assign usbb_oe_n = ~txoe_b;
assign usbb_vp = txoe_b ? (generate_reset[1] ? 1'b0 : txp) : 1'bz;
assign usbb_vm = txoe_b ? (generate_reset[1] ? 1'b0 : txm) : 1'bz;
/* Assert USB disconnect if we see SE0 for at least 2.5us */
reg [6:0] usba_discon_cnt;
assign usba_discon = (usba_discon_cnt == 7'd127);
always @(posedge usb_clk) begin
if(usb_rst)
usba_discon_cnt <= 7'd0;
else begin
if(line_state_a != 7'd0)
usba_discon_cnt <= 7'd0;
else if(~usba_discon)
usba_discon_cnt <= usba_discon_cnt + 7'd1;
end
end
reg [6:0] usbb_discon_cnt;
assign usbb_discon = (usbb_discon_cnt == 7'd127);
always @(posedge usb_clk) begin
if(usb_rst)
usbb_discon_cnt <= 7'd0;
else begin
if(line_state_b != 2'h0)
usbb_discon_cnt <= 7'd0;
else if(~usbb_discon)
usbb_discon_cnt <= usbb_discon_cnt + 7'd1;
end
end
assign usba_spd = ~low_speed[0];
assign usbb_spd = ~low_speed[1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__OR4_PP_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4_PP_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sp_mux_6to1_sel3_7_1 #(
parameter
ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
dout_WIDTH = 32
)(
input [6 : 0] din1,
input [6 : 0] din2,
input [6 : 0] din3,
input [6 : 0] din4,
input [6 : 0] din5,
input [6 : 0] din6,
input [2 : 0] din7,
output [6 : 0] dout);
// puts internal signals
wire [2 : 0] sel;
// level 1 signals
wire [6 : 0] mux_1_0;
wire [6 : 0] mux_1_1;
wire [6 : 0] mux_1_2;
// level 2 signals
wire [6 : 0] mux_2_0;
wire [6 : 0] mux_2_1;
// level 3 signals
wire [6 : 0] mux_3_0;
assign sel = din7;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din1 : din2;
assign mux_1_1 = (sel[0] == 0)? din3 : din4;
assign mux_1_2 = (sel[0] == 0)? din5 : din6;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
assign mux_2_1 = mux_1_2;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1;
// output logic
assign dout = mux_3_0;
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module ripple_adder(a,b,c_in, sum, cout);
input [7:0] a,b;
input c_in;
output [7:0] sum;
output cout;
wire [7:0] c;
fulladder f0(a[0], b[0], c_in, sum[0], c[1]);
fulladder f1(a[1], b[1], c[1], sum[1], c[2]);
fulladder f2(a[2], b[2], c[2], sum[2], c[3]);
fulladder f3(a[3], b[3], c[3], sum[3], c[4]);
fulladder f4(a[4], b[4], c[4], sum[4], c[5]);
fulladder f5(a[5], b[5], c[5], sum[5], c[6]);
fulladder f6(a[6], b[6], c[6], sum[6], c[7]);
fulladder f7(a[7], b[7], c[7], sum[7], cout);
endmodule
|
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2011
//
// integrates sound features: tapeout, beeper and covox
module sound(
input wire clk,
input wire [7:0] din,
input wire beeper_wr,
input wire covox_wr,
input wire beeper_mux, // output either tape_out or beeper
output wire sound_bit
);
reg [6:0] ctr;
reg [7:0] val;
reg mx_beep_n_covox;
reg beep_bit;
reg beep_bit_old;
wire covox_bit;
always @(posedge clk)
begin
/* if( beeper_wr ) */
if( beeper_wr && (beep_bit!=beep_bit_old) )
mx_beep_n_covox <= 1'b1;
else if( covox_wr )
mx_beep_n_covox <= 1'b0;
end
always @(posedge clk) if( beeper_wr ) beep_bit_old <= beep_bit;
always @(posedge clk)
if( beeper_wr )
beep_bit <= beeper_mux ? din[3] /*tapeout*/ : din[4] /*beeper*/;
always @(posedge clk)
if( covox_wr )
val <= din;
always @(negedge clk)
ctr <= ctr + 6'd1;
assign covox_bit = ( {ctr,clk} < val );
bothedge trigger
(
.clk( clk ),
.d( mx_beep_n_covox ? beep_bit : covox_bit ),
.q( sound_bit )
);
endmodule
// both-edge trigger emulator
module bothedge(
input wire clk,
input wire d,
output wire q
);
reg trgp, trgn;
assign q = trgp ^ trgn;
always @(posedge clk)
if( d!=q )
trgp <= ~trgp;
always @(negedge clk)
if( d!=q )
trgn <= ~trgn;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97_ctlif #(
parameter csr_addr = 4'h0
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output reg crrequest_irq,
output reg crreply_irq,
output reg dmar_irq,
output reg dmaw_irq,
input down_en,
input down_next_frame,
output reg down_addr_valid,
output reg [19:0] down_addr,
output reg down_data_valid,
output reg [19:0] down_data,
input up_en,
input up_next_frame,
input up_frame_valid,
input up_addr_valid,
input [19:0] up_addr,
input up_data_valid,
input [19:0] up_data,
output reg dmar_en,
output reg [29:0] dmar_addr,
output reg [15:0] dmar_remaining,
input dmar_next,
output reg dmaw_en,
output reg [29:0] dmaw_addr,
output reg [15:0] dmaw_remaining,
input dmaw_next
);
wire dmar_finished = dmar_remaining == 16'd0;
reg dmar_finished_r;
always @(posedge sys_clk) begin
if(sys_rst)
dmar_finished_r <= 1'b1;
else
dmar_finished_r <= dmar_finished;
end
wire dmaw_finished = dmaw_remaining == 16'd0;
reg dmaw_finished_r;
always @(posedge sys_clk) begin
if(sys_rst)
dmaw_finished_r <= 1'b1;
else
dmaw_finished_r <= dmaw_finished;
end
wire csr_selected = csr_a[13:10] == csr_addr;
reg request_en;
reg request_write;
reg [6:0] request_addr;
reg [15:0] request_data;
reg [15:0] reply_data;
always @(posedge sys_clk) begin
if(sys_rst) begin
csr_do <= 32'd0;
request_en <= 1'b0;
request_write <= 1'b0;
request_addr <= 7'd0;
request_data <= 16'd0;
down_addr_valid <= 1'b0;
down_data_valid <= 1'b0;
dmar_en <= 1'b0;
dmar_addr <= 30'd0;
dmar_remaining <= 16'd0;
dmaw_en <= 1'b0;
dmaw_addr <= 30'd0;
dmaw_remaining <= 16'd0;
crrequest_irq <= 1'b0;
crreply_irq <= 1'b0;
dmar_irq <= 1'b0;
dmaw_irq <= 1'b0;
end else begin
crrequest_irq <= 1'b0;
crreply_irq <= 1'b0;
dmar_irq <= 1'b0;
dmaw_irq <= 1'b0;
if(down_en & down_next_frame) begin
down_addr_valid <= request_en;
down_addr <= {~request_write, request_addr, 12'd0};
down_data_valid <= request_en & request_write;
down_data <= {request_data, 4'd0};
request_en <= 1'b0;
if(request_en)
crrequest_irq <= 1'b1;
end
if(up_en & up_next_frame) begin
if(up_frame_valid & up_addr_valid & up_data_valid) begin
crreply_irq <= 1'b1;
reply_data <= up_data[19:4];
end
end
if(dmar_next) begin
dmar_addr <= dmar_addr + 30'd1;
dmar_remaining <= dmar_remaining - 16'd1;
end
if(dmaw_next) begin
dmaw_addr <= dmaw_addr + 30'd1;
dmaw_remaining <= dmaw_remaining - 16'd1;
end
if(dmar_finished & ~dmar_finished_r)
dmar_irq <= 1'b1;
if(dmaw_finished & ~dmaw_finished_r)
dmaw_irq <= 1'b1;
csr_do <= 32'd0;
if(csr_selected) begin
if(csr_we) begin
case(csr_a[3:0])
/* Codec register access */
4'b0000: begin
request_en <= csr_di[0];
request_write <= csr_di[1];
end
4'b0001: request_addr <= csr_di[6:0];
4'b0010: request_data <= csr_di[15:0];
// Reply Data is read-only
/* Downstream */
4'b0100: dmar_en <= csr_di[0];
4'b0101: dmar_addr <= csr_di[31:2];
4'b0110: dmar_remaining <= csr_di[17:2];
/* Upstream */
4'b1000: dmaw_en <= csr_di[0];
4'b1001: dmaw_addr <= csr_di[31:2];
4'b1010: dmaw_remaining <= csr_di[17:2];
endcase
end
case(csr_a[3:0])
/* Codec register access */
4'b0000: csr_do <= {request_write, request_en};
4'b0001: csr_do <= request_addr;
4'b0010: csr_do <= request_data;
4'b0011: csr_do <= reply_data;
/* Downstream */
4'b0100: csr_do <= dmar_en;
4'b0101: csr_do <= {dmar_addr, 2'b00};
4'b0110: csr_do <= {dmar_remaining, 2'b00};
/* Upstream */
4'b1000: csr_do <= dmaw_en;
4'b1001: csr_do <= {dmaw_addr, 2'b00};
4'b1010: csr_do <= {dmaw_remaining, 2'b00};
endcase
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_BEHAVIORAL_PP_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_BEHAVIORAL_PP_V |
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_int_phy_alt_mem_phy_seq_wrapper (
// dss ports
phy_clk_1x,
reset_phy_clk_1x_n,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
ctl_cal_req,
int_RANK_HAS_ADDR_SWAP,
ctl_cal_byte_lane_sel_n,
seq_pll_inc_dec_n,
seq_pll_start_reconfig,
seq_pll_select,
phs_shft_busy,
pll_resync_clk_index,
pll_measure_clk_index,
sc_clk_dp,
scan_enable_dqs_config,
scan_update,
scan_din,
scan_enable_ck,
scan_enable_dqs,
scan_enable_dqsn,
scan_enable_dq,
scan_enable_dm,
hr_rsc_clk,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n,
seq_ac_sel,
seq_mem_clk_disable,
ctl_add_1t_ac_lat_internal,
ctl_add_1t_odt_lat_internal,
ctl_add_intermediate_regs_internal,
seq_rdv_doing_rd,
seq_rdp_reset_req_n,
seq_rdp_inc_read_lat_1x,
seq_rdp_dec_read_lat_1x,
ctl_rdata,
int_rdata_valid_1t,
seq_rdata_valid_lat_inc,
seq_rdata_valid_lat_dec,
ctl_rlat,
seq_poa_lat_dec_1x,
seq_poa_lat_inc_1x,
seq_poa_protection_override_1x,
seq_oct_oct_delay,
seq_oct_oct_extend,
seq_oct_val,
seq_wdp_dqs_burst,
seq_wdp_wdata_valid,
seq_wdp_wdata,
seq_wdp_dm,
seq_wdp_dqs,
seq_wdp_ovride,
seq_dqs_add_2t_delay,
ctl_wlat,
seq_mmc_start,
mmc_seq_done,
mmc_seq_value,
mem_err_out_n,
parity_error_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
//Inserted Generics
localparam SPEED_GRADE = "C3";
localparam MEM_IF_DQS_WIDTH = 8;
localparam MEM_IF_DWIDTH = 64;
localparam MEM_IF_DM_WIDTH = 8;
localparam MEM_IF_DQ_PER_DQS = 8;
localparam DWIDTH_RATIO = 4;
localparam CLOCK_INDEX_WIDTH = 3;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_ADDR_WIDTH = 13;
localparam MEM_IF_BANKADDR_WIDTH = 3;
localparam MEM_IF_CS_WIDTH = 1;
localparam RESYNCHRONISE_AVALON_DBG = 0;
localparam DBG_A_WIDTH = 13;
localparam DQS_PHASE_SETTING = 2;
localparam SCAN_CLK_DIVIDE_BY = 2;
localparam PLL_STEPS_PER_CYCLE = 32;
localparam MEM_IF_CLK_PS = 3003;
localparam DQS_DELAY_CTL_WIDTH = 6;
localparam MEM_IF_MEMTYPE = "DDR3";
localparam RANK_HAS_ADDR_SWAP = 0;
localparam MEM_IF_MR_0 = 4641;
localparam MEM_IF_MR_1 = 70;
localparam MEM_IF_MR_2 = 8;
localparam MEM_IF_MR_3 = 0;
localparam MEM_IF_OCT_EN = 0;
localparam IP_BUILDNUM = 0;
localparam FAMILY = "Arria II GX";
localparam FAMILYGROUP_ID = 4;
localparam MEM_IF_ADDR_CMD_PHASE = 90;
localparam CAPABILITIES = 0;
localparam WRITE_DESKEW_T10 = 6;
localparam WRITE_DESKEW_HC_T10 = 6;
localparam WRITE_DESKEW_T9NI = 6;
localparam WRITE_DESKEW_HC_T9NI = 6;
localparam WRITE_DESKEW_T9I = 0;
localparam WRITE_DESKEW_HC_T9I = 0;
localparam WRITE_DESKEW_RANGE = 0;
localparam IOE_PHASES_PER_TCK = 10;
localparam ADV_LAT_WIDTH = 5;
localparam RDP_ADDR_WIDTH = 4;
localparam IOE_DELAYS_PER_PHS = 5;
localparam SINGLE_DQS_DELAY_CONTROL_CODE = 0;
localparam PRESET_RLAT = 0;
localparam FORCE_HC = 0;
localparam MEM_IF_DQS_CAPTURE_EN = 1;
localparam REDUCE_SIM_TIME = 0;
localparam TINIT_TCK = 83223;
localparam TINIT_RST = 33289;
localparam GENERATE_ADDITIONAL_DBG_RTL = 0;
localparam MEM_IF_CS_PER_RANK = 1;
localparam MEM_IF_RANKS_PER_SLOT = 1;
localparam CHIP_OR_DIMM = "Discrete Device";
localparam RDIMM_CONFIG_BITS = "0000000000000000000000000000000000000000000000000000000000000000";
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
localparam GENERATE_TRACKING_PHASE_STORE = 0;
// note that num_ranks if the number of discrete chip select signals output from the sequencer
// cs_width is the total number of chip selects which go from the phy to the memory (there can
// be more than one chip select per rank).
localparam MEM_IF_NUM_RANKS = MEM_IF_CS_WIDTH/MEM_IF_CS_PER_RANK;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
input wire ctl_cal_req;
input wire [MEM_IF_NUM_RANKS - 1 : 0] int_RANK_HAS_ADDR_SWAP;
input wire [MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
output wire seq_pll_inc_dec_n;
output wire seq_pll_start_reconfig;
output wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
input wire phs_shft_busy;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
output [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs_config;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_update;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_din;
output wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqsn;
output wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
output wire [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
input wire hr_rsc_clk;
output wire [(DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 : 0] seq_ac_addr;
output wire [(DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 : 0] seq_ac_ba;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_cas_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_ras_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_we_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_cke;
output wire [(DWIDTH_RATIO/2) * MEM_IF_CS_WIDTH - 1 : 0] seq_ac_cs_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_odt;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_rst_n;
output wire seq_ac_sel;
output wire seq_mem_clk_disable;
output wire ctl_add_1t_ac_lat_internal;
output wire ctl_add_1t_odt_lat_internal;
output wire ctl_add_intermediate_regs_internal;
output wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_rdv_doing_rd;
output wire seq_rdp_reset_req_n;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_inc_read_lat_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_dec_read_lat_1x;
input wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] ctl_rdata;
input wire [DWIDTH_RATIO/2 - 1 : 0] int_rdata_valid_1t;
output wire seq_rdata_valid_lat_inc;
output wire seq_rdata_valid_lat_dec;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_rlat;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_dec_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_inc_1x;
output wire seq_poa_protection_override_1x;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend;
output wire seq_oct_val;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_dqs_burst;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_wdata_valid;
output wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] seq_wdp_wdata;
output wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0] seq_wdp_dm;
output wire [DWIDTH_RATIO - 1 : 0] seq_wdp_dqs;
output wire seq_wdp_ovride;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_dqs_add_2t_delay;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_wlat;
output wire seq_mmc_start;
input wire mmc_seq_done;
input wire mmc_seq_value;
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH - 1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [ 31 : 0] dbg_wr_data;
output wire [ 31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
input wire mem_err_out_n;
output wire parity_error_n;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// instantiate the deskew (DDR3) or non-deskew (DDR/DDR2/DDR3) sequencer:
//
ddr3_int_phy_alt_mem_phy_seq #(
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.DWIDTH_RATIO (DWIDTH_RATIO),
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_ADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
.MEM_IF_RANKS_PER_SLOT (MEM_IF_RANKS_PER_SLOT),
.ADV_LAT_WIDTH (ADV_LAT_WIDTH),
.RESYNCHRONISE_AVALON_DBG (RESYNCHRONISE_AVALON_DBG),
.AV_IF_ADDR_WIDTH (DBG_A_WIDTH),
.NOM_DQS_PHASE_SETTING (DQS_PHASE_SETTING),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.RDP_ADDR_WIDTH (RDP_ADDR_WIDTH),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE),
.IOE_PHASES_PER_TCK (IOE_PHASES_PER_TCK),
.IOE_DELAYS_PER_PHS (IOE_DELAYS_PER_PHS),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.PHY_DEF_MR_1ST (MEM_IF_MR_0),
.PHY_DEF_MR_2ND (MEM_IF_MR_1),
.PHY_DEF_MR_3RD (MEM_IF_MR_2),
.PHY_DEF_MR_4TH (MEM_IF_MR_3),
.MEM_IF_DQSN_EN (0),
.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
.FAMILY (FAMILY),
.FAMILYGROUP_ID (FAMILYGROUP_ID),
.SPEED_GRADE (SPEED_GRADE),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.WRITE_DESKEW_T10 (WRITE_DESKEW_T10),
.WRITE_DESKEW_HC_T10 (WRITE_DESKEW_HC_T10),
.WRITE_DESKEW_T9NI (WRITE_DESKEW_T9NI),
.WRITE_DESKEW_HC_T9NI (WRITE_DESKEW_HC_T9NI),
.WRITE_DESKEW_T9I (WRITE_DESKEW_T9I),
.WRITE_DESKEW_HC_T9I (WRITE_DESKEW_HC_T9I),
.WRITE_DESKEW_RANGE (WRITE_DESKEW_RANGE),
.SINGLE_DQS_DELAY_CONTROL_CODE (SINGLE_DQS_DELAY_CONTROL_CODE),
.PRESET_RLAT (PRESET_RLAT),
.EN_OCT (MEM_IF_OCT_EN),
.SIM_TIME_REDUCTIONS (REDUCE_SIM_TIME),
.FORCE_HC (FORCE_HC),
.CAPABILITIES (CAPABILITIES),
.GENERATE_ADDITIONAL_DBG_RTL (GENERATE_ADDITIONAL_DBG_RTL),
.TINIT_TCK (TINIT_TCK),
.TINIT_RST (TINIT_RST),
.GENERATE_TRACKING_PHASE_STORE (0),
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
.IP_BUILDNUM (IP_BUILDNUM),
.CHIP_OR_DIMM (CHIP_OR_DIMM),
.RDIMM_CONFIG_BITS (RDIMM_CONFIG_BITS)
) seq_inst (
.clk (phy_clk_1x),
.rst_n (reset_phy_clk_1x_n),
.ctl_init_success (ctl_cal_success),
.ctl_init_fail (ctl_cal_fail),
.ctl_init_warning (ctl_cal_warning),
.ctl_recalibrate_req (ctl_cal_req),
.MEM_AC_SWAPPED_RANKS (int_RANK_HAS_ADDR_SWAP),
.ctl_cal_byte_lanes (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.seq_pll_phs_shift_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.seq_scan_clk (sc_clk_dp),
.seq_scan_enable_dqs_config (scan_enable_dqs_config),
.seq_scan_update (scan_update),
.seq_scan_din (scan_din),
.seq_scan_enable_ck (scan_enable_ck),
.seq_scan_enable_dqs (scan_enable_dqs),
.seq_scan_enable_dqsn (scan_enable_dqsn),
.seq_scan_enable_dq (scan_enable_dq),
.seq_scan_enable_dm (scan_enable_dm),
.hr_rsc_clk (hr_rsc_clk),
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.seq_ac_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.seq_ac_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.seq_ac_add_2t (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_rdv_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.rdata (ctl_rdata),
.rdata_valid (int_rdata_valid_1t),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_value (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.seq_ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (mem_err_out_n),
.parity_error_n (parity_error_n),
.dbg_seq_clk (dbg_clk),
.dbg_seq_rst_n (dbg_reset_n),
.dbg_seq_addr (dbg_addr),
.dbg_seq_wr (dbg_wr),
.dbg_seq_rd (dbg_rd),
.dbg_seq_cs (dbg_cs),
.dbg_seq_wr_data (dbg_wr_data),
.seq_dbg_rd_data (dbg_rd_data),
.seq_dbg_waitrequest (dbg_waitrequest)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dds data to samples conversion
module cf_ddsv_vdma (
// vdma interface
vdma_clk,
vdma_valid,
vdma_data,
vdma_ready,
vdma_ovf,
vdma_unf,
// dac side (interpolator default) interface
dac_div3_clk,
dds_enable,
dds_rd,
dds_rdata,
// debug data (chipscope)
vdma_dbg_data,
vdma_dbg_trigger,
// debug data (chipscope)
dac_dbg_data,
dac_dbg_trigger);
// vdma interface
input vdma_clk;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
output vdma_ovf;
output vdma_unf;
// dac side (interpolator default) interface
input dac_div3_clk;
input dds_enable;
input dds_rd;
output [95:0] dds_rdata;
// debug data (chipscope)
output [198:0] vdma_dbg_data;
output [ 7:0] vdma_dbg_trigger;
// debug data (chipscope)
output [107:0] dac_dbg_data;
output [ 7:0] dac_dbg_trigger;
reg dds_start_m1 = 'd0;
reg dds_start = 'd0;
reg [ 7:0] dds_raddr = 'd0;
reg [ 7:0] dds_raddr_g = 'd0;
reg [95:0] dds_rdata = 'd0;
reg vdma_master_enable_m1 = 'd0;
reg vdma_master_enable = 'd0;
reg vdma_start = 'd0;
reg [ 1:0] vdma_dcnt = 'd0;
reg [63:0] vdma_data_d = 'd0;
reg vdma_wr = 'd0;
reg [ 7:0] vdma_waddr = 'd0;
reg [95:0] vdma_wdata = 'd0;
reg [ 7:0] vdma_raddr_g_m1 = 'd0;
reg [ 7:0] vdma_raddr_g_m2 = 'd0;
reg [ 7:0] vdma_raddr = 'd0;
reg [ 7:0] vdma_addr_diff = 'd0;
reg vdma_ready = 'd0;
reg vdma_almost_full = 'd0;
reg vdma_almost_empty = 'd0;
reg [ 4:0] vdma_ovf_count = 'd0;
reg vdma_ovf = 'd0;
reg [ 4:0] vdma_unf_count = 'd0;
reg vdma_unf = 'd0;
wire vdma_we_s;
wire [ 8:0] vdma_addr_diff_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [95:0] dds_rdata_s;
// binary to grey coversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// debug signals
assign vdma_dbg_trigger[7:7] = vdma_valid;
assign vdma_dbg_trigger[6:6] = vdma_ready;
assign vdma_dbg_trigger[5:5] = vdma_master_enable;
assign vdma_dbg_trigger[4:4] = vdma_start;
assign vdma_dbg_trigger[3:3] = vdma_wr;
assign vdma_dbg_trigger[2:2] = vdma_we_s;
assign vdma_dbg_trigger[1:1] = vdma_ovf_s;
assign vdma_dbg_trigger[0:0] = vdma_unf_s;
assign vdma_dbg_data[198:198] = vdma_valid;
assign vdma_dbg_data[197:197] = vdma_ready;
assign vdma_dbg_data[196:196] = vdma_ovf;
assign vdma_dbg_data[195:195] = vdma_unf;
assign vdma_dbg_data[194:194] = vdma_master_enable_m1;
assign vdma_dbg_data[193:193] = vdma_master_enable;
assign vdma_dbg_data[192:192] = vdma_start;
assign vdma_dbg_data[191:191] = vdma_wr;
assign vdma_dbg_data[190:190] = vdma_almost_full;
assign vdma_dbg_data[189:189] = vdma_almost_empty;
assign vdma_dbg_data[188:188] = vdma_we_s;
assign vdma_dbg_data[187:187] = vdma_ovf_s;
assign vdma_dbg_data[186:186] = vdma_unf_s;
assign vdma_dbg_data[185:184] = vdma_dcnt;
assign vdma_dbg_data[183:176] = vdma_waddr;
assign vdma_dbg_data[175:168] = vdma_raddr;
assign vdma_dbg_data[167:160] = vdma_addr_diff;
assign vdma_dbg_data[159: 96] = vdma_data;
assign vdma_dbg_data[ 95: 0] = vdma_wdata;
assign dac_dbg_trigger[7:4] = 'd0;
assign dac_dbg_trigger[3:3] = dds_enable;
assign dac_dbg_trigger[2:2] = dds_rd;
assign dac_dbg_trigger[1:1] = dds_start_m1;
assign dac_dbg_trigger[0:0] = dds_start;
assign dac_dbg_data[107:107] = dds_enable;
assign dac_dbg_data[106:106] = dds_rd;
assign dac_dbg_data[105:105] = dds_start_m1;
assign dac_dbg_data[104:104] = dds_start;
assign dac_dbg_data[103: 96] = dds_raddr;
assign dac_dbg_data[ 95: 0] = dds_rdata;
// dds read and data output (nothing special)
always @(posedge dac_div3_clk) begin
dds_start_m1 <= vdma_start;
dds_start <= dds_start_m1;
if (dds_start == 1'b0) begin
dds_raddr <= 8'h80;
end else if (dds_rd == 1'b1) begin
dds_raddr <= dds_raddr + 1'b1;
end
dds_raddr_g <= b2g(dds_raddr);
dds_rdata <= dds_rdata_s;
end
// vdma write, the incoming data is 4 samples (64bits), in order to interface seamlessly to the
// OSERDES 3:1 ratio, the dac is set to read 3 (or 6) samples. So data is written to the
// memory as 6 samples (96bits).
assign vdma_we_s = vdma_valid & vdma_ready;
always @(posedge vdma_clk) begin
vdma_master_enable_m1 <= dds_enable;
vdma_master_enable <= vdma_master_enable_m1;
if (vdma_master_enable == 1'b0) begin
vdma_start <= 1'b0;
vdma_dcnt <= 2'd0;
vdma_data_d <= 64'd0;
vdma_wr <= 1'b0;
vdma_waddr <= 8'd0;
vdma_wdata <= 96'd0;
end else if (vdma_we_s == 1'b1) begin
vdma_start <= 1'b1;
if (vdma_dcnt >= 2'd2) begin
vdma_dcnt <= 2'd0;
end else begin
vdma_dcnt <= vdma_dcnt + 1'b1;
end
vdma_data_d <= vdma_data;
vdma_wr <= vdma_dcnt[0] | vdma_dcnt[1];
if (vdma_wr == 1'b1) begin
vdma_waddr <= vdma_waddr + 1'b1;
end
if (vdma_dcnt == 2'd1) begin
vdma_wdata[95:80] <= vdma_data_d[15: 0];
vdma_wdata[79:64] <= vdma_data_d[31:16];
vdma_wdata[63:48] <= vdma_data_d[47:32];
vdma_wdata[47:32] <= vdma_data_d[63:48];
vdma_wdata[31:16] <= vdma_data[15: 0];
vdma_wdata[15: 0] <= vdma_data[31:16];
end else begin
vdma_wdata[95:80] <= vdma_data_d[47:32];
vdma_wdata[79:64] <= vdma_data_d[63:48];
vdma_wdata[63:48] <= vdma_data[15: 0];
vdma_wdata[47:32] <= vdma_data[31:16];
vdma_wdata[31:16] <= vdma_data[47:32];
vdma_wdata[15: 0] <= vdma_data[63:48];
end
end
end
// overflow or underflow status
assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
assign vdma_ovf_s = (vdma_addr_diff < 3) ? vdma_almost_full : 1'b0;
assign vdma_unf_s = (vdma_addr_diff > 250) ? vdma_almost_empty : 1'b0;
always @(posedge vdma_clk) begin
vdma_raddr_g_m1 <= dds_raddr_g;
vdma_raddr_g_m2 <= vdma_raddr_g_m1;
vdma_raddr <= g2b(vdma_raddr_g_m2);
vdma_addr_diff <= vdma_addr_diff_s[7:0];
if (vdma_addr_diff >= 250) begin
vdma_ready <= ~vdma_master_enable;
end else if (vdma_addr_diff <= 200) begin
vdma_ready <= 1'b1;
end
vdma_almost_full = (vdma_addr_diff > 250) ? 1'b1 : 1'b0;
vdma_almost_empty = (vdma_addr_diff < 3) ? 1'b1 : 1'b0;
if (vdma_ovf_s == 1'b1) begin
vdma_ovf_count <= 5'h10;
end else if (vdma_ovf_count[4] == 1'b1) begin
vdma_ovf_count <= vdma_ovf_count + 1'b1;
end
vdma_ovf <= vdma_ovf_count[4];
if (vdma_unf_s == 1'b1) begin
vdma_unf_count <= 5'h10;
end else if (vdma_unf_count[4] == 1'b1) begin
vdma_unf_count <= vdma_unf_count + 1'b1;
end
vdma_unf <= vdma_unf_count[4];
end
// memory
cf_mem #(.DW(96), .AW(8)) i_mem (
.clka (vdma_clk),
.wea (vdma_wr),
.addra (vdma_waddr),
.dina (vdma_wdata),
.clkb (dac_div3_clk),
.addrb (dds_raddr),
.doutb (dds_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Connection Matrix Register File ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_conmax_rf.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: wb_conmax_rf.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.2 2002/10/03 05:40:07 rudi
// Fixed a minor bug in parameter passing, updated headers and specification.
//
// Revision 1.1.1.1 2001/10/19 11:01:42 rudi
// WISHBONE CONMAX IP Core
//
//
//
//
//
`include "wb_conmax_defines.v"
module wb_conmax_rf(
clk_i, rst_i,
// Internal Wishbone Interface
i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i,
i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o,
// External Wishbone Interface
e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o,
e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i,
// Configuration Registers
conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7,
conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter [3:0] rf_addr = 4'hf;
parameter dw = 32; // Data bus Width
parameter aw = 32; // Address bus Width
parameter sw = dw / 8; // Number of Select Lines
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
// Internal Wishbone Interface
input [dw-1:0] i_wb_data_i;
output [dw-1:0] i_wb_data_o;
input [aw-1:0] i_wb_addr_i;
input [sw-1:0] i_wb_sel_i;
input i_wb_we_i;
input i_wb_cyc_i;
input i_wb_stb_i;
output i_wb_ack_o;
output i_wb_err_o;
output i_wb_rty_o;
// External Wishbone Interface
input [dw-1:0] e_wb_data_i;
output [dw-1:0] e_wb_data_o;
output [aw-1:0] e_wb_addr_o;
output [sw-1:0] e_wb_sel_o;
output e_wb_we_o;
output e_wb_cyc_o;
output e_wb_stb_o;
input e_wb_ack_i;
input e_wb_err_i;
input e_wb_rty_i;
// Configuration Registers
output [15:0] conf0;
output [15:0] conf1;
output [15:0] conf2;
output [15:0] conf3;
output [15:0] conf4;
output [15:0] conf5;
output [15:0] conf6;
output [15:0] conf7;
output [15:0] conf8;
output [15:0] conf9;
output [15:0] conf10;
output [15:0] conf11;
output [15:0] conf12;
output [15:0] conf13;
output [15:0] conf14;
output [15:0] conf15;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [15:0] conf0, conf1, conf2, conf3, conf4, conf5;
reg [15:0] conf6, conf7, conf8, conf9, conf10, conf11;
reg [15:0] conf12, conf13, conf14, conf15;
//synopsys infer_multibit "conf0"
//synopsys infer_multibit "conf1"
//synopsys infer_multibit "conf2"
//synopsys infer_multibit "conf3"
//synopsys infer_multibit "conf4"
//synopsys infer_multibit "conf5"
//synopsys infer_multibit "conf6"
//synopsys infer_multibit "conf7"
//synopsys infer_multibit "conf8"
//synopsys infer_multibit "conf9"
//synopsys infer_multibit "conf10"
//synopsys infer_multibit "conf11"
//synopsys infer_multibit "conf12"
//synopsys infer_multibit "conf13"
//synopsys infer_multibit "conf14"
//synopsys infer_multibit "conf15"
wire rf_sel;
reg [15:0] rf_dout;
reg rf_ack;
reg rf_we;
////////////////////////////////////////////////////////////////////
//
// Register File Select Logic
//
assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr);
////////////////////////////////////////////////////////////////////
//
// Register File Logic
//
always @(posedge clk_i)
rf_we <= #1 rf_sel & i_wb_we_i & !rf_we;
always @(posedge clk_i)
rf_ack <= #1 rf_sel & !rf_ack;
// Writre Logic
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf0 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd0) ) conf0 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf1 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd1) ) conf1 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf2 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd2) ) conf2 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf3 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd3) ) conf3 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf4 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd4) ) conf4 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf5 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd5) ) conf5 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf6 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd6) ) conf6 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf7 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd7) ) conf7 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf8 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd8) ) conf8 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf9 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd9) ) conf9 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf10 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd10) ) conf10 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf11 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd11) ) conf11 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf12 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd12) ) conf12 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf13 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd13) ) conf13 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf14 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd14) ) conf14 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf15 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd15) ) conf15 <= #1 i_wb_data_i[15:0];
// Read Logic
always @(posedge clk_i)
if(!rf_sel) rf_dout <= #1 16'h0;
else
case(i_wb_addr_i[5:2])
4'd0: rf_dout <= #1 conf0;
4'd1: rf_dout <= #1 conf1;
4'd2: rf_dout <= #1 conf2;
4'd3: rf_dout <= #1 conf3;
4'd4: rf_dout <= #1 conf4;
4'd5: rf_dout <= #1 conf5;
4'd6: rf_dout <= #1 conf6;
4'd7: rf_dout <= #1 conf7;
4'd8: rf_dout <= #1 conf8;
4'd9: rf_dout <= #1 conf9;
4'd10: rf_dout <= #1 conf10;
4'd11: rf_dout <= #1 conf11;
4'd12: rf_dout <= #1 conf12;
4'd13: rf_dout <= #1 conf13;
4'd14: rf_dout <= #1 conf14;
4'd15: rf_dout <= #1 conf15;
endcase
////////////////////////////////////////////////////////////////////
//
// Register File By-Pass Logic
//
assign e_wb_addr_o = i_wb_addr_i;
assign e_wb_sel_o = i_wb_sel_i;
assign e_wb_data_o = i_wb_data_i;
assign e_wb_cyc_o = rf_sel ? 1'b0 : i_wb_cyc_i;
assign e_wb_stb_o = i_wb_stb_i;
assign e_wb_we_o = i_wb_we_i;
assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i;
assign i_wb_ack_o = rf_sel ? rf_ack : e_wb_ack_i;
assign i_wb_err_o = rf_sel ? 1'b0 : e_wb_err_i;
assign i_wb_rty_o = rf_sel ? 1'b0 : e_wb_rty_i;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFKAPWR_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUFKAPWR_BEHAVIORAL_V
/**
* bufkapwr: Buffer on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__bufkapwr (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFKAPWR_BEHAVIORAL_V |
//======================================================================
//
// tb_sha512.v
// -----------
// Testbench for the SHA-512 top level wrapper.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module tb_sha512();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_PERIOD = 2;
parameter CLK_HALF_PERIOD = CLK_PERIOD / 2;
// The address map.
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter ADDR_CTRL = 8'h08;
parameter CTRL_INIT_BIT = 0;
parameter CTRL_NEXT_BIT = 1;
parameter CTRL_MODE_LOW_BIT = 2;
parameter CTRL_MODE_HIGH_BIT = 3;
parameter CTRL_WORK_FACTOR_BIT = 7;
parameter ADDR_STATUS = 8'h09;
parameter STATUS_READY_BIT = 0;
parameter STATUS_VALID_BIT = 1;
parameter ADDR_WORK_FACTOR_NUM = 8'h0a;
parameter ADDR_BLOCK0 = 8'h10;
parameter ADDR_BLOCK1 = 8'h11;
parameter ADDR_BLOCK2 = 8'h12;
parameter ADDR_BLOCK3 = 8'h13;
parameter ADDR_BLOCK4 = 8'h14;
parameter ADDR_BLOCK5 = 8'h15;
parameter ADDR_BLOCK6 = 8'h16;
parameter ADDR_BLOCK7 = 8'h17;
parameter ADDR_BLOCK8 = 8'h18;
parameter ADDR_BLOCK9 = 8'h19;
parameter ADDR_BLOCK10 = 8'h1a;
parameter ADDR_BLOCK11 = 8'h1b;
parameter ADDR_BLOCK12 = 8'h1c;
parameter ADDR_BLOCK13 = 8'h1d;
parameter ADDR_BLOCK14 = 8'h1e;
parameter ADDR_BLOCK15 = 8'h1f;
parameter ADDR_BLOCK16 = 8'h20;
parameter ADDR_BLOCK17 = 8'h21;
parameter ADDR_BLOCK18 = 8'h22;
parameter ADDR_BLOCK19 = 8'h23;
parameter ADDR_BLOCK20 = 8'h24;
parameter ADDR_BLOCK21 = 8'h25;
parameter ADDR_BLOCK22 = 8'h26;
parameter ADDR_BLOCK23 = 8'h27;
parameter ADDR_BLOCK24 = 8'h28;
parameter ADDR_BLOCK25 = 8'h29;
parameter ADDR_BLOCK26 = 8'h2a;
parameter ADDR_BLOCK27 = 8'h2b;
parameter ADDR_BLOCK28 = 8'h2c;
parameter ADDR_BLOCK29 = 8'h2d;
parameter ADDR_BLOCK30 = 8'h2e;
parameter ADDR_BLOCK31 = 8'h2f;
parameter ADDR_DIGEST0 = 8'h40;
parameter ADDR_DIGEST1 = 8'h41;
parameter ADDR_DIGEST2 = 8'h42;
parameter ADDR_DIGEST3 = 8'h43;
parameter ADDR_DIGEST4 = 8'h44;
parameter ADDR_DIGEST5 = 8'h45;
parameter ADDR_DIGEST6 = 8'h46;
parameter ADDR_DIGEST7 = 8'h47;
parameter ADDR_DIGEST8 = 8'h48;
parameter ADDR_DIGEST9 = 8'h49;
parameter ADDR_DIGEST10 = 8'h4a;
parameter ADDR_DIGEST11 = 8'h4b;
parameter ADDR_DIGEST12 = 8'h4c;
parameter ADDR_DIGEST13 = 8'h4d;
parameter ADDR_DIGEST14 = 8'h4e;
parameter ADDR_DIGEST15 = 8'h4f;
parameter MODE_SHA_512_224 = 2'h0;
parameter MODE_SHA_512_256 = 2'h1;
parameter MODE_SHA_384 = 2'h2;
parameter MODE_SHA_512 = 2'h3;
parameter CTRL_INIT_VALUE = 2'h1;
parameter CTRL_NEXT_VALUE = 2'h2;
parameter CTRL_WORK_FACTOR_VALUE = 1'h1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
reg [31 : 0] read_data;
reg [511 : 0] digest_data;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
sha512 dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data),
.error(tb_error)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor
//
// Generates a cycle counter and displays information about
// the dut as needed.
//----------------------------------------------------------------
always
begin : sys_monitor
#(2 * CLK_HALF_PERIOD);
cycle_ctr = cycle_ctr + 1;
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("cs = 0x%01x, we = 0x%01x",
dut.cs, dut.we);
$display("address = 0x%02x", dut.address);
$display("write_data = 0x%08x, read_data = 0x%08x",
dut.write_data, dut.read_data);
$display("tmp_read_data = 0x%08x", dut.tmp_read_data);
$display("");
$display("Control and status:");
$display("ctrl = 0x%02x, status = 0x%02x",
{dut.next_reg, dut.init_reg},
{dut.digest_valid_reg, dut.ready_reg});
$display("");
$display("Message block:");
$display("block0 = 0x%08x, block1 = 0x%08x, block2 = 0x%08x, block3 = 0x%08x",
dut.block_reg[00], dut.block_reg[01], dut.block_reg[02], dut.block_reg[03]);
$display("block4 = 0x%08x, block5 = 0x%08x, block6 = 0x%08x, block7 = 0x%08x",
dut.block_reg[04], dut.block_reg[05], dut.block_reg[06], dut.block_reg[07]);
$display("block8 = 0x%08x, block9 = 0x%08x, block10 = 0x%08x, block11 = 0x%08x",
dut.block_reg[08], dut.block_reg[09], dut.block_reg[10], dut.block_reg[11]);
$display("block12 = 0x%08x, block13 = 0x%08x, block14 = 0x%08x, block15 = 0x%08x",
dut.block_reg[12], dut.block_reg[13], dut.block_reg[14], dut.block_reg[15]);
$display("block16 = 0x%08x, block17 = 0x%08x, block18 = 0x%08x, block19 = 0x%08x",
dut.block_reg[16], dut.block_reg[17], dut.block_reg[18], dut.block_reg[19]);
$display("block20 = 0x%08x, block21 = 0x%08x, block22 = 0x%08x, block23 = 0x%08x",
dut.block_reg[20], dut.block_reg[21], dut.block_reg[22], dut.block_reg[23]);
$display("block24 = 0x%08x, block25 = 0x%08x, block26 = 0x%08x, block27 = 0x%08x",
dut.block_reg[24], dut.block_reg[25], dut.block_reg[26], dut.block_reg[27]);
$display("block28 = 0x%08x, block29 = 0x%08x, block30 = 0x%08x, block31 = 0x%08x",
dut.block_reg[28], dut.block_reg[29], dut.block_reg[30], dut.block_reg[31]);
$display("");
$display("Digest:");
$display("digest = 0x%0128x", dut.digest_reg);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggles reset to force the DUT into a well defined state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 32'h00000000;
error_ctr = 32'h00000000;
tc_ctr = 32'h00000000;
tb_clk = 0;
tb_reset_n = 0;
tb_cs = 0;
tb_we = 0;
tb_address = 6'h00;
tb_write_data = 32'h00000000;
end
endtask // init_dut
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully.", tc_ctr);
end
else
begin
$display("*** %02d test cases completed.", tc_ctr);
$display("*** %02d errors detected during testing.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
// (Actually we wait for either ready or valid to be set.)
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
read_data = 0;
while (read_data == 0)
begin
read_word(ADDR_STATUS);
end
end
endtask // wait_ready
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [7 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(2 * CLK_HALF_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// write_block()
//
// Write the given block to the dut.
//----------------------------------------------------------------
task write_block(input [1023 : 0] block);
begin
write_word(ADDR_BLOCK0, block[1023 : 992]);
write_word(ADDR_BLOCK1, block[991 : 960]);
write_word(ADDR_BLOCK2, block[959 : 928]);
write_word(ADDR_BLOCK3, block[927 : 896]);
write_word(ADDR_BLOCK4, block[895 : 864]);
write_word(ADDR_BLOCK5, block[863 : 832]);
write_word(ADDR_BLOCK6, block[831 : 800]);
write_word(ADDR_BLOCK7, block[799 : 768]);
write_word(ADDR_BLOCK8, block[767 : 736]);
write_word(ADDR_BLOCK9, block[735 : 704]);
write_word(ADDR_BLOCK10, block[703 : 672]);
write_word(ADDR_BLOCK11, block[671 : 640]);
write_word(ADDR_BLOCK12, block[639 : 608]);
write_word(ADDR_BLOCK13, block[607 : 576]);
write_word(ADDR_BLOCK14, block[575 : 544]);
write_word(ADDR_BLOCK15, block[543 : 512]);
write_word(ADDR_BLOCK16, block[511 : 480]);
write_word(ADDR_BLOCK17, block[479 : 448]);
write_word(ADDR_BLOCK18, block[447 : 416]);
write_word(ADDR_BLOCK19, block[415 : 384]);
write_word(ADDR_BLOCK20, block[383 : 352]);
write_word(ADDR_BLOCK21, block[351 : 320]);
write_word(ADDR_BLOCK22, block[319 : 288]);
write_word(ADDR_BLOCK23, block[287 : 256]);
write_word(ADDR_BLOCK24, block[255 : 224]);
write_word(ADDR_BLOCK25, block[223 : 192]);
write_word(ADDR_BLOCK26, block[191 : 160]);
write_word(ADDR_BLOCK27, block[159 : 128]);
write_word(ADDR_BLOCK28, block[127 : 96]);
write_word(ADDR_BLOCK29, block[95 : 64]);
write_word(ADDR_BLOCK30, block[63 : 32]);
write_word(ADDR_BLOCK31, block[31 : 0]);
end
endtask // write_block
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [7 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// check_name_version()
//
// Read the name and version from the DUT.
//----------------------------------------------------------------
task check_name_version;
reg [31 : 0] name0;
reg [31 : 0] name1;
reg [31 : 0] version;
begin
read_word(ADDR_NAME0);
name0 = read_data;
read_word(ADDR_NAME1);
name1 = read_data;
read_word(ADDR_VERSION);
version = read_data;
$display("DUT name: %c%c%c%c%c%c%c%c",
name0[31 : 24], name0[23 : 16], name0[15 : 8], name0[7 : 0],
name1[31 : 24], name1[23 : 16], name1[15 : 8], name1[7 : 0]);
$display("DUT version: %c%c%c%c",
version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]);
end
endtask // check_name_version
//----------------------------------------------------------------
// read_digest()
//
// Read the digest in the dut. The resulting digest will be
// available in the global variable digest_data.
//----------------------------------------------------------------
task read_digest;
begin
read_word(ADDR_DIGEST0);
digest_data[511 : 480] = read_data;
read_word(ADDR_DIGEST1);
digest_data[479 : 448] = read_data;
read_word(ADDR_DIGEST2);
digest_data[447 : 416] = read_data;
read_word(ADDR_DIGEST3);
digest_data[415 : 384] = read_data;
read_word(ADDR_DIGEST4);
digest_data[383 : 352] = read_data;
read_word(ADDR_DIGEST5);
digest_data[351 : 320] = read_data;
read_word(ADDR_DIGEST6);
digest_data[319 : 288] = read_data;
read_word(ADDR_DIGEST7);
digest_data[287 : 256] = read_data;
read_word(ADDR_DIGEST8);
digest_data[255 : 224] = read_data;
read_word(ADDR_DIGEST9);
digest_data[223 : 192] = read_data;
read_word(ADDR_DIGEST10);
digest_data[191 : 160] = read_data;
read_word(ADDR_DIGEST11);
digest_data[159 : 128] = read_data;
read_word(ADDR_DIGEST12);
digest_data[127 : 96] = read_data;
read_word(ADDR_DIGEST13);
digest_data[95 : 64] = read_data;
read_word(ADDR_DIGEST14);
digest_data[63 : 32] = read_data;
read_word(ADDR_DIGEST15);
digest_data[31 : 0] = read_data;
end
endtask // read_digest
//----------------------------------------------------------------
// get_mask()
//
// Create the mask needed for a given mode.
//----------------------------------------------------------------
function [511 : 0] get_mask(input [1 : 0] mode);
begin
case (mode)
MODE_SHA_512_224:
begin
if (DEBUG)
begin
$display("Mode MODE_SHA_512_224");
end
get_mask = {{7{32'hffffffff}}, {9{32'h00000000}}};
end
MODE_SHA_512_256:
begin
if (DEBUG)
begin
$display("Mode MODE_SHA_512_256");
end
get_mask = {{8{32'hffffffff}}, {8{32'h00000000}}};
end
MODE_SHA_384:
begin
if (DEBUG)
begin
$display("Mode MODE_SHA_512_384");
end
get_mask = {{12{32'hffffffff}}, {4{32'h00000000}}};
end
MODE_SHA_512:
begin
if (DEBUG)
begin
$display("Mode MODE_SHA_512");
end
get_mask = {16{32'hffffffff}};
end
endcase // case (mode)
end
endfunction // get_mask
//----------------------------------------------------------------
// single_block_test()
//
//
// Perform test of a single block digest.
//----------------------------------------------------------------
task single_block_test(input [7 : 0] tc_number,
input [1 : 0] mode,
input [1023 : 0] block,
input [511 : 0] expected);
reg [511 : 0] mask;
reg [511 : 0] masked_data;
begin
$display("*** TC%01d - Single block test started.", tc_ctr);
write_block(block);
write_word(ADDR_CTRL, {28'h0000000, mode, CTRL_INIT_VALUE});
#(CLK_PERIOD);
wait_ready();
read_digest();
mask = get_mask(mode);
masked_data = digest_data & mask;
if (DEBUG)
begin
$display("masked_data = 0x%0128x", masked_data);
end
if (masked_data == expected)
begin
$display("TC%01d: OK.", tc_ctr);
end
else
begin
$display("TC%01d: ERROR.", tc_ctr);
$display("TC%01d: Expected: 0x%0128x", tc_ctr, expected);
$display("TC%01d: Got: 0x%0128x", tc_ctr, masked_data);
error_ctr = error_ctr + 1;
end
$display("*** TC%01d - Single block test done.", tc_ctr);
tc_ctr = tc_ctr + 1;
end
endtask // single_block_test
//----------------------------------------------------------------
// double_block_test()
//
//
// Perform test of a double block digest. Note that we check
// the digests for both the first and final block.
//----------------------------------------------------------------
task double_block_test(input [7 : 0] tc_number,
input [1 : 0] mode,
input [1023 : 0] block0,
input [1023 : 0] block1,
input [511 : 0] expected0,
input [511 : 0] expected1
);
reg [511 : 0] mask;
reg [511 : 0] masked_data1;
reg [31 : 0] ctrl_cmd;
begin
$display("*** TC%01d - Double block test started.", tc_ctr);
// First block
write_block(block0);
write_word(ADDR_CTRL, {28'h0000000, mode, CTRL_INIT_VALUE});
#(CLK_PERIOD);
wait_ready();
read_digest();
if (digest_data == expected0)
begin
$display("TC%01d first block: OK.", tc_ctr);
end
else
begin
$display("TC%01d: ERROR in first digest", tc_ctr);
$display("TC%01d: Expected: 0x%064x", tc_ctr, expected0);
$display("TC%01d: Got: 0x%064x", tc_ctr, digest_data);
error_ctr = error_ctr + 1;
end
// Final block
write_block(block1);
write_word(ADDR_CTRL, {28'h0000000, mode, CTRL_NEXT_VALUE});
#(CLK_PERIOD);
wait_ready();
read_digest();
mask = get_mask(mode);
masked_data1 = digest_data & mask;
if (masked_data1 == expected1)
begin
$display("TC%01d final block: OK.", tc_ctr);
end
else
begin
$display("TC%01d: ERROR in final digest", tc_ctr);
$display("TC%01d: Expected: 0x%0128x", tc_ctr, expected1);
$display("TC%01d: Got: 0x%0128x", tc_ctr, masked_data1);
error_ctr = error_ctr + 1;
end
$display("*** TC%01d - Double block test done.", tc_ctr);
tc_ctr = tc_ctr + 1;
end
endtask // double_block_test
//----------------------------------------------------------------
// work_factor_test()
//
// Perform test of the work factor function.
//----------------------------------------------------------------
task work_factor_test;
reg [1023 : 0] my_block;
reg [511 : 0] my_digest;
reg [31 : 0] my_ctrl_cmd;
begin
$display("*** TC%01d - Work factor test started.", tc_ctr);
// Read out work factor number.
read_word(ADDR_WORK_FACTOR_NUM);
// Trying to change the work factor number.
write_word(ADDR_WORK_FACTOR_NUM, 32'h00000003);
read_word(ADDR_WORK_FACTOR_NUM);
// Set block to all zero
my_block = {16{64'h0000000000000000}};
write_block(my_block);
// Set init+ work factor. We use SHA-512 mode.
my_ctrl_cmd = 32'h00000000 + (CTRL_WORK_FACTOR_VALUE << 7) +
(MODE_SHA_512 << 2) + CTRL_INIT_VALUE;
write_word(ADDR_CTRL, my_ctrl_cmd);
#(CLK_PERIOD);
wait_ready();
read_digest();
$display("*** TC%01d - Work factor test done.", tc_ctr);
tc_ctr = tc_ctr + 1;
end
endtask // work_factor_test
//----------------------------------------------------------------
// sha512_test
// The main test functionality.
//
// Test cases taken from:
// http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf
//----------------------------------------------------------------
initial
begin : sha512_test
reg [1024 : 0] single_block;
reg [511 : 0] tc1_expected;
reg [511 : 0] tc2_expected;
reg [511 : 0] tc3_expected;
reg [511 : 0] tc4_expected;
reg [1024 : 0] double_block_one;
reg [1024 : 0] double_block_two;
reg [511 : 0] tc5_expected;
reg [511 : 0] tc6_expected;
reg [511 : 0] tc7_expected;
reg [511 : 0] tc8_expected;
reg [511 : 0] tc9_expected;
reg [511 : 0] tc10_expected;
reg [511 : 0] tc11_expected;
reg [511 : 0] tc12_expected;
$display(" -- Testbench for sha512 started --");
init_sim();
reset_dut();
check_name_version();
// dump_dut_state();
// write_word(ADDR_BLOCK0, 32'hdeadbeef);
dump_dut_state();
// read_word(ADDR_BLOCK0);
// dump_dut_state();
// Single block test mesage.
single_block = 1024'h6162638000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
// SHA-512 single block digest and test.
tc1_expected = 512'hDDAF35A193617ABACC417349AE20413112E6FA4E89A97EA20A9EEEE64B55D39A2192992A274FC1A836BA3C23A3FEEBBD454D4423643CE80E2A9AC94FA54CA49F;
single_block_test(8'h01, MODE_SHA_512, single_block, tc1_expected);
// SHA-512_224 single block digest and test.
tc2_expected = {224'h4634270F707B6A54DAAE7530460842E20E37ED265CEEE9A43E8924AA, {9{32'h00000000}}};
single_block_test(8'h02, MODE_SHA_512_224, single_block, tc2_expected);
// SHA-512_256 single block digest and test.
tc3_expected = {256'h53048E2681941EF99B2E29B76B4C7DABE4C2D0C634FC6D46E0E2F13107E7AF23, {8{32'h00000000}}};
single_block_test(8'h03, MODE_SHA_512_256, single_block, tc3_expected);
// SHA-384 single block digest and test.
tc4_expected = {384'hCB00753F45A35E8BB5A03D699AC65007272C32AB0EDED1631A8B605A43FF5BED8086072BA1E7CC2358BAECA134C825A7, {4{32'h00000000}}};
single_block_test(8'h04, MODE_SHA_384, single_block, tc4_expected);
// Two block test message.
double_block_one = 1024'h61626364656667686263646566676869636465666768696A6465666768696A6B65666768696A6B6C666768696A6B6C6D6768696A6B6C6D6E68696A6B6C6D6E6F696A6B6C6D6E6F706A6B6C6D6E6F70716B6C6D6E6F7071726C6D6E6F707172736D6E6F70717273746E6F70717273747580000000000000000000000000000000;
double_block_two = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000380;
// SHA-512 two block digests and test.
tc5_expected = 512'h4319017A2B706E69CD4B05938BAE5E890186BF199F30AA956EF8B71D2F810585D787D6764B20BDA2A26014470973692000EC057F37D14B8E06ADD5B50E671C72;
tc6_expected = 512'h8E959B75DAE313DA8CF4F72814FC143F8F7779C6EB9F7FA17299AEADB6889018501D289E4900F7E4331B99DEC4B5433AC7D329EEB6DD26545E96E55B874BE909;
double_block_test(8'h05, MODE_SHA_512, double_block_one, double_block_two, tc5_expected, tc6_expected);
// SHA-512_224 two block digests and test.
tc7_expected = 512'h9606CB2DB7823CE75FE35E2674A8F9EF1417ED9E89C412BB54EA29664586108625852563EED495096DEBAAE2F4737FD75319224B135486F8E6C0F55E700C35B3;
tc8_expected = {224'h23FEC5BB94D60B23308192640B0C453335D664734FE40E7268674AF9, {9{32'h00000000}}};
double_block_test(8'h06, MODE_SHA_512_224, double_block_one, double_block_two, tc7_expected, tc8_expected);
// SHA-512_256 two block digests and test.
tc9_expected = 512'h8DD99EB081311F8BCBBBC42CC7AFB288E8E9408730419D1E953FF7A2B194048DAE24175483C44C7C809B348E8E88E3ECBF2EA614CEED9C5B51807937F11867E1;
tc10_expected = {256'h3928E184FB8690F840DA3988121D31BE65CB9D3EF83EE6146FEAC861E19B563A, {8{32'h00000000}}};
double_block_test(8'h07, MODE_SHA_512_256, double_block_one, double_block_two, tc9_expected, tc10_expected);
// SHA-384 two block digests and test.
tc11_expected = 512'h2A7F1D895FD58E0BEAAE96D1A673C741015A2173796C1A88F6352CA156ACAFF7C662113E9EBB4D6417B61A85E2CCF0A937EB9A6660FEB5198F2EBE9A81E6A2C5;
tc12_expected = {384'h09330C33F71147E83D192FC782CD1B4753111B173B3B05D22FA08086E3B0F712FCC7C71A557E2DB966C3E9FA91746039, {4{32'h00000000}}};
double_block_test(8'h08, MODE_SHA_384, double_block_one, double_block_two, tc11_expected, tc12_expected);
// Work factor test.
work_factor_test();
dump_dut_state();
display_test_result();
$display(" -- Testbench for sha512 done. --");
$finish;
end // sha512_test
endmodule // tb_sha512
//======================================================================
// EOF tb_sha512.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_PR_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_DLATCH_PR_SYMBOL_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dlatch$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_PR_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.68d
// \ \ Application: netgen
// / / Filename: mult10to12.v
// /___/ /\ Timestamp: Sat Aug 30 20:07:15 2014
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog "C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/Lab3_part1/ipcore_dir/tmp/_cg/mult10to12.ngc" "C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/Lab3_part1/ipcore_dir/tmp/_cg/mult10to12.v"
// Device : 7a100tcsg324-3
// Input file : C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/Lab3_part1/ipcore_dir/tmp/_cg/mult10to12.ngc
// Output file : C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/Lab3_part1/ipcore_dir/tmp/_cg/mult10to12.v
// # of Modules : 1
// Design Name : mult10to12
// Xilinx : C:\Xilinx\14.6\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module mult10to12 (
clk, a, b, p
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input [9 : 0] a;
input [11 : 0] b;
output [21 : 0] p;
// synthesis translate_off
wire \blk00000001/sig000001ea ;
wire \blk00000001/sig000001e9 ;
wire \blk00000001/sig000001e8 ;
wire \blk00000001/sig000001e7 ;
wire \blk00000001/sig000001e6 ;
wire \blk00000001/sig000001e5 ;
wire \blk00000001/sig000001e4 ;
wire \blk00000001/sig000001e3 ;
wire \blk00000001/sig000001e2 ;
wire \blk00000001/sig000001e1 ;
wire \blk00000001/sig000001e0 ;
wire \blk00000001/sig000001df ;
wire \blk00000001/sig000001de ;
wire \blk00000001/sig000001dd ;
wire \blk00000001/sig000001dc ;
wire \blk00000001/sig000001db ;
wire \blk00000001/sig000001da ;
wire \blk00000001/sig000001d9 ;
wire \blk00000001/sig000001d8 ;
wire \blk00000001/sig000001d7 ;
wire \blk00000001/sig000001d6 ;
wire \blk00000001/sig000001d5 ;
wire \blk00000001/sig000001d4 ;
wire \blk00000001/sig000001d3 ;
wire \blk00000001/sig000001d2 ;
wire \blk00000001/sig000001d1 ;
wire \blk00000001/sig000001d0 ;
wire \blk00000001/sig000001cf ;
wire \blk00000001/sig000001ce ;
wire \blk00000001/sig000001cd ;
wire \blk00000001/sig000001cc ;
wire \blk00000001/sig000001cb ;
wire \blk00000001/sig000001ca ;
wire \blk00000001/sig000001c9 ;
wire \blk00000001/sig000001c8 ;
wire \blk00000001/sig000001c7 ;
wire \blk00000001/sig000001c6 ;
wire \blk00000001/sig000001c5 ;
wire \blk00000001/sig000001c4 ;
wire \blk00000001/sig000001c3 ;
wire \blk00000001/sig000001c2 ;
wire \blk00000001/sig000001c1 ;
wire \blk00000001/sig000001c0 ;
wire \blk00000001/sig000001bf ;
wire \blk00000001/sig000001be ;
wire \blk00000001/sig000001bd ;
wire \blk00000001/sig000001bc ;
wire \blk00000001/sig000001bb ;
wire \blk00000001/sig000001ba ;
wire \blk00000001/sig000001b9 ;
wire \blk00000001/sig000001b8 ;
wire \blk00000001/sig000001b7 ;
wire \blk00000001/sig000001b6 ;
wire \blk00000001/sig000001b5 ;
wire \blk00000001/sig000001b4 ;
wire \blk00000001/sig000001b3 ;
wire \blk00000001/sig000001b2 ;
wire \blk00000001/sig000001b1 ;
wire \blk00000001/sig000001b0 ;
wire \blk00000001/sig000001af ;
wire \blk00000001/sig000001ae ;
wire \blk00000001/sig000001ad ;
wire \blk00000001/sig000001ac ;
wire \blk00000001/sig000001ab ;
wire \blk00000001/sig000001aa ;
wire \blk00000001/sig000001a9 ;
wire \blk00000001/sig000001a8 ;
wire \blk00000001/sig000001a7 ;
wire \blk00000001/sig000001a6 ;
wire \blk00000001/sig000001a5 ;
wire \blk00000001/sig000001a4 ;
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \blk00000001/sig00000031 ;
wire \blk00000001/sig00000030 ;
wire \blk00000001/sig0000002f ;
wire \blk00000001/sig0000002e ;
LUT3 #(
.INIT ( 8'h9F ))
\blk00000001/blk000001d4 (
.I0(a[9]),
.I1(a[8]),
.I2(b[11]),
.O(\blk00000001/sig000001ea )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk000001d3 (
.I0(b[0]),
.I1(a[0]),
.O(\blk00000001/sig000001e9 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk000001d2 (
.I0(b[0]),
.I1(a[2]),
.O(\blk00000001/sig000001e6 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk000001d1 (
.I0(b[0]),
.I1(a[4]),
.O(\blk00000001/sig000001e3 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk000001d0 (
.I0(b[0]),
.I1(a[6]),
.O(\blk00000001/sig000001e0 )
);
LUT2 #(
.INIT ( 4'h7 ))
\blk00000001/blk000001cf (
.I0(b[0]),
.I1(a[8]),
.O(\blk00000001/sig00000198 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001ce (
.I0(b[10]),
.I1(a[0]),
.I2(b[9]),
.I3(a[1]),
.O(\blk00000001/sig00000108 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001cd (
.I0(b[10]),
.I1(a[1]),
.I2(b[11]),
.I3(a[0]),
.O(\blk00000001/sig000000ff )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000001cc (
.I0(b[11]),
.I1(a[1]),
.I2(a[0]),
.O(\blk00000001/sig000000f6 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000001cb (
.I0(b[11]),
.I1(a[1]),
.I2(a[0]),
.O(\blk00000001/sig000000ed )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001ca (
.I0(b[0]),
.I1(a[1]),
.I2(b[1]),
.I3(a[0]),
.O(\blk00000001/sig0000015d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c9 (
.I0(b[1]),
.I1(a[1]),
.I2(b[2]),
.I3(a[0]),
.O(\blk00000001/sig00000150 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c8 (
.I0(b[2]),
.I1(a[1]),
.I2(b[3]),
.I3(a[0]),
.O(\blk00000001/sig00000147 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c7 (
.I0(b[3]),
.I1(a[1]),
.I2(b[4]),
.I3(a[0]),
.O(\blk00000001/sig0000013e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c6 (
.I0(b[4]),
.I1(a[1]),
.I2(b[5]),
.I3(a[0]),
.O(\blk00000001/sig00000135 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c5 (
.I0(b[5]),
.I1(a[1]),
.I2(b[6]),
.I3(a[0]),
.O(\blk00000001/sig0000012c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c4 (
.I0(b[6]),
.I1(a[1]),
.I2(b[7]),
.I3(a[0]),
.O(\blk00000001/sig00000123 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c3 (
.I0(b[7]),
.I1(a[1]),
.I2(b[8]),
.I3(a[0]),
.O(\blk00000001/sig0000011a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c2 (
.I0(b[8]),
.I1(a[1]),
.I2(b[9]),
.I3(a[0]),
.O(\blk00000001/sig00000111 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c1 (
.I0(b[10]),
.I1(a[2]),
.I2(b[9]),
.I3(a[3]),
.O(\blk00000001/sig00000106 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001c0 (
.I0(b[10]),
.I1(a[3]),
.I2(b[11]),
.I3(a[2]),
.O(\blk00000001/sig000000fd )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000001bf (
.I0(b[11]),
.I1(a[3]),
.I2(a[2]),
.O(\blk00000001/sig000000f4 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000001be (
.I0(b[11]),
.I1(a[3]),
.I2(a[2]),
.O(\blk00000001/sig000000ec )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001bd (
.I0(b[0]),
.I1(a[3]),
.I2(b[1]),
.I3(a[2]),
.O(\blk00000001/sig0000015a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001bc (
.I0(b[1]),
.I1(a[3]),
.I2(b[2]),
.I3(a[2]),
.O(\blk00000001/sig0000014e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001bb (
.I0(b[2]),
.I1(a[3]),
.I2(b[3]),
.I3(a[2]),
.O(\blk00000001/sig00000145 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001ba (
.I0(b[3]),
.I1(a[3]),
.I2(b[4]),
.I3(a[2]),
.O(\blk00000001/sig0000013c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001b9 (
.I0(b[4]),
.I1(a[3]),
.I2(b[5]),
.I3(a[2]),
.O(\blk00000001/sig00000133 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001b8 (
.I0(b[5]),
.I1(a[3]),
.I2(b[6]),
.I3(a[2]),
.O(\blk00000001/sig0000012a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001b7 (
.I0(b[6]),
.I1(a[3]),
.I2(b[7]),
.I3(a[2]),
.O(\blk00000001/sig00000121 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001b6 (
.I0(b[7]),
.I1(a[3]),
.I2(b[8]),
.I3(a[2]),
.O(\blk00000001/sig00000118 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001b5 (
.I0(b[8]),
.I1(a[3]),
.I2(b[9]),
.I3(a[2]),
.O(\blk00000001/sig0000010f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001b4 (
.I0(b[10]),
.I1(a[4]),
.I2(b[9]),
.I3(a[5]),
.O(\blk00000001/sig00000104 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001b3 (
.I0(b[10]),
.I1(a[5]),
.I2(b[11]),
.I3(a[4]),
.O(\blk00000001/sig000000fb )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000001b2 (
.I0(b[11]),
.I1(a[5]),
.I2(a[4]),
.O(\blk00000001/sig000000f2 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000001b1 (
.I0(b[11]),
.I1(a[5]),
.I2(a[4]),
.O(\blk00000001/sig000000eb )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001b0 (
.I0(b[0]),
.I1(a[5]),
.I2(b[1]),
.I3(a[4]),
.O(\blk00000001/sig00000157 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001af (
.I0(b[1]),
.I1(a[5]),
.I2(b[2]),
.I3(a[4]),
.O(\blk00000001/sig0000014c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001ae (
.I0(b[2]),
.I1(a[5]),
.I2(b[3]),
.I3(a[4]),
.O(\blk00000001/sig00000143 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001ad (
.I0(b[3]),
.I1(a[5]),
.I2(b[4]),
.I3(a[4]),
.O(\blk00000001/sig0000013a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001ac (
.I0(b[4]),
.I1(a[5]),
.I2(b[5]),
.I3(a[4]),
.O(\blk00000001/sig00000131 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001ab (
.I0(b[5]),
.I1(a[5]),
.I2(b[6]),
.I3(a[4]),
.O(\blk00000001/sig00000128 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001aa (
.I0(b[6]),
.I1(a[5]),
.I2(b[7]),
.I3(a[4]),
.O(\blk00000001/sig0000011f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001a9 (
.I0(b[7]),
.I1(a[5]),
.I2(b[8]),
.I3(a[4]),
.O(\blk00000001/sig00000116 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001a8 (
.I0(b[8]),
.I1(a[5]),
.I2(b[9]),
.I3(a[4]),
.O(\blk00000001/sig0000010d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001a7 (
.I0(b[10]),
.I1(a[6]),
.I2(b[9]),
.I3(a[7]),
.O(\blk00000001/sig00000102 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001a6 (
.I0(b[10]),
.I1(a[7]),
.I2(b[11]),
.I3(a[6]),
.O(\blk00000001/sig000000f9 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000001a5 (
.I0(b[11]),
.I1(a[7]),
.I2(a[6]),
.O(\blk00000001/sig000000f0 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000001a4 (
.I0(b[11]),
.I1(a[7]),
.I2(a[6]),
.O(\blk00000001/sig000000ea )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001a3 (
.I0(b[0]),
.I1(a[7]),
.I2(b[1]),
.I3(a[6]),
.O(\blk00000001/sig00000154 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001a2 (
.I0(b[1]),
.I1(a[7]),
.I2(b[2]),
.I3(a[6]),
.O(\blk00000001/sig0000014a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001a1 (
.I0(b[2]),
.I1(a[7]),
.I2(b[3]),
.I3(a[6]),
.O(\blk00000001/sig00000141 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000001a0 (
.I0(b[3]),
.I1(a[7]),
.I2(b[4]),
.I3(a[6]),
.O(\blk00000001/sig00000138 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000019f (
.I0(b[4]),
.I1(a[7]),
.I2(b[5]),
.I3(a[6]),
.O(\blk00000001/sig0000012f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000019e (
.I0(b[5]),
.I1(a[7]),
.I2(b[6]),
.I3(a[6]),
.O(\blk00000001/sig00000126 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000019d (
.I0(b[6]),
.I1(a[7]),
.I2(b[7]),
.I3(a[6]),
.O(\blk00000001/sig0000011d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000019c (
.I0(b[7]),
.I1(a[7]),
.I2(b[8]),
.I3(a[6]),
.O(\blk00000001/sig00000114 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000019b (
.I0(b[8]),
.I1(a[7]),
.I2(b[9]),
.I3(a[6]),
.O(\blk00000001/sig0000010b )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk0000019a (
.I0(a[9]),
.I1(b[9]),
.I2(a[8]),
.I3(b[10]),
.O(\blk00000001/sig000000c3 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000199 (
.I0(a[8]),
.I1(b[5]),
.I2(a[9]),
.I3(b[4]),
.O(\blk00000001/sig000000c8 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000198 (
.I0(b[1]),
.I1(a[8]),
.I2(a[9]),
.I3(b[0]),
.O(\blk00000001/sig000000cc )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000197 (
.I0(b[2]),
.I1(a[8]),
.I2(a[9]),
.I3(b[1]),
.O(\blk00000001/sig000000cb )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000196 (
.I0(b[3]),
.I1(a[8]),
.I2(a[9]),
.I3(b[2]),
.O(\blk00000001/sig000000ca )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000195 (
.I0(b[4]),
.I1(a[8]),
.I2(a[9]),
.I3(b[3]),
.O(\blk00000001/sig000000c9 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000194 (
.I0(b[6]),
.I1(a[8]),
.I2(a[9]),
.I3(b[5]),
.O(\blk00000001/sig000000c7 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000193 (
.I0(b[7]),
.I1(a[8]),
.I2(a[9]),
.I3(b[6]),
.O(\blk00000001/sig000000c6 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000192 (
.I0(b[8]),
.I1(a[8]),
.I2(a[9]),
.I3(b[7]),
.O(\blk00000001/sig000000c5 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000191 (
.I0(b[9]),
.I1(a[8]),
.I2(a[9]),
.I3(b[8]),
.O(\blk00000001/sig000000c4 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk00000190 (
.I0(b[11]),
.I1(a[8]),
.I2(a[9]),
.I3(b[10]),
.O(\blk00000001/sig000000c2 )
);
LUT3 #(
.INIT ( 8'h9F ))
\blk00000001/blk0000018f (
.I0(a[9]),
.I1(a[8]),
.I2(b[11]),
.O(\blk00000001/sig000000c1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018e (
.C(clk),
.D(\blk00000001/sig000001a3 ),
.Q(p[0])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018d (
.C(clk),
.D(\blk00000001/sig0000015e ),
.Q(p[1])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018c (
.C(clk),
.D(\blk00000001/sig000000db ),
.Q(p[2])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018b (
.C(clk),
.D(\blk00000001/sig000000dc ),
.Q(p[3])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018a (
.C(clk),
.D(\blk00000001/sig000000b0 ),
.Q(p[4])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000189 (
.C(clk),
.D(\blk00000001/sig000000b1 ),
.Q(p[5])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000188 (
.C(clk),
.D(\blk00000001/sig000000b2 ),
.Q(p[6])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000187 (
.C(clk),
.D(\blk00000001/sig000000b3 ),
.Q(p[7])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000186 (
.C(clk),
.D(\blk00000001/sig000000a2 ),
.Q(p[8])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000185 (
.C(clk),
.D(\blk00000001/sig000000a3 ),
.Q(p[9])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000184 (
.C(clk),
.D(\blk00000001/sig000000a4 ),
.Q(p[10])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000183 (
.C(clk),
.D(\blk00000001/sig000000a5 ),
.Q(p[11])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000182 (
.C(clk),
.D(\blk00000001/sig000000a6 ),
.Q(p[12])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000181 (
.C(clk),
.D(\blk00000001/sig000000a7 ),
.Q(p[13])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000180 (
.C(clk),
.D(\blk00000001/sig000000a8 ),
.Q(p[14])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017f (
.C(clk),
.D(\blk00000001/sig000000a9 ),
.Q(p[15])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017e (
.C(clk),
.D(\blk00000001/sig000000aa ),
.Q(p[16])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017d (
.C(clk),
.D(\blk00000001/sig000000ab ),
.Q(p[17])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017c (
.C(clk),
.D(\blk00000001/sig000000ac ),
.Q(p[18])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017b (
.C(clk),
.D(\blk00000001/sig000000ad ),
.Q(p[19])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017a (
.C(clk),
.D(\blk00000001/sig000000ae ),
.Q(p[20])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000179 (
.C(clk),
.D(\blk00000001/sig000000af ),
.Q(p[21])
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000178 (
.I0(\blk00000001/sig0000015c ),
.I1(\blk00000001/sig000001a0 ),
.O(\blk00000001/sig000000a1 )
);
MUXCY \blk00000001/blk00000177 (
.CI(\blk00000001/sig0000002f ),
.DI(\blk00000001/sig0000015c ),
.S(\blk00000001/sig000000a1 ),
.O(\blk00000001/sig000000a0 )
);
XORCY \blk00000001/blk00000176 (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig000000a1 ),
.O(\blk00000001/sig000000db )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000175 (
.I0(\blk00000001/sig0000014f ),
.I1(\blk00000001/sig0000015b ),
.O(\blk00000001/sig0000009f )
);
MUXCY \blk00000001/blk00000174 (
.CI(\blk00000001/sig000000a0 ),
.DI(\blk00000001/sig0000014f ),
.S(\blk00000001/sig0000009f ),
.O(\blk00000001/sig0000009e )
);
XORCY \blk00000001/blk00000173 (
.CI(\blk00000001/sig000000a0 ),
.LI(\blk00000001/sig0000009f ),
.O(\blk00000001/sig000000dc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000172 (
.I0(\blk00000001/sig00000146 ),
.I1(\blk00000001/sig00000159 ),
.O(\blk00000001/sig0000009d )
);
MUXCY \blk00000001/blk00000171 (
.CI(\blk00000001/sig0000009e ),
.DI(\blk00000001/sig00000146 ),
.S(\blk00000001/sig0000009d ),
.O(\blk00000001/sig0000009c )
);
XORCY \blk00000001/blk00000170 (
.CI(\blk00000001/sig0000009e ),
.LI(\blk00000001/sig0000009d ),
.O(\blk00000001/sig000000dd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000016f (
.I0(\blk00000001/sig0000013d ),
.I1(\blk00000001/sig0000014d ),
.O(\blk00000001/sig0000009b )
);
MUXCY \blk00000001/blk0000016e (
.CI(\blk00000001/sig0000009c ),
.DI(\blk00000001/sig0000013d ),
.S(\blk00000001/sig0000009b ),
.O(\blk00000001/sig0000009a )
);
XORCY \blk00000001/blk0000016d (
.CI(\blk00000001/sig0000009c ),
.LI(\blk00000001/sig0000009b ),
.O(\blk00000001/sig000000de )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000016c (
.I0(\blk00000001/sig00000134 ),
.I1(\blk00000001/sig00000144 ),
.O(\blk00000001/sig00000099 )
);
MUXCY \blk00000001/blk0000016b (
.CI(\blk00000001/sig0000009a ),
.DI(\blk00000001/sig00000134 ),
.S(\blk00000001/sig00000099 ),
.O(\blk00000001/sig00000098 )
);
XORCY \blk00000001/blk0000016a (
.CI(\blk00000001/sig0000009a ),
.LI(\blk00000001/sig00000099 ),
.O(\blk00000001/sig000000df )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000169 (
.I0(\blk00000001/sig0000012b ),
.I1(\blk00000001/sig0000013b ),
.O(\blk00000001/sig00000097 )
);
MUXCY \blk00000001/blk00000168 (
.CI(\blk00000001/sig00000098 ),
.DI(\blk00000001/sig0000012b ),
.S(\blk00000001/sig00000097 ),
.O(\blk00000001/sig00000096 )
);
XORCY \blk00000001/blk00000167 (
.CI(\blk00000001/sig00000098 ),
.LI(\blk00000001/sig00000097 ),
.O(\blk00000001/sig000000e0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000166 (
.I0(\blk00000001/sig00000122 ),
.I1(\blk00000001/sig00000132 ),
.O(\blk00000001/sig00000095 )
);
MUXCY \blk00000001/blk00000165 (
.CI(\blk00000001/sig00000096 ),
.DI(\blk00000001/sig00000122 ),
.S(\blk00000001/sig00000095 ),
.O(\blk00000001/sig00000094 )
);
XORCY \blk00000001/blk00000164 (
.CI(\blk00000001/sig00000096 ),
.LI(\blk00000001/sig00000095 ),
.O(\blk00000001/sig000000e1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000163 (
.I0(\blk00000001/sig00000119 ),
.I1(\blk00000001/sig00000129 ),
.O(\blk00000001/sig00000093 )
);
MUXCY \blk00000001/blk00000162 (
.CI(\blk00000001/sig00000094 ),
.DI(\blk00000001/sig00000119 ),
.S(\blk00000001/sig00000093 ),
.O(\blk00000001/sig00000092 )
);
XORCY \blk00000001/blk00000161 (
.CI(\blk00000001/sig00000094 ),
.LI(\blk00000001/sig00000093 ),
.O(\blk00000001/sig000000e2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000160 (
.I0(\blk00000001/sig00000110 ),
.I1(\blk00000001/sig00000120 ),
.O(\blk00000001/sig00000091 )
);
MUXCY \blk00000001/blk0000015f (
.CI(\blk00000001/sig00000092 ),
.DI(\blk00000001/sig00000110 ),
.S(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000090 )
);
XORCY \blk00000001/blk0000015e (
.CI(\blk00000001/sig00000092 ),
.LI(\blk00000001/sig00000091 ),
.O(\blk00000001/sig000000e3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000015d (
.I0(\blk00000001/sig00000107 ),
.I1(\blk00000001/sig00000117 ),
.O(\blk00000001/sig0000008f )
);
MUXCY \blk00000001/blk0000015c (
.CI(\blk00000001/sig00000090 ),
.DI(\blk00000001/sig00000107 ),
.S(\blk00000001/sig0000008f ),
.O(\blk00000001/sig0000008e )
);
XORCY \blk00000001/blk0000015b (
.CI(\blk00000001/sig00000090 ),
.LI(\blk00000001/sig0000008f ),
.O(\blk00000001/sig000000e4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000015a (
.I0(\blk00000001/sig000000fe ),
.I1(\blk00000001/sig0000010e ),
.O(\blk00000001/sig0000008d )
);
MUXCY \blk00000001/blk00000159 (
.CI(\blk00000001/sig0000008e ),
.DI(\blk00000001/sig000000fe ),
.S(\blk00000001/sig0000008d ),
.O(\blk00000001/sig0000008c )
);
XORCY \blk00000001/blk00000158 (
.CI(\blk00000001/sig0000008e ),
.LI(\blk00000001/sig0000008d ),
.O(\blk00000001/sig000000e5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000157 (
.I0(\blk00000001/sig000000f5 ),
.I1(\blk00000001/sig00000105 ),
.O(\blk00000001/sig0000008b )
);
MUXCY \blk00000001/blk00000156 (
.CI(\blk00000001/sig0000008c ),
.DI(\blk00000001/sig000000f5 ),
.S(\blk00000001/sig0000008b ),
.O(\blk00000001/sig0000008a )
);
XORCY \blk00000001/blk00000155 (
.CI(\blk00000001/sig0000008c ),
.LI(\blk00000001/sig0000008b ),
.O(\blk00000001/sig000000e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000154 (
.I0(\blk00000001/sig000000f5 ),
.I1(\blk00000001/sig000000fc ),
.O(\blk00000001/sig00000089 )
);
MUXCY \blk00000001/blk00000153 (
.CI(\blk00000001/sig0000008a ),
.DI(\blk00000001/sig000000f5 ),
.S(\blk00000001/sig00000089 ),
.O(\blk00000001/sig00000088 )
);
XORCY \blk00000001/blk00000152 (
.CI(\blk00000001/sig0000008a ),
.LI(\blk00000001/sig00000089 ),
.O(\blk00000001/sig000000e7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000151 (
.I0(\blk00000001/sig000000f5 ),
.I1(\blk00000001/sig000000f3 ),
.O(\blk00000001/sig00000087 )
);
XORCY \blk00000001/blk00000150 (
.CI(\blk00000001/sig00000088 ),
.LI(\blk00000001/sig00000087 ),
.O(\blk00000001/sig000000e8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000014f (
.I0(\blk00000001/sig00000156 ),
.I1(\blk00000001/sig0000019a ),
.O(\blk00000001/sig00000086 )
);
MUXCY \blk00000001/blk0000014e (
.CI(\blk00000001/sig0000002f ),
.DI(\blk00000001/sig00000156 ),
.S(\blk00000001/sig00000086 ),
.O(\blk00000001/sig00000085 )
);
XORCY \blk00000001/blk0000014d (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig00000086 ),
.O(\blk00000001/sig000000cd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000014c (
.I0(\blk00000001/sig0000014b ),
.I1(\blk00000001/sig00000155 ),
.O(\blk00000001/sig00000084 )
);
MUXCY \blk00000001/blk0000014b (
.CI(\blk00000001/sig00000085 ),
.DI(\blk00000001/sig0000014b ),
.S(\blk00000001/sig00000084 ),
.O(\blk00000001/sig00000083 )
);
XORCY \blk00000001/blk0000014a (
.CI(\blk00000001/sig00000085 ),
.LI(\blk00000001/sig00000084 ),
.O(\blk00000001/sig000000ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000149 (
.I0(\blk00000001/sig00000142 ),
.I1(\blk00000001/sig00000153 ),
.O(\blk00000001/sig00000082 )
);
MUXCY \blk00000001/blk00000148 (
.CI(\blk00000001/sig00000083 ),
.DI(\blk00000001/sig00000142 ),
.S(\blk00000001/sig00000082 ),
.O(\blk00000001/sig00000081 )
);
XORCY \blk00000001/blk00000147 (
.CI(\blk00000001/sig00000083 ),
.LI(\blk00000001/sig00000082 ),
.O(\blk00000001/sig000000cf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000146 (
.I0(\blk00000001/sig00000139 ),
.I1(\blk00000001/sig00000149 ),
.O(\blk00000001/sig00000080 )
);
MUXCY \blk00000001/blk00000145 (
.CI(\blk00000001/sig00000081 ),
.DI(\blk00000001/sig00000139 ),
.S(\blk00000001/sig00000080 ),
.O(\blk00000001/sig0000007f )
);
XORCY \blk00000001/blk00000144 (
.CI(\blk00000001/sig00000081 ),
.LI(\blk00000001/sig00000080 ),
.O(\blk00000001/sig000000d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000143 (
.I0(\blk00000001/sig00000130 ),
.I1(\blk00000001/sig00000140 ),
.O(\blk00000001/sig0000007e )
);
MUXCY \blk00000001/blk00000142 (
.CI(\blk00000001/sig0000007f ),
.DI(\blk00000001/sig00000130 ),
.S(\blk00000001/sig0000007e ),
.O(\blk00000001/sig0000007d )
);
XORCY \blk00000001/blk00000141 (
.CI(\blk00000001/sig0000007f ),
.LI(\blk00000001/sig0000007e ),
.O(\blk00000001/sig000000d1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000140 (
.I0(\blk00000001/sig00000127 ),
.I1(\blk00000001/sig00000137 ),
.O(\blk00000001/sig0000007c )
);
MUXCY \blk00000001/blk0000013f (
.CI(\blk00000001/sig0000007d ),
.DI(\blk00000001/sig00000127 ),
.S(\blk00000001/sig0000007c ),
.O(\blk00000001/sig0000007b )
);
XORCY \blk00000001/blk0000013e (
.CI(\blk00000001/sig0000007d ),
.LI(\blk00000001/sig0000007c ),
.O(\blk00000001/sig000000d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000013d (
.I0(\blk00000001/sig0000011e ),
.I1(\blk00000001/sig0000012e ),
.O(\blk00000001/sig0000007a )
);
MUXCY \blk00000001/blk0000013c (
.CI(\blk00000001/sig0000007b ),
.DI(\blk00000001/sig0000011e ),
.S(\blk00000001/sig0000007a ),
.O(\blk00000001/sig00000079 )
);
XORCY \blk00000001/blk0000013b (
.CI(\blk00000001/sig0000007b ),
.LI(\blk00000001/sig0000007a ),
.O(\blk00000001/sig000000d3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000013a (
.I0(\blk00000001/sig00000115 ),
.I1(\blk00000001/sig00000125 ),
.O(\blk00000001/sig00000078 )
);
MUXCY \blk00000001/blk00000139 (
.CI(\blk00000001/sig00000079 ),
.DI(\blk00000001/sig00000115 ),
.S(\blk00000001/sig00000078 ),
.O(\blk00000001/sig00000077 )
);
XORCY \blk00000001/blk00000138 (
.CI(\blk00000001/sig00000079 ),
.LI(\blk00000001/sig00000078 ),
.O(\blk00000001/sig000000d4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000137 (
.I0(\blk00000001/sig0000010c ),
.I1(\blk00000001/sig0000011c ),
.O(\blk00000001/sig00000076 )
);
MUXCY \blk00000001/blk00000136 (
.CI(\blk00000001/sig00000077 ),
.DI(\blk00000001/sig0000010c ),
.S(\blk00000001/sig00000076 ),
.O(\blk00000001/sig00000075 )
);
XORCY \blk00000001/blk00000135 (
.CI(\blk00000001/sig00000077 ),
.LI(\blk00000001/sig00000076 ),
.O(\blk00000001/sig000000d5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000134 (
.I0(\blk00000001/sig00000103 ),
.I1(\blk00000001/sig00000113 ),
.O(\blk00000001/sig00000074 )
);
MUXCY \blk00000001/blk00000133 (
.CI(\blk00000001/sig00000075 ),
.DI(\blk00000001/sig00000103 ),
.S(\blk00000001/sig00000074 ),
.O(\blk00000001/sig00000073 )
);
XORCY \blk00000001/blk00000132 (
.CI(\blk00000001/sig00000075 ),
.LI(\blk00000001/sig00000074 ),
.O(\blk00000001/sig000000d6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000131 (
.I0(\blk00000001/sig000000fa ),
.I1(\blk00000001/sig0000010a ),
.O(\blk00000001/sig00000072 )
);
MUXCY \blk00000001/blk00000130 (
.CI(\blk00000001/sig00000073 ),
.DI(\blk00000001/sig000000fa ),
.S(\blk00000001/sig00000072 ),
.O(\blk00000001/sig00000071 )
);
XORCY \blk00000001/blk0000012f (
.CI(\blk00000001/sig00000073 ),
.LI(\blk00000001/sig00000072 ),
.O(\blk00000001/sig000000d7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000012e (
.I0(\blk00000001/sig000000f1 ),
.I1(\blk00000001/sig00000101 ),
.O(\blk00000001/sig00000070 )
);
MUXCY \blk00000001/blk0000012d (
.CI(\blk00000001/sig00000071 ),
.DI(\blk00000001/sig000000f1 ),
.S(\blk00000001/sig00000070 ),
.O(\blk00000001/sig0000006f )
);
XORCY \blk00000001/blk0000012c (
.CI(\blk00000001/sig00000071 ),
.LI(\blk00000001/sig00000070 ),
.O(\blk00000001/sig000000d8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000012b (
.I0(\blk00000001/sig000000f1 ),
.I1(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig0000006e )
);
MUXCY \blk00000001/blk0000012a (
.CI(\blk00000001/sig0000006f ),
.DI(\blk00000001/sig000000f1 ),
.S(\blk00000001/sig0000006e ),
.O(\blk00000001/sig0000006d )
);
XORCY \blk00000001/blk00000129 (
.CI(\blk00000001/sig0000006f ),
.LI(\blk00000001/sig0000006e ),
.O(\blk00000001/sig000000d9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000128 (
.I0(\blk00000001/sig000000f1 ),
.I1(\blk00000001/sig000000ef ),
.O(\blk00000001/sig0000006c )
);
XORCY \blk00000001/blk00000127 (
.CI(\blk00000001/sig0000006d ),
.LI(\blk00000001/sig0000006c ),
.O(\blk00000001/sig000000da )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000126 (
.I0(\blk00000001/sig000000dd ),
.I1(\blk00000001/sig0000019d ),
.O(\blk00000001/sig0000006b )
);
MUXCY \blk00000001/blk00000125 (
.CI(\blk00000001/sig0000002f ),
.DI(\blk00000001/sig000000dd ),
.S(\blk00000001/sig0000006b ),
.O(\blk00000001/sig0000006a )
);
XORCY \blk00000001/blk00000124 (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig0000006b ),
.O(\blk00000001/sig000000b0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000123 (
.I0(\blk00000001/sig000000de ),
.I1(\blk00000001/sig00000158 ),
.O(\blk00000001/sig00000069 )
);
MUXCY \blk00000001/blk00000122 (
.CI(\blk00000001/sig0000006a ),
.DI(\blk00000001/sig000000de ),
.S(\blk00000001/sig00000069 ),
.O(\blk00000001/sig00000068 )
);
XORCY \blk00000001/blk00000121 (
.CI(\blk00000001/sig0000006a ),
.LI(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000000b1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000120 (
.I0(\blk00000001/sig000000df ),
.I1(\blk00000001/sig000000cd ),
.O(\blk00000001/sig00000067 )
);
MUXCY \blk00000001/blk0000011f (
.CI(\blk00000001/sig00000068 ),
.DI(\blk00000001/sig000000df ),
.S(\blk00000001/sig00000067 ),
.O(\blk00000001/sig00000066 )
);
XORCY \blk00000001/blk0000011e (
.CI(\blk00000001/sig00000068 ),
.LI(\blk00000001/sig00000067 ),
.O(\blk00000001/sig000000b2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000011d (
.I0(\blk00000001/sig000000e0 ),
.I1(\blk00000001/sig000000ce ),
.O(\blk00000001/sig00000065 )
);
MUXCY \blk00000001/blk0000011c (
.CI(\blk00000001/sig00000066 ),
.DI(\blk00000001/sig000000e0 ),
.S(\blk00000001/sig00000065 ),
.O(\blk00000001/sig00000064 )
);
XORCY \blk00000001/blk0000011b (
.CI(\blk00000001/sig00000066 ),
.LI(\blk00000001/sig00000065 ),
.O(\blk00000001/sig000000b3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000011a (
.I0(\blk00000001/sig000000e1 ),
.I1(\blk00000001/sig000000cf ),
.O(\blk00000001/sig00000063 )
);
MUXCY \blk00000001/blk00000119 (
.CI(\blk00000001/sig00000064 ),
.DI(\blk00000001/sig000000e1 ),
.S(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000062 )
);
XORCY \blk00000001/blk00000118 (
.CI(\blk00000001/sig00000064 ),
.LI(\blk00000001/sig00000063 ),
.O(\blk00000001/sig000000b4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000117 (
.I0(\blk00000001/sig000000e2 ),
.I1(\blk00000001/sig000000d0 ),
.O(\blk00000001/sig00000061 )
);
MUXCY \blk00000001/blk00000116 (
.CI(\blk00000001/sig00000062 ),
.DI(\blk00000001/sig000000e2 ),
.S(\blk00000001/sig00000061 ),
.O(\blk00000001/sig00000060 )
);
XORCY \blk00000001/blk00000115 (
.CI(\blk00000001/sig00000062 ),
.LI(\blk00000001/sig00000061 ),
.O(\blk00000001/sig000000b5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000114 (
.I0(\blk00000001/sig000000e3 ),
.I1(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig0000005f )
);
MUXCY \blk00000001/blk00000113 (
.CI(\blk00000001/sig00000060 ),
.DI(\blk00000001/sig000000e3 ),
.S(\blk00000001/sig0000005f ),
.O(\blk00000001/sig0000005e )
);
XORCY \blk00000001/blk00000112 (
.CI(\blk00000001/sig00000060 ),
.LI(\blk00000001/sig0000005f ),
.O(\blk00000001/sig000000b6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000111 (
.I0(\blk00000001/sig000000e4 ),
.I1(\blk00000001/sig000000d2 ),
.O(\blk00000001/sig0000005d )
);
MUXCY \blk00000001/blk00000110 (
.CI(\blk00000001/sig0000005e ),
.DI(\blk00000001/sig000000e4 ),
.S(\blk00000001/sig0000005d ),
.O(\blk00000001/sig0000005c )
);
XORCY \blk00000001/blk0000010f (
.CI(\blk00000001/sig0000005e ),
.LI(\blk00000001/sig0000005d ),
.O(\blk00000001/sig000000b7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000010e (
.I0(\blk00000001/sig000000e5 ),
.I1(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig0000005b )
);
MUXCY \blk00000001/blk0000010d (
.CI(\blk00000001/sig0000005c ),
.DI(\blk00000001/sig000000e5 ),
.S(\blk00000001/sig0000005b ),
.O(\blk00000001/sig0000005a )
);
XORCY \blk00000001/blk0000010c (
.CI(\blk00000001/sig0000005c ),
.LI(\blk00000001/sig0000005b ),
.O(\blk00000001/sig000000b8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000010b (
.I0(\blk00000001/sig000000e6 ),
.I1(\blk00000001/sig000000d4 ),
.O(\blk00000001/sig00000059 )
);
MUXCY \blk00000001/blk0000010a (
.CI(\blk00000001/sig0000005a ),
.DI(\blk00000001/sig000000e6 ),
.S(\blk00000001/sig00000059 ),
.O(\blk00000001/sig00000058 )
);
XORCY \blk00000001/blk00000109 (
.CI(\blk00000001/sig0000005a ),
.LI(\blk00000001/sig00000059 ),
.O(\blk00000001/sig000000b9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000108 (
.I0(\blk00000001/sig000000e7 ),
.I1(\blk00000001/sig000000d5 ),
.O(\blk00000001/sig00000057 )
);
MUXCY \blk00000001/blk00000107 (
.CI(\blk00000001/sig00000058 ),
.DI(\blk00000001/sig000000e7 ),
.S(\blk00000001/sig00000057 ),
.O(\blk00000001/sig00000056 )
);
XORCY \blk00000001/blk00000106 (
.CI(\blk00000001/sig00000058 ),
.LI(\blk00000001/sig00000057 ),
.O(\blk00000001/sig000000ba )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000105 (
.I0(\blk00000001/sig000000e8 ),
.I1(\blk00000001/sig000000d6 ),
.O(\blk00000001/sig00000055 )
);
MUXCY \blk00000001/blk00000104 (
.CI(\blk00000001/sig00000056 ),
.DI(\blk00000001/sig000000e8 ),
.S(\blk00000001/sig00000055 ),
.O(\blk00000001/sig00000054 )
);
XORCY \blk00000001/blk00000103 (
.CI(\blk00000001/sig00000056 ),
.LI(\blk00000001/sig00000055 ),
.O(\blk00000001/sig000000bb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000102 (
.I0(\blk00000001/sig000000e8 ),
.I1(\blk00000001/sig000000d7 ),
.O(\blk00000001/sig00000053 )
);
MUXCY \blk00000001/blk00000101 (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig000000e8 ),
.S(\blk00000001/sig00000053 ),
.O(\blk00000001/sig00000052 )
);
XORCY \blk00000001/blk00000100 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig00000053 ),
.O(\blk00000001/sig000000bc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ff (
.I0(\blk00000001/sig000000e8 ),
.I1(\blk00000001/sig000000d8 ),
.O(\blk00000001/sig00000051 )
);
MUXCY \blk00000001/blk000000fe (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig000000e8 ),
.S(\blk00000001/sig00000051 ),
.O(\blk00000001/sig00000050 )
);
XORCY \blk00000001/blk000000fd (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig00000051 ),
.O(\blk00000001/sig000000bd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000fc (
.I0(\blk00000001/sig000000e8 ),
.I1(\blk00000001/sig000000d9 ),
.O(\blk00000001/sig0000004f )
);
MUXCY \blk00000001/blk000000fb (
.CI(\blk00000001/sig00000050 ),
.DI(\blk00000001/sig000000e8 ),
.S(\blk00000001/sig0000004f ),
.O(\blk00000001/sig0000004e )
);
XORCY \blk00000001/blk000000fa (
.CI(\blk00000001/sig00000050 ),
.LI(\blk00000001/sig0000004f ),
.O(\blk00000001/sig000000be )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f9 (
.I0(\blk00000001/sig000000e8 ),
.I1(\blk00000001/sig000000da ),
.O(\blk00000001/sig0000004d )
);
MUXCY \blk00000001/blk000000f8 (
.CI(\blk00000001/sig0000004e ),
.DI(\blk00000001/sig000000e8 ),
.S(\blk00000001/sig0000004d ),
.O(\blk00000001/sig0000004c )
);
XORCY \blk00000001/blk000000f7 (
.CI(\blk00000001/sig0000004e ),
.LI(\blk00000001/sig0000004d ),
.O(\blk00000001/sig000000bf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f6 (
.I0(\blk00000001/sig000000e8 ),
.I1(\blk00000001/sig000000da ),
.O(\blk00000001/sig0000004b )
);
XORCY \blk00000001/blk000000f5 (
.CI(\blk00000001/sig0000004c ),
.LI(\blk00000001/sig0000004b ),
.O(\blk00000001/sig000000c0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f4 (
.I0(\blk00000001/sig000000b4 ),
.I1(\blk00000001/sig00000152 ),
.O(\blk00000001/sig0000004a )
);
MUXCY \blk00000001/blk000000f3 (
.CI(\blk00000001/sig0000002f ),
.DI(\blk00000001/sig000000b4 ),
.S(\blk00000001/sig0000004a ),
.O(\blk00000001/sig00000049 )
);
XORCY \blk00000001/blk000000f2 (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig0000004a ),
.O(\blk00000001/sig000000a2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f1 (
.I0(\blk00000001/sig000000b5 ),
.I1(\blk00000001/sig00000151 ),
.O(\blk00000001/sig00000048 )
);
MUXCY \blk00000001/blk000000f0 (
.CI(\blk00000001/sig00000049 ),
.DI(\blk00000001/sig000000b5 ),
.S(\blk00000001/sig00000048 ),
.O(\blk00000001/sig00000047 )
);
XORCY \blk00000001/blk000000ef (
.CI(\blk00000001/sig00000049 ),
.LI(\blk00000001/sig00000048 ),
.O(\blk00000001/sig000000a3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ee (
.I0(\blk00000001/sig000000b6 ),
.I1(\blk00000001/sig00000148 ),
.O(\blk00000001/sig00000046 )
);
MUXCY \blk00000001/blk000000ed (
.CI(\blk00000001/sig00000047 ),
.DI(\blk00000001/sig000000b6 ),
.S(\blk00000001/sig00000046 ),
.O(\blk00000001/sig00000045 )
);
XORCY \blk00000001/blk000000ec (
.CI(\blk00000001/sig00000047 ),
.LI(\blk00000001/sig00000046 ),
.O(\blk00000001/sig000000a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000eb (
.I0(\blk00000001/sig000000b7 ),
.I1(\blk00000001/sig0000013f ),
.O(\blk00000001/sig00000044 )
);
MUXCY \blk00000001/blk000000ea (
.CI(\blk00000001/sig00000045 ),
.DI(\blk00000001/sig000000b7 ),
.S(\blk00000001/sig00000044 ),
.O(\blk00000001/sig00000043 )
);
XORCY \blk00000001/blk000000e9 (
.CI(\blk00000001/sig00000045 ),
.LI(\blk00000001/sig00000044 ),
.O(\blk00000001/sig000000a5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000e8 (
.I0(\blk00000001/sig000000b8 ),
.I1(\blk00000001/sig00000136 ),
.O(\blk00000001/sig00000042 )
);
MUXCY \blk00000001/blk000000e7 (
.CI(\blk00000001/sig00000043 ),
.DI(\blk00000001/sig000000b8 ),
.S(\blk00000001/sig00000042 ),
.O(\blk00000001/sig00000041 )
);
XORCY \blk00000001/blk000000e6 (
.CI(\blk00000001/sig00000043 ),
.LI(\blk00000001/sig00000042 ),
.O(\blk00000001/sig000000a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000e5 (
.I0(\blk00000001/sig000000b9 ),
.I1(\blk00000001/sig0000012d ),
.O(\blk00000001/sig00000040 )
);
MUXCY \blk00000001/blk000000e4 (
.CI(\blk00000001/sig00000041 ),
.DI(\blk00000001/sig000000b9 ),
.S(\blk00000001/sig00000040 ),
.O(\blk00000001/sig0000003f )
);
XORCY \blk00000001/blk000000e3 (
.CI(\blk00000001/sig00000041 ),
.LI(\blk00000001/sig00000040 ),
.O(\blk00000001/sig000000a7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000e2 (
.I0(\blk00000001/sig000000ba ),
.I1(\blk00000001/sig00000124 ),
.O(\blk00000001/sig0000003e )
);
MUXCY \blk00000001/blk000000e1 (
.CI(\blk00000001/sig0000003f ),
.DI(\blk00000001/sig000000ba ),
.S(\blk00000001/sig0000003e ),
.O(\blk00000001/sig0000003d )
);
XORCY \blk00000001/blk000000e0 (
.CI(\blk00000001/sig0000003f ),
.LI(\blk00000001/sig0000003e ),
.O(\blk00000001/sig000000a8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000df (
.I0(\blk00000001/sig000000bb ),
.I1(\blk00000001/sig0000011b ),
.O(\blk00000001/sig0000003c )
);
MUXCY \blk00000001/blk000000de (
.CI(\blk00000001/sig0000003d ),
.DI(\blk00000001/sig000000bb ),
.S(\blk00000001/sig0000003c ),
.O(\blk00000001/sig0000003b )
);
XORCY \blk00000001/blk000000dd (
.CI(\blk00000001/sig0000003d ),
.LI(\blk00000001/sig0000003c ),
.O(\blk00000001/sig000000a9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000dc (
.I0(\blk00000001/sig000000bc ),
.I1(\blk00000001/sig00000112 ),
.O(\blk00000001/sig0000003a )
);
MUXCY \blk00000001/blk000000db (
.CI(\blk00000001/sig0000003b ),
.DI(\blk00000001/sig000000bc ),
.S(\blk00000001/sig0000003a ),
.O(\blk00000001/sig00000039 )
);
XORCY \blk00000001/blk000000da (
.CI(\blk00000001/sig0000003b ),
.LI(\blk00000001/sig0000003a ),
.O(\blk00000001/sig000000aa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d9 (
.I0(\blk00000001/sig000000bd ),
.I1(\blk00000001/sig00000109 ),
.O(\blk00000001/sig00000038 )
);
MUXCY \blk00000001/blk000000d8 (
.CI(\blk00000001/sig00000039 ),
.DI(\blk00000001/sig000000bd ),
.S(\blk00000001/sig00000038 ),
.O(\blk00000001/sig00000037 )
);
XORCY \blk00000001/blk000000d7 (
.CI(\blk00000001/sig00000039 ),
.LI(\blk00000001/sig00000038 ),
.O(\blk00000001/sig000000ab )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d6 (
.I0(\blk00000001/sig000000be ),
.I1(\blk00000001/sig00000100 ),
.O(\blk00000001/sig00000036 )
);
MUXCY \blk00000001/blk000000d5 (
.CI(\blk00000001/sig00000037 ),
.DI(\blk00000001/sig000000be ),
.S(\blk00000001/sig00000036 ),
.O(\blk00000001/sig00000035 )
);
XORCY \blk00000001/blk000000d4 (
.CI(\blk00000001/sig00000037 ),
.LI(\blk00000001/sig00000036 ),
.O(\blk00000001/sig000000ac )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d3 (
.I0(\blk00000001/sig000000bf ),
.I1(\blk00000001/sig000000f7 ),
.O(\blk00000001/sig00000034 )
);
MUXCY \blk00000001/blk000000d2 (
.CI(\blk00000001/sig00000035 ),
.DI(\blk00000001/sig000000bf ),
.S(\blk00000001/sig00000034 ),
.O(\blk00000001/sig00000033 )
);
XORCY \blk00000001/blk000000d1 (
.CI(\blk00000001/sig00000035 ),
.LI(\blk00000001/sig00000034 ),
.O(\blk00000001/sig000000ad )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d0 (
.I0(\blk00000001/sig000000c0 ),
.I1(\blk00000001/sig000000ee ),
.O(\blk00000001/sig00000032 )
);
MUXCY \blk00000001/blk000000cf (
.CI(\blk00000001/sig00000033 ),
.DI(\blk00000001/sig000000c0 ),
.S(\blk00000001/sig00000032 ),
.O(\blk00000001/sig00000031 )
);
XORCY \blk00000001/blk000000ce (
.CI(\blk00000001/sig00000033 ),
.LI(\blk00000001/sig00000032 ),
.O(\blk00000001/sig000000ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000cd (
.I0(\blk00000001/sig000000c0 ),
.I1(\blk00000001/sig000000e9 ),
.O(\blk00000001/sig00000030 )
);
XORCY \blk00000001/blk000000cc (
.CI(\blk00000001/sig00000031 ),
.LI(\blk00000001/sig00000030 ),
.O(\blk00000001/sig000000af )
);
MULT_AND \blk00000001/blk000000cb (
.I0(a[0]),
.I1(b[0]),
.LO(\blk00000001/sig000001e8 )
);
MULT_AND \blk00000001/blk000000ca (
.I0(a[1]),
.I1(b[0]),
.LO(\blk00000001/sig000001e7 )
);
MULT_AND \blk00000001/blk000000c9 (
.I0(a[2]),
.I1(b[0]),
.LO(\blk00000001/sig000001e5 )
);
MULT_AND \blk00000001/blk000000c8 (
.I0(a[3]),
.I1(b[0]),
.LO(\blk00000001/sig000001e4 )
);
MULT_AND \blk00000001/blk000000c7 (
.I0(a[4]),
.I1(b[0]),
.LO(\blk00000001/sig000001e2 )
);
MULT_AND \blk00000001/blk000000c6 (
.I0(a[5]),
.I1(b[0]),
.LO(\blk00000001/sig000001e1 )
);
MULT_AND \blk00000001/blk000000c5 (
.I0(a[6]),
.I1(b[0]),
.LO(\blk00000001/sig000001df )
);
MULT_AND \blk00000001/blk000000c4 (
.I0(a[7]),
.I1(b[0]),
.LO(\blk00000001/sig000001de )
);
MULT_AND \blk00000001/blk000000c3 (
.I0(a[8]),
.I1(b[0]),
.LO(\blk00000001/sig000001dd )
);
MULT_AND \blk00000001/blk000000c2 (
.I0(a[1]),
.I1(b[1]),
.LO(\blk00000001/sig000001dc )
);
MULT_AND \blk00000001/blk000000c1 (
.I0(a[3]),
.I1(b[1]),
.LO(\blk00000001/sig000001db )
);
MULT_AND \blk00000001/blk000000c0 (
.I0(a[5]),
.I1(b[1]),
.LO(\blk00000001/sig000001da )
);
MULT_AND \blk00000001/blk000000bf (
.I0(a[7]),
.I1(b[1]),
.LO(\blk00000001/sig000001d9 )
);
MULT_AND \blk00000001/blk000000be (
.I0(a[8]),
.I1(b[1]),
.LO(\blk00000001/sig000001d8 )
);
MULT_AND \blk00000001/blk000000bd (
.I0(a[1]),
.I1(b[2]),
.LO(\blk00000001/sig000001d7 )
);
MULT_AND \blk00000001/blk000000bc (
.I0(a[3]),
.I1(b[2]),
.LO(\blk00000001/sig000001d6 )
);
MULT_AND \blk00000001/blk000000bb (
.I0(a[5]),
.I1(b[2]),
.LO(\blk00000001/sig000001d5 )
);
MULT_AND \blk00000001/blk000000ba (
.I0(a[7]),
.I1(b[2]),
.LO(\blk00000001/sig000001d4 )
);
MULT_AND \blk00000001/blk000000b9 (
.I0(a[8]),
.I1(b[2]),
.LO(\blk00000001/sig000001d3 )
);
MULT_AND \blk00000001/blk000000b8 (
.I0(a[1]),
.I1(b[3]),
.LO(\blk00000001/sig000001d2 )
);
MULT_AND \blk00000001/blk000000b7 (
.I0(a[3]),
.I1(b[3]),
.LO(\blk00000001/sig000001d1 )
);
MULT_AND \blk00000001/blk000000b6 (
.I0(a[5]),
.I1(b[3]),
.LO(\blk00000001/sig000001d0 )
);
MULT_AND \blk00000001/blk000000b5 (
.I0(a[7]),
.I1(b[3]),
.LO(\blk00000001/sig000001cf )
);
MULT_AND \blk00000001/blk000000b4 (
.I0(a[8]),
.I1(b[3]),
.LO(\blk00000001/sig000001ce )
);
MULT_AND \blk00000001/blk000000b3 (
.I0(a[1]),
.I1(b[4]),
.LO(\blk00000001/sig000001cd )
);
MULT_AND \blk00000001/blk000000b2 (
.I0(a[3]),
.I1(b[4]),
.LO(\blk00000001/sig000001cc )
);
MULT_AND \blk00000001/blk000000b1 (
.I0(a[5]),
.I1(b[4]),
.LO(\blk00000001/sig000001cb )
);
MULT_AND \blk00000001/blk000000b0 (
.I0(a[7]),
.I1(b[4]),
.LO(\blk00000001/sig000001ca )
);
MULT_AND \blk00000001/blk000000af (
.I0(a[8]),
.I1(b[4]),
.LO(\blk00000001/sig000001c9 )
);
MULT_AND \blk00000001/blk000000ae (
.I0(a[1]),
.I1(b[5]),
.LO(\blk00000001/sig000001c8 )
);
MULT_AND \blk00000001/blk000000ad (
.I0(a[3]),
.I1(b[5]),
.LO(\blk00000001/sig000001c7 )
);
MULT_AND \blk00000001/blk000000ac (
.I0(a[5]),
.I1(b[5]),
.LO(\blk00000001/sig000001c6 )
);
MULT_AND \blk00000001/blk000000ab (
.I0(a[7]),
.I1(b[5]),
.LO(\blk00000001/sig000001c5 )
);
MULT_AND \blk00000001/blk000000aa (
.I0(a[8]),
.I1(b[5]),
.LO(\blk00000001/sig000001c4 )
);
MULT_AND \blk00000001/blk000000a9 (
.I0(a[1]),
.I1(b[6]),
.LO(\blk00000001/sig000001c3 )
);
MULT_AND \blk00000001/blk000000a8 (
.I0(a[3]),
.I1(b[6]),
.LO(\blk00000001/sig000001c2 )
);
MULT_AND \blk00000001/blk000000a7 (
.I0(a[5]),
.I1(b[6]),
.LO(\blk00000001/sig000001c1 )
);
MULT_AND \blk00000001/blk000000a6 (
.I0(a[7]),
.I1(b[6]),
.LO(\blk00000001/sig000001c0 )
);
MULT_AND \blk00000001/blk000000a5 (
.I0(a[8]),
.I1(b[6]),
.LO(\blk00000001/sig000001bf )
);
MULT_AND \blk00000001/blk000000a4 (
.I0(a[1]),
.I1(b[7]),
.LO(\blk00000001/sig000001be )
);
MULT_AND \blk00000001/blk000000a3 (
.I0(a[3]),
.I1(b[7]),
.LO(\blk00000001/sig000001bd )
);
MULT_AND \blk00000001/blk000000a2 (
.I0(a[5]),
.I1(b[7]),
.LO(\blk00000001/sig000001bc )
);
MULT_AND \blk00000001/blk000000a1 (
.I0(a[7]),
.I1(b[7]),
.LO(\blk00000001/sig000001bb )
);
MULT_AND \blk00000001/blk000000a0 (
.I0(a[8]),
.I1(b[7]),
.LO(\blk00000001/sig000001ba )
);
MULT_AND \blk00000001/blk0000009f (
.I0(a[1]),
.I1(b[8]),
.LO(\blk00000001/sig000001b9 )
);
MULT_AND \blk00000001/blk0000009e (
.I0(a[3]),
.I1(b[8]),
.LO(\blk00000001/sig000001b8 )
);
MULT_AND \blk00000001/blk0000009d (
.I0(a[5]),
.I1(b[8]),
.LO(\blk00000001/sig000001b7 )
);
MULT_AND \blk00000001/blk0000009c (
.I0(a[7]),
.I1(b[8]),
.LO(\blk00000001/sig000001b6 )
);
MULT_AND \blk00000001/blk0000009b (
.I0(a[8]),
.I1(b[8]),
.LO(\blk00000001/sig000001b5 )
);
MULT_AND \blk00000001/blk0000009a (
.I0(a[1]),
.I1(b[9]),
.LO(\blk00000001/sig000001b4 )
);
MULT_AND \blk00000001/blk00000099 (
.I0(a[3]),
.I1(b[9]),
.LO(\blk00000001/sig000001b3 )
);
MULT_AND \blk00000001/blk00000098 (
.I0(a[5]),
.I1(b[9]),
.LO(\blk00000001/sig000001b2 )
);
MULT_AND \blk00000001/blk00000097 (
.I0(a[7]),
.I1(b[9]),
.LO(\blk00000001/sig000001b1 )
);
MULT_AND \blk00000001/blk00000096 (
.I0(a[8]),
.I1(b[9]),
.LO(\blk00000001/sig000001b0 )
);
MULT_AND \blk00000001/blk00000095 (
.I0(a[1]),
.I1(b[10]),
.LO(\blk00000001/sig000001af )
);
MULT_AND \blk00000001/blk00000094 (
.I0(a[3]),
.I1(b[10]),
.LO(\blk00000001/sig000001ae )
);
MULT_AND \blk00000001/blk00000093 (
.I0(a[5]),
.I1(b[10]),
.LO(\blk00000001/sig000001ad )
);
MULT_AND \blk00000001/blk00000092 (
.I0(a[7]),
.I1(b[10]),
.LO(\blk00000001/sig000001ac )
);
MULT_AND \blk00000001/blk00000091 (
.I0(a[8]),
.I1(b[10]),
.LO(\blk00000001/sig000001ab )
);
MULT_AND \blk00000001/blk00000090 (
.I0(a[1]),
.I1(b[11]),
.LO(\blk00000001/sig000001aa )
);
MULT_AND \blk00000001/blk0000008f (
.I0(a[3]),
.I1(b[11]),
.LO(\blk00000001/sig000001a9 )
);
MULT_AND \blk00000001/blk0000008e (
.I0(a[5]),
.I1(b[11]),
.LO(\blk00000001/sig000001a8 )
);
MULT_AND \blk00000001/blk0000008d (
.I0(a[7]),
.I1(b[11]),
.LO(\blk00000001/sig000001a7 )
);
MULT_AND \blk00000001/blk0000008c (
.I0(a[8]),
.I1(b[11]),
.LO(\blk00000001/sig000001a6 )
);
MULT_AND \blk00000001/blk0000008b (
.I0(a[8]),
.I1(b[11]),
.LO(\blk00000001/sig000001a5 )
);
MUXCY \blk00000001/blk0000008a (
.CI(\blk00000001/sig0000002f ),
.DI(\blk00000001/sig000001e8 ),
.S(\blk00000001/sig000001e9 ),
.O(\blk00000001/sig000001a4 )
);
XORCY \blk00000001/blk00000089 (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig000001e9 ),
.O(\blk00000001/sig000001a3 )
);
MUXCY \blk00000001/blk00000088 (
.CI(\blk00000001/sig000001a4 ),
.DI(\blk00000001/sig000001e7 ),
.S(\blk00000001/sig0000015d ),
.O(\blk00000001/sig000001a2 )
);
MUXCY \blk00000001/blk00000087 (
.CI(\blk00000001/sig0000002f ),
.DI(\blk00000001/sig000001e5 ),
.S(\blk00000001/sig000001e6 ),
.O(\blk00000001/sig000001a1 )
);
XORCY \blk00000001/blk00000086 (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig000001e6 ),
.O(\blk00000001/sig000001a0 )
);
MUXCY \blk00000001/blk00000085 (
.CI(\blk00000001/sig000001a1 ),
.DI(\blk00000001/sig000001e4 ),
.S(\blk00000001/sig0000015a ),
.O(\blk00000001/sig0000019f )
);
MUXCY \blk00000001/blk00000084 (
.CI(\blk00000001/sig0000002f ),
.DI(\blk00000001/sig000001e2 ),
.S(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig0000019e )
);
XORCY \blk00000001/blk00000083 (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig0000019d )
);
MUXCY \blk00000001/blk00000082 (
.CI(\blk00000001/sig0000019e ),
.DI(\blk00000001/sig000001e1 ),
.S(\blk00000001/sig00000157 ),
.O(\blk00000001/sig0000019c )
);
MUXCY \blk00000001/blk00000081 (
.CI(\blk00000001/sig0000002f ),
.DI(\blk00000001/sig000001df ),
.S(\blk00000001/sig000001e0 ),
.O(\blk00000001/sig0000019b )
);
XORCY \blk00000001/blk00000080 (
.CI(\blk00000001/sig0000002f ),
.LI(\blk00000001/sig000001e0 ),
.O(\blk00000001/sig0000019a )
);
MUXCY \blk00000001/blk0000007f (
.CI(\blk00000001/sig0000019b ),
.DI(\blk00000001/sig000001de ),
.S(\blk00000001/sig00000154 ),
.O(\blk00000001/sig00000199 )
);
MUXCY \blk00000001/blk0000007e (
.CI(\blk00000001/sig0000002e ),
.DI(\blk00000001/sig000001dd ),
.S(\blk00000001/sig00000198 ),
.O(\blk00000001/sig00000197 )
);
MUXCY \blk00000001/blk0000007d (
.CI(\blk00000001/sig000001a2 ),
.DI(\blk00000001/sig000001dc ),
.S(\blk00000001/sig00000150 ),
.O(\blk00000001/sig00000196 )
);
MUXCY \blk00000001/blk0000007c (
.CI(\blk00000001/sig0000019f ),
.DI(\blk00000001/sig000001db ),
.S(\blk00000001/sig0000014e ),
.O(\blk00000001/sig00000195 )
);
MUXCY \blk00000001/blk0000007b (
.CI(\blk00000001/sig0000019c ),
.DI(\blk00000001/sig000001da ),
.S(\blk00000001/sig0000014c ),
.O(\blk00000001/sig00000194 )
);
MUXCY \blk00000001/blk0000007a (
.CI(\blk00000001/sig00000199 ),
.DI(\blk00000001/sig000001d9 ),
.S(\blk00000001/sig0000014a ),
.O(\blk00000001/sig00000193 )
);
MUXCY \blk00000001/blk00000079 (
.CI(\blk00000001/sig00000197 ),
.DI(\blk00000001/sig000001d8 ),
.S(\blk00000001/sig000000cc ),
.O(\blk00000001/sig00000192 )
);
MUXCY \blk00000001/blk00000078 (
.CI(\blk00000001/sig00000196 ),
.DI(\blk00000001/sig000001d7 ),
.S(\blk00000001/sig00000147 ),
.O(\blk00000001/sig00000191 )
);
MUXCY \blk00000001/blk00000077 (
.CI(\blk00000001/sig00000195 ),
.DI(\blk00000001/sig000001d6 ),
.S(\blk00000001/sig00000145 ),
.O(\blk00000001/sig00000190 )
);
MUXCY \blk00000001/blk00000076 (
.CI(\blk00000001/sig00000194 ),
.DI(\blk00000001/sig000001d5 ),
.S(\blk00000001/sig00000143 ),
.O(\blk00000001/sig0000018f )
);
MUXCY \blk00000001/blk00000075 (
.CI(\blk00000001/sig00000193 ),
.DI(\blk00000001/sig000001d4 ),
.S(\blk00000001/sig00000141 ),
.O(\blk00000001/sig0000018e )
);
MUXCY \blk00000001/blk00000074 (
.CI(\blk00000001/sig00000192 ),
.DI(\blk00000001/sig000001d3 ),
.S(\blk00000001/sig000000cb ),
.O(\blk00000001/sig0000018d )
);
MUXCY \blk00000001/blk00000073 (
.CI(\blk00000001/sig00000191 ),
.DI(\blk00000001/sig000001d2 ),
.S(\blk00000001/sig0000013e ),
.O(\blk00000001/sig0000018c )
);
MUXCY \blk00000001/blk00000072 (
.CI(\blk00000001/sig00000190 ),
.DI(\blk00000001/sig000001d1 ),
.S(\blk00000001/sig0000013c ),
.O(\blk00000001/sig0000018b )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig0000018f ),
.DI(\blk00000001/sig000001d0 ),
.S(\blk00000001/sig0000013a ),
.O(\blk00000001/sig0000018a )
);
MUXCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig0000018e ),
.DI(\blk00000001/sig000001cf ),
.S(\blk00000001/sig00000138 ),
.O(\blk00000001/sig00000189 )
);
MUXCY \blk00000001/blk0000006f (
.CI(\blk00000001/sig0000018d ),
.DI(\blk00000001/sig000001ce ),
.S(\blk00000001/sig000000ca ),
.O(\blk00000001/sig00000188 )
);
MUXCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig0000018c ),
.DI(\blk00000001/sig000001cd ),
.S(\blk00000001/sig00000135 ),
.O(\blk00000001/sig00000187 )
);
MUXCY \blk00000001/blk0000006d (
.CI(\blk00000001/sig0000018b ),
.DI(\blk00000001/sig000001cc ),
.S(\blk00000001/sig00000133 ),
.O(\blk00000001/sig00000186 )
);
MUXCY \blk00000001/blk0000006c (
.CI(\blk00000001/sig0000018a ),
.DI(\blk00000001/sig000001cb ),
.S(\blk00000001/sig00000131 ),
.O(\blk00000001/sig00000185 )
);
MUXCY \blk00000001/blk0000006b (
.CI(\blk00000001/sig00000189 ),
.DI(\blk00000001/sig000001ca ),
.S(\blk00000001/sig0000012f ),
.O(\blk00000001/sig00000184 )
);
MUXCY \blk00000001/blk0000006a (
.CI(\blk00000001/sig00000188 ),
.DI(\blk00000001/sig000001c9 ),
.S(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig00000183 )
);
MUXCY \blk00000001/blk00000069 (
.CI(\blk00000001/sig00000187 ),
.DI(\blk00000001/sig000001c8 ),
.S(\blk00000001/sig0000012c ),
.O(\blk00000001/sig00000182 )
);
MUXCY \blk00000001/blk00000068 (
.CI(\blk00000001/sig00000186 ),
.DI(\blk00000001/sig000001c7 ),
.S(\blk00000001/sig0000012a ),
.O(\blk00000001/sig00000181 )
);
MUXCY \blk00000001/blk00000067 (
.CI(\blk00000001/sig00000185 ),
.DI(\blk00000001/sig000001c6 ),
.S(\blk00000001/sig00000128 ),
.O(\blk00000001/sig00000180 )
);
MUXCY \blk00000001/blk00000066 (
.CI(\blk00000001/sig00000184 ),
.DI(\blk00000001/sig000001c5 ),
.S(\blk00000001/sig00000126 ),
.O(\blk00000001/sig0000017f )
);
MUXCY \blk00000001/blk00000065 (
.CI(\blk00000001/sig00000183 ),
.DI(\blk00000001/sig000001c4 ),
.S(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig0000017e )
);
MUXCY \blk00000001/blk00000064 (
.CI(\blk00000001/sig00000182 ),
.DI(\blk00000001/sig000001c3 ),
.S(\blk00000001/sig00000123 ),
.O(\blk00000001/sig0000017d )
);
MUXCY \blk00000001/blk00000063 (
.CI(\blk00000001/sig00000181 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig00000121 ),
.O(\blk00000001/sig0000017c )
);
MUXCY \blk00000001/blk00000062 (
.CI(\blk00000001/sig00000180 ),
.DI(\blk00000001/sig000001c1 ),
.S(\blk00000001/sig0000011f ),
.O(\blk00000001/sig0000017b )
);
MUXCY \blk00000001/blk00000061 (
.CI(\blk00000001/sig0000017f ),
.DI(\blk00000001/sig000001c0 ),
.S(\blk00000001/sig0000011d ),
.O(\blk00000001/sig0000017a )
);
MUXCY \blk00000001/blk00000060 (
.CI(\blk00000001/sig0000017e ),
.DI(\blk00000001/sig000001bf ),
.S(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig00000179 )
);
MUXCY \blk00000001/blk0000005f (
.CI(\blk00000001/sig0000017d ),
.DI(\blk00000001/sig000001be ),
.S(\blk00000001/sig0000011a ),
.O(\blk00000001/sig00000178 )
);
MUXCY \blk00000001/blk0000005e (
.CI(\blk00000001/sig0000017c ),
.DI(\blk00000001/sig000001bd ),
.S(\blk00000001/sig00000118 ),
.O(\blk00000001/sig00000177 )
);
MUXCY \blk00000001/blk0000005d (
.CI(\blk00000001/sig0000017b ),
.DI(\blk00000001/sig000001bc ),
.S(\blk00000001/sig00000116 ),
.O(\blk00000001/sig00000176 )
);
MUXCY \blk00000001/blk0000005c (
.CI(\blk00000001/sig0000017a ),
.DI(\blk00000001/sig000001bb ),
.S(\blk00000001/sig00000114 ),
.O(\blk00000001/sig00000175 )
);
MUXCY \blk00000001/blk0000005b (
.CI(\blk00000001/sig00000179 ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000c6 ),
.O(\blk00000001/sig00000174 )
);
MUXCY \blk00000001/blk0000005a (
.CI(\blk00000001/sig00000178 ),
.DI(\blk00000001/sig000001b9 ),
.S(\blk00000001/sig00000111 ),
.O(\blk00000001/sig00000173 )
);
MUXCY \blk00000001/blk00000059 (
.CI(\blk00000001/sig00000177 ),
.DI(\blk00000001/sig000001b8 ),
.S(\blk00000001/sig0000010f ),
.O(\blk00000001/sig00000172 )
);
MUXCY \blk00000001/blk00000058 (
.CI(\blk00000001/sig00000176 ),
.DI(\blk00000001/sig000001b7 ),
.S(\blk00000001/sig0000010d ),
.O(\blk00000001/sig00000171 )
);
MUXCY \blk00000001/blk00000057 (
.CI(\blk00000001/sig00000175 ),
.DI(\blk00000001/sig000001b6 ),
.S(\blk00000001/sig0000010b ),
.O(\blk00000001/sig00000170 )
);
MUXCY \blk00000001/blk00000056 (
.CI(\blk00000001/sig00000174 ),
.DI(\blk00000001/sig000001b5 ),
.S(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig0000016f )
);
MUXCY \blk00000001/blk00000055 (
.CI(\blk00000001/sig00000173 ),
.DI(\blk00000001/sig000001b4 ),
.S(\blk00000001/sig00000108 ),
.O(\blk00000001/sig0000016e )
);
MUXCY \blk00000001/blk00000054 (
.CI(\blk00000001/sig00000172 ),
.DI(\blk00000001/sig000001b3 ),
.S(\blk00000001/sig00000106 ),
.O(\blk00000001/sig0000016d )
);
MUXCY \blk00000001/blk00000053 (
.CI(\blk00000001/sig00000171 ),
.DI(\blk00000001/sig000001b2 ),
.S(\blk00000001/sig00000104 ),
.O(\blk00000001/sig0000016c )
);
MUXCY \blk00000001/blk00000052 (
.CI(\blk00000001/sig00000170 ),
.DI(\blk00000001/sig000001b1 ),
.S(\blk00000001/sig00000102 ),
.O(\blk00000001/sig0000016b )
);
MUXCY \blk00000001/blk00000051 (
.CI(\blk00000001/sig0000016f ),
.DI(\blk00000001/sig000001b0 ),
.S(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig0000016a )
);
MUXCY \blk00000001/blk00000050 (
.CI(\blk00000001/sig0000016e ),
.DI(\blk00000001/sig000001af ),
.S(\blk00000001/sig000000ff ),
.O(\blk00000001/sig00000169 )
);
MUXCY \blk00000001/blk0000004f (
.CI(\blk00000001/sig0000016d ),
.DI(\blk00000001/sig000001ae ),
.S(\blk00000001/sig000000fd ),
.O(\blk00000001/sig00000168 )
);
MUXCY \blk00000001/blk0000004e (
.CI(\blk00000001/sig0000016c ),
.DI(\blk00000001/sig000001ad ),
.S(\blk00000001/sig000000fb ),
.O(\blk00000001/sig00000167 )
);
MUXCY \blk00000001/blk0000004d (
.CI(\blk00000001/sig0000016b ),
.DI(\blk00000001/sig000001ac ),
.S(\blk00000001/sig000000f9 ),
.O(\blk00000001/sig00000166 )
);
MUXCY \blk00000001/blk0000004c (
.CI(\blk00000001/sig0000016a ),
.DI(\blk00000001/sig000001ab ),
.S(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig00000165 )
);
MUXCY \blk00000001/blk0000004b (
.CI(\blk00000001/sig00000169 ),
.DI(\blk00000001/sig000001aa ),
.S(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig00000164 )
);
MUXCY \blk00000001/blk0000004a (
.CI(\blk00000001/sig00000168 ),
.DI(\blk00000001/sig000001a9 ),
.S(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig00000163 )
);
MUXCY \blk00000001/blk00000049 (
.CI(\blk00000001/sig00000167 ),
.DI(\blk00000001/sig000001a8 ),
.S(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig00000162 )
);
MUXCY \blk00000001/blk00000048 (
.CI(\blk00000001/sig00000166 ),
.DI(\blk00000001/sig000001a7 ),
.S(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig00000161 )
);
MUXCY \blk00000001/blk00000047 (
.CI(\blk00000001/sig00000165 ),
.DI(\blk00000001/sig000001a6 ),
.S(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig00000160 )
);
MUXCY \blk00000001/blk00000046 (
.CI(\blk00000001/sig00000160 ),
.DI(\blk00000001/sig000001a5 ),
.S(\blk00000001/sig000001ea ),
.O(\blk00000001/sig0000015f )
);
XORCY \blk00000001/blk00000045 (
.CI(\blk00000001/sig000001a4 ),
.LI(\blk00000001/sig0000015d ),
.O(\blk00000001/sig0000015e )
);
XORCY \blk00000001/blk00000044 (
.CI(\blk00000001/sig000001a2 ),
.LI(\blk00000001/sig00000150 ),
.O(\blk00000001/sig0000015c )
);
XORCY \blk00000001/blk00000043 (
.CI(\blk00000001/sig000001a1 ),
.LI(\blk00000001/sig0000015a ),
.O(\blk00000001/sig0000015b )
);
XORCY \blk00000001/blk00000042 (
.CI(\blk00000001/sig0000019f ),
.LI(\blk00000001/sig0000014e ),
.O(\blk00000001/sig00000159 )
);
XORCY \blk00000001/blk00000041 (
.CI(\blk00000001/sig0000019e ),
.LI(\blk00000001/sig00000157 ),
.O(\blk00000001/sig00000158 )
);
XORCY \blk00000001/blk00000040 (
.CI(\blk00000001/sig0000019c ),
.LI(\blk00000001/sig0000014c ),
.O(\blk00000001/sig00000156 )
);
XORCY \blk00000001/blk0000003f (
.CI(\blk00000001/sig0000019b ),
.LI(\blk00000001/sig00000154 ),
.O(\blk00000001/sig00000155 )
);
XORCY \blk00000001/blk0000003e (
.CI(\blk00000001/sig00000199 ),
.LI(\blk00000001/sig0000014a ),
.O(\blk00000001/sig00000153 )
);
XORCY \blk00000001/blk0000003d (
.CI(\blk00000001/sig0000002e ),
.LI(\blk00000001/sig00000198 ),
.O(\blk00000001/sig00000152 )
);
XORCY \blk00000001/blk0000003c (
.CI(\blk00000001/sig00000197 ),
.LI(\blk00000001/sig000000cc ),
.O(\blk00000001/sig00000151 )
);
XORCY \blk00000001/blk0000003b (
.CI(\blk00000001/sig00000196 ),
.LI(\blk00000001/sig00000147 ),
.O(\blk00000001/sig0000014f )
);
XORCY \blk00000001/blk0000003a (
.CI(\blk00000001/sig00000195 ),
.LI(\blk00000001/sig00000145 ),
.O(\blk00000001/sig0000014d )
);
XORCY \blk00000001/blk00000039 (
.CI(\blk00000001/sig00000194 ),
.LI(\blk00000001/sig00000143 ),
.O(\blk00000001/sig0000014b )
);
XORCY \blk00000001/blk00000038 (
.CI(\blk00000001/sig00000193 ),
.LI(\blk00000001/sig00000141 ),
.O(\blk00000001/sig00000149 )
);
XORCY \blk00000001/blk00000037 (
.CI(\blk00000001/sig00000192 ),
.LI(\blk00000001/sig000000cb ),
.O(\blk00000001/sig00000148 )
);
XORCY \blk00000001/blk00000036 (
.CI(\blk00000001/sig00000191 ),
.LI(\blk00000001/sig0000013e ),
.O(\blk00000001/sig00000146 )
);
XORCY \blk00000001/blk00000035 (
.CI(\blk00000001/sig00000190 ),
.LI(\blk00000001/sig0000013c ),
.O(\blk00000001/sig00000144 )
);
XORCY \blk00000001/blk00000034 (
.CI(\blk00000001/sig0000018f ),
.LI(\blk00000001/sig0000013a ),
.O(\blk00000001/sig00000142 )
);
XORCY \blk00000001/blk00000033 (
.CI(\blk00000001/sig0000018e ),
.LI(\blk00000001/sig00000138 ),
.O(\blk00000001/sig00000140 )
);
XORCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig0000018d ),
.LI(\blk00000001/sig000000ca ),
.O(\blk00000001/sig0000013f )
);
XORCY \blk00000001/blk00000031 (
.CI(\blk00000001/sig0000018c ),
.LI(\blk00000001/sig00000135 ),
.O(\blk00000001/sig0000013d )
);
XORCY \blk00000001/blk00000030 (
.CI(\blk00000001/sig0000018b ),
.LI(\blk00000001/sig00000133 ),
.O(\blk00000001/sig0000013b )
);
XORCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig0000018a ),
.LI(\blk00000001/sig00000131 ),
.O(\blk00000001/sig00000139 )
);
XORCY \blk00000001/blk0000002e (
.CI(\blk00000001/sig00000189 ),
.LI(\blk00000001/sig0000012f ),
.O(\blk00000001/sig00000137 )
);
XORCY \blk00000001/blk0000002d (
.CI(\blk00000001/sig00000188 ),
.LI(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig00000136 )
);
XORCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig00000187 ),
.LI(\blk00000001/sig0000012c ),
.O(\blk00000001/sig00000134 )
);
XORCY \blk00000001/blk0000002b (
.CI(\blk00000001/sig00000186 ),
.LI(\blk00000001/sig0000012a ),
.O(\blk00000001/sig00000132 )
);
XORCY \blk00000001/blk0000002a (
.CI(\blk00000001/sig00000185 ),
.LI(\blk00000001/sig00000128 ),
.O(\blk00000001/sig00000130 )
);
XORCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig00000184 ),
.LI(\blk00000001/sig00000126 ),
.O(\blk00000001/sig0000012e )
);
XORCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig00000183 ),
.LI(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig0000012d )
);
XORCY \blk00000001/blk00000027 (
.CI(\blk00000001/sig00000182 ),
.LI(\blk00000001/sig00000123 ),
.O(\blk00000001/sig0000012b )
);
XORCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig00000181 ),
.LI(\blk00000001/sig00000121 ),
.O(\blk00000001/sig00000129 )
);
XORCY \blk00000001/blk00000025 (
.CI(\blk00000001/sig00000180 ),
.LI(\blk00000001/sig0000011f ),
.O(\blk00000001/sig00000127 )
);
XORCY \blk00000001/blk00000024 (
.CI(\blk00000001/sig0000017f ),
.LI(\blk00000001/sig0000011d ),
.O(\blk00000001/sig00000125 )
);
XORCY \blk00000001/blk00000023 (
.CI(\blk00000001/sig0000017e ),
.LI(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig00000124 )
);
XORCY \blk00000001/blk00000022 (
.CI(\blk00000001/sig0000017d ),
.LI(\blk00000001/sig0000011a ),
.O(\blk00000001/sig00000122 )
);
XORCY \blk00000001/blk00000021 (
.CI(\blk00000001/sig0000017c ),
.LI(\blk00000001/sig00000118 ),
.O(\blk00000001/sig00000120 )
);
XORCY \blk00000001/blk00000020 (
.CI(\blk00000001/sig0000017b ),
.LI(\blk00000001/sig00000116 ),
.O(\blk00000001/sig0000011e )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig0000017a ),
.LI(\blk00000001/sig00000114 ),
.O(\blk00000001/sig0000011c )
);
XORCY \blk00000001/blk0000001e (
.CI(\blk00000001/sig00000179 ),
.LI(\blk00000001/sig000000c6 ),
.O(\blk00000001/sig0000011b )
);
XORCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig00000178 ),
.LI(\blk00000001/sig00000111 ),
.O(\blk00000001/sig00000119 )
);
XORCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig00000177 ),
.LI(\blk00000001/sig0000010f ),
.O(\blk00000001/sig00000117 )
);
XORCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig00000176 ),
.LI(\blk00000001/sig0000010d ),
.O(\blk00000001/sig00000115 )
);
XORCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig00000175 ),
.LI(\blk00000001/sig0000010b ),
.O(\blk00000001/sig00000113 )
);
XORCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig00000174 ),
.LI(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig00000112 )
);
XORCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig00000173 ),
.LI(\blk00000001/sig00000108 ),
.O(\blk00000001/sig00000110 )
);
XORCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig00000172 ),
.LI(\blk00000001/sig00000106 ),
.O(\blk00000001/sig0000010e )
);
XORCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig00000171 ),
.LI(\blk00000001/sig00000104 ),
.O(\blk00000001/sig0000010c )
);
XORCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig00000170 ),
.LI(\blk00000001/sig00000102 ),
.O(\blk00000001/sig0000010a )
);
XORCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig0000016f ),
.LI(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig00000109 )
);
XORCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig0000016e ),
.LI(\blk00000001/sig000000ff ),
.O(\blk00000001/sig00000107 )
);
XORCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig0000016d ),
.LI(\blk00000001/sig000000fd ),
.O(\blk00000001/sig00000105 )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig0000016c ),
.LI(\blk00000001/sig000000fb ),
.O(\blk00000001/sig00000103 )
);
XORCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig0000016b ),
.LI(\blk00000001/sig000000f9 ),
.O(\blk00000001/sig00000101 )
);
XORCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig0000016a ),
.LI(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig00000100 )
);
XORCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig00000169 ),
.LI(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig000000fe )
);
XORCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig00000168 ),
.LI(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig000000fc )
);
XORCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig00000167 ),
.LI(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig000000fa )
);
XORCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig00000166 ),
.LI(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig000000f8 )
);
XORCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig00000165 ),
.LI(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig000000f7 )
);
XORCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig00000164 ),
.LI(\blk00000001/sig000000ed ),
.O(\blk00000001/sig000000f5 )
);
XORCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig00000163 ),
.LI(\blk00000001/sig000000ec ),
.O(\blk00000001/sig000000f3 )
);
XORCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig00000162 ),
.LI(\blk00000001/sig000000eb ),
.O(\blk00000001/sig000000f1 )
);
XORCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig00000161 ),
.LI(\blk00000001/sig000000ea ),
.O(\blk00000001/sig000000ef )
);
XORCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig00000160 ),
.LI(\blk00000001/sig000001ea ),
.O(\blk00000001/sig000000ee )
);
XORCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig0000015f ),
.LI(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000000e9 )
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig0000002f )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig0000002e )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_2_V
`define SKY130_FD_SC_LS__O41AI_2_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_2_V
|
// Modified from John Loomis, http://www.johnloomis.org/
module LCD_display_string(index,out,state_code);
input [4:0] index;
input [4:0] state_code;
output [7:0] out;
reg [7:0] out;
// ASCII hex values for LCD Display
// Line 1
always
case (index)
5'h00: case (state_code)
5'b10000: out <= 8'h44;//D
default: out <= 8'h53;//S
endcase
5'h01: case (state_code)
5'b00000: out <= 8'h74;//t
5'b10000: out <= 8'h6F;//o
default: out <= 8'h65;//e
endcase
5'h02: case (state_code)
5'b00000: out <= 8'h61;//a
5'b10000: out <= 8'h6E;//n
default: out <= 8'h74;//t
endcase
5'h03: case (state_code)
5'b00000: out <= 8'h72;//r
5'b10000: out <= 8'h65;//e
default: out <= 8'h20;//sp
endcase
5'h04: case (state_code)
5'b00000: out <= 8'h74;//t
5'b00001: out <= 8'h43;//C
5'b00010: out <= 8'h4D;//M
5'b00100: out <= 8'h54;//T
5'b01000: out <= 8'h53;//S
5'b10000: out <= 8'h20;//sp
default: out <= 8'h20;//sp
endcase
5'h05: case (state_code)
5'b00001: out <= 8'h6C;//l
5'b00010: out <= 8'h65;//e
5'b00100: out <= 8'h69;//i
5'b01000: out <= 8'h69;//i
default: out <= 8'h20;//sp
endcase
5'h06: case (state_code)
5'b00001: out <= 8'h6F;//o
5'b00010: out <= 8'h61;//a
5'b00100: out <= 8'h6D;//m
5'b01000: out <= 8'h7A;//z
default: out <= 8'h20;//sp
endcase
5'h07: case (state_code)
5'b00001: out <= 8'h63;//l
5'b00010: out <= 8'h6C;//l
5'b00100: out <= 8'h65;//e
5'b01000: out <= 8'h65;//e
default: out <= 8'h20;//sp
endcase
5'h08: case (state_code)
5'b00001: out <= 8'h6B;//k
default: out <= 8'h20;//sp
endcase
// Line 2
5'h10: out <= 8'h50;//P
5'h11: out <= 8'h72;//r
5'h12: out <= 8'h65;//e
5'h13: out <= 8'h73;//s
5'h14: out <= 8'h73;//s
5'h15: out <= 8'h20;//sp
5'h16: out <= 8'h4F;//O
5'h17: out <= 8'h6B;//k
default: out <= 8'h20;
endcase
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_icd.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: bw_r_icd
// Description:
// The ICD contains the icache data.
// 32B line size.
// Write BW: 16B
// Read BW: 16Bx2 (fetdata and topdata), collapsed to 4Bx2
// Associativity: 4
// Write boundary: 34b (32b inst + parity + predec bit)
// NOTES:
// 1. No clock enable. Rd/Wr enable is used to trigger the
// operation.
// 2. 2:1 mux on address input. Selects provided externally.
// 3. 3:1 mux on data input. Selects provided and guaranteed
// exclusive, externally.
//
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
//`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "ifu.h"
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_ICD
`endif
`ifdef FPGA_SYN_ICD
module bw_r_icd(icd_wsel_fetdata_s1, icd_wsel_topdata_s1, icd_fuse_repair_value,
icd_fuse_repair_en, so, rclk, se, si, reset_l, sehold, fdp_icd_index_bf,
ifq_icd_index_bf, fcl_icd_index_sel_ifq_bf, ifq_icd_wrway_bf,
ifq_icd_worden_bf, ifq_icd_wrdata_i2, fcl_icd_rdreq_bf,
fcl_icd_wrreq_bf, bist_ic_data, rst_tri_en, ifq_icd_data_sel_old_i2,
ifq_icd_data_sel_fill_i2, ifq_icd_data_sel_bist_i2, fuse_icd_wren,
fuse_icd_rid, fuse_icd_repair_value, fuse_icd_repair_en,
efc_spc_fuse_clk1);
input rclk;
input se;
input si;
input reset_l;
input sehold;
input [11:2] fdp_icd_index_bf;
input [11:2] ifq_icd_index_bf;
input fcl_icd_index_sel_ifq_bf;
input [1:0] ifq_icd_wrway_bf;
input [3:0] ifq_icd_worden_bf;
input [135:0] ifq_icd_wrdata_i2;
input fcl_icd_rdreq_bf;
input fcl_icd_wrreq_bf;
input [7:0] bist_ic_data;
input rst_tri_en;
input ifq_icd_data_sel_old_i2;
input ifq_icd_data_sel_fill_i2;
input ifq_icd_data_sel_bist_i2;
input fuse_icd_wren;
input [3:0] fuse_icd_rid;
input [7:0] fuse_icd_repair_value;
input [1:0] fuse_icd_repair_en;
input efc_spc_fuse_clk1;
output [135:0] icd_wsel_fetdata_s1;
output [135:0] icd_wsel_topdata_s1;
output [7:0] icd_fuse_repair_value;
output [1:0] icd_fuse_repair_en;
output so;
reg [7:0] icd_fuse_repair_value;
reg [1:0] icd_fuse_repair_en;
reg [135:0] fetdata_f;
reg [135:0] topdata_f;
reg [135:0] fetdata_sa;
reg [135:0] topdata_sa;
reg [135:0] fetdata_s1;
reg [135:0] topdata_s1;
wire clk;
wire [135:0] next_wrdata_bf;
wire [135:0] wrdata_f;
wire [135:0] bist_data_expand;
`ifdef FPGA_SYN_ALTERA
reg [11:2] index_bf;
`else
wire [11:2] index_bf;
`endif
reg [11:2] index_f;
reg [11:0] wr_index0;
reg [11:0] wr_index1;
reg [11:0] wr_index2;
reg [11:0] wr_index3;
reg rdreq_f;
reg wrreq_f;
reg [3:0] worden_f;
reg [1:0] wrway_f;
`ifdef FPGA_SYN_ALTERA
reg [33:0] icdata_ary_00_00 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_00_01 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_00_10 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_00_11 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_01_00 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_01_01 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_01_10 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_01_11 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_10_00 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_10_01 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_10_10 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_10_11 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_11_00 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_11_01 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_11_10 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
reg [33:0] icdata_ary_11_11 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
`else
reg [33:0] icdata_ary_00_00 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_00_01 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_00_10 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_00_11 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_01_00 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_01_01 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_01_10 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_01_11 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_10_00 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_10_01 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_10_10 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_10_11 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_11_00 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_11_01 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_11_10 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
reg [33:0] icdata_ary_11_11 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
`endif
assign clk = rclk;
`ifdef FPGA_SYN_ALTERA
`else
assign index_bf = (fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf :
fdp_icd_index_bf);
`endif
// assign index_bf = (fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf :
// fdp_icd_index_bf);
wire [11:2] top_index = {index_f[11:3] , 1'b1};
assign bist_data_expand = 136'b0;
assign icd_wsel_fetdata_s1 = fetdata_s1;
assign icd_wsel_topdata_s1 = topdata_s1;
mux3ds #(136) icden_mux(
.dout (next_wrdata_bf),
.in0 (wrdata_f),
.in1 (ifq_icd_wrdata_i2),
.in2 (bist_data_expand),
.sel0 (ifq_icd_data_sel_old_i2),
.sel1 (ifq_icd_data_sel_fill_i2),
.sel2 (ifq_icd_data_sel_bist_i2));
dffe_s #(136) wrdata_reg(
.din (next_wrdata_bf),
.clk (clk),
.q (wrdata_f),
.en ((~sehold)),
.se (se));
always @(posedge clk) begin
if (~sehold) begin
rdreq_f <= fcl_icd_rdreq_bf;
wrreq_f <= fcl_icd_wrreq_bf;
`ifdef FPGA_SYN_ALTERA
`else
index_f <= index_bf;
`endif
wrway_f <= ifq_icd_wrway_bf;
worden_f <= ifq_icd_worden_bf;
wr_index0 <= {index_bf[11:4], 2'b0, ifq_icd_wrway_bf};
wr_index1 <= {index_bf[11:4], 2'b1, ifq_icd_wrway_bf};
wr_index2 <= {index_bf[11:4], 2'b10, ifq_icd_wrway_bf};
wr_index3 <= {index_bf[11:4], 2'b11, ifq_icd_wrway_bf};
end
fetdata_s1 <= fetdata_f;
topdata_s1 <= topdata_f;
end
reg [33:0] fetch_00_00;
reg [33:0] fetch_00_01;
reg [33:0] fetch_00_10;
reg [33:0] fetch_00_11;
reg [33:0] fetch_01_00;
reg [33:0] fetch_01_01;
reg [33:0] fetch_01_10;
reg [33:0] fetch_01_11;
reg [33:0] fetch_10_00;
reg [33:0] fetch_10_01;
reg [33:0] fetch_10_10;
reg [33:0] fetch_10_11;
reg [33:0] fetch_11_00;
reg [33:0] fetch_11_01;
reg [33:0] fetch_11_10;
reg [33:0] fetch_11_11;
`ifdef FPGA_SYN_ALTERA
reg [33:0] fetch_00_00_d;
reg [33:0] fetch_00_01_d;
reg [33:0] fetch_00_10_d;
reg [33:0] fetch_00_11_d;
reg [33:0] fetch_01_00_d;
reg [33:0] fetch_01_01_d;
reg [33:0] fetch_01_10_d;
reg [33:0] fetch_01_11_d;
reg [33:0] fetch_10_00_d;
reg [33:0] fetch_10_01_d;
reg [33:0] fetch_10_10_d;
reg [33:0] fetch_10_11_d;
reg [33:0] fetch_11_00_d;
reg [33:0] fetch_11_01_d;
reg [33:0] fetch_11_10_d;
reg [33:0] fetch_11_11_d;
reg delay_half_cycle;
always @(negedge clk) begin // Sandeep Changed this to negedge clock from posedge clock
// Can we push the reads to the next negedge? Delay this read!! Looks
// like the previous write does not get through
`else
always @(posedge clk) begin
`endif
fetch_00_00 <= icdata_ary_00_00[index_bf[11:4]];
fetch_00_01 <= icdata_ary_00_01[index_bf[11:4]];
fetch_00_10 <= icdata_ary_00_10[index_bf[11:4]];
fetch_00_11 <= icdata_ary_00_11[index_bf[11:4]];
fetch_01_00 <= icdata_ary_01_00[index_bf[11:4]];
fetch_01_01 <= icdata_ary_01_01[index_bf[11:4]];
fetch_01_10 <= icdata_ary_01_10[index_bf[11:4]];
fetch_01_11 <= icdata_ary_01_11[index_bf[11:4]];
fetch_10_00 <= icdata_ary_10_00[index_bf[11:4]];
fetch_10_01 <= icdata_ary_10_01[index_bf[11:4]];
fetch_10_10 <= icdata_ary_10_10[index_bf[11:4]];
fetch_10_11 <= icdata_ary_10_11[index_bf[11:4]];
fetch_11_00 <= icdata_ary_11_00[index_bf[11:4]];
fetch_11_01 <= icdata_ary_11_01[index_bf[11:4]];
fetch_11_10 <= icdata_ary_11_10[index_bf[11:4]];
fetch_11_11 <= icdata_ary_11_11[index_bf[11:4]];
`ifdef FPGA_SYN_ALTERA
index_f <= index_bf; // Sandeep moved this logic 1/2 cycle forward for altera
index_bf <= (fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf : // Moved this logic from a continuous assignment to a synchronous assignment
fdp_icd_index_bf);
`endif
end
always @(index_f or rdreq_f or fetch_00_00 or fetch_01_00 or fetch_10_00 or fetch_11_00
or fetch_00_01 or fetch_01_01 or fetch_10_01 or fetch_11_01
or fetch_00_10 or fetch_01_10 or fetch_10_10 or fetch_11_10
or fetch_00_11 or fetch_01_11 or fetch_10_11 or fetch_11_11) begin
// if (rdreq_f) begin
case(index_f[3:2])
2'b00: fetdata_f[33:0] = fetch_00_00;
2'b01: fetdata_f[33:0] = fetch_01_00;
2'b10: fetdata_f[33:0] = fetch_10_00;
2'b11: fetdata_f[33:0] = fetch_11_00;
endcase
case(index_f[3:2])
2'b00: fetdata_f[67:34] = fetch_00_01;
2'b01: fetdata_f[67:34] = fetch_01_01;
2'b10: fetdata_f[67:34] = fetch_10_01;
2'b11: fetdata_f[67:34] = fetch_11_01;
endcase
case(index_f[3:2])
2'b00: fetdata_f[101:68] = fetch_00_10;
2'b01: fetdata_f[101:68] = fetch_01_10;
2'b10: fetdata_f[101:68] = fetch_10_10;
2'b11: fetdata_f[101:68] = fetch_11_10;
endcase
case(index_f[3:2])
2'b00: fetdata_f[135:102] = fetch_00_11;
2'b01: fetdata_f[135:102] = fetch_01_11;
2'b10: fetdata_f[135:102] = fetch_10_11;
2'b11: fetdata_f[135:102] = fetch_11_11;
endcase
case(index_f[3])
1'b0: topdata_f[33:0] = fetch_01_00;
1'b1: topdata_f[33:0] = fetch_11_00;
endcase
case(index_f[3])
1'b0: topdata_f[67:34] = fetch_01_01;
1'b1: topdata_f[67:34] = fetch_11_01;
endcase
case(index_f[3])
1'b0: topdata_f[101:68] = fetch_01_10;
1'b1: topdata_f[101:68] = fetch_11_10;
endcase
case(index_f[3])
1'b0: topdata_f[135:102] = fetch_01_11;
1'b1: topdata_f[135:102] = fetch_11_11;
endcase
end
// else
// begin
// fetdata_f = 136'b0;
// topdata_f = 136'b0;
// end
// end
always @(negedge clk) begin // Writes happening at the negedge
if (wrreq_f & (~rst_tri_en)) begin
if (worden_f[0]) begin
if (wr_index0[1:0] == 2'b0) begin
icdata_ary_00_00[wr_index0[11:4]] <= wrdata_f[135:102];
end
if (wr_index0[1:0] == 2'b1) begin
icdata_ary_00_01[wr_index0[11:4]] <= wrdata_f[135:102];
end
if (wr_index0[1:0] == 2'b10) begin
icdata_ary_00_10[wr_index0[11:4]] <= wrdata_f[135:102];
end
if (wr_index0[1:0] == 2'b11) begin
icdata_ary_00_11[wr_index0[11:4]] <= wrdata_f[135:102];
end
end
if (worden_f[1]) begin
if (wr_index1[1:0] == 2'b0) begin
icdata_ary_01_00[wr_index1[11:4]] <= wrdata_f[101:68];
end
if (wr_index1[1:0] == 2'b1) begin
icdata_ary_01_01[wr_index1[11:4]] <= wrdata_f[101:68];
end
if (wr_index1[1:0] == 2'b10) begin
icdata_ary_01_10[wr_index1[11:4]] <= wrdata_f[101:68];
end
if (wr_index1[1:0] == 2'b11) begin
icdata_ary_01_11[wr_index1[11:4]] <= wrdata_f[101:68];
end
end
if (worden_f[2]) begin
if (wr_index2[1:0] == 2'b0) begin
icdata_ary_10_00[wr_index2[11:4]] <= wrdata_f[67:34];
end
if (wr_index2[1:0] == 2'b1) begin
icdata_ary_10_01[wr_index2[11:4]] <= wrdata_f[67:34];
end
if (wr_index2[1:0] == 2'b10) begin
icdata_ary_10_10[wr_index2[11:4]] <= wrdata_f[67:34];
end
if (wr_index2[1:0] == 2'b11) begin
icdata_ary_10_11[wr_index2[11:4]] <= wrdata_f[67:34];
end
end
if (worden_f[3]) begin
if (wr_index3[1:0] == 2'b0) begin
icdata_ary_11_00[wr_index3[11:4]] <= wrdata_f[33:0];
end
if (wr_index3[1:0] == 2'b1) begin
icdata_ary_11_01[wr_index3[11:4]] <= wrdata_f[33:0];
end
if (wr_index3[1:0] == 2'b10) begin
icdata_ary_11_10[wr_index3[11:4]] <= wrdata_f[33:0];
end
if (wr_index3[1:0] == 2'b11) begin
icdata_ary_11_11[wr_index3[11:4]] <= wrdata_f[33:0];
end
end
end
end
endmodule
`else
module bw_r_icd(/*AUTOARG*/
// Outputs
icd_wsel_fetdata_s1, icd_wsel_topdata_s1, icd_fuse_repair_value,
icd_fuse_repair_en, so,
// Inputs
rclk, se, si, reset_l, sehold, fdp_icd_index_bf, ifq_icd_index_bf,
fcl_icd_index_sel_ifq_bf, ifq_icd_wrway_bf, ifq_icd_worden_bf,
ifq_icd_wrdata_i2, fcl_icd_rdreq_bf, fcl_icd_wrreq_bf,
bist_ic_data, rst_tri_en, ifq_icd_data_sel_old_i2,
ifq_icd_data_sel_fill_i2, ifq_icd_data_sel_bist_i2, fuse_icd_wren,
fuse_icd_rid, fuse_icd_repair_value, fuse_icd_repair_en,
efc_spc_fuse_clk1
);
input rclk,
se,
si,
reset_l;
input sehold;
input [11:2] fdp_icd_index_bf, // index to write to/read from
ifq_icd_index_bf;
input fcl_icd_index_sel_ifq_bf;
input [1:0] ifq_icd_wrway_bf; // way to write to
input [3:0] ifq_icd_worden_bf; // word to write to (ignore index 1:0)
input [135:0] ifq_icd_wrdata_i2; // 128b data, 4b sw, 4b parity
input fcl_icd_rdreq_bf,
fcl_icd_wrreq_bf;
input [7:0] bist_ic_data; // needs to be expanded
input rst_tri_en;
// datain mux selects
input ifq_icd_data_sel_old_i2,
ifq_icd_data_sel_fill_i2,
ifq_icd_data_sel_bist_i2;
// efuse values for redundancy
input fuse_icd_wren;
input [3:0] fuse_icd_rid;
input [7:0] fuse_icd_repair_value;
input [1:0] fuse_icd_repair_en;
// efuse non ovl clks
input efc_spc_fuse_clk1; // use this clk to talk to fuse hdr
// outputs
output [135:0] icd_wsel_fetdata_s1,
icd_wsel_topdata_s1;
// redundancy reg read
output [7:0] icd_fuse_repair_value;
output [1:0] icd_fuse_repair_en;
output so;
//----------------------------------------------------------------------
// Declarations
//----------------------------------------------------------------------
// local signals
`ifdef DEFINE_0IN
reg [135:0] fetdata_s1,
topdata_s1;
wire [135:0] fetdata_sa,
topdata_sa;
`else
reg [33:0] icdata_ary [4095:0];
reg [135:0] fetdata_f, // way0 is lsb, way3 is msb
topdata_f,
fetdata_sa,
topdata_sa,
fetdata_s1,
topdata_s1;
`endif
wire clk;
wire [135:0] next_wrdata_bf,
wrdata_f,
bist_data_expand;
wire [11:2] top_index,
index_bf;
reg [11:2] index_f;
wire [11:0] wr_index0,
wr_index1,
wr_index2,
wr_index3;
reg rdreq_f,
wrreq_f;
reg [3:0] worden_f;
reg [1:0] wrway_f;
// redundancy crap
reg [7:0] red0_ev_row,
red0_od_row;
reg [9:0] red0_ev_col,
red0_od_col;
reg [7:0] red1_ev_row,
red1_od_row;
reg [9:0] red1_ev_col,
red1_od_col;
reg [7:0] red2_ev_row,
red2_od_row;
reg [9:0] red2_ev_col,
red2_od_col;
reg [7:0] red3_ev_row,
red3_od_row;
reg [9:0] red3_ev_col,
red3_od_col;
reg [7:0] icd_fuse_repair_value;
reg [1:0] icd_fuse_repair_en;
//
// Code start here
//
// clk header derives clk from rclk
assign clk = rclk;
// mux merged with flop
assign index_bf = fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf :
fdp_icd_index_bf;
always @ (posedge clk)
begin
// input flops
if (~sehold)
begin
rdreq_f <= fcl_icd_rdreq_bf;
wrreq_f <= fcl_icd_wrreq_bf;
index_f <= index_bf;
wrway_f <= ifq_icd_wrway_bf;
worden_f <= ifq_icd_worden_bf;
end
// S stage flops (for rd data)
fetdata_s1 <= fetdata_sa;
topdata_s1 <= topdata_sa;
end // always @ (posedge clk)
// BIST data
assign bist_data_expand = {bist_ic_data[1:0], {4{bist_ic_data[7:0]}},
bist_ic_data[1:0], {4{bist_ic_data[7:0]}},
bist_ic_data[1:0], {4{bist_ic_data[7:0]}},
bist_ic_data[1:0], {4{bist_ic_data[7:0]}}};
// Mux + flop for write data input
// ic data enable mux
mux3ds #(136) icden_mux(.dout (next_wrdata_bf),
.in0 (wrdata_f),
.in1 (ifq_icd_wrdata_i2),
.in2 (bist_data_expand),
.sel0 (ifq_icd_data_sel_old_i2),
.sel1 (ifq_icd_data_sel_fill_i2),
.sel2 (ifq_icd_data_sel_bist_i2));
// write data regsiter
// se hold is taken care of by external logic (in ifqctl)
dffe_s #(136) wrdata_reg(.din (next_wrdata_bf),
.clk (clk),
.q (wrdata_f),
.en (~sehold),
.se (se), .si(), .so());
//----------------------------------------------------------------------
// Read Operation
//----------------------------------------------------------------------
// The index has 2 parts.
// 1. The 16B half-line index -- bits 11:4
// 2. The word offset -- bits 3:2 for reads, xx for writes
// 3. The way -- wrway_f for writes, xx for reads
// i.e. we read 1 word from each of 4 ways, but
// we write 4 words to 1 way
assign top_index = {index_f[11:3] , 1'b1};
`ifdef DEFINE_0IN
// physical implmentation: ignore this and use else portion
wire [15:0] we_wrd = ({ 3'b0,worden_f[3], 3'b0,worden_f[2],
3'b0,worden_f[1], 3'b0,worden_f[0] }) << wrway_f;
wire [543:0] we = (~wrreq_f ) ? 544'h0 :
{ {34{we_wrd[15]}}, {34{we_wrd[14]}}, {34{we_wrd[13]}}, {34{we_wrd[12]}},
{34{we_wrd[11]}}, {34{we_wrd[10]}}, {34{we_wrd[ 9]}}, {34{we_wrd[ 8]}},
{34{we_wrd[ 7]}}, {34{we_wrd[ 6]}}, {34{we_wrd[ 5]}}, {34{we_wrd[ 4]}},
{34{we_wrd[ 3]}}, {34{we_wrd[ 2]}}, {34{we_wrd[ 1]}}, {34{we_wrd[ 0]}} };
wire [543:0] din = ({ {4{wrdata_f[ 33: 0]}}, {4{wrdata_f[ 67: 34]}},
{4{wrdata_f[101:68]}}, {4{wrdata_f[135:102]}} });
wire [543:0] dout;
ic_data ic_data ( .nclk(~clk), .adr(index_f[11:4]), .we(we), .din(din), .dout(dout) );
wire [271:0] dout_l1 = index_f[3] ? dout[543:272] : dout[271:0];
assign fetdata_sa[135:0] = index_f[2] ? dout_l1[271:136] : dout_l1[135:0];
assign topdata_sa[135:0] = dout_l1[271:136];
`else
// for physical implementation use this
// read (inst[31:0] + sw bit + par bit) * 4 ways
always @(/*AUTOSENSE*/ /*memory or*/ index_f or rdreq_f
or top_index or wrreq_f)
begin
if (rdreq_f)
begin
if (wrreq_f) // rd-wr contention
begin
fetdata_f = 136'bx;
topdata_f = 136'bx;
end
else
begin // regular read
fetdata_f[33:0] = icdata_ary[{index_f,2'b00}]; // way 0
fetdata_f[67:34] = icdata_ary[{index_f,2'b01}]; // way 1
fetdata_f[101:68] = icdata_ary[{index_f,2'b10}]; // way 2
fetdata_f[135:102] = icdata_ary[{index_f,2'b11}]; // way 3
topdata_f[33:0] = icdata_ary[{top_index, 2'b00}];
topdata_f[67:34] = icdata_ary[{top_index, 2'b01}];
topdata_f[101:68] = icdata_ary[{top_index, 2'b10}];
topdata_f[135:102] = icdata_ary[{top_index, 2'b11}];
end // else: !if(wrreq_f)
end // if (rdreq_f)
else // icache disabled or rd disabled
begin
// JC modified begin
// fetdata_f = 136'bx;
// topdata_f = 136'bx;
fetdata_f = 136'b0;
topdata_f = 136'b0;
// JC modified end
end // else: !if(rdreq_f)
end // always @ (...
// SA latch -- to make 0in happy
always @ (clk or fetdata_f or topdata_f)
begin
if (~clk)
begin
fetdata_sa <= fetdata_f;
topdata_sa <= topdata_f;
end
end
`endif // !`ifdef DEFINE_0IN
// final outputs (272bits)
assign icd_wsel_fetdata_s1 = fetdata_s1;
assign icd_wsel_topdata_s1 = topdata_s1;
//----------------------------------------------------------------------
// Write Operation
//----------------------------------------------------------------------
// The index has 3 parts.
// 1. The 16B half-line index -- bits 11:4 of index_f
// 2. The word offset -- bits 3:2 for reads, xx for writes
// 3. The way -- wrway_f for writes, xx for reads
// index word way
// ----- ---- ---
assign wr_index0 = {index_f[11:4], 2'b00, wrway_f};
assign wr_index1 = {index_f[11:4], 2'b01, wrway_f};
assign wr_index2 = {index_f[11:4], 2'b10, wrway_f};
assign wr_index3 = {index_f[11:4], 2'b11, wrway_f};
`ifdef DEFINE_0IN
`else
// assume write happens @ negedge clk (i.e. phase 1)
always @ (negedge clk)
begin
if (wrreq_f & ~rst_tri_en)
begin
// instructions always Big Endian
if (worden_f[0])
icdata_ary[wr_index0] <= wrdata_f[135:102];
if (worden_f[1])
icdata_ary[wr_index1] <= wrdata_f[101:68];
if (worden_f[2])
icdata_ary[wr_index2] <= wrdata_f[67:34];
if (worden_f[3])
icdata_ary[wr_index3] <= wrdata_f[33:0];
end // if (wrreq_f)
end // always @ (...
`endif // !`ifdef DEFINE_0IN
//--------------------------------------------------------------
// Redundancy Registers
//--------------------------------------------------------------
//
// read red regs
// 16:1 mux
always @ (/*AUTOSENSE*/fuse_icd_rid or red0_ev_col or red0_ev_row
or red0_od_col or red0_od_row or red1_ev_col
or red1_ev_row or red1_od_col or red1_od_row
or red2_ev_col or red2_ev_row or red2_od_col
or red2_od_row or red3_ev_col or red3_ev_row
or red3_od_col or red3_od_row)
begin
// sub array 0
if (fuse_icd_rid[3:0] == 4'b0)
begin
icd_fuse_repair_value = {2'b0, red0_ev_row[5:0]};
icd_fuse_repair_en = red0_ev_row[7:6];
end
else if (fuse_icd_rid[3:0] == 4'b1)
begin
icd_fuse_repair_value = {2'b0, red0_od_row[5:0]};
icd_fuse_repair_en = red0_od_row[7:6];
end
else if (fuse_icd_rid[3:0] == 4'b10)
begin
icd_fuse_repair_value = red0_ev_col[7:0];
icd_fuse_repair_en = red0_ev_col[9:8];
end
else if (fuse_icd_rid[3:0] == 4'b11)
begin
icd_fuse_repair_value = red0_od_col[7:0];
icd_fuse_repair_en = red0_od_col[9:8];
end
// sub array 1
else if (fuse_icd_rid[3:0] == 4'b100)
begin
icd_fuse_repair_value = {2'b0, red1_ev_row[5:0]};
icd_fuse_repair_en = red1_ev_row[7:6];
end
else if (fuse_icd_rid[3:0] == 4'b101)
begin
icd_fuse_repair_value = {2'b0, red1_od_row[5:0]};
icd_fuse_repair_en = red1_od_row[7:6];
end
else if (fuse_icd_rid[3:0] == 4'b110)
begin
icd_fuse_repair_value = red1_ev_col[7:0];
icd_fuse_repair_en = red1_ev_col[9:8];
end
else if (fuse_icd_rid[3:0] == 4'b111)
begin
icd_fuse_repair_value = red1_od_col[7:0];
icd_fuse_repair_en = red1_od_col[9:8];
end
// sub array 2
else if (fuse_icd_rid[3:0] == 4'b1000)
begin
icd_fuse_repair_value = {2'b0, red2_ev_row[5:0]};
icd_fuse_repair_en = red2_ev_row[7:6];
end
else if (fuse_icd_rid[3:0] == 4'b1001)
begin
icd_fuse_repair_value = {2'b0, red2_od_row[5:0]};
icd_fuse_repair_en = red2_od_row[7:6];
end
else if (fuse_icd_rid[3:0] == 4'b1010)
begin
icd_fuse_repair_value = red2_ev_col[7:0];
icd_fuse_repair_en = red2_ev_col[9:8];
end
else if (fuse_icd_rid[3:0] == 4'b1011)
begin
icd_fuse_repair_value = red2_od_col[7:0];
icd_fuse_repair_en = red2_od_col[9:8];
end
// sub array 3
else if (fuse_icd_rid[3:0] == 4'b1100)
begin
icd_fuse_repair_value = {2'b0, red3_ev_row[5:0]};
icd_fuse_repair_en = red3_ev_row[7:6];
end
else if (fuse_icd_rid[3:0] == 4'b1101)
begin
icd_fuse_repair_value = {2'b0, red3_od_row[5:0]};
icd_fuse_repair_en = red3_od_row[7:6];
end
else if (fuse_icd_rid[3:0] == 4'b1110)
begin
icd_fuse_repair_value = red3_ev_col[7:0];
icd_fuse_repair_en = red3_ev_col[9:8];
end
else // if (fuse_icd_rid[3:0] == 4'b1111)
begin
icd_fuse_repair_value = red3_od_col[7:0];
icd_fuse_repair_en = red3_od_col[9:8];
end
end // always @ (...
//
// write red regs
//
// use clk1 to latch anything to/from the hdr
//
// reset_l is an asynchronous reset. Only the the repair enables [9:8]
// need to be reset. However, the actual circuit resets all the bits.
always @ (posedge efc_spc_fuse_clk1 or negedge reset_l)
begin
if (~reset_l)
begin // async reset
red0_ev_row[7:0] <= 8'b0;
red1_ev_row[7:0] <= 8'b0;
red2_ev_row[7:0] <= 8'b0;
red3_ev_row[7:0] <= 8'b0;
red0_od_row[7:0] <= 8'b0;
red1_od_row[7:0] <= 8'b0;
red2_od_row[7:0] <= 8'b0;
red3_od_row[7:0] <= 8'b0;
red0_ev_col[9:0] <= 10'b0;
red1_ev_col[9:0] <= 10'b0;
red2_ev_col[9:0] <= 10'b0;
red3_ev_col[9:0] <= 10'b0;
red0_od_col[9:0] <= 10'b0;
red1_od_col[9:0] <= 10'b0;
red2_od_col[9:0] <= 10'b0;
red3_od_col[9:0] <= 10'b0;
end // if (~reset_l)
else if (fuse_icd_wren & reset_l)
begin // 4:16 decode
if (fuse_icd_rid[3:0] == 4'b0)
begin
red0_ev_row <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[5:0]};
end
else if (fuse_icd_rid[3:0] == 4'b1)
begin
red0_od_row <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[5:0]};
end
else if (fuse_icd_rid[3:0] == 4'b10)
begin
red0_ev_col <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[7:0]};
end
else if (fuse_icd_rid[3:0] == 4'b11)
begin
red0_od_col <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[7:0]};
end
// sub array 1
else if (fuse_icd_rid[3:0] == 4'b100)
begin
red1_ev_row <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[5:0]};
end
else if (fuse_icd_rid[3:0] == 4'b101)
begin
red1_od_row <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[5:0]};
end
else if (fuse_icd_rid[3:0] == 4'b110)
begin
red1_ev_col <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[7:0]};
end
else if (fuse_icd_rid[3:0] == 4'b111)
begin
red1_od_col <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[7:0]};
end
// sub array 2
else if (fuse_icd_rid[3:0] == 4'b1000)
begin
red2_ev_row <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[5:0]};
end
else if (fuse_icd_rid[3:0] == 4'b1001)
begin
red2_od_row <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[5:0]};
end
else if (fuse_icd_rid[3:0] == 4'b1010)
begin
red2_ev_col <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[7:0]};
end
else if (fuse_icd_rid[3:0] == 4'b1011)
begin
red2_od_col <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[7:0]};
end
// sub array 2
else if (fuse_icd_rid[3:0] == 4'b1100)
begin
red3_ev_row <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[5:0]};
end
else if (fuse_icd_rid[3:0] == 4'b1101)
begin
red3_od_row <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[5:0]};
end
else if (fuse_icd_rid[3:0] == 4'b1110)
begin
red3_ev_col <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[7:0]};
end
else // if (fuse_icd_rid[3:0] == 4'b1111)
begin
red3_od_col <= {fuse_icd_repair_en[1:0],
fuse_icd_repair_value[7:0]};
end
end // if (fuse_icd_wren)
end // always @ (...
endmodule // bw_r_icd
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O31AI_BEHAVIORAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKINV_BEHAVIORAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkinv (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_BEHAVIORAL_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:20:13 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top led_controller_design_auto_pc_0 -prefix
// led_controller_design_auto_pc_0_ led_controller_design_auto_pc_0_sim_netlist.v
// Design : led_controller_design_auto_pc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_arready,
s_axi_rready,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_axi_awready,
s_axi_awvalid,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_arready;
input s_axi_rready;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input m_axi_awready;
input s_axi_awvalid;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [22:0]Q;
wire \RD.ar_channel_0_n_0 ;
wire \RD.ar_channel_0_n_38 ;
wire \RD.ar_channel_0_n_39 ;
wire \RD.ar_channel_0_n_40 ;
wire \RD.ar_channel_0_n_41 ;
wire \RD.ar_channel_0_n_8 ;
wire \RD.ar_channel_0_n_9 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_1 ;
wire SI_REG_n_10;
wire SI_REG_n_103;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_144;
wire SI_REG_n_145;
wire SI_REG_n_146;
wire SI_REG_n_147;
wire SI_REG_n_148;
wire SI_REG_n_153;
wire SI_REG_n_154;
wire SI_REG_n_161;
wire SI_REG_n_162;
wire SI_REG_n_163;
wire SI_REG_n_164;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_168;
wire SI_REG_n_169;
wire SI_REG_n_170;
wire SI_REG_n_171;
wire SI_REG_n_172;
wire SI_REG_n_173;
wire SI_REG_n_174;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_45;
wire SI_REG_n_83;
wire SI_REG_n_84;
wire SI_REG_n_85;
wire SI_REG_n_86;
wire \WR.aw_channel_0_n_2 ;
wire \WR.aw_channel_0_n_42 ;
wire \WR.aw_channel_0_n_43 ;
wire \WR.aw_channel_0_n_44 ;
wire \WR.aw_channel_0_n_45 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire \WR.b_channel_0_n_3 ;
wire aclk;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire [1:0]\aw_cmd_fsm_0/state ;
wire [11:0]axaddr_incr;
wire [11:0]b_awid;
wire [3:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ;
wire \gen_simple_ar.ar_pipe/m_valid_i0 ;
wire \gen_simple_ar.ar_pipe/p_1_in ;
wire \gen_simple_aw.aw_pipe/p_1_in ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_push;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire shandshake;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [2:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:0]wrap_cnt;
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel \RD.ar_channel_0
(.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.E(\gen_simple_ar.ar_pipe/p_1_in ),
.O({SI_REG_n_145,SI_REG_n_146,SI_REG_n_147,SI_REG_n_148}),
.Q({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_103,si_rs_arsize,si_rs_araddr}),
.S({\RD.ar_channel_0_n_38 ,\RD.ar_channel_0_n_39 ,\RD.ar_channel_0_n_40 ,\RD.ar_channel_0_n_41 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\cnt_read_reg[1]_rep__0 (\RD.r_channel_0_n_1 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_8 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_9 ),
.\m_payload_i_reg[35] (SI_REG_n_161),
.\m_payload_i_reg[35]_0 (SI_REG_n_163),
.\m_payload_i_reg[3] (SI_REG_n_173),
.\m_payload_i_reg[3]_0 ({SI_REG_n_83,SI_REG_n_84,SI_REG_n_85,SI_REG_n_86}),
.\m_payload_i_reg[44] (SI_REG_n_162),
.\m_payload_i_reg[47] (SI_REG_n_164),
.\m_payload_i_reg[47]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
.\m_payload_i_reg[6] ({SI_REG_n_166,SI_REG_n_167,SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172}),
.\m_payload_i_reg[7] ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
.m_valid_i0(\gen_simple_ar.ar_pipe/m_valid_i0 ),
.\r_arid_r_reg[11] (s_arid_r),
.r_push(r_push),
.r_rlast(r_rlast),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg(s_axi_arready),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_0 ),
.\wrap_second_len_r_reg[2] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_0 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_push(r_push),
.r_rlast(r_rlast),
.s_ready_i_reg(SI_REG_n_165),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_1 ));
led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice SI_REG
(.D({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}),
.E(\gen_simple_aw.aw_pipe/p_1_in ),
.O({SI_REG_n_145,SI_REG_n_146,SI_REG_n_147,SI_REG_n_148}),
.Q({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_45,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_42 ,\WR.aw_channel_0_n_43 ,\WR.aw_channel_0_n_44 ,\WR.aw_channel_0_n_45 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[3] ({SI_REG_n_83,SI_REG_n_84,SI_REG_n_85,SI_REG_n_86}),
.\axaddr_incr_reg[7] ({SI_REG_n_141,SI_REG_n_142,SI_REG_n_143,SI_REG_n_144}),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.axaddr_offset_0(\cmd_translator_0/wrap_cmd_0/axaddr_offset [0]),
.\axaddr_offset_r_reg[0] (SI_REG_n_173),
.\axaddr_offset_r_reg[1] (SI_REG_n_161),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3:1]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
.\axaddr_offset_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axlen_cnt_reg[3] (SI_REG_n_153),
.\axlen_cnt_reg[3]_0 (SI_REG_n_164),
.b_push(b_push),
.\cnt_read_reg[0]_rep__1 (SI_REG_n_165),
.\cnt_read_reg[3]_rep__0 (\RD.r_channel_0_n_0 ),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_38 ,\RD.ar_channel_0_n_39 ,\RD.ar_channel_0_n_40 ,\RD.ar_channel_0_n_41 }),
.m_valid_i0(\gen_simple_ar.ar_pipe/m_valid_i0 ),
.next_pending_r_reg(SI_REG_n_154),
.next_pending_r_reg_0(SI_REG_n_162),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_103,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.shandshake(shandshake),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\RD.ar_channel_0_n_9 ),
.\state_reg[1] (\aw_cmd_fsm_0/state ),
.\state_reg[1]_rep (\WR.aw_channel_0_n_2 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_0 ),
.\state_reg[1]_rep_1 (\RD.ar_channel_0_n_8 ),
.\state_reg[1]_rep_2 (\gen_simple_ar.ar_pipe/p_1_in ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_166,SI_REG_n_167,SI_REG_n_168,SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_174,SI_REG_n_175,SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180}),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
.\wrap_second_len_r_reg[2] (\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[2]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3] (SI_REG_n_163),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel \WR.aw_channel_0
(.D(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.E(\gen_simple_aw.aw_pipe/p_1_in ),
.Q(\aw_cmd_fsm_0/state ),
.S({\WR.aw_channel_0_n_42 ,\WR.aw_channel_0_n_43 ,\WR.aw_channel_0_n_44 ,\WR.aw_channel_0_n_45 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_3 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_3 ),
.\cnt_read_reg[1]_rep__0_0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[46] (SI_REG_n_154),
.\m_payload_i_reg[47] (SI_REG_n_153),
.\m_payload_i_reg[61] ({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_45,si_rs_awsize,si_rs_awaddr}),
.\m_payload_i_reg[6] ({SI_REG_n_174,SI_REG_n_175,SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180}),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_boundary_axaddr_r_reg[0] (\WR.aw_channel_0_n_2 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_2 ),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
.\wrap_second_len_r_reg[3]_1 ({wrap_cnt[3:2],SI_REG_n_10,wrap_cnt[0]}));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.shandshake(shandshake),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp),
.\state_reg[0]_rep (\WR.b_channel_0_n_3 ));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel
(\wrap_boundary_axaddr_r_reg[11] ,
\wrap_second_len_r_reg[2] ,
axaddr_offset,
\axaddr_offset_r_reg[3] ,
r_push,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
m_axi_arvalid,
r_rlast,
m_valid_i0,
E,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
\m_payload_i_reg[47] ,
m_axi_arready,
si_rs_arvalid,
\cnt_read_reg[1]_rep__0 ,
Q,
D,
\m_payload_i_reg[35] ,
\m_payload_i_reg[47]_0 ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[44] ,
areset_d1,
s_axi_arvalid,
s_ready_i_reg,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3]_0 ,
\m_payload_i_reg[6] );
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]\wrap_second_len_r_reg[2] ;
output [0:0]axaddr_offset;
output [2:0]\axaddr_offset_r_reg[3] ;
output r_push;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output m_axi_arvalid;
output r_rlast;
output m_valid_i0;
output [0:0]E;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input \m_payload_i_reg[47] ;
input m_axi_arready;
input si_rs_arvalid;
input \cnt_read_reg[1]_rep__0 ;
input [30:0]Q;
input [1:0]D;
input \m_payload_i_reg[35] ;
input [2:0]\m_payload_i_reg[47]_0 ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[44] ;
input areset_d1;
input s_axi_arvalid;
input s_ready_i_reg;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6] ;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [30:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_11;
wire ar_cmd_fsm_0_n_14;
wire ar_cmd_fsm_0_n_16;
wire ar_cmd_fsm_0_n_17;
wire ar_cmd_fsm_0_n_18;
wire ar_cmd_fsm_0_n_21;
wire ar_cmd_fsm_0_n_3;
wire ar_cmd_fsm_0_n_4;
wire ar_cmd_fsm_0_n_5;
wire ar_cmd_fsm_0_n_6;
wire areset_d1;
wire [0:0]axaddr_offset;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_4;
wire cmd_translator_0_n_5;
wire cmd_translator_0_n_6;
wire cmd_translator_0_n_8;
wire \cnt_read_reg[1]_rep__0 ;
wire \incr_cmd_0/sel_first ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[47] ;
wire [2:0]\m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire m_valid_i0;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push;
wire r_rlast;
wire s_axi_arvalid;
wire s_ready_i_reg;
wire sel_first_i;
wire si_rs_arvalid;
wire [1:0]state;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [0:0]\wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\wrap_cmd_0/wrap_second_len ;
wire [3:0]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [1:0]\wrap_second_len_r_reg[2] ;
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D({ar_cmd_fsm_0_n_3,ar_cmd_fsm_0_n_4,ar_cmd_fsm_0_n_5}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(state),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[0] (ar_cmd_fsm_0_n_21),
.\axaddr_offset_r_reg[0] (axaddr_offset),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r }),
.\axlen_cnt_reg[3] (cmd_translator_0_n_6),
.\axlen_cnt_reg[4] (ar_cmd_fsm_0_n_16),
.\axlen_cnt_reg[6] (cmd_translator_0_n_5),
.\axlen_cnt_reg[7] (ar_cmd_fsm_0_n_0),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[35]_0 (\m_payload_i_reg[35]_0 ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[44] (Q[16:15]),
.\m_payload_i_reg[44]_0 (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 [2:1]),
.m_valid_i0(m_valid_i0),
.next_pending_r_reg(cmd_translator_0_n_1),
.r_push_r_reg(r_push),
.s_axburst_eq0_reg(ar_cmd_fsm_0_n_11),
.s_axburst_eq1_reg(ar_cmd_fsm_0_n_14),
.s_axburst_eq1_reg_0(cmd_translator_0_n_8),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg(s_ready_i_reg),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_17),
.sel_first_reg_0(ar_cmd_fsm_0_n_18),
.sel_first_reg_1(cmd_translator_0_n_4),
.sel_first_reg_2(cmd_translator_0_n_2),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_cnt_r_reg[0] (ar_cmd_fsm_0_n_6),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[2] (D),
.\wrap_second_len_r_reg[3] ({\wrap_cmd_0/wrap_second_len [3],\wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_cmd_0/wrap_second_len_r [3],\wrap_cmd_0/wrap_second_len_r [0]}));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 cmd_translator_0
(.D({\m_payload_i_reg[47]_0 ,axaddr_offset}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q(Q[18:0]),
.S(S),
.aclk(aclk),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] ,\wrap_cmd_0/axaddr_offset_r }),
.\axaddr_offset_r_reg[3]_0 (ar_cmd_fsm_0_n_6),
.\axlen_cnt_reg[0] (cmd_translator_0_n_5),
.\axlen_cnt_reg[0]_0 (cmd_translator_0_n_6),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[39] (ar_cmd_fsm_0_n_11),
.\m_payload_i_reg[39]_0 (ar_cmd_fsm_0_n_14),
.\m_payload_i_reg[3] (\m_payload_i_reg[3]_0 ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(ar_cmd_fsm_0_n_16),
.next_pending_r_reg(cmd_translator_0_n_1),
.r_rlast(r_rlast),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(cmd_translator_0_n_4),
.sel_first_reg_2(ar_cmd_fsm_0_n_18),
.sel_first_reg_3(ar_cmd_fsm_0_n_17),
.sel_first_reg_4(ar_cmd_fsm_0_n_21),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (cmd_translator_0_n_8),
.\state_reg[0]_rep_0 (\m_payload_i_reg[0]_0 ),
.\state_reg[1] (ar_cmd_fsm_0_n_0),
.\state_reg[1]_0 (state),
.\state_reg[1]_rep (r_push),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_cmd_0/wrap_second_len_r [3],\wrap_second_len_r_reg[2] ,\wrap_cmd_0/wrap_second_len_r [0]}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_cmd_0/wrap_second_len [3],D,\wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_1 ({ar_cmd_fsm_0_n_3,ar_cmd_fsm_0_n_4,ar_cmd_fsm_0_n_5}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[19]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(Q[29]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(Q[30]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[25]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[26]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(Q[27]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(Q[28]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel
(Q,
\wrap_boundary_axaddr_r_reg[0] ,
m_axi_awvalid,
E,
b_push,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
in,
S,
aclk,
si_rs_awvalid,
\m_payload_i_reg[47] ,
\m_payload_i_reg[61] ,
\m_payload_i_reg[46] ,
areset_d1,
\cnt_read_reg[1]_rep__0 ,
m_axi_awready,
\cnt_read_reg[1]_rep__0_0 ,
\cnt_read_reg[0]_rep__0 ,
axaddr_incr,
D,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output [1:0]Q;
output \wrap_boundary_axaddr_r_reg[0] ;
output m_axi_awvalid;
output [0:0]E;
output b_push;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [15:0]in;
output [3:0]S;
input aclk;
input si_rs_awvalid;
input \m_payload_i_reg[47] ;
input [31:0]\m_payload_i_reg[61] ;
input \m_payload_i_reg[46] ;
input areset_d1;
input \cnt_read_reg[1]_rep__0 ;
input m_axi_awready;
input \cnt_read_reg[1]_rep__0_0 ;
input \cnt_read_reg[0]_rep__0 ;
input [11:0]axaddr_incr;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_0;
wire aw_cmd_fsm_0_n_10;
wire aw_cmd_fsm_0_n_11;
wire aw_cmd_fsm_0_n_12;
wire aw_cmd_fsm_0_n_3;
wire aw_cmd_fsm_0_n_5;
wire aw_cmd_fsm_0_n_6;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_5;
wire cmd_translator_0_n_6;
wire cmd_translator_0_n_7;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire [15:0]in;
wire \incr_cmd_0/sel_first ;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [31:0]\m_payload_i_reg[61] ;
wire [6:0]\m_payload_i_reg[6] ;
wire sel_first;
wire sel_first_i;
wire si_rs_awvalid;
wire \wrap_boundary_axaddr_r_reg[0] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.E(aw_cmd_fsm_0_n_0),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axlen_cnt_reg[0] (aw_cmd_fsm_0_n_3),
.\axlen_cnt_reg[1] (cmd_translator_0_n_7),
.\axlen_cnt_reg[6] (cmd_translator_0_n_5),
.\axlen_cnt_reg[7] (aw_cmd_fsm_0_n_5),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0_0 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[39] (\m_payload_i_reg[61] [15]),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_6),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_10),
.s_axburst_eq1_reg_0(cmd_translator_0_n_6),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_11),
.sel_first_reg_0(aw_cmd_fsm_0_n_12),
.sel_first_reg_1(cmd_translator_0_n_2),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_boundary_axaddr_r_reg[0] (\wrap_boundary_axaddr_r_reg[0] ),
.wrap_next_pending(wrap_next_pending));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator cmd_translator_0
(.D(D),
.E(\wrap_boundary_axaddr_r_reg[0] ),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axlen_cnt_reg[0] (cmd_translator_0_n_5),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_6),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_10),
.\m_payload_i_reg[46] (\m_payload_i_reg[61] [18:0]),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.next_pending_r_reg_1(cmd_translator_0_n_7),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_12),
.sel_first_reg_2(aw_cmd_fsm_0_n_11),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (aw_cmd_fsm_0_n_0),
.\state_reg[0]_rep (cmd_translator_0_n_6),
.\state_reg[0]_rep_0 (aw_cmd_fsm_0_n_5),
.\state_reg[1]_rep (aw_cmd_fsm_0_n_3),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_1 ));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [30]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [31]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [23]),
.Q(in[7]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [25]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [26]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [27]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [28]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [29]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[61] [19]),
.Q(in[3]),
.R(1'b0));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__0 ,
\state_reg[0]_rep ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
shandshake,
aclk,
b_push,
si_rs_bready,
m_axi_bvalid,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__0 ;
output \state_reg[0]_rep ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input shandshake;
input aclk;
input b_push;
input si_rs_bready;
input m_axi_bvalid;
input [15:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_3;
wire bid_fifo_0_n_5;
wire \bresp_cnt[7]_i_7_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire [15:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
wire \state_reg[0]_rep ;
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_5),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bresp_push(bresp_push),
.bvalid_i_reg(bid_fifo_0_n_3),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\state_reg[0]_rep (\state_reg[0]_rep ));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[0]),
.I1(bresp_cnt_reg__0[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_7_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_7_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_7
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_7_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_5),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_3),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT6 #(
.INIT(64'h00000000EACECCCC))
\s_bresp_acc[0]_i_1
(.I0(m_axi_bresp[0]),
.I1(\s_bresp_acc_reg_n_0_[0] ),
.I2(\s_bresp_acc_reg_n_0_[1] ),
.I3(m_axi_bresp[1]),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EA))
\s_bresp_acc[1]_i_1
(.I0(\s_bresp_acc_reg_n_0_[1] ),
.I1(m_axi_bresp[1]),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator
(next_pending_r_reg,
next_pending_r_reg_0,
sel_first_reg_0,
sel_first_0,
sel_first,
\axlen_cnt_reg[0] ,
\state_reg[0]_rep ,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
sel_first_reg_2,
\m_payload_i_reg[47] ,
Q,
si_rs_awvalid,
\m_payload_i_reg[46] ,
E,
\state_reg[1]_rep ,
axaddr_incr,
\state_reg[0] ,
\state_reg[0]_rep_0 ,
D,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output next_pending_r_reg;
output next_pending_r_reg_0;
output sel_first_reg_0;
output sel_first_0;
output sel_first;
output \axlen_cnt_reg[0] ;
output \state_reg[0]_rep ;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input sel_first_reg_2;
input \m_payload_i_reg[47] ;
input [1:0]Q;
input si_rs_awvalid;
input [18:0]\m_payload_i_reg[46] ;
input [0:0]E;
input \state_reg[1]_rep ;
input [11:0]axaddr_incr;
input [0:0]\state_reg[0] ;
input \state_reg[0]_rep_0 ;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axlen_cnt_reg[0] ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_3;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [18:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire \state_reg[1]_rep ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd incr_cmd_0
(.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[0]_0 (sel_first_0),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12}),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[11] (incr_cmd_0_n_13),
.\m_axi_awaddr[2] (incr_cmd_0_n_15),
.\m_axi_awaddr[3] (incr_cmd_0_n_14),
.\m_payload_i_reg[46] ({\m_payload_i_reg[46] [18:16],\m_payload_i_reg[46] [14:12],\m_payload_i_reg[46] [3:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[46] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd wrap_cmd_0
(.D(D),
.E(E),
.Q(Q),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[46] ({\m_payload_i_reg[46] [18:15],\m_payload_i_reg[46] [13:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg_0(next_pending_r_reg_0),
.next_pending_r_reg_1(next_pending_r_reg_1),
.sel_first_reg_0(sel_first),
.sel_first_reg_1(sel_first_reg_2),
.sel_first_reg_2(incr_cmd_0_n_13),
.sel_first_reg_3(incr_cmd_0_n_14),
.sel_first_reg_4(incr_cmd_0_n_15),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_cmd_translator" *)
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1
(incr_next_pending,
next_pending_r_reg,
sel_first_reg_0,
sel_first,
sel_first_reg_1,
\axlen_cnt_reg[0] ,
\axlen_cnt_reg[0]_0 ,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
S,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_2,
sel_first_reg_3,
\m_payload_i_reg[47] ,
E,
Q,
\state_reg[1]_rep ,
\m_payload_i_reg[44] ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
si_rs_arvalid,
\state_reg[0]_rep_0 ,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
m_valid_i_reg,
\state_reg[1] ,
D,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
sel_first_reg_4,
m_axi_arready,
\state_reg[1]_0 );
output incr_next_pending;
output next_pending_r_reg;
output sel_first_reg_0;
output sel_first;
output sel_first_reg_1;
output \axlen_cnt_reg[0] ;
output \axlen_cnt_reg[0]_0 ;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_2;
input sel_first_reg_3;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [18:0]Q;
input \state_reg[1]_rep ;
input \m_payload_i_reg[44] ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input si_rs_arvalid;
input \state_reg[0]_rep_0 ;
input \axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]m_valid_i_reg;
input \state_reg[1] ;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [0:0]sel_first_reg_4;
input m_axi_arready;
input [1:0]\state_reg[1]_0 ;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [18:0]Q;
wire [3:0]S;
wire aclk;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[0] ;
wire \axlen_cnt_reg[0]_0 ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_3;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire [0:0]sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 incr_cmd_0
(.E(E),
.O(O),
.Q({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[0]_0 (sel_first),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[11] (incr_cmd_0_n_15),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[46] ({Q[18:16],Q[14:12],Q[3:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_4),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_0 (\state_reg[1]_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(Q[15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_2
(.I0(s_axburst_eq1),
.I1(Q[15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 wrap_cmd_0
(.D(D),
.E(E),
.Q({Q[18:15],Q[13:0]}),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0]_0 ),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_15),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[0]_0 ,
\axlen_cnt_reg[0]_0 ,
\axaddr_incr_reg[11]_0 ,
\m_axi_awaddr[11] ,
\m_axi_awaddr[3] ,
\m_axi_awaddr[2] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
\m_payload_i_reg[47] ,
Q,
si_rs_awvalid,
\m_payload_i_reg[46] ,
E,
\state_reg[1]_rep ,
axaddr_incr,
\state_reg[0] ,
\state_reg[0]_rep );
output next_pending_r_reg_0;
output \axaddr_incr_reg[0]_0 ;
output \axlen_cnt_reg[0]_0 ;
output [9:0]\axaddr_incr_reg[11]_0 ;
output \m_axi_awaddr[11] ;
output \m_axi_awaddr[3] ;
output \m_axi_awaddr[2] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input \m_payload_i_reg[47] ;
input [1:0]Q;
input si_rs_awvalid;
input [9:0]\m_payload_i_reg[46] ;
input [0:0]E;
input \state_reg[1]_rep ;
input [11:0]axaddr_incr;
input [0:0]\state_reg[0] ;
input \state_reg[0]_rep ;
wire [0:0]E;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire \axaddr_incr[11]_i_1_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [9:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4_n_1 ;
wire \axaddr_incr_reg[11]_i_4_n_2 ;
wire \axaddr_incr_reg[11]_i_4_n_3 ;
wire \axaddr_incr_reg[11]_i_4_n_4 ;
wire \axaddr_incr_reg[11]_i_4_n_5 ;
wire \axaddr_incr_reg[11]_i_4_n_6 ;
wire \axaddr_incr_reg[11]_i_4_n_7 ;
wire \axaddr_incr_reg[3]_i_3_n_0 ;
wire \axaddr_incr_reg[3]_i_3_n_1 ;
wire \axaddr_incr_reg[3]_i_3_n_2 ;
wire \axaddr_incr_reg[3]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_3_n_4 ;
wire \axaddr_incr_reg[3]_i_3_n_5 ;
wire \axaddr_incr_reg[3]_i_3_n_6 ;
wire \axaddr_incr_reg[3]_i_3_n_7 ;
wire \axaddr_incr_reg[7]_i_3_n_0 ;
wire \axaddr_incr_reg[7]_i_3_n_1 ;
wire \axaddr_incr_reg[7]_i_3_n_2 ;
wire \axaddr_incr_reg[7]_i_3_n_3 ;
wire \axaddr_incr_reg[7]_i_3_n_4 ;
wire \axaddr_incr_reg[7]_i_3_n_5 ;
wire \axaddr_incr_reg[7]_i_3_n_6 ;
wire \axaddr_incr_reg[7]_i_3_n_7 ;
wire \axaddr_incr_reg_n_0_[2] ;
wire \axaddr_incr_reg_n_0_[3] ;
wire \axlen_cnt[0]_i_1__1_n_0 ;
wire \axlen_cnt[1]_i_1_n_0 ;
wire \axlen_cnt[2]_i_1_n_0 ;
wire \axlen_cnt[3]_i_2__0_n_0 ;
wire \axlen_cnt[4]_i_1_n_0 ;
wire \axlen_cnt[5]_i_1_n_0 ;
wire \axlen_cnt[6]_i_1_n_0 ;
wire \axlen_cnt[7]_i_2_n_0 ;
wire \axlen_cnt[7]_i_3_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[11] ;
wire \m_axi_awaddr[2] ;
wire \m_axi_awaddr[3] ;
wire [9:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire next_pending_r_i_5_n_0;
wire next_pending_r_reg_0;
wire [11:0]p_1_in;
wire sel_first_reg_0;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1
(.I0(axaddr_incr[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_7 ),
.O(p_1_in[0]));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1
(.I0(axaddr_incr[10]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_5 ),
.O(p_1_in[10]));
LUT2 #(
.INIT(4'hB))
\axaddr_incr[11]_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\state_reg[1]_rep ),
.O(\axaddr_incr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2
(.I0(axaddr_incr[11]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_4 ),
.O(p_1_in[11]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1
(.I0(axaddr_incr[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_6 ),
.O(p_1_in[1]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1
(.I0(axaddr_incr[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_5 ),
.O(p_1_in[2]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1
(.I0(axaddr_incr[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_4 ),
.O(p_1_in[3]));
LUT4 #(
.INIT(16'h0009))
\axaddr_incr[3]_i_10
(.I0(\m_payload_i_reg[46] [0]),
.I1(\state_reg[1]_rep ),
.I2(\m_payload_i_reg[46] [4]),
.I3(\m_payload_i_reg[46] [5]),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg_n_0_[3] ),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg_n_0_[2] ),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg[11]_0 [1]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_14_n_0 ));
LUT4 #(
.INIT(16'h9AAA))
\axaddr_incr[3]_i_7
(.I0(\m_payload_i_reg[46] [3]),
.I1(\state_reg[1]_rep ),
.I2(\m_payload_i_reg[46] [4]),
.I3(\m_payload_i_reg[46] [5]),
.O(S[3]));
LUT4 #(
.INIT(16'h0A9A))
\axaddr_incr[3]_i_8
(.I0(\m_payload_i_reg[46] [2]),
.I1(\state_reg[1]_rep ),
.I2(\m_payload_i_reg[46] [5]),
.I3(\m_payload_i_reg[46] [4]),
.O(S[2]));
LUT4 #(
.INIT(16'h009A))
\axaddr_incr[3]_i_9
(.I0(\m_payload_i_reg[46] [1]),
.I1(\state_reg[1]_rep ),
.I2(\m_payload_i_reg[46] [4]),
.I3(\m_payload_i_reg[46] [5]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1
(.I0(axaddr_incr[4]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_7 ),
.O(p_1_in[4]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1
(.I0(axaddr_incr[5]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_6 ),
.O(p_1_in[5]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1
(.I0(axaddr_incr[6]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_5 ),
.O(p_1_in[6]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1
(.I0(axaddr_incr[7]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_4 ),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1
(.I0(axaddr_incr[8]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_7 ),
.O(p_1_in[8]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1
(.I0(axaddr_incr[9]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_6 ),
.O(p_1_in[9]));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[0]),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[10]),
.Q(\axaddr_incr_reg[11]_0 [8]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[11]),
.Q(\axaddr_incr_reg[11]_0 [9]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4
(.CI(\axaddr_incr_reg[7]_i_3_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4_n_1 ,\axaddr_incr_reg[11]_i_4_n_2 ,\axaddr_incr_reg[11]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4_n_4 ,\axaddr_incr_reg[11]_i_4_n_5 ,\axaddr_incr_reg[11]_i_4_n_6 ,\axaddr_incr_reg[11]_i_4_n_7 }),
.S(\axaddr_incr_reg[11]_0 [9:6]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[1]),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[2]),
.Q(\axaddr_incr_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[3]),
.Q(\axaddr_incr_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3_n_0 ,\axaddr_incr_reg[3]_i_3_n_1 ,\axaddr_incr_reg[3]_i_3_n_2 ,\axaddr_incr_reg[3]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr_reg_n_0_[3] ,\axaddr_incr_reg_n_0_[2] ,\axaddr_incr_reg[11]_0 [1:0]}),
.O({\axaddr_incr_reg[3]_i_3_n_4 ,\axaddr_incr_reg[3]_i_3_n_5 ,\axaddr_incr_reg[3]_i_3_n_6 ,\axaddr_incr_reg[3]_i_3_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[4]),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[5]),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[6]),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[7]),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3
(.CI(\axaddr_incr_reg[3]_i_3_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3_n_0 ,\axaddr_incr_reg[7]_i_3_n_1 ,\axaddr_incr_reg[7]_i_3_n_2 ,\axaddr_incr_reg[7]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3_n_4 ,\axaddr_incr_reg[7]_i_3_n_5 ,\axaddr_incr_reg[7]_i_3_n_6 ,\axaddr_incr_reg[7]_i_3_n_7 }),
.S(\axaddr_incr_reg[11]_0 [5:2]));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[8]),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[9]),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
LUT6 #(
.INIT(64'h44444F4444444444))
\axlen_cnt[0]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[0] ),
.I1(\axlen_cnt_reg[0]_0 ),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(\m_payload_i_reg[46] [7]),
.O(\axlen_cnt[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1
(.I0(E),
.I1(\m_payload_i_reg[46] [8]),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1
(.I0(E),
.I1(\m_payload_i_reg[46] [9]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[4] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'h9A))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.O(\axlen_cnt[7]_i_3_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[4]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[5]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[6]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[7]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[0]_rep ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT2 #(
.INIT(4'hB))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\m_payload_i_reg[46] [6]),
.O(\m_axi_awaddr[11] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[2]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[2] ),
.I2(\m_payload_i_reg[46] [6]),
.I3(\m_payload_i_reg[46] [2]),
.O(\m_axi_awaddr[2] ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[3]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[3] ),
.I2(\m_payload_i_reg[46] [6]),
.I3(\m_payload_i_reg[46] [3]),
.O(\m_axi_awaddr[3] ));
LUT5 #(
.INIT(32'h55545555))
next_pending_r_i_4__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.I4(next_pending_r_i_5_n_0),
.O(\axlen_cnt_reg[0]_0 ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_5
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_i_5_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_incr_cmd" *)
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2
(incr_next_pending,
\axaddr_incr_reg[0]_0 ,
\axlen_cnt_reg[0]_0 ,
Q,
\m_axi_araddr[11] ,
S,
aclk,
sel_first_reg_0,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[46] ,
\state_reg[1]_rep ,
\m_payload_i_reg[44] ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
si_rs_arvalid,
\state_reg[0]_rep ,
m_valid_i_reg,
\state_reg[1] ,
sel_first_reg_1,
m_axi_arready,
\state_reg[1]_0 );
output incr_next_pending;
output \axaddr_incr_reg[0]_0 ;
output \axlen_cnt_reg[0]_0 ;
output [11:0]Q;
output \m_axi_araddr[11] ;
output [3:0]S;
input aclk;
input sel_first_reg_0;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [9:0]\m_payload_i_reg[46] ;
input \state_reg[1]_rep ;
input \m_payload_i_reg[44] ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input si_rs_arvalid;
input \state_reg[0]_rep ;
input [0:0]m_valid_i_reg;
input \state_reg[1] ;
input [0:0]sel_first_reg_1;
input m_axi_arready;
input [1:0]\state_reg[1]_0 ;
wire [0:0]E;
wire [3:0]O;
wire [11:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[0]_i_1__0_n_0 ;
wire \axaddr_incr[10]_i_1__0_n_0 ;
wire \axaddr_incr[11]_i_2__0_n_0 ;
wire \axaddr_incr[1]_i_1__0_n_0 ;
wire \axaddr_incr[2]_i_1__0_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr[3]_i_1__0_n_0 ;
wire \axaddr_incr[4]_i_1__0_n_0 ;
wire \axaddr_incr[5]_i_1__0_n_0 ;
wire \axaddr_incr[6]_i_1__0_n_0 ;
wire \axaddr_incr[7]_i_1__0_n_0 ;
wire \axaddr_incr[8]_i_1__0_n_0 ;
wire \axaddr_incr[9]_i_1__0_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire \axaddr_incr_reg[11]_i_4__0_n_1 ;
wire \axaddr_incr_reg[11]_i_4__0_n_2 ;
wire \axaddr_incr_reg[11]_i_4__0_n_3 ;
wire \axaddr_incr_reg[11]_i_4__0_n_4 ;
wire \axaddr_incr_reg[11]_i_4__0_n_5 ;
wire \axaddr_incr_reg[11]_i_4__0_n_6 ;
wire \axaddr_incr_reg[11]_i_4__0_n_7 ;
wire \axaddr_incr_reg[3]_i_3__0_n_0 ;
wire \axaddr_incr_reg[3]_i_3__0_n_1 ;
wire \axaddr_incr_reg[3]_i_3__0_n_2 ;
wire \axaddr_incr_reg[3]_i_3__0_n_3 ;
wire \axaddr_incr_reg[3]_i_3__0_n_4 ;
wire \axaddr_incr_reg[3]_i_3__0_n_5 ;
wire \axaddr_incr_reg[3]_i_3__0_n_6 ;
wire \axaddr_incr_reg[3]_i_3__0_n_7 ;
wire \axaddr_incr_reg[7]_i_3__0_n_0 ;
wire \axaddr_incr_reg[7]_i_3__0_n_1 ;
wire \axaddr_incr_reg[7]_i_3__0_n_2 ;
wire \axaddr_incr_reg[7]_i_3__0_n_3 ;
wire \axaddr_incr_reg[7]_i_3__0_n_4 ;
wire \axaddr_incr_reg[7]_i_3__0_n_5 ;
wire \axaddr_incr_reg[7]_i_3__0_n_6 ;
wire \axaddr_incr_reg[7]_i_3__0_n_7 ;
wire \axlen_cnt[0]_i_1_n_0 ;
wire \axlen_cnt[1]_i_1__1_n_0 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_2__1_n_0 ;
wire \axlen_cnt[4]_i_1__2_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[11] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire [9:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__1_n_0;
wire next_pending_r_i_4_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire [0:0]sel_first_reg_1;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_7 ),
.O(\axaddr_incr[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1__0
(.I0(O[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_5 ),
.O(\axaddr_incr[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2__0
(.I0(O[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_4 ),
.O(\axaddr_incr[11]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_6 ),
.O(\axaddr_incr[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_5 ),
.O(\axaddr_incr[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0202010202020202))
\axaddr_incr[3]_i_10
(.I0(\m_payload_i_reg[46] [0]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(Q[3]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(Q[2]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(Q[1]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(Q[0]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.O(\axaddr_incr[3]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_4 ),
.O(\axaddr_incr[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA6AAAAAAAAAAA))
\axaddr_incr[3]_i_7
(.I0(\m_payload_i_reg[46] [3]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[3]));
LUT6 #(
.INIT(64'h2A2A262A2A2A2A2A))
\axaddr_incr[3]_i_8
(.I0(\m_payload_i_reg[46] [2]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [4]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[2]));
LUT6 #(
.INIT(64'h0A0A060A0A0A0A0A))
\axaddr_incr[3]_i_9
(.I0(\m_payload_i_reg[46] [1]),
.I1(\m_payload_i_reg[46] [4]),
.I2(\m_payload_i_reg[46] [5]),
.I3(m_axi_arready),
.I4(\state_reg[1]_0 [1]),
.I5(\state_reg[1]_0 [0]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1__0
(.I0(\m_payload_i_reg[7] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_7 ),
.O(\axaddr_incr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1__0
(.I0(\m_payload_i_reg[7] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_6 ),
.O(\axaddr_incr[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1__0
(.I0(\m_payload_i_reg[7] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_5 ),
.O(\axaddr_incr[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1__0
(.I0(\m_payload_i_reg[7] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_4 ),
.O(\axaddr_incr[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1__0
(.I0(O[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_7 ),
.O(\axaddr_incr[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1__0
(.I0(O[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_6 ),
.O(\axaddr_incr[9]_i_1__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[11]_i_2__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4__0
(.CI(\axaddr_incr_reg[7]_i_3__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4__0_n_1 ,\axaddr_incr_reg[11]_i_4__0_n_2 ,\axaddr_incr_reg[11]_i_4__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4__0_n_4 ,\axaddr_incr_reg[11]_i_4__0_n_5 ,\axaddr_incr_reg[11]_i_4__0_n_6 ,\axaddr_incr_reg[11]_i_4__0_n_7 }),
.S(Q[11:8]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3__0_n_0 ,\axaddr_incr_reg[3]_i_3__0_n_1 ,\axaddr_incr_reg[3]_i_3__0_n_2 ,\axaddr_incr_reg[3]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI(Q[3:0]),
.O({\axaddr_incr_reg[3]_i_3__0_n_4 ,\axaddr_incr_reg[3]_i_3__0_n_5 ,\axaddr_incr_reg[3]_i_3__0_n_6 ,\axaddr_incr_reg[3]_i_3__0_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3__0
(.CI(\axaddr_incr_reg[3]_i_3__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3__0_n_0 ,\axaddr_incr_reg[7]_i_3__0_n_1 ,\axaddr_incr_reg[7]_i_3__0_n_2 ,\axaddr_incr_reg[7]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3__0_n_4 ,\axaddr_incr_reg[7]_i_3__0_n_5 ,\axaddr_incr_reg[7]_i_3__0_n_6 ,\axaddr_incr_reg[7]_i_3__0_n_7 }),
.S(Q[7:4]));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h20FF2020))
\axlen_cnt[0]_i_1
(.I0(si_rs_arvalid),
.I1(\state_reg[0]_rep ),
.I2(\m_payload_i_reg[46] [7]),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[46] [8]),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[1]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[46] [9]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_2__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h55545555))
\axlen_cnt[3]_i_3__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.I4(next_pending_r_i_4_n_0),
.O(\axlen_cnt_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[4]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[4] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hA6))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt[7]_i_3__0_n_0 ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_2__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[1] ));
LUT2 #(
.INIT(4'hB))
\m_axi_araddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\m_payload_i_reg[46] [6]),
.O(\m_axi_araddr[11] ));
LUT5 #(
.INIT(32'hFFFF505C))
next_pending_r_i_1__2
(.I0(next_pending_r_i_2__1_n_0),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(E),
.I4(\m_payload_i_reg[44] ),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0002))
next_pending_r_i_2__1
(.I0(next_pending_r_i_4_n_0),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[6] ),
.O(next_pending_r_i_2__1_n_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_4
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_4_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel
(m_valid_i_reg,
\state_reg[1]_rep ,
m_axi_rready,
out,
\skid_buffer_reg[46] ,
r_push,
aclk,
r_rlast,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output m_axi_rready;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input r_push;
input aclk;
input r_rlast;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_3;
wire rd_data_fifo_0_n_5;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire [12:0]trans_in;
wire transaction_fifo_0_n_2;
wire wr_en0;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_push),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[3]_rep__0_0 (m_valid_i_reg),
.\cnt_read_reg[3]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_3),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.s_ready_i_reg_0(transaction_fifo_0_n_2),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_5),
.wr_en0(wr_en0));
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__2 (rd_data_fifo_0_n_5),
.\cnt_read_reg[2]_rep__2 (rd_data_fifo_0_n_3),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (transaction_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wr_en0(wr_en0));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm
(\axlen_cnt_reg[7] ,
Q,
D,
\wrap_cnt_r_reg[0] ,
\axaddr_offset_r_reg[0] ,
E,
\wrap_second_len_r_reg[3] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
s_axburst_eq1_reg,
r_push_r_reg,
\axlen_cnt_reg[4] ,
sel_first_reg,
sel_first_reg_0,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\axaddr_incr_reg[0] ,
m_axi_arvalid,
m_valid_i0,
\m_payload_i_reg[0]_1 ,
m_axi_arready,
si_rs_arvalid,
\axlen_cnt_reg[6] ,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[2] ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[47] ,
\m_payload_i_reg[35]_0 ,
\axaddr_offset_r_reg[3] ,
\m_payload_i_reg[44] ,
\m_payload_i_reg[3] ,
incr_next_pending,
\m_payload_i_reg[44]_0 ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
sel_first_reg_1,
areset_d1,
sel_first,
sel_first_reg_2,
s_axi_arvalid,
s_ready_i_reg,
aclk);
output \axlen_cnt_reg[7] ;
output [1:0]Q;
output [2:0]D;
output \wrap_cnt_r_reg[0] ;
output [0:0]\axaddr_offset_r_reg[0] ;
output [0:0]E;
output [1:0]\wrap_second_len_r_reg[3] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output s_axburst_eq1_reg;
output r_push_r_reg;
output [0:0]\axlen_cnt_reg[4] ;
output sel_first_reg;
output sel_first_reg_0;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [0:0]\axaddr_incr_reg[0] ;
output m_axi_arvalid;
output m_valid_i0;
output [0:0]\m_payload_i_reg[0]_1 ;
input m_axi_arready;
input si_rs_arvalid;
input \axlen_cnt_reg[6] ;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__0 ;
input [1:0]\wrap_second_len_r_reg[3]_0 ;
input [1:0]\wrap_second_len_r_reg[2] ;
input \m_payload_i_reg[35] ;
input [1:0]\m_payload_i_reg[47] ;
input \m_payload_i_reg[35]_0 ;
input [1:0]\axaddr_offset_r_reg[3] ;
input [1:0]\m_payload_i_reg[44] ;
input \m_payload_i_reg[3] ;
input incr_next_pending;
input \m_payload_i_reg[44]_0 ;
input \axlen_cnt_reg[3] ;
input next_pending_r_reg;
input sel_first_reg_1;
input areset_d1;
input sel_first;
input sel_first_reg_2;
input s_axi_arvalid;
input s_ready_i_reg;
input aclk;
wire [2:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [0:0]\axaddr_incr_reg[0] ;
wire [0:0]\axaddr_offset_r_reg[0] ;
wire [1:0]\axaddr_offset_r_reg[3] ;
wire \axlen_cnt_reg[3] ;
wire [0:0]\axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[6] ;
wire \axlen_cnt_reg[7] ;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [1:0]\m_payload_i_reg[44] ;
wire \m_payload_i_reg[44]_0 ;
wire [1:0]\m_payload_i_reg[47] ;
wire m_valid_i0;
wire next_pending_r_reg;
wire [1:0]next_state;
wire r_push_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire s_axi_arvalid;
wire s_ready_i_reg;
wire sel_first;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire \wrap_cnt_r[3]_i_2__0_n_0 ;
wire \wrap_cnt_r_reg[0] ;
wire wrap_next_pending;
wire [1:0]\wrap_second_len_r_reg[2] ;
wire [1:0]\wrap_second_len_r_reg[3] ;
wire [1:0]\wrap_second_len_r_reg[3]_0 ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAEAA))
\axaddr_incr[11]_i_1__0
(.I0(sel_first),
.I1(\m_payload_i_reg[0]_0 ),
.I2(\m_payload_i_reg[0] ),
.I3(m_axi_arready),
.O(\axaddr_incr_reg[0] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [0]),
.I1(\m_payload_i_reg[44] [1]),
.I2(Q[0]),
.I3(si_rs_arvalid),
.I4(Q[1]),
.I5(\m_payload_i_reg[3] ),
.O(\axaddr_offset_r_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h0E02))
\axlen_cnt[3]_i_1
(.I0(si_rs_arvalid),
.I1(Q[0]),
.I2(Q[1]),
.I3(m_axi_arready),
.O(\axlen_cnt_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00002320))
\axlen_cnt[7]_i_1
(.I0(m_axi_arready),
.I1(Q[1]),
.I2(Q[0]),
.I3(si_rs_arvalid),
.I4(\axlen_cnt_reg[6] ),
.O(\axlen_cnt_reg[7] ));
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[31]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.O(\m_payload_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFF70FFFF))
m_valid_i_i_1__1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.I3(s_axi_arvalid),
.I4(s_ready_i_reg),
.O(m_valid_i0));
LUT5 #(
.INIT(32'hFFABEEAA))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[44]_0 ),
.I1(r_push_r_reg),
.I2(E),
.I3(\axlen_cnt_reg[3] ),
.I4(next_pending_r_reg),
.O(wrap_next_pending));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h20))
r_push_r_i_1
(.I0(m_axi_arready),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[44] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[44] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__2
(.I0(m_axi_arready),
.I1(sel_first_reg_1),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__4
(.I0(m_axi_arready),
.I1(sel_first_reg_2),
.I2(\m_payload_i_reg[0] ),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_i));
LUT6 #(
.INIT(64'h0000770000FFFFF0))
\state[0]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(m_axi_arready),
.I2(si_rs_arvalid),
.I3(Q[0]),
.I4(Q[1]),
.I5(\cnt_read_reg[1]_rep__0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h0FC00040))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.I4(\cnt_read_reg[1]_rep__0 ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(E));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(\axaddr_offset_r_reg[0] ),
.O(D[0]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[2] [1]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(E),
.I3(\wrap_cnt_r_reg[0] ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\wrap_second_len_r_reg[2] [0]),
.O(D[1]));
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_second_len_r_reg[2] [0]),
.I2(\wrap_cnt_r[3]_i_2__0_n_0 ),
.I3(\wrap_second_len_r_reg[2] [1]),
.O(D[2]));
LUT6 #(
.INIT(64'hD1D1D1D1D1D1DFD1))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[47] [1]),
.I5(\m_payload_i_reg[47] [0]),
.O(\wrap_cnt_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(\axaddr_offset_r_reg[0] ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'h0000000004000404))
\wrap_second_len_r[0]_i_2__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(\m_payload_i_reg[35] ),
.I2(\m_payload_i_reg[35]_0 ),
.I3(E),
.I4(\axaddr_offset_r_reg[3] [1]),
.I5(\m_payload_i_reg[47] [0]),
.O(\wrap_cnt_r_reg[0] ));
LUT6 #(
.INIT(64'hFB00FFFFFB00FB00))
\wrap_second_len_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(\m_payload_i_reg[35] ),
.I2(\m_payload_i_reg[47] [0]),
.I3(\m_payload_i_reg[35]_0 ),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__0_0 ,
\state_reg[0]_rep ,
bvalid_i_reg,
SR,
D,
bresp_push,
out,
b_push,
shandshake_r,
areset_d1,
si_rs_bvalid,
si_rs_bready,
Q,
\bresp_cnt_reg[7] ,
mhandshake_r,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__0_0 ;
output \state_reg[0]_rep ;
output bvalid_i_reg;
output [0:0]SR;
output [0:0]D;
output bresp_push;
output [11:0]out;
input b_push;
input shandshake_r;
input areset_d1;
input si_rs_bvalid;
input si_rs_bready;
input [1:0]Q;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input [15:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire \bresp_cnt[7]_i_3_n_0 ;
wire \bresp_cnt[7]_i_4_n_0 ;
wire \bresp_cnt[7]_i_5_n_0 ;
wire \bresp_cnt[7]_i_6_n_0 ;
wire [7:0]\bresp_cnt_reg[7] ;
wire bresp_push;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [15:0]in;
wire \memory_reg[3][0]_srl4_i_2__0_n_0 ;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire \state_reg[0]_rep ;
LUT5 #(
.INIT(32'hAAABAAAA))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(\bresp_cnt[7]_i_4_n_0 ),
.I3(\bresp_cnt[7]_i_5_n_0 ),
.I4(\bresp_cnt[7]_i_6_n_0 ),
.O(SR));
LUT6 #(
.INIT(64'h22F2FFFF22F222F2))
\bresp_cnt[7]_i_3
(.I0(\memory_reg[3][1]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [1]),
.I2(\bresp_cnt_reg[7] [3]),
.I3(\memory_reg[3][3]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [0]),
.I5(\memory_reg[3][0]_srl4_n_0 ),
.O(\bresp_cnt[7]_i_3_n_0 ));
LUT5 #(
.INIT(32'hAEAEFFAE))
\bresp_cnt[7]_i_4
(.I0(\bresp_cnt_reg[7] [4]),
.I1(\bresp_cnt_reg[7] [1]),
.I2(\memory_reg[3][1]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [0]),
.I4(\memory_reg[3][0]_srl4_n_0 ),
.O(\bresp_cnt[7]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT5 #(
.INIT(32'hEAFFEAEA))
\bresp_cnt[7]_i_5
(.I0(\bresp_cnt_reg[7] [6]),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.I2(\cnt_read_reg[1]_rep__0_0 ),
.I3(\bresp_cnt_reg[7] [3]),
.I4(\memory_reg[3][3]_srl4_n_0 ),
.O(\bresp_cnt[7]_i_5_n_0 ));
LUT5 #(
.INIT(32'h00004004))
\bresp_cnt[7]_i_6
(.I0(\bresp_cnt_reg[7] [5]),
.I1(mhandshake_r),
.I2(\bresp_cnt_reg[7] [2]),
.I3(\memory_reg[3][2]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [7]),
.O(\bresp_cnt[7]_i_6_n_0 ));
LUT4 #(
.INIT(16'h0444))
bvalid_i_i_1
(.I0(areset_d1),
.I1(bvalid_i_i_2_n_0),
.I2(si_rs_bvalid),
.I3(si_rs_bready),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(\cnt_read_reg[1]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[0]),
.I4(Q[1]),
.I5(si_rs_bvalid),
.O(bvalid_i_i_2_n_0));
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1
(.I0(bresp_push),
.I1(Q[0]),
.I2(shandshake_r),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
LUT6 #(
.INIT(64'h0000000000004100))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\bresp_cnt_reg[7] [7]),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\bresp_cnt_reg[7] [2]),
.I3(mhandshake_r),
.I4(\bresp_cnt_reg[7] [5]),
.I5(\memory_reg[3][0]_srl4_i_2__0_n_0 ),
.O(bresp_push));
LUT6 #(
.INIT(64'hFFFEFFFFFFFEFFFE))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\bresp_cnt[7]_i_3_n_0 ),
.I1(\bresp_cnt[7]_i_4_n_0 ),
.I2(\bresp_cnt_reg[7] [6]),
.I3(\memory_reg[3][0]_srl4_i_3_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][3]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT2 #(
.INIT(4'h8))
\memory_reg[3][0]_srl4_i_3
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(\cnt_read_reg[1]_rep__0_0 ),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(out[1]));
LUT2 #(
.INIT(4'h2))
\state[0]_i_2
(.I0(\cnt_read_reg[1]_rep__0_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.O(\state_reg[0]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_simple_fifo" *)
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0
(mhandshake,
Q,
m_axi_bready,
\skid_buffer_reg[1] ,
m_axi_bvalid,
mhandshake_r,
shandshake_r,
sel,
in,
aclk,
areset_d1,
D);
output mhandshake;
output [1:0]Q;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input m_axi_bvalid;
input mhandshake_r;
input shandshake_r;
input sel;
input [1:0]in;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire sel;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT4 #(
.INIT(16'h9AA6))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(shandshake_r),
.I2(Q[0]),
.I3(sel),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[0]),
.I1(Q[1]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[1]),
.I3(Q[0]),
.O(mhandshake));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_simple_fifo" *)
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1
(\cnt_read_reg[3]_rep__2_0 ,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
si_rs_rready,
\cnt_read_reg[3]_rep__0_0 ,
s_ready_i_reg_0,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[3]_rep__2_0 ;
output wr_en0;
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input si_rs_rready;
input \cnt_read_reg[3]_rep__0_0 ;
input s_ready_i_reg_0;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_2__0_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep__2_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(wr_en0),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hA96A))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(wr_en0),
.I3(s_ready_i_reg),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hA6AAAA9A))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(wr_en0),
.I2(s_ready_i_reg),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.I4(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA96AAAAAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[0]_rep__2_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(wr_en0),
.I5(s_ready_i_reg),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAA55AA6A6AAA6AAA))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read[4]_i_2__0_n_0 ),
.I2(\cnt_read[4]_i_3_n_0 ),
.I3(s_ready_i_reg_0),
.I4(\cnt_read_reg[4]_rep__2_1 ),
.I5(\cnt_read_reg[3]_rep__2_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0004))
\cnt_read[4]_i_2__0
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(si_rs_rready),
.I2(\cnt_read_reg[3]_rep__0_0 ),
.I3(wr_en0),
.O(\cnt_read[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_3
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_1 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hF77F777F))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read_reg[3]_rep__2_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hAA2A2AAA2A2A2AAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[3]_rep__2_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[1]_rep__2_n_0 ),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h7C000000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.I3(\cnt_read_reg[3]_rep__2_0 ),
.I4(\cnt_read_reg[4]_rep__2_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_simple_fifo" *)
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2
(m_valid_i_reg,
\state_reg[1]_rep ,
\cnt_read_reg[4]_rep__2 ,
\skid_buffer_reg[46] ,
si_rs_rready,
r_push_r,
s_ready_i_reg,
\cnt_read_reg[0]_rep__2 ,
wr_en0,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[2]_rep__2 ,
in,
aclk,
areset_d1);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output \cnt_read_reg[4]_rep__2 ;
output [12:0]\skid_buffer_reg[46] ;
input si_rs_rready;
input r_push_r;
input s_ready_i_reg;
input \cnt_read_reg[0]_rep__2 ;
input wr_en0;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[4]_rep__2_0 ;
input \cnt_read_reg[2]_rep__2 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__2 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_i_3_n_0;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__1_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[0]_rep__1_n_0 ),
.I1(r_push_r),
.I2(s_ready_i_reg),
.I3(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[1]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hFE7F0180))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hDFFFFFFB20000004))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[2]_rep__0_n_0 ),
.I5(\cnt_read_reg[3]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h9AAA9AAA9AAA9AA6))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read_reg[2]_rep__0_n_0 ),
.I3(\cnt_read_reg[3]_rep__0_n_0 ),
.I4(\cnt_read[4]_i_3__0_n_0 ),
.I5(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h5DFFFFFF))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(r_push_r),
.I4(\cnt_read_reg[0]_rep__1_n_0 ),
.O(\cnt_read[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'hFFEF))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(m_valid_i_reg),
.I2(si_rs_rready),
.I3(r_push_r),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h4F))
\cnt_read[4]_i_4
(.I0(m_valid_i_reg),
.I1(si_rs_rready),
.I2(wr_en0),
.O(\cnt_read_reg[4]_rep__2 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT6 #(
.INIT(64'hFF08080808080808))
m_valid_i_i_2
(.I0(\cnt_read_reg[3]_rep__0_n_0 ),
.I1(\cnt_read_reg[4]_rep__0_n_0 ),
.I2(m_valid_i_i_3_n_0),
.I3(\cnt_read_reg[3]_rep__2 ),
.I4(\cnt_read_reg[4]_rep__2_0 ),
.I5(\cnt_read_reg[2]_rep__2 ),
.O(m_valid_i_reg));
LUT3 #(
.INIT(8'h7F))
m_valid_i_i_3
(.I0(\cnt_read_reg[0]_rep__1_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.O(m_valid_i_i_3_n_0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBEAAAAAAFEAAAAAA))
\state[1]_i_3
(.I0(\cnt_read_reg[0]_rep__2 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[2]_rep__0_n_0 ),
.I3(\cnt_read_reg[4]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm
(E,
Q,
\axlen_cnt_reg[0] ,
\wrap_boundary_axaddr_r_reg[0] ,
\axlen_cnt_reg[7] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
sel_first_reg,
sel_first_reg_0,
m_axi_awvalid,
\m_payload_i_reg[0] ,
b_push,
si_rs_awvalid,
\axlen_cnt_reg[6] ,
\m_payload_i_reg[39] ,
\m_payload_i_reg[46] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axlen_cnt_reg[1] ,
sel_first,
areset_d1,
sel_first_0,
sel_first_reg_1,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__0 ,
m_axi_awready,
\cnt_read_reg[1]_rep__0_0 ,
\cnt_read_reg[0]_rep__0 ,
aclk);
output [0:0]E;
output [1:0]Q;
output \axlen_cnt_reg[0] ;
output [0:0]\wrap_boundary_axaddr_r_reg[0] ;
output \axlen_cnt_reg[7] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output sel_first_reg;
output sel_first_reg_0;
output m_axi_awvalid;
output [0:0]\m_payload_i_reg[0] ;
output b_push;
input si_rs_awvalid;
input \axlen_cnt_reg[6] ;
input [0:0]\m_payload_i_reg[39] ;
input \m_payload_i_reg[46] ;
input next_pending_r_reg;
input next_pending_r_reg_0;
input \axlen_cnt_reg[1] ;
input sel_first;
input areset_d1;
input sel_first_0;
input sel_first_reg_1;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__0 ;
input m_axi_awready;
input \cnt_read_reg[1]_rep__0_0 ;
input \cnt_read_reg[0]_rep__0 ;
input aclk;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axlen_cnt_reg[0] ;
wire \axlen_cnt_reg[1] ;
wire \axlen_cnt_reg[6] ;
wire \axlen_cnt_reg[7] ;
wire b_push;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]\m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[39] ;
wire \m_payload_i_reg[46] ;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [1:0]next_state;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire si_rs_awvalid;
wire \state_reg[0]_rep_n_0 ;
wire \state_reg[1]_rep_n_0 ;
wire [0:0]\wrap_boundary_axaddr_r_reg[0] ;
wire wrap_next_pending;
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'h04FF))
\axlen_cnt[3]_i_1__0
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[0] ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT5 #(
.INIT(32'h000004FF))
\axlen_cnt[7]_i_1__0
(.I0(\state_reg[0]_rep_n_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[1]_rep_n_0 ),
.I3(\axlen_cnt_reg[0] ),
.I4(\axlen_cnt_reg[6] ),
.O(\axlen_cnt_reg[7] ));
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(\state_reg[0]_rep_n_0 ),
.I1(\state_reg[1]_rep_n_0 ),
.O(m_axi_awvalid));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(b_push),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0] ));
LUT6 #(
.INIT(64'hCFCF000045000000))
\memory_reg[3][0]_srl4_i_1
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[0]_rep__0 ),
.I2(\cnt_read_reg[1]_rep__0_0 ),
.I3(m_axi_awready),
.I4(\state_reg[0]_rep_n_0 ),
.I5(\state_reg[1]_rep_n_0 ),
.O(b_push));
LUT5 #(
.INIT(32'hB8BBB888))
next_pending_r_i_1
(.I0(\m_payload_i_reg[46] ),
.I1(\wrap_boundary_axaddr_r_reg[0] ),
.I2(next_pending_r_reg),
.I3(\axlen_cnt_reg[0] ),
.I4(\axlen_cnt_reg[6] ),
.O(incr_next_pending));
LUT5 #(
.INIT(32'hB888B8BB))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[46] ),
.I1(\wrap_boundary_axaddr_r_reg[0] ),
.I2(next_pending_r_reg_0),
.I3(\axlen_cnt_reg[0] ),
.I4(\axlen_cnt_reg[1] ),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'h5555DD551515DD15))
next_pending_r_i_3
(.I0(\state_reg[1]_rep_n_0 ),
.I1(\state_reg[0]_rep_n_0 ),
.I2(m_axi_awready),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.I4(\cnt_read_reg[0]_rep__0 ),
.I5(s_axburst_eq1_reg_0),
.O(\axlen_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[39] ),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[39] ),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFFFFFFF88888F88))
sel_first_i_1
(.I0(\axlen_cnt_reg[0] ),
.I1(sel_first),
.I2(\state_reg[1]_rep_n_0 ),
.I3(si_rs_awvalid),
.I4(\state_reg[0]_rep_n_0 ),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF88888F88))
sel_first_i_1__0
(.I0(\axlen_cnt_reg[0] ),
.I1(sel_first_0),
.I2(\state_reg[1]_rep_n_0 ),
.I3(si_rs_awvalid),
.I4(\state_reg[0]_rep_n_0 ),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFFFFFFFF88888F88))
sel_first_i_1__1
(.I0(\axlen_cnt_reg[0] ),
.I1(sel_first_reg_1),
.I2(\state_reg[1]_rep_n_0 ),
.I3(si_rs_awvalid),
.I4(\state_reg[0]_rep_n_0 ),
.I5(areset_d1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hAEFE0E0EFEFE5E5E))
\state[0]_i_1
(.I0(\state_reg[1]_rep_n_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[0]_rep_n_0 ),
.I3(s_axburst_eq1_reg_0),
.I4(\cnt_read_reg[1]_rep__0 ),
.I5(m_axi_awready),
.O(next_state[0]));
LUT6 #(
.INIT(64'h2E220E0000000000))
\state[1]_i_1
(.I0(m_axi_awready),
.I1(\state_reg[1]_rep_n_0 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.I4(s_axburst_eq1_reg_0),
.I5(\state_reg[0]_rep_n_0 ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\state_reg[0]_rep_n_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\state_reg[1]_rep_n_0 ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\state_reg[1]_rep_n_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[0]_rep_n_0 ),
.O(\wrap_boundary_axaddr_r_reg[0] ));
endmodule
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
Q,
si_rs_awvalid,
\m_payload_i_reg[46] ,
\m_payload_i_reg[47] ,
\state_reg[1]_rep ,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
sel_first_reg_3,
sel_first_reg_4,
D,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[0] ,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [1:0]Q;
input si_rs_awvalid;
input [17:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[47] ;
input \state_reg[1]_rep ;
input sel_first_reg_2;
input [9:0]\axaddr_incr_reg[11] ;
input sel_first_reg_3;
input sel_first_reg_4;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire [9:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_3_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_2_n_1 ;
wire \axaddr_wrap_reg[11]_i_2_n_2 ;
wire \axaddr_wrap_reg[11]_i_2_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_2_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire [11:0]m_axi_awaddr;
wire [17:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[1]_rep ;
wire [11:0]wrap_boundary_axaddr_r;
wire [3:0]wrap_cnt_r;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[0]_i_1
(.I0(\m_payload_i_reg[46] [0]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[0]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[10]_i_1
(.I0(\m_payload_i_reg[46] [10]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[10]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[11]_i_1
(.I0(\m_payload_i_reg[46] [11]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[11]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFFF6))
\axaddr_wrap[11]_i_3
(.I0(wrap_cnt_r[3]),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axaddr_wrap[11]_i_4_n_0 ),
.I3(\axlen_cnt_reg_n_0_[4] ),
.O(\axaddr_wrap[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(wrap_cnt_r[1]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(wrap_cnt_r[2]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[1]_i_1
(.I0(\m_payload_i_reg[46] [1]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[1]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[2]_i_1
(.I0(\m_payload_i_reg[46] [2]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[2]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[3]_i_1
(.I0(\m_payload_i_reg[46] [3]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[3]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[46] [13]),
.I2(\m_payload_i_reg[46] [12]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[46] [12]),
.I2(\m_payload_i_reg[46] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[46] [13]),
.I2(\m_payload_i_reg[46] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[46] [13]),
.I2(\m_payload_i_reg[46] [12]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[4]_i_1
(.I0(\m_payload_i_reg[46] [4]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[4]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[5]_i_1
(.I0(\m_payload_i_reg[46] [5]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[5]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[6]_i_1
(.I0(\m_payload_i_reg[46] [6]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[6]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[7]_i_1
(.I0(\m_payload_i_reg[46] [7]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[7]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[8]_i_1
(.I0(\m_payload_i_reg[46] [8]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[8]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\axaddr_wrap[9]_i_1
(.I0(\m_payload_i_reg[46] [9]),
.I1(\state_reg[1]_rep ),
.I2(axaddr_wrap0[9]),
.I3(\axaddr_wrap[11]_i_3_n_0 ),
.I4(wrap_boundary_axaddr_r[9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_2
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_2_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_2_n_1 ,\axaddr_wrap_reg[11]_i_2_n_2 ,\axaddr_wrap_reg[11]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S(axaddr_wrap[11:8]));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S(axaddr_wrap[7:4]));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h44444F4444444444))
\axlen_cnt[0]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[0] ),
.I1(\axlen_cnt[3]_i_2_n_0 ),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(\m_payload_i_reg[46] [15]),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[46] [16]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt[3]_i_2_n_0 ),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[46] [17]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt[3]_i_2_n_0 ),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt[3]_i_2_n_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT5 #(
.INIT(32'h55555554))
\axlen_cnt[3]_i_2
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h4444444444444440))
\axlen_cnt[4]_i_1__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [8]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [9]),
.O(m_axi_awaddr[11]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[1]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [1]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_awaddr[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[2]_INST_0
(.I0(\m_payload_i_reg[46] [2]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[2]),
.I3(\m_payload_i_reg[46] [14]),
.I4(sel_first_reg_4),
.O(m_axi_awaddr[2]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[3]_INST_0
(.I0(\m_payload_i_reg[46] [3]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[3]),
.I3(\m_payload_i_reg[46] [14]),
.I4(sel_first_reg_3),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[5]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [5]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[46] [14]),
.I3(\m_payload_i_reg[46] [9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_awaddr[9]));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_2__0
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[46] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_wrap_cmd" *)
module led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3
(next_pending_r_reg_0,
sel_first_reg_0,
\axlen_cnt_reg[0]_0 ,
m_axi_araddr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
Q,
\state_reg[1]_rep ,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
si_rs_arvalid,
\state_reg[0]_rep ,
\axaddr_offset_r_reg[3]_1 ,
\m_payload_i_reg[35] ,
D,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output \axlen_cnt_reg[0]_0 ;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input \m_payload_i_reg[47] ;
input [17:0]Q;
input \state_reg[1]_rep ;
input sel_first_reg_2;
input [11:0]\axaddr_incr_reg[11] ;
input si_rs_arvalid;
input \state_reg[0]_rep ;
input \axaddr_offset_r_reg[3]_1 ;
input \m_payload_i_reg[35] ;
input [3:0]D;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [17:0]Q;
wire aclk;
wire [11:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_3__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__0_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__2_n_0 ;
wire \axlen_cnt[4]_i_1__1_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r[1]_i_1_n_0 ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I3(\state_reg[1]_rep ),
.I4(Q[0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_5 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I3(\state_reg[1]_rep ),
.I4(Q[10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_4 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I3(\state_reg[1]_rep ),
.I4(Q[11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'hFFF6))
\axaddr_wrap[11]_i_3__0
(.I0(\wrap_cnt_r_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axaddr_wrap[11]_i_4__0_n_0 ),
.I3(\axlen_cnt_reg_n_0_[4] ),
.O(\axaddr_wrap[11]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\wrap_cnt_r_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\wrap_cnt_r_reg_n_0_[1] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I3(\state_reg[1]_rep ),
.I4(Q[1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I3(\state_reg[1]_rep ),
.I4(Q[2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I3(\state_reg[1]_rep ),
.I4(Q[3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I3(\state_reg[1]_rep ),
.I4(Q[4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I3(\state_reg[1]_rep ),
.I4(Q[5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I3(\state_reg[1]_rep ),
.I4(Q[6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I3(\state_reg[1]_rep ),
.I4(Q[7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_7 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I3(\state_reg[1]_rep ),
.I4(Q[8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\axaddr_wrap_reg[11]_i_2__0_n_6 ),
.I1(\axaddr_wrap[11]_i_3__0_n_0 ),
.I2(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I3(\state_reg[1]_rep ),
.I4(Q[9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_2__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_2__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_2__0_n_1 ,\axaddr_wrap_reg[11]_i_2__0_n_2 ,\axaddr_wrap_reg[11]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_2__0_n_4 ,\axaddr_wrap_reg[11]_i_2__0_n_5 ,\axaddr_wrap_reg[11]_i_2__0_n_6 ,\axaddr_wrap_reg[11]_i_2__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[11] ,\axaddr_wrap_reg_n_0_[10] ,\axaddr_wrap_reg_n_0_[9] ,\axaddr_wrap_reg_n_0_[8] }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[7] ,\axaddr_wrap_reg_n_0_[6] ,\axaddr_wrap_reg_n_0_[5] ,\axaddr_wrap_reg_n_0_[4] }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h20FF2020))
\axlen_cnt[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(\state_reg[0]_rep ),
.I2(Q[15]),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__2
(.I0(E),
.I1(Q[16]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__2
(.I0(E),
.I1(Q[17]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h55555554))
\axlen_cnt[3]_i_2__2
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt_reg[0]_0 ));
LUT6 #(
.INIT(64'h4444444444444440))
\axlen_cnt[4]_i_1__1
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1__1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(Q[14]),
.I3(Q[0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(Q[14]),
.I3(Q[10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [10]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(Q[14]),
.I3(Q[11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [11]),
.O(m_axi_araddr[11]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[1] ),
.I2(Q[14]),
.I3(Q[1]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_araddr[1]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[2] ),
.I2(Q[14]),
.I3(Q[2]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[3] ),
.I2(Q[14]),
.I3(Q[3]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(Q[14]),
.I3(Q[4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_araddr[4]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[5] ),
.I2(Q[14]),
.I3(Q[5]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(Q[14]),
.I3(Q[6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(Q[14]),
.I3(Q[7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(Q[14]),
.I3(Q[8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [8]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(Q[14]),
.I3(Q[9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [9]),
.O(m_axi_araddr[9]));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(Q[10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(Q[11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(Q[7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(Q[8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(Q[9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h313D020E))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_1 ),
.I3(\m_payload_i_reg[35] ),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_cnt_r[1]_i_1_n_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_cnt_r[1]_i_1_n_0 ),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
module led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
D,
wrap_second_len,
axaddr_incr,
Q,
\axaddr_incr_reg[3] ,
\s_arid_r_reg[11] ,
\axaddr_incr_reg[7] ,
O,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
shandshake,
\wrap_second_len_r_reg[2] ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
next_pending_r_reg_0,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3]_0 ,
\cnt_read_reg[0]_rep__1 ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
m_valid_i0,
aresetn,
\cnt_read_reg[3]_rep__0 ,
s_axi_rready,
S,
\m_payload_i_reg[3] ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1] ,
\axaddr_offset_r_reg[3]_0 ,
s_axi_awvalid,
b_push,
si_rs_bvalid,
axaddr_offset_0,
\state_reg[1]_rep_0 ,
\wrap_second_len_r_reg[2]_0 ,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[1]_rep_1 ,
\state_reg[0]_rep ,
s_axi_bready,
s_axi_arvalid,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
E,
\state_reg[1]_rep_2 );
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output [3:0]D;
output [3:0]wrap_second_len;
output [11:0]axaddr_incr;
output [54:0]Q;
output [3:0]\axaddr_incr_reg[3] ;
output [53:0]\s_arid_r_reg[11] ;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [3:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output shandshake;
output [1:0]\wrap_second_len_r_reg[2] ;
output [2:0]\axaddr_offset_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output next_pending_r_reg_0;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3]_0 ;
output \cnt_read_reg[0]_rep__1 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input m_valid_i0;
input aresetn;
input \cnt_read_reg[3]_rep__0 ;
input s_axi_rready;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input \state_reg[1]_rep ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [1:0]\state_reg[1] ;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input s_axi_awvalid;
input b_push;
input si_rs_bvalid;
input [0:0]axaddr_offset_0;
input \state_reg[1]_rep_0 ;
input [1:0]\wrap_second_len_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[1]_rep_1 ;
input \state_reg[0]_rep ;
input s_axi_bready;
input s_axi_arvalid;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [0:0]E;
input [0:0]\state_reg[1]_rep_2 ;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [3:0]axaddr_offset;
wire [0:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [2:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[0]_rep__1 ;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \gen_simple_ar.ar_pipe_n_2 ;
wire \gen_simple_aw.aw_pipe_n_1 ;
wire \gen_simple_aw.aw_pipe_n_91 ;
wire [3:0]\m_payload_i_reg[3] ;
wire m_valid_i0;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [53:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire shandshake;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire [0:0]\state_reg[1]_rep_2 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire [3:0]wrap_second_len;
wire [1:0]\wrap_second_len_r_reg[2] ;
wire [1:0]\wrap_second_len_r_reg[2]_0 ;
wire \wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice \gen_simple_ar.ar_pipe
(.O(O),
.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (\gen_simple_aw.aw_pipe_n_1 ),
.\aresetn_d_reg[0]_0 (\gen_simple_aw.aw_pipe_n_91 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.axaddr_offset_0(axaddr_offset_0),
.\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0] ),
.\axaddr_offset_r_reg[1] (\axaddr_offset_r_reg[1] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i0(m_valid_i0),
.m_valid_i_reg_0(\gen_simple_ar.ar_pipe_n_2 ),
.next_pending_r_reg(next_pending_r_reg_0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1]_rep (\state_reg[1]_rep_0 ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_1 ),
.\state_reg[1]_rep_1 (\state_reg[1]_rep_2 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_second_len_r_reg[2] (\wrap_second_len_r_reg[2] ),
.\wrap_second_len_r_reg[2]_0 (\wrap_second_len_r_reg[2]_0 ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ));
led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0 \gen_simple_aw.aw_pipe
(.D(D),
.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (\gen_simple_aw.aw_pipe_n_91 ),
.\aresetn_d_reg[1]_inv_0 (\gen_simple_ar.ar_pipe_n_2 ),
.axaddr_incr(axaddr_incr),
.axaddr_offset({axaddr_offset[2],axaddr_offset[0]}),
.\axaddr_offset_r_reg[1] (axaddr_offset[1]),
.\axaddr_offset_r_reg[3] (axaddr_offset[3]),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(\gen_simple_aw.aw_pipe_n_1 ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.wrap_second_len({wrap_second_len[3:2],wrap_second_len[0]}),
.\wrap_second_len_r_reg[1] (wrap_second_len[1]),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ));
led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1 \gen_simple_b.b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\gen_simple_aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\gen_simple_ar.ar_pipe_n_2 ),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.shandshake(shandshake),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2 \gen_simple_r.r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\gen_simple_aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\gen_simple_ar.ar_pipe_n_2 ),
.\cnt_read_reg[0]_rep__1 (\cnt_read_reg[0]_rep__1 ),
.\cnt_read_reg[3]_rep__0 (\cnt_read_reg[3]_rep__0 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
module led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice
(s_axi_arready,
s_ready_i_reg_0,
m_valid_i_reg_0,
\axaddr_incr_reg[3] ,
Q,
\axaddr_incr_reg[7] ,
O,
\wrap_second_len_r_reg[2] ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
next_pending_r_reg,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\aresetn_d_reg[0] ,
aclk,
m_valid_i0,
\aresetn_d_reg[0]_0 ,
\m_payload_i_reg[3]_0 ,
axaddr_offset_0,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[2]_0 ,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep_0 ,
\state_reg[0]_rep ,
s_axi_arvalid,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
\state_reg[1]_rep_1 );
output s_axi_arready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output [53:0]Q;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]\wrap_second_len_r_reg[2] ;
output [2:0]\axaddr_offset_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output next_pending_r_reg;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
input \aresetn_d_reg[0] ;
input aclk;
input m_valid_i0;
input \aresetn_d_reg[0]_0 ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [0:0]axaddr_offset_0;
input \state_reg[1]_rep ;
input [1:0]\wrap_second_len_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep_0 ;
input \state_reg[0]_rep ;
input s_axi_arvalid;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [0:0]\state_reg[1]_rep_1 ;
wire [3:0]O;
wire [53:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[3]_i_4__0_n_0 ;
wire \axaddr_incr[3]_i_5__0_n_0 ;
wire \axaddr_incr[3]_i_6__0_n_0 ;
wire \axaddr_incr_reg[11]_i_3__0_n_1 ;
wire \axaddr_incr_reg[11]_i_3__0_n_2 ;
wire \axaddr_incr_reg[11]_i_3__0_n_3 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire \axaddr_incr_reg[3]_i_2__0_n_0 ;
wire \axaddr_incr_reg[3]_i_2__0_n_1 ;
wire \axaddr_incr_reg[3]_i_2__0_n_2 ;
wire \axaddr_incr_reg[3]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire \axaddr_incr_reg[7]_i_2__0_n_0 ;
wire \axaddr_incr_reg[7]_i_2__0_n_1 ;
wire \axaddr_incr_reg[7]_i_2__0_n_2 ;
wire \axaddr_incr_reg[7]_i_2__0_n_3 ;
wire [0:0]axaddr_offset_0;
wire \axaddr_offset_r[1]_i_3_n_0 ;
wire \axaddr_offset_r[2]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_3__0_n_0 ;
wire \axaddr_offset_r[3]_i_2__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire [2:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[52]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [3:3]si_rs_arlen;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [0:0]\state_reg[1]_rep_1 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [1:0]\wrap_second_len_r_reg[2] ;
wire [1:0]\wrap_second_len_r_reg[2]_0 ;
wire \wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4__0
(.I0(Q[2]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[3]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[3]_i_6__0_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3__0
(.CI(\axaddr_incr_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3__0_n_1 ,\axaddr_incr_reg[11]_i_3__0_n_2 ,\axaddr_incr_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2__0_n_0 ,\axaddr_incr_reg[3]_i_2__0_n_1 ,\axaddr_incr_reg[3]_i_2__0_n_2 ,\axaddr_incr_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4__0_n_0 ,\axaddr_incr[3]_i_5__0_n_0 ,\axaddr_incr[3]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[7]_i_2__0
(.CI(\axaddr_incr_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2__0_n_0 ,\axaddr_incr_reg[7]_i_2__0_n_1 ,\axaddr_incr_reg[7]_i_2__0_n_2 ,\axaddr_incr_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r_reg[0] ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.O(\axaddr_offset_r_reg[3] [0]));
LUT6 #(
.INIT(64'h1FDF00001FDFFFFF))
\axaddr_offset_r[1]_i_2
(.I0(\axaddr_offset_r[1]_i_3_n_0 ),
.I1(Q[35]),
.I2(Q[40]),
.I3(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [0]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_3
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [1]),
.O(\axaddr_offset_r_reg[3] [1]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3__0
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1__0
(.I0(si_rs_arlen),
.I1(\axaddr_offset_r[3]_i_2__0_n_0 ),
.I2(\state_reg[1]_rep_0 ),
.I3(s_ready_i_reg_0),
.I4(\state_reg[0]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [2]),
.O(\axaddr_offset_r_reg[3] [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_4
(.I0(si_rs_arlen),
.I1(\state_reg[0]_rep ),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\axlen_cnt_reg[3] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(\m_payload_i[52]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(si_rs_arlen),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[52]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\state_reg[1]_rep_1 ),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_3__0
(.I0(\state_reg[1]_rep ),
.I1(Q[39]),
.I2(si_rs_arlen),
.I3(Q[40]),
.I4(Q[41]),
.O(next_pending_r_reg));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[0]_rep ),
.I4(s_ready_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'h8888082AAAAA082A))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[40]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(si_rs_arlen),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h002AA02A0A2AAA2A))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[4]),
.I1(si_rs_arlen),
.I2(Q[35]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(si_rs_arlen),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[35]),
.I3(si_rs_arlen),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'h0EF0FFFF0EF00000))
\wrap_second_len_r[1]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [1]),
.I1(\axaddr_offset_r_reg[3] [2]),
.I2(axaddr_offset_0),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[2]_0 [0]),
.O(\wrap_second_len_r_reg[2] [0]));
LUT6 #(
.INIT(64'hAA4AFFFFAA4A0000))
\wrap_second_len_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [1]),
.I1(\axaddr_offset_r_reg[3] [2]),
.I2(\axaddr_offset_r_reg[1] ),
.I3(axaddr_offset_0),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[2]_0 [1]),
.O(\wrap_second_len_r_reg[2] [1]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r_reg[3] ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_14_axic_register_slice" *)
module led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
D,
\wrap_second_len_r_reg[1] ,
axaddr_incr,
Q,
wrap_second_len,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[3] ,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
\wrap_boundary_axaddr_r_reg[6] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
S,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[3] ,
\state_reg[1] ,
\axaddr_offset_r_reg[3]_0 ,
s_axi_awvalid,
b_push,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [3:0]D;
output \wrap_second_len_r_reg[1] ;
output [11:0]axaddr_incr;
output [54:0]Q;
output [2:0]wrap_second_len;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[3] ;
output [1:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input [3:0]S;
input \state_reg[1]_rep ;
input [3:0]\wrap_second_len_r_reg[3] ;
input [1:0]\state_reg[1] ;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input s_axi_awvalid;
input b_push;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [0:0]E;
wire [3:0]D;
wire [0:0]E;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire [11:0]axaddr_incr;
wire \axaddr_incr[3]_i_4_n_0 ;
wire \axaddr_incr[3]_i_5_n_0 ;
wire \axaddr_incr[3]_i_6_n_0 ;
wire \axaddr_incr_reg[11]_i_3_n_1 ;
wire \axaddr_incr_reg[11]_i_3_n_2 ;
wire \axaddr_incr_reg[11]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_2_n_0 ;
wire \axaddr_incr_reg[3]_i_2_n_1 ;
wire \axaddr_incr_reg[3]_i_2_n_2 ;
wire \axaddr_incr_reg[3]_i_2_n_3 ;
wire \axaddr_incr_reg[7]_i_2_n_0 ;
wire \axaddr_incr_reg[7]_i_2_n_1 ;
wire \axaddr_incr_reg[7]_i_2_n_2 ;
wire \axaddr_incr_reg[7]_i_2_n_3 ;
wire [1:0]axaddr_offset;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[0]_i_3_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_3_n_0 ;
wire \axaddr_offset_r[2]_i_4_n_0 ;
wire \axaddr_offset_r[3]_i_2_n_0 ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [61:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_2_n_0 ;
wire \wrap_cnt_r[3]_i_3_n_0 ;
wire [2:0]wrap_second_len;
wire \wrap_second_len_r[0]_i_2_n_0 ;
wire \wrap_second_len_r[0]_i_3_n_0 ;
wire \wrap_second_len_r[0]_i_4_n_0 ;
wire \wrap_second_len_r[0]_i_5_n_0 ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire \wrap_second_len_r_reg[1] ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4
(.I0(Q[2]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[35]),
.O(\axaddr_incr[3]_i_6_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3
(.CI(\axaddr_incr_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3_n_1 ,\axaddr_incr_reg[11]_i_3_n_2 ,\axaddr_incr_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[11:8]),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2_n_0 ,\axaddr_incr_reg[3]_i_2_n_1 ,\axaddr_incr_reg[3]_i_2_n_2 ,\axaddr_incr_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4_n_0 ,\axaddr_incr[3]_i_5_n_0 ,\axaddr_incr[3]_i_6_n_0 }),
.O(axaddr_incr[3:0]),
.S(S));
CARRY4 \axaddr_incr_reg[7]_i_2
(.CI(\axaddr_incr_reg[3]_i_2_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2_n_0 ,\axaddr_incr_reg[7]_i_2_n_1 ,\axaddr_incr_reg[7]_i_2_n_2 ,\axaddr_incr_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[7:4]),
.S(Q[7:4]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'h00000700FFFFF7FF))
\axaddr_offset_r[0]_i_2
(.I0(Q[39]),
.I1(\axaddr_offset_r[0]_i_3_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_3
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[1]_i_1
(.I0(Q[40]),
.I1(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [1]),
.O(\axaddr_offset_r_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[35]),
.I3(Q[3]),
.I4(Q[36]),
.I5(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.O(axaddr_offset[1]));
LUT6 #(
.INIT(64'h03FFF3FF55555555))
\axaddr_offset_r[2]_i_2
(.I0(\axaddr_offset_r_reg[3]_0 [2]),
.I1(\axaddr_offset_r[2]_i_3_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\axaddr_offset_r[2]_i_4_n_0 ),
.I5(\state_reg[1]_rep ),
.O(\axaddr_offset_r[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_4
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1
(.I0(Q[42]),
.I1(\axaddr_offset_r[3]_i_2_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [3]),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_3
(.I0(Q[42]),
.I1(\state_reg[1] [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\axlen_cnt_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(skid_buffer[52]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(E),
.D(skid_buffer[52]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_2
(.I0(Q[41]),
.I1(Q[40]),
.I2(Q[42]),
.I3(Q[39]),
.O(next_pending_r_reg));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_awready),
.I2(b_push),
.I3(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A002A2AAAA02A2))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[2]),
.I1(Q[41]),
.I2(Q[35]),
.I3(Q[40]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h002A0A2AA02AAA2A))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[4]),
.I1(Q[42]),
.I2(Q[35]),
.I3(Q[36]),
.I4(Q[41]),
.I5(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[35]),
.I3(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hDDDDD8DDAAAAA8AA))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r[0]_i_3_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(D[0]));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[1] ),
.I1(\wrap_cnt_r[3]_i_2_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1
(.I0(wrap_second_len[1]),
.I1(\wrap_cnt_r[3]_i_2_n_0 ),
.I2(\wrap_second_len_r_reg[1] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1
(.I0(wrap_second_len[2]),
.I1(\wrap_second_len_r_reg[1] ),
.I2(\wrap_cnt_r[3]_i_2_n_0 ),
.I3(wrap_second_len[1]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'hAAAABAAA))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_cnt_r[3]_i_3_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r[0]_i_2_n_0 ),
.I3(\axaddr_offset_r[2]_i_2_n_0 ),
.I4(\axaddr_offset_r_reg[3] ),
.O(\wrap_cnt_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000800FFFFF8FF))
\wrap_cnt_r[3]_i_3
(.I0(Q[39]),
.I1(\axaddr_offset_r[0]_i_3_n_0 ),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(\wrap_cnt_r[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h00000000CCCCCACC))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3] [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(wrap_second_len[0]));
LUT6 #(
.INIT(64'hFFFFFFFFF2FFFFFF))
\wrap_second_len_r[0]_i_2
(.I0(\axaddr_offset_r_reg[3]_0 [3]),
.I1(\state_reg[1]_rep ),
.I2(\wrap_second_len_r[3]_i_2_n_0 ),
.I3(\axaddr_offset_r[2]_i_2_n_0 ),
.I4(\axaddr_offset_r[0]_i_2_n_0 ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000FFE200E2))
\wrap_second_len_r[0]_i_3
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[2]),
.I3(Q[35]),
.I4(\wrap_second_len_r[0]_i_4_n_0 ),
.I5(\wrap_second_len_r[0]_i_5_n_0 ),
.O(\wrap_second_len_r[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_second_len_r[0]_i_4
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\wrap_second_len_r[0]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT4 #(
.INIT(16'hFFDF))
\wrap_second_len_r[0]_i_5
(.I0(Q[39]),
.I1(\state_reg[1] [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\wrap_second_len_r[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'h2EE22E222EE22EE2))
\wrap_second_len_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\state_reg[1]_rep ),
.I2(\axaddr_offset_r[0]_i_2_n_0 ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[3] ),
.I5(\axaddr_offset_r[2]_i_2_n_0 ),
.O(\wrap_second_len_r_reg[1] ));
LUT6 #(
.INIT(64'h08F3FFFF08F30000))
\wrap_second_len_r[2]_i_1
(.I0(\axaddr_offset_r_reg[3] ),
.I1(\axaddr_offset_r[0]_i_2_n_0 ),
.I2(\axaddr_offset_r_reg[1] ),
.I3(\axaddr_offset_r[2]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3] [2]),
.O(wrap_second_len[1]));
LUT6 #(
.INIT(64'hBF00FFFFBF00BF00))
\wrap_second_len_r[3]_i_1
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r[0]_i_2_n_0 ),
.I2(\axaddr_offset_r[2]_i_2_n_0 ),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3] [3]),
.O(wrap_second_len[2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2
(.I0(\axaddr_offset_r[2]_i_4_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_14_axic_register_slice" *)
module led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
shandshake,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output shandshake;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire shandshake;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__0
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(\skid_buffer_reg[0]_0 ),
.I1(si_rs_bvalid),
.O(shandshake));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_14_axic_register_slice" *)
module led_controller_design_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[0]_rep__1 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[3]_rep__0 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[0]_rep__1 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[3]_rep__0 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[0]_rep__1 ;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__2_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[3]_i_2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[3]_rep__0 ),
.O(\cnt_read_reg[0]_rep__1 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\skid_buffer_reg[0]_0 ),
.I3(\cnt_read_reg[3]_rep__0 ),
.O(m_valid_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__2_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[3]_rep__0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "led_controller_design_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
(* NotValidForBitStream *)
module led_controller_design_auto_pc_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [11:0]s_axi_wid;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
led_controller_design_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(s_axi_wid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFXTP_BEHAVIORAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_BEHAVIORAL_V |
/*
* Copyright 2015 Forest Crossman
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
module display_hex_byte(
input clk,
input [7:0] hex_byte,
output wire [7:0] segments,
output wire [2:0] segments_enable
);
/* These are the module's configurable parameters */
parameter refresh_rate = 1000; // Refresh rate in Hz
parameter sys_clk_freq = 100000000; // Input clock frequency in Hz
/* Pre-calculate the clock divider */
localparam clk_divider = sys_clk_freq / (refresh_rate * 3);
/* 32 bits should be enough for any reasonable clock/freq combo */
reg [31:0] divider;
/*
* Link the registers to their respective output wires, but invert
* them since the physical display segment LEDs are active low.
*/
reg [7:0] segments_out;
reg [2:0] segments_enable_out;
assign segments = ~segments_out;
assign segments_enable = ~segments_enable_out;
/* Declare the wires the segment data will be output to */
wire [7:0] high_segments;
wire [7:0] low_segments;
/* Instantiate the nibble to segments converters */
nibble_to_segments high_nib(hex_byte[7:4], high_segments);
nibble_to_segments low_nib(hex_byte[3:0], low_segments);
always @(posedge clk) begin
if (divider < clk_divider)
/* Increment the counter by one to count the delay cycles */
divider <= divider + 1;
else begin
/* Reset the counter (divider) */
divider <= 0;
/*
* This case statement cycles between the three 7-segment displays.
* Each case describes the state of the next cycle, updating each
* the displays from left to right.
*/
case (segments_enable_out)
3'b001: begin
segments_out <= 8'b00101110; // 'h'
segments_enable_out <= 3'b100; // The left display
end
3'b100: begin
segments_out <= high_segments; // The high nibble
segments_enable_out <= 3'b010; // The center display
end
3'b010: begin
segments_out <= low_segments; // The low nibble
segments_enable_out <= 3'b001; // The right display
end
default: begin
segments_out <= 8'h00; // Turn all segments off
segments_enable_out <= 3'b001; // The right display
end
endcase
end
end
endmodule
module nibble_to_segments(
input [3:0] nibble,
output wire [7:0] segments
);
/*
* Store the segment information in segments_out and send that signal
* through the "segments" wire.
*/
reg [7:0] segments_out;
assign segments = segments_out;
/*
* This section is essentially a lookup table that maps hex digits to
* active display segments.
*/
always begin
case (nibble)
4'h0: segments_out = 8'b11111100;
4'h1: segments_out = 8'b01100000;
4'h2: segments_out = 8'b11011010;
4'h3: segments_out = 8'b11110010;
4'h4: segments_out = 8'b01100110;
4'h5: segments_out = 8'b10110110;
4'h6: segments_out = 8'b10111110;
4'h7: segments_out = 8'b11100000;
4'h8: segments_out = 8'b11111110;
4'h9: segments_out = 8'b11110110;
4'ha: segments_out = 8'b11101110;
4'hb: segments_out = 8'b00111110;
4'hc: segments_out = 8'b10011100;
4'hd: segments_out = 8'b01111010;
4'he: segments_out = 8'b10011110;
4'hf: segments_out = 8'b10001110;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_BEHAVIORAL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_BEHAVIORAL_V |
/* Dual-core ARM Cortex-A9 instance (wrapper for Qsys generation) */
module arm
(
input wire clk_proc,
input wire reset_reset_n,
output wire [14:0] memory_mem_a,
output wire [2:0] memory_mem_ba,
output wire memory_mem_ck,
output wire memory_mem_ck_n,
output wire memory_mem_cke,
output wire memory_mem_cs_n,
output wire memory_mem_ras_n,
output wire memory_mem_cas_n,
output wire memory_mem_we_n,
output wire memory_mem_reset_n,
inout wire [31:0] memory_mem_dq,
inout wire [3:0] memory_mem_dqs,
inout wire [3:0] memory_mem_dqs_n,
output wire memory_mem_odt,
output wire [3:0] memory_mem_dm,
input wire memory_oct_rzqin,
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK,
output wire hps_0_hps_io_hps_io_emac1_inst_TXD0,
output wire hps_0_hps_io_hps_io_emac1_inst_TXD1,
output wire hps_0_hps_io_hps_io_emac1_inst_TXD2,
output wire hps_0_hps_io_hps_io_emac1_inst_TXD3,
input wire hps_0_hps_io_hps_io_emac1_inst_RXD0,
inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO,
output wire hps_0_hps_io_hps_io_emac1_inst_MDC,
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL,
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL,
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK,
input wire hps_0_hps_io_hps_io_emac1_inst_RXD1,
input wire hps_0_hps_io_hps_io_emac1_inst_RXD2,
input wire hps_0_hps_io_hps_io_emac1_inst_RXD3,
inout wire hps_0_hps_io_hps_io_qspi_inst_IO0,
inout wire hps_0_hps_io_hps_io_qspi_inst_IO1,
inout wire hps_0_hps_io_hps_io_qspi_inst_IO2,
inout wire hps_0_hps_io_hps_io_qspi_inst_IO3,
output wire hps_0_hps_io_hps_io_qspi_inst_SS0,
output wire hps_0_hps_io_hps_io_qspi_inst_CLK,
inout wire hps_0_hps_io_hps_io_sdio_inst_CMD,
inout wire hps_0_hps_io_hps_io_sdio_inst_D0,
inout wire hps_0_hps_io_hps_io_sdio_inst_D1,
output wire hps_0_hps_io_hps_io_sdio_inst_CLK,
inout wire hps_0_hps_io_hps_io_sdio_inst_D2,
inout wire hps_0_hps_io_hps_io_sdio_inst_D3,
inout wire hps_0_hps_io_hps_io_usb1_inst_D0,
inout wire hps_0_hps_io_hps_io_usb1_inst_D1,
inout wire hps_0_hps_io_hps_io_usb1_inst_D2,
inout wire hps_0_hps_io_hps_io_usb1_inst_D3,
inout wire hps_0_hps_io_hps_io_usb1_inst_D4,
inout wire hps_0_hps_io_hps_io_usb1_inst_D5,
inout wire hps_0_hps_io_hps_io_usb1_inst_D6,
inout wire hps_0_hps_io_hps_io_usb1_inst_D7,
input wire hps_0_hps_io_hps_io_usb1_inst_CLK,
output wire hps_0_hps_io_hps_io_usb1_inst_STP,
input wire hps_0_hps_io_hps_io_usb1_inst_DIR,
input wire hps_0_hps_io_hps_io_usb1_inst_NXT,
output wire hps_0_hps_io_hps_io_spim0_inst_CLK,
output wire hps_0_hps_io_hps_io_spim0_inst_MOSI,
input wire hps_0_hps_io_hps_io_spim0_inst_MISO,
output wire hps_0_hps_io_hps_io_spim0_inst_SS0,
output wire hps_0_hps_io_hps_io_spim1_inst_CLK,
output wire hps_0_hps_io_hps_io_spim1_inst_MOSI,
input wire hps_0_hps_io_hps_io_spim1_inst_MISO,
output wire hps_0_hps_io_hps_io_spim1_inst_SS0,
input wire hps_0_hps_io_hps_io_uart0_inst_RX,
output wire hps_0_hps_io_hps_io_uart0_inst_TX,
inout wire hps_0_hps_io_hps_io_i2c1_inst_SDA,
inout wire hps_0_hps_io_hps_io_i2c1_inst_SCL,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO00,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO09,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO35,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO48,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO53,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO54,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO55,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO56,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO61,
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO62,
output wire hps_0_h2f_reset_reset_n,
input wire hps_0_f2h_cold_reset_req_reset_n,
input wire hps_0_f2h_debug_reset_req_reset_n,
input wire hps_0_f2h_warm_reset_req_reset_n,
input wire [27:0] hps_0_f2h_stm_hw_events_stm_hwevents,
output wire out0_fv,
output wire out0_dv,
output wire [OUT0_SIZE-1:0] out0_data,
output wire out1_fv,
output wire out1_dv,
output wire [OUT1_SIZE-1:0] out1_data,
input wire in0_dv,
input wire [IN0_SIZE-1:0] in0_data,
input wire in0_fv,
input wire in1_dv,
input wire [IN1_SIZE-1:0] in1_data,
input wire in1_fv,
output wire [MASTER_ADDR_WIDTH-1:0] master_addr_o,
output wire master_wr_o,
output wire master_rd_o,
output wire [31:0] master_datawr_o,
input wire [31:0] master_datard_i,
input wire master_waitreq
);
parameter CLK_PROC_FREQ = 50000000;
parameter CLK_CLK_FREQ = 50000000;
parameter IN0_SIZE = 16;
parameter IN1_SIZE = 16;
parameter OUT0_SIZE = 16;
parameter OUT1_SIZE = 16;
parameter MASTER_ADDR_WIDTH = 32;
soc_system soc_system_inst
(
.clk_clk(clk_proc),
.reset_reset_n(reset_reset_n),
.memory_mem_a(memory_mem_a),
.memory_mem_ba(memory_mem_ba),
.memory_mem_ck(memory_mem_ck),
.memory_mem_ck_n(memory_mem_ck_n),
.memory_mem_cke(memory_mem_cke),
.memory_mem_cs_n(memory_mem_cs_n),
.memory_mem_ras_n(memory_mem_ras_n),
.memory_mem_cas_n(memory_mem_cas_n),
.memory_mem_we_n(memory_mem_we_n),
.memory_mem_reset_n(memory_mem_reset_n),
.memory_mem_dq(memory_mem_dq),
.memory_mem_dqs(memory_mem_dqs),
.memory_mem_dqs_n(memory_mem_dqs_n),
.memory_mem_odt(memory_mem_odt),
.memory_mem_dm(memory_mem_dm),
.memory_oct_rzqin(memory_oct_rzqin),
.hps_0_hps_io_hps_io_emac1_inst_TX_CLK(hps_0_hps_io_hps_io_emac1_inst_TX_CLK),
.hps_0_hps_io_hps_io_emac1_inst_TXD0(hps_0_hps_io_hps_io_emac1_inst_TXD0),
.hps_0_hps_io_hps_io_emac1_inst_TXD1(hps_0_hps_io_hps_io_emac1_inst_TXD1),
.hps_0_hps_io_hps_io_emac1_inst_TXD2(hps_0_hps_io_hps_io_emac1_inst_TXD2),
.hps_0_hps_io_hps_io_emac1_inst_TXD3(hps_0_hps_io_hps_io_emac1_inst_TXD3),
.hps_0_hps_io_hps_io_emac1_inst_RXD0(hps_0_hps_io_hps_io_emac1_inst_RXD0),
.hps_0_hps_io_hps_io_emac1_inst_MDIO(hps_0_hps_io_hps_io_emac1_inst_MDIO),
.hps_0_hps_io_hps_io_emac1_inst_MDC(hps_0_hps_io_hps_io_emac1_inst_MDC),
.hps_0_hps_io_hps_io_emac1_inst_RX_CTL(hps_0_hps_io_hps_io_emac1_inst_RX_CTL),
.hps_0_hps_io_hps_io_emac1_inst_TX_CTL(hps_0_hps_io_hps_io_emac1_inst_TX_CTL),
.hps_0_hps_io_hps_io_emac1_inst_RX_CLK(hps_0_hps_io_hps_io_emac1_inst_RX_CLK),
.hps_0_hps_io_hps_io_emac1_inst_RXD1(hps_0_hps_io_hps_io_emac1_inst_RXD1),
.hps_0_hps_io_hps_io_emac1_inst_RXD2(hps_0_hps_io_hps_io_emac1_inst_RXD2),
.hps_0_hps_io_hps_io_emac1_inst_RXD3(hps_0_hps_io_hps_io_emac1_inst_RXD3),
.hps_0_hps_io_hps_io_qspi_inst_IO0(hps_0_hps_io_hps_io_qspi_inst_IO0),
.hps_0_hps_io_hps_io_qspi_inst_IO1(hps_0_hps_io_hps_io_qspi_inst_IO1),
.hps_0_hps_io_hps_io_qspi_inst_IO2(hps_0_hps_io_hps_io_qspi_inst_IO2),
.hps_0_hps_io_hps_io_qspi_inst_IO3(hps_0_hps_io_hps_io_qspi_inst_IO3),
.hps_0_hps_io_hps_io_qspi_inst_SS0(hps_0_hps_io_hps_io_qspi_inst_SS0),
.hps_0_hps_io_hps_io_qspi_inst_CLK(hps_0_hps_io_hps_io_qspi_inst_CLK),
.hps_0_hps_io_hps_io_sdio_inst_CMD(hps_0_hps_io_hps_io_sdio_inst_CMD),
.hps_0_hps_io_hps_io_sdio_inst_D0(hps_0_hps_io_hps_io_sdio_inst_D0),
.hps_0_hps_io_hps_io_sdio_inst_D1(hps_0_hps_io_hps_io_sdio_inst_D1),
.hps_0_hps_io_hps_io_sdio_inst_CLK(hps_0_hps_io_hps_io_sdio_inst_CLK),
.hps_0_hps_io_hps_io_sdio_inst_D2(hps_0_hps_io_hps_io_sdio_inst_D2),
.hps_0_hps_io_hps_io_sdio_inst_D3(hps_0_hps_io_hps_io_sdio_inst_D3),
.hps_0_hps_io_hps_io_usb1_inst_D0(hps_0_hps_io_hps_io_usb1_inst_D0),
.hps_0_hps_io_hps_io_usb1_inst_D1(hps_0_hps_io_hps_io_usb1_inst_D1),
.hps_0_hps_io_hps_io_usb1_inst_D2(hps_0_hps_io_hps_io_usb1_inst_D2),
.hps_0_hps_io_hps_io_usb1_inst_D3(hps_0_hps_io_hps_io_usb1_inst_D3),
.hps_0_hps_io_hps_io_usb1_inst_D4(hps_0_hps_io_hps_io_usb1_inst_D4),
.hps_0_hps_io_hps_io_usb1_inst_D5(hps_0_hps_io_hps_io_usb1_inst_D5),
.hps_0_hps_io_hps_io_usb1_inst_D6(hps_0_hps_io_hps_io_usb1_inst_D6),
.hps_0_hps_io_hps_io_usb1_inst_D7(hps_0_hps_io_hps_io_usb1_inst_D7),
.hps_0_hps_io_hps_io_usb1_inst_CLK(hps_0_hps_io_hps_io_usb1_inst_CLK),
.hps_0_hps_io_hps_io_usb1_inst_STP(hps_0_hps_io_hps_io_usb1_inst_STP),
.hps_0_hps_io_hps_io_usb1_inst_DIR(hps_0_hps_io_hps_io_usb1_inst_DIR),
.hps_0_hps_io_hps_io_usb1_inst_NXT(hps_0_hps_io_hps_io_usb1_inst_NXT),
.hps_0_hps_io_hps_io_spim0_inst_CLK(hps_0_hps_io_hps_io_spim0_inst_CLK),
.hps_0_hps_io_hps_io_spim0_inst_MOSI(hps_0_hps_io_hps_io_spim0_inst_MOSI),
.hps_0_hps_io_hps_io_spim0_inst_MISO(hps_0_hps_io_hps_io_spim0_inst_MISO),
.hps_0_hps_io_hps_io_spim0_inst_SS0(hps_0_hps_io_hps_io_spim0_inst_SS0),
.hps_0_hps_io_hps_io_spim1_inst_CLK(hps_0_hps_io_hps_io_spim1_inst_CLK),
.hps_0_hps_io_hps_io_spim1_inst_MOSI(hps_0_hps_io_hps_io_spim1_inst_MOSI),
.hps_0_hps_io_hps_io_spim1_inst_MISO(hps_0_hps_io_hps_io_spim1_inst_MISO),
.hps_0_hps_io_hps_io_spim1_inst_SS0(hps_0_hps_io_hps_io_spim1_inst_SS0),
.hps_0_hps_io_hps_io_uart0_inst_RX(hps_0_hps_io_hps_io_uart0_inst_RX),
.hps_0_hps_io_hps_io_uart0_inst_TX(hps_0_hps_io_hps_io_uart0_inst_TX),
.hps_0_hps_io_hps_io_i2c1_inst_SDA(hps_0_hps_io_hps_io_i2c1_inst_SDA),
.hps_0_hps_io_hps_io_i2c1_inst_SCL(hps_0_hps_io_hps_io_i2c1_inst_SCL),
.hps_0_hps_io_hps_io_gpio_inst_GPIO00(hps_0_hps_io_hps_io_gpio_inst_GPIO00),
.hps_0_hps_io_hps_io_gpio_inst_GPIO09(hps_0_hps_io_hps_io_gpio_inst_GPIO09),
.hps_0_hps_io_hps_io_gpio_inst_GPIO35(hps_0_hps_io_hps_io_gpio_inst_GPIO35),
.hps_0_hps_io_hps_io_gpio_inst_GPIO48(hps_0_hps_io_hps_io_gpio_inst_GPIO48),
.hps_0_hps_io_hps_io_gpio_inst_GPIO53(hps_0_hps_io_hps_io_gpio_inst_GPIO53),
.hps_0_hps_io_hps_io_gpio_inst_GPIO54(hps_0_hps_io_hps_io_gpio_inst_GPIO54),
.hps_0_hps_io_hps_io_gpio_inst_GPIO55(hps_0_hps_io_hps_io_gpio_inst_GPIO55),
.hps_0_hps_io_hps_io_gpio_inst_GPIO56(hps_0_hps_io_hps_io_gpio_inst_GPIO56),
.hps_0_hps_io_hps_io_gpio_inst_GPIO61(hps_0_hps_io_hps_io_gpio_inst_GPIO61),
.hps_0_hps_io_hps_io_gpio_inst_GPIO62(hps_0_hps_io_hps_io_gpio_inst_GPIO62),
.hps_0_h2f_reset_reset_n(hps_0_h2f_reset_reset_n),
.hps_0_f2h_cold_reset_req_reset_n(1'b1),//hps_0_f2h_cold_reset_req_reset_n), //TODO
.hps_0_f2h_debug_reset_req_reset_n(1'b1),//hps_0_f2h_debug_reset_req_reset_n), //TODO
.hps_0_f2h_warm_reset_req_reset_n(1'b1),//hps_0_f2h_warm_reset_req_reset_n), //TODO
.hps_0_f2h_stm_hw_events_stm_hwevents(hps_0_f2h_stm_hw_events_stm_hwevents), //TODO
.out0_fv(out0_fv),
.out0_dv(out0_dv),
.out0_data(out0_data),
.out1_fv(out1_fv),
.out1_dv(out1_dv),
.out1_data(out1_data),
.in0_dv(in0_dv),
.in0_data(in0_data),
.in0_fv(in0_fv),
.in1_dv(in1_dv),
.in1_data(in1_data),
.in1_fv(in1_fv),
.master_addr_o(master_addr_o),
.master_wr_o(master_wr_o),
.master_rd_o(master_rd_o),
.master_datawr_o(master_datawr_o),
.master_datard_i(master_datard_i),
.master_waitreq(master_waitreq)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:38:56 06/14/2016
// Design Name:
// Module Name: LZD_16bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LZD_16bit( in, out, valid
);
input [15:0]in;
output reg [3:0]out;
output reg valid;
wire v1,v2;
wire [2:0]l1, l2;
initial
begin
out<=4'b0000;
valid<=0;
end
LZD_8bit d5( .in(in[7:0]), .out(l1), .valid(v1));
LZD_8bit d6( .in(in[15:8]), .out(l2), .valid(v2));
always@(in,v1,v2,l1,l2)
begin
if(v2==0&&v1==1)
begin
out<={{~v2},{l1}} ;
end
/*
here l1, l2 are 3 bits each and v1,v2 are 1bit
when v2=0
eg- 0000_0000_0010_0100
v2=0,l2=3'b000, v1=1, l1=3'b010
out= {{1},{010}}= {1010}=10 there are 10 leading zeros in 0000_0000_0010_0100
*/
else if( v2==0&&v1==0)
begin
out<=0;
end
else
begin
out<={{~v2},{l2}};
end
/*eg- 0000_0100_0010_0100
v2=0,l2=3'b101, v1=1, l1=3'b010
out= {{1},{101}}= {0101}=5 there are 5 leading zeros in 0000_0100_0010_0100
*/
valid<= v1|v2 ; /* valid = in[15]|in[14]|in[13]|in[12]|in[11]|in[10]|in[9]|in[8]
|in[7]|in[6]|in[5]|in[4]|in[3]|in[2]|in[1]|in[0]*/
end
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: sa1_mult.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sa1_mult (
clock,
dataa,
datab,
result);
input clock;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 1.1
// \ \ Application : MIG
// / / Filename : example_top.v
// /___/ /\ Date Last Modified : $Date: 2010/11/09 17:40:54 $
// \ \ / \ Date Created : Mon Jun 23 2008
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level module. This module serves both as an example,
// and allows the user to synthesize a self-contained design,
// which they can be used to test their hardware.
// In addition to the memory controller, the module instantiates:
// 1. Synthesizable testbench - used to model user's backend logic
// and generate different traffic patterns
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module example_top #
(
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter SIMULATION = "FALSE",
parameter BL_WIDTH = 8,
parameter PORT_MODE = "BI_MODE",
parameter DATA_MODE = 4'b0010,
parameter EYE_TEST = "FALSE",
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL",
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL",
// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter BEGIN_ADDRESS = 32'h00000000,
parameter END_ADDRESS = 32'h00ffffff,
parameter PRBS_EADDR_MASK_POS = 32'hff000000,
parameter SEL_VICTIM_LINE = 0,
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DQ_CNT_WIDTH = 6,
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8,
parameter DM_WIDTH = 8,
// # of DM (data mask)
parameter DQ_WIDTH = 64,
// # of DQ (data)
parameter DQS_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ROW_WIDTH = 14,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 28,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
parameter USE_DM_PORT = 1,
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1,
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0",
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0,
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ",
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 6,
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter CWL = 5,
// in number of clock cycles
// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
// DDR2 SDRAM: Can be ignored
parameter DDR2_DQSN_ENABLE = "YES",
// Enable differential DQS for DDR2
parameter OUTPUT_DRV = "HIGH",
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter RTT_NOM = "60",
// RTT_NOM (ODT) (Mode Register 1).
// # = "DISABLED" - RTT_NOM disabled,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF",
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter ADDR_CMD_MODE = "1T" ,
// # = "1T", "2T".
parameter REG_CTRL = "OFF",
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
//***************************************************************************
// The following parameters are multiplier and divisor factors for MMCM.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKFBOUT_MULT_F = 4,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT_DIVIDE = 4,
// VCO output divisor for fast (memory) clocks
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tFAW = 30000,
// memory tRAW paramter in pS.
parameter tRAS = 35000,
// memory tRAS paramter in pS.
parameter tRCD = 13750,
// memory tRCD paramter in pS.
parameter tREFI = 7800000,
// memory tREFI paramter in pS.
parameter tRFC = 110000,
// memory tRFC paramter in pS.
parameter tRP = 13750,
// memory tRP paramter in pS.
parameter tRRD = 6000,
// memory tRRD paramter in pS.
parameter tRTP = 7500,
// memory tRTP paramter in pS.
parameter tWTR = 7500,
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000,
// memory tZQI paramter in nS.
parameter tZQCS = 64,
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "OFF",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b1110,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b1111,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000,
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000,
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'hF,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'h0,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'hF,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'h0,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'h0,
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'h3FE_3FE_3FE_2FF,
parameter PHY_1_BITLANES = 48'hFFF_FFE_000_000,
parameter PHY_2_BITLANES = 48'h3FE_3FE_3FE_2FF,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_13,
parameter ADDR_MAP
= 192'h000_000_139_138_137_136_135_134_133_132_131_130_129_128_127_126,
parameter BANK_MAP = 36'h12B_12A_125,
parameter CAS_MAP = 12'h123,
parameter CKE_ODT_BYTE_MAP = 8'h13,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_121,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h124,
parameter WE_MAP = 12'h122,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_20_21_22_23_00_01_02_03,
parameter DATA0_MAP = 96'h031_032_033_034_035_036_037_038,
parameter DATA1_MAP = 96'h021_022_023_024_025_026_027_028,
parameter DATA2_MAP = 96'h011_012_013_014_015_016_017_018,
parameter DATA3_MAP = 96'h000_001_002_003_004_005_006_007,
parameter DATA4_MAP = 96'h231_232_233_234_235_236_237_238,
parameter DATA5_MAP = 96'h221_222_223_224_225_226_227_228,
parameter DATA6_MAP = 96'h211_212_213_214_215_216_217_218,
parameter DATA7_MAP = 96'h200_201_202_203_204_205_206_207,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_209_219_229_239_009_019_029_039,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000,
// Mapping of Ranks.
parameter MEM_ADDR_ORDER
= "ROW_BANK_COLUMN",
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IODELAY_HP_MODE = "ON",
// to phy_top
parameter IBUF_LPWR_MODE = "OFF",
// to phy_top
parameter WRLVL = "ON",
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "NORM",
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000,
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000,
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0,
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100,
parameter IODELAY_GRP = "IODELAY_MIG",
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
parameter INPUT_CLK_TYPE = "DIFFERENTIAL",
// input clock type DIFFERNTIAL or SINGLE_ENDED
parameter RST_ACT_LOW = 1,
// =1 for active low reset,
// =0 for active high.
parameter CAL_WIDTH = "HALF",
parameter STARVE_LIMIT = 2,
// # = 2,3,4.
//***************************************************************************
// System clock and Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0,
// IODELAYCTRL reference clock frequency
parameter tCK = 2500,
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 4,
// # of memory CKs per fabric CLK
parameter DIFF_TERM = "FALSE",
// Differential Termination
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter DRAM_TYPE = "DDR3"
)
(
// Inouts
inout [DQ_WIDTH-1:0] ddr3_dq,
inout [DQS_WIDTH-1:0] ddr3_dqs_n,
inout [DQS_WIDTH-1:0] ddr3_dqs_p,
// Outputs
output [ROW_WIDTH-1:0] ddr3_addr,
output [BANK_WIDTH-1:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [CK_WIDTH-1:0] ddr3_ck_p,
output [CK_WIDTH-1:0] ddr3_ck_n,
output [CKE_WIDTH-1:0] ddr3_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr3_cs_n,
output [DM_WIDTH-1:0] ddr3_dm,
output [RANKS-1:0] ddr3_odt,
// Inputs
// Differential system clocks
input sys_clk_p,
input sys_clk_n,
// differential iodelayctrl clk (reference clock)
input clk_ref_p,
input clk_ref_n,
output error,
output init_calib_complete,
// System reset
input sys_rst
);
function integer STR_TO_INT;
input [7:0] in;
begin
if(in == "8")
STR_TO_INT = 8;
else if(in == "4")
STR_TO_INT = 4;
else
STR_TO_INT = 0;
end
endfunction
localparam CMD_PIPE_PLUS1 = "ON";
// add pipeline stage between MC and PHY
localparam ECC = "OFF";
localparam ECC_WIDTH = 8;
localparam ECC_TEST = "OFF";
localparam MC_ERR_ADDR_WIDTH = 31;
localparam tPRDI = 1_000_000;
// memory tPRDI paramter in pS.
localparam DATA_WIDTH = 64;
localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;
localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
//***************************************************************************
// Traffic Gen related parameters (derived)
//***************************************************************************
localparam MASK_SIZE = DATA_WIDTH/8;
// Wire declarations
wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_i;
wire [47:0] traffic_wr_data_counts;
wire [47:0] traffic_rd_data_counts;
wire [ADDR_WIDTH-1:0] app_addr;
wire [2:0] app_cmd;
wire app_en;
wire app_rdy;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire app_rd_data_valid;
wire [APP_DATA_WIDTH-1:0] app_wdf_data;
wire app_wdf_end;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask;
wire app_wdf_rdy;
wire app_wdf_wren;
wire [64 + (2*APP_DATA_WIDTH - 1):0] error_status;
wire modify_enable_sel;
wire [2:0] data_mode_manual_sel;
wire [2:0] addr_mode_manual_sel;
wire [APP_DATA_WIDTH-1:0] cmp_data;
wire cmp_data_valid;
wire clk;
wire rst;
wire vio_modify_enable;
wire [3:0] vio_data_mode_value;
wire [2:0] vio_addr_mode_value;
wire [3:0] vio_instr_mode_value;
wire [1:0] vio_bl_mode_value;
wire [7:0] vio_fixed_bl_value;
wire vio_data_mask_gen;
//***************************************************************************
//***************************************************************************
// The User design is instantiated below. The memory interface ports are
// connected to the top-level and the application interface ports are
// connected to the traffic generator module. This provides a reference
// for connecting the memory controller to system.
//***************************************************************************
mig_7series_v1_1 #
(
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.ECC_TEST (ECC_TEST),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.DM_WIDTH (DM_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.tCK (tCK),
.DIFF_TERM (DIFF_TERM),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT_DIVIDE (CLKOUT_DIVIDE),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.RST_ACT_LOW (RST_ACT_LOW),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP),
.DRAM_TYPE (DRAM_TYPE)
)
u_mig_7series_v1_1
(
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.tb_clk (clk),
.tb_rst (rst),
.app_wdf_mask (app_wdf_mask),
// System Clock Ports
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
// Reference Clock Ports
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.sys_rst (sys_rst)
);
//***************************************************************************
// The traffic generation module instantiated below drives traffic (patterns)
// on the application interface of the memory controller
//***************************************************************************
traffic_gen_top #
(
.TCQ (TCQ),
.SIMULATION (SIMULATION),
.FAMILY ("VIRTEX7"),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.NUM_DQ_PINS (DQ_WIDTH),
.MEM_BURST_LEN (BURST_LENGTH),
.MEM_COL_WIDTH (COL_WIDTH),
.PORT_MODE (PORT_MODE),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.DATA_WIDTH (APP_DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.MASK_SIZE (MASK_SIZE),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.DATA_MODE (DATA_MODE),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.EYE_TEST (EYE_TEST)
)
u_traffic_gen_top
(
.clk (clk),
.rst (rst),
.manual_clear_error (manual_clear_error),
.memc_init_done (init_calib_complete),
.memc_cmd_full (~app_rdy),
.memc_cmd_en (app_en),
.memc_cmd_instr (app_cmd),
.memc_cmd_bl (),
.memc_cmd_addr (app_addr),
.memc_wr_en (app_wdf_wren),
.memc_wr_end (app_wdf_end),
.memc_wr_mask (app_wdf_mask),
.memc_wr_data (app_wdf_data),
.memc_wr_full (~app_wdf_rdy),
.memc_rd_en (),
.memc_rd_data (app_rd_data),
.memc_rd_empty (~app_rd_data_valid),
.vio_modify_enable (vio_modify_enable),
.vio_data_mode_value (vio_data_mode_value),
.vio_addr_mode_value (vio_addr_mode_value),
.vio_instr_mode_value (vio_instr_mode_value),
.vio_bl_mode_value (vio_bl_mode_value),
.vio_fixed_bl_value (vio_fixed_bl_value),
.vio_data_mask_gen (vio_data_mask_gen),
.fixed_addr_i (32'b0),
.fixed_data_i (32'b0),
.simple_data0 (32'b0),
.simple_data1 (32'b0),
.simple_data2 (32'b0),
.simple_data3 (32'b0),
.simple_data4 (32'b0),
.simple_data5 (32'b0),
.simple_data6 (32'b0),
.simple_data7 (32'b0),
.bram_cmd_i (39'b0),
.bram_valid_i (1'b0),
.bram_rdy_o (),
.cmp_data (cmp_data),
.cmp_data_valid (cmp_data_valid),
.cmp_error (cmp_error),
.error (error),
.error_status (error_status)
);
assign vio_modify_enable = 1'b1;
assign vio_data_mode_value = 4'b0010;
assign vio_addr_mode_value = 3'b011;
assign vio_instr_mode_value = 4'b0010;
assign vio_bl_mode_value = 2'b10;
assign vio_fixed_bl_value = 16;
assign vio_data_mask_gen = 1'b0;
endmodule
|
module prefab_alu_rf;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout,in;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
//reg [31:0] A,B; //Rn Rm
reg [4:0] OP;
reg [3:0] FLAGS;
reg S,ALU_OUT;
wire [31:0] Out;
wire [3:0] FLAGS_OUT;
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(Rn,Rm, OP, FLAGS, in,FLAGS_OUT,S,ALU_OUT);
initial fork
//Clk 0
Clk = 0 ; RESET = 1 ; Pcin = 32'bz ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ; OP=17; FLAGS=0; S=1;ALU_OUT=1;
//Clk 1 (Rising Edge)
#1 RESET = 0 ; #1 Pcin = 32'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0 /* Rn */ ; #1 RSLCT[7:4] = 0 /* Rm */; #1 RSLCT[11:8] = 0 /* Rs */; #1 RSLCT[15:12] = 0 /* Rd */; #1 RSLCT[19:16] = 0 /* Rn */ ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;
//Clk 0 (Falling Edge)Send CU signals
#2 Pcin = 32'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0 /* Rn */ ; #2 RSLCT[7:4] = 0 /* Rm */; #2 RSLCT[11:8] = 0 /* Rs */; #2 RSLCT[15:12] = 0 /* Rd */; #2 RSLCT[19:16] = 0 /* Rn */ ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;
//Clk 1 (Rising Edge
#3 RESET = 0 ; #3 Pcin = 32'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0 /* Rn */ ; #3 RSLCT[7:4] = 0 /* Rm */; #3 RSLCT[11:8] = 0 /* Rs */; #3 RSLCT[15:12] = 0 /* Rd */; #3 RSLCT[19:16] = 0 /* Rn */ ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;
//Clk 0 (Falling Edge) Send CU signals
#4 Pcin = 32'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0 /* Rn */ ; #4 RSLCT[7:4] = 0 /* Rm */; #4 RSLCT[11:8] = 0 /* Rs */; #4 RSLCT[15:12] = 1 /* Rd */; #4 RSLCT[19:16] = 0 /* Rn */ ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("prefab_alu_rf.vcd");
$dumpvars(0,prefab_alu_rf);
$display(" Test Results" );
$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3h, Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d,OP=%3d;FLAGS=0; S=%1b;ALU_OUT=%1b;",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout,OP,FLAGS,S,ALU_OUT);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v ARM_ALU.v prefab_alu_rf.v |
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// A library of various basic logic elements.
// D flip-flop.
module CC_DFlipFlop(clk, en, reset, d, q);
parameter WIDTH=1;
input clk;
input en;
input reset;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @ (posedge clk or posedge reset)
if (reset)
q <= 0;
else if (en)
q <= d;
endmodule
// Chain of D flip-flops.
module CC_Delay(clk, reset, d, q);
parameter WIDTH=1;
parameter DELAY=1;
input clk;
input reset;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
wire [(WIDTH*DELAY)-1:0] reg_inputs;
wire [(WIDTH*DELAY)-1:0] reg_outputs;
genvar i;
generate
for (i = 0; i < DELAY; i = i + 1)
begin: DFF_CHAIN
CC_DFlipFlop #(WIDTH) chain_reg(.clk(clk),
.en(1'b1),
.reset(reset),
.d(reg_inputs[(i+1)*WIDTH-1:i*WIDTH]),
.q(reg_outputs[(i+1)*WIDTH-1:i*WIDTH]));
if (i < DELAY - 1) begin
assign reg_inputs[(i+2)*WIDTH-1:(i+1)*WIDTH] =
reg_outputs[(i+1)*WIDTH-1:i*WIDTH];
end
end
endgenerate
assign q = reg_outputs[(DELAY*WIDTH)-1:(DELAY-1)*WIDTH];
assign reg_inputs[WIDTH-1:0] = d;
endmodule
// D-type Latch.
module CC_DLatch(en, d, q);
parameter WIDTH=1;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
wire [WIDTH-1:0] reg_out;
CC_DFlipFlop #(WIDTH) r(.clk(~en), .en(1'b1), .reset(0), .d(d), .q(reg_out));
assign q = en ? d : reg_out;
endmodule
// Bidirectional I/O pin.
module CC_Bidir(sel_in, io, in, out);
parameter WIDTH=1;
input sel_in;
inout [WIDTH-1:0] io;
output [WIDTH-1:0] in;
input [WIDTH-1:0] out;
assign in = sel_in ? io : {WIDTH{1'bz}};
assign io = sel_in ? {WIDTH{1'bz}} : out;
endmodule
// Double D flip-flop with a 2:1 multiplexed output.
module CC_MuxReg(sel, clk, en, in_a, in_b, out);
parameter WIDTH=8;
input sel;
input clk;
input en;
input [WIDTH-1:0] in_a;
input [WIDTH-1:0] in_b;
output [WIDTH-1:0] out;
wire [WIDTH-1:0] out_a;
wire [WIDTH-1:0] out_b;
CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);
CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);
assign out = sel ? out_a : out_b;
endmodule
// N-to-2^N decoder/selector/demultiplexer.
module CC_Decoder(in, out);
parameter IN_WIDTH=8;
parameter OUT_WIDTH=(1 << IN_WIDTH);
input [IN_WIDTH-1:0] in;
output [OUT_WIDTH-1:0] out;
genvar i;
generate
for (i = 0; i < OUT_WIDTH; i = i + 1)
begin: SELECT
assign out[i] = (i == in) ? 1'b1 : 1'b0;
end
endgenerate
endmodule
|
/*
* NAME
* ----
*
* led_ctl - bussed LED control
*
*
* DESCRIPTION
* -----------
*
* 8-bit bar led module suitable for use with a "bus"
* consisting of address, data and control lines.
*
* To write, data must be assigned to the data bus ('data'),
* write must be enabled (write_n=0), read must not be
* enabled (read_n=1), and the chip must be enabled (ce_n=0).
*
* AUTHOR
* ------
*
* Jeremiah Mahler <[email protected]>
*
*/
module led_ctl(
input read_n,
write_n,
reset_n,
ce_n,
inout [7:0] data,
output reg [7:0] leds);
// ~(leds) and ~(data) are used to invert the inputs/outputs
// to compensate for actual pull up circuit which inverts the
// value.
// READ
// If we are enabled (ce_n lo) and read is enabled (read_n lo)
// and write is not enabled (write_n hi)
// drive the leds values on to the data bus.
assign data = (~(ce_n | read_n | ~write_n)) ? ~(leds) : 8'bz;
// This is a psuedo wire that goes low when BOTH write_n
// and ce_n are low.
// ~A & ~B = ~(A | B) (De Morgans Law)
wire write_ce_n;
assign write_ce_n = write_n | ce_n;
// WRITE
// If anything here changes and reset_n is low, reset leds
// If write_n or ce_n change such that write is enabled
// (write_n lo) and the chip is enabled (ce_n lo)
// write the data to the leds.
always @(negedge reset_n, posedge write_ce_n) begin
if (~reset_n)
leds <= ~(8'h00);
else
leds <= ~(data);
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_transition (clock, reset, enable, test_expr, start_state, next_state, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr, start_state, next_state;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_TRANSITION";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_transition_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_transition_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_transition_psl_logic.v"
`else
`endmodule // ovl_transition
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_4_V
`define SKY130_FD_SC_LS__NAND4BB_4_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_4 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_4 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A21BOI_PP_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_PP_BLACKBOX_V
|
module LCDCONTROL (
input CLK, RST,
input WRITE,
input [8:0] WRDATA,
output reg STATUS,
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA // LCD Data bus 8 bits
);
reg [8:0] cmd;
reg [4:0] en_cnt;
reg [17:0] wait_cnt;
wire st;
wire busy;
reg rst_dly;
reg [19:0] dly_cnt;
assign LCD_RW = 1'b0; // always write
assign LCD_BLON = 1'b1; // Backlight on
assign LCD_RS = cmd[8];
assign LCD_DATA = cmd[7:0];
assign LCD_EN = (en_cnt!=0) ? 1'b1 : 1'b0;
assign st = (WRITE==1 && busy==0) ? 1'b1 : 1'b0;
always @(posedge CLK or posedge RST)
begin
if (RST) begin
dly_cnt <= 20'h0;
rst_dly <= 1'b1;
end
else if (dly_cnt!=20'hFFFFF)
begin
dly_cnt <= dly_cnt + 20'h1;
rst_dly <= 1'b1;
end
else
begin
rst_dly <= 1'b0;
end
end
always @(posedge CLK or posedge RST)
begin
if (RST)
cmd <= 9'h0;
else if (rst_dly)
cmd <= 9'h0;
else if (st)
cmd <= WRDATA[8:0];
end
always @(posedge CLK or posedge RST)
begin
if (RST)
en_cnt <= 5'h0;
else if (rst_dly)
en_cnt <= 5'h0;
else if (st)
en_cnt <= 5'h10;
else if (en_cnt!=5'h0)
en_cnt <= en_cnt - 5'h1;
end
always @(posedge CLK or posedge RST)
begin
if (RST)
wait_cnt <= 18'h00000;
else if (rst_dly)
wait_cnt <= 18'h00000;
else if (en_cnt == 5'h1)
wait_cnt <= 18'h3FFFF; // this should be changed depending on the command
else if (wait_cnt!=18'h0)
wait_cnt <= wait_cnt - 18'h1;
end
assign busy = (en_cnt==5'h0 && wait_cnt==18'h0) ? 1'b0 : 1'b1;
always @(posedge CLK or posedge RST)
begin
if (RST)
STATUS <= 1'b1;
else if (rst_dly)
STATUS <= 1'b1;
else
STATUS <= st | busy;
end
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* 10G Ethernet PHY RX IF
*/
module eth_phy_10g_rx_if #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_rx_data,
output wire [HDR_WIDTH-1:0] encoded_rx_hdr,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
output wire serdes_rx_reset_req,
/*
* Status
*/
input wire rx_bad_block,
input wire rx_sequence_error,
output wire [6:0] rx_error_count,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] serdes_rx_data_rev, serdes_rx_data_int;
wire [HDR_WIDTH-1:0] serdes_rx_hdr_rev, serdes_rx_hdr_int;
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_rx_data_rev[n] = serdes_rx_data[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_rx_hdr_rev[n] = serdes_rx_hdr[HDR_WIDTH-n-1];
end
end else begin
assign serdes_rx_data_rev = serdes_rx_data;
assign serdes_rx_hdr_rev = serdes_rx_hdr;
end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_WIDTH-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_WIDTH-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
for (n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_rx_data_pipe_reg[n] <= {DATA_WIDTH{1'b0}};
serdes_rx_hdr_pipe_reg[n] <= {HDR_WIDTH{1'b0}};
end
always @(posedge clk) begin
serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1];
end
end
assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_hdr_int = serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1];
end else begin
assign serdes_rx_data_int = serdes_rx_data_rev;
assign serdes_rx_hdr_int = serdes_rx_hdr_rev;
end
endgenerate
wire [DATA_WIDTH-1:0] descrambled_rx_data;
reg [DATA_WIDTH-1:0] encoded_rx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] encoded_rx_hdr_reg = {HDR_WIDTH{1'b0}};
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
reg [30:0] prbs31_state_reg = 31'h7fffffff;
wire [30:0] prbs31_state;
wire [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data;
reg [6:0] rx_error_count_reg = 0;
reg [5:0] rx_error_count_1_reg = 0;
reg [5:0] rx_error_count_2_reg = 0;
reg [5:0] rx_error_count_1_temp = 0;
reg [5:0] rx_error_count_2_temp = 0;
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
)
descrambler_inst (
.data_in(serdes_rx_data_int),
.state_in(scrambler_state_reg),
.data_out(descrambled_rx_data),
.state_out(scrambler_state)
);
lfsr #(
.LFSR_WIDTH(31),
.LFSR_POLY(31'h10000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH+HDR_WIDTH),
.STYLE("AUTO")
)
prbs31_check_inst (
.data_in(~{serdes_rx_data_int, serdes_rx_hdr_int}),
.state_in(prbs31_state_reg),
.data_out(prbs31_data),
.state_out(prbs31_state)
);
integer i;
always @* begin
rx_error_count_1_temp = 0;
rx_error_count_2_temp = 0;
for (i = 0; i < DATA_WIDTH+HDR_WIDTH; i = i + 1) begin
if (i & 1) begin
rx_error_count_1_temp = rx_error_count_1_temp + prbs31_data[i];
end else begin
rx_error_count_2_temp = rx_error_count_2_temp + prbs31_data[i];
end
end
end
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
if (PRBS31_ENABLE && rx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
rx_error_count_1_reg <= rx_error_count_1_temp;
rx_error_count_2_reg <= rx_error_count_2_temp;
rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg;
end
end
assign encoded_rx_data = encoded_rx_data_reg;
assign encoded_rx_hdr = encoded_rx_hdr_reg;
assign rx_error_count = rx_error_count_reg;
wire serdes_rx_bitslip_int;
wire serdes_rx_reset_req_int;
assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && rx_prbs31_enable);
assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_ENABLE && rx_prbs31_enable);
eth_phy_10g_rx_frame_sync #(
.HDR_WIDTH(HDR_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES)
)
eth_phy_10g_rx_frame_sync_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_bitslip(serdes_rx_bitslip_int),
.rx_block_lock(rx_block_lock)
);
eth_phy_10g_rx_ber_mon #(
.HDR_WIDTH(HDR_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_ber_mon_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.rx_high_ber(rx_high_ber)
);
eth_phy_10g_rx_watchdog #(
.HDR_WIDTH(HDR_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_watchdog_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_reset_req(serdes_rx_reset_req_int),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber)
);
endmodule
`resetall
|
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
(* ram_init_file = "hub_rom_low.hex" *) reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
(* ram_init_file = "hub_rom_high.hex" *) reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
: !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "setup.v"
module system(
input clkin,
input resetin,
// Boot ROM
output [24:0] flash_adr,
input [31:0] flash_d,
output flash_byte_n,
output flash_oe_n,
output flash_we_n,
output flash_ce,
output flash_ac97_reset_n,
output sram_clk,
output sram_ce_n,
output sram_zz,
// UART
input uart_rxd,
output uart_txd,
// DDR SDRAM
output sdram_clk_p,
output sdram_clk_n,
input sdram_clk_fb,
output sdram_cke,
output sdram_cs_n,
output sdram_we_n,
output sdram_cas_n,
output sdram_ras_n,
output [3:0] sdram_dqm,
output [12:0] sdram_adr,
output [1:0] sdram_ba,
inout [31:0] sdram_dq,
inout [3:0] sdram_dqs,
// GPIO
input [4:0] btn, // 5
output [4:0] btnled, // 5
output [3:0] led, // 2 (2 LEDs for UART activity)
input [7:0] dipsw, // 8
output lcd_e, // 1
output lcd_rs, // 1
output lcd_rw, // 1
output [3:0] lcd_d, // 4
// 13 14
// VGA
output vga_psave_n,
output vga_hsync_n,
output vga_vsync_n,
output vga_sync_n,
output vga_blank_n,
output [7:0] vga_r,
output [7:0] vga_g,
output [7:0] vga_b,
output vga_clkout,
// SystemACE/USB
output [6:0] aceusb_a,
inout [15:0] aceusb_d,
output aceusb_oe_n,
output aceusb_we_n,
input ace_clkin,
output ace_mpce_n,
input ace_mpirq,
output usb_cs_n,
output usb_hpi_reset_n,
input usb_hpi_int,
// AC97
input ac97_clk,
input ac97_sin,
output ac97_sout,
output ac97_sync,
// PS2
inout ps2_clk1,
inout ps2_data1,
inout ps2_clk2,
inout ps2_data2,
// Ethernet
output phy_rst_n,
input phy_tx_clk,
output [3:0] phy_tx_data,
output phy_tx_en,
output phy_tx_er,
input phy_rx_clk,
input [3:0] phy_rx_data,
input phy_dv,
input phy_rx_er,
input phy_col,
input phy_crs,
output phy_mii_clk,
inout phy_mii_data,
// USB
inout usba_vp,
inout usba_vm,
inout usbb_vp,
inout usbb_vm
);
//------------------------------------------------------------------
// Clock and Reset Generation
//------------------------------------------------------------------
wire sys_clk;
wire hard_reset;
`ifndef SIMULATION
BUFG clkbuf(
.I(clkin),
.O(sys_clk)
);
`else
assign sys_clk = clkin;
`endif
`ifndef SIMULATION
/* Synchronize the reset input */
reg rst0;
reg rst1;
always @(posedge sys_clk) rst0 <= resetin;
always @(posedge sys_clk) rst1 <= rst0;
/* Debounce it (counter holds reset for 10.49ms),
* and generate power-on reset.
*/
reg [19:0] rst_debounce;
reg sys_rst;
initial rst_debounce <= 20'hFFFFF;
initial sys_rst <= 1'b1;
always @(posedge sys_clk) begin
if(~rst1 | hard_reset) /* reset pin is active low */
rst_debounce <= 20'hFFFFF;
else if(rst_debounce != 20'd0)
rst_debounce <= rst_debounce - 20'd1;
sys_rst <= rst_debounce != 20'd0;
end
/*
* We must release the Flash reset before the system reset
* because the Flash needs some time to come out of reset
* and the CPU begins fetching instructions from it
* as soon as the system reset is released.
* From datasheet, minimum reset pulse width is 100ns
* and reset-to-read time is 150ns.
* On the ML401, the reset is combined with the AC97
* reset, which must be held for 1us.
* Here we use a 7-bit counter that holds reset
* for 1.28us and makes everybody happy.
*/
reg [7:0] flash_rstcounter;
initial flash_rstcounter <= 8'd0;
always @(posedge sys_clk) begin
if(~rst1 & ~sys_rst) /* ~sys_rst is for debouncing */
flash_rstcounter <= 8'd0;
else if(~flash_rstcounter[7])
flash_rstcounter <= flash_rstcounter + 8'd1;
end
assign flash_ac97_reset_n = flash_rstcounter[7];
wire ac97_rst_n;
assign ac97_rst_n = flash_rstcounter[7];
/* Just use the same signal for PHY reset */
assign phy_rst_n = flash_rstcounter[7];
`else
wire sys_rst;
assign sys_rst = ~resetin;
`endif
//------------------------------------------------------------------
// Wishbone master wires
//------------------------------------------------------------------
wire [31:0] cpuibus_adr,
cpudbus_adr,
ac97bus_adr,
pfpubus_adr,
tmumbus_adr,
ethernetrxbus_adr,
ethernettxbus_adr;
wire [2:0] cpuibus_cti,
cpudbus_cti,
ac97bus_cti,
tmumbus_cti,
ethernetrxbus_cti,
ethernettxbus_cti;
wire [31:0] cpuibus_dat_r,
cpudbus_dat_r,
cpudbus_dat_w,
ac97bus_dat_r,
ac97bus_dat_w,
pfpubus_dat_w,
tmumbus_dat_r,
ethernetrxbus_dat_w,
ethernettxbus_dat_r;
wire [3:0] cpudbus_sel;
wire cpudbus_we,
ac97bus_we;
wire cpuibus_cyc,
cpudbus_cyc,
ac97bus_cyc,
pfpubus_cyc,
tmumbus_cyc,
ethernetrxbus_cyc,
ethernettxbus_cyc;
wire cpuibus_stb,
cpudbus_stb,
ac97bus_stb,
pfpubus_stb,
tmumbus_stb,
ethernetrxbus_stb,
ethernettxbus_stb;
wire cpuibus_ack,
cpudbus_ack,
ac97bus_ack,
tmumbus_ack,
pfpubus_ack,
ethernetrxbus_ack,
ethernettxbus_ack;
//------------------------------------------------------------------
// Wishbone slave wires
//------------------------------------------------------------------
wire [31:0] norflash_adr,
usb_adr,
brg_adr,
csrbrg_adr,
aceusb_adr;
wire [2:0] brg_cti;
wire [31:0] norflash_dat_r,
norflash_dat_w,
usb_dat_r,
usb_dat_w,
brg_dat_r,
brg_dat_w,
csrbrg_dat_r,
csrbrg_dat_w,
aceusb_dat_r,
aceusb_dat_w;
wire [3:0] norflash_sel,
usb_sel,
brg_sel;
wire norflash_we,
usb_we,
brg_we,
csrbrg_we,
aceusb_we;
wire norflash_cyc,
usb_cyc,
brg_cyc,
csrbrg_cyc,
aceusb_cyc;
wire norflash_stb,
usb_stb,
brg_stb,
csrbrg_stb,
aceusb_stb;
wire norflash_ack,
usb_ack,
brg_ack,
csrbrg_ack,
aceusb_ack;
//---------------------------------------------------------------------------
// Wishbone switch
//---------------------------------------------------------------------------
conbus #(
/* MSB (Bit 31) is ignored by conbus */
.s_addr_w(3),
.s0_addr(3'b000), // norflash 0x00000000 (shadow @0x80000000)
.s1_addr(3'b010), // USB 0x20000000 (shadow @0xa0000000)
.s2_addr(3'b100), // FML bridge 0x40000000 (shadow @0xc0000000)
.s3_addr(3'b110), // CSR bridge 0x60000000 (shadow @0xe0000000)
.s4_addr(3'b111) // aceusb 0x70000000 (shadow @0xf0000000)
) conbus (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
// Master 0
.m0_dat_i(32'hx),
.m0_dat_o(cpuibus_dat_r),
.m0_adr_i(cpuibus_adr),
.m0_cti_i(cpuibus_cti),
.m0_we_i(1'b0),
.m0_sel_i(4'hf),
.m0_cyc_i(cpuibus_cyc),
.m0_stb_i(cpuibus_stb),
.m0_ack_o(cpuibus_ack),
// Master 1
.m1_dat_i(cpudbus_dat_w),
.m1_dat_o(cpudbus_dat_r),
.m1_adr_i(cpudbus_adr),
.m1_cti_i(cpudbus_cti),
.m1_we_i(cpudbus_we),
.m1_sel_i(cpudbus_sel),
.m1_cyc_i(cpudbus_cyc),
.m1_stb_i(cpudbus_stb),
.m1_ack_o(cpudbus_ack),
// Master 2
.m2_dat_i(ac97bus_dat_w),
.m2_dat_o(ac97bus_dat_r),
.m2_adr_i(ac97bus_adr),
.m2_cti_i(ac97bus_cti),
.m2_we_i(ac97bus_we),
.m2_sel_i(4'hf),
.m2_cyc_i(ac97bus_cyc),
.m2_stb_i(ac97bus_stb),
.m2_ack_o(ac97bus_ack),
// Master 3
.m3_dat_i(pfpubus_dat_w),
.m3_dat_o(),
.m3_adr_i(pfpubus_adr),
.m3_cti_i(3'd0),
.m3_we_i(1'b1),
.m3_sel_i(4'hf),
.m3_cyc_i(pfpubus_cyc),
.m3_stb_i(pfpubus_stb),
.m3_ack_o(pfpubus_ack),
// Master 4
.m4_dat_i(32'bx),
.m4_dat_o(tmumbus_dat_r),
.m4_adr_i(tmumbus_adr),
.m4_cti_i(tmumbus_cti),
.m4_we_i(1'b0),
.m4_sel_i(4'hf),
.m4_cyc_i(tmumbus_cyc),
.m4_stb_i(tmumbus_stb),
.m4_ack_o(tmumbus_ack),
// Master 5
.m5_dat_i(ethernetrxbus_dat_w),
.m5_dat_o(),
.m5_adr_i(ethernetrxbus_adr),
.m5_cti_i(ethernetrxbus_cti),
.m5_we_i(1'b1),
.m5_sel_i(4'hf),
.m5_cyc_i(ethernetrxbus_cyc),
.m5_stb_i(ethernetrxbus_stb),
.m5_ack_o(ethernetrxbus_ack),
// Master 6
.m6_dat_i(32'bx),
.m6_dat_o(ethernettxbus_dat_r),
.m6_adr_i(ethernettxbus_adr),
.m6_cti_i(ethernettxbus_cti),
.m6_we_i(1'b0),
.m6_sel_i(4'hf),
.m6_cyc_i(ethernettxbus_cyc),
.m6_stb_i(ethernettxbus_stb),
.m6_ack_o(ethernettxbus_ack),
// Slave 0
.s0_dat_i(norflash_dat_r),
.s0_dat_o(norflash_dat_w),
.s0_adr_o(norflash_adr),
.s0_sel_o(norflash_sel),
.s0_we_o(norflash_we),
.s0_cyc_o(norflash_cyc),
.s0_stb_o(norflash_stb),
.s0_ack_i(norflash_ack),
// Slave 1
.s1_dat_i(usb_dat_r),
.s1_dat_o(usb_dat_w),
.s1_adr_o(usb_adr),
.s1_cti_o(),
.s1_sel_o(usb_sel),
.s1_we_o(usb_we),
.s1_cyc_o(usb_cyc),
.s1_stb_o(usb_stb),
.s1_ack_i(usb_ack),
// Slave 2
.s2_dat_i(brg_dat_r),
.s2_dat_o(brg_dat_w),
.s2_adr_o(brg_adr),
.s2_cti_o(brg_cti),
.s2_sel_o(brg_sel),
.s2_we_o(brg_we),
.s2_cyc_o(brg_cyc),
.s2_stb_o(brg_stb),
.s2_ack_i(brg_ack),
// Slave 3
.s3_dat_i(csrbrg_dat_r),
.s3_dat_o(csrbrg_dat_w),
.s3_adr_o(csrbrg_adr),
.s3_we_o(csrbrg_we),
.s3_cyc_o(csrbrg_cyc),
.s3_stb_o(csrbrg_stb),
.s3_ack_i(csrbrg_ack),
// Slave 4
.s4_dat_i(aceusb_dat_r),
.s4_dat_o(aceusb_dat_w),
.s4_adr_o(aceusb_adr),
.s4_we_o(aceusb_we),
.s4_cyc_o(aceusb_cyc),
.s4_stb_o(aceusb_stb),
.s4_ack_i(aceusb_ack)
);
//------------------------------------------------------------------
// CSR bus
//------------------------------------------------------------------
wire [13:0] csr_a;
wire csr_we;
wire [31:0] csr_dw;
wire [31:0] csr_dr_uart,
csr_dr_sysctl,
csr_dr_hpdmc,
csr_dr_vga,
csr_dr_ac97,
csr_dr_pfpu,
csr_dr_tmu,
csr_dr_ethernet,
csr_dr_fmlmeter,
csr_dr_usb,
csr_dr_ps2,
csr_dr_mouse;
//------------------------------------------------------------------
// FML master wires
//------------------------------------------------------------------
wire [`SDRAM_DEPTH-1:0] fml_brg_adr,
fml_vga_adr,
fml_tmur_adr,
fml_tmudr_adr,
fml_tmuw_adr;
wire fml_brg_stb,
fml_vga_stb,
fml_tmur_stb,
fml_tmudr_stb,
fml_tmuw_stb;
wire fml_brg_we;
wire fml_brg_ack,
fml_vga_ack,
fml_tmur_ack,
fml_tmudr_ack,
fml_tmuw_ack;
wire [7:0] fml_brg_sel,
fml_tmuw_sel;
wire [63:0] fml_brg_dw,
fml_tmuw_dw;
wire [63:0] fml_brg_dr,
fml_vga_dr,
fml_tmur_dr,
fml_tmudr_dr;
//------------------------------------------------------------------
// FML slave wires, to memory controller
//------------------------------------------------------------------
wire [`SDRAM_DEPTH-1:0] fml_adr;
wire fml_stb;
wire fml_we;
wire fml_ack;
wire [7:0] fml_sel;
wire [63:0] fml_dw;
wire [63:0] fml_dr;
//---------------------------------------------------------------------------
// FML arbiter
//---------------------------------------------------------------------------
fmlarb #(
.fml_depth(`SDRAM_DEPTH)
) fmlarb (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
/* VGA framebuffer (high priority) */
.m0_adr(fml_vga_adr),
.m0_stb(fml_vga_stb),
.m0_we(1'b0),
.m0_ack(fml_vga_ack),
.m0_sel(8'bx),
.m0_di(64'bx),
.m0_do(fml_vga_dr),
/* WISHBONE bridge */
.m1_adr(fml_brg_adr),
.m1_stb(fml_brg_stb),
.m1_we(fml_brg_we),
.m1_ack(fml_brg_ack),
.m1_sel(fml_brg_sel),
.m1_di(fml_brg_dw),
.m1_do(fml_brg_dr),
/* TMU, pixel read DMA (texture) */
.m2_adr(fml_tmur_adr),
.m2_stb(fml_tmur_stb),
.m2_we(1'b0),
.m2_ack(fml_tmur_ack),
.m2_sel(8'bx),
.m2_di(64'bx),
.m2_do(fml_tmur_dr),
/* TMU, pixel write DMA */
.m3_adr(fml_tmuw_adr),
.m3_stb(fml_tmuw_stb),
.m3_we(1'b1),
.m3_ack(fml_tmuw_ack),
.m3_sel(fml_tmuw_sel),
.m3_di(fml_tmuw_dw),
.m3_do(),
/* TMU, pixel read DMA (destination) */
.m4_adr(fml_tmudr_adr),
.m4_stb(fml_tmudr_stb),
.m4_we(1'b0),
.m4_ack(fml_tmudr_ack),
.m4_sel(8'bx),
.m4_di(64'bx),
.m4_do(fml_tmudr_dr),
.s_adr(fml_adr),
.s_stb(fml_stb),
.s_we(fml_we),
.s_ack(fml_ack),
.s_sel(fml_sel),
.s_di(fml_dr),
.s_do(fml_dw)
);
//---------------------------------------------------------------------------
// WISHBONE to CSR bridge
//---------------------------------------------------------------------------
csrbrg csrbrg(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(csrbrg_adr),
.wb_dat_i(csrbrg_dat_w),
.wb_dat_o(csrbrg_dat_r),
.wb_cyc_i(csrbrg_cyc),
.wb_stb_i(csrbrg_stb),
.wb_we_i(csrbrg_we),
.wb_ack_o(csrbrg_ack),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_do(csr_dw),
/* combine all slave->master data lines with an OR */
.csr_di(
csr_dr_uart
|csr_dr_sysctl
|csr_dr_hpdmc
|csr_dr_vga
|csr_dr_ac97
|csr_dr_pfpu
|csr_dr_tmu
|csr_dr_ethernet
|csr_dr_fmlmeter
|csr_dr_usb
|csr_dr_ps2
|csr_dr_mouse
)
);
//---------------------------------------------------------------------------
// WISHBONE to FML bridge
//---------------------------------------------------------------------------
wire dcb_stb;
wire [`SDRAM_DEPTH-1:0] dcb_adr;
wire [63:0] dcb_dat;
wire dcb_hit;
fmlbrg #(
.fml_depth(`SDRAM_DEPTH)
) fmlbrg (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(brg_adr),
.wb_cti_i(brg_cti),
.wb_dat_o(brg_dat_r),
.wb_dat_i(brg_dat_w),
.wb_sel_i(brg_sel),
.wb_stb_i(brg_stb),
.wb_cyc_i(brg_cyc),
.wb_ack_o(brg_ack),
.wb_we_i(brg_we),
.fml_adr(fml_brg_adr),
.fml_stb(fml_brg_stb),
.fml_we(fml_brg_we),
.fml_ack(fml_brg_ack),
.fml_sel(fml_brg_sel),
.fml_di(fml_brg_dr),
.fml_do(fml_brg_dw),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit)
);
//---------------------------------------------------------------------------
// Interrupts
//---------------------------------------------------------------------------
wire gpio_irq;
wire timer0_irq;
wire timer1_irq;
wire uartrx_irq;
wire uarttx_irq;
wire ac97crrequest_irq;
wire ac97crreply_irq;
wire ac97dmar_irq;
wire ac97dmaw_irq;
wire pfpu_irq;
wire tmu_irq;
wire ethernetrx_irq;
wire ethernettx_irq;
wire usb_irq;
wire keyboard_irq;
wire mouse_irq;
wire [31:0] cpu_interrupt;
assign cpu_interrupt = {14'd0,
usb_irq,
1'b0,
mouse_irq,
keyboard_irq,
1'b0,
ethernettx_irq,
ethernetrx_irq,
tmu_irq,
pfpu_irq,
ac97dmaw_irq,
ac97dmar_irq,
ac97crreply_irq,
ac97crrequest_irq,
timer1_irq,
timer0_irq,
gpio_irq,
uarttx_irq,
uartrx_irq
};
//---------------------------------------------------------------------------
// LM32 CPU
//---------------------------------------------------------------------------
lm32_top cpu(
.clk_i(sys_clk),
.rst_i(sys_rst),
.interrupt(cpu_interrupt),
.I_ADR_O(cpuibus_adr),
.I_DAT_I(cpuibus_dat_r),
.I_DAT_O(),
.I_SEL_O(),
.I_CYC_O(cpuibus_cyc),
.I_STB_O(cpuibus_stb),
.I_ACK_I(cpuibus_ack),
.I_WE_O(),
.I_CTI_O(cpuibus_cti),
.I_LOCK_O(),
.I_BTE_O(),
.I_ERR_I(1'b0),
.I_RTY_I(1'b0),
.D_ADR_O(cpudbus_adr),
.D_DAT_I(cpudbus_dat_r),
.D_DAT_O(cpudbus_dat_w),
.D_SEL_O(cpudbus_sel),
.D_CYC_O(cpudbus_cyc),
.D_STB_O(cpudbus_stb),
.D_ACK_I(cpudbus_ack),
.D_WE_O (cpudbus_we),
.D_CTI_O(cpudbus_cti),
.D_LOCK_O(),
.D_BTE_O(),
.D_ERR_I(1'b0),
.D_RTY_I(1'b0)
);
//---------------------------------------------------------------------------
// Boot ROM
//---------------------------------------------------------------------------
norflash32 #(
.adr_width(21)
) norflash (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(norflash_adr),
.wb_dat_o(norflash_dat_r),
.wb_stb_i(norflash_stb),
.wb_cyc_i(norflash_cyc),
.wb_ack_o(norflash_ack),
.flash_adr(flash_adr[21:1]),
.flash_d(flash_d)
);
assign flash_adr[0] = 1'b0;
assign flash_adr[24:22] = 3'b000;
assign flash_byte_n = 1'b1;
assign flash_oe_n = 1'b0;
assign flash_we_n = 1'b1;
assign flash_ce = 1'b1;
/*
* Disable the SRAM.
* Since CE_N is a synchronous input
* we also clock the SRAM so that
* we make sure it gets the message.
*/
assign sram_clk = sys_clk;
assign sram_ce_n = 1'b1;
assign sram_zz = 1'b1;
//---------------------------------------------------------------------------
// UART
//---------------------------------------------------------------------------
uart #(
.csr_addr(4'h0),
.clk_freq(`CLOCK_FREQUENCY),
.baud(`BAUD_RATE)
) uart (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_uart),
.rx_irq(uartrx_irq),
.tx_irq(uarttx_irq),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd)
);
/* LED0 and LED1 are used as TX/RX indicators.
* Generate long pulses so we have time to see them
*/
reg [18:0] rxcounter;
reg rxled;
always @(posedge sys_clk) begin
if(~uart_rxd)
rxcounter <= {19{1'b1}};
else if(rxcounter != 19'd0)
rxcounter <= rxcounter - 19'd1;
rxled <= rxcounter != 19'd0;
end
reg [18:0] txcounter;
reg txled;
always @(posedge sys_clk) begin
if(~uart_txd)
txcounter <= {19{1'b1}};
else if(txcounter != 19'd0)
txcounter <= txcounter - 20'd1;
txled <= txcounter != 19'd0;
end
assign led[0] = txled;
assign led[1] = rxled;
//---------------------------------------------------------------------------
// System Controller
//---------------------------------------------------------------------------
wire [13:0] gpio_outputs;
wire [31:0] capabilities;
sysctl #(
.csr_addr(4'h1),
.ninputs(13),
.noutputs(14),
.systemid(32'h58343031) /* X401 */
) sysctl (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.gpio_irq(gpio_irq),
.timer0_irq(timer0_irq),
.timer1_irq(timer1_irq),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_sysctl),
.gpio_inputs({dipsw, btn}),
.gpio_outputs(gpio_outputs),
.capabilities(capabilities),
.hard_reset(hard_reset)
);
gen_capabilities gen_capabilities(
.capabilities(capabilities)
);
/* LED0 and LED1 are used as TX/RX indicators. */
assign led[2] = gpio_outputs[0];
assign led[3] = gpio_outputs[1];
assign btnled = gpio_outputs[6:2];
assign lcd_e = gpio_outputs[7];
assign lcd_rs = gpio_outputs[8];
assign lcd_rw = gpio_outputs[9];
assign lcd_d = gpio_outputs[13:10];
//---------------------------------------------------------------------------
// SystemACE/USB interface
//---------------------------------------------------------------------------
`ifdef ENABLE_ACEUSB
aceusb aceusb(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_cyc_i(aceusb_cyc),
.wb_stb_i(aceusb_stb),
.wb_ack_o(aceusb_ack),
.wb_adr_i(aceusb_adr),
.wb_dat_i(aceusb_dat_w),
.wb_dat_o(aceusb_dat_r),
.wb_we_i(aceusb_we),
.aceusb_a(aceusb_a),
.aceusb_d(aceusb_d),
.aceusb_oe_n(aceusb_oe_n),
.aceusb_we_n(aceusb_we_n),
.ace_clkin(ace_clkin),
.ace_mpce_n(ace_mpce_n),
.ace_mpirq(ace_mpirq),
.usb_cs_n(usb_cs_n),
.usb_hpi_reset_n(usb_hpi_reset_n),
.usb_hpi_int(usb_hpi_int)
);
`else
assign aceusb_a = 7'd0;
assign aceusb_d = 16'bz;
assign aceusb_oe_n = 1'b1;
assign aceusb_we_n = 1'b1;
assign ace_mpce_n = 1'b0;
assign usb_cs_n = 1'b1;
assign usb_hpi_reset_n = 1'b1;
assign aceusb_ack = aceusb_cyc & aceusb_stb;
assign aceusb_dat_r = 32'habadface;
`endif
//---------------------------------------------------------------------------
// DDR SDRAM
//---------------------------------------------------------------------------
ddram #(
.csr_addr(4'h2)
) ddram (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_hpdmc),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_di(fml_dw),
.fml_do(fml_dr),
.sdram_clk_p(sdram_clk_p),
.sdram_clk_n(sdram_clk_n),
.sdram_clk_fb(sdram_clk_fb),
.sdram_cke(sdram_cke),
.sdram_cs_n(sdram_cs_n),
.sdram_we_n(sdram_we_n),
.sdram_cas_n(sdram_cas_n),
.sdram_ras_n(sdram_ras_n),
.sdram_dqm(sdram_dqm),
.sdram_adr(sdram_adr),
.sdram_ba(sdram_ba),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs)
);
//---------------------------------------------------------------------------
// VGA
//---------------------------------------------------------------------------
vga #(
.csr_addr(4'h3),
.fml_depth(`SDRAM_DEPTH)
) vga (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_vga),
.fml_adr(fml_vga_adr),
.fml_stb(fml_vga_stb),
.fml_ack(fml_vga_ack),
.fml_di(fml_vga_dr),
.dcb_stb(dcb_stb),
.dcb_adr(dcb_adr),
.dcb_dat(dcb_dat),
.dcb_hit(dcb_hit),
.vga_psave_n(vga_psave_n),
.vga_hsync_n(vga_hsync_n),
.vga_vsync_n(vga_vsync_n),
.vga_sync_n(vga_sync_n),
.vga_blank_n(vga_blank_n),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b),
.vga_clkout(vga_clkout)
);
//---------------------------------------------------------------------------
// AC97
//---------------------------------------------------------------------------
`ifdef ENABLE_AC97
ac97 #(
.csr_addr(4'h5)
) ac97 (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.ac97_clk(ac97_clk),
.ac97_rst_n(ac97_rst_n),
.ac97_sin(ac97_sin),
.ac97_sout(ac97_sout),
.ac97_sync(ac97_sync),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_ac97),
.crrequest_irq(ac97crrequest_irq),
.crreply_irq(ac97crreply_irq),
.dmar_irq(ac97dmar_irq),
.dmaw_irq(ac97dmaw_irq),
.wbm_adr_o(ac97bus_adr),
.wbm_cti_o(ac97bus_cti),
.wbm_we_o(ac97bus_we),
.wbm_cyc_o(ac97bus_cyc),
.wbm_stb_o(ac97bus_stb),
.wbm_ack_i(ac97bus_ack),
.wbm_dat_i(ac97bus_dat_r),
.wbm_dat_o(ac97bus_dat_w)
);
`else
assign csr_dr_ac97 = 32'd0;
assign ac97crrequest_irq = 1'b0;
assign ac97crreply_irq = 1'b0;
assign ac97dmar_irq = 1'b0;
assign ac97dmaw_irq = 1'b0;
assign ac97_sout = 1'b0;
assign ac97_sync = 1'b0;
assign ac97bus_adr = 32'bx;
assign ac97bus_cti = 3'bx;
assign ac97bus_we = 1'bx;
assign ac97bus_cyc = 1'b0;
assign ac97bus_stb = 1'b0;
assign ac97bus_dat_w = 32'bx;
`endif
//---------------------------------------------------------------------------
// Programmable FPU
//---------------------------------------------------------------------------
`ifdef ENABLE_PFPU
pfpu #(
.csr_addr(4'h6)
) pfpu (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_pfpu),
.irq(pfpu_irq),
.wbm_dat_o(pfpubus_dat_w),
.wbm_adr_o(pfpubus_adr),
.wbm_cyc_o(pfpubus_cyc),
.wbm_stb_o(pfpubus_stb),
.wbm_ack_i(pfpubus_ack)
);
`else
assign csr_dr_pfpu = 32'd0;
assign pfpu_irq = 1'b0;
assign pfpubus_dat_w = 32'hx;
assign pfpubus_adr = 32'hx;
assign pfpubus_cyc = 1'b0;
assign pfpubus_stb = 1'b0;
`endif
//---------------------------------------------------------------------------
// Texture Mapping Unit
//---------------------------------------------------------------------------
`ifdef ENABLE_TMU
tmu2 #(
.csr_addr(4'h7),
.fml_depth(`SDRAM_DEPTH)
) tmu (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_tmu),
.irq(tmu_irq),
.wbm_adr_o(tmumbus_adr),
.wbm_cti_o(tmumbus_cti),
.wbm_cyc_o(tmumbus_cyc),
.wbm_stb_o(tmumbus_stb),
.wbm_ack_i(tmumbus_ack),
.wbm_dat_i(tmumbus_dat_r),
.fmlr_adr(fml_tmur_adr),
.fmlr_stb(fml_tmur_stb),
.fmlr_ack(fml_tmur_ack),
.fmlr_di(fml_tmur_dr),
.fmldr_adr(fml_tmudr_adr),
.fmldr_stb(fml_tmudr_stb),
.fmldr_ack(fml_tmudr_ack),
.fmldr_di(fml_tmudr_dr),
.fmlw_adr(fml_tmuw_adr),
.fmlw_stb(fml_tmuw_stb),
.fmlw_ack(fml_tmuw_ack),
.fmlw_sel(fml_tmuw_sel),
.fmlw_do(fml_tmuw_dw)
);
`else
assign csr_dr_tmu = 32'd0;
assign tmu_irq = 1'b0;
assign tmumbus_adr = 32'hx;
assign tmumbus_cti = 3'bxxx;
assign tmumbus_cyc = 1'b0;
assign tmumbus_stb = 1'b0;
assign fml_tmur_adr = {`SDRAM_DEPTH{1'bx}};
assign fml_tmur_stb = 1'b0;
assign fml_tmudr_adr = {`SDRAM_DEPTH{1'bx}};
assign fml_tmudr_stb = 1'b0;
assign fml_tmuw_adr = {`SDRAM_DEPTH{1'bx}};
assign fml_tmuw_stb = 1'b0;
assign fml_tmuw_sel = 8'bx;
assign fml_tmuw_dw = 64'bx;
`endif
//---------------------------------------------------------------------------
// PS2 Interface
//---------------------------------------------------------------------------
`ifdef ENABLE_PS2_KEYBOARD
ps2 #(
.csr_addr(4'hc),
.clk_freq(`CLOCK_FREQUENCY)
) ps2_keyboard (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_ps2),
.ps2_clk(ps2_clk1),
.ps2_data(ps2_data1),
.irq(keyboard_irq)
);
`else
assign csr_dr_ps2 = 32'd0;
assign keyboard_irq = 1'd0;
`endif
`ifdef ENABLE_PS2_MOUSE
ps2 #(
.csr_addr(4'hd),
.clk_freq(`CLOCK_FREQUENCY)
) ps2_mouse (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_mouse),
.ps2_clk(ps2_clk2),
.ps2_data(ps2_data2),
.irq(mouse_irq)
);
`else
assign csr_dr_mouse = 32'd0;
assign mouse_irq = 1'd0;
`endif
//---------------------------------------------------------------------------
// Ethernet
//---------------------------------------------------------------------------
`ifdef ENABLE_ETHERNET
minimac #(
.csr_addr(4'h8)
) ethernet (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_ethernet),
.wbrx_adr_o(ethernetrxbus_adr),
.wbrx_cti_o(ethernetrxbus_cti),
.wbrx_cyc_o(ethernetrxbus_cyc),
.wbrx_stb_o(ethernetrxbus_stb),
.wbrx_ack_i(ethernetrxbus_ack),
.wbrx_dat_o(ethernetrxbus_dat_w),
.wbtx_adr_o(ethernettxbus_adr),
.wbtx_cti_o(ethernettxbus_cti),
.wbtx_cyc_o(ethernettxbus_cyc),
.wbtx_stb_o(ethernettxbus_stb),
.wbtx_ack_i(ethernettxbus_ack),
.wbtx_dat_i(ethernettxbus_dat_r),
.irq_rx(ethernetrx_irq),
.irq_tx(ethernettx_irq),
.phy_tx_clk(phy_tx_clk),
.phy_tx_data(phy_tx_data),
.phy_tx_en(phy_tx_en),
.phy_tx_er(phy_tx_er),
.phy_rx_clk(phy_rx_clk),
.phy_rx_data(phy_rx_data),
.phy_dv(phy_dv),
.phy_rx_er(phy_rx_er),
.phy_col(phy_col),
.phy_crs(phy_crs),
.phy_mii_clk(phy_mii_clk),
.phy_mii_data(phy_mii_data)
);
`else
assign csr_dr_ethernet = 32'd0;
assign ethernetrxbus_adr = 32'bx;
assign ethernetrxbus_cti = 3'bx;
assign ethernetrxbus_cyc = 1'b0;
assign ethernetrxbus_stb = 1'b0;
assign ethernetrxbus_dat_w = 32'bx;
assign ethernettxbus_adr = 32'bx;
assign ethernettxbus_cti = 3'bx;
assign ethernettxbus_cyc = 1'b0;
assign ethernettxbus_stb = 1'b0;
assign ethernettxbus_dat_r = 32'bx;
assign ethernetrx_irq = 1'b0;
assign ethernettx_irq = 1'b0;
assign phy_tx_data = 4'b0;
assign phy_tx_en = 1'b0;
assign phy_tx_er = 1'b0;
assign phy_mii_clk = 1'b0;
assign phy_mii_data = 1'bz;
`endif
//---------------------------------------------------------------------------
// FastMemoryLink usage and performance meter
//---------------------------------------------------------------------------
`ifdef ENABLE_FMLMETER
fmlmeter #(
.csr_addr(4'h9)
) fmlmeter (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_fmlmeter),
.fml_stb(fml_stb),
.fml_ack(fml_ack)
);
`else
assign csr_dr_fmlmeter = 32'd0;
`endif
//---------------------------------------------------------------------------
// USB
//---------------------------------------------------------------------------
wire usb_clk_dcm;
wire usb_clk;
DCM_PS #(
.CLKDV_DIVIDE(2.0), // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
.CLKFX_DIVIDE(25), // 1 to 32
.CLKFX_MULTIPLY(12), // 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(`CLOCK_PERIOD),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hF0F0),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) clkgen_usb (
.CLK0(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKDV(),
.CLKFX(usb_clk_dcm),
.CLKFX180(),
.LOCKED(),
.CLKFB(),
.CLKIN(sys_clk),
.RST(1'b0)
);
BUFG usb_b_p(
.I(usb_clk_dcm),
.O(usb_clk)
);
softusb #(
.csr_addr(4'hf)
) usb (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.usb_clk(usb_clk),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_dw),
.csr_do(csr_dr_usb),
.irq(usb_irq),
.wb_adr_i(usb_adr),
.wb_dat_o(usb_dat_r),
.wb_dat_i(usb_dat_w),
.wb_sel_i(usb_sel),
.wb_stb_i(usb_stb),
.wb_cyc_i(usb_cyc),
.wb_ack_o(usb_ack),
.wb_we_i(usb_we),
.usba_spd(),
.usba_oe_n(),
.usba_rcv(usba_vp),
.usba_vp(usba_vp),
.usba_vm(usba_vm),
.usbb_spd(),
.usbb_oe_n(),
.usbb_rcv(usbb_vp),
.usbb_vp(usbb_vp),
.usbb_vm(usbb_vm)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A221O_FUNCTIONAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a221o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221O_FUNCTIONAL_V |
// This is a modified version of the primitive.v of the verilog to routing project:
https://github.com/verilog-to-routing/vtr-verilog-to-routing.
Therefore this file is under MIT License.
//Overivew
//========
//This file contains the verilog primitives produced by VPR's
//post-synthesis netlist writer.
//
//K-input Look-Up Table
module LUT_K #(
//The Look-up Table size (number of inputs)
parameter K = 6,
//The lut mask.
//Left-most (MSB) bit corresponds to all inputs logic one.
//Defaults to always false.
parameter LUT_MASK={2**K{1'b0}}
) (
input [K-1:0] in,
output out
);
assign out = LUT_MASK[in];
endmodule
//D-FlipFlop module
module DFF #(
parameter INITIAL_VALUE=1'b0
) (
input clock,
input D,
output reg Q
);
initial begin
Q <= INITIAL_VALUE;
end
always@(posedge clock) begin
Q <= D;
end
endmodule
//D-FlipFlop module
module DFF_RESET #(
parameter INITIAL_VALUE=1'b0
) (
input clock,
input D,
input reset,
output reg Q
);
initial begin
Q <= INITIAL_VALUE;
end
always@(posedge clock or posedge reset) begin
if (reset == 1'b1) begin
Q <= INITIAL_VALUE;
end else begin
Q <= D;
end
end
endmodule
//Routing fpga_interconnect module
module fpga_interconnect(
input datain,
output dataout
);
assign dataout = datain;
endmodule
//2-to-1 mux module
module mux(
input select,
input x,
input y,
output z
);
assign z = (x & ~select) | (y & select);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_2_V
`define SKY130_FD_SC_LP__MUX2I_2_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_2 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_2 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_2_V
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module design_1_processing_system7_0_1 (
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
SDIO0_WP,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB,
);
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input SDIO0_WP;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100),
.C_FCLK_CLK1_FREQ(175),
.C_FCLK_CLK2_FREQ(12),
.C_FCLK_CLK3_FREQ(100)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:31:51 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_system_ila_0_0_stub.v
// Design : zynq_design_1_system_ila_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "bd_c3fe,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, SLOT_0_AXI_awaddr, SLOT_0_AXI_awvalid,
SLOT_0_AXI_awready, SLOT_0_AXI_wdata, SLOT_0_AXI_wstrb, SLOT_0_AXI_wvalid,
SLOT_0_AXI_wready, SLOT_0_AXI_bresp, SLOT_0_AXI_bvalid, SLOT_0_AXI_bready,
SLOT_0_AXI_araddr, SLOT_0_AXI_arvalid, SLOT_0_AXI_arready, SLOT_0_AXI_rdata,
SLOT_0_AXI_rresp, SLOT_0_AXI_rvalid, SLOT_0_AXI_rready, resetn)
/* synthesis syn_black_box black_box_pad_pin="clk,SLOT_0_AXI_awaddr[8:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[8:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,resetn" */;
input clk;
input [8:0]SLOT_0_AXI_awaddr;
input SLOT_0_AXI_awvalid;
input SLOT_0_AXI_awready;
input [31:0]SLOT_0_AXI_wdata;
input [3:0]SLOT_0_AXI_wstrb;
input SLOT_0_AXI_wvalid;
input SLOT_0_AXI_wready;
input [1:0]SLOT_0_AXI_bresp;
input SLOT_0_AXI_bvalid;
input SLOT_0_AXI_bready;
input [8:0]SLOT_0_AXI_araddr;
input SLOT_0_AXI_arvalid;
input SLOT_0_AXI_arready;
input [31:0]SLOT_0_AXI_rdata;
input [1:0]SLOT_0_AXI_rresp;
input SLOT_0_AXI_rvalid;
input SLOT_0_AXI_rready;
input resetn;
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//name : user_design
//input : input_speed:16
//input : input_socket:16
//input : input_rs232_rx:16
//output : output_rs232_tx:16
//output : output_leds:16
//output : output_socket:16
//source_file : user_design.c
///===========
///
///Created by C2CHIP
//////////////////////////////////////////////////////////////////////////////
// Register Allocation
// ===================
// Register Name Size
// 0 HTTP_OK return address 2
// 1 array 2
// 2 variable header_length 2
// 3 variable body_length 2
// 4 variable length 2
// 5 variable index 2
// 6 variable packet_count 2
// 7 array 2
// 8 array 2
// 9 find return address 2
// 10 variable find return value 2
// 11 array 2
// 12 variable search 2
// 13 variable start 2
// 14 variable end 2
// 15 variable value 2
// 16 array 2
// 17 array 2
// 18 user_design return address 2
// 19 variable length 2
// 20 variable i 2
// 21 variable index 2
// 22 array 2
// 23 variable word 2
// 24 variable speed 2
// 25 variable leds 2
// 26 variable start 2
// 27 variable end 2
// 28 array 2
// 29 array 2
// 30 array 2
// 31 temporary_register 2
// 32 temporary_register 2
// 33 temporary_register 2
// 34 temporary_register 4
// 35 temporary_register 2
// 36 temporary_register 252
// 37 temporary_register 228
// 38 temporary_register 10
// 39 temporary_register 80
// 40 temporary_register 82
// 41 temporary_register 2
// 42 temporary_register 2920
// 43 temporary_register 1464
// 44 put_socket return address 2
// 45 variable i 2
// 46 stdout_put_char return address 2
// 47 variable i 2
// 48 print_string return address 2
// 49 array 2
// 50 variable i 2
// 51 print_udecimal return address 2
// 52 variable udecimal 2
// 53 variable digit 2
// 54 variable significant 2
// 55 print_decimal return address 2
// 56 variable decimal 2
// 57 variable socket_high 2
// 58 variable socket_data 2
// 59 socket_put_char return address 2
// 60 variable x 2
// 61 socket_flush return address 2
// 62 socket_put_string return address 2
// 63 array 2
// 64 variable i 2
// 65 socket_put_decimal return address 2
// 66 variable value 2
// 67 variable digit_0 2
// 68 variable digit_1 2
// 69 variable digit_2 2
// 70 variable digit_3 2
// 71 variable digit_4 2
// 72 variable significant 2
// 73 HTTP_Not_Found return address 2
// 74 variable header_length 2
// 75 array 2
module user_design(input_speed,input_socket,input_rs232_rx,input_speed_stb,input_socket_stb,input_rs232_rx_stb,output_rs232_tx_ack,output_leds_ack,output_socket_ack,clk,rst,output_rs232_tx,output_leds,output_socket,output_rs232_tx_stb,output_leds_stb,output_socket_stb,input_speed_ack,input_socket_ack,input_rs232_rx_ack);
integer file_count;
real fp_value;
input [15:0] input_speed;
input [15:0] input_socket;
input [15:0] input_rs232_rx;
input input_speed_stb;
input input_socket_stb;
input input_rs232_rx_stb;
input output_rs232_tx_ack;
input output_leds_ack;
input output_socket_ack;
input clk;
input rst;
output [15:0] output_rs232_tx;
output [15:0] output_leds;
output [15:0] output_socket;
output output_rs232_tx_stb;
output output_leds_stb;
output output_socket_stb;
output input_speed_ack;
output input_socket_ack;
output input_rs232_rx_ack;
reg [15:0] timer;
reg timer_enable;
reg stage_0_enable;
reg stage_1_enable;
reg stage_2_enable;
reg [10:0] program_counter;
reg [10:0] program_counter_0;
reg [51:0] instruction_0;
reg [5:0] opcode_0;
reg [6:0] dest_0;
reg [6:0] src_0;
reg [6:0] srcb_0;
reg [31:0] literal_0;
reg [10:0] program_counter_1;
reg [5:0] opcode_1;
reg [6:0] dest_1;
reg [31:0] register_1;
reg [31:0] registerb_1;
reg [31:0] literal_1;
reg [6:0] dest_2;
reg [31:0] result_2;
reg write_enable_2;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg memory_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg memory_enable_4;
reg [15:0] s_output_rs232_tx_stb;
reg [15:0] s_output_leds_stb;
reg [15:0] s_output_socket_stb;
reg [15:0] s_output_rs232_tx;
reg [15:0] s_output_leds;
reg [15:0] s_output_socket;
reg [15:0] s_input_speed_ack;
reg [15:0] s_input_socket_ack;
reg [15:0] s_input_rs232_rx_ack;
reg [15:0] memory_2 [2529:0];
reg [51:0] instructions [1422:0];
reg [31:0] registers [75:0];
//////////////////////////////////////////////////////////////////////////////
// MEMORY INITIALIZATION
//
// In order to reduce program size, array contents have been stored into
// memory at initialization. In an FPGA, this will result in the memory being
// initialized when the FPGA configures.
// Memory will not be re-initialized at reset.
// Dissable this behaviour using the no_initialize_memory switch
initial
begin
memory_2[2048] = 105;
memory_2[2049] = 110;
memory_2[2050] = 112;
memory_2[2051] = 117;
memory_2[4] = 72;
memory_2[5] = 84;
memory_2[6] = 84;
memory_2[7] = 80;
memory_2[8] = 47;
memory_2[9] = 49;
memory_2[10] = 46;
memory_2[11] = 49;
memory_2[12] = 32;
memory_2[13] = 52;
memory_2[14] = 48;
memory_2[15] = 52;
memory_2[16] = 32;
memory_2[17] = 78;
memory_2[18] = 111;
memory_2[19] = 116;
memory_2[20] = 32;
memory_2[21] = 70;
memory_2[22] = 111;
memory_2[23] = 117;
memory_2[24] = 110;
memory_2[25] = 100;
memory_2[26] = 13;
memory_2[27] = 10;
memory_2[28] = 68;
memory_2[29] = 97;
memory_2[30] = 116;
memory_2[31] = 101;
memory_2[32] = 58;
memory_2[33] = 32;
memory_2[34] = 84;
memory_2[35] = 104;
memory_2[36] = 117;
memory_2[37] = 32;
memory_2[38] = 79;
memory_2[39] = 99;
memory_2[40] = 116;
memory_2[41] = 32;
memory_2[42] = 51;
memory_2[43] = 49;
memory_2[44] = 32;
memory_2[45] = 49;
memory_2[46] = 57;
memory_2[47] = 58;
memory_2[48] = 49;
memory_2[49] = 54;
memory_2[50] = 58;
memory_2[51] = 48;
memory_2[52] = 48;
memory_2[53] = 32;
memory_2[54] = 50;
memory_2[55] = 48;
memory_2[56] = 49;
memory_2[57] = 51;
memory_2[58] = 13;
memory_2[59] = 10;
memory_2[60] = 83;
memory_2[61] = 101;
memory_2[62] = 114;
memory_2[63] = 118;
memory_2[64] = 101;
memory_2[65] = 114;
memory_2[66] = 58;
memory_2[67] = 32;
memory_2[68] = 99;
memory_2[69] = 104;
memory_2[70] = 105;
memory_2[71] = 112;
memory_2[72] = 115;
memory_2[73] = 45;
memory_2[74] = 119;
memory_2[75] = 101;
memory_2[76] = 98;
memory_2[77] = 47;
memory_2[78] = 48;
memory_2[79] = 46;
memory_2[80] = 48;
memory_2[81] = 13;
memory_2[82] = 10;
memory_2[83] = 67;
memory_2[84] = 111;
memory_2[85] = 110;
memory_2[86] = 116;
memory_2[87] = 101;
memory_2[88] = 110;
memory_2[89] = 116;
memory_2[90] = 45;
memory_2[91] = 84;
memory_2[92] = 121;
memory_2[93] = 112;
memory_2[94] = 101;
memory_2[95] = 58;
memory_2[96] = 32;
memory_2[97] = 116;
memory_2[98] = 101;
memory_2[99] = 120;
memory_2[100] = 116;
memory_2[101] = 47;
memory_2[102] = 104;
memory_2[103] = 116;
memory_2[104] = 109;
memory_2[105] = 108;
memory_2[106] = 13;
memory_2[107] = 10;
memory_2[108] = 67;
memory_2[109] = 111;
memory_2[110] = 110;
memory_2[111] = 116;
memory_2[112] = 101;
memory_2[113] = 110;
memory_2[114] = 116;
memory_2[115] = 45;
memory_2[116] = 76;
memory_2[117] = 101;
memory_2[118] = 110;
memory_2[119] = 103;
memory_2[120] = 116;
memory_2[121] = 104;
memory_2[122] = 58;
memory_2[123] = 32;
memory_2[124] = 48;
memory_2[125] = 13;
memory_2[126] = 10;
memory_2[127] = 13;
memory_2[128] = 10;
memory_2[129] = 0;
memory_2[2178] = 34;
memory_2[2179] = 115;
memory_2[132] = 72;
memory_2[133] = 84;
memory_2[134] = 84;
memory_2[135] = 80;
memory_2[136] = 47;
memory_2[137] = 49;
memory_2[138] = 46;
memory_2[139] = 49;
memory_2[140] = 32;
memory_2[141] = 50;
memory_2[142] = 48;
memory_2[143] = 48;
memory_2[144] = 32;
memory_2[145] = 79;
memory_2[146] = 75;
memory_2[147] = 13;
memory_2[148] = 10;
memory_2[149] = 68;
memory_2[150] = 97;
memory_2[151] = 116;
memory_2[152] = 101;
memory_2[153] = 58;
memory_2[154] = 32;
memory_2[155] = 84;
memory_2[156] = 104;
memory_2[157] = 117;
memory_2[158] = 32;
memory_2[159] = 79;
memory_2[160] = 99;
memory_2[161] = 116;
memory_2[162] = 32;
memory_2[163] = 51;
memory_2[164] = 49;
memory_2[165] = 32;
memory_2[166] = 49;
memory_2[167] = 57;
memory_2[168] = 58;
memory_2[169] = 49;
memory_2[170] = 54;
memory_2[171] = 58;
memory_2[172] = 48;
memory_2[173] = 48;
memory_2[174] = 32;
memory_2[175] = 50;
memory_2[176] = 48;
memory_2[177] = 49;
memory_2[178] = 51;
memory_2[179] = 13;
memory_2[180] = 10;
memory_2[181] = 83;
memory_2[182] = 101;
memory_2[183] = 114;
memory_2[184] = 118;
memory_2[185] = 101;
memory_2[186] = 114;
memory_2[187] = 58;
memory_2[188] = 32;
memory_2[189] = 99;
memory_2[190] = 104;
memory_2[191] = 105;
memory_2[192] = 112;
memory_2[193] = 115;
memory_2[194] = 45;
memory_2[195] = 119;
memory_2[196] = 101;
memory_2[197] = 98;
memory_2[198] = 47;
memory_2[199] = 48;
memory_2[200] = 46;
memory_2[201] = 48;
memory_2[202] = 13;
memory_2[203] = 10;
memory_2[204] = 67;
memory_2[205] = 111;
memory_2[206] = 110;
memory_2[207] = 116;
memory_2[208] = 101;
memory_2[209] = 110;
memory_2[210] = 116;
memory_2[211] = 45;
memory_2[212] = 84;
memory_2[213] = 121;
memory_2[214] = 112;
memory_2[215] = 101;
memory_2[216] = 58;
memory_2[217] = 32;
memory_2[218] = 116;
memory_2[219] = 101;
memory_2[220] = 120;
memory_2[221] = 116;
memory_2[222] = 47;
memory_2[223] = 104;
memory_2[224] = 116;
memory_2[225] = 109;
memory_2[226] = 108;
memory_2[227] = 13;
memory_2[228] = 10;
memory_2[229] = 67;
memory_2[230] = 111;
memory_2[231] = 110;
memory_2[232] = 116;
memory_2[233] = 101;
memory_2[234] = 110;
memory_2[235] = 116;
memory_2[236] = 45;
memory_2[237] = 76;
memory_2[238] = 101;
memory_2[239] = 110;
memory_2[240] = 103;
memory_2[241] = 116;
memory_2[242] = 104;
memory_2[243] = 58;
memory_2[244] = 32;
memory_2[245] = 0;
memory_2[246] = 13;
memory_2[247] = 10;
memory_2[248] = 13;
memory_2[249] = 10;
memory_2[250] = 0;
memory_2[2299] = 115;
memory_2[2300] = 32;
memory_2[253] = 10;
memory_2[254] = 0;
memory_2[255] = 10;
memory_2[256] = 0;
memory_2[2305] = 114;
memory_2[2306] = 101;
memory_2[2091] = 62;
memory_2[2308] = 32;
memory_2[2309] = 98;
memory_2[2310] = 121;
memory_2[2311] = 32;
memory_2[2312] = 60;
memory_2[2092] = 108;
memory_2[2314] = 32;
memory_2[2315] = 104;
memory_2[2316] = 114;
memory_2[2317] = 101;
memory_2[2318] = 102;
memory_2[2093] = 101;
memory_2[2320] = 34;
memory_2[2321] = 104;
memory_2[2322] = 116;
memory_2[2323] = 116;
memory_2[2324] = 112;
memory_2[2094] = 100;
memory_2[2326] = 47;
memory_2[2327] = 47;
memory_2[2055] = 121;
memory_2[2329] = 121;
memory_2[2330] = 97;
memory_2[2095] = 32;
memory_2[2332] = 100;
memory_2[2333] = 99;
memory_2[2334] = 104;
memory_2[2335] = 105;
memory_2[2336] = 112;
memory_2[2096] = 50;
memory_2[2338] = 46;
memory_2[2339] = 111;
memory_2[2340] = 114;
memory_2[2341] = 103;
memory_2[2342] = 34;
memory_2[2097] = 60;
memory_2[2344] = 67;
memory_2[2345] = 104;
memory_2[2346] = 105;
memory_2[2347] = 112;
memory_2[2348] = 115;
memory_2[2098] = 47;
memory_2[2350] = 50;
memory_2[2351] = 46;
memory_2[2352] = 48;
memory_2[2353] = 60;
memory_2[2354] = 47;
memory_2[2099] = 105;
memory_2[2356] = 62;
memory_2[2357] = 32;
memory_2[2056] = 112;
memory_2[2359] = 110;
memory_2[2360] = 100;
memory_2[2100] = 110;
memory_2[2362] = 60;
memory_2[2363] = 97;
memory_2[2364] = 32;
memory_2[2365] = 104;
memory_2[2366] = 114;
memory_2[2101] = 112;
memory_2[2368] = 102;
memory_2[2369] = 61;
memory_2[2370] = 34;
memory_2[2371] = 104;
memory_2[2372] = 116;
memory_2[2102] = 117;
memory_2[2374] = 112;
memory_2[2375] = 115;
memory_2[2376] = 58;
memory_2[2377] = 47;
memory_2[2378] = 47;
memory_2[2103] = 116;
memory_2[2380] = 105;
memory_2[2381] = 116;
memory_2[2382] = 104;
memory_2[2383] = 117;
memory_2[2384] = 98;
memory_2[2104] = 62;
memory_2[2386] = 99;
memory_2[2387] = 111;
memory_2[2057] = 101;
memory_2[2389] = 47;
memory_2[2390] = 112;
memory_2[2105] = 9;
memory_2[2392] = 101;
memory_2[2393] = 114;
memory_2[2394] = 108;
memory_2[2395] = 105;
memory_2[2396] = 110;
memory_2[2106] = 60;
memory_2[2398] = 47;
memory_2[2399] = 101;
memory_2[2400] = 116;
memory_2[2401] = 104;
memory_2[2402] = 101;
memory_2[2107] = 105;
memory_2[2404] = 110;
memory_2[2405] = 101;
memory_2[2406] = 116;
memory_2[2407] = 95;
memory_2[2408] = 109;
memory_2[2108] = 110;
memory_2[2410] = 99;
memory_2[2411] = 34;
memory_2[2412] = 62;
memory_2[2413] = 101;
memory_2[2414] = 116;
memory_2[2109] = 112;
memory_2[2416] = 101;
memory_2[2417] = 114;
memory_2[2058] = 61;
memory_2[2419] = 101;
memory_2[2420] = 116;
memory_2[2110] = 117;
memory_2[2422] = 109;
memory_2[2423] = 97;
memory_2[2424] = 99;
memory_2[2425] = 60;
memory_2[2426] = 47;
memory_2[2111] = 116;
memory_2[2428] = 62;
memory_2[2429] = 46;
memory_2[2430] = 60;
memory_2[2431] = 47;
memory_2[2432] = 112;
memory_2[2112] = 32;
memory_2[2434] = 60;
memory_2[2435] = 47;
memory_2[2436] = 98;
memory_2[2437] = 111;
memory_2[2438] = 100;
memory_2[2113] = 116;
memory_2[2440] = 62;
memory_2[2441] = 60;
memory_2[2442] = 47;
memory_2[2443] = 104;
memory_2[2444] = 116;
memory_2[2114] = 121;
memory_2[2446] = 108;
memory_2[2447] = 62;
memory_2[2059] = 34;
memory_2[2449] = 87;
memory_2[2450] = 101;
memory_2[2115] = 112;
memory_2[2452] = 99;
memory_2[2453] = 111;
memory_2[2454] = 109;
memory_2[2455] = 101;
memory_2[2456] = 32;
memory_2[2116] = 101;
memory_2[2379] = 103;
memory_2[2459] = 32;
memory_2[2460] = 116;
memory_2[2458] = 111;
memory_2[2462] = 101;
memory_2[2117] = 61;
memory_2[2464] = 71;
memory_2[2465] = 105;
memory_2[2466] = 103;
memory_2[2467] = 97;
memory_2[2468] = 66;
memory_2[2118] = 34;
memory_2[2470] = 101;
memory_2[2471] = 32;
memory_2[2472] = 67;
memory_2[2473] = 104;
memory_2[2474] = 105;
memory_2[2119] = 99;
memory_2[2476] = 115;
memory_2[2477] = 45;
memory_2[2060] = 99;
memory_2[2461] = 104;
memory_2[2480] = 48;
memory_2[2120] = 104;
memory_2[2482] = 100;
memory_2[2483] = 101;
memory_2[2484] = 109;
memory_2[2485] = 111;
memory_2[2486] = 33;
memory_2[2121] = 101;
memory_2[2488] = 0;
memory_2[2489] = 67;
memory_2[2490] = 111;
memory_2[2463] = 32;
memory_2[2492] = 110;
memory_2[2122] = 99;
memory_2[2494] = 99;
memory_2[2495] = 116;
memory_2[2496] = 32;
memory_2[2497] = 121;
memory_2[2498] = 111;
memory_2[2123] = 107;
memory_2[2500] = 114;
memory_2[2501] = 32;
memory_2[2502] = 119;
memory_2[2503] = 101;
memory_2[2504] = 98;
memory_2[2124] = 98;
memory_2[2506] = 98;
memory_2[2507] = 114;
memory_2[2061] = 104;
memory_2[2509] = 119;
memory_2[2510] = 115;
memory_2[2125] = 111;
memory_2[2512] = 114;
memory_2[2513] = 32;
memory_2[2514] = 116;
memory_2[2515] = 111;
memory_2[2516] = 32;
memory_2[2126] = 120;
memory_2[2518] = 57;
memory_2[2519] = 50;
memory_2[2520] = 46;
memory_2[2521] = 49;
memory_2[2522] = 54;
memory_2[2127] = 34;
memory_2[2524] = 46;
memory_2[2525] = 49;
memory_2[2526] = 46;
memory_2[2469] = 101;
memory_2[2528] = 10;
memory_2[2128] = 32;
memory_2[2129] = 110;
memory_2[2062] = 101;
memory_2[2403] = 114;
memory_2[2130] = 97;
memory_2[2131] = 109;
memory_2[2132] = 101;
memory_2[2133] = 61;
memory_2[2475] = 112;
memory_2[2134] = 34;
memory_2[2063] = 99;
memory_2[2135] = 108;
memory_2[2136] = 101;
memory_2[2478] = 50;
memory_2[2137] = 100;
memory_2[2479] = 46;
memory_2[2138] = 52;
memory_2[2139] = 34;
memory_2[2064] = 107;
memory_2[2481] = 32;
memory_2[2140] = 32;
memory_2[2337] = 115;
memory_2[2141] = 118;
memory_2[2142] = 97;
memory_2[2143] = 108;
memory_2[2144] = 117;
memory_2[2065] = 98;
memory_2[2145] = 101;
memory_2[2487] = 10;
memory_2[2146] = 61;
memory_2[2147] = 34;
memory_2[2148] = 68;
memory_2[2149] = 34;
memory_2[2066] = 111;
memory_2[2491] = 110;
memory_2[2150] = 62;
memory_2[2151] = 108;
memory_2[2493] = 101;
memory_2[2152] = 101;
memory_2[2153] = 100;
memory_2[2154] = 32;
memory_2[2067] = 120;
memory_2[2155] = 51;
memory_2[2156] = 60;
memory_2[2391] = 107;
memory_2[2157] = 47;
memory_2[2499] = 117;
memory_2[2158] = 105;
memory_2[2159] = 110;
memory_2[2068] = 34;
memory_2[2409] = 97;
memory_2[2160] = 112;
memory_2[2161] = 117;
memory_2[2162] = 116;
memory_2[2163] = 62;
memory_2[2505] = 32;
memory_2[2164] = 9;
memory_2[2069] = 32;
memory_2[2165] = 60;
memory_2[2166] = 98;
memory_2[2508] = 111;
memory_2[2167] = 117;
memory_2[2168] = 116;
memory_2[2169] = 116;
memory_2[2070] = 110;
memory_2[2511] = 101;
memory_2[2170] = 111;
memory_2[2343] = 62;
memory_2[2171] = 110;
memory_2[2172] = 32;
memory_2[2173] = 116;
memory_2[2174] = 121;
memory_2[2071] = 97;
memory_2[2175] = 112;
memory_2[2517] = 49;
memory_2[2176] = 101;
memory_2[2177] = 61;
memory_2[2072] = 109;
memory_2[2180] = 117;
memory_2[2181] = 98;
memory_2[2523] = 56;
memory_2[2182] = 109;
memory_2[2445] = 109;
memory_2[2183] = 105;
memory_2[2385] = 46;
memory_2[2184] = 116;
memory_2[2073] = 101;
memory_2[2185] = 34;
memory_2[2527] = 49;
memory_2[2186] = 32;
memory_2[2187] = 118;
memory_2[2529] = 0;
memory_2[2188] = 97;
memory_2[2189] = 108;
memory_2[2074] = 61;
memory_2[2415] = 104;
memory_2[2190] = 117;
memory_2[2191] = 101;
memory_2[2192] = 61;
memory_2[2193] = 34;
memory_2[2194] = 83;
memory_2[2075] = 34;
memory_2[2195] = 117;
memory_2[2196] = 98;
memory_2[2197] = 109;
memory_2[2198] = 105;
memory_2[2199] = 116;
memory_2[2076] = 108;
memory_2[2200] = 34;
memory_2[2349] = 45;
memory_2[2201] = 62;
memory_2[2202] = 85;
memory_2[2203] = 112;
memory_2[2204] = 100;
memory_2[2077] = 101;
memory_2[2418] = 110;
memory_2[2205] = 97;
memory_2[2206] = 116;
memory_2[2052] = 116;
memory_2[2207] = 101;
memory_2[2208] = 32;
memory_2[2209] = 76;
memory_2[2078] = 100;
memory_2[2210] = 69;
memory_2[2211] = 68;
memory_2[2212] = 115;
memory_2[2213] = 60;
memory_2[2214] = 47;
memory_2[2079] = 51;
memory_2[2215] = 98;
memory_2[2216] = 117;
memory_2[2448] = 0;
memory_2[2217] = 116;
memory_2[2388] = 109;
memory_2[2218] = 116;
memory_2[2219] = 111;
memory_2[2080] = 34;
memory_2[2220] = 110;
memory_2[2221] = 62;
memory_2[2222] = 60;
memory_2[2223] = 47;
memory_2[2224] = 102;
memory_2[2081] = 32;
memory_2[2421] = 95;
memory_2[2225] = 111;
memory_2[2226] = 114;
memory_2[2227] = 109;
memory_2[2228] = 62;
memory_2[2229] = 60;
memory_2[2082] = 118;
memory_2[2230] = 112;
memory_2[2355] = 97;
memory_2[2231] = 62;
memory_2[2053] = 32;
memory_2[2232] = 84;
memory_2[2233] = 104;
memory_2[2234] = 105;
memory_2[2083] = 97;
memory_2[2235] = 115;
memory_2[2236] = 32;
memory_2[2237] = 60;
memory_2[2238] = 97;
memory_2[2239] = 32;
memory_2[2084] = 108;
memory_2[2240] = 104;
memory_2[2241] = 114;
memory_2[2242] = 101;
memory_2[2243] = 102;
memory_2[2244] = 61;
memory_2[2085] = 117;
memory_2[2245] = 34;
memory_2[2358] = 97;
memory_2[2246] = 104;
memory_2[2247] = 116;
memory_2[2248] = 116;
memory_2[2249] = 112;
memory_2[2086] = 101;
memory_2[2451] = 108;
memory_2[2250] = 115;
memory_2[2251] = 58;
memory_2[2252] = 47;
memory_2[2253] = 47;
memory_2[2254] = 103;
memory_2[2087] = 61;
memory_2[2255] = 105;
memory_2[2256] = 116;
memory_2[2054] = 116;
memory_2[2257] = 104;
memory_2[2258] = 117;
memory_2[2259] = 98;
memory_2[2088] = 34;
memory_2[2260] = 46;
memory_2[2361] = 32;
memory_2[2261] = 99;
memory_2[2262] = 111;
memory_2[2263] = 109;
memory_2[2264] = 47;
memory_2[2089] = 67;
memory_2[2265] = 112;
memory_2[2266] = 107;
memory_2[2267] = 101;
memory_2[2268] = 114;
memory_2[2269] = 108;
memory_2[2090] = 34;
memory_2[2270] = 105;
memory_2[2271] = 110;
memory_2[2272] = 103;
memory_2[2273] = 47;
memory_2[2274] = 67;
memory_2[2275] = 104;
memory_2[2276] = 105;
memory_2[2277] = 112;
memory_2[2278] = 115;
memory_2[2279] = 45;
memory_2[2433] = 62;
memory_2[2280] = 68;
memory_2[2281] = 101;
memory_2[2282] = 109;
memory_2[2283] = 111;
memory_2[2284] = 34;
memory_2[2285] = 62;
memory_2[2286] = 112;
memory_2[2287] = 114;
memory_2[2288] = 111;
memory_2[2289] = 106;
memory_2[2290] = 101;
memory_2[2367] = 101;
memory_2[2291] = 99;
memory_2[2292] = 116;
memory_2[2293] = 60;
memory_2[2294] = 47;
memory_2[2295] = 97;
memory_2[2296] = 62;
memory_2[2297] = 32;
memory_2[2298] = 105;
memory_2[2301] = 112;
memory_2[2302] = 111;
memory_2[2303] = 119;
memory_2[2304] = 101;
memory_2[2397] = 103;
memory_2[2307] = 100;
memory_2[2439] = 121;
memory_2[2313] = 97;
memory_2[2457] = 116;
memory_2[2427] = 97;
memory_2[2319] = 61;
memory_2[2373] = 116;
memory_2[2325] = 58;
memory_2[2328] = 112;
memory_2[2331] = 110;
memory_2[1717] = 60;
memory_2[1718] = 104;
memory_2[1719] = 116;
memory_2[1720] = 109;
memory_2[1721] = 108;
memory_2[1722] = 62;
memory_2[1723] = 60;
memory_2[1724] = 104;
memory_2[1725] = 101;
memory_2[1726] = 97;
memory_2[1727] = 100;
memory_2[1728] = 62;
memory_2[1729] = 60;
memory_2[1730] = 116;
memory_2[1731] = 105;
memory_2[1732] = 116;
memory_2[1733] = 108;
memory_2[1734] = 101;
memory_2[1735] = 62;
memory_2[1736] = 101;
memory_2[1737] = 116;
memory_2[1738] = 104;
memory_2[1739] = 101;
memory_2[1740] = 114;
memory_2[1741] = 110;
memory_2[1742] = 101;
memory_2[1743] = 116;
memory_2[1744] = 95;
memory_2[1745] = 109;
memory_2[1746] = 97;
memory_2[1747] = 99;
memory_2[1748] = 32;
memory_2[1749] = 67;
memory_2[1750] = 104;
memory_2[1751] = 105;
memory_2[1752] = 112;
memory_2[1753] = 115;
memory_2[1754] = 45;
memory_2[1755] = 50;
memory_2[1756] = 46;
memory_2[1757] = 48;
memory_2[1758] = 32;
memory_2[1759] = 71;
memory_2[1760] = 105;
memory_2[1761] = 103;
memory_2[1762] = 97;
memory_2[1763] = 66;
memory_2[1764] = 101;
memory_2[1765] = 101;
memory_2[1766] = 32;
memory_2[1767] = 68;
memory_2[1768] = 101;
memory_2[1769] = 109;
memory_2[1770] = 111;
memory_2[1771] = 60;
memory_2[1772] = 47;
memory_2[1773] = 116;
memory_2[1774] = 105;
memory_2[1775] = 116;
memory_2[1776] = 108;
memory_2[1777] = 101;
memory_2[1778] = 62;
memory_2[1779] = 60;
memory_2[1780] = 47;
memory_2[1781] = 104;
memory_2[1782] = 101;
memory_2[1783] = 97;
memory_2[1784] = 100;
memory_2[1785] = 62;
memory_2[1786] = 60;
memory_2[1787] = 98;
memory_2[1788] = 111;
memory_2[1789] = 100;
memory_2[1790] = 121;
memory_2[1791] = 62;
memory_2[1792] = 60;
memory_2[1793] = 104;
memory_2[1794] = 49;
memory_2[1795] = 62;
memory_2[1796] = 101;
memory_2[1797] = 116;
memory_2[1798] = 104;
memory_2[1799] = 101;
memory_2[1800] = 114;
memory_2[1801] = 110;
memory_2[1802] = 101;
memory_2[1803] = 116;
memory_2[1804] = 95;
memory_2[1805] = 109;
memory_2[1806] = 97;
memory_2[1807] = 99;
memory_2[1808] = 32;
memory_2[1809] = 67;
memory_2[1810] = 104;
memory_2[1811] = 105;
memory_2[1812] = 112;
memory_2[1813] = 115;
memory_2[1814] = 45;
memory_2[1815] = 50;
memory_2[1816] = 46;
memory_2[1817] = 48;
memory_2[1818] = 32;
memory_2[1819] = 71;
memory_2[1820] = 105;
memory_2[1821] = 103;
memory_2[1822] = 97;
memory_2[1823] = 66;
memory_2[1824] = 101;
memory_2[1825] = 101;
memory_2[1826] = 32;
memory_2[1827] = 68;
memory_2[1828] = 101;
memory_2[1829] = 109;
memory_2[1830] = 111;
memory_2[1831] = 60;
memory_2[1832] = 47;
memory_2[1833] = 104;
memory_2[1834] = 49;
memory_2[1835] = 62;
memory_2[1836] = 60;
memory_2[1837] = 112;
memory_2[1838] = 62;
memory_2[1839] = 87;
memory_2[1840] = 101;
memory_2[1841] = 108;
memory_2[1842] = 99;
memory_2[1843] = 111;
memory_2[1844] = 109;
memory_2[1845] = 101;
memory_2[1846] = 32;
memory_2[1847] = 116;
memory_2[1848] = 111;
memory_2[1849] = 32;
memory_2[1850] = 116;
memory_2[1851] = 104;
memory_2[1852] = 101;
memory_2[1853] = 32;
memory_2[1854] = 101;
memory_2[1855] = 116;
memory_2[1856] = 104;
memory_2[1857] = 101;
memory_2[1858] = 114;
memory_2[1859] = 110;
memory_2[1860] = 101;
memory_2[1861] = 116;
memory_2[1862] = 95;
memory_2[1863] = 109;
memory_2[1864] = 97;
memory_2[1865] = 99;
memory_2[1866] = 32;
memory_2[1867] = 67;
memory_2[1868] = 104;
memory_2[1869] = 105;
memory_2[1870] = 112;
memory_2[1871] = 115;
memory_2[1872] = 45;
memory_2[1873] = 50;
memory_2[1874] = 46;
memory_2[1875] = 48;
memory_2[1876] = 32;
memory_2[1877] = 71;
memory_2[1878] = 105;
memory_2[1879] = 103;
memory_2[1880] = 97;
memory_2[1881] = 66;
memory_2[1882] = 101;
memory_2[1883] = 101;
memory_2[1884] = 32;
memory_2[1885] = 68;
memory_2[1886] = 101;
memory_2[1887] = 109;
memory_2[1888] = 111;
memory_2[1889] = 33;
memory_2[1890] = 60;
memory_2[1891] = 47;
memory_2[1892] = 112;
memory_2[1893] = 62;
memory_2[1894] = 60;
memory_2[1895] = 112;
memory_2[1896] = 62;
memory_2[1897] = 76;
memory_2[1898] = 105;
memory_2[1899] = 110;
memory_2[1900] = 107;
memory_2[1901] = 32;
memory_2[1902] = 115;
memory_2[1903] = 112;
memory_2[1904] = 101;
memory_2[1905] = 101;
memory_2[1906] = 100;
memory_2[1907] = 58;
memory_2[1908] = 32;
memory_2[1909] = 49;
memory_2[1910] = 48;
memory_2[1911] = 48;
memory_2[1912] = 48;
memory_2[1913] = 32;
memory_2[1914] = 77;
memory_2[1915] = 98;
memory_2[1916] = 47;
memory_2[1917] = 115;
memory_2[1918] = 60;
memory_2[1919] = 47;
memory_2[1920] = 112;
memory_2[1921] = 62;
memory_2[1922] = 60;
memory_2[1923] = 102;
memory_2[1924] = 111;
memory_2[1925] = 114;
memory_2[1926] = 109;
memory_2[1927] = 62;
memory_2[1928] = 9;
memory_2[1929] = 60;
memory_2[1930] = 105;
memory_2[1931] = 110;
memory_2[1932] = 112;
memory_2[1933] = 117;
memory_2[1934] = 116;
memory_2[1935] = 32;
memory_2[1936] = 116;
memory_2[1937] = 121;
memory_2[1938] = 112;
memory_2[1939] = 101;
memory_2[1940] = 61;
memory_2[1941] = 34;
memory_2[1942] = 99;
memory_2[1943] = 104;
memory_2[1944] = 101;
memory_2[1945] = 99;
memory_2[1946] = 107;
memory_2[1947] = 98;
memory_2[1948] = 111;
memory_2[1949] = 120;
memory_2[1950] = 34;
memory_2[1951] = 32;
memory_2[1952] = 110;
memory_2[1953] = 97;
memory_2[1954] = 109;
memory_2[1955] = 101;
memory_2[1956] = 61;
memory_2[1957] = 34;
memory_2[1958] = 108;
memory_2[1959] = 101;
memory_2[1960] = 100;
memory_2[1961] = 49;
memory_2[1962] = 34;
memory_2[1963] = 32;
memory_2[1964] = 118;
memory_2[1965] = 97;
memory_2[1966] = 108;
memory_2[1967] = 117;
memory_2[1968] = 101;
memory_2[1969] = 61;
memory_2[1970] = 34;
memory_2[1971] = 65;
memory_2[1972] = 34;
memory_2[1973] = 62;
memory_2[1974] = 108;
memory_2[1975] = 101;
memory_2[1976] = 100;
memory_2[1977] = 32;
memory_2[1978] = 48;
memory_2[1979] = 60;
memory_2[1980] = 47;
memory_2[1981] = 105;
memory_2[1982] = 110;
memory_2[1983] = 112;
memory_2[1984] = 117;
memory_2[1985] = 116;
memory_2[1986] = 62;
memory_2[1987] = 9;
memory_2[1988] = 60;
memory_2[1989] = 105;
memory_2[1990] = 110;
memory_2[1991] = 112;
memory_2[1992] = 117;
memory_2[1993] = 116;
memory_2[1994] = 32;
memory_2[1995] = 116;
memory_2[1996] = 121;
memory_2[1997] = 112;
memory_2[1998] = 101;
memory_2[1999] = 61;
memory_2[2000] = 34;
memory_2[2001] = 99;
memory_2[2002] = 104;
memory_2[2003] = 101;
memory_2[2004] = 99;
memory_2[2005] = 107;
memory_2[2006] = 98;
memory_2[2007] = 111;
memory_2[2008] = 120;
memory_2[2009] = 34;
memory_2[2010] = 32;
memory_2[2011] = 110;
memory_2[2012] = 97;
memory_2[2013] = 109;
memory_2[2014] = 101;
memory_2[2015] = 61;
memory_2[2016] = 34;
memory_2[2017] = 108;
memory_2[2018] = 101;
memory_2[2019] = 100;
memory_2[2020] = 50;
memory_2[2021] = 34;
memory_2[2022] = 32;
memory_2[2023] = 118;
memory_2[2024] = 97;
memory_2[2025] = 108;
memory_2[2026] = 117;
memory_2[2027] = 101;
memory_2[2028] = 61;
memory_2[2029] = 34;
memory_2[2030] = 66;
memory_2[2031] = 34;
memory_2[2032] = 62;
memory_2[2033] = 108;
memory_2[2034] = 101;
memory_2[2035] = 100;
memory_2[2036] = 32;
memory_2[2037] = 49;
memory_2[2038] = 60;
memory_2[2039] = 47;
memory_2[2040] = 105;
memory_2[2041] = 110;
memory_2[2042] = 112;
memory_2[2043] = 117;
memory_2[2044] = 116;
memory_2[2045] = 62;
memory_2[2046] = 9;
memory_2[2047] = 60;
end
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'literal'}
// 1 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_and_link'}
// 2 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'stop'}
// 3 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'move'}
// 4 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'nop'}
// 5 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'socket', 'op': 'write'}
// 6 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'jmp_to_reg'}
// 7 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'rs232_tx', 'op': 'write'}
// 8 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '+'}
// 9 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_request'}
// 10 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_wait'}
// 11 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read'}
// 12 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_false'}
// 13 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '+'}
// 14 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'goto'}
// 15 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>='}
// 16 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '-'}
// 17 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '|'}
// 18 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '|'}
// 19 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '>='}
// 20 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': '-'}
// 21 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '<<'}
// 22 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '&'}
// 23 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '=='}
// 24 {'float': False, 'literal': True, 'right': False, 'unsigned': True, 'op': '|'}
// 25 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>'}
// 26 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<'}
// 27 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<'}
// 28 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '=='}
// 29 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '+'}
// 30 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'read'}
// 31 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>>'}
// 32 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '&'}
// 33 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_write'}
// 34 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_true'}
// 35 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '!='}
// 36 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'leds', 'op': 'write'}
// 37 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'speed', 'op': 'read'}
// 38 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '+'}
// 39 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'rs232_rx', 'op': 'read'}
// Intructions
// ===========
initial
begin
instructions[0] = {6'd0, 7'd57, 7'd0, 32'd1};//{'dest': 57, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1] = {6'd0, 7'd58, 7'd0, 32'd0};//{'dest': 58, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2] = {6'd1, 7'd18, 7'd0, 32'd930};//{'dest': 18, 'label': 930, 'op': 'jmp_and_link'}
instructions[3] = {6'd2, 7'd0, 7'd0, 32'd0};//{'op': 'stop'}
instructions[4] = {6'd3, 7'd31, 7'd45, 32'd0};//{'dest': 31, 'src': 45, 'op': 'move'}
instructions[5] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[6] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[7] = {6'd5, 7'd0, 7'd31, 32'd0};//{'src': 31, 'output': 'socket', 'op': 'write'}
instructions[8] = {6'd6, 7'd0, 7'd44, 32'd0};//{'src': 44, 'op': 'jmp_to_reg'}
instructions[9] = {6'd3, 7'd31, 7'd47, 32'd0};//{'dest': 31, 'src': 47, 'op': 'move'}
instructions[10] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[11] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[12] = {6'd7, 7'd0, 7'd31, 32'd0};//{'src': 31, 'output': 'rs232_tx', 'op': 'write'}
instructions[13] = {6'd6, 7'd0, 7'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[14] = {6'd0, 7'd50, 7'd0, 32'd0};//{'dest': 50, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[15] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[16] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[17] = {6'd3, 7'd32, 7'd50, 32'd0};//{'dest': 32, 'src': 50, 'op': 'move'}
instructions[18] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[19] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[20] = {6'd8, 7'd33, 7'd32, 32'd49};//{'dest': 33, 'src': 32, 'srcb': 49, 'signed': False, 'op': '+'}
instructions[21] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[22] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[23] = {6'd9, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842450488, 'op': 'memory_read_request'}
instructions[24] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[25] = {6'd10, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842450488, 'op': 'memory_read_wait'}
instructions[26] = {6'd11, 7'd31, 7'd33, 32'd0};//{'dest': 31, 'src': 33, 'sequence': 139888842450488, 'element_size': 2, 'op': 'memory_read'}
instructions[27] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[28] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[29] = {6'd12, 7'd0, 7'd31, 32'd47};//{'src': 31, 'label': 47, 'op': 'jmp_if_false'}
instructions[30] = {6'd3, 7'd33, 7'd50, 32'd0};//{'dest': 33, 'src': 50, 'op': 'move'}
instructions[31] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[32] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[33] = {6'd8, 7'd35, 7'd33, 32'd49};//{'dest': 35, 'src': 33, 'srcb': 49, 'signed': False, 'op': '+'}
instructions[34] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[35] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[36] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842475640, 'op': 'memory_read_request'}
instructions[37] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[38] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842475640, 'op': 'memory_read_wait'}
instructions[39] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842475640, 'element_size': 2, 'op': 'memory_read'}
instructions[40] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[41] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[42] = {6'd3, 7'd47, 7'd32, 32'd0};//{'dest': 47, 'src': 32, 'op': 'move'}
instructions[43] = {6'd1, 7'd46, 7'd0, 32'd9};//{'dest': 46, 'label': 9, 'op': 'jmp_and_link'}
instructions[44] = {6'd3, 7'd31, 7'd50, 32'd0};//{'dest': 31, 'src': 50, 'op': 'move'}
instructions[45] = {6'd13, 7'd50, 7'd50, 32'd1};//{'src': 50, 'right': 1, 'dest': 50, 'signed': False, 'op': '+', 'size': 2}
instructions[46] = {6'd14, 7'd0, 7'd0, 32'd48};//{'label': 48, 'op': 'goto'}
instructions[47] = {6'd14, 7'd0, 7'd0, 32'd49};//{'label': 49, 'op': 'goto'}
instructions[48] = {6'd14, 7'd0, 7'd0, 32'd15};//{'label': 15, 'op': 'goto'}
instructions[49] = {6'd6, 7'd0, 7'd48, 32'd0};//{'src': 48, 'op': 'jmp_to_reg'}
instructions[50] = {6'd0, 7'd53, 7'd0, 32'd0};//{'dest': 53, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[51] = {6'd0, 7'd54, 7'd0, 32'd0};//{'dest': 54, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[52] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[53] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[54] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[55] = {6'd3, 7'd53, 7'd31, 32'd0};//{'dest': 53, 'src': 31, 'op': 'move'}
instructions[56] = {6'd3, 7'd32, 7'd52, 32'd0};//{'dest': 32, 'src': 52, 'op': 'move'}
instructions[57] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[58] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[59] = {6'd15, 7'd31, 7'd32, 32'd10000};//{'src': 32, 'right': 10000, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[60] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[61] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[62] = {6'd12, 7'd0, 7'd31, 32'd78};//{'src': 31, 'label': 78, 'op': 'jmp_if_false'}
instructions[63] = {6'd3, 7'd32, 7'd52, 32'd0};//{'dest': 32, 'src': 52, 'op': 'move'}
instructions[64] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[65] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[66] = {6'd16, 7'd31, 7'd32, 32'd10000};//{'src': 32, 'right': 10000, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[67] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[68] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[69] = {6'd3, 7'd52, 7'd31, 32'd0};//{'dest': 52, 'src': 31, 'op': 'move'}
instructions[70] = {6'd3, 7'd32, 7'd53, 32'd0};//{'dest': 32, 'src': 53, 'op': 'move'}
instructions[71] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[72] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[73] = {6'd13, 7'd31, 7'd32, 32'd1};//{'src': 32, 'right': 1, 'dest': 31, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[74] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[75] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[76] = {6'd3, 7'd53, 7'd31, 32'd0};//{'dest': 53, 'src': 31, 'op': 'move'}
instructions[77] = {6'd14, 7'd0, 7'd0, 32'd79};//{'label': 79, 'op': 'goto'}
instructions[78] = {6'd14, 7'd0, 7'd0, 32'd80};//{'label': 80, 'op': 'goto'}
instructions[79] = {6'd14, 7'd0, 7'd0, 32'd56};//{'label': 56, 'op': 'goto'}
instructions[80] = {6'd3, 7'd32, 7'd53, 32'd0};//{'dest': 32, 'src': 53, 'op': 'move'}
instructions[81] = {6'd3, 7'd33, 7'd54, 32'd0};//{'dest': 33, 'src': 54, 'op': 'move'}
instructions[82] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[83] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[84] = {6'd17, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[85] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[86] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[87] = {6'd12, 7'd0, 7'd31, 32'd101};//{'src': 31, 'label': 101, 'op': 'jmp_if_false'}
instructions[88] = {6'd3, 7'd33, 7'd53, 32'd0};//{'dest': 33, 'src': 53, 'op': 'move'}
instructions[89] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[90] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[91] = {6'd18, 7'd32, 7'd33, 32'd48};//{'src': 33, 'right': 48, 'dest': 32, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[92] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[93] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[94] = {6'd3, 7'd47, 7'd32, 32'd0};//{'dest': 47, 'src': 32, 'op': 'move'}
instructions[95] = {6'd1, 7'd46, 7'd0, 32'd9};//{'dest': 46, 'label': 9, 'op': 'jmp_and_link'}
instructions[96] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[97] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[98] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[99] = {6'd3, 7'd54, 7'd31, 32'd0};//{'dest': 54, 'src': 31, 'op': 'move'}
instructions[100] = {6'd14, 7'd0, 7'd0, 32'd101};//{'label': 101, 'op': 'goto'}
instructions[101] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[102] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[103] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[104] = {6'd3, 7'd53, 7'd31, 32'd0};//{'dest': 53, 'src': 31, 'op': 'move'}
instructions[105] = {6'd3, 7'd32, 7'd52, 32'd0};//{'dest': 32, 'src': 52, 'op': 'move'}
instructions[106] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[107] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[108] = {6'd15, 7'd31, 7'd32, 32'd1000};//{'src': 32, 'right': 1000, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[109] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[110] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[111] = {6'd12, 7'd0, 7'd31, 32'd127};//{'src': 31, 'label': 127, 'op': 'jmp_if_false'}
instructions[112] = {6'd3, 7'd32, 7'd52, 32'd0};//{'dest': 32, 'src': 52, 'op': 'move'}
instructions[113] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[114] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[115] = {6'd16, 7'd31, 7'd32, 32'd1000};//{'src': 32, 'right': 1000, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[116] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[117] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[118] = {6'd3, 7'd52, 7'd31, 32'd0};//{'dest': 52, 'src': 31, 'op': 'move'}
instructions[119] = {6'd3, 7'd32, 7'd53, 32'd0};//{'dest': 32, 'src': 53, 'op': 'move'}
instructions[120] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[121] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[122] = {6'd13, 7'd31, 7'd32, 32'd1};//{'src': 32, 'right': 1, 'dest': 31, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[123] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[124] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[125] = {6'd3, 7'd53, 7'd31, 32'd0};//{'dest': 53, 'src': 31, 'op': 'move'}
instructions[126] = {6'd14, 7'd0, 7'd0, 32'd128};//{'label': 128, 'op': 'goto'}
instructions[127] = {6'd14, 7'd0, 7'd0, 32'd129};//{'label': 129, 'op': 'goto'}
instructions[128] = {6'd14, 7'd0, 7'd0, 32'd105};//{'label': 105, 'op': 'goto'}
instructions[129] = {6'd3, 7'd32, 7'd53, 32'd0};//{'dest': 32, 'src': 53, 'op': 'move'}
instructions[130] = {6'd3, 7'd33, 7'd54, 32'd0};//{'dest': 33, 'src': 54, 'op': 'move'}
instructions[131] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[132] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[133] = {6'd17, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[134] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[135] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[136] = {6'd12, 7'd0, 7'd31, 32'd150};//{'src': 31, 'label': 150, 'op': 'jmp_if_false'}
instructions[137] = {6'd3, 7'd33, 7'd53, 32'd0};//{'dest': 33, 'src': 53, 'op': 'move'}
instructions[138] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[139] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[140] = {6'd18, 7'd32, 7'd33, 32'd48};//{'src': 33, 'right': 48, 'dest': 32, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[141] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[142] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[143] = {6'd3, 7'd47, 7'd32, 32'd0};//{'dest': 47, 'src': 32, 'op': 'move'}
instructions[144] = {6'd1, 7'd46, 7'd0, 32'd9};//{'dest': 46, 'label': 9, 'op': 'jmp_and_link'}
instructions[145] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[146] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[147] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[148] = {6'd3, 7'd54, 7'd31, 32'd0};//{'dest': 54, 'src': 31, 'op': 'move'}
instructions[149] = {6'd14, 7'd0, 7'd0, 32'd150};//{'label': 150, 'op': 'goto'}
instructions[150] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[151] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[152] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[153] = {6'd3, 7'd53, 7'd31, 32'd0};//{'dest': 53, 'src': 31, 'op': 'move'}
instructions[154] = {6'd3, 7'd32, 7'd52, 32'd0};//{'dest': 32, 'src': 52, 'op': 'move'}
instructions[155] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[156] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[157] = {6'd15, 7'd31, 7'd32, 32'd100};//{'src': 32, 'right': 100, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[158] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[159] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[160] = {6'd12, 7'd0, 7'd31, 32'd176};//{'src': 31, 'label': 176, 'op': 'jmp_if_false'}
instructions[161] = {6'd3, 7'd32, 7'd52, 32'd0};//{'dest': 32, 'src': 52, 'op': 'move'}
instructions[162] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[163] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[164] = {6'd16, 7'd31, 7'd32, 32'd100};//{'src': 32, 'right': 100, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[165] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[166] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[167] = {6'd3, 7'd52, 7'd31, 32'd0};//{'dest': 52, 'src': 31, 'op': 'move'}
instructions[168] = {6'd3, 7'd32, 7'd53, 32'd0};//{'dest': 32, 'src': 53, 'op': 'move'}
instructions[169] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[170] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[171] = {6'd13, 7'd31, 7'd32, 32'd1};//{'src': 32, 'right': 1, 'dest': 31, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[172] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[173] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[174] = {6'd3, 7'd53, 7'd31, 32'd0};//{'dest': 53, 'src': 31, 'op': 'move'}
instructions[175] = {6'd14, 7'd0, 7'd0, 32'd177};//{'label': 177, 'op': 'goto'}
instructions[176] = {6'd14, 7'd0, 7'd0, 32'd178};//{'label': 178, 'op': 'goto'}
instructions[177] = {6'd14, 7'd0, 7'd0, 32'd154};//{'label': 154, 'op': 'goto'}
instructions[178] = {6'd3, 7'd32, 7'd53, 32'd0};//{'dest': 32, 'src': 53, 'op': 'move'}
instructions[179] = {6'd3, 7'd33, 7'd54, 32'd0};//{'dest': 33, 'src': 54, 'op': 'move'}
instructions[180] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[181] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[182] = {6'd17, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[183] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[184] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[185] = {6'd12, 7'd0, 7'd31, 32'd199};//{'src': 31, 'label': 199, 'op': 'jmp_if_false'}
instructions[186] = {6'd3, 7'd33, 7'd53, 32'd0};//{'dest': 33, 'src': 53, 'op': 'move'}
instructions[187] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[188] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[189] = {6'd18, 7'd32, 7'd33, 32'd48};//{'src': 33, 'right': 48, 'dest': 32, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[190] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[191] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[192] = {6'd3, 7'd47, 7'd32, 32'd0};//{'dest': 47, 'src': 32, 'op': 'move'}
instructions[193] = {6'd1, 7'd46, 7'd0, 32'd9};//{'dest': 46, 'label': 9, 'op': 'jmp_and_link'}
instructions[194] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[195] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[196] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[197] = {6'd3, 7'd54, 7'd31, 32'd0};//{'dest': 54, 'src': 31, 'op': 'move'}
instructions[198] = {6'd14, 7'd0, 7'd0, 32'd199};//{'label': 199, 'op': 'goto'}
instructions[199] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[200] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[201] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[202] = {6'd3, 7'd53, 7'd31, 32'd0};//{'dest': 53, 'src': 31, 'op': 'move'}
instructions[203] = {6'd3, 7'd32, 7'd52, 32'd0};//{'dest': 32, 'src': 52, 'op': 'move'}
instructions[204] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[205] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[206] = {6'd15, 7'd31, 7'd32, 32'd10};//{'src': 32, 'right': 10, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[207] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[208] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[209] = {6'd12, 7'd0, 7'd31, 32'd225};//{'src': 31, 'label': 225, 'op': 'jmp_if_false'}
instructions[210] = {6'd3, 7'd32, 7'd52, 32'd0};//{'dest': 32, 'src': 52, 'op': 'move'}
instructions[211] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[212] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[213] = {6'd16, 7'd31, 7'd32, 32'd10};//{'src': 32, 'right': 10, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[214] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[215] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[216] = {6'd3, 7'd52, 7'd31, 32'd0};//{'dest': 52, 'src': 31, 'op': 'move'}
instructions[217] = {6'd3, 7'd32, 7'd53, 32'd0};//{'dest': 32, 'src': 53, 'op': 'move'}
instructions[218] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[219] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[220] = {6'd13, 7'd31, 7'd32, 32'd1};//{'src': 32, 'right': 1, 'dest': 31, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[221] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[222] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[223] = {6'd3, 7'd53, 7'd31, 32'd0};//{'dest': 53, 'src': 31, 'op': 'move'}
instructions[224] = {6'd14, 7'd0, 7'd0, 32'd226};//{'label': 226, 'op': 'goto'}
instructions[225] = {6'd14, 7'd0, 7'd0, 32'd227};//{'label': 227, 'op': 'goto'}
instructions[226] = {6'd14, 7'd0, 7'd0, 32'd203};//{'label': 203, 'op': 'goto'}
instructions[227] = {6'd3, 7'd32, 7'd53, 32'd0};//{'dest': 32, 'src': 53, 'op': 'move'}
instructions[228] = {6'd3, 7'd33, 7'd54, 32'd0};//{'dest': 33, 'src': 54, 'op': 'move'}
instructions[229] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[230] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[231] = {6'd17, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[232] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[233] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[234] = {6'd12, 7'd0, 7'd31, 32'd248};//{'src': 31, 'label': 248, 'op': 'jmp_if_false'}
instructions[235] = {6'd3, 7'd33, 7'd53, 32'd0};//{'dest': 33, 'src': 53, 'op': 'move'}
instructions[236] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[237] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[238] = {6'd18, 7'd32, 7'd33, 32'd48};//{'src': 33, 'right': 48, 'dest': 32, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[239] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[240] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[241] = {6'd3, 7'd47, 7'd32, 32'd0};//{'dest': 47, 'src': 32, 'op': 'move'}
instructions[242] = {6'd1, 7'd46, 7'd0, 32'd9};//{'dest': 46, 'label': 9, 'op': 'jmp_and_link'}
instructions[243] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[244] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[245] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[246] = {6'd3, 7'd54, 7'd31, 32'd0};//{'dest': 54, 'src': 31, 'op': 'move'}
instructions[247] = {6'd14, 7'd0, 7'd0, 32'd248};//{'label': 248, 'op': 'goto'}
instructions[248] = {6'd3, 7'd33, 7'd52, 32'd0};//{'dest': 33, 'src': 52, 'op': 'move'}
instructions[249] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[250] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[251] = {6'd18, 7'd32, 7'd33, 32'd48};//{'src': 33, 'right': 48, 'dest': 32, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[252] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[253] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[254] = {6'd3, 7'd47, 7'd32, 32'd0};//{'dest': 47, 'src': 32, 'op': 'move'}
instructions[255] = {6'd1, 7'd46, 7'd0, 32'd9};//{'dest': 46, 'label': 9, 'op': 'jmp_and_link'}
instructions[256] = {6'd6, 7'd0, 7'd51, 32'd0};//{'src': 51, 'op': 'jmp_to_reg'}
instructions[257] = {6'd3, 7'd32, 7'd56, 32'd0};//{'dest': 32, 'src': 56, 'op': 'move'}
instructions[258] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[259] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[260] = {6'd19, 7'd31, 7'd32, 32'd0};//{'src': 32, 'right': 0, 'dest': 31, 'signed': True, 'op': '>=', 'type': 'int', 'size': 2}
instructions[261] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[262] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[263] = {6'd12, 7'd0, 7'd31, 32'd270};//{'src': 31, 'label': 270, 'op': 'jmp_if_false'}
instructions[264] = {6'd3, 7'd32, 7'd56, 32'd0};//{'dest': 32, 'src': 56, 'op': 'move'}
instructions[265] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[266] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[267] = {6'd3, 7'd52, 7'd32, 32'd0};//{'dest': 52, 'src': 32, 'op': 'move'}
instructions[268] = {6'd1, 7'd51, 7'd0, 32'd50};//{'dest': 51, 'label': 50, 'op': 'jmp_and_link'}
instructions[269] = {6'd14, 7'd0, 7'd0, 32'd283};//{'label': 283, 'op': 'goto'}
instructions[270] = {6'd0, 7'd32, 7'd0, 32'd45};//{'dest': 32, 'literal': 45, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[271] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[272] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[273] = {6'd3, 7'd47, 7'd32, 32'd0};//{'dest': 47, 'src': 32, 'op': 'move'}
instructions[274] = {6'd1, 7'd46, 7'd0, 32'd9};//{'dest': 46, 'label': 9, 'op': 'jmp_and_link'}
instructions[275] = {6'd3, 7'd33, 7'd56, 32'd0};//{'dest': 33, 'src': 56, 'op': 'move'}
instructions[276] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[277] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[278] = {6'd20, 7'd32, 7'd33, 32'd0};//{'src': 33, 'dest': 32, 'signed': True, 'op': '-', 'size': 2, 'type': 'int', 'left': 0}
instructions[279] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[280] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[281] = {6'd3, 7'd52, 7'd32, 32'd0};//{'dest': 52, 'src': 32, 'op': 'move'}
instructions[282] = {6'd1, 7'd51, 7'd0, 32'd50};//{'dest': 51, 'label': 50, 'op': 'jmp_and_link'}
instructions[283] = {6'd6, 7'd0, 7'd55, 32'd0};//{'src': 55, 'op': 'jmp_to_reg'}
instructions[284] = {6'd3, 7'd31, 7'd57, 32'd0};//{'dest': 31, 'src': 57, 'op': 'move'}
instructions[285] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[286] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[287] = {6'd12, 7'd0, 7'd31, 32'd300};//{'src': 31, 'label': 300, 'op': 'jmp_if_false'}
instructions[288] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[289] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[290] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[291] = {6'd3, 7'd57, 7'd31, 32'd0};//{'dest': 57, 'src': 31, 'op': 'move'}
instructions[292] = {6'd3, 7'd32, 7'd60, 32'd0};//{'dest': 32, 'src': 60, 'op': 'move'}
instructions[293] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[294] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[295] = {6'd21, 7'd31, 7'd32, 32'd8};//{'src': 32, 'right': 8, 'dest': 31, 'signed': True, 'op': '<<', 'type': 'int', 'size': 2}
instructions[296] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[297] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[298] = {6'd3, 7'd58, 7'd31, 32'd0};//{'dest': 58, 'src': 31, 'op': 'move'}
instructions[299] = {6'd14, 7'd0, 7'd0, 32'd322};//{'label': 322, 'op': 'goto'}
instructions[300] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[301] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[302] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[303] = {6'd3, 7'd57, 7'd31, 32'd0};//{'dest': 57, 'src': 31, 'op': 'move'}
instructions[304] = {6'd3, 7'd32, 7'd58, 32'd0};//{'dest': 32, 'src': 58, 'op': 'move'}
instructions[305] = {6'd3, 7'd35, 7'd60, 32'd0};//{'dest': 35, 'src': 60, 'op': 'move'}
instructions[306] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[307] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[308] = {6'd22, 7'd33, 7'd35, 32'd255};//{'src': 35, 'right': 255, 'dest': 33, 'signed': True, 'op': '&', 'type': 'int', 'size': 2}
instructions[309] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[310] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[311] = {6'd17, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[312] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[313] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[314] = {6'd3, 7'd58, 7'd31, 32'd0};//{'dest': 58, 'src': 31, 'op': 'move'}
instructions[315] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[316] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[317] = {6'd3, 7'd32, 7'd58, 32'd0};//{'dest': 32, 'src': 58, 'op': 'move'}
instructions[318] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[319] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[320] = {6'd3, 7'd45, 7'd32, 32'd0};//{'dest': 45, 'src': 32, 'op': 'move'}
instructions[321] = {6'd1, 7'd44, 7'd0, 32'd4};//{'dest': 44, 'label': 4, 'op': 'jmp_and_link'}
instructions[322] = {6'd6, 7'd0, 7'd59, 32'd0};//{'src': 59, 'op': 'jmp_to_reg'}
instructions[323] = {6'd3, 7'd32, 7'd57, 32'd0};//{'dest': 32, 'src': 57, 'op': 'move'}
instructions[324] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[325] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[326] = {6'd23, 7'd31, 7'd32, 32'd0};//{'src': 32, 'right': 0, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[327] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[328] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[329] = {6'd12, 7'd0, 7'd31, 32'd336};//{'src': 31, 'label': 336, 'op': 'jmp_if_false'}
instructions[330] = {6'd3, 7'd32, 7'd58, 32'd0};//{'dest': 32, 'src': 58, 'op': 'move'}
instructions[331] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[332] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[333] = {6'd3, 7'd45, 7'd32, 32'd0};//{'dest': 45, 'src': 32, 'op': 'move'}
instructions[334] = {6'd1, 7'd44, 7'd0, 32'd4};//{'dest': 44, 'label': 4, 'op': 'jmp_and_link'}
instructions[335] = {6'd14, 7'd0, 7'd0, 32'd336};//{'label': 336, 'op': 'goto'}
instructions[336] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[337] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[338] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[339] = {6'd3, 7'd57, 7'd31, 32'd0};//{'dest': 57, 'src': 31, 'op': 'move'}
instructions[340] = {6'd6, 7'd0, 7'd61, 32'd0};//{'src': 61, 'op': 'jmp_to_reg'}
instructions[341] = {6'd0, 7'd64, 7'd0, 32'd0};//{'dest': 64, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[342] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[343] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[344] = {6'd3, 7'd32, 7'd64, 32'd0};//{'dest': 32, 'src': 64, 'op': 'move'}
instructions[345] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[346] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[347] = {6'd8, 7'd33, 7'd32, 32'd63};//{'dest': 33, 'src': 32, 'srcb': 63, 'signed': False, 'op': '+'}
instructions[348] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[349] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[350] = {6'd9, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842595720, 'op': 'memory_read_request'}
instructions[351] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[352] = {6'd10, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842595720, 'op': 'memory_read_wait'}
instructions[353] = {6'd11, 7'd31, 7'd33, 32'd0};//{'dest': 31, 'src': 33, 'sequence': 139888842595720, 'element_size': 2, 'op': 'memory_read'}
instructions[354] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[355] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[356] = {6'd12, 7'd0, 7'd31, 32'd374};//{'src': 31, 'label': 374, 'op': 'jmp_if_false'}
instructions[357] = {6'd3, 7'd33, 7'd64, 32'd0};//{'dest': 33, 'src': 64, 'op': 'move'}
instructions[358] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[359] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[360] = {6'd8, 7'd35, 7'd33, 32'd63};//{'dest': 35, 'src': 33, 'srcb': 63, 'signed': False, 'op': '+'}
instructions[361] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[362] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[363] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842608584, 'op': 'memory_read_request'}
instructions[364] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[365] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842608584, 'op': 'memory_read_wait'}
instructions[366] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842608584, 'element_size': 2, 'op': 'memory_read'}
instructions[367] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[368] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[369] = {6'd3, 7'd60, 7'd32, 32'd0};//{'dest': 60, 'src': 32, 'op': 'move'}
instructions[370] = {6'd1, 7'd59, 7'd0, 32'd284};//{'dest': 59, 'label': 284, 'op': 'jmp_and_link'}
instructions[371] = {6'd3, 7'd31, 7'd64, 32'd0};//{'dest': 31, 'src': 64, 'op': 'move'}
instructions[372] = {6'd13, 7'd64, 7'd64, 32'd1};//{'src': 64, 'right': 1, 'dest': 64, 'signed': False, 'op': '+', 'size': 2}
instructions[373] = {6'd14, 7'd0, 7'd0, 32'd375};//{'label': 375, 'op': 'goto'}
instructions[374] = {6'd14, 7'd0, 7'd0, 32'd376};//{'label': 376, 'op': 'goto'}
instructions[375] = {6'd14, 7'd0, 7'd0, 32'd342};//{'label': 342, 'op': 'goto'}
instructions[376] = {6'd6, 7'd0, 7'd62, 32'd0};//{'src': 62, 'op': 'jmp_to_reg'}
instructions[377] = {6'd0, 7'd67, 7'd0, 32'd0};//{'dest': 67, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[378] = {6'd0, 7'd68, 7'd0, 32'd0};//{'dest': 68, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[379] = {6'd0, 7'd69, 7'd0, 32'd0};//{'dest': 69, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[380] = {6'd0, 7'd70, 7'd0, 32'd0};//{'dest': 70, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[381] = {6'd0, 7'd71, 7'd0, 32'd0};//{'dest': 71, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[382] = {6'd0, 7'd72, 7'd0, 32'd0};//{'dest': 72, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[383] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[384] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[385] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[386] = {6'd15, 7'd31, 7'd32, 32'd10000};//{'src': 32, 'right': 10000, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[387] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[388] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[389] = {6'd12, 7'd0, 7'd31, 32'd400};//{'src': 31, 'label': 400, 'op': 'jmp_if_false'}
instructions[390] = {6'd3, 7'd31, 7'd71, 32'd0};//{'dest': 31, 'src': 71, 'op': 'move'}
instructions[391] = {6'd13, 7'd71, 7'd71, 32'd1};//{'src': 71, 'right': 1, 'dest': 71, 'signed': False, 'op': '+', 'size': 2}
instructions[392] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[393] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[394] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[395] = {6'd16, 7'd31, 7'd32, 32'd10000};//{'src': 32, 'right': 10000, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[396] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[397] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[398] = {6'd3, 7'd66, 7'd31, 32'd0};//{'dest': 66, 'src': 31, 'op': 'move'}
instructions[399] = {6'd14, 7'd0, 7'd0, 32'd401};//{'label': 401, 'op': 'goto'}
instructions[400] = {6'd14, 7'd0, 7'd0, 32'd402};//{'label': 402, 'op': 'goto'}
instructions[401] = {6'd14, 7'd0, 7'd0, 32'd383};//{'label': 383, 'op': 'goto'}
instructions[402] = {6'd3, 7'd32, 7'd71, 32'd0};//{'dest': 32, 'src': 71, 'op': 'move'}
instructions[403] = {6'd3, 7'd33, 7'd72, 32'd0};//{'dest': 33, 'src': 72, 'op': 'move'}
instructions[404] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[405] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[406] = {6'd17, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[407] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[408] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[409] = {6'd12, 7'd0, 7'd31, 32'd423};//{'src': 31, 'label': 423, 'op': 'jmp_if_false'}
instructions[410] = {6'd3, 7'd33, 7'd71, 32'd0};//{'dest': 33, 'src': 71, 'op': 'move'}
instructions[411] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[412] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[413] = {6'd24, 7'd32, 7'd33, 32'd48};//{'src': 33, 'dest': 32, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[414] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[415] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[416] = {6'd3, 7'd60, 7'd32, 32'd0};//{'dest': 60, 'src': 32, 'op': 'move'}
instructions[417] = {6'd1, 7'd59, 7'd0, 32'd284};//{'dest': 59, 'label': 284, 'op': 'jmp_and_link'}
instructions[418] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[419] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[420] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[421] = {6'd3, 7'd72, 7'd31, 32'd0};//{'dest': 72, 'src': 31, 'op': 'move'}
instructions[422] = {6'd14, 7'd0, 7'd0, 32'd423};//{'label': 423, 'op': 'goto'}
instructions[423] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[424] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[425] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[426] = {6'd15, 7'd31, 7'd32, 32'd1000};//{'src': 32, 'right': 1000, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[427] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[428] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[429] = {6'd12, 7'd0, 7'd31, 32'd440};//{'src': 31, 'label': 440, 'op': 'jmp_if_false'}
instructions[430] = {6'd3, 7'd31, 7'd70, 32'd0};//{'dest': 31, 'src': 70, 'op': 'move'}
instructions[431] = {6'd13, 7'd70, 7'd70, 32'd1};//{'src': 70, 'right': 1, 'dest': 70, 'signed': False, 'op': '+', 'size': 2}
instructions[432] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[433] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[434] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[435] = {6'd16, 7'd31, 7'd32, 32'd1000};//{'src': 32, 'right': 1000, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[436] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[437] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[438] = {6'd3, 7'd66, 7'd31, 32'd0};//{'dest': 66, 'src': 31, 'op': 'move'}
instructions[439] = {6'd14, 7'd0, 7'd0, 32'd441};//{'label': 441, 'op': 'goto'}
instructions[440] = {6'd14, 7'd0, 7'd0, 32'd442};//{'label': 442, 'op': 'goto'}
instructions[441] = {6'd14, 7'd0, 7'd0, 32'd423};//{'label': 423, 'op': 'goto'}
instructions[442] = {6'd3, 7'd32, 7'd70, 32'd0};//{'dest': 32, 'src': 70, 'op': 'move'}
instructions[443] = {6'd3, 7'd33, 7'd72, 32'd0};//{'dest': 33, 'src': 72, 'op': 'move'}
instructions[444] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[445] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[446] = {6'd17, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[447] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[448] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[449] = {6'd12, 7'd0, 7'd31, 32'd463};//{'src': 31, 'label': 463, 'op': 'jmp_if_false'}
instructions[450] = {6'd3, 7'd33, 7'd70, 32'd0};//{'dest': 33, 'src': 70, 'op': 'move'}
instructions[451] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[452] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[453] = {6'd24, 7'd32, 7'd33, 32'd48};//{'src': 33, 'dest': 32, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[454] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[455] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[456] = {6'd3, 7'd60, 7'd32, 32'd0};//{'dest': 60, 'src': 32, 'op': 'move'}
instructions[457] = {6'd1, 7'd59, 7'd0, 32'd284};//{'dest': 59, 'label': 284, 'op': 'jmp_and_link'}
instructions[458] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[459] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[460] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[461] = {6'd3, 7'd72, 7'd31, 32'd0};//{'dest': 72, 'src': 31, 'op': 'move'}
instructions[462] = {6'd14, 7'd0, 7'd0, 32'd463};//{'label': 463, 'op': 'goto'}
instructions[463] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[464] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[465] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[466] = {6'd15, 7'd31, 7'd32, 32'd100};//{'src': 32, 'right': 100, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[467] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[468] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[469] = {6'd12, 7'd0, 7'd31, 32'd480};//{'src': 31, 'label': 480, 'op': 'jmp_if_false'}
instructions[470] = {6'd3, 7'd31, 7'd69, 32'd0};//{'dest': 31, 'src': 69, 'op': 'move'}
instructions[471] = {6'd13, 7'd69, 7'd69, 32'd1};//{'src': 69, 'right': 1, 'dest': 69, 'signed': False, 'op': '+', 'size': 2}
instructions[472] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[473] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[474] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[475] = {6'd16, 7'd31, 7'd32, 32'd100};//{'src': 32, 'right': 100, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[476] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[477] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[478] = {6'd3, 7'd66, 7'd31, 32'd0};//{'dest': 66, 'src': 31, 'op': 'move'}
instructions[479] = {6'd14, 7'd0, 7'd0, 32'd481};//{'label': 481, 'op': 'goto'}
instructions[480] = {6'd14, 7'd0, 7'd0, 32'd482};//{'label': 482, 'op': 'goto'}
instructions[481] = {6'd14, 7'd0, 7'd0, 32'd463};//{'label': 463, 'op': 'goto'}
instructions[482] = {6'd3, 7'd32, 7'd69, 32'd0};//{'dest': 32, 'src': 69, 'op': 'move'}
instructions[483] = {6'd3, 7'd33, 7'd72, 32'd0};//{'dest': 33, 'src': 72, 'op': 'move'}
instructions[484] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[485] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[486] = {6'd17, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[487] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[488] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[489] = {6'd12, 7'd0, 7'd31, 32'd503};//{'src': 31, 'label': 503, 'op': 'jmp_if_false'}
instructions[490] = {6'd3, 7'd33, 7'd69, 32'd0};//{'dest': 33, 'src': 69, 'op': 'move'}
instructions[491] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[492] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[493] = {6'd24, 7'd32, 7'd33, 32'd48};//{'src': 33, 'dest': 32, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[494] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[495] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[496] = {6'd3, 7'd60, 7'd32, 32'd0};//{'dest': 60, 'src': 32, 'op': 'move'}
instructions[497] = {6'd1, 7'd59, 7'd0, 32'd284};//{'dest': 59, 'label': 284, 'op': 'jmp_and_link'}
instructions[498] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[499] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[500] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[501] = {6'd3, 7'd72, 7'd31, 32'd0};//{'dest': 72, 'src': 31, 'op': 'move'}
instructions[502] = {6'd14, 7'd0, 7'd0, 32'd503};//{'label': 503, 'op': 'goto'}
instructions[503] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[504] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[505] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[506] = {6'd15, 7'd31, 7'd32, 32'd10};//{'src': 32, 'right': 10, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[507] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[508] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[509] = {6'd12, 7'd0, 7'd31, 32'd520};//{'src': 31, 'label': 520, 'op': 'jmp_if_false'}
instructions[510] = {6'd3, 7'd31, 7'd68, 32'd0};//{'dest': 31, 'src': 68, 'op': 'move'}
instructions[511] = {6'd13, 7'd68, 7'd68, 32'd1};//{'src': 68, 'right': 1, 'dest': 68, 'signed': False, 'op': '+', 'size': 2}
instructions[512] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[513] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[514] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[515] = {6'd16, 7'd31, 7'd32, 32'd10};//{'src': 32, 'right': 10, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[516] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[517] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[518] = {6'd3, 7'd66, 7'd31, 32'd0};//{'dest': 66, 'src': 31, 'op': 'move'}
instructions[519] = {6'd14, 7'd0, 7'd0, 32'd521};//{'label': 521, 'op': 'goto'}
instructions[520] = {6'd14, 7'd0, 7'd0, 32'd522};//{'label': 522, 'op': 'goto'}
instructions[521] = {6'd14, 7'd0, 7'd0, 32'd503};//{'label': 503, 'op': 'goto'}
instructions[522] = {6'd3, 7'd32, 7'd68, 32'd0};//{'dest': 32, 'src': 68, 'op': 'move'}
instructions[523] = {6'd3, 7'd33, 7'd72, 32'd0};//{'dest': 33, 'src': 72, 'op': 'move'}
instructions[524] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[525] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[526] = {6'd17, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[527] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[528] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[529] = {6'd12, 7'd0, 7'd31, 32'd543};//{'src': 31, 'label': 543, 'op': 'jmp_if_false'}
instructions[530] = {6'd3, 7'd33, 7'd68, 32'd0};//{'dest': 33, 'src': 68, 'op': 'move'}
instructions[531] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[532] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[533] = {6'd24, 7'd32, 7'd33, 32'd48};//{'src': 33, 'dest': 32, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[534] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[535] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[536] = {6'd3, 7'd60, 7'd32, 32'd0};//{'dest': 60, 'src': 32, 'op': 'move'}
instructions[537] = {6'd1, 7'd59, 7'd0, 32'd284};//{'dest': 59, 'label': 284, 'op': 'jmp_and_link'}
instructions[538] = {6'd0, 7'd31, 7'd0, 32'd1};//{'dest': 31, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[539] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[540] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[541] = {6'd3, 7'd72, 7'd31, 32'd0};//{'dest': 72, 'src': 31, 'op': 'move'}
instructions[542] = {6'd14, 7'd0, 7'd0, 32'd543};//{'label': 543, 'op': 'goto'}
instructions[543] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[544] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[545] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[546] = {6'd15, 7'd31, 7'd32, 32'd1};//{'src': 32, 'right': 1, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[547] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[548] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[549] = {6'd12, 7'd0, 7'd31, 32'd560};//{'src': 31, 'label': 560, 'op': 'jmp_if_false'}
instructions[550] = {6'd3, 7'd31, 7'd67, 32'd0};//{'dest': 31, 'src': 67, 'op': 'move'}
instructions[551] = {6'd13, 7'd67, 7'd67, 32'd1};//{'src': 67, 'right': 1, 'dest': 67, 'signed': False, 'op': '+', 'size': 2}
instructions[552] = {6'd3, 7'd32, 7'd66, 32'd0};//{'dest': 32, 'src': 66, 'op': 'move'}
instructions[553] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[554] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[555] = {6'd16, 7'd31, 7'd32, 32'd1};//{'src': 32, 'right': 1, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[556] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[557] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[558] = {6'd3, 7'd66, 7'd31, 32'd0};//{'dest': 66, 'src': 31, 'op': 'move'}
instructions[559] = {6'd14, 7'd0, 7'd0, 32'd561};//{'label': 561, 'op': 'goto'}
instructions[560] = {6'd14, 7'd0, 7'd0, 32'd562};//{'label': 562, 'op': 'goto'}
instructions[561] = {6'd14, 7'd0, 7'd0, 32'd543};//{'label': 543, 'op': 'goto'}
instructions[562] = {6'd3, 7'd33, 7'd67, 32'd0};//{'dest': 33, 'src': 67, 'op': 'move'}
instructions[563] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[564] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[565] = {6'd24, 7'd32, 7'd33, 32'd48};//{'src': 33, 'dest': 32, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 48}
instructions[566] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[567] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[568] = {6'd3, 7'd60, 7'd32, 32'd0};//{'dest': 60, 'src': 32, 'op': 'move'}
instructions[569] = {6'd1, 7'd59, 7'd0, 32'd284};//{'dest': 59, 'label': 284, 'op': 'jmp_and_link'}
instructions[570] = {6'd6, 7'd0, 7'd65, 32'd0};//{'src': 65, 'op': 'jmp_to_reg'}
instructions[571] = {6'd0, 7'd74, 7'd0, 32'd0};//{'dest': 74, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[572] = {6'd0, 7'd75, 7'd0, 32'd4};//{'dest': 75, 'literal': 4, 'op': 'literal'}
instructions[573] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[574] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[575] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[576] = {6'd3, 7'd74, 7'd31, 32'd0};//{'dest': 74, 'src': 31, 'op': 'move'}
instructions[577] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[578] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[579] = {6'd3, 7'd32, 7'd74, 32'd0};//{'dest': 32, 'src': 74, 'op': 'move'}
instructions[580] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[581] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[582] = {6'd8, 7'd33, 7'd32, 32'd75};//{'dest': 33, 'src': 32, 'srcb': 75, 'signed': False, 'op': '+'}
instructions[583] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[584] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[585] = {6'd9, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842668656, 'op': 'memory_read_request'}
instructions[586] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[587] = {6'd10, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842668656, 'op': 'memory_read_wait'}
instructions[588] = {6'd11, 7'd31, 7'd33, 32'd0};//{'dest': 31, 'src': 33, 'sequence': 139888842668656, 'element_size': 2, 'op': 'memory_read'}
instructions[589] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[590] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[591] = {6'd12, 7'd0, 7'd31, 32'd595};//{'src': 31, 'label': 595, 'op': 'jmp_if_false'}
instructions[592] = {6'd3, 7'd31, 7'd74, 32'd0};//{'dest': 31, 'src': 74, 'op': 'move'}
instructions[593] = {6'd13, 7'd74, 7'd74, 32'd1};//{'src': 74, 'right': 1, 'dest': 74, 'signed': False, 'op': '+', 'size': 2}
instructions[594] = {6'd14, 7'd0, 7'd0, 32'd596};//{'label': 596, 'op': 'goto'}
instructions[595] = {6'd14, 7'd0, 7'd0, 32'd597};//{'label': 597, 'op': 'goto'}
instructions[596] = {6'd14, 7'd0, 7'd0, 32'd577};//{'label': 577, 'op': 'goto'}
instructions[597] = {6'd3, 7'd32, 7'd74, 32'd0};//{'dest': 32, 'src': 74, 'op': 'move'}
instructions[598] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[599] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[600] = {6'd3, 7'd45, 7'd32, 32'd0};//{'dest': 45, 'src': 32, 'op': 'move'}
instructions[601] = {6'd1, 7'd44, 7'd0, 32'd4};//{'dest': 44, 'label': 4, 'op': 'jmp_and_link'}
instructions[602] = {6'd3, 7'd36, 7'd75, 32'd0};//{'dest': 36, 'src': 75, 'op': 'move'}
instructions[603] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[604] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[605] = {6'd3, 7'd63, 7'd36, 32'd0};//{'dest': 63, 'src': 36, 'op': 'move'}
instructions[606] = {6'd1, 7'd62, 7'd0, 32'd341};//{'dest': 62, 'label': 341, 'op': 'jmp_and_link'}
instructions[607] = {6'd1, 7'd61, 7'd0, 32'd323};//{'dest': 61, 'label': 323, 'op': 'jmp_and_link'}
instructions[608] = {6'd6, 7'd0, 7'd73, 32'd0};//{'src': 73, 'op': 'jmp_to_reg'}
instructions[609] = {6'd0, 7'd2, 7'd0, 32'd0};//{'dest': 2, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[610] = {6'd0, 7'd3, 7'd0, 32'd0};//{'dest': 3, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[611] = {6'd0, 7'd4, 7'd0, 32'd0};//{'dest': 4, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[612] = {6'd0, 7'd5, 7'd0, 32'd0};//{'dest': 5, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[613] = {6'd0, 7'd6, 7'd0, 32'd0};//{'dest': 6, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[614] = {6'd0, 7'd7, 7'd0, 32'd132};//{'dest': 7, 'literal': 132, 'op': 'literal'}
instructions[615] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[616] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[617] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[618] = {6'd3, 7'd3, 7'd31, 32'd0};//{'dest': 3, 'src': 31, 'op': 'move'}
instructions[619] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[620] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[621] = {6'd3, 7'd32, 7'd3, 32'd0};//{'dest': 32, 'src': 3, 'op': 'move'}
instructions[622] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[623] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[624] = {6'd8, 7'd33, 7'd32, 32'd1};//{'dest': 33, 'src': 32, 'srcb': 1, 'signed': False, 'op': '+'}
instructions[625] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[626] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[627] = {6'd9, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842168440, 'op': 'memory_read_request'}
instructions[628] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[629] = {6'd10, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842168440, 'op': 'memory_read_wait'}
instructions[630] = {6'd11, 7'd31, 7'd33, 32'd0};//{'dest': 31, 'src': 33, 'sequence': 139888842168440, 'element_size': 2, 'op': 'memory_read'}
instructions[631] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[632] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[633] = {6'd12, 7'd0, 7'd31, 32'd637};//{'src': 31, 'label': 637, 'op': 'jmp_if_false'}
instructions[634] = {6'd3, 7'd31, 7'd3, 32'd0};//{'dest': 31, 'src': 3, 'op': 'move'}
instructions[635] = {6'd13, 7'd3, 7'd3, 32'd1};//{'src': 3, 'right': 1, 'dest': 3, 'signed': False, 'op': '+', 'size': 2}
instructions[636] = {6'd14, 7'd0, 7'd0, 32'd638};//{'label': 638, 'op': 'goto'}
instructions[637] = {6'd14, 7'd0, 7'd0, 32'd639};//{'label': 639, 'op': 'goto'}
instructions[638] = {6'd14, 7'd0, 7'd0, 32'd619};//{'label': 619, 'op': 'goto'}
instructions[639] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[640] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[641] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[642] = {6'd3, 7'd2, 7'd31, 32'd0};//{'dest': 2, 'src': 31, 'op': 'move'}
instructions[643] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[644] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[645] = {6'd3, 7'd32, 7'd2, 32'd0};//{'dest': 32, 'src': 2, 'op': 'move'}
instructions[646] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[647] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[648] = {6'd8, 7'd33, 7'd32, 32'd7};//{'dest': 33, 'src': 32, 'srcb': 7, 'signed': False, 'op': '+'}
instructions[649] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[650] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[651] = {6'd9, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842169304, 'op': 'memory_read_request'}
instructions[652] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[653] = {6'd10, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842169304, 'op': 'memory_read_wait'}
instructions[654] = {6'd11, 7'd31, 7'd33, 32'd0};//{'dest': 31, 'src': 33, 'sequence': 139888842169304, 'element_size': 2, 'op': 'memory_read'}
instructions[655] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[656] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[657] = {6'd12, 7'd0, 7'd31, 32'd661};//{'src': 31, 'label': 661, 'op': 'jmp_if_false'}
instructions[658] = {6'd3, 7'd31, 7'd2, 32'd0};//{'dest': 31, 'src': 2, 'op': 'move'}
instructions[659] = {6'd13, 7'd2, 7'd2, 32'd1};//{'src': 2, 'right': 1, 'dest': 2, 'signed': False, 'op': '+', 'size': 2}
instructions[660] = {6'd14, 7'd0, 7'd0, 32'd662};//{'label': 662, 'op': 'goto'}
instructions[661] = {6'd14, 7'd0, 7'd0, 32'd663};//{'label': 663, 'op': 'goto'}
instructions[662] = {6'd14, 7'd0, 7'd0, 32'd643};//{'label': 643, 'op': 'goto'}
instructions[663] = {6'd3, 7'd32, 7'd2, 32'd0};//{'dest': 32, 'src': 2, 'op': 'move'}
instructions[664] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[665] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[666] = {6'd13, 7'd31, 7'd32, 32'd5};//{'src': 32, 'right': 5, 'dest': 31, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[667] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[668] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[669] = {6'd3, 7'd4, 7'd31, 32'd0};//{'dest': 4, 'src': 31, 'op': 'move'}
instructions[670] = {6'd3, 7'd32, 7'd3, 32'd0};//{'dest': 32, 'src': 3, 'op': 'move'}
instructions[671] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[672] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[673] = {6'd25, 7'd31, 7'd32, 32'd9};//{'src': 32, 'right': 9, 'dest': 31, 'signed': False, 'op': '>', 'type': 'int', 'size': 2}
instructions[674] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[675] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[676] = {6'd12, 7'd0, 7'd31, 32'd680};//{'src': 31, 'label': 680, 'op': 'jmp_if_false'}
instructions[677] = {6'd3, 7'd31, 7'd4, 32'd0};//{'dest': 31, 'src': 4, 'op': 'move'}
instructions[678] = {6'd13, 7'd4, 7'd4, 32'd1};//{'src': 4, 'right': 1, 'dest': 4, 'signed': False, 'op': '+', 'size': 2}
instructions[679] = {6'd14, 7'd0, 7'd0, 32'd680};//{'label': 680, 'op': 'goto'}
instructions[680] = {6'd3, 7'd32, 7'd3, 32'd0};//{'dest': 32, 'src': 3, 'op': 'move'}
instructions[681] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[682] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[683] = {6'd25, 7'd31, 7'd32, 32'd99};//{'src': 32, 'right': 99, 'dest': 31, 'signed': False, 'op': '>', 'type': 'int', 'size': 2}
instructions[684] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[685] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[686] = {6'd12, 7'd0, 7'd31, 32'd690};//{'src': 31, 'label': 690, 'op': 'jmp_if_false'}
instructions[687] = {6'd3, 7'd31, 7'd4, 32'd0};//{'dest': 31, 'src': 4, 'op': 'move'}
instructions[688] = {6'd13, 7'd4, 7'd4, 32'd1};//{'src': 4, 'right': 1, 'dest': 4, 'signed': False, 'op': '+', 'size': 2}
instructions[689] = {6'd14, 7'd0, 7'd0, 32'd690};//{'label': 690, 'op': 'goto'}
instructions[690] = {6'd3, 7'd32, 7'd3, 32'd0};//{'dest': 32, 'src': 3, 'op': 'move'}
instructions[691] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[692] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[693] = {6'd25, 7'd31, 7'd32, 32'd999};//{'src': 32, 'right': 999, 'dest': 31, 'signed': False, 'op': '>', 'type': 'int', 'size': 2}
instructions[694] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[695] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[696] = {6'd12, 7'd0, 7'd31, 32'd700};//{'src': 31, 'label': 700, 'op': 'jmp_if_false'}
instructions[697] = {6'd3, 7'd31, 7'd4, 32'd0};//{'dest': 31, 'src': 4, 'op': 'move'}
instructions[698] = {6'd13, 7'd4, 7'd4, 32'd1};//{'src': 4, 'right': 1, 'dest': 4, 'signed': False, 'op': '+', 'size': 2}
instructions[699] = {6'd14, 7'd0, 7'd0, 32'd700};//{'label': 700, 'op': 'goto'}
instructions[700] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[701] = {6'd3, 7'd32, 7'd4, 32'd0};//{'dest': 32, 'src': 4, 'op': 'move'}
instructions[702] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[703] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[704] = {6'd3, 7'd45, 7'd32, 32'd0};//{'dest': 45, 'src': 32, 'op': 'move'}
instructions[705] = {6'd1, 7'd44, 7'd0, 32'd4};//{'dest': 44, 'label': 4, 'op': 'jmp_and_link'}
instructions[706] = {6'd3, 7'd37, 7'd7, 32'd0};//{'dest': 37, 'src': 7, 'op': 'move'}
instructions[707] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[708] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[709] = {6'd3, 7'd63, 7'd37, 32'd0};//{'dest': 63, 'src': 37, 'op': 'move'}
instructions[710] = {6'd1, 7'd62, 7'd0, 32'd341};//{'dest': 62, 'label': 341, 'op': 'jmp_and_link'}
instructions[711] = {6'd3, 7'd32, 7'd3, 32'd0};//{'dest': 32, 'src': 3, 'op': 'move'}
instructions[712] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[713] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[714] = {6'd3, 7'd66, 7'd32, 32'd0};//{'dest': 66, 'src': 32, 'op': 'move'}
instructions[715] = {6'd1, 7'd65, 7'd0, 32'd377};//{'dest': 65, 'label': 377, 'op': 'jmp_and_link'}
instructions[716] = {6'd0, 7'd8, 7'd0, 32'd246};//{'dest': 8, 'literal': 246, 'op': 'literal'}
instructions[717] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[718] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[719] = {6'd3, 7'd38, 7'd8, 32'd0};//{'dest': 38, 'src': 8, 'op': 'move'}
instructions[720] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[721] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[722] = {6'd3, 7'd63, 7'd38, 32'd0};//{'dest': 63, 'src': 38, 'op': 'move'}
instructions[723] = {6'd1, 7'd62, 7'd0, 32'd341};//{'dest': 62, 'label': 341, 'op': 'jmp_and_link'}
instructions[724] = {6'd1, 7'd61, 7'd0, 32'd323};//{'dest': 61, 'label': 323, 'op': 'jmp_and_link'}
instructions[725] = {6'd3, 7'd31, 7'd3, 32'd0};//{'dest': 31, 'src': 3, 'op': 'move'}
instructions[726] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[727] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[728] = {6'd3, 7'd4, 7'd31, 32'd0};//{'dest': 4, 'src': 31, 'op': 'move'}
instructions[729] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[730] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[731] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[732] = {6'd3, 7'd5, 7'd31, 32'd0};//{'dest': 5, 'src': 31, 'op': 'move'}
instructions[733] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[734] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[735] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[736] = {6'd3, 7'd6, 7'd31, 32'd0};//{'dest': 6, 'src': 31, 'op': 'move'}
instructions[737] = {6'd3, 7'd32, 7'd4, 32'd0};//{'dest': 32, 'src': 4, 'op': 'move'}
instructions[738] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[739] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[740] = {6'd15, 7'd31, 7'd32, 32'd1046};//{'src': 32, 'right': 1046, 'dest': 31, 'signed': False, 'op': '>=', 'type': 'int', 'size': 2}
instructions[741] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[742] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[743] = {6'd12, 7'd0, 7'd31, 32'd790};//{'src': 31, 'label': 790, 'op': 'jmp_if_false'}
instructions[744] = {6'd3, 7'd32, 7'd4, 32'd0};//{'dest': 32, 'src': 4, 'op': 'move'}
instructions[745] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[746] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[747] = {6'd16, 7'd31, 7'd32, 32'd1046};//{'src': 32, 'right': 1046, 'dest': 31, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[748] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[749] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[750] = {6'd3, 7'd4, 7'd31, 32'd0};//{'dest': 4, 'src': 31, 'op': 'move'}
instructions[751] = {6'd0, 7'd32, 7'd0, 32'd1046};//{'dest': 32, 'literal': 1046, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[752] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[753] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[754] = {6'd3, 7'd45, 7'd32, 32'd0};//{'dest': 45, 'src': 32, 'op': 'move'}
instructions[755] = {6'd1, 7'd44, 7'd0, 32'd4};//{'dest': 44, 'label': 4, 'op': 'jmp_and_link'}
instructions[756] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[757] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[758] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[759] = {6'd3, 7'd6, 7'd31, 32'd0};//{'dest': 6, 'src': 31, 'op': 'move'}
instructions[760] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[761] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[762] = {6'd3, 7'd32, 7'd6, 32'd0};//{'dest': 32, 'src': 6, 'op': 'move'}
instructions[763] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[764] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[765] = {6'd26, 7'd31, 7'd32, 32'd1046};//{'src': 32, 'right': 1046, 'dest': 31, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[766] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[767] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[768] = {6'd12, 7'd0, 7'd31, 32'd788};//{'src': 31, 'label': 788, 'op': 'jmp_if_false'}
instructions[769] = {6'd3, 7'd33, 7'd5, 32'd0};//{'dest': 33, 'src': 5, 'op': 'move'}
instructions[770] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[771] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[772] = {6'd8, 7'd35, 7'd33, 32'd1};//{'dest': 35, 'src': 33, 'srcb': 1, 'signed': False, 'op': '+'}
instructions[773] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[774] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[775] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842209400, 'op': 'memory_read_request'}
instructions[776] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[777] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842209400, 'op': 'memory_read_wait'}
instructions[778] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842209400, 'element_size': 2, 'op': 'memory_read'}
instructions[779] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[780] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[781] = {6'd3, 7'd60, 7'd32, 32'd0};//{'dest': 60, 'src': 32, 'op': 'move'}
instructions[782] = {6'd1, 7'd59, 7'd0, 32'd284};//{'dest': 59, 'label': 284, 'op': 'jmp_and_link'}
instructions[783] = {6'd3, 7'd31, 7'd5, 32'd0};//{'dest': 31, 'src': 5, 'op': 'move'}
instructions[784] = {6'd13, 7'd5, 7'd5, 32'd1};//{'src': 5, 'right': 1, 'dest': 5, 'signed': False, 'op': '+', 'size': 2}
instructions[785] = {6'd3, 7'd31, 7'd6, 32'd0};//{'dest': 31, 'src': 6, 'op': 'move'}
instructions[786] = {6'd13, 7'd6, 7'd6, 32'd1};//{'src': 6, 'right': 1, 'dest': 6, 'signed': False, 'op': '+', 'size': 2}
instructions[787] = {6'd14, 7'd0, 7'd0, 32'd760};//{'label': 760, 'op': 'goto'}
instructions[788] = {6'd1, 7'd61, 7'd0, 32'd323};//{'dest': 61, 'label': 323, 'op': 'jmp_and_link'}
instructions[789] = {6'd14, 7'd0, 7'd0, 32'd791};//{'label': 791, 'op': 'goto'}
instructions[790] = {6'd14, 7'd0, 7'd0, 32'd792};//{'label': 792, 'op': 'goto'}
instructions[791] = {6'd14, 7'd0, 7'd0, 32'd737};//{'label': 737, 'op': 'goto'}
instructions[792] = {6'd3, 7'd32, 7'd4, 32'd0};//{'dest': 32, 'src': 4, 'op': 'move'}
instructions[793] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[794] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[795] = {6'd3, 7'd45, 7'd32, 32'd0};//{'dest': 45, 'src': 32, 'op': 'move'}
instructions[796] = {6'd1, 7'd44, 7'd0, 32'd4};//{'dest': 44, 'label': 4, 'op': 'jmp_and_link'}
instructions[797] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[798] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[799] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[800] = {6'd3, 7'd6, 7'd31, 32'd0};//{'dest': 6, 'src': 31, 'op': 'move'}
instructions[801] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[802] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[803] = {6'd3, 7'd32, 7'd6, 32'd0};//{'dest': 32, 'src': 6, 'op': 'move'}
instructions[804] = {6'd3, 7'd33, 7'd4, 32'd0};//{'dest': 33, 'src': 4, 'op': 'move'}
instructions[805] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[806] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[807] = {6'd27, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[808] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[809] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[810] = {6'd12, 7'd0, 7'd31, 32'd830};//{'src': 31, 'label': 830, 'op': 'jmp_if_false'}
instructions[811] = {6'd3, 7'd33, 7'd5, 32'd0};//{'dest': 33, 'src': 5, 'op': 'move'}
instructions[812] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[813] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[814] = {6'd8, 7'd35, 7'd33, 32'd1};//{'dest': 35, 'src': 33, 'srcb': 1, 'signed': False, 'op': '+'}
instructions[815] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[816] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[817] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842232104, 'op': 'memory_read_request'}
instructions[818] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[819] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842232104, 'op': 'memory_read_wait'}
instructions[820] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842232104, 'element_size': 2, 'op': 'memory_read'}
instructions[821] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[822] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[823] = {6'd3, 7'd60, 7'd32, 32'd0};//{'dest': 60, 'src': 32, 'op': 'move'}
instructions[824] = {6'd1, 7'd59, 7'd0, 32'd284};//{'dest': 59, 'label': 284, 'op': 'jmp_and_link'}
instructions[825] = {6'd3, 7'd31, 7'd5, 32'd0};//{'dest': 31, 'src': 5, 'op': 'move'}
instructions[826] = {6'd13, 7'd5, 7'd5, 32'd1};//{'src': 5, 'right': 1, 'dest': 5, 'signed': False, 'op': '+', 'size': 2}
instructions[827] = {6'd3, 7'd31, 7'd6, 32'd0};//{'dest': 31, 'src': 6, 'op': 'move'}
instructions[828] = {6'd13, 7'd6, 7'd6, 32'd1};//{'src': 6, 'right': 1, 'dest': 6, 'signed': False, 'op': '+', 'size': 2}
instructions[829] = {6'd14, 7'd0, 7'd0, 32'd801};//{'label': 801, 'op': 'goto'}
instructions[830] = {6'd1, 7'd61, 7'd0, 32'd323};//{'dest': 61, 'label': 323, 'op': 'jmp_and_link'}
instructions[831] = {6'd6, 7'd0, 7'd0, 32'd0};//{'src': 0, 'op': 'jmp_to_reg'}
instructions[832] = {6'd3, 7'd15, 7'd13, 32'd0};//{'dest': 15, 'src': 13, 'op': 'move'}
instructions[833] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[834] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[835] = {6'd3, 7'd32, 7'd15, 32'd0};//{'dest': 32, 'src': 15, 'op': 'move'}
instructions[836] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[837] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[838] = {6'd8, 7'd33, 7'd32, 32'd11};//{'dest': 33, 'src': 32, 'srcb': 11, 'signed': False, 'op': '+'}
instructions[839] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[840] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[841] = {6'd9, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842198048, 'op': 'memory_read_request'}
instructions[842] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[843] = {6'd10, 7'd0, 7'd33, 32'd0};//{'element_size': 2, 'src': 33, 'sequence': 139888842198048, 'op': 'memory_read_wait'}
instructions[844] = {6'd11, 7'd31, 7'd33, 32'd0};//{'dest': 31, 'src': 33, 'sequence': 139888842198048, 'element_size': 2, 'op': 'memory_read'}
instructions[845] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[846] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[847] = {6'd12, 7'd0, 7'd31, 32'd923};//{'src': 31, 'label': 923, 'op': 'jmp_if_false'}
instructions[848] = {6'd3, 7'd33, 7'd15, 32'd0};//{'dest': 33, 'src': 15, 'op': 'move'}
instructions[849] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[850] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[851] = {6'd8, 7'd35, 7'd33, 32'd11};//{'dest': 35, 'src': 33, 'srcb': 11, 'signed': False, 'op': '+'}
instructions[852] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[853] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[854] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842234624, 'op': 'memory_read_request'}
instructions[855] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[856] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842234624, 'op': 'memory_read_wait'}
instructions[857] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842234624, 'element_size': 2, 'op': 'memory_read'}
instructions[858] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[859] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[860] = {6'd3, 7'd56, 7'd32, 32'd0};//{'dest': 56, 'src': 32, 'op': 'move'}
instructions[861] = {6'd1, 7'd55, 7'd0, 32'd257};//{'dest': 55, 'label': 257, 'op': 'jmp_and_link'}
instructions[862] = {6'd0, 7'd16, 7'd0, 32'd253};//{'dest': 16, 'literal': 253, 'op': 'literal'}
instructions[863] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[864] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[865] = {6'd3, 7'd34, 7'd16, 32'd0};//{'dest': 34, 'src': 16, 'op': 'move'}
instructions[866] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[867] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[868] = {6'd3, 7'd49, 7'd34, 32'd0};//{'dest': 49, 'src': 34, 'op': 'move'}
instructions[869] = {6'd1, 7'd48, 7'd0, 32'd14};//{'dest': 48, 'label': 14, 'op': 'jmp_and_link'}
instructions[870] = {6'd3, 7'd32, 7'd15, 32'd0};//{'dest': 32, 'src': 15, 'op': 'move'}
instructions[871] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[872] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[873] = {6'd3, 7'd56, 7'd32, 32'd0};//{'dest': 56, 'src': 32, 'op': 'move'}
instructions[874] = {6'd1, 7'd55, 7'd0, 32'd257};//{'dest': 55, 'label': 257, 'op': 'jmp_and_link'}
instructions[875] = {6'd0, 7'd17, 7'd0, 32'd255};//{'dest': 17, 'literal': 255, 'op': 'literal'}
instructions[876] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[877] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[878] = {6'd3, 7'd34, 7'd17, 32'd0};//{'dest': 34, 'src': 17, 'op': 'move'}
instructions[879] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[880] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[881] = {6'd3, 7'd49, 7'd34, 32'd0};//{'dest': 49, 'src': 34, 'op': 'move'}
instructions[882] = {6'd1, 7'd48, 7'd0, 32'd14};//{'dest': 48, 'label': 14, 'op': 'jmp_and_link'}
instructions[883] = {6'd3, 7'd32, 7'd15, 32'd0};//{'dest': 32, 'src': 15, 'op': 'move'}
instructions[884] = {6'd3, 7'd33, 7'd14, 32'd0};//{'dest': 33, 'src': 14, 'op': 'move'}
instructions[885] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[886] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[887] = {6'd28, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[888] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[889] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[890] = {6'd12, 7'd0, 7'd31, 32'd897};//{'src': 31, 'label': 897, 'op': 'jmp_if_false'}
instructions[891] = {6'd0, 7'd31, 7'd0, -32'd1};//{'dest': 31, 'literal': -1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[892] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[893] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[894] = {6'd3, 7'd10, 7'd31, 32'd0};//{'dest': 10, 'src': 31, 'op': 'move'}
instructions[895] = {6'd6, 7'd0, 7'd9, 32'd0};//{'src': 9, 'op': 'jmp_to_reg'}
instructions[896] = {6'd14, 7'd0, 7'd0, 32'd897};//{'label': 897, 'op': 'goto'}
instructions[897] = {6'd3, 7'd33, 7'd15, 32'd0};//{'dest': 33, 'src': 15, 'op': 'move'}
instructions[898] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[899] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[900] = {6'd8, 7'd35, 7'd33, 32'd11};//{'dest': 35, 'src': 33, 'srcb': 11, 'signed': False, 'op': '+'}
instructions[901] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[902] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[903] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842233616, 'op': 'memory_read_request'}
instructions[904] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[905] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842233616, 'op': 'memory_read_wait'}
instructions[906] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842233616, 'element_size': 2, 'op': 'memory_read'}
instructions[907] = {6'd3, 7'd33, 7'd12, 32'd0};//{'dest': 33, 'src': 12, 'op': 'move'}
instructions[908] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[909] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[910] = {6'd28, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[911] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[912] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[913] = {6'd12, 7'd0, 7'd31, 32'd920};//{'src': 31, 'label': 920, 'op': 'jmp_if_false'}
instructions[914] = {6'd3, 7'd31, 7'd15, 32'd0};//{'dest': 31, 'src': 15, 'op': 'move'}
instructions[915] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[916] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[917] = {6'd3, 7'd10, 7'd31, 32'd0};//{'dest': 10, 'src': 31, 'op': 'move'}
instructions[918] = {6'd6, 7'd0, 7'd9, 32'd0};//{'src': 9, 'op': 'jmp_to_reg'}
instructions[919] = {6'd14, 7'd0, 7'd0, 32'd920};//{'label': 920, 'op': 'goto'}
instructions[920] = {6'd3, 7'd31, 7'd15, 32'd0};//{'dest': 31, 'src': 15, 'op': 'move'}
instructions[921] = {6'd29, 7'd15, 7'd15, 32'd1};//{'src': 15, 'right': 1, 'dest': 15, 'signed': True, 'op': '+', 'size': 2}
instructions[922] = {6'd14, 7'd0, 7'd0, 32'd924};//{'label': 924, 'op': 'goto'}
instructions[923] = {6'd14, 7'd0, 7'd0, 32'd925};//{'label': 925, 'op': 'goto'}
instructions[924] = {6'd14, 7'd0, 7'd0, 32'd833};//{'label': 833, 'op': 'goto'}
instructions[925] = {6'd0, 7'd31, 7'd0, -32'd1};//{'dest': 31, 'literal': -1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[926] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[927] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[928] = {6'd3, 7'd10, 7'd31, 32'd0};//{'dest': 10, 'src': 31, 'op': 'move'}
instructions[929] = {6'd6, 7'd0, 7'd9, 32'd0};//{'src': 9, 'op': 'jmp_to_reg'}
instructions[930] = {6'd0, 7'd19, 7'd0, 32'd0};//{'dest': 19, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[931] = {6'd0, 7'd20, 7'd0, 32'd0};//{'dest': 20, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[932] = {6'd0, 7'd21, 7'd0, 32'd0};//{'dest': 21, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[933] = {6'd0, 7'd22, 7'd0, 32'd257};//{'dest': 22, 'literal': 257, 'op': 'literal'}
instructions[934] = {6'd0, 7'd23, 7'd0, 32'd0};//{'dest': 23, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[935] = {6'd0, 7'd24, 7'd0, 32'd0};//{'dest': 24, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[936] = {6'd0, 7'd25, 7'd0, 32'd0};//{'dest': 25, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[937] = {6'd0, 7'd26, 7'd0, 32'd0};//{'dest': 26, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[938] = {6'd0, 7'd27, 7'd0, 32'd0};//{'dest': 27, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[939] = {6'd0, 7'd28, 7'd0, 32'd1717};//{'dest': 28, 'literal': 1717, 'op': 'literal'}
instructions[940] = {6'd0, 7'd29, 7'd0, 32'd2449};//{'dest': 29, 'literal': 2449, 'op': 'literal'}
instructions[941] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[942] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[943] = {6'd3, 7'd39, 7'd29, 32'd0};//{'dest': 39, 'src': 29, 'op': 'move'}
instructions[944] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[945] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[946] = {6'd3, 7'd49, 7'd39, 32'd0};//{'dest': 49, 'src': 39, 'op': 'move'}
instructions[947] = {6'd1, 7'd48, 7'd0, 32'd14};//{'dest': 48, 'label': 14, 'op': 'jmp_and_link'}
instructions[948] = {6'd0, 7'd30, 7'd0, 32'd2489};//{'dest': 30, 'literal': 2489, 'op': 'literal'}
instructions[949] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[950] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[951] = {6'd3, 7'd40, 7'd30, 32'd0};//{'dest': 40, 'src': 30, 'op': 'move'}
instructions[952] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[953] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[954] = {6'd3, 7'd49, 7'd40, 32'd0};//{'dest': 49, 'src': 40, 'op': 'move'}
instructions[955] = {6'd1, 7'd48, 7'd0, 32'd14};//{'dest': 48, 'label': 14, 'op': 'jmp_and_link'}
instructions[956] = {6'd30, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'input': 'socket', 'op': 'read'}
instructions[957] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[958] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[959] = {6'd3, 7'd19, 7'd31, 32'd0};//{'dest': 19, 'src': 31, 'op': 'move'}
instructions[960] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[961] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[962] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[963] = {6'd3, 7'd21, 7'd31, 32'd0};//{'dest': 21, 'src': 31, 'op': 'move'}
instructions[964] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[965] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[966] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[967] = {6'd3, 7'd20, 7'd31, 32'd0};//{'dest': 20, 'src': 31, 'op': 'move'}
instructions[968] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[969] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[970] = {6'd3, 7'd32, 7'd20, 32'd0};//{'dest': 32, 'src': 20, 'op': 'move'}
instructions[971] = {6'd3, 7'd33, 7'd19, 32'd0};//{'dest': 33, 'src': 19, 'op': 'move'}
instructions[972] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[973] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[974] = {6'd27, 7'd31, 7'd32, 32'd33};//{'srcb': 33, 'src': 32, 'dest': 31, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[975] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[976] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[977] = {6'd12, 7'd0, 7'd31, 32'd1021};//{'src': 31, 'label': 1021, 'op': 'jmp_if_false'}
instructions[978] = {6'd30, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'input': 'socket', 'op': 'read'}
instructions[979] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[980] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[981] = {6'd3, 7'd23, 7'd31, 32'd0};//{'dest': 23, 'src': 31, 'op': 'move'}
instructions[982] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[983] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[984] = {6'd3, 7'd41, 7'd23, 32'd0};//{'dest': 41, 'src': 23, 'op': 'move'}
instructions[985] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[986] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[987] = {6'd31, 7'd35, 7'd41, 32'd8};//{'src': 41, 'right': 8, 'dest': 35, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[988] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[989] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[990] = {6'd32, 7'd31, 7'd35, 32'd255};//{'src': 35, 'right': 255, 'dest': 31, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[991] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[992] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[993] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[994] = {6'd8, 7'd33, 7'd32, 32'd22};//{'dest': 33, 'src': 32, 'srcb': 22, 'signed': False, 'op': '+'}
instructions[995] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[996] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[997] = {6'd33, 7'd0, 7'd33, 32'd31};//{'srcb': 31, 'src': 33, 'element_size': 2, 'op': 'memory_write'}
instructions[998] = {6'd3, 7'd31, 7'd21, 32'd0};//{'dest': 31, 'src': 21, 'op': 'move'}
instructions[999] = {6'd13, 7'd21, 7'd21, 32'd1};//{'src': 21, 'right': 1, 'dest': 21, 'signed': False, 'op': '+', 'size': 2}
instructions[1000] = {6'd3, 7'd35, 7'd23, 32'd0};//{'dest': 35, 'src': 23, 'op': 'move'}
instructions[1001] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1002] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1003] = {6'd32, 7'd31, 7'd35, 32'd255};//{'src': 35, 'right': 255, 'dest': 31, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1004] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[1005] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1006] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1007] = {6'd8, 7'd33, 7'd32, 32'd22};//{'dest': 33, 'src': 32, 'srcb': 22, 'signed': False, 'op': '+'}
instructions[1008] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1009] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1010] = {6'd33, 7'd0, 7'd33, 32'd31};//{'srcb': 31, 'src': 33, 'element_size': 2, 'op': 'memory_write'}
instructions[1011] = {6'd3, 7'd31, 7'd21, 32'd0};//{'dest': 31, 'src': 21, 'op': 'move'}
instructions[1012] = {6'd13, 7'd21, 7'd21, 32'd1};//{'src': 21, 'right': 1, 'dest': 21, 'signed': False, 'op': '+', 'size': 2}
instructions[1013] = {6'd3, 7'd32, 7'd20, 32'd0};//{'dest': 32, 'src': 20, 'op': 'move'}
instructions[1014] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1015] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1016] = {6'd13, 7'd31, 7'd32, 32'd2};//{'src': 32, 'right': 2, 'dest': 31, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1017] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1018] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1019] = {6'd3, 7'd20, 7'd31, 32'd0};//{'dest': 20, 'src': 31, 'op': 'move'}
instructions[1020] = {6'd14, 7'd0, 7'd0, 32'd968};//{'label': 968, 'op': 'goto'}
instructions[1021] = {6'd0, 7'd33, 7'd0, 32'd0};//{'dest': 33, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1022] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1023] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1024] = {6'd8, 7'd35, 7'd33, 32'd22};//{'dest': 35, 'src': 33, 'srcb': 22, 'signed': False, 'op': '+'}
instructions[1025] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1026] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1027] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842278024, 'op': 'memory_read_request'}
instructions[1028] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1029] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842278024, 'op': 'memory_read_wait'}
instructions[1030] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842278024, 'element_size': 2, 'op': 'memory_read'}
instructions[1031] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1032] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1033] = {6'd23, 7'd31, 7'd32, 32'd71};//{'src': 32, 'right': 71, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1034] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1035] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1036] = {6'd12, 7'd0, 7'd31, 32'd1050};//{'src': 31, 'label': 1050, 'op': 'jmp_if_false'}
instructions[1037] = {6'd0, 7'd33, 7'd0, 32'd1};//{'dest': 33, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1038] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1039] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1040] = {6'd8, 7'd35, 7'd33, 32'd22};//{'dest': 35, 'src': 33, 'srcb': 22, 'signed': False, 'op': '+'}
instructions[1041] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1042] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1043] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842278312, 'op': 'memory_read_request'}
instructions[1044] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1045] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842278312, 'op': 'memory_read_wait'}
instructions[1046] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842278312, 'element_size': 2, 'op': 'memory_read'}
instructions[1047] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1048] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1049] = {6'd23, 7'd31, 7'd32, 32'd69};//{'src': 32, 'right': 69, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1050] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1051] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1052] = {6'd12, 7'd0, 7'd31, 32'd1066};//{'src': 31, 'label': 1066, 'op': 'jmp_if_false'}
instructions[1053] = {6'd0, 7'd33, 7'd0, 32'd2};//{'dest': 33, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1054] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1055] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1056] = {6'd8, 7'd35, 7'd33, 32'd22};//{'dest': 35, 'src': 33, 'srcb': 22, 'signed': False, 'op': '+'}
instructions[1057] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1058] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1059] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842278672, 'op': 'memory_read_request'}
instructions[1060] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1061] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842278672, 'op': 'memory_read_wait'}
instructions[1062] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842278672, 'element_size': 2, 'op': 'memory_read'}
instructions[1063] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1064] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1065] = {6'd23, 7'd31, 7'd32, 32'd84};//{'src': 32, 'right': 84, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1066] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1067] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1068] = {6'd12, 7'd0, 7'd31, 32'd1082};//{'src': 31, 'label': 1082, 'op': 'jmp_if_false'}
instructions[1069] = {6'd0, 7'd33, 7'd0, 32'd3};//{'dest': 33, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1070] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1071] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1072] = {6'd8, 7'd35, 7'd33, 32'd22};//{'dest': 35, 'src': 33, 'srcb': 22, 'signed': False, 'op': '+'}
instructions[1073] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1074] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1075] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842279032, 'op': 'memory_read_request'}
instructions[1076] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1077] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842279032, 'op': 'memory_read_wait'}
instructions[1078] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842279032, 'element_size': 2, 'op': 'memory_read'}
instructions[1079] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1080] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1081] = {6'd23, 7'd31, 7'd32, 32'd32};//{'src': 32, 'right': 32, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1082] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1083] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1084] = {6'd12, 7'd0, 7'd31, 32'd1098};//{'src': 31, 'label': 1098, 'op': 'jmp_if_false'}
instructions[1085] = {6'd0, 7'd33, 7'd0, 32'd4};//{'dest': 33, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1086] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1087] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1088] = {6'd8, 7'd35, 7'd33, 32'd22};//{'dest': 35, 'src': 33, 'srcb': 22, 'signed': False, 'op': '+'}
instructions[1089] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1090] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1091] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842279392, 'op': 'memory_read_request'}
instructions[1092] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1093] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888842279392, 'op': 'memory_read_wait'}
instructions[1094] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888842279392, 'element_size': 2, 'op': 'memory_read'}
instructions[1095] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1096] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1097] = {6'd23, 7'd31, 7'd32, 32'd47};//{'src': 32, 'right': 47, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1098] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1099] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1100] = {6'd12, 7'd0, 7'd31, 32'd1130};//{'src': 31, 'label': 1130, 'op': 'jmp_if_false'}
instructions[1101] = {6'd0, 7'd33, 7'd0, 32'd5};//{'dest': 33, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1102] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1103] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1104] = {6'd8, 7'd35, 7'd33, 32'd22};//{'dest': 35, 'src': 33, 'srcb': 22, 'signed': False, 'op': '+'}
instructions[1105] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1106] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1107] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888884214744, 'op': 'memory_read_request'}
instructions[1108] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1109] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888884214744, 'op': 'memory_read_wait'}
instructions[1110] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888884214744, 'element_size': 2, 'op': 'memory_read'}
instructions[1111] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1112] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1113] = {6'd23, 7'd31, 7'd32, 32'd63};//{'src': 32, 'right': 63, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1114] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1115] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1116] = {6'd34, 7'd0, 7'd31, 32'd1130};//{'src': 31, 'label': 1130, 'op': 'jmp_if_true'}
instructions[1117] = {6'd0, 7'd33, 7'd0, 32'd5};//{'dest': 33, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1118] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1119] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1120] = {6'd8, 7'd35, 7'd33, 32'd22};//{'dest': 35, 'src': 33, 'srcb': 22, 'signed': False, 'op': '+'}
instructions[1121] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1122] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1123] = {6'd9, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888884215032, 'op': 'memory_read_request'}
instructions[1124] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1125] = {6'd10, 7'd0, 7'd35, 32'd0};//{'element_size': 2, 'src': 35, 'sequence': 139888884215032, 'op': 'memory_read_wait'}
instructions[1126] = {6'd11, 7'd32, 7'd35, 32'd0};//{'dest': 32, 'src': 35, 'sequence': 139888884215032, 'element_size': 2, 'op': 'memory_read'}
instructions[1127] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1128] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1129] = {6'd23, 7'd31, 7'd32, 32'd32};//{'src': 32, 'right': 32, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1130] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1131] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1132] = {6'd12, 7'd0, 7'd31, 32'd1416};//{'src': 31, 'label': 1416, 'op': 'jmp_if_false'}
instructions[1133] = {6'd0, 7'd31, 7'd0, 32'd5};//{'dest': 31, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1134] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1135] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1136] = {6'd3, 7'd26, 7'd31, 32'd0};//{'dest': 26, 'src': 31, 'op': 'move'}
instructions[1137] = {6'd3, 7'd42, 7'd22, 32'd0};//{'dest': 42, 'src': 22, 'op': 'move'}
instructions[1138] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1139] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1140] = {6'd3, 7'd11, 7'd42, 32'd0};//{'dest': 11, 'src': 42, 'op': 'move'}
instructions[1141] = {6'd0, 7'd32, 7'd0, 32'd32};//{'dest': 32, 'literal': 32, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1142] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1143] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1144] = {6'd3, 7'd12, 7'd32, 32'd0};//{'dest': 12, 'src': 32, 'op': 'move'}
instructions[1145] = {6'd3, 7'd32, 7'd26, 32'd0};//{'dest': 32, 'src': 26, 'op': 'move'}
instructions[1146] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1147] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1148] = {6'd3, 7'd13, 7'd32, 32'd0};//{'dest': 13, 'src': 32, 'op': 'move'}
instructions[1149] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[1150] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1151] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1152] = {6'd3, 7'd14, 7'd32, 32'd0};//{'dest': 14, 'src': 32, 'op': 'move'}
instructions[1153] = {6'd1, 7'd9, 7'd0, 32'd832};//{'dest': 9, 'label': 832, 'op': 'jmp_and_link'}
instructions[1154] = {6'd3, 7'd31, 7'd10, 32'd0};//{'dest': 31, 'src': 10, 'op': 'move'}
instructions[1155] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1156] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1157] = {6'd3, 7'd27, 7'd31, 32'd0};//{'dest': 27, 'src': 31, 'op': 'move'}
instructions[1158] = {6'd0, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1159] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1160] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1161] = {6'd3, 7'd25, 7'd31, 32'd0};//{'dest': 25, 'src': 31, 'op': 'move'}
instructions[1162] = {6'd3, 7'd42, 7'd22, 32'd0};//{'dest': 42, 'src': 22, 'op': 'move'}
instructions[1163] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1164] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1165] = {6'd3, 7'd11, 7'd42, 32'd0};//{'dest': 11, 'src': 42, 'op': 'move'}
instructions[1166] = {6'd0, 7'd33, 7'd0, 32'd65};//{'dest': 33, 'literal': 65, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1167] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1168] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1169] = {6'd3, 7'd12, 7'd33, 32'd0};//{'dest': 12, 'src': 33, 'op': 'move'}
instructions[1170] = {6'd3, 7'd33, 7'd26, 32'd0};//{'dest': 33, 'src': 26, 'op': 'move'}
instructions[1171] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1172] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1173] = {6'd3, 7'd13, 7'd33, 32'd0};//{'dest': 13, 'src': 33, 'op': 'move'}
instructions[1174] = {6'd3, 7'd33, 7'd27, 32'd0};//{'dest': 33, 'src': 27, 'op': 'move'}
instructions[1175] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1176] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1177] = {6'd3, 7'd14, 7'd33, 32'd0};//{'dest': 14, 'src': 33, 'op': 'move'}
instructions[1178] = {6'd1, 7'd9, 7'd0, 32'd832};//{'dest': 9, 'label': 832, 'op': 'jmp_and_link'}
instructions[1179] = {6'd3, 7'd32, 7'd10, 32'd0};//{'dest': 32, 'src': 10, 'op': 'move'}
instructions[1180] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1181] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1182] = {6'd35, 7'd31, 7'd32, -32'd1};//{'src': 32, 'right': -1, 'dest': 31, 'signed': True, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1183] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1184] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1185] = {6'd12, 7'd0, 7'd31, 32'd1194};//{'src': 31, 'label': 1194, 'op': 'jmp_if_false'}
instructions[1186] = {6'd3, 7'd32, 7'd25, 32'd0};//{'dest': 32, 'src': 25, 'op': 'move'}
instructions[1187] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1188] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1189] = {6'd18, 7'd31, 7'd32, 32'd1};//{'src': 32, 'right': 1, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1190] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1191] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1192] = {6'd3, 7'd25, 7'd31, 32'd0};//{'dest': 25, 'src': 31, 'op': 'move'}
instructions[1193] = {6'd14, 7'd0, 7'd0, 32'd1194};//{'label': 1194, 'op': 'goto'}
instructions[1194] = {6'd3, 7'd42, 7'd22, 32'd0};//{'dest': 42, 'src': 22, 'op': 'move'}
instructions[1195] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1196] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1197] = {6'd3, 7'd11, 7'd42, 32'd0};//{'dest': 11, 'src': 42, 'op': 'move'}
instructions[1198] = {6'd0, 7'd33, 7'd0, 32'd66};//{'dest': 33, 'literal': 66, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1199] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1200] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1201] = {6'd3, 7'd12, 7'd33, 32'd0};//{'dest': 12, 'src': 33, 'op': 'move'}
instructions[1202] = {6'd3, 7'd33, 7'd26, 32'd0};//{'dest': 33, 'src': 26, 'op': 'move'}
instructions[1203] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1204] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1205] = {6'd3, 7'd13, 7'd33, 32'd0};//{'dest': 13, 'src': 33, 'op': 'move'}
instructions[1206] = {6'd3, 7'd33, 7'd27, 32'd0};//{'dest': 33, 'src': 27, 'op': 'move'}
instructions[1207] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1208] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1209] = {6'd3, 7'd14, 7'd33, 32'd0};//{'dest': 14, 'src': 33, 'op': 'move'}
instructions[1210] = {6'd1, 7'd9, 7'd0, 32'd832};//{'dest': 9, 'label': 832, 'op': 'jmp_and_link'}
instructions[1211] = {6'd3, 7'd32, 7'd10, 32'd0};//{'dest': 32, 'src': 10, 'op': 'move'}
instructions[1212] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1213] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1214] = {6'd35, 7'd31, 7'd32, -32'd1};//{'src': 32, 'right': -1, 'dest': 31, 'signed': True, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1215] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1216] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1217] = {6'd12, 7'd0, 7'd31, 32'd1226};//{'src': 31, 'label': 1226, 'op': 'jmp_if_false'}
instructions[1218] = {6'd3, 7'd32, 7'd25, 32'd0};//{'dest': 32, 'src': 25, 'op': 'move'}
instructions[1219] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1220] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1221] = {6'd18, 7'd31, 7'd32, 32'd2};//{'src': 32, 'right': 2, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1222] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1223] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1224] = {6'd3, 7'd25, 7'd31, 32'd0};//{'dest': 25, 'src': 31, 'op': 'move'}
instructions[1225] = {6'd14, 7'd0, 7'd0, 32'd1226};//{'label': 1226, 'op': 'goto'}
instructions[1226] = {6'd3, 7'd42, 7'd22, 32'd0};//{'dest': 42, 'src': 22, 'op': 'move'}
instructions[1227] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1228] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1229] = {6'd3, 7'd11, 7'd42, 32'd0};//{'dest': 11, 'src': 42, 'op': 'move'}
instructions[1230] = {6'd0, 7'd33, 7'd0, 32'd67};//{'dest': 33, 'literal': 67, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1231] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1232] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1233] = {6'd3, 7'd12, 7'd33, 32'd0};//{'dest': 12, 'src': 33, 'op': 'move'}
instructions[1234] = {6'd3, 7'd33, 7'd26, 32'd0};//{'dest': 33, 'src': 26, 'op': 'move'}
instructions[1235] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1236] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1237] = {6'd3, 7'd13, 7'd33, 32'd0};//{'dest': 13, 'src': 33, 'op': 'move'}
instructions[1238] = {6'd3, 7'd33, 7'd27, 32'd0};//{'dest': 33, 'src': 27, 'op': 'move'}
instructions[1239] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1240] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1241] = {6'd3, 7'd14, 7'd33, 32'd0};//{'dest': 14, 'src': 33, 'op': 'move'}
instructions[1242] = {6'd1, 7'd9, 7'd0, 32'd832};//{'dest': 9, 'label': 832, 'op': 'jmp_and_link'}
instructions[1243] = {6'd3, 7'd32, 7'd10, 32'd0};//{'dest': 32, 'src': 10, 'op': 'move'}
instructions[1244] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1245] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1246] = {6'd35, 7'd31, 7'd32, -32'd1};//{'src': 32, 'right': -1, 'dest': 31, 'signed': True, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1247] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1248] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1249] = {6'd12, 7'd0, 7'd31, 32'd1258};//{'src': 31, 'label': 1258, 'op': 'jmp_if_false'}
instructions[1250] = {6'd3, 7'd32, 7'd25, 32'd0};//{'dest': 32, 'src': 25, 'op': 'move'}
instructions[1251] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1252] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1253] = {6'd18, 7'd31, 7'd32, 32'd4};//{'src': 32, 'right': 4, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1254] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1255] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1256] = {6'd3, 7'd25, 7'd31, 32'd0};//{'dest': 25, 'src': 31, 'op': 'move'}
instructions[1257] = {6'd14, 7'd0, 7'd0, 32'd1258};//{'label': 1258, 'op': 'goto'}
instructions[1258] = {6'd3, 7'd42, 7'd22, 32'd0};//{'dest': 42, 'src': 22, 'op': 'move'}
instructions[1259] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1260] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1261] = {6'd3, 7'd11, 7'd42, 32'd0};//{'dest': 11, 'src': 42, 'op': 'move'}
instructions[1262] = {6'd0, 7'd33, 7'd0, 32'd68};//{'dest': 33, 'literal': 68, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1263] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1264] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1265] = {6'd3, 7'd12, 7'd33, 32'd0};//{'dest': 12, 'src': 33, 'op': 'move'}
instructions[1266] = {6'd3, 7'd33, 7'd26, 32'd0};//{'dest': 33, 'src': 26, 'op': 'move'}
instructions[1267] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1268] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1269] = {6'd3, 7'd13, 7'd33, 32'd0};//{'dest': 13, 'src': 33, 'op': 'move'}
instructions[1270] = {6'd3, 7'd33, 7'd27, 32'd0};//{'dest': 33, 'src': 27, 'op': 'move'}
instructions[1271] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1272] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1273] = {6'd3, 7'd14, 7'd33, 32'd0};//{'dest': 14, 'src': 33, 'op': 'move'}
instructions[1274] = {6'd1, 7'd9, 7'd0, 32'd832};//{'dest': 9, 'label': 832, 'op': 'jmp_and_link'}
instructions[1275] = {6'd3, 7'd32, 7'd10, 32'd0};//{'dest': 32, 'src': 10, 'op': 'move'}
instructions[1276] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1277] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1278] = {6'd35, 7'd31, 7'd32, -32'd1};//{'src': 32, 'right': -1, 'dest': 31, 'signed': True, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1279] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1280] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1281] = {6'd12, 7'd0, 7'd31, 32'd1290};//{'src': 31, 'label': 1290, 'op': 'jmp_if_false'}
instructions[1282] = {6'd3, 7'd32, 7'd25, 32'd0};//{'dest': 32, 'src': 25, 'op': 'move'}
instructions[1283] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1284] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1285] = {6'd18, 7'd31, 7'd32, 32'd8};//{'src': 32, 'right': 8, 'dest': 31, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1286] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1287] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1288] = {6'd3, 7'd25, 7'd31, 32'd0};//{'dest': 25, 'src': 31, 'op': 'move'}
instructions[1289] = {6'd14, 7'd0, 7'd0, 32'd1290};//{'label': 1290, 'op': 'goto'}
instructions[1290] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1291] = {6'd3, 7'd31, 7'd25, 32'd0};//{'dest': 31, 'src': 25, 'op': 'move'}
instructions[1292] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1293] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1294] = {6'd36, 7'd0, 7'd31, 32'd0};//{'src': 31, 'output': 'leds', 'op': 'write'}
instructions[1295] = {6'd37, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'input': 'speed', 'op': 'read'}
instructions[1296] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1297] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1298] = {6'd3, 7'd24, 7'd31, 32'd0};//{'dest': 24, 'src': 31, 'op': 'move'}
instructions[1299] = {6'd3, 7'd43, 7'd28, 32'd0};//{'dest': 43, 'src': 28, 'op': 'move'}
instructions[1300] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1301] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1302] = {6'd3, 7'd11, 7'd43, 32'd0};//{'dest': 11, 'src': 43, 'op': 'move'}
instructions[1303] = {6'd0, 7'd32, 7'd0, 32'd58};//{'dest': 32, 'literal': 58, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1304] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1305] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1306] = {6'd3, 7'd12, 7'd32, 32'd0};//{'dest': 12, 'src': 32, 'op': 'move'}
instructions[1307] = {6'd0, 7'd32, 7'd0, 32'd0};//{'dest': 32, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1308] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1309] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1310] = {6'd3, 7'd13, 7'd32, 32'd0};//{'dest': 13, 'src': 32, 'op': 'move'}
instructions[1311] = {6'd0, 7'd32, 7'd0, 32'd1460};//{'dest': 32, 'literal': 1460, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1312] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1313] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1314] = {6'd3, 7'd14, 7'd32, 32'd0};//{'dest': 14, 'src': 32, 'op': 'move'}
instructions[1315] = {6'd1, 7'd9, 7'd0, 32'd832};//{'dest': 9, 'label': 832, 'op': 'jmp_and_link'}
instructions[1316] = {6'd3, 7'd31, 7'd10, 32'd0};//{'dest': 31, 'src': 10, 'op': 'move'}
instructions[1317] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1318] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1319] = {6'd3, 7'd21, 7'd31, 32'd0};//{'dest': 21, 'src': 31, 'op': 'move'}
instructions[1320] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1321] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1322] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[1323] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1324] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1325] = {6'd13, 7'd31, 7'd32, 32'd4};//{'src': 32, 'right': 4, 'dest': 31, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1326] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1327] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1328] = {6'd3, 7'd21, 7'd31, 32'd0};//{'dest': 21, 'src': 31, 'op': 'move'}
instructions[1329] = {6'd3, 7'd32, 7'd24, 32'd0};//{'dest': 32, 'src': 24, 'op': 'move'}
instructions[1330] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1331] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1332] = {6'd23, 7'd31, 7'd32, 32'd0};//{'src': 32, 'right': 0, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1333] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1334] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1335] = {6'd12, 7'd0, 7'd31, 32'd1356};//{'src': 31, 'label': 1356, 'op': 'jmp_if_false'}
instructions[1336] = {6'd0, 7'd31, 7'd0, 32'd32};//{'dest': 31, 'literal': 32, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1337] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[1338] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1339] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1340] = {6'd38, 7'd33, 7'd32, 32'd28};//{'dest': 33, 'src': 32, 'srcb': 28, 'signed': True, 'op': '+'}
instructions[1341] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1342] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1343] = {6'd33, 7'd0, 7'd33, 32'd31};//{'srcb': 31, 'src': 33, 'element_size': 2, 'op': 'memory_write'}
instructions[1344] = {6'd3, 7'd31, 7'd21, 32'd0};//{'dest': 31, 'src': 21, 'op': 'move'}
instructions[1345] = {6'd13, 7'd21, 7'd21, 32'd1};//{'src': 21, 'right': 1, 'dest': 21, 'signed': False, 'op': '+', 'size': 2}
instructions[1346] = {6'd0, 7'd31, 7'd0, 32'd32};//{'dest': 31, 'literal': 32, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1347] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1348] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[1349] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1350] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1351] = {6'd38, 7'd33, 7'd32, 32'd28};//{'dest': 33, 'src': 32, 'srcb': 28, 'signed': True, 'op': '+'}
instructions[1352] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1353] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1354] = {6'd33, 7'd0, 7'd33, 32'd31};//{'srcb': 31, 'src': 33, 'element_size': 2, 'op': 'memory_write'}
instructions[1355] = {6'd14, 7'd0, 7'd0, 32'd1356};//{'label': 1356, 'op': 'goto'}
instructions[1356] = {6'd3, 7'd32, 7'd24, 32'd0};//{'dest': 32, 'src': 24, 'op': 'move'}
instructions[1357] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1358] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1359] = {6'd23, 7'd31, 7'd32, 32'd1};//{'src': 32, 'right': 1, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1360] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1361] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1362] = {6'd12, 7'd0, 7'd31, 32'd1383};//{'src': 31, 'label': 1383, 'op': 'jmp_if_false'}
instructions[1363] = {6'd0, 7'd31, 7'd0, 32'd48};//{'dest': 31, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1364] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[1365] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1366] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1367] = {6'd38, 7'd33, 7'd32, 32'd28};//{'dest': 33, 'src': 32, 'srcb': 28, 'signed': True, 'op': '+'}
instructions[1368] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1369] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1370] = {6'd33, 7'd0, 7'd33, 32'd31};//{'srcb': 31, 'src': 33, 'element_size': 2, 'op': 'memory_write'}
instructions[1371] = {6'd3, 7'd31, 7'd21, 32'd0};//{'dest': 31, 'src': 21, 'op': 'move'}
instructions[1372] = {6'd13, 7'd21, 7'd21, 32'd1};//{'src': 21, 'right': 1, 'dest': 21, 'signed': False, 'op': '+', 'size': 2}
instructions[1373] = {6'd0, 7'd31, 7'd0, 32'd32};//{'dest': 31, 'literal': 32, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1374] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1375] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[1376] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1377] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1378] = {6'd38, 7'd33, 7'd32, 32'd28};//{'dest': 33, 'src': 32, 'srcb': 28, 'signed': True, 'op': '+'}
instructions[1379] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1380] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1381] = {6'd33, 7'd0, 7'd33, 32'd31};//{'srcb': 31, 'src': 33, 'element_size': 2, 'op': 'memory_write'}
instructions[1382] = {6'd14, 7'd0, 7'd0, 32'd1383};//{'label': 1383, 'op': 'goto'}
instructions[1383] = {6'd3, 7'd32, 7'd24, 32'd0};//{'dest': 32, 'src': 24, 'op': 'move'}
instructions[1384] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1385] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1386] = {6'd23, 7'd31, 7'd32, 32'd2};//{'src': 32, 'right': 2, 'dest': 31, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1387] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1388] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1389] = {6'd12, 7'd0, 7'd31, 32'd1410};//{'src': 31, 'label': 1410, 'op': 'jmp_if_false'}
instructions[1390] = {6'd0, 7'd31, 7'd0, 32'd48};//{'dest': 31, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1391] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[1392] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1393] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1394] = {6'd38, 7'd33, 7'd32, 32'd28};//{'dest': 33, 'src': 32, 'srcb': 28, 'signed': True, 'op': '+'}
instructions[1395] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1396] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1397] = {6'd33, 7'd0, 7'd33, 32'd31};//{'srcb': 31, 'src': 33, 'element_size': 2, 'op': 'memory_write'}
instructions[1398] = {6'd3, 7'd31, 7'd21, 32'd0};//{'dest': 31, 'src': 21, 'op': 'move'}
instructions[1399] = {6'd13, 7'd21, 7'd21, 32'd1};//{'src': 21, 'right': 1, 'dest': 21, 'signed': False, 'op': '+', 'size': 2}
instructions[1400] = {6'd0, 7'd31, 7'd0, 32'd48};//{'dest': 31, 'literal': 48, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1401] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1402] = {6'd3, 7'd32, 7'd21, 32'd0};//{'dest': 32, 'src': 21, 'op': 'move'}
instructions[1403] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1404] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1405] = {6'd38, 7'd33, 7'd32, 32'd28};//{'dest': 33, 'src': 32, 'srcb': 28, 'signed': True, 'op': '+'}
instructions[1406] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1407] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1408] = {6'd33, 7'd0, 7'd33, 32'd31};//{'srcb': 31, 'src': 33, 'element_size': 2, 'op': 'memory_write'}
instructions[1409] = {6'd14, 7'd0, 7'd0, 32'd1410};//{'label': 1410, 'op': 'goto'}
instructions[1410] = {6'd3, 7'd43, 7'd28, 32'd0};//{'dest': 43, 'src': 28, 'op': 'move'}
instructions[1411] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1412] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1413] = {6'd3, 7'd1, 7'd43, 32'd0};//{'dest': 1, 'src': 43, 'op': 'move'}
instructions[1414] = {6'd1, 7'd0, 7'd0, 32'd609};//{'dest': 0, 'label': 609, 'op': 'jmp_and_link'}
instructions[1415] = {6'd14, 7'd0, 7'd0, 32'd1417};//{'label': 1417, 'op': 'goto'}
instructions[1416] = {6'd1, 7'd73, 7'd0, 32'd571};//{'dest': 73, 'label': 571, 'op': 'jmp_and_link'}
instructions[1417] = {6'd14, 7'd0, 7'd0, 32'd956};//{'label': 956, 'op': 'goto'}
instructions[1418] = {6'd39, 7'd31, 7'd0, 32'd0};//{'dest': 31, 'input': 'rs232_rx', 'op': 'read'}
instructions[1419] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1420] = {6'd4, 7'd0, 7'd0, 32'd0};//{'op': 'nop'}
instructions[1421] = {6'd3, 7'd21, 7'd31, 32'd0};//{'dest': 21, 'src': 31, 'op': 'move'}
instructions[1422] = {6'd6, 7'd0, 7'd18, 32'd0};//{'src': 18, 'op': 'jmp_to_reg'}
end
//////////////////////////////////////////////////////////////////////////////
// CPU IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a CPU implementing the C process.
always @(posedge clk)
begin
//implement memory for 2 byte x n arrays
if (memory_enable_2 == 1'b1) begin
memory_2[address_2] <= data_in_2;
end
data_out_2 <= memory_2[address_2];
memory_enable_2 <= 1'b0;
write_enable_2 <= 0;
//stage 0 instruction fetch
if (stage_0_enable) begin
stage_1_enable <= 1;
instruction_0 <= instructions[program_counter];
opcode_0 = instruction_0[51:46];
dest_0 = instruction_0[45:39];
src_0 = instruction_0[38:32];
srcb_0 = instruction_0[6:0];
literal_0 = instruction_0[31:0];
if(write_enable_2) begin
registers[dest_2] <= result_2;
end
program_counter_0 <= program_counter;
program_counter <= program_counter + 1;
end
//stage 1 opcode fetch
if (stage_1_enable) begin
stage_2_enable <= 1;
register_1 <= registers[src_0];
registerb_1 <= registers[srcb_0];
dest_1 <= dest_0;
literal_1 <= literal_0;
opcode_1 <= opcode_0;
program_counter_1 <= program_counter_0;
end
//stage 2 opcode fetch
if (stage_2_enable) begin
dest_2 <= dest_1;
case(opcode_1)
16'd0:
begin
result_2 <= literal_1;
write_enable_2 <= 1;
end
16'd1:
begin
program_counter <= literal_1;
result_2 <= program_counter_1 + 1;
write_enable_2 <= 1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd2:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd3:
begin
result_2 <= register_1;
write_enable_2 <= 1;
end
16'd5:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_socket_stb <= 1'b1;
s_output_socket <= register_1;
end
16'd6:
begin
program_counter <= register_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd7:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_rs232_tx_stb <= 1'b1;
s_output_rs232_tx <= register_1;
end
16'd8:
begin
result_2 <= $unsigned(register_1) + $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd9:
begin
address_2 <= register_1;
end
16'd11:
begin
result_2 <= data_out_2;
write_enable_2 <= 1;
end
16'd12:
begin
if (register_1 == 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd13:
begin
result_2 <= $unsigned(register_1) + $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd14:
begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd15:
begin
result_2 <= $unsigned(register_1) >= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd16:
begin
result_2 <= $unsigned(register_1) - $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd17:
begin
result_2 <= $unsigned(register_1) | $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd18:
begin
result_2 <= $unsigned(register_1) | $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd19:
begin
result_2 <= $signed(register_1) >= $signed(literal_1);
write_enable_2 <= 1;
end
16'd20:
begin
result_2 <= $signed(literal_1) - $signed(register_1);
write_enable_2 <= 1;
end
16'd21:
begin
result_2 <= $signed(register_1) << $signed(literal_1);
write_enable_2 <= 1;
end
16'd22:
begin
result_2 <= $signed(register_1) & $signed(literal_1);
write_enable_2 <= 1;
end
16'd23:
begin
result_2 <= $unsigned(register_1) == $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd24:
begin
result_2 <= $unsigned(literal_1) | $unsigned(register_1);
write_enable_2 <= 1;
end
16'd25:
begin
result_2 <= $unsigned(register_1) > $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd26:
begin
result_2 <= $unsigned(register_1) < $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd27:
begin
result_2 <= $unsigned(register_1) < $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd28:
begin
result_2 <= $unsigned(register_1) == $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd29:
begin
result_2 <= $signed(register_1) + $signed(literal_1);
write_enable_2 <= 1;
end
16'd30:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_socket_ack <= 1'b1;
end
16'd31:
begin
result_2 <= $unsigned(register_1) >> $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd32:
begin
result_2 <= $unsigned(register_1) & $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd33:
begin
address_2 <= register_1;
data_in_2 <= registerb_1;
memory_enable_2 <= 1'b1;
end
16'd34:
begin
if (register_1 != 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd35:
begin
result_2 <= $signed(register_1) != $signed(literal_1);
write_enable_2 <= 1;
end
16'd36:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_leds_stb <= 1'b1;
s_output_leds <= register_1;
end
16'd37:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_speed_ack <= 1'b1;
end
16'd38:
begin
result_2 <= $signed(register_1) + $signed(registerb_1);
write_enable_2 <= 1;
end
16'd39:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_rs232_rx_ack <= 1'b1;
end
endcase
end
if (s_output_socket_stb == 1'b1 && output_socket_ack == 1'b1) begin
s_output_socket_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_rs232_tx_stb == 1'b1 && output_rs232_tx_ack == 1'b1) begin
s_output_rs232_tx_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_socket_ack == 1'b1 && input_socket_stb == 1'b1) begin
result_2 <= input_socket;
write_enable_2 <= 1;
s_input_socket_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_leds_stb == 1'b1 && output_leds_ack == 1'b1) begin
s_output_leds_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_speed_ack == 1'b1 && input_speed_stb == 1'b1) begin
result_2 <= input_speed;
write_enable_2 <= 1;
s_input_speed_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_rs232_rx_ack == 1'b1 && input_rs232_rx_stb == 1'b1) begin
result_2 <= input_rs232_rx;
write_enable_2 <= 1;
s_input_rs232_rx_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (timer == 0) begin
if (timer_enable) begin
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
timer_enable <= 0;
end
end else begin
timer <= timer - 1;
end
if (rst == 1'b1) begin
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
timer <= 0;
timer_enable <= 0;
program_counter <= 0;
s_input_speed_ack <= 0;
s_input_socket_ack <= 0;
s_input_rs232_rx_ack <= 0;
s_output_rs232_tx_stb <= 0;
s_output_leds_stb <= 0;
s_output_socket_stb <= 0;
end
end
assign input_speed_ack = s_input_speed_ack;
assign input_socket_ack = s_input_socket_ack;
assign input_rs232_rx_ack = s_input_rs232_rx_ack;
assign output_rs232_tx_stb = s_output_rs232_tx_stb;
assign output_rs232_tx = s_output_rs232_tx;
assign output_leds_stb = s_output_leds_stb;
assign output_leds = s_output_leds;
assign output_socket_stb = s_output_socket_stb;
assign output_socket = s_output_socket;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_2_V
`define SKY130_FD_SC_HDLL__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2 (
VPWR,
VGND,
Y ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_FUNCTIONAL_PP_V |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Wed Apr 30 22:30:36 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_adc/clk_adc_stub.v
// Design : clk_adc
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_adc(clk_in1_p, clk_in1_n, clk_250Mhz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1_p,clk_in1_n,clk_250Mhz,locked" */;
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_clk (
clk_in_p,
clk_in_n,
clk);
parameter BUFTYPE = 0;
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
input clk_in_p;
input clk_in_n;
output clk;
// wires
wire clk_ibuf_s;
// instantiations
IBUFGDS i_rx_clk_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_ibuf_s));
generate
if (BUFTYPE == VIRTEX6) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_ibuf_s),
.O (clk));
end else begin
BUFG i_clk_gbuf (
.I (clk_ibuf_s),
.O (clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:43:25 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_xbar_1/system_xbar_1_sim_netlist.v
// Design : system_xbar_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_xbar_1,axi_crossbar_v2_1_12_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_xbar_1
(aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI AWADDR [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI AWADDR [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI AWADDR [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI AWADDR [31:0] [351:320], xilinx.com:interface:aximm:1.0 M11_AXI AWADDR [31:0] [383:352], xilinx.com:interface:aximm:1.0 M12_AXI AWADDR [31:0] [415:384], xilinx.com:interface:aximm:1.0 M13_AXI AWADDR [31:0] [447:416]" *) output [447:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI AWPROT [2:0] [23:21], xilinx.com:interface:aximm:1.0 M08_AXI AWPROT [2:0] [26:24], xilinx.com:interface:aximm:1.0 M09_AXI AWPROT [2:0] [29:27], xilinx.com:interface:aximm:1.0 M10_AXI AWPROT [2:0] [32:30], xilinx.com:interface:aximm:1.0 M11_AXI AWPROT [2:0] [35:33], xilinx.com:interface:aximm:1.0 M12_AXI AWPROT [2:0] [38:36], xilinx.com:interface:aximm:1.0 M13_AXI AWPROT [2:0] [41:39]" *) output [41:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI AWVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI AWVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI AWVALID [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI AWVALID [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI AWVALID [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI AWVALID [0:0] [13:13]" *) output [13:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI AWREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI AWREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI AWREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI AWREADY [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI AWREADY [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI AWREADY [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI AWREADY [0:0] [13:13]" *) input [13:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI WDATA [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI WDATA [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI WDATA [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI WDATA [31:0] [351:320], xilinx.com:interface:aximm:1.0 M11_AXI WDATA [31:0] [383:352], xilinx.com:interface:aximm:1.0 M12_AXI WDATA [31:0] [415:384], xilinx.com:interface:aximm:1.0 M13_AXI WDATA [31:0] [447:416]" *) output [447:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24], xilinx.com:interface:aximm:1.0 M07_AXI WSTRB [3:0] [31:28], xilinx.com:interface:aximm:1.0 M08_AXI WSTRB [3:0] [35:32], xilinx.com:interface:aximm:1.0 M09_AXI WSTRB [3:0] [39:36], xilinx.com:interface:aximm:1.0 M10_AXI WSTRB [3:0] [43:40], xilinx.com:interface:aximm:1.0 M11_AXI WSTRB [3:0] [47:44], xilinx.com:interface:aximm:1.0 M12_AXI WSTRB [3:0] [51:48], xilinx.com:interface:aximm:1.0 M13_AXI WSTRB [3:0] [55:52]" *) output [55:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI WVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI WVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI WVALID [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI WVALID [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI WVALID [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI WVALID [0:0] [13:13]" *) output [13:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI WREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI WREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI WREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI WREADY [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI WREADY [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI WREADY [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI WREADY [0:0] [13:13]" *) input [13:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI BRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0 M08_AXI BRESP [1:0] [17:16], xilinx.com:interface:aximm:1.0 M09_AXI BRESP [1:0] [19:18], xilinx.com:interface:aximm:1.0 M10_AXI BRESP [1:0] [21:20], xilinx.com:interface:aximm:1.0 M11_AXI BRESP [1:0] [23:22], xilinx.com:interface:aximm:1.0 M12_AXI BRESP [1:0] [25:24], xilinx.com:interface:aximm:1.0 M13_AXI BRESP [1:0] [27:26]" *) input [27:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI BVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI BVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI BVALID [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI BVALID [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI BVALID [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI BVALID [0:0] [13:13]" *) input [13:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI BREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI BREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI BREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI BREADY [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI BREADY [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI BREADY [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI BREADY [0:0] [13:13]" *) output [13:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI ARADDR [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI ARADDR [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI ARADDR [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI ARADDR [31:0] [351:320], xilinx.com:interface:aximm:1.0 M11_AXI ARADDR [31:0] [383:352], xilinx.com:interface:aximm:1.0 M12_AXI ARADDR [31:0] [415:384], xilinx.com:interface:aximm:1.0 M13_AXI ARADDR [31:0] [447:416]" *) output [447:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18], xilinx.com:interface:aximm:1.0 M07_AXI ARPROT [2:0] [23:21], xilinx.com:interface:aximm:1.0 M08_AXI ARPROT [2:0] [26:24], xilinx.com:interface:aximm:1.0 M09_AXI ARPROT [2:0] [29:27], xilinx.com:interface:aximm:1.0 M10_AXI ARPROT [2:0] [32:30], xilinx.com:interface:aximm:1.0 M11_AXI ARPROT [2:0] [35:33], xilinx.com:interface:aximm:1.0 M12_AXI ARPROT [2:0] [38:36], xilinx.com:interface:aximm:1.0 M13_AXI ARPROT [2:0] [41:39]" *) output [41:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI ARVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI ARVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI ARVALID [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI ARVALID [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI ARVALID [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI ARVALID [0:0] [13:13]" *) output [13:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI ARREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI ARREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI ARREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI ARREADY [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI ARREADY [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI ARREADY [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI ARREADY [0:0] [13:13]" *) input [13:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192], xilinx.com:interface:aximm:1.0 M07_AXI RDATA [31:0] [255:224], xilinx.com:interface:aximm:1.0 M08_AXI RDATA [31:0] [287:256], xilinx.com:interface:aximm:1.0 M09_AXI RDATA [31:0] [319:288], xilinx.com:interface:aximm:1.0 M10_AXI RDATA [31:0] [351:320], xilinx.com:interface:aximm:1.0 M11_AXI RDATA [31:0] [383:352], xilinx.com:interface:aximm:1.0 M12_AXI RDATA [31:0] [415:384], xilinx.com:interface:aximm:1.0 M13_AXI RDATA [31:0] [447:416]" *) input [447:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12], xilinx.com:interface:aximm:1.0 M07_AXI RRESP [1:0] [15:14], xilinx.com:interface:aximm:1.0 M08_AXI RRESP [1:0] [17:16], xilinx.com:interface:aximm:1.0 M09_AXI RRESP [1:0] [19:18], xilinx.com:interface:aximm:1.0 M10_AXI RRESP [1:0] [21:20], xilinx.com:interface:aximm:1.0 M11_AXI RRESP [1:0] [23:22], xilinx.com:interface:aximm:1.0 M12_AXI RRESP [1:0] [25:24], xilinx.com:interface:aximm:1.0 M13_AXI RRESP [1:0] [27:26]" *) input [27:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RVALID [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI RVALID [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI RVALID [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI RVALID [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI RVALID [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI RVALID [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI RVALID [0:0] [13:13]" *) input [13:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6], xilinx.com:interface:aximm:1.0 M07_AXI RREADY [0:0] [7:7], xilinx.com:interface:aximm:1.0 M08_AXI RREADY [0:0] [8:8], xilinx.com:interface:aximm:1.0 M09_AXI RREADY [0:0] [9:9], xilinx.com:interface:aximm:1.0 M10_AXI RREADY [0:0] [10:10], xilinx.com:interface:aximm:1.0 M11_AXI RREADY [0:0] [11:11], xilinx.com:interface:aximm:1.0 M12_AXI RREADY [0:0] [12:12], xilinx.com:interface:aximm:1.0 M13_AXI RREADY [0:0] [13:13]" *) output [13:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [447:0]m_axi_araddr;
wire [41:0]m_axi_arprot;
wire [13:0]m_axi_arready;
wire [13:0]m_axi_arvalid;
wire [447:0]m_axi_awaddr;
wire [41:0]m_axi_awprot;
wire [13:0]m_axi_awready;
wire [13:0]m_axi_awvalid;
wire [13:0]m_axi_bready;
wire [27:0]m_axi_bresp;
wire [13:0]m_axi_bvalid;
wire [447:0]m_axi_rdata;
wire [13:0]m_axi_rready;
wire [27:0]m_axi_rresp;
wire [13:0]m_axi_rvalid;
wire [447:0]m_axi_wdata;
wire [13:0]m_axi_wready;
wire [55:0]m_axi_wstrb;
wire [13:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [27:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [55:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [111:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [55:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [55:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [41:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [27:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [55:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [111:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [55:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [55:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [41:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_wlast_UNCONNECTED;
wire [13:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rlast_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "0" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "artix7" *)
(* C_M_AXI_ADDR_WIDTH = "448'b0000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "896'b00000000000000000000000000000000010001001010001000000000000000000000000000000000000000000000000001000000000001000000000000000000000000000000000000000000000000000100000000000011000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000001000000000000100000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000100000000000000000000000000000000000000000000000000000000100010010100001000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000011000000000000000000000000000000000000000000000000000000100000111000000000000000000000000000000000000000000000000000000010000001110000000000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_READ_ISSUING = "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_SECURE = "448'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_WRITE_ISSUING = "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "14" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *)
(* C_S_AXI_THREAD_ID_WIDTH = "0" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "artix7" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "448'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "14'b11111111111111" *)
(* P_M_AXI_SUPPORTS_WRITE = "14'b11111111111111" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[27:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[55:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[13:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[111:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[13:0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[55:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[55:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[41:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[13:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[27:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[55:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[13:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[111:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[13:0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[55:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[55:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[41:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[13:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[13:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED[13:0]),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[13:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(s_axi_arready),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED[0]),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b1),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_addr_arbiter_sasd" *)
module system_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_sasd
(m_valid_i,
reset,
aa_grant_rnw,
\m_ready_d_reg[0] ,
\m_atarget_enc_reg[0] ,
\m_atarget_enc_reg[1] ,
\m_atarget_enc_reg[2] ,
\m_atarget_enc_reg[3] ,
D,
Q,
\m_atarget_enc_reg[1]_rep ,
\m_atarget_enc_reg[0]_rep ,
\m_ready_d_reg[2] ,
\m_ready_d_reg[2]_0 ,
\m_ready_d_reg[1] ,
s_axi_bvalid,
\m_ready_d_reg[0]_0 ,
\m_ready_d_reg[0]_1 ,
m_axi_bready,
s_axi_wready,
m_axi_wvalid,
\gen_axilite.s_axi_bvalid_i_reg ,
m_axi_awvalid,
\gen_axilite.s_axi_bvalid_i_reg_0 ,
m_valid_i_reg,
E,
s_ready_i_reg,
\gen_axilite.s_axi_rvalid_i_reg ,
m_axi_arvalid,
\m_ready_d_reg[0]_2 ,
s_axi_awready,
s_axi_arready,
s_axi_rvalid,
\gen_axilite.s_axi_bvalid_i_reg_1 ,
aclk,
aresetn_d,
\m_ready_d_reg[0]_3 ,
s_axi_wvalid,
m_ready_d,
\m_atarget_enc_reg[3]_0 ,
\m_atarget_enc_reg[2]_0 ,
\m_atarget_enc_reg[2]_1 ,
\m_atarget_enc_reg[0]_0 ,
\m_atarget_enc_reg[2]_2 ,
m_axi_bvalid,
\m_atarget_enc_reg[2]_3 ,
\m_atarget_enc_reg[2]_4 ,
\m_atarget_enc_reg[3]_1 ,
\m_atarget_enc_reg[2]_5 ,
\m_atarget_hot_reg[14] ,
s_axi_bready,
m_atarget_enc,
\m_atarget_enc_reg[1]_0 ,
m_axi_wready,
\m_atarget_enc_reg[3]_2 ,
m_axi_rvalid,
m_ready_d_0,
s_axi_rready,
sr_rvalid,
\m_atarget_enc_reg[2]_6 ,
\m_atarget_enc_reg[2]_7 ,
\m_atarget_enc_reg[2]_8 ,
m_valid_i_reg_0,
s_axi_arprot,
s_axi_arvalid,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr,
mi_wready,
mi_bvalid,
s_axi_awvalid);
output m_valid_i;
output reset;
output aa_grant_rnw;
output \m_ready_d_reg[0] ;
output \m_atarget_enc_reg[0] ;
output \m_atarget_enc_reg[1] ;
output \m_atarget_enc_reg[2] ;
output \m_atarget_enc_reg[3] ;
output [13:0]D;
output [34:0]Q;
output \m_atarget_enc_reg[1]_rep ;
output \m_atarget_enc_reg[0]_rep ;
output \m_ready_d_reg[2] ;
output \m_ready_d_reg[2]_0 ;
output \m_ready_d_reg[1] ;
output [0:0]s_axi_bvalid;
output \m_ready_d_reg[0]_0 ;
output \m_ready_d_reg[0]_1 ;
output [12:0]m_axi_bready;
output [0:0]s_axi_wready;
output [12:0]m_axi_wvalid;
output \gen_axilite.s_axi_bvalid_i_reg ;
output [12:0]m_axi_awvalid;
output \gen_axilite.s_axi_bvalid_i_reg_0 ;
output m_valid_i_reg;
output [0:0]E;
output s_ready_i_reg;
output \gen_axilite.s_axi_rvalid_i_reg ;
output [12:0]m_axi_arvalid;
output \m_ready_d_reg[0]_2 ;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
output \gen_axilite.s_axi_bvalid_i_reg_1 ;
input aclk;
input aresetn_d;
input \m_ready_d_reg[0]_3 ;
input [0:0]s_axi_wvalid;
input [2:0]m_ready_d;
input \m_atarget_enc_reg[3]_0 ;
input \m_atarget_enc_reg[2]_0 ;
input \m_atarget_enc_reg[2]_1 ;
input \m_atarget_enc_reg[0]_0 ;
input \m_atarget_enc_reg[2]_2 ;
input [1:0]m_axi_bvalid;
input \m_atarget_enc_reg[2]_3 ;
input \m_atarget_enc_reg[2]_4 ;
input \m_atarget_enc_reg[3]_1 ;
input \m_atarget_enc_reg[2]_5 ;
input [13:0]\m_atarget_hot_reg[14] ;
input [0:0]s_axi_bready;
input [3:0]m_atarget_enc;
input \m_atarget_enc_reg[1]_0 ;
input [6:0]m_axi_wready;
input \m_atarget_enc_reg[3]_2 ;
input [0:0]m_axi_rvalid;
input [1:0]m_ready_d_0;
input [0:0]s_axi_rready;
input sr_rvalid;
input \m_atarget_enc_reg[2]_6 ;
input \m_atarget_enc_reg[2]_7 ;
input \m_atarget_enc_reg[2]_8 ;
input m_valid_i_reg_0;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
input [0:0]mi_wready;
input [0:0]mi_bvalid;
input [0:0]s_axi_awvalid;
wire [13:0]D;
wire [0:0]E;
wire [34:0]Q;
wire aa_grant_any;
wire aa_grant_rnw;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_bvalid_i_i_2_n_0 ;
wire \gen_axilite.s_axi_bvalid_i_reg ;
wire \gen_axilite.s_axi_bvalid_i_reg_0 ;
wire \gen_axilite.s_axi_bvalid_i_reg_1 ;
wire \gen_axilite.s_axi_rvalid_i_reg ;
wire \gen_no_arbiter.grant_rnw_i_1_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_2_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_4_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_5_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_6_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
wire [3:0]m_atarget_enc;
wire \m_atarget_enc[0]_i_2_n_0 ;
wire \m_atarget_enc[3]_i_2_n_0 ;
wire \m_atarget_enc[3]_i_3_n_0 ;
wire \m_atarget_enc[3]_i_4_n_0 ;
wire \m_atarget_enc_reg[0] ;
wire \m_atarget_enc_reg[0]_0 ;
wire \m_atarget_enc_reg[0]_rep ;
wire \m_atarget_enc_reg[1] ;
wire \m_atarget_enc_reg[1]_0 ;
wire \m_atarget_enc_reg[1]_rep ;
wire \m_atarget_enc_reg[2] ;
wire \m_atarget_enc_reg[2]_0 ;
wire \m_atarget_enc_reg[2]_1 ;
wire \m_atarget_enc_reg[2]_2 ;
wire \m_atarget_enc_reg[2]_3 ;
wire \m_atarget_enc_reg[2]_4 ;
wire \m_atarget_enc_reg[2]_5 ;
wire \m_atarget_enc_reg[2]_6 ;
wire \m_atarget_enc_reg[2]_7 ;
wire \m_atarget_enc_reg[2]_8 ;
wire \m_atarget_enc_reg[3] ;
wire \m_atarget_enc_reg[3]_0 ;
wire \m_atarget_enc_reg[3]_1 ;
wire \m_atarget_enc_reg[3]_2 ;
wire \m_atarget_hot[0]_i_2_n_0 ;
wire \m_atarget_hot[0]_i_3_n_0 ;
wire \m_atarget_hot[11]_i_2_n_0 ;
wire \m_atarget_hot[11]_i_3_n_0 ;
wire \m_atarget_hot[11]_i_4_n_0 ;
wire \m_atarget_hot[12]_i_2_n_0 ;
wire \m_atarget_hot[13]_i_2_n_0 ;
wire \m_atarget_hot[14]_i_2_n_0 ;
wire \m_atarget_hot[14]_i_3_n_0 ;
wire \m_atarget_hot[14]_i_4_n_0 ;
wire \m_atarget_hot[14]_i_5_n_0 ;
wire \m_atarget_hot[1]_i_2_n_0 ;
wire \m_atarget_hot[2]_i_2_n_0 ;
wire \m_atarget_hot[2]_i_3_n_0 ;
wire \m_atarget_hot[3]_i_2_n_0 ;
wire \m_atarget_hot[3]_i_3_n_0 ;
wire \m_atarget_hot[4]_i_2_n_0 ;
wire \m_atarget_hot[4]_i_3_n_0 ;
wire \m_atarget_hot[5]_i_2_n_0 ;
wire \m_atarget_hot[6]_i_2_n_0 ;
wire \m_atarget_hot[6]_i_3_n_0 ;
wire \m_atarget_hot[6]_i_4_n_0 ;
wire \m_atarget_hot[7]_i_2_n_0 ;
wire \m_atarget_hot[8]_i_2_n_0 ;
wire \m_atarget_hot[9]_i_2_n_0 ;
wire [13:0]\m_atarget_hot_reg[14] ;
wire [12:0]m_axi_arvalid;
wire [12:0]m_axi_awvalid;
wire [12:0]m_axi_bready;
wire [1:0]m_axi_bvalid;
wire [0:0]m_axi_rvalid;
wire [6:0]m_axi_wready;
wire [12:0]m_axi_wvalid;
wire [2:0]m_ready_d;
wire \m_ready_d[0]_i_4_n_0 ;
wire [1:0]m_ready_d_0;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[0]_1 ;
wire \m_ready_d_reg[0]_2 ;
wire \m_ready_d_reg[0]_3 ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[2] ;
wire \m_ready_d_reg[2]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire [0:0]mi_bvalid;
wire [0:0]mi_wready;
wire p_0_in1_in;
wire reset;
wire [48:1]s_amesg;
wire \s_arvalid_reg[0]_i_1_n_0 ;
wire \s_arvalid_reg_reg_n_0_[0] ;
wire s_awvalid_reg;
wire \s_awvalid_reg[0]_i_1_n_0 ;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wready;
wire \s_axi_wready[0]_INST_0_i_2_n_0 ;
wire \s_axi_wready[0]_INST_0_i_3_n_0 ;
wire \s_axi_wready[0]_INST_0_i_4_n_0 ;
wire [0:0]s_axi_wvalid;
wire s_ready_i;
wire s_ready_i_reg;
wire [1:1]\splitter_aw/m_ready_d0 ;
wire sr_rvalid;
LUT6 #(
.INIT(64'h5050F0F05C50F0F0))
\gen_axilite.s_axi_bvalid_i_i_1
(.I0(\gen_axilite.s_axi_bvalid_i_i_2_n_0 ),
.I1(mi_wready),
.I2(mi_bvalid),
.I3(\gen_axilite.s_axi_bvalid_i_reg ),
.I4(\m_atarget_hot_reg[14] [13]),
.I5(\gen_axilite.s_axi_bvalid_i_reg_0 ),
.O(\gen_axilite.s_axi_bvalid_i_reg_1 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0020))
\gen_axilite.s_axi_bvalid_i_i_2
(.I0(s_axi_bready),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[0]),
.O(\gen_axilite.s_axi_bvalid_i_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h0020))
\gen_axilite.s_axi_bvalid_i_i_3
(.I0(s_axi_wvalid),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[1]),
.O(\gen_axilite.s_axi_bvalid_i_reg ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hFB))
\gen_axilite.s_axi_bvalid_i_i_4
(.I0(m_ready_d[2]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.O(\gen_axilite.s_axi_bvalid_i_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hBF))
\gen_axilite.s_axi_rvalid_i_i_2
(.I0(m_ready_d_0[1]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.O(\gen_axilite.s_axi_rvalid_i_reg ));
LUT6 #(
.INIT(64'hFFFFFF5300000050))
\gen_no_arbiter.grant_rnw_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.I3(aa_grant_any),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(\gen_no_arbiter.grant_rnw_i_1_n_0 ));
FDRE \gen_no_arbiter.grant_rnw_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.grant_rnw_i_1_n_0 ),
.Q(aa_grant_rnw),
.R(reset));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[10]_i_1
(.I0(s_axi_araddr[9]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[9]),
.O(s_amesg[10]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[11]_i_1
(.I0(s_axi_araddr[10]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[10]),
.O(s_amesg[11]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[12]_i_1
(.I0(s_axi_araddr[11]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[11]),
.O(s_amesg[12]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[13]_i_1
(.I0(s_axi_araddr[12]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[12]),
.O(s_amesg[13]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[14]_i_1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[13]),
.O(s_amesg[14]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[15]_i_1
(.I0(s_axi_araddr[14]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[14]),
.O(s_amesg[15]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[16]_i_1
(.I0(s_axi_araddr[15]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[15]),
.O(s_amesg[16]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[17]_i_1
(.I0(s_axi_araddr[16]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[16]),
.O(s_amesg[17]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[18]_i_1
(.I0(s_axi_araddr[17]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[17]),
.O(s_amesg[18]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[19]_i_1
(.I0(s_axi_araddr[18]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[18]),
.O(s_amesg[19]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[1]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[0]),
.O(s_amesg[1]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[20]_i_1
(.I0(s_axi_araddr[19]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[19]),
.O(s_amesg[20]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[21]_i_1
(.I0(s_axi_araddr[20]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[20]),
.O(s_amesg[21]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[22]_i_1
(.I0(s_axi_araddr[21]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[21]),
.O(s_amesg[22]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[23]_i_1
(.I0(s_axi_araddr[22]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[22]),
.O(s_amesg[23]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[24]_i_1
(.I0(s_axi_araddr[23]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[23]),
.O(s_amesg[24]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[25]_i_1
(.I0(s_axi_araddr[24]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[24]),
.O(s_amesg[25]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[26]_i_1
(.I0(s_axi_araddr[25]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[25]),
.O(s_amesg[26]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[27]_i_1
(.I0(s_axi_araddr[26]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[26]),
.O(s_amesg[27]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[28]_i_1
(.I0(s_axi_araddr[27]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[27]),
.O(s_amesg[28]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[29]_i_1
(.I0(s_axi_araddr[28]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[28]),
.O(s_amesg[29]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[2]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[1]),
.O(s_amesg[2]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[30]_i_1
(.I0(s_axi_araddr[29]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[29]),
.O(s_amesg[30]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[31]_i_1
(.I0(s_axi_araddr[30]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[30]),
.O(s_amesg[31]));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[32]_i_1
(.I0(aresetn_d),
.O(reset));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[32]_i_2
(.I0(aa_grant_any),
.O(p_0_in1_in));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[32]_i_3
(.I0(s_axi_araddr[31]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[31]),
.O(s_amesg[32]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[3]_i_1
(.I0(s_axi_araddr[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[2]),
.O(s_amesg[3]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[46]_i_1
(.I0(s_axi_arprot[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[0]),
.O(s_amesg[46]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[47]_i_1
(.I0(s_axi_arprot[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[1]),
.O(s_amesg[47]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[48]_i_1
(.I0(s_axi_arprot[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[2]),
.O(s_amesg[48]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[4]_i_1
(.I0(s_axi_araddr[3]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[3]),
.O(s_amesg[4]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[5]_i_1
(.I0(s_axi_araddr[4]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[4]),
.O(s_amesg[5]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[6]_i_1
(.I0(s_axi_araddr[5]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[5]),
.O(s_amesg[6]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[7]_i_1
(.I0(s_axi_araddr[6]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[6]),
.O(s_amesg[7]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[8]_i_1
(.I0(s_axi_araddr[7]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[7]),
.O(s_amesg[8]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[9]_i_1
(.I0(s_axi_araddr[8]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[8]),
.O(s_amesg[9]));
FDRE \gen_no_arbiter.m_amesg_i_reg[10]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[10]),
.Q(Q[9]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[11]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[11]),
.Q(Q[10]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[12]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[12]),
.Q(Q[11]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[13]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[13]),
.Q(Q[12]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[14]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[14]),
.Q(Q[13]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[15]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[15]),
.Q(Q[14]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[16]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[16]),
.Q(Q[15]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[17]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[17]),
.Q(Q[16]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[18]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[18]),
.Q(Q[17]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[19]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[19]),
.Q(Q[18]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[1]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[1]),
.Q(Q[0]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[20]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[20]),
.Q(Q[19]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[21]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[21]),
.Q(Q[20]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[22]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[22]),
.Q(Q[21]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[23]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[23]),
.Q(Q[22]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[24]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[24]),
.Q(Q[23]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[25]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[25]),
.Q(Q[24]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[26]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[26]),
.Q(Q[25]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[27]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[27]),
.Q(Q[26]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[28]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[28]),
.Q(Q[27]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[29]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[29]),
.Q(Q[28]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[2]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[2]),
.Q(Q[1]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[30]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[30]),
.Q(Q[29]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[31]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[31]),
.Q(Q[30]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[32]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[32]),
.Q(Q[31]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[3]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[3]),
.Q(Q[2]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[46]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[46]),
.Q(Q[32]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[47]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[47]),
.Q(Q[33]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[48]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[48]),
.Q(Q[34]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[4]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[4]),
.Q(Q[3]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[5]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[5]),
.Q(Q[4]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[6]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[6]),
.Q(Q[5]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[7]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[7]),
.Q(Q[6]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[8]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[8]),
.Q(Q[7]),
.R(reset));
FDRE \gen_no_arbiter.m_amesg_i_reg[9]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[9]),
.Q(Q[8]),
.R(reset));
LUT6 #(
.INIT(64'h00000000DDDC0000))
\gen_no_arbiter.m_grant_hot_i[0]_i_1
(.I0(m_valid_i),
.I1(aa_grant_any),
.I2(s_axi_arvalid),
.I3(s_axi_awvalid),
.I4(aresetn_d),
.I5(\gen_no_arbiter.m_valid_i_i_2_n_0 ),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
FDRE \gen_no_arbiter.m_grant_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
.Q(aa_grant_any),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'h4E))
\gen_no_arbiter.m_valid_i_i_1
(.I0(m_valid_i),
.I1(aa_grant_any),
.I2(\gen_no_arbiter.m_valid_i_i_2_n_0 ),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF02000000020000))
\gen_no_arbiter.m_valid_i_i_2
(.I0(\splitter_aw/m_ready_d0 ),
.I1(\m_ready_d_reg[0]_3 ),
.I2(\m_ready_d_reg[2] ),
.I3(aa_grant_rnw),
.I4(m_valid_i),
.I5(\m_ready_d[0]_i_4_n_0 ),
.O(\gen_no_arbiter.m_valid_i_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF47FF44FF00FF00))
\gen_no_arbiter.m_valid_i_i_3
(.I0(\gen_no_arbiter.m_valid_i_i_4_n_0 ),
.I1(m_atarget_enc[0]),
.I2(\gen_no_arbiter.m_valid_i_i_5_n_0 ),
.I3(m_ready_d[1]),
.I4(\m_atarget_enc_reg[1]_0 ),
.I5(s_axi_wvalid),
.O(\splitter_aw/m_ready_d0 ));
LUT6 #(
.INIT(64'hFFFFAE00FFFFAEFF))
\gen_no_arbiter.m_valid_i_i_4
(.I0(\gen_no_arbiter.m_valid_i_i_6_n_0 ),
.I1(m_atarget_enc[3]),
.I2(m_axi_wready[5]),
.I3(m_atarget_enc[1]),
.I4(\s_axi_wready[0]_INST_0_i_4_n_0 ),
.I5(\s_axi_wready[0]_INST_0_i_3_n_0 ),
.O(\gen_no_arbiter.m_valid_i_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'hB))
\gen_no_arbiter.m_valid_i_i_5
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.O(\gen_no_arbiter.m_valid_i_i_5_n_0 ));
LUT4 #(
.INIT(16'hC4C7))
\gen_no_arbiter.m_valid_i_i_6
(.I0(m_axi_wready[3]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_axi_wready[1]),
.O(\gen_no_arbiter.m_valid_i_i_6_n_0 ));
FDRE \gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(m_valid_i),
.R(reset));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h40))
\gen_no_arbiter.s_ready_i[0]_i_1
(.I0(m_valid_i),
.I1(aa_grant_any),
.I2(aresetn_d),
.O(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
FDRE \gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
.Q(s_ready_i),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFEFFFF))
\m_atarget_enc[0]_i_1
(.I0(\m_atarget_hot[13]_i_2_n_0 ),
.I1(\m_atarget_hot[5]_i_2_n_0 ),
.I2(\m_atarget_hot[9]_i_2_n_0 ),
.I3(\m_atarget_hot[1]_i_2_n_0 ),
.I4(\m_atarget_enc[0]_i_2_n_0 ),
.O(\m_atarget_enc_reg[0] ));
LUT6 #(
.INIT(64'h5545555555555545))
\m_atarget_enc[0]_i_2
(.I0(\m_atarget_hot[3]_i_2_n_0 ),
.I1(\m_atarget_hot[11]_i_3_n_0 ),
.I2(\m_atarget_hot[11]_i_4_n_0 ),
.I3(\m_atarget_hot[14]_i_5_n_0 ),
.I4(Q[17]),
.I5(Q[16]),
.O(\m_atarget_enc[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFEFFFF))
\m_atarget_enc[0]_rep_i_1
(.I0(\m_atarget_hot[13]_i_2_n_0 ),
.I1(\m_atarget_hot[5]_i_2_n_0 ),
.I2(\m_atarget_hot[9]_i_2_n_0 ),
.I3(\m_atarget_hot[1]_i_2_n_0 ),
.I4(\m_atarget_enc[0]_i_2_n_0 ),
.O(\m_atarget_enc_reg[0]_rep ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hBBBF))
\m_atarget_enc[1]_i_1
(.I0(\m_atarget_hot[6]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_2_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_4_n_0 ),
.O(\m_atarget_enc_reg[1] ));
LUT4 #(
.INIT(16'hBBBF))
\m_atarget_enc[1]_rep_i_1
(.I0(\m_atarget_hot[6]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_2_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_4_n_0 ),
.O(\m_atarget_enc_reg[1]_rep ));
LUT5 #(
.INIT(32'hFFEEFFFE))
\m_atarget_enc[2]_i_1
(.I0(\m_atarget_hot[7]_i_2_n_0 ),
.I1(\m_atarget_hot[5]_i_2_n_0 ),
.I2(\m_atarget_hot[14]_i_2_n_0 ),
.I3(\m_atarget_hot[14]_i_3_n_0 ),
.I4(\m_atarget_hot[14]_i_4_n_0 ),
.O(\m_atarget_enc_reg[2] ));
LUT6 #(
.INIT(64'hFFFFFFFFEEEEEEFE))
\m_atarget_enc[3]_i_1
(.I0(\m_atarget_hot[11]_i_2_n_0 ),
.I1(\m_atarget_enc[3]_i_2_n_0 ),
.I2(\m_atarget_hot[14]_i_2_n_0 ),
.I3(\m_atarget_hot[14]_i_3_n_0 ),
.I4(\m_atarget_enc[3]_i_3_n_0 ),
.I5(\m_atarget_enc[3]_i_4_n_0 ),
.O(\m_atarget_enc_reg[3] ));
LUT6 #(
.INIT(64'hFFFFFFFF00100000))
\m_atarget_enc[3]_i_2
(.I0(Q[16]),
.I1(Q[17]),
.I2(Q[18]),
.I3(Q[19]),
.I4(\m_atarget_hot[8]_i_2_n_0 ),
.I5(\m_atarget_hot[13]_i_2_n_0 ),
.O(\m_atarget_enc[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hFE))
\m_atarget_enc[3]_i_3
(.I0(\m_atarget_hot[0]_i_2_n_0 ),
.I1(\m_atarget_hot[5]_i_2_n_0 ),
.I2(\m_atarget_hot[1]_i_2_n_0 ),
.O(\m_atarget_enc[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h01100000))
\m_atarget_enc[3]_i_4
(.I0(Q[19]),
.I1(Q[18]),
.I2(Q[17]),
.I3(Q[16]),
.I4(\m_atarget_hot[8]_i_2_n_0 ),
.O(\m_atarget_enc[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_hot[0]_i_1
(.I0(\m_atarget_hot[0]_i_2_n_0 ),
.I1(aa_grant_any),
.O(D[0]));
LUT6 #(
.INIT(64'h0000000000000002))
\m_atarget_hot[0]_i_2
(.I0(\m_atarget_hot[11]_i_4_n_0 ),
.I1(\m_atarget_hot[0]_i_3_n_0 ),
.I2(Q[16]),
.I3(Q[17]),
.I4(Q[19]),
.I5(Q[18]),
.O(\m_atarget_hot[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFFF))
\m_atarget_hot[0]_i_3
(.I0(Q[23]),
.I1(Q[20]),
.I2(Q[21]),
.I3(Q[24]),
.I4(Q[25]),
.I5(Q[22]),
.O(\m_atarget_hot[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA8AA0000))
\m_atarget_hot[11]_i_1
(.I0(\m_atarget_hot[11]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_4_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[10]));
LUT6 #(
.INIT(64'h0000004000000000))
\m_atarget_hot[11]_i_2
(.I0(\m_atarget_hot[11]_i_3_n_0 ),
.I1(\m_atarget_hot[11]_i_4_n_0 ),
.I2(Q[16]),
.I3(Q[18]),
.I4(Q[19]),
.I5(Q[17]),
.O(\m_atarget_hot[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\m_atarget_hot[11]_i_3
(.I0(Q[25]),
.I1(Q[22]),
.I2(Q[24]),
.I3(Q[21]),
.I4(Q[20]),
.I5(Q[23]),
.O(\m_atarget_hot[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\m_atarget_hot[11]_i_4
(.I0(Q[27]),
.I1(Q[30]),
.I2(Q[26]),
.I3(Q[29]),
.I4(Q[28]),
.I5(Q[31]),
.O(\m_atarget_hot[11]_i_4_n_0 ));
LUT5 #(
.INIT(32'hA8AA0000))
\m_atarget_hot[12]_i_1
(.I0(\m_atarget_hot[12]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_4_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00000020))
\m_atarget_hot[12]_i_2
(.I0(\m_atarget_hot[8]_i_2_n_0 ),
.I1(Q[19]),
.I2(Q[18]),
.I3(Q[17]),
.I4(Q[16]),
.O(\m_atarget_hot[12]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hA8AA0000))
\m_atarget_hot[13]_i_1
(.I0(\m_atarget_hot[13]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_4_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00000004))
\m_atarget_hot[13]_i_2
(.I0(Q[16]),
.I1(Q[17]),
.I2(Q[18]),
.I3(Q[19]),
.I4(\m_atarget_hot[4]_i_2_n_0 ),
.O(\m_atarget_hot[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0008))
\m_atarget_hot[14]_i_1
(.I0(aa_grant_any),
.I1(\m_atarget_hot[14]_i_2_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_4_n_0 ),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h2))
\m_atarget_hot[14]_i_2
(.I0(\m_atarget_enc[0]_i_2_n_0 ),
.I1(\m_atarget_hot[2]_i_2_n_0 ),
.O(\m_atarget_hot[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFAAAB))
\m_atarget_hot[14]_i_3
(.I0(\m_atarget_hot[12]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_5_n_0 ),
.I2(Q[16]),
.I3(\m_atarget_hot[4]_i_2_n_0 ),
.I4(\m_atarget_hot[6]_i_2_n_0 ),
.O(\m_atarget_hot[14]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFFFE))
\m_atarget_hot[14]_i_4
(.I0(\m_atarget_enc[3]_i_4_n_0 ),
.I1(\m_atarget_hot[1]_i_2_n_0 ),
.I2(\m_atarget_hot[5]_i_2_n_0 ),
.I3(\m_atarget_hot[0]_i_2_n_0 ),
.O(\m_atarget_hot[14]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'hE))
\m_atarget_hot[14]_i_5
(.I0(Q[18]),
.I1(Q[19]),
.O(\m_atarget_hot[14]_i_5_n_0 ));
LUT5 #(
.INIT(32'hA8AA0000))
\m_atarget_hot[1]_i_1
(.I0(\m_atarget_hot[1]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_4_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[1]));
LUT6 #(
.INIT(64'h0000000000000800))
\m_atarget_hot[1]_i_2
(.I0(\m_atarget_hot[11]_i_4_n_0 ),
.I1(Q[22]),
.I2(Q[25]),
.I3(Q[21]),
.I4(Q[24]),
.I5(\m_atarget_hot[2]_i_3_n_0 ),
.O(\m_atarget_hot[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_hot[2]_i_1
(.I0(\m_atarget_hot[2]_i_2_n_0 ),
.I1(aa_grant_any),
.O(D[2]));
LUT6 #(
.INIT(64'h0000000000400000))
\m_atarget_hot[2]_i_2
(.I0(Q[21]),
.I1(\m_atarget_hot[11]_i_4_n_0 ),
.I2(Q[22]),
.I3(Q[25]),
.I4(Q[24]),
.I5(\m_atarget_hot[2]_i_3_n_0 ),
.O(\m_atarget_hot[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFD))
\m_atarget_hot[2]_i_3
(.I0(Q[23]),
.I1(Q[20]),
.I2(Q[18]),
.I3(Q[19]),
.I4(Q[17]),
.I5(Q[16]),
.O(\m_atarget_hot[2]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA8AA0000))
\m_atarget_hot[3]_i_1
(.I0(\m_atarget_hot[3]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_4_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[3]));
LUT5 #(
.INIT(32'h00000002))
\m_atarget_hot[3]_i_2
(.I0(\m_atarget_hot[11]_i_4_n_0 ),
.I1(Q[23]),
.I2(Q[20]),
.I3(\m_atarget_hot[3]_i_3_n_0 ),
.I4(\m_atarget_hot[6]_i_4_n_0 ),
.O(\m_atarget_hot[3]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFDF))
\m_atarget_hot[3]_i_3
(.I0(Q[22]),
.I1(Q[25]),
.I2(Q[21]),
.I3(Q[24]),
.O(\m_atarget_hot[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000100000000))
\m_atarget_hot[4]_i_1
(.I0(Q[18]),
.I1(Q[19]),
.I2(Q[17]),
.I3(Q[16]),
.I4(\m_atarget_hot[4]_i_2_n_0 ),
.I5(aa_grant_any),
.O(D[4]));
LUT6 #(
.INIT(64'hFFFFFFFFFBFFFFFF))
\m_atarget_hot[4]_i_2
(.I0(\m_atarget_hot[6]_i_3_n_0 ),
.I1(Q[30]),
.I2(Q[27]),
.I3(Q[26]),
.I4(Q[21]),
.I5(\m_atarget_hot[4]_i_3_n_0 ),
.O(\m_atarget_hot[4]_i_2_n_0 ));
LUT3 #(
.INIT(8'hFE))
\m_atarget_hot[4]_i_3
(.I0(Q[31]),
.I1(Q[28]),
.I2(Q[29]),
.O(\m_atarget_hot[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA8AA0000))
\m_atarget_hot[5]_i_1
(.I0(\m_atarget_hot[5]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_4_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00000100))
\m_atarget_hot[5]_i_2
(.I0(\m_atarget_hot[4]_i_2_n_0 ),
.I1(Q[19]),
.I2(Q[18]),
.I3(Q[16]),
.I4(Q[17]),
.O(\m_atarget_hot[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hA8AA0000))
\m_atarget_hot[6]_i_1
(.I0(\m_atarget_hot[6]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_4_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0004))
\m_atarget_hot[6]_i_2
(.I0(Q[21]),
.I1(\m_atarget_hot[11]_i_4_n_0 ),
.I2(\m_atarget_hot[6]_i_3_n_0 ),
.I3(\m_atarget_hot[6]_i_4_n_0 ),
.O(\m_atarget_hot[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFD))
\m_atarget_hot[6]_i_3
(.I0(Q[23]),
.I1(Q[20]),
.I2(Q[25]),
.I3(Q[22]),
.I4(Q[24]),
.O(\m_atarget_hot[6]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hFFFE))
\m_atarget_hot[6]_i_4
(.I0(Q[16]),
.I1(Q[17]),
.I2(Q[19]),
.I3(Q[18]),
.O(\m_atarget_hot[6]_i_4_n_0 ));
LUT5 #(
.INIT(32'hA8AA0000))
\m_atarget_hot[7]_i_1
(.I0(\m_atarget_hot[7]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_4_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000002))
\m_atarget_hot[7]_i_2
(.I0(\m_atarget_hot[8]_i_2_n_0 ),
.I1(Q[18]),
.I2(Q[19]),
.I3(Q[17]),
.I4(Q[16]),
.O(\m_atarget_hot[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000020000000000))
\m_atarget_hot[8]_i_1
(.I0(\m_atarget_hot[8]_i_2_n_0 ),
.I1(Q[19]),
.I2(Q[18]),
.I3(Q[16]),
.I4(Q[17]),
.I5(aa_grant_any),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h2))
\m_atarget_hot[8]_i_2
(.I0(\m_atarget_hot[11]_i_4_n_0 ),
.I1(\m_atarget_hot[11]_i_3_n_0 ),
.O(\m_atarget_hot[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'hA8AA0000))
\m_atarget_hot[9]_i_1
(.I0(\m_atarget_hot[9]_i_2_n_0 ),
.I1(\m_atarget_hot[14]_i_4_n_0 ),
.I2(\m_atarget_hot[14]_i_3_n_0 ),
.I3(\m_atarget_hot[14]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000020))
\m_atarget_hot[9]_i_2
(.I0(\m_atarget_hot[8]_i_2_n_0 ),
.I1(Q[16]),
.I2(Q[17]),
.I3(Q[18]),
.I4(Q[19]),
.O(\m_atarget_hot[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[14] [0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[11]_INST_0
(.I0(\m_atarget_hot_reg[14] [10]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[10]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[12]_INST_0
(.I0(\m_atarget_hot_reg[14] [11]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[11]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[13]_INST_0
(.I0(\m_atarget_hot_reg[14] [12]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[12]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[14] [1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[2]_INST_0
(.I0(\m_atarget_hot_reg[14] [2]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[3]_INST_0
(.I0(\m_atarget_hot_reg[14] [3]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[3]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[4]_INST_0
(.I0(\m_atarget_hot_reg[14] [4]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[4]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[5]_INST_0
(.I0(\m_atarget_hot_reg[14] [5]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[5]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[6]_INST_0
(.I0(\m_atarget_hot_reg[14] [6]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[6]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[7]_INST_0
(.I0(\m_atarget_hot_reg[14] [7]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[7]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[8]_INST_0
(.I0(\m_atarget_hot_reg[14] [8]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[8]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[9]_INST_0
(.I0(\m_atarget_hot_reg[14] [9]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[1]),
.O(m_axi_arvalid[9]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[14] [0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[11]_INST_0
(.I0(\m_atarget_hot_reg[14] [10]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[10]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[12]_INST_0
(.I0(\m_atarget_hot_reg[14] [11]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[11]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[13]_INST_0
(.I0(\m_atarget_hot_reg[14] [12]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[12]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[14] [1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[2]_INST_0
(.I0(\m_atarget_hot_reg[14] [2]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[3]_INST_0
(.I0(\m_atarget_hot_reg[14] [3]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[3]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[4]_INST_0
(.I0(\m_atarget_hot_reg[14] [4]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[4]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[5]_INST_0
(.I0(\m_atarget_hot_reg[14] [5]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[5]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[6]_INST_0
(.I0(\m_atarget_hot_reg[14] [6]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[6]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[7]_INST_0
(.I0(\m_atarget_hot_reg[14] [7]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[7]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[8]_INST_0
(.I0(\m_atarget_hot_reg[14] [8]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[8]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[9]_INST_0
(.I0(\m_atarget_hot_reg[14] [9]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d[2]),
.O(m_axi_awvalid[9]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[0]_INST_0
(.I0(\m_atarget_hot_reg[14] [0]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[0]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[11]_INST_0
(.I0(\m_atarget_hot_reg[14] [10]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[10]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[12]_INST_0
(.I0(\m_atarget_hot_reg[14] [11]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[11]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[13]_INST_0
(.I0(\m_atarget_hot_reg[14] [12]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[12]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[1]_INST_0
(.I0(\m_atarget_hot_reg[14] [1]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[1]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[2]_INST_0
(.I0(\m_atarget_hot_reg[14] [2]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[2]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[3]_INST_0
(.I0(\m_atarget_hot_reg[14] [3]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[3]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[4]_INST_0
(.I0(\m_atarget_hot_reg[14] [4]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[4]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[5]_INST_0
(.I0(\m_atarget_hot_reg[14] [5]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[5]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[6]_INST_0
(.I0(\m_atarget_hot_reg[14] [6]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[6]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[7]_INST_0
(.I0(\m_atarget_hot_reg[14] [7]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[7]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[8]_INST_0
(.I0(\m_atarget_hot_reg[14] [8]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[8]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[9]_INST_0
(.I0(\m_atarget_hot_reg[14] [9]),
.I1(m_ready_d[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[9]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[14] [0]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[11]_INST_0
(.I0(\m_atarget_hot_reg[14] [10]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[10]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[12]_INST_0
(.I0(\m_atarget_hot_reg[14] [11]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[11]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[13]_INST_0
(.I0(\m_atarget_hot_reg[14] [12]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[12]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[14] [1]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[1]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[2]_INST_0
(.I0(\m_atarget_hot_reg[14] [2]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[2]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[3]_INST_0
(.I0(\m_atarget_hot_reg[14] [3]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[3]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[4]_INST_0
(.I0(\m_atarget_hot_reg[14] [4]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[4]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[5]_INST_0
(.I0(\m_atarget_hot_reg[14] [5]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[5]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[6]_INST_0
(.I0(\m_atarget_hot_reg[14] [6]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[6]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[7]_INST_0
(.I0(\m_atarget_hot_reg[14] [7]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[7]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[8]_INST_0
(.I0(\m_atarget_hot_reg[14] [8]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00200000))
\m_axi_wvalid[9]_INST_0
(.I0(\m_atarget_hot_reg[14] [9]),
.I1(m_ready_d[1]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_wvalid),
.O(m_axi_wvalid[9]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h0080FFFF))
\m_payload_i[34]_i_1
(.I0(s_axi_rready),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[0]),
.I4(sr_rvalid),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h7))
\m_ready_d[0]_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.O(\m_ready_d_reg[0]_2 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'hB))
\m_ready_d[0]_i_3
(.I0(\m_ready_d[0]_i_4_n_0 ),
.I1(aresetn_d),
.O(\m_ready_d_reg[0] ));
LUT6 #(
.INIT(64'h00000000FFFF0010))
\m_ready_d[0]_i_4
(.I0(\gen_axilite.s_axi_rvalid_i_reg ),
.I1(\m_atarget_enc_reg[2]_6 ),
.I2(\m_atarget_enc_reg[2]_7 ),
.I3(\m_atarget_enc_reg[2]_8 ),
.I4(m_ready_d_0[1]),
.I5(m_valid_i_reg_0),
.O(\m_ready_d[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5555554555555555))
\m_ready_d[2]_i_2
(.I0(m_ready_d[2]),
.I1(\m_atarget_enc_reg[3]_0 ),
.I2(\m_atarget_enc_reg[2]_0 ),
.I3(\m_atarget_enc_reg[2]_1 ),
.I4(aa_grant_rnw),
.I5(m_valid_i),
.O(\m_ready_d_reg[2] ));
LUT5 #(
.INIT(32'h000000F2))
\m_ready_d[2]_i_3
(.I0(s_axi_wvalid),
.I1(\m_ready_d_reg[1] ),
.I2(m_ready_d[1]),
.I3(\m_ready_d_reg[0]_3 ),
.I4(\m_ready_d_reg[2] ),
.O(\m_ready_d_reg[2]_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h8AAAAAAA))
m_valid_i_i_3
(.I0(sr_rvalid),
.I1(m_ready_d_0[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_rready),
.O(s_ready_i_reg));
LUT6 #(
.INIT(64'hFFABFFFFFFFFFFFF))
m_valid_i_i_5
(.I0(\m_atarget_enc_reg[3]_2 ),
.I1(m_axi_rvalid),
.I2(\m_atarget_enc_reg[2]_5 ),
.I3(m_ready_d_0[0]),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(m_valid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0040))
\s_arvalid_reg[0]_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_arvalid),
.I2(aresetn_d),
.I3(s_ready_i),
.O(\s_arvalid_reg[0]_i_1_n_0 ));
FDRE \s_arvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_arvalid_reg[0]_i_1_n_0 ),
.Q(\s_arvalid_reg_reg_n_0_[0] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000D00000))
\s_awvalid_reg[0]_i_1
(.I0(s_axi_arvalid),
.I1(s_awvalid_reg),
.I2(s_axi_awvalid),
.I3(\s_arvalid_reg_reg_n_0_[0] ),
.I4(aresetn_d),
.I5(s_ready_i),
.O(\s_awvalid_reg[0]_i_1_n_0 ));
FDRE \s_awvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_awvalid_reg[0]_i_1_n_0 ),
.Q(s_awvalid_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h8))
\s_axi_arready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_arready));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h2))
\s_axi_awready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_awready));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h2))
\s_axi_bvalid[0]_INST_0
(.I0(aa_grant_any),
.I1(\m_ready_d_reg[0]_0 ),
.O(s_axi_bvalid));
LUT6 #(
.INIT(64'hFFFFFFFFAAAABABB))
\s_axi_bvalid[0]_INST_0_i_1
(.I0(\m_ready_d_reg[0]_1 ),
.I1(\m_atarget_enc_reg[0]_0 ),
.I2(\m_atarget_enc_reg[2]_2 ),
.I3(m_axi_bvalid[1]),
.I4(\m_atarget_enc_reg[2]_3 ),
.I5(\m_atarget_enc_reg[2]_4 ),
.O(\m_ready_d_reg[0]_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFABFFFF))
\s_axi_bvalid[0]_INST_0_i_2
(.I0(\m_atarget_enc_reg[3]_1 ),
.I1(m_axi_bvalid[0]),
.I2(\m_atarget_enc_reg[2]_5 ),
.I3(m_ready_d[0]),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(\m_ready_d_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[0]_INST_0
(.I0(aa_grant_any),
.I1(sr_rvalid),
.O(s_axi_rvalid));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h2))
\s_axi_wready[0]_INST_0
(.I0(aa_grant_any),
.I1(\m_ready_d_reg[1] ),
.O(s_axi_wready));
LUT6 #(
.INIT(64'hBBFF8B00BBFF8BFF))
\s_axi_wready[0]_INST_0_i_1
(.I0(\s_axi_wready[0]_INST_0_i_2_n_0 ),
.I1(m_atarget_enc[1]),
.I2(\s_axi_wready[0]_INST_0_i_3_n_0 ),
.I3(m_atarget_enc[0]),
.I4(\s_axi_wready[0]_INST_0_i_4_n_0 ),
.I5(\m_atarget_enc_reg[1]_0 ),
.O(\m_ready_d_reg[1] ));
LUT6 #(
.INIT(64'hFFFFFFFFCC1DFF1D))
\s_axi_wready[0]_INST_0_i_2
(.I0(m_axi_wready[1]),
.I1(m_atarget_enc[2]),
.I2(m_axi_wready[3]),
.I3(m_atarget_enc[3]),
.I4(m_axi_wready[5]),
.I5(\s_axi_wready[0]_INST_0_i_4_n_0 ),
.O(\s_axi_wready[0]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_wready[0]_INST_0_i_3
(.I0(m_axi_wready[6]),
.I1(m_axi_wready[2]),
.I2(m_atarget_enc[2]),
.I3(m_axi_wready[4]),
.I4(m_atarget_enc[3]),
.I5(m_axi_wready[0]),
.O(\s_axi_wready[0]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hFB))
\s_axi_wready[0]_INST_0_i_4
(.I0(m_ready_d[1]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.O(\s_axi_wready[0]_INST_0_i_4_n_0 ));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_PROTOCOL = "2" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *)
(* C_FAMILY = "artix7" *) (* C_M_AXI_ADDR_WIDTH = "448'b0000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *) (* C_M_AXI_BASE_ADDR = "896'b00000000000000000000000000000000010001001010001000000000000000000000000000000000000000000000000001000000000001000000000000000000000000000000000000000000000000000100000000000011000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000001000000000000100000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000100000000000000000000000000000000000000000000000000000000100010010100001000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000011000000000000000000000000000000000000000000000000000000100000111000000000000000000000000000000000000000000000000000000010000001110000000000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "448'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "14" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "0" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_crossbar_v2_1_12_axi_crossbar" *) (* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *) (* P_FAMILY = "artix7" *) (* P_INCR = "2'b01" *)
(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "448'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "14'b11111111111111" *) (* P_M_AXI_SUPPORTS_WRITE = "14'b11111111111111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *) (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
module system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [0:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wuser;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [13:0]m_axi_awid;
output [447:0]m_axi_awaddr;
output [111:0]m_axi_awlen;
output [41:0]m_axi_awsize;
output [27:0]m_axi_awburst;
output [13:0]m_axi_awlock;
output [55:0]m_axi_awcache;
output [41:0]m_axi_awprot;
output [55:0]m_axi_awregion;
output [55:0]m_axi_awqos;
output [13:0]m_axi_awuser;
output [13:0]m_axi_awvalid;
input [13:0]m_axi_awready;
output [13:0]m_axi_wid;
output [447:0]m_axi_wdata;
output [55:0]m_axi_wstrb;
output [13:0]m_axi_wlast;
output [13:0]m_axi_wuser;
output [13:0]m_axi_wvalid;
input [13:0]m_axi_wready;
input [13:0]m_axi_bid;
input [27:0]m_axi_bresp;
input [13:0]m_axi_buser;
input [13:0]m_axi_bvalid;
output [13:0]m_axi_bready;
output [13:0]m_axi_arid;
output [447:0]m_axi_araddr;
output [111:0]m_axi_arlen;
output [41:0]m_axi_arsize;
output [27:0]m_axi_arburst;
output [13:0]m_axi_arlock;
output [55:0]m_axi_arcache;
output [41:0]m_axi_arprot;
output [55:0]m_axi_arregion;
output [55:0]m_axi_arqos;
output [13:0]m_axi_aruser;
output [13:0]m_axi_arvalid;
input [13:0]m_axi_arready;
input [13:0]m_axi_rid;
input [447:0]m_axi_rdata;
input [27:0]m_axi_rresp;
input [13:0]m_axi_rlast;
input [13:0]m_axi_ruser;
input [13:0]m_axi_rvalid;
output [13:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [15:0]\^m_axi_araddr ;
wire [2:0]\^m_axi_arprot ;
wire [13:0]m_axi_arready;
wire [13:0]\^m_axi_arvalid ;
wire [447:432]\^m_axi_awaddr ;
wire [13:0]m_axi_awready;
wire [13:0]\^m_axi_awvalid ;
wire [13:0]\^m_axi_bready ;
wire [27:0]m_axi_bresp;
wire [13:0]m_axi_bvalid;
wire [447:0]m_axi_rdata;
wire [13:0]\^m_axi_rready ;
wire [27:0]m_axi_rresp;
wire [13:0]m_axi_rvalid;
wire [13:0]m_axi_wready;
wire [13:0]\^m_axi_wvalid ;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
assign m_axi_araddr[447:432] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[431:416] = \^m_axi_araddr [15:0];
assign m_axi_araddr[415:400] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[399:384] = \^m_axi_araddr [15:0];
assign m_axi_araddr[383:368] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[367:352] = \^m_axi_araddr [15:0];
assign m_axi_araddr[351:336] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[335:320] = \^m_axi_araddr [15:0];
assign m_axi_araddr[319:304] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[303:288] = \^m_axi_araddr [15:0];
assign m_axi_araddr[287:272] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[271:256] = \^m_axi_araddr [15:0];
assign m_axi_araddr[255:240] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[239:224] = \^m_axi_araddr [15:0];
assign m_axi_araddr[223:208] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[207:192] = \^m_axi_araddr [15:0];
assign m_axi_araddr[191:176] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[175:160] = \^m_axi_araddr [15:0];
assign m_axi_araddr[159:144] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[143:128] = \^m_axi_araddr [15:0];
assign m_axi_araddr[127:112] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[111:96] = \^m_axi_araddr [15:0];
assign m_axi_araddr[95:80] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[79:64] = \^m_axi_araddr [15:0];
assign m_axi_araddr[63:48] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[47:32] = \^m_axi_araddr [15:0];
assign m_axi_araddr[31:16] = \^m_axi_awaddr [447:432];
assign m_axi_araddr[15:0] = \^m_axi_araddr [15:0];
assign m_axi_arburst[27] = \<const0> ;
assign m_axi_arburst[26] = \<const0> ;
assign m_axi_arburst[25] = \<const0> ;
assign m_axi_arburst[24] = \<const0> ;
assign m_axi_arburst[23] = \<const0> ;
assign m_axi_arburst[22] = \<const0> ;
assign m_axi_arburst[21] = \<const0> ;
assign m_axi_arburst[20] = \<const0> ;
assign m_axi_arburst[19] = \<const0> ;
assign m_axi_arburst[18] = \<const0> ;
assign m_axi_arburst[17] = \<const0> ;
assign m_axi_arburst[16] = \<const0> ;
assign m_axi_arburst[15] = \<const0> ;
assign m_axi_arburst[14] = \<const0> ;
assign m_axi_arburst[13] = \<const0> ;
assign m_axi_arburst[12] = \<const0> ;
assign m_axi_arburst[11] = \<const0> ;
assign m_axi_arburst[10] = \<const0> ;
assign m_axi_arburst[9] = \<const0> ;
assign m_axi_arburst[8] = \<const0> ;
assign m_axi_arburst[7] = \<const0> ;
assign m_axi_arburst[6] = \<const0> ;
assign m_axi_arburst[5] = \<const0> ;
assign m_axi_arburst[4] = \<const0> ;
assign m_axi_arburst[3] = \<const0> ;
assign m_axi_arburst[2] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[55] = \<const0> ;
assign m_axi_arcache[54] = \<const0> ;
assign m_axi_arcache[53] = \<const0> ;
assign m_axi_arcache[52] = \<const0> ;
assign m_axi_arcache[51] = \<const0> ;
assign m_axi_arcache[50] = \<const0> ;
assign m_axi_arcache[49] = \<const0> ;
assign m_axi_arcache[48] = \<const0> ;
assign m_axi_arcache[47] = \<const0> ;
assign m_axi_arcache[46] = \<const0> ;
assign m_axi_arcache[45] = \<const0> ;
assign m_axi_arcache[44] = \<const0> ;
assign m_axi_arcache[43] = \<const0> ;
assign m_axi_arcache[42] = \<const0> ;
assign m_axi_arcache[41] = \<const0> ;
assign m_axi_arcache[40] = \<const0> ;
assign m_axi_arcache[39] = \<const0> ;
assign m_axi_arcache[38] = \<const0> ;
assign m_axi_arcache[37] = \<const0> ;
assign m_axi_arcache[36] = \<const0> ;
assign m_axi_arcache[35] = \<const0> ;
assign m_axi_arcache[34] = \<const0> ;
assign m_axi_arcache[33] = \<const0> ;
assign m_axi_arcache[32] = \<const0> ;
assign m_axi_arcache[31] = \<const0> ;
assign m_axi_arcache[30] = \<const0> ;
assign m_axi_arcache[29] = \<const0> ;
assign m_axi_arcache[28] = \<const0> ;
assign m_axi_arcache[27] = \<const0> ;
assign m_axi_arcache[26] = \<const0> ;
assign m_axi_arcache[25] = \<const0> ;
assign m_axi_arcache[24] = \<const0> ;
assign m_axi_arcache[23] = \<const0> ;
assign m_axi_arcache[22] = \<const0> ;
assign m_axi_arcache[21] = \<const0> ;
assign m_axi_arcache[20] = \<const0> ;
assign m_axi_arcache[19] = \<const0> ;
assign m_axi_arcache[18] = \<const0> ;
assign m_axi_arcache[17] = \<const0> ;
assign m_axi_arcache[16] = \<const0> ;
assign m_axi_arcache[15] = \<const0> ;
assign m_axi_arcache[14] = \<const0> ;
assign m_axi_arcache[13] = \<const0> ;
assign m_axi_arcache[12] = \<const0> ;
assign m_axi_arcache[11] = \<const0> ;
assign m_axi_arcache[10] = \<const0> ;
assign m_axi_arcache[9] = \<const0> ;
assign m_axi_arcache[8] = \<const0> ;
assign m_axi_arcache[7] = \<const0> ;
assign m_axi_arcache[6] = \<const0> ;
assign m_axi_arcache[5] = \<const0> ;
assign m_axi_arcache[4] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[13] = \<const0> ;
assign m_axi_arid[12] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[111] = \<const0> ;
assign m_axi_arlen[110] = \<const0> ;
assign m_axi_arlen[109] = \<const0> ;
assign m_axi_arlen[108] = \<const0> ;
assign m_axi_arlen[107] = \<const0> ;
assign m_axi_arlen[106] = \<const0> ;
assign m_axi_arlen[105] = \<const0> ;
assign m_axi_arlen[104] = \<const0> ;
assign m_axi_arlen[103] = \<const0> ;
assign m_axi_arlen[102] = \<const0> ;
assign m_axi_arlen[101] = \<const0> ;
assign m_axi_arlen[100] = \<const0> ;
assign m_axi_arlen[99] = \<const0> ;
assign m_axi_arlen[98] = \<const0> ;
assign m_axi_arlen[97] = \<const0> ;
assign m_axi_arlen[96] = \<const0> ;
assign m_axi_arlen[95] = \<const0> ;
assign m_axi_arlen[94] = \<const0> ;
assign m_axi_arlen[93] = \<const0> ;
assign m_axi_arlen[92] = \<const0> ;
assign m_axi_arlen[91] = \<const0> ;
assign m_axi_arlen[90] = \<const0> ;
assign m_axi_arlen[89] = \<const0> ;
assign m_axi_arlen[88] = \<const0> ;
assign m_axi_arlen[87] = \<const0> ;
assign m_axi_arlen[86] = \<const0> ;
assign m_axi_arlen[85] = \<const0> ;
assign m_axi_arlen[84] = \<const0> ;
assign m_axi_arlen[83] = \<const0> ;
assign m_axi_arlen[82] = \<const0> ;
assign m_axi_arlen[81] = \<const0> ;
assign m_axi_arlen[80] = \<const0> ;
assign m_axi_arlen[79] = \<const0> ;
assign m_axi_arlen[78] = \<const0> ;
assign m_axi_arlen[77] = \<const0> ;
assign m_axi_arlen[76] = \<const0> ;
assign m_axi_arlen[75] = \<const0> ;
assign m_axi_arlen[74] = \<const0> ;
assign m_axi_arlen[73] = \<const0> ;
assign m_axi_arlen[72] = \<const0> ;
assign m_axi_arlen[71] = \<const0> ;
assign m_axi_arlen[70] = \<const0> ;
assign m_axi_arlen[69] = \<const0> ;
assign m_axi_arlen[68] = \<const0> ;
assign m_axi_arlen[67] = \<const0> ;
assign m_axi_arlen[66] = \<const0> ;
assign m_axi_arlen[65] = \<const0> ;
assign m_axi_arlen[64] = \<const0> ;
assign m_axi_arlen[63] = \<const0> ;
assign m_axi_arlen[62] = \<const0> ;
assign m_axi_arlen[61] = \<const0> ;
assign m_axi_arlen[60] = \<const0> ;
assign m_axi_arlen[59] = \<const0> ;
assign m_axi_arlen[58] = \<const0> ;
assign m_axi_arlen[57] = \<const0> ;
assign m_axi_arlen[56] = \<const0> ;
assign m_axi_arlen[55] = \<const0> ;
assign m_axi_arlen[54] = \<const0> ;
assign m_axi_arlen[53] = \<const0> ;
assign m_axi_arlen[52] = \<const0> ;
assign m_axi_arlen[51] = \<const0> ;
assign m_axi_arlen[50] = \<const0> ;
assign m_axi_arlen[49] = \<const0> ;
assign m_axi_arlen[48] = \<const0> ;
assign m_axi_arlen[47] = \<const0> ;
assign m_axi_arlen[46] = \<const0> ;
assign m_axi_arlen[45] = \<const0> ;
assign m_axi_arlen[44] = \<const0> ;
assign m_axi_arlen[43] = \<const0> ;
assign m_axi_arlen[42] = \<const0> ;
assign m_axi_arlen[41] = \<const0> ;
assign m_axi_arlen[40] = \<const0> ;
assign m_axi_arlen[39] = \<const0> ;
assign m_axi_arlen[38] = \<const0> ;
assign m_axi_arlen[37] = \<const0> ;
assign m_axi_arlen[36] = \<const0> ;
assign m_axi_arlen[35] = \<const0> ;
assign m_axi_arlen[34] = \<const0> ;
assign m_axi_arlen[33] = \<const0> ;
assign m_axi_arlen[32] = \<const0> ;
assign m_axi_arlen[31] = \<const0> ;
assign m_axi_arlen[30] = \<const0> ;
assign m_axi_arlen[29] = \<const0> ;
assign m_axi_arlen[28] = \<const0> ;
assign m_axi_arlen[27] = \<const0> ;
assign m_axi_arlen[26] = \<const0> ;
assign m_axi_arlen[25] = \<const0> ;
assign m_axi_arlen[24] = \<const0> ;
assign m_axi_arlen[23] = \<const0> ;
assign m_axi_arlen[22] = \<const0> ;
assign m_axi_arlen[21] = \<const0> ;
assign m_axi_arlen[20] = \<const0> ;
assign m_axi_arlen[19] = \<const0> ;
assign m_axi_arlen[18] = \<const0> ;
assign m_axi_arlen[17] = \<const0> ;
assign m_axi_arlen[16] = \<const0> ;
assign m_axi_arlen[15] = \<const0> ;
assign m_axi_arlen[14] = \<const0> ;
assign m_axi_arlen[13] = \<const0> ;
assign m_axi_arlen[12] = \<const0> ;
assign m_axi_arlen[11] = \<const0> ;
assign m_axi_arlen[10] = \<const0> ;
assign m_axi_arlen[9] = \<const0> ;
assign m_axi_arlen[8] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[13] = \<const0> ;
assign m_axi_arlock[12] = \<const0> ;
assign m_axi_arlock[11] = \<const0> ;
assign m_axi_arlock[10] = \<const0> ;
assign m_axi_arlock[9] = \<const0> ;
assign m_axi_arlock[8] = \<const0> ;
assign m_axi_arlock[7] = \<const0> ;
assign m_axi_arlock[6] = \<const0> ;
assign m_axi_arlock[5] = \<const0> ;
assign m_axi_arlock[4] = \<const0> ;
assign m_axi_arlock[3] = \<const0> ;
assign m_axi_arlock[2] = \<const0> ;
assign m_axi_arlock[1] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[41:39] = \^m_axi_arprot [2:0];
assign m_axi_arprot[38:36] = \^m_axi_arprot [2:0];
assign m_axi_arprot[35:33] = \^m_axi_arprot [2:0];
assign m_axi_arprot[32:30] = \^m_axi_arprot [2:0];
assign m_axi_arprot[29:27] = \^m_axi_arprot [2:0];
assign m_axi_arprot[26:24] = \^m_axi_arprot [2:0];
assign m_axi_arprot[23:21] = \^m_axi_arprot [2:0];
assign m_axi_arprot[20:18] = \^m_axi_arprot [2:0];
assign m_axi_arprot[17:15] = \^m_axi_arprot [2:0];
assign m_axi_arprot[14:12] = \^m_axi_arprot [2:0];
assign m_axi_arprot[11:9] = \^m_axi_arprot [2:0];
assign m_axi_arprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_arprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_arprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_arqos[55] = \<const0> ;
assign m_axi_arqos[54] = \<const0> ;
assign m_axi_arqos[53] = \<const0> ;
assign m_axi_arqos[52] = \<const0> ;
assign m_axi_arqos[51] = \<const0> ;
assign m_axi_arqos[50] = \<const0> ;
assign m_axi_arqos[49] = \<const0> ;
assign m_axi_arqos[48] = \<const0> ;
assign m_axi_arqos[47] = \<const0> ;
assign m_axi_arqos[46] = \<const0> ;
assign m_axi_arqos[45] = \<const0> ;
assign m_axi_arqos[44] = \<const0> ;
assign m_axi_arqos[43] = \<const0> ;
assign m_axi_arqos[42] = \<const0> ;
assign m_axi_arqos[41] = \<const0> ;
assign m_axi_arqos[40] = \<const0> ;
assign m_axi_arqos[39] = \<const0> ;
assign m_axi_arqos[38] = \<const0> ;
assign m_axi_arqos[37] = \<const0> ;
assign m_axi_arqos[36] = \<const0> ;
assign m_axi_arqos[35] = \<const0> ;
assign m_axi_arqos[34] = \<const0> ;
assign m_axi_arqos[33] = \<const0> ;
assign m_axi_arqos[32] = \<const0> ;
assign m_axi_arqos[31] = \<const0> ;
assign m_axi_arqos[30] = \<const0> ;
assign m_axi_arqos[29] = \<const0> ;
assign m_axi_arqos[28] = \<const0> ;
assign m_axi_arqos[27] = \<const0> ;
assign m_axi_arqos[26] = \<const0> ;
assign m_axi_arqos[25] = \<const0> ;
assign m_axi_arqos[24] = \<const0> ;
assign m_axi_arqos[23] = \<const0> ;
assign m_axi_arqos[22] = \<const0> ;
assign m_axi_arqos[21] = \<const0> ;
assign m_axi_arqos[20] = \<const0> ;
assign m_axi_arqos[19] = \<const0> ;
assign m_axi_arqos[18] = \<const0> ;
assign m_axi_arqos[17] = \<const0> ;
assign m_axi_arqos[16] = \<const0> ;
assign m_axi_arqos[15] = \<const0> ;
assign m_axi_arqos[14] = \<const0> ;
assign m_axi_arqos[13] = \<const0> ;
assign m_axi_arqos[12] = \<const0> ;
assign m_axi_arqos[11] = \<const0> ;
assign m_axi_arqos[10] = \<const0> ;
assign m_axi_arqos[9] = \<const0> ;
assign m_axi_arqos[8] = \<const0> ;
assign m_axi_arqos[7] = \<const0> ;
assign m_axi_arqos[6] = \<const0> ;
assign m_axi_arqos[5] = \<const0> ;
assign m_axi_arqos[4] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[55] = \<const0> ;
assign m_axi_arregion[54] = \<const0> ;
assign m_axi_arregion[53] = \<const0> ;
assign m_axi_arregion[52] = \<const0> ;
assign m_axi_arregion[51] = \<const0> ;
assign m_axi_arregion[50] = \<const0> ;
assign m_axi_arregion[49] = \<const0> ;
assign m_axi_arregion[48] = \<const0> ;
assign m_axi_arregion[47] = \<const0> ;
assign m_axi_arregion[46] = \<const0> ;
assign m_axi_arregion[45] = \<const0> ;
assign m_axi_arregion[44] = \<const0> ;
assign m_axi_arregion[43] = \<const0> ;
assign m_axi_arregion[42] = \<const0> ;
assign m_axi_arregion[41] = \<const0> ;
assign m_axi_arregion[40] = \<const0> ;
assign m_axi_arregion[39] = \<const0> ;
assign m_axi_arregion[38] = \<const0> ;
assign m_axi_arregion[37] = \<const0> ;
assign m_axi_arregion[36] = \<const0> ;
assign m_axi_arregion[35] = \<const0> ;
assign m_axi_arregion[34] = \<const0> ;
assign m_axi_arregion[33] = \<const0> ;
assign m_axi_arregion[32] = \<const0> ;
assign m_axi_arregion[31] = \<const0> ;
assign m_axi_arregion[30] = \<const0> ;
assign m_axi_arregion[29] = \<const0> ;
assign m_axi_arregion[28] = \<const0> ;
assign m_axi_arregion[27] = \<const0> ;
assign m_axi_arregion[26] = \<const0> ;
assign m_axi_arregion[25] = \<const0> ;
assign m_axi_arregion[24] = \<const0> ;
assign m_axi_arregion[23] = \<const0> ;
assign m_axi_arregion[22] = \<const0> ;
assign m_axi_arregion[21] = \<const0> ;
assign m_axi_arregion[20] = \<const0> ;
assign m_axi_arregion[19] = \<const0> ;
assign m_axi_arregion[18] = \<const0> ;
assign m_axi_arregion[17] = \<const0> ;
assign m_axi_arregion[16] = \<const0> ;
assign m_axi_arregion[15] = \<const0> ;
assign m_axi_arregion[14] = \<const0> ;
assign m_axi_arregion[13] = \<const0> ;
assign m_axi_arregion[12] = \<const0> ;
assign m_axi_arregion[11] = \<const0> ;
assign m_axi_arregion[10] = \<const0> ;
assign m_axi_arregion[9] = \<const0> ;
assign m_axi_arregion[8] = \<const0> ;
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[41] = \<const0> ;
assign m_axi_arsize[40] = \<const0> ;
assign m_axi_arsize[39] = \<const0> ;
assign m_axi_arsize[38] = \<const0> ;
assign m_axi_arsize[37] = \<const0> ;
assign m_axi_arsize[36] = \<const0> ;
assign m_axi_arsize[35] = \<const0> ;
assign m_axi_arsize[34] = \<const0> ;
assign m_axi_arsize[33] = \<const0> ;
assign m_axi_arsize[32] = \<const0> ;
assign m_axi_arsize[31] = \<const0> ;
assign m_axi_arsize[30] = \<const0> ;
assign m_axi_arsize[29] = \<const0> ;
assign m_axi_arsize[28] = \<const0> ;
assign m_axi_arsize[27] = \<const0> ;
assign m_axi_arsize[26] = \<const0> ;
assign m_axi_arsize[25] = \<const0> ;
assign m_axi_arsize[24] = \<const0> ;
assign m_axi_arsize[23] = \<const0> ;
assign m_axi_arsize[22] = \<const0> ;
assign m_axi_arsize[21] = \<const0> ;
assign m_axi_arsize[20] = \<const0> ;
assign m_axi_arsize[19] = \<const0> ;
assign m_axi_arsize[18] = \<const0> ;
assign m_axi_arsize[17] = \<const0> ;
assign m_axi_arsize[16] = \<const0> ;
assign m_axi_arsize[15] = \<const0> ;
assign m_axi_arsize[14] = \<const0> ;
assign m_axi_arsize[13] = \<const0> ;
assign m_axi_arsize[12] = \<const0> ;
assign m_axi_arsize[11] = \<const0> ;
assign m_axi_arsize[10] = \<const0> ;
assign m_axi_arsize[9] = \<const0> ;
assign m_axi_arsize[8] = \<const0> ;
assign m_axi_arsize[7] = \<const0> ;
assign m_axi_arsize[6] = \<const0> ;
assign m_axi_arsize[5] = \<const0> ;
assign m_axi_arsize[4] = \<const0> ;
assign m_axi_arsize[3] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[13] = \<const0> ;
assign m_axi_aruser[12] = \<const0> ;
assign m_axi_aruser[11] = \<const0> ;
assign m_axi_aruser[10] = \<const0> ;
assign m_axi_aruser[9] = \<const0> ;
assign m_axi_aruser[8] = \<const0> ;
assign m_axi_aruser[7] = \<const0> ;
assign m_axi_aruser[6] = \<const0> ;
assign m_axi_aruser[5] = \<const0> ;
assign m_axi_aruser[4] = \<const0> ;
assign m_axi_aruser[3] = \<const0> ;
assign m_axi_aruser[2] = \<const0> ;
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid[13:11] = \^m_axi_arvalid [13:11];
assign m_axi_arvalid[10] = \<const0> ;
assign m_axi_arvalid[9:0] = \^m_axi_arvalid [9:0];
assign m_axi_awaddr[447:432] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[431:416] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[415:400] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[399:384] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[383:368] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[367:352] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[351:336] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[335:320] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[319:304] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[303:288] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[287:272] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[271:256] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[255:240] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[239:224] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[223:208] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[207:192] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[191:176] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[175:160] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[159:144] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[143:128] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[127:112] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[111:96] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[95:80] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[79:64] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[63:48] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[47:32] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[31:16] = \^m_axi_awaddr [447:432];
assign m_axi_awaddr[15:0] = \^m_axi_araddr [15:0];
assign m_axi_awburst[27] = \<const0> ;
assign m_axi_awburst[26] = \<const0> ;
assign m_axi_awburst[25] = \<const0> ;
assign m_axi_awburst[24] = \<const0> ;
assign m_axi_awburst[23] = \<const0> ;
assign m_axi_awburst[22] = \<const0> ;
assign m_axi_awburst[21] = \<const0> ;
assign m_axi_awburst[20] = \<const0> ;
assign m_axi_awburst[19] = \<const0> ;
assign m_axi_awburst[18] = \<const0> ;
assign m_axi_awburst[17] = \<const0> ;
assign m_axi_awburst[16] = \<const0> ;
assign m_axi_awburst[15] = \<const0> ;
assign m_axi_awburst[14] = \<const0> ;
assign m_axi_awburst[13] = \<const0> ;
assign m_axi_awburst[12] = \<const0> ;
assign m_axi_awburst[11] = \<const0> ;
assign m_axi_awburst[10] = \<const0> ;
assign m_axi_awburst[9] = \<const0> ;
assign m_axi_awburst[8] = \<const0> ;
assign m_axi_awburst[7] = \<const0> ;
assign m_axi_awburst[6] = \<const0> ;
assign m_axi_awburst[5] = \<const0> ;
assign m_axi_awburst[4] = \<const0> ;
assign m_axi_awburst[3] = \<const0> ;
assign m_axi_awburst[2] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[55] = \<const0> ;
assign m_axi_awcache[54] = \<const0> ;
assign m_axi_awcache[53] = \<const0> ;
assign m_axi_awcache[52] = \<const0> ;
assign m_axi_awcache[51] = \<const0> ;
assign m_axi_awcache[50] = \<const0> ;
assign m_axi_awcache[49] = \<const0> ;
assign m_axi_awcache[48] = \<const0> ;
assign m_axi_awcache[47] = \<const0> ;
assign m_axi_awcache[46] = \<const0> ;
assign m_axi_awcache[45] = \<const0> ;
assign m_axi_awcache[44] = \<const0> ;
assign m_axi_awcache[43] = \<const0> ;
assign m_axi_awcache[42] = \<const0> ;
assign m_axi_awcache[41] = \<const0> ;
assign m_axi_awcache[40] = \<const0> ;
assign m_axi_awcache[39] = \<const0> ;
assign m_axi_awcache[38] = \<const0> ;
assign m_axi_awcache[37] = \<const0> ;
assign m_axi_awcache[36] = \<const0> ;
assign m_axi_awcache[35] = \<const0> ;
assign m_axi_awcache[34] = \<const0> ;
assign m_axi_awcache[33] = \<const0> ;
assign m_axi_awcache[32] = \<const0> ;
assign m_axi_awcache[31] = \<const0> ;
assign m_axi_awcache[30] = \<const0> ;
assign m_axi_awcache[29] = \<const0> ;
assign m_axi_awcache[28] = \<const0> ;
assign m_axi_awcache[27] = \<const0> ;
assign m_axi_awcache[26] = \<const0> ;
assign m_axi_awcache[25] = \<const0> ;
assign m_axi_awcache[24] = \<const0> ;
assign m_axi_awcache[23] = \<const0> ;
assign m_axi_awcache[22] = \<const0> ;
assign m_axi_awcache[21] = \<const0> ;
assign m_axi_awcache[20] = \<const0> ;
assign m_axi_awcache[19] = \<const0> ;
assign m_axi_awcache[18] = \<const0> ;
assign m_axi_awcache[17] = \<const0> ;
assign m_axi_awcache[16] = \<const0> ;
assign m_axi_awcache[15] = \<const0> ;
assign m_axi_awcache[14] = \<const0> ;
assign m_axi_awcache[13] = \<const0> ;
assign m_axi_awcache[12] = \<const0> ;
assign m_axi_awcache[11] = \<const0> ;
assign m_axi_awcache[10] = \<const0> ;
assign m_axi_awcache[9] = \<const0> ;
assign m_axi_awcache[8] = \<const0> ;
assign m_axi_awcache[7] = \<const0> ;
assign m_axi_awcache[6] = \<const0> ;
assign m_axi_awcache[5] = \<const0> ;
assign m_axi_awcache[4] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[13] = \<const0> ;
assign m_axi_awid[12] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[111] = \<const0> ;
assign m_axi_awlen[110] = \<const0> ;
assign m_axi_awlen[109] = \<const0> ;
assign m_axi_awlen[108] = \<const0> ;
assign m_axi_awlen[107] = \<const0> ;
assign m_axi_awlen[106] = \<const0> ;
assign m_axi_awlen[105] = \<const0> ;
assign m_axi_awlen[104] = \<const0> ;
assign m_axi_awlen[103] = \<const0> ;
assign m_axi_awlen[102] = \<const0> ;
assign m_axi_awlen[101] = \<const0> ;
assign m_axi_awlen[100] = \<const0> ;
assign m_axi_awlen[99] = \<const0> ;
assign m_axi_awlen[98] = \<const0> ;
assign m_axi_awlen[97] = \<const0> ;
assign m_axi_awlen[96] = \<const0> ;
assign m_axi_awlen[95] = \<const0> ;
assign m_axi_awlen[94] = \<const0> ;
assign m_axi_awlen[93] = \<const0> ;
assign m_axi_awlen[92] = \<const0> ;
assign m_axi_awlen[91] = \<const0> ;
assign m_axi_awlen[90] = \<const0> ;
assign m_axi_awlen[89] = \<const0> ;
assign m_axi_awlen[88] = \<const0> ;
assign m_axi_awlen[87] = \<const0> ;
assign m_axi_awlen[86] = \<const0> ;
assign m_axi_awlen[85] = \<const0> ;
assign m_axi_awlen[84] = \<const0> ;
assign m_axi_awlen[83] = \<const0> ;
assign m_axi_awlen[82] = \<const0> ;
assign m_axi_awlen[81] = \<const0> ;
assign m_axi_awlen[80] = \<const0> ;
assign m_axi_awlen[79] = \<const0> ;
assign m_axi_awlen[78] = \<const0> ;
assign m_axi_awlen[77] = \<const0> ;
assign m_axi_awlen[76] = \<const0> ;
assign m_axi_awlen[75] = \<const0> ;
assign m_axi_awlen[74] = \<const0> ;
assign m_axi_awlen[73] = \<const0> ;
assign m_axi_awlen[72] = \<const0> ;
assign m_axi_awlen[71] = \<const0> ;
assign m_axi_awlen[70] = \<const0> ;
assign m_axi_awlen[69] = \<const0> ;
assign m_axi_awlen[68] = \<const0> ;
assign m_axi_awlen[67] = \<const0> ;
assign m_axi_awlen[66] = \<const0> ;
assign m_axi_awlen[65] = \<const0> ;
assign m_axi_awlen[64] = \<const0> ;
assign m_axi_awlen[63] = \<const0> ;
assign m_axi_awlen[62] = \<const0> ;
assign m_axi_awlen[61] = \<const0> ;
assign m_axi_awlen[60] = \<const0> ;
assign m_axi_awlen[59] = \<const0> ;
assign m_axi_awlen[58] = \<const0> ;
assign m_axi_awlen[57] = \<const0> ;
assign m_axi_awlen[56] = \<const0> ;
assign m_axi_awlen[55] = \<const0> ;
assign m_axi_awlen[54] = \<const0> ;
assign m_axi_awlen[53] = \<const0> ;
assign m_axi_awlen[52] = \<const0> ;
assign m_axi_awlen[51] = \<const0> ;
assign m_axi_awlen[50] = \<const0> ;
assign m_axi_awlen[49] = \<const0> ;
assign m_axi_awlen[48] = \<const0> ;
assign m_axi_awlen[47] = \<const0> ;
assign m_axi_awlen[46] = \<const0> ;
assign m_axi_awlen[45] = \<const0> ;
assign m_axi_awlen[44] = \<const0> ;
assign m_axi_awlen[43] = \<const0> ;
assign m_axi_awlen[42] = \<const0> ;
assign m_axi_awlen[41] = \<const0> ;
assign m_axi_awlen[40] = \<const0> ;
assign m_axi_awlen[39] = \<const0> ;
assign m_axi_awlen[38] = \<const0> ;
assign m_axi_awlen[37] = \<const0> ;
assign m_axi_awlen[36] = \<const0> ;
assign m_axi_awlen[35] = \<const0> ;
assign m_axi_awlen[34] = \<const0> ;
assign m_axi_awlen[33] = \<const0> ;
assign m_axi_awlen[32] = \<const0> ;
assign m_axi_awlen[31] = \<const0> ;
assign m_axi_awlen[30] = \<const0> ;
assign m_axi_awlen[29] = \<const0> ;
assign m_axi_awlen[28] = \<const0> ;
assign m_axi_awlen[27] = \<const0> ;
assign m_axi_awlen[26] = \<const0> ;
assign m_axi_awlen[25] = \<const0> ;
assign m_axi_awlen[24] = \<const0> ;
assign m_axi_awlen[23] = \<const0> ;
assign m_axi_awlen[22] = \<const0> ;
assign m_axi_awlen[21] = \<const0> ;
assign m_axi_awlen[20] = \<const0> ;
assign m_axi_awlen[19] = \<const0> ;
assign m_axi_awlen[18] = \<const0> ;
assign m_axi_awlen[17] = \<const0> ;
assign m_axi_awlen[16] = \<const0> ;
assign m_axi_awlen[15] = \<const0> ;
assign m_axi_awlen[14] = \<const0> ;
assign m_axi_awlen[13] = \<const0> ;
assign m_axi_awlen[12] = \<const0> ;
assign m_axi_awlen[11] = \<const0> ;
assign m_axi_awlen[10] = \<const0> ;
assign m_axi_awlen[9] = \<const0> ;
assign m_axi_awlen[8] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[13] = \<const0> ;
assign m_axi_awlock[12] = \<const0> ;
assign m_axi_awlock[11] = \<const0> ;
assign m_axi_awlock[10] = \<const0> ;
assign m_axi_awlock[9] = \<const0> ;
assign m_axi_awlock[8] = \<const0> ;
assign m_axi_awlock[7] = \<const0> ;
assign m_axi_awlock[6] = \<const0> ;
assign m_axi_awlock[5] = \<const0> ;
assign m_axi_awlock[4] = \<const0> ;
assign m_axi_awlock[3] = \<const0> ;
assign m_axi_awlock[2] = \<const0> ;
assign m_axi_awlock[1] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[41:39] = \^m_axi_arprot [2:0];
assign m_axi_awprot[38:36] = \^m_axi_arprot [2:0];
assign m_axi_awprot[35:33] = \^m_axi_arprot [2:0];
assign m_axi_awprot[32:30] = \^m_axi_arprot [2:0];
assign m_axi_awprot[29:27] = \^m_axi_arprot [2:0];
assign m_axi_awprot[26:24] = \^m_axi_arprot [2:0];
assign m_axi_awprot[23:21] = \^m_axi_arprot [2:0];
assign m_axi_awprot[20:18] = \^m_axi_arprot [2:0];
assign m_axi_awprot[17:15] = \^m_axi_arprot [2:0];
assign m_axi_awprot[14:12] = \^m_axi_arprot [2:0];
assign m_axi_awprot[11:9] = \^m_axi_arprot [2:0];
assign m_axi_awprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_awprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_awprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_awqos[55] = \<const0> ;
assign m_axi_awqos[54] = \<const0> ;
assign m_axi_awqos[53] = \<const0> ;
assign m_axi_awqos[52] = \<const0> ;
assign m_axi_awqos[51] = \<const0> ;
assign m_axi_awqos[50] = \<const0> ;
assign m_axi_awqos[49] = \<const0> ;
assign m_axi_awqos[48] = \<const0> ;
assign m_axi_awqos[47] = \<const0> ;
assign m_axi_awqos[46] = \<const0> ;
assign m_axi_awqos[45] = \<const0> ;
assign m_axi_awqos[44] = \<const0> ;
assign m_axi_awqos[43] = \<const0> ;
assign m_axi_awqos[42] = \<const0> ;
assign m_axi_awqos[41] = \<const0> ;
assign m_axi_awqos[40] = \<const0> ;
assign m_axi_awqos[39] = \<const0> ;
assign m_axi_awqos[38] = \<const0> ;
assign m_axi_awqos[37] = \<const0> ;
assign m_axi_awqos[36] = \<const0> ;
assign m_axi_awqos[35] = \<const0> ;
assign m_axi_awqos[34] = \<const0> ;
assign m_axi_awqos[33] = \<const0> ;
assign m_axi_awqos[32] = \<const0> ;
assign m_axi_awqos[31] = \<const0> ;
assign m_axi_awqos[30] = \<const0> ;
assign m_axi_awqos[29] = \<const0> ;
assign m_axi_awqos[28] = \<const0> ;
assign m_axi_awqos[27] = \<const0> ;
assign m_axi_awqos[26] = \<const0> ;
assign m_axi_awqos[25] = \<const0> ;
assign m_axi_awqos[24] = \<const0> ;
assign m_axi_awqos[23] = \<const0> ;
assign m_axi_awqos[22] = \<const0> ;
assign m_axi_awqos[21] = \<const0> ;
assign m_axi_awqos[20] = \<const0> ;
assign m_axi_awqos[19] = \<const0> ;
assign m_axi_awqos[18] = \<const0> ;
assign m_axi_awqos[17] = \<const0> ;
assign m_axi_awqos[16] = \<const0> ;
assign m_axi_awqos[15] = \<const0> ;
assign m_axi_awqos[14] = \<const0> ;
assign m_axi_awqos[13] = \<const0> ;
assign m_axi_awqos[12] = \<const0> ;
assign m_axi_awqos[11] = \<const0> ;
assign m_axi_awqos[10] = \<const0> ;
assign m_axi_awqos[9] = \<const0> ;
assign m_axi_awqos[8] = \<const0> ;
assign m_axi_awqos[7] = \<const0> ;
assign m_axi_awqos[6] = \<const0> ;
assign m_axi_awqos[5] = \<const0> ;
assign m_axi_awqos[4] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[55] = \<const0> ;
assign m_axi_awregion[54] = \<const0> ;
assign m_axi_awregion[53] = \<const0> ;
assign m_axi_awregion[52] = \<const0> ;
assign m_axi_awregion[51] = \<const0> ;
assign m_axi_awregion[50] = \<const0> ;
assign m_axi_awregion[49] = \<const0> ;
assign m_axi_awregion[48] = \<const0> ;
assign m_axi_awregion[47] = \<const0> ;
assign m_axi_awregion[46] = \<const0> ;
assign m_axi_awregion[45] = \<const0> ;
assign m_axi_awregion[44] = \<const0> ;
assign m_axi_awregion[43] = \<const0> ;
assign m_axi_awregion[42] = \<const0> ;
assign m_axi_awregion[41] = \<const0> ;
assign m_axi_awregion[40] = \<const0> ;
assign m_axi_awregion[39] = \<const0> ;
assign m_axi_awregion[38] = \<const0> ;
assign m_axi_awregion[37] = \<const0> ;
assign m_axi_awregion[36] = \<const0> ;
assign m_axi_awregion[35] = \<const0> ;
assign m_axi_awregion[34] = \<const0> ;
assign m_axi_awregion[33] = \<const0> ;
assign m_axi_awregion[32] = \<const0> ;
assign m_axi_awregion[31] = \<const0> ;
assign m_axi_awregion[30] = \<const0> ;
assign m_axi_awregion[29] = \<const0> ;
assign m_axi_awregion[28] = \<const0> ;
assign m_axi_awregion[27] = \<const0> ;
assign m_axi_awregion[26] = \<const0> ;
assign m_axi_awregion[25] = \<const0> ;
assign m_axi_awregion[24] = \<const0> ;
assign m_axi_awregion[23] = \<const0> ;
assign m_axi_awregion[22] = \<const0> ;
assign m_axi_awregion[21] = \<const0> ;
assign m_axi_awregion[20] = \<const0> ;
assign m_axi_awregion[19] = \<const0> ;
assign m_axi_awregion[18] = \<const0> ;
assign m_axi_awregion[17] = \<const0> ;
assign m_axi_awregion[16] = \<const0> ;
assign m_axi_awregion[15] = \<const0> ;
assign m_axi_awregion[14] = \<const0> ;
assign m_axi_awregion[13] = \<const0> ;
assign m_axi_awregion[12] = \<const0> ;
assign m_axi_awregion[11] = \<const0> ;
assign m_axi_awregion[10] = \<const0> ;
assign m_axi_awregion[9] = \<const0> ;
assign m_axi_awregion[8] = \<const0> ;
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[41] = \<const0> ;
assign m_axi_awsize[40] = \<const0> ;
assign m_axi_awsize[39] = \<const0> ;
assign m_axi_awsize[38] = \<const0> ;
assign m_axi_awsize[37] = \<const0> ;
assign m_axi_awsize[36] = \<const0> ;
assign m_axi_awsize[35] = \<const0> ;
assign m_axi_awsize[34] = \<const0> ;
assign m_axi_awsize[33] = \<const0> ;
assign m_axi_awsize[32] = \<const0> ;
assign m_axi_awsize[31] = \<const0> ;
assign m_axi_awsize[30] = \<const0> ;
assign m_axi_awsize[29] = \<const0> ;
assign m_axi_awsize[28] = \<const0> ;
assign m_axi_awsize[27] = \<const0> ;
assign m_axi_awsize[26] = \<const0> ;
assign m_axi_awsize[25] = \<const0> ;
assign m_axi_awsize[24] = \<const0> ;
assign m_axi_awsize[23] = \<const0> ;
assign m_axi_awsize[22] = \<const0> ;
assign m_axi_awsize[21] = \<const0> ;
assign m_axi_awsize[20] = \<const0> ;
assign m_axi_awsize[19] = \<const0> ;
assign m_axi_awsize[18] = \<const0> ;
assign m_axi_awsize[17] = \<const0> ;
assign m_axi_awsize[16] = \<const0> ;
assign m_axi_awsize[15] = \<const0> ;
assign m_axi_awsize[14] = \<const0> ;
assign m_axi_awsize[13] = \<const0> ;
assign m_axi_awsize[12] = \<const0> ;
assign m_axi_awsize[11] = \<const0> ;
assign m_axi_awsize[10] = \<const0> ;
assign m_axi_awsize[9] = \<const0> ;
assign m_axi_awsize[8] = \<const0> ;
assign m_axi_awsize[7] = \<const0> ;
assign m_axi_awsize[6] = \<const0> ;
assign m_axi_awsize[5] = \<const0> ;
assign m_axi_awsize[4] = \<const0> ;
assign m_axi_awsize[3] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[13] = \<const0> ;
assign m_axi_awuser[12] = \<const0> ;
assign m_axi_awuser[11] = \<const0> ;
assign m_axi_awuser[10] = \<const0> ;
assign m_axi_awuser[9] = \<const0> ;
assign m_axi_awuser[8] = \<const0> ;
assign m_axi_awuser[7] = \<const0> ;
assign m_axi_awuser[6] = \<const0> ;
assign m_axi_awuser[5] = \<const0> ;
assign m_axi_awuser[4] = \<const0> ;
assign m_axi_awuser[3] = \<const0> ;
assign m_axi_awuser[2] = \<const0> ;
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid[13:11] = \^m_axi_awvalid [13:11];
assign m_axi_awvalid[10] = \<const0> ;
assign m_axi_awvalid[9:0] = \^m_axi_awvalid [9:0];
assign m_axi_bready[13:11] = \^m_axi_bready [13:11];
assign m_axi_bready[10] = \<const0> ;
assign m_axi_bready[9:0] = \^m_axi_bready [9:0];
assign m_axi_rready[13:11] = \^m_axi_rready [13:11];
assign m_axi_rready[10] = \<const0> ;
assign m_axi_rready[9:0] = \^m_axi_rready [9:0];
assign m_axi_wdata[447:416] = s_axi_wdata;
assign m_axi_wdata[415:384] = s_axi_wdata;
assign m_axi_wdata[383:352] = s_axi_wdata;
assign m_axi_wdata[351:320] = s_axi_wdata;
assign m_axi_wdata[319:288] = s_axi_wdata;
assign m_axi_wdata[287:256] = s_axi_wdata;
assign m_axi_wdata[255:224] = s_axi_wdata;
assign m_axi_wdata[223:192] = s_axi_wdata;
assign m_axi_wdata[191:160] = s_axi_wdata;
assign m_axi_wdata[159:128] = s_axi_wdata;
assign m_axi_wdata[127:96] = s_axi_wdata;
assign m_axi_wdata[95:64] = s_axi_wdata;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[13] = \<const0> ;
assign m_axi_wid[12] = \<const0> ;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[13] = \<const0> ;
assign m_axi_wlast[12] = \<const0> ;
assign m_axi_wlast[11] = \<const0> ;
assign m_axi_wlast[10] = \<const0> ;
assign m_axi_wlast[9] = \<const0> ;
assign m_axi_wlast[8] = \<const0> ;
assign m_axi_wlast[7] = \<const0> ;
assign m_axi_wlast[6] = \<const0> ;
assign m_axi_wlast[5] = \<const0> ;
assign m_axi_wlast[4] = \<const0> ;
assign m_axi_wlast[3] = \<const0> ;
assign m_axi_wlast[2] = \<const0> ;
assign m_axi_wlast[1] = \<const0> ;
assign m_axi_wlast[0] = \<const0> ;
assign m_axi_wstrb[55:52] = s_axi_wstrb;
assign m_axi_wstrb[51:48] = s_axi_wstrb;
assign m_axi_wstrb[47:44] = s_axi_wstrb;
assign m_axi_wstrb[43:40] = s_axi_wstrb;
assign m_axi_wstrb[39:36] = s_axi_wstrb;
assign m_axi_wstrb[35:32] = s_axi_wstrb;
assign m_axi_wstrb[31:28] = s_axi_wstrb;
assign m_axi_wstrb[27:24] = s_axi_wstrb;
assign m_axi_wstrb[23:20] = s_axi_wstrb;
assign m_axi_wstrb[19:16] = s_axi_wstrb;
assign m_axi_wstrb[15:12] = s_axi_wstrb;
assign m_axi_wstrb[11:8] = s_axi_wstrb;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[13] = \<const0> ;
assign m_axi_wuser[12] = \<const0> ;
assign m_axi_wuser[11] = \<const0> ;
assign m_axi_wuser[10] = \<const0> ;
assign m_axi_wuser[9] = \<const0> ;
assign m_axi_wuser[8] = \<const0> ;
assign m_axi_wuser[7] = \<const0> ;
assign m_axi_wuser[6] = \<const0> ;
assign m_axi_wuser[5] = \<const0> ;
assign m_axi_wuser[4] = \<const0> ;
assign m_axi_wuser[3] = \<const0> ;
assign m_axi_wuser[2] = \<const0> ;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid[13:11] = \^m_axi_wvalid [13:11];
assign m_axi_wvalid[10] = \<const0> ;
assign m_axi_wvalid[9:0] = \^m_axi_wvalid [9:0];
assign s_axi_bid[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
system_xbar_1_axi_crossbar_v2_1_12_crossbar_sasd \gen_sasd.crossbar_sasd_0
(.Q({\^m_axi_arprot ,\^m_axi_awaddr ,\^m_axi_araddr }),
.aclk(aclk),
.aresetn(aresetn),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid({\^m_axi_arvalid [13:11],\^m_axi_arvalid [9:0]}),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid({\^m_axi_awvalid [13:11],\^m_axi_awvalid [9:0]}),
.m_axi_bready({\^m_axi_bready [13:11],\^m_axi_bready [9:0]}),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready({\^m_axi_rready [13:11],\^m_axi_rready [9:0]}),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid({\^m_axi_wvalid [13:11],\^m_axi_wvalid [9:0]}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_crossbar_sasd" *)
module system_xbar_1_axi_crossbar_v2_1_12_crossbar_sasd
(Q,
\s_axi_rdata[31] ,
s_axi_bvalid,
m_axi_bready,
s_axi_wready,
m_axi_wvalid,
m_axi_awvalid,
m_axi_arvalid,
s_axi_bresp,
s_axi_awready,
s_axi_arready,
s_axi_rvalid,
m_axi_rready,
aresetn,
aclk,
s_axi_wvalid,
s_axi_bready,
s_axi_rready,
m_axi_bvalid,
m_axi_wready,
m_axi_rvalid,
m_axi_bresp,
m_axi_rresp,
m_axi_rdata,
m_axi_awready,
m_axi_arready,
s_axi_arprot,
s_axi_arvalid,
s_axi_awprot,
s_axi_araddr,
s_axi_awaddr,
s_axi_awvalid);
output [34:0]Q;
output [33:0]\s_axi_rdata[31] ;
output [0:0]s_axi_bvalid;
output [12:0]m_axi_bready;
output [0:0]s_axi_wready;
output [12:0]m_axi_wvalid;
output [12:0]m_axi_awvalid;
output [12:0]m_axi_arvalid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
output [12:0]m_axi_rready;
input aresetn;
input aclk;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_bready;
input [0:0]s_axi_rready;
input [13:0]m_axi_bvalid;
input [13:0]m_axi_wready;
input [13:0]m_axi_rvalid;
input [27:0]m_axi_bresp;
input [27:0]m_axi_rresp;
input [447:0]m_axi_rdata;
input [13:0]m_axi_awready;
input [13:0]m_axi_arready;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
input [2:0]s_axi_awprot;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
input [0:0]s_axi_awvalid;
wire [34:0]Q;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire addr_arbiter_inst_n_106;
wire addr_arbiter_inst_n_107;
wire addr_arbiter_inst_n_109;
wire addr_arbiter_inst_n_110;
wire addr_arbiter_inst_n_124;
wire addr_arbiter_inst_n_128;
wire addr_arbiter_inst_n_3;
wire addr_arbiter_inst_n_4;
wire addr_arbiter_inst_n_5;
wire addr_arbiter_inst_n_57;
wire addr_arbiter_inst_n_58;
wire addr_arbiter_inst_n_59;
wire addr_arbiter_inst_n_6;
wire addr_arbiter_inst_n_60;
wire addr_arbiter_inst_n_61;
wire addr_arbiter_inst_n_63;
wire addr_arbiter_inst_n_64;
wire addr_arbiter_inst_n_7;
wire addr_arbiter_inst_n_92;
wire aresetn;
wire aresetn_d;
wire \gen_decerr.decerr_slave_inst_n_2 ;
wire \gen_decerr.decerr_slave_inst_n_3 ;
wire \gen_decerr.decerr_slave_inst_n_4 ;
wire \gen_decerr.decerr_slave_inst_n_5 ;
wire \gen_decerr.decerr_slave_inst_n_6 ;
wire \gen_decerr.decerr_slave_inst_n_7 ;
wire \gen_decerr.decerr_slave_inst_n_8 ;
wire [3:0]m_atarget_enc;
wire \m_atarget_enc_reg[0]_rep_n_0 ;
wire \m_atarget_enc_reg[1]_rep_n_0 ;
wire [14:0]m_atarget_hot;
wire [14:0]m_atarget_hot0;
wire [13:0]m_axi_arready;
wire [12:0]m_axi_arvalid;
wire [13:0]m_axi_awready;
wire [12:0]m_axi_awvalid;
wire [12:0]m_axi_bready;
wire [27:0]m_axi_bresp;
wire [13:0]m_axi_bvalid;
wire [447:0]m_axi_rdata;
wire [12:0]m_axi_rready;
wire [27:0]m_axi_rresp;
wire [13:0]m_axi_rvalid;
wire [13:0]m_axi_wready;
wire [12:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [2:0]m_ready_d_0;
wire m_valid_i;
wire [14:14]mi_bvalid;
wire [14:14]mi_wready;
wire p_1_in;
wire reg_slice_r_n_2;
wire reg_slice_r_n_37;
wire reg_slice_r_n_38;
wire reg_slice_r_n_39;
wire reg_slice_r_n_40;
wire reg_slice_r_n_41;
wire reg_slice_r_n_42;
wire reg_slice_r_n_43;
wire reg_slice_r_n_44;
wire reg_slice_r_n_45;
wire reg_slice_r_n_46;
wire reg_slice_r_n_47;
wire reg_slice_r_n_48;
wire reset;
wire [31:0]s_axi_araddr;
wire [2:0]s_axi_arprot;
wire [0:0]s_axi_arready;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire \s_axi_bresp[0]_INST_0_i_10_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_12_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_1_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_2_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_3_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_4_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_7_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_8_n_0 ;
wire \s_axi_bresp[0]_INST_0_i_9_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_11_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_3_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_4_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_5_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_7_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_8_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_9_n_0 ;
wire [0:0]s_axi_bvalid;
wire [33:0]\s_axi_rdata[31] ;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire splitter_ar_n_2;
wire splitter_ar_n_3;
wire splitter_ar_n_4;
wire splitter_ar_n_5;
wire splitter_ar_n_6;
wire splitter_aw_n_0;
wire splitter_aw_n_10;
wire splitter_aw_n_11;
wire splitter_aw_n_12;
wire splitter_aw_n_13;
wire splitter_aw_n_14;
wire splitter_aw_n_15;
wire splitter_aw_n_16;
wire splitter_aw_n_4;
wire splitter_aw_n_5;
wire splitter_aw_n_6;
wire splitter_aw_n_7;
wire splitter_aw_n_8;
wire splitter_aw_n_9;
wire sr_rvalid;
system_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_sasd addr_arbiter_inst
(.D({m_atarget_hot0[14:11],m_atarget_hot0[9:0]}),
.E(p_1_in),
.Q(Q),
.aa_grant_rnw(aa_grant_rnw),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axilite.s_axi_bvalid_i_reg (addr_arbiter_inst_n_92),
.\gen_axilite.s_axi_bvalid_i_reg_0 (addr_arbiter_inst_n_106),
.\gen_axilite.s_axi_bvalid_i_reg_1 (addr_arbiter_inst_n_128),
.\gen_axilite.s_axi_rvalid_i_reg (addr_arbiter_inst_n_110),
.m_atarget_enc(m_atarget_enc),
.\m_atarget_enc_reg[0] (addr_arbiter_inst_n_4),
.\m_atarget_enc_reg[0]_0 (splitter_aw_n_15),
.\m_atarget_enc_reg[0]_rep (addr_arbiter_inst_n_58),
.\m_atarget_enc_reg[1] (addr_arbiter_inst_n_5),
.\m_atarget_enc_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_7 ),
.\m_atarget_enc_reg[1]_rep (addr_arbiter_inst_n_57),
.\m_atarget_enc_reg[2] (addr_arbiter_inst_n_6),
.\m_atarget_enc_reg[2]_0 (splitter_aw_n_12),
.\m_atarget_enc_reg[2]_1 (splitter_aw_n_8),
.\m_atarget_enc_reg[2]_2 (splitter_aw_n_7),
.\m_atarget_enc_reg[2]_3 (splitter_aw_n_5),
.\m_atarget_enc_reg[2]_4 (\gen_decerr.decerr_slave_inst_n_3 ),
.\m_atarget_enc_reg[2]_5 (reg_slice_r_n_41),
.\m_atarget_enc_reg[2]_6 (splitter_ar_n_3),
.\m_atarget_enc_reg[2]_7 (splitter_ar_n_2),
.\m_atarget_enc_reg[2]_8 (\gen_decerr.decerr_slave_inst_n_5 ),
.\m_atarget_enc_reg[3] (addr_arbiter_inst_n_7),
.\m_atarget_enc_reg[3]_0 (\gen_decerr.decerr_slave_inst_n_2 ),
.\m_atarget_enc_reg[3]_1 (splitter_aw_n_14),
.\m_atarget_enc_reg[3]_2 (reg_slice_r_n_47),
.\m_atarget_hot_reg[14] ({m_atarget_hot[14:11],m_atarget_hot[9:0]}),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid({m_axi_bvalid[8],m_axi_bvalid[3]}),
.m_axi_rvalid(m_axi_rvalid[3]),
.m_axi_wready({m_axi_wready[13],m_axi_wready[11],m_axi_wready[9],m_axi_wready[7],m_axi_wready[5],m_axi_wready[3],m_axi_wready[1]}),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d_0),
.m_ready_d_0(m_ready_d),
.\m_ready_d_reg[0] (addr_arbiter_inst_n_3),
.\m_ready_d_reg[0]_0 (addr_arbiter_inst_n_63),
.\m_ready_d_reg[0]_1 (addr_arbiter_inst_n_64),
.\m_ready_d_reg[0]_2 (addr_arbiter_inst_n_124),
.\m_ready_d_reg[0]_3 (splitter_aw_n_0),
.\m_ready_d_reg[1] (addr_arbiter_inst_n_61),
.\m_ready_d_reg[2] (addr_arbiter_inst_n_59),
.\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_60),
.m_valid_i(m_valid_i),
.m_valid_i_reg(addr_arbiter_inst_n_107),
.m_valid_i_reg_0(reg_slice_r_n_2),
.mi_bvalid(mi_bvalid),
.mi_wready(mi_wready),
.reset(reset),
.s_axi_araddr(s_axi_araddr),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(addr_arbiter_inst_n_109),
.sr_rvalid(sr_rvalid));
FDRE #(
.INIT(1'b0))
aresetn_d_reg
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
system_xbar_1_axi_crossbar_v2_1_12_decerr_slave \gen_decerr.decerr_slave_inst
(.Q(m_atarget_hot[14]),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axilite.s_axi_awready_i_reg_0 (addr_arbiter_inst_n_128),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_92),
.\gen_no_arbiter.m_grant_hot_i_reg[0] (\gen_decerr.decerr_slave_inst_n_4 ),
.m_atarget_enc(m_atarget_enc),
.\m_atarget_enc_reg[0] (splitter_aw_n_13),
.\m_atarget_enc_reg[0]_0 (splitter_aw_n_10),
.\m_atarget_enc_reg[0]_1 (splitter_aw_n_11),
.\m_atarget_enc_reg[0]_2 (splitter_ar_n_5),
.\m_atarget_enc_reg[2] (splitter_aw_n_6),
.\m_atarget_enc_reg[2]_0 (splitter_ar_n_4),
.\m_atarget_enc_reg[2]_1 (splitter_aw_n_16),
.\m_atarget_enc_reg[2]_2 (reg_slice_r_n_48),
.\m_atarget_enc_reg[3] (splitter_aw_n_4),
.\m_atarget_enc_reg[3]_0 (reg_slice_r_n_46),
.\m_atarget_enc_reg[3]_1 (splitter_ar_n_6),
.m_axi_arready({m_axi_arready[13],m_axi_arready[10],m_axi_arready[6],m_axi_arready[2]}),
.m_axi_awready({m_axi_awready[10],m_axi_awready[2:1]}),
.m_axi_bvalid({m_axi_bvalid[10],m_axi_bvalid[6],m_axi_bvalid[2:1]}),
.m_axi_rvalid({m_axi_rvalid[10],m_axi_rvalid[6],m_axi_rvalid[2]}),
.m_axi_wready({m_axi_wready[10],m_axi_wready[6],m_axi_wready[2]}),
.\m_ready_d_reg[0] (\gen_decerr.decerr_slave_inst_n_3 ),
.\m_ready_d_reg[0]_0 (\gen_decerr.decerr_slave_inst_n_5 ),
.\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_6 ),
.\m_ready_d_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_7 ),
.\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_110),
.\m_ready_d_reg[2] (\gen_decerr.decerr_slave_inst_n_2 ),
.\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_106),
.m_valid_i_reg(\gen_decerr.decerr_slave_inst_n_8 ),
.mi_bvalid(mi_bvalid),
.mi_wready(mi_wready),
.reset(reset));
(* ORIG_CELL_NAME = "m_atarget_enc_reg[0]" *)
FDRE \m_atarget_enc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_4),
.Q(m_atarget_enc[0]),
.R(reset));
(* ORIG_CELL_NAME = "m_atarget_enc_reg[0]" *)
FDRE \m_atarget_enc_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_58),
.Q(\m_atarget_enc_reg[0]_rep_n_0 ),
.R(reset));
(* ORIG_CELL_NAME = "m_atarget_enc_reg[1]" *)
FDRE \m_atarget_enc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_5),
.Q(m_atarget_enc[1]),
.R(reset));
(* ORIG_CELL_NAME = "m_atarget_enc_reg[1]" *)
FDRE \m_atarget_enc_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_57),
.Q(\m_atarget_enc_reg[1]_rep_n_0 ),
.R(reset));
FDRE \m_atarget_enc_reg[2]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_6),
.Q(m_atarget_enc[2]),
.R(reset));
FDRE \m_atarget_enc_reg[3]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_7),
.Q(m_atarget_enc[3]),
.R(reset));
FDRE \m_atarget_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[0]),
.Q(m_atarget_hot[0]),
.R(reset));
FDRE \m_atarget_hot_reg[11]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[11]),
.Q(m_atarget_hot[11]),
.R(reset));
FDRE \m_atarget_hot_reg[12]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[12]),
.Q(m_atarget_hot[12]),
.R(reset));
FDRE \m_atarget_hot_reg[13]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[13]),
.Q(m_atarget_hot[13]),
.R(reset));
FDRE \m_atarget_hot_reg[14]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[14]),
.Q(m_atarget_hot[14]),
.R(reset));
FDRE \m_atarget_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[1]),
.Q(m_atarget_hot[1]),
.R(reset));
FDRE \m_atarget_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[2]),
.Q(m_atarget_hot[2]),
.R(reset));
FDRE \m_atarget_hot_reg[3]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[3]),
.Q(m_atarget_hot[3]),
.R(reset));
FDRE \m_atarget_hot_reg[4]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[4]),
.Q(m_atarget_hot[4]),
.R(reset));
FDRE \m_atarget_hot_reg[5]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[5]),
.Q(m_atarget_hot[5]),
.R(reset));
FDRE \m_atarget_hot_reg[6]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[6]),
.Q(m_atarget_hot[6]),
.R(reset));
FDRE \m_atarget_hot_reg[7]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[7]),
.Q(m_atarget_hot[7]),
.R(reset));
FDRE \m_atarget_hot_reg[8]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[8]),
.Q(m_atarget_hot[8]),
.R(reset));
FDRE \m_atarget_hot_reg[9]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0[9]),
.Q(m_atarget_hot[9]),
.R(reset));
system_xbar_1_axi_register_slice_v2_1_11_axic_register_slice reg_slice_r
(.E(p_1_in),
.Q({\s_axi_rdata[31] ,reg_slice_r_n_37}),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.m_atarget_enc(m_atarget_enc),
.\m_atarget_enc_reg[0]_rep (\m_atarget_enc_reg[0]_rep_n_0 ),
.\m_atarget_enc_reg[1] (\gen_decerr.decerr_slave_inst_n_8 ),
.\m_atarget_enc_reg[1]_rep (\m_atarget_enc_reg[1]_rep_n_0 ),
.\m_atarget_hot_reg[13] ({m_atarget_hot[13:11],m_atarget_hot[9:0]}),
.m_axi_rdata(m_axi_rdata),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid({m_axi_rvalid[13:11],m_axi_rvalid[9:7],m_axi_rvalid[5:4],m_axi_rvalid[1:0]}),
.\m_payload_i_reg[1]_0 (reg_slice_r_n_39),
.\m_payload_i_reg[1]_1 (reg_slice_r_n_40),
.\m_payload_i_reg[1]_2 (reg_slice_r_n_41),
.\m_payload_i_reg[2]_0 (reg_slice_r_n_38),
.\m_payload_i_reg[2]_1 (reg_slice_r_n_42),
.\m_payload_i_reg[2]_2 (reg_slice_r_n_43),
.m_ready_d(m_ready_d[0]),
.\m_ready_d_reg[0] (addr_arbiter_inst_n_107),
.\m_ready_d_reg[1] (reg_slice_r_n_2),
.m_valid_i(m_valid_i),
.m_valid_i_reg_0(reg_slice_r_n_47),
.m_valid_i_reg_1(reg_slice_r_n_48),
.m_valid_i_reg_2(addr_arbiter_inst_n_109),
.reset(reset),
.s_axi_rready(s_axi_rready),
.\skid_buffer_reg[3]_0 (reg_slice_r_n_44),
.\skid_buffer_reg[3]_1 (reg_slice_r_n_45),
.\skid_buffer_reg[3]_2 (reg_slice_r_n_46),
.sr_rvalid(sr_rvalid));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF2))
\s_axi_bresp[0]_INST_0
(.I0(m_axi_bresp[2]),
.I1(\s_axi_bresp[0]_INST_0_i_1_n_0 ),
.I2(reg_slice_r_n_43),
.I3(\s_axi_bresp[0]_INST_0_i_2_n_0 ),
.I4(\s_axi_bresp[0]_INST_0_i_3_n_0 ),
.I5(\s_axi_bresp[0]_INST_0_i_4_n_0 ),
.O(s_axi_bresp[0]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'hFEFF))
\s_axi_bresp[0]_INST_0_i_1
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\s_axi_bresp[0]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'hDFFF))
\s_axi_bresp[0]_INST_0_i_10
(.I0(m_atarget_enc[3]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\s_axi_bresp[0]_INST_0_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'hDFFF))
\s_axi_bresp[0]_INST_0_i_12
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\s_axi_bresp[0]_INST_0_i_12_n_0 ));
LUT6 #(
.INIT(64'h0308000000080000))
\s_axi_bresp[0]_INST_0_i_2
(.I0(m_axi_bresp[10]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_bresp[6]),
.O(\s_axi_bresp[0]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFF22F2))
\s_axi_bresp[0]_INST_0_i_3
(.I0(m_axi_bresp[8]),
.I1(reg_slice_r_n_38),
.I2(m_axi_bresp[12]),
.I3(reg_slice_r_n_40),
.I4(\s_axi_bresp[0]_INST_0_i_7_n_0 ),
.O(\s_axi_bresp[0]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hEFEEFFFFEFEEEFEE))
\s_axi_bresp[0]_INST_0_i_4
(.I0(\s_axi_bresp[0]_INST_0_i_8_n_0 ),
.I1(\s_axi_bresp[0]_INST_0_i_9_n_0 ),
.I2(\s_axi_bresp[0]_INST_0_i_10_n_0 ),
.I3(m_axi_bresp[22]),
.I4(reg_slice_r_n_44),
.I5(m_axi_bresp[0]),
.O(\s_axi_bresp[0]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'h0080000C00800000))
\s_axi_bresp[0]_INST_0_i_7
(.I0(m_axi_bresp[26]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_bresp[16]),
.O(\s_axi_bresp[0]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\s_axi_bresp[0]_INST_0_i_8
(.I0(\s_axi_bresp[1]_INST_0_i_11_n_0 ),
.I1(m_axi_bresp[4]),
.I2(m_axi_bresp[18]),
.I3(reg_slice_r_n_39),
.I4(m_axi_bresp[14]),
.I5(\s_axi_bresp[0]_INST_0_i_12_n_0 ),
.O(\s_axi_bresp[0]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'h000020C000002000))
\s_axi_bresp[0]_INST_0_i_9
(.I0(m_axi_bresp[20]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_bresp[24]),
.O(\s_axi_bresp[0]_INST_0_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF2))
\s_axi_bresp[1]_INST_0
(.I0(m_axi_bresp[19]),
.I1(reg_slice_r_n_39),
.I2(reg_slice_r_n_43),
.I3(\s_axi_bresp[1]_INST_0_i_3_n_0 ),
.I4(\s_axi_bresp[1]_INST_0_i_4_n_0 ),
.I5(\s_axi_bresp[1]_INST_0_i_5_n_0 ),
.O(s_axi_bresp[1]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'hFEFF))
\s_axi_bresp[1]_INST_0_i_11
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.O(\s_axi_bresp[1]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'h0008000300080000))
\s_axi_bresp[1]_INST_0_i_3
(.I0(m_axi_bresp[11]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_bresp[1]),
.O(\s_axi_bresp[1]_INST_0_i_3_n_0 ));
LUT5 #(
.INIT(32'hFFFF22F2))
\s_axi_bresp[1]_INST_0_i_4
(.I0(m_axi_bresp[7]),
.I1(reg_slice_r_n_41),
.I2(m_axi_bresp[3]),
.I3(\s_axi_bresp[0]_INST_0_i_1_n_0 ),
.I4(\s_axi_bresp[1]_INST_0_i_7_n_0 ),
.O(\s_axi_bresp[1]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hEFEEFFFFEFEEEFEE))
\s_axi_bresp[1]_INST_0_i_5
(.I0(\s_axi_bresp[1]_INST_0_i_8_n_0 ),
.I1(\s_axi_bresp[1]_INST_0_i_9_n_0 ),
.I2(reg_slice_r_n_42),
.I3(m_axi_bresp[17]),
.I4(\s_axi_bresp[1]_INST_0_i_11_n_0 ),
.I5(m_axi_bresp[5]),
.O(\s_axi_bresp[1]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h200C000020000000))
\s_axi_bresp[1]_INST_0_i_7
(.I0(m_axi_bresp[15]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_bresp[21]),
.O(\s_axi_bresp[1]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\s_axi_bresp[1]_INST_0_i_8
(.I0(\s_axi_bresp[0]_INST_0_i_10_n_0 ),
.I1(m_axi_bresp[23]),
.I2(m_axi_bresp[25]),
.I3(reg_slice_r_n_45),
.I4(m_axi_bresp[13]),
.I5(reg_slice_r_n_40),
.O(\s_axi_bresp[1]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'h00C0000800000008))
\s_axi_bresp[1]_INST_0_i_9
(.I0(m_axi_bresp[9]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_bresp[27]),
.O(\s_axi_bresp[1]_INST_0_i_9_n_0 ));
system_xbar_1_axi_crossbar_v2_1_12_splitter__parameterized0 splitter_ar
(.Q(reg_slice_r_n_37),
.aclk(aclk),
.aresetn_d(aresetn_d),
.aresetn_d_reg(addr_arbiter_inst_n_3),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_124),
.m_atarget_enc(m_atarget_enc),
.\m_atarget_enc_reg[0] (splitter_aw_n_9),
.\m_atarget_enc_reg[2] (\gen_decerr.decerr_slave_inst_n_6 ),
.m_axi_arready({m_axi_arready[13:11],m_axi_arready[9:7],m_axi_arready[5:0]}),
.m_ready_d(m_ready_d),
.\m_ready_d_reg[0]_0 (splitter_ar_n_5),
.\m_ready_d_reg[0]_1 (splitter_ar_n_6),
.\m_ready_d_reg[1]_0 (splitter_ar_n_2),
.\m_ready_d_reg[1]_1 (splitter_ar_n_3),
.\m_ready_d_reg[1]_2 (splitter_ar_n_4),
.\m_ready_d_reg[1]_3 (addr_arbiter_inst_n_110),
.m_valid_i_reg(reg_slice_r_n_2),
.s_axi_rready(s_axi_rready),
.sr_rvalid(sr_rvalid));
system_xbar_1_axi_crossbar_v2_1_12_splitter splitter_aw
(.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_no_arbiter.m_grant_hot_i_reg[0] (splitter_aw_n_0),
.m_atarget_enc(m_atarget_enc),
.\m_atarget_enc_reg[1] (addr_arbiter_inst_n_61),
.\m_atarget_enc_reg[2] (\gen_decerr.decerr_slave_inst_n_4 ),
.m_axi_awready({m_axi_awready[13:11],m_axi_awready[9:3],m_axi_awready[0]}),
.m_axi_bvalid({m_axi_bvalid[13:11],m_axi_bvalid[9:4],m_axi_bvalid[1:0]}),
.m_axi_wready({m_axi_wready[12],m_axi_wready[8],m_axi_wready[4],m_axi_wready[0]}),
.m_ready_d(m_ready_d_0),
.\m_ready_d_reg[0]_0 (splitter_aw_n_5),
.\m_ready_d_reg[0]_1 (splitter_aw_n_6),
.\m_ready_d_reg[0]_2 (splitter_aw_n_7),
.\m_ready_d_reg[0]_3 (splitter_aw_n_11),
.\m_ready_d_reg[0]_4 (splitter_aw_n_14),
.\m_ready_d_reg[0]_5 (splitter_aw_n_15),
.\m_ready_d_reg[0]_6 (addr_arbiter_inst_n_64),
.\m_ready_d_reg[0]_7 (addr_arbiter_inst_n_63),
.\m_ready_d_reg[1]_0 (splitter_aw_n_16),
.\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_60),
.\m_ready_d_reg[2]_0 (splitter_aw_n_4),
.\m_ready_d_reg[2]_1 (splitter_aw_n_8),
.\m_ready_d_reg[2]_2 (splitter_aw_n_9),
.\m_ready_d_reg[2]_3 (splitter_aw_n_10),
.\m_ready_d_reg[2]_4 (splitter_aw_n_12),
.\m_ready_d_reg[2]_5 (splitter_aw_n_13),
.\m_ready_d_reg[2]_6 (addr_arbiter_inst_n_59),
.s_axi_bready(s_axi_bready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_decerr_slave" *)
module system_xbar_1_axi_crossbar_v2_1_12_decerr_slave
(mi_bvalid,
mi_wready,
\m_ready_d_reg[2] ,
\m_ready_d_reg[0] ,
\gen_no_arbiter.m_grant_hot_i_reg[0] ,
\m_ready_d_reg[0]_0 ,
\m_ready_d_reg[1] ,
\m_ready_d_reg[1]_0 ,
m_valid_i_reg,
reset,
\gen_axilite.s_axi_awready_i_reg_0 ,
aclk,
\m_atarget_enc_reg[3] ,
\m_atarget_enc_reg[0] ,
\m_atarget_enc_reg[3]_0 ,
m_axi_awready,
\m_atarget_enc_reg[0]_0 ,
m_atarget_enc,
\m_atarget_enc_reg[2] ,
m_axi_bvalid,
\m_atarget_enc_reg[0]_1 ,
\m_atarget_enc_reg[2]_0 ,
\m_atarget_enc_reg[3]_1 ,
m_axi_arready,
\m_atarget_enc_reg[0]_2 ,
\m_atarget_enc_reg[2]_1 ,
m_axi_wready,
\m_atarget_enc_reg[2]_2 ,
m_axi_rvalid,
\m_ready_d_reg[1]_1 ,
aa_rready,
Q,
aresetn_d,
\gen_no_arbiter.grant_rnw_reg ,
\m_ready_d_reg[2]_0 );
output [0:0]mi_bvalid;
output [0:0]mi_wready;
output \m_ready_d_reg[2] ;
output \m_ready_d_reg[0] ;
output \gen_no_arbiter.m_grant_hot_i_reg[0] ;
output \m_ready_d_reg[0]_0 ;
output \m_ready_d_reg[1] ;
output \m_ready_d_reg[1]_0 ;
output m_valid_i_reg;
input reset;
input \gen_axilite.s_axi_awready_i_reg_0 ;
input aclk;
input \m_atarget_enc_reg[3] ;
input \m_atarget_enc_reg[0] ;
input \m_atarget_enc_reg[3]_0 ;
input [2:0]m_axi_awready;
input \m_atarget_enc_reg[0]_0 ;
input [3:0]m_atarget_enc;
input \m_atarget_enc_reg[2] ;
input [3:0]m_axi_bvalid;
input \m_atarget_enc_reg[0]_1 ;
input \m_atarget_enc_reg[2]_0 ;
input \m_atarget_enc_reg[3]_1 ;
input [3:0]m_axi_arready;
input \m_atarget_enc_reg[0]_2 ;
input \m_atarget_enc_reg[2]_1 ;
input [2:0]m_axi_wready;
input \m_atarget_enc_reg[2]_2 ;
input [2:0]m_axi_rvalid;
input \m_ready_d_reg[1]_1 ;
input aa_rready;
input [0:0]Q;
input aresetn_d;
input \gen_no_arbiter.grant_rnw_reg ;
input \m_ready_d_reg[2]_0 ;
wire [0:0]Q;
wire aa_rready;
wire aclk;
wire aresetn_d;
wire \gen_axilite.s_axi_arready_i_i_1_n_0 ;
wire \gen_axilite.s_axi_awready_i_i_1_n_0 ;
wire \gen_axilite.s_axi_awready_i_reg_0 ;
wire \gen_axilite.s_axi_rvalid_i_i_1_n_0 ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire \gen_no_arbiter.m_grant_hot_i_reg[0] ;
wire [3:0]m_atarget_enc;
wire \m_atarget_enc_reg[0] ;
wire \m_atarget_enc_reg[0]_0 ;
wire \m_atarget_enc_reg[0]_1 ;
wire \m_atarget_enc_reg[0]_2 ;
wire \m_atarget_enc_reg[2] ;
wire \m_atarget_enc_reg[2]_0 ;
wire \m_atarget_enc_reg[2]_1 ;
wire \m_atarget_enc_reg[2]_2 ;
wire \m_atarget_enc_reg[3] ;
wire \m_atarget_enc_reg[3]_0 ;
wire \m_atarget_enc_reg[3]_1 ;
wire [3:0]m_axi_arready;
wire [2:0]m_axi_awready;
wire [3:0]m_axi_bvalid;
wire [2:0]m_axi_rvalid;
wire [2:0]m_axi_wready;
wire \m_ready_d[1]_i_9_n_0 ;
wire \m_ready_d[2]_i_9_n_0 ;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[2] ;
wire \m_ready_d_reg[2]_0 ;
wire m_valid_i_i_10_n_0;
wire m_valid_i_reg;
wire [14:14]mi_arready;
wire [0:0]mi_bvalid;
wire [14:14]mi_rvalid;
wire [0:0]mi_wready;
wire reset;
wire \s_axi_bvalid[0]_INST_0_i_11_n_0 ;
wire \s_axi_wready[0]_INST_0_i_7_n_0 ;
LUT5 #(
.INIT(32'hA2A282A2))
\gen_axilite.s_axi_arready_i_i_1
(.I0(aresetn_d),
.I1(mi_rvalid),
.I2(mi_arready),
.I3(Q),
.I4(\m_ready_d_reg[1]_1 ),
.O(\gen_axilite.s_axi_arready_i_i_1_n_0 ));
FDRE \gen_axilite.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready),
.R(1'b0));
LUT5 #(
.INIT(32'hFFBF0040))
\gen_axilite.s_axi_awready_i_i_1
(.I0(mi_bvalid),
.I1(\gen_no_arbiter.grant_rnw_reg ),
.I2(Q),
.I3(\m_ready_d_reg[2]_0 ),
.I4(mi_wready),
.O(\gen_axilite.s_axi_awready_i_i_1_n_0 ));
FDRE \gen_axilite.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_awready_i_i_1_n_0 ),
.Q(mi_wready),
.R(reset));
FDRE \gen_axilite.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_awready_i_reg_0 ),
.Q(mi_bvalid),
.R(reset));
LUT5 #(
.INIT(32'h0FFF4400))
\gen_axilite.s_axi_rvalid_i_i_1
(.I0(\m_ready_d_reg[1]_1 ),
.I1(mi_arready),
.I2(aa_rready),
.I3(Q),
.I4(mi_rvalid),
.O(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ));
FDRE \gen_axilite.s_axi_rvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axilite.s_axi_rvalid_i_i_1_n_0 ),
.Q(mi_rvalid),
.R(reset));
LUT6 #(
.INIT(64'h4044FFFF40444044))
\m_ready_d[0]_i_5
(.I0(\m_atarget_enc_reg[2]_0 ),
.I1(\m_atarget_enc_reg[0] ),
.I2(\m_atarget_enc_reg[3]_1 ),
.I3(m_axi_arready[3]),
.I4(\m_ready_d[1]_i_9_n_0 ),
.I5(\m_atarget_enc_reg[0]_2 ),
.O(\m_ready_d_reg[0]_0 ));
LUT6 #(
.INIT(64'h000000000000FD00))
\m_ready_d[1]_i_5
(.I0(m_axi_arready[0]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(\m_ready_d[1]_i_9_n_0 ),
.O(\m_ready_d_reg[1] ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\m_ready_d[1]_i_9
(.I0(mi_arready),
.I1(m_axi_arready[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.I4(m_axi_arready[2]),
.O(\m_ready_d[1]_i_9_n_0 ));
LUT6 #(
.INIT(64'h000000000000F700))
\m_ready_d[2]_i_14
(.I0(m_axi_bvalid[2]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(\s_axi_bvalid[0]_INST_0_i_11_n_0 ),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0] ));
LUT6 #(
.INIT(64'h4044FFFF40444044))
\m_ready_d[2]_i_4
(.I0(\m_atarget_enc_reg[3] ),
.I1(\m_atarget_enc_reg[0] ),
.I2(\m_atarget_enc_reg[3]_0 ),
.I3(m_axi_awready[0]),
.I4(\m_ready_d[2]_i_9_n_0 ),
.I5(\m_atarget_enc_reg[0]_0 ),
.O(\m_ready_d_reg[2] ));
LUT5 #(
.INIT(32'hF0CA00CA))
\m_ready_d[2]_i_9
(.I0(m_axi_awready[1]),
.I1(m_axi_awready[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(mi_wready),
.O(\m_ready_d[2]_i_9_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
m_valid_i_i_10
(.I0(mi_rvalid),
.I1(m_axi_rvalid[1]),
.I2(m_atarget_enc[2]),
.I3(m_axi_rvalid[2]),
.I4(m_atarget_enc[3]),
.I5(m_axi_rvalid[0]),
.O(m_valid_i_i_10_n_0));
MUXF7 m_valid_i_reg_i_6
(.I0(\m_atarget_enc_reg[2]_2 ),
.I1(m_valid_i_i_10_n_0),
.O(m_valid_i_reg),
.S(m_atarget_enc[1]));
LUT5 #(
.INIT(32'hFA0C0A0C))
\s_axi_bvalid[0]_INST_0_i_11
(.I0(m_axi_bvalid[3]),
.I1(m_axi_bvalid[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.I4(mi_bvalid),
.O(\s_axi_bvalid[0]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'h4044FFFF40444044))
\s_axi_bvalid[0]_INST_0_i_6
(.I0(\m_atarget_enc_reg[2] ),
.I1(\m_atarget_enc_reg[0] ),
.I2(\m_atarget_enc_reg[3]_0 ),
.I3(m_axi_bvalid[0]),
.I4(\s_axi_bvalid[0]_INST_0_i_11_n_0 ),
.I5(\m_atarget_enc_reg[0]_1 ),
.O(\m_ready_d_reg[0] ));
MUXF7 \s_axi_wready[0]_INST_0_i_5
(.I0(\m_atarget_enc_reg[2]_1 ),
.I1(\s_axi_wready[0]_INST_0_i_7_n_0 ),
.O(\m_ready_d_reg[1]_0 ),
.S(m_atarget_enc[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_wready[0]_INST_0_i_7
(.I0(mi_wready),
.I1(m_axi_wready[1]),
.I2(m_atarget_enc[2]),
.I3(m_axi_wready[2]),
.I4(m_atarget_enc[3]),
.I5(m_axi_wready[0]),
.O(\s_axi_wready[0]_INST_0_i_7_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_splitter" *)
module system_xbar_1_axi_crossbar_v2_1_12_splitter
(\gen_no_arbiter.m_grant_hot_i_reg[0] ,
m_ready_d,
\m_ready_d_reg[2]_0 ,
\m_ready_d_reg[0]_0 ,
\m_ready_d_reg[0]_1 ,
\m_ready_d_reg[0]_2 ,
\m_ready_d_reg[2]_1 ,
\m_ready_d_reg[2]_2 ,
\m_ready_d_reg[2]_3 ,
\m_ready_d_reg[0]_3 ,
\m_ready_d_reg[2]_4 ,
\m_ready_d_reg[2]_5 ,
\m_ready_d_reg[0]_4 ,
\m_ready_d_reg[0]_5 ,
\m_ready_d_reg[1]_0 ,
\m_ready_d_reg[0]_6 ,
\m_atarget_enc_reg[2] ,
s_axi_bready,
m_axi_awready,
m_atarget_enc,
m_axi_bvalid,
m_axi_wready,
\m_ready_d_reg[2]_6 ,
aresetn_d,
\m_ready_d_reg[1]_1 ,
s_axi_wvalid,
\m_atarget_enc_reg[1] ,
\m_ready_d_reg[0]_7 ,
aclk);
output \gen_no_arbiter.m_grant_hot_i_reg[0] ;
output [2:0]m_ready_d;
output \m_ready_d_reg[2]_0 ;
output \m_ready_d_reg[0]_0 ;
output \m_ready_d_reg[0]_1 ;
output \m_ready_d_reg[0]_2 ;
output \m_ready_d_reg[2]_1 ;
output \m_ready_d_reg[2]_2 ;
output \m_ready_d_reg[2]_3 ;
output \m_ready_d_reg[0]_3 ;
output \m_ready_d_reg[2]_4 ;
output \m_ready_d_reg[2]_5 ;
output \m_ready_d_reg[0]_4 ;
output \m_ready_d_reg[0]_5 ;
output \m_ready_d_reg[1]_0 ;
input \m_ready_d_reg[0]_6 ;
input \m_atarget_enc_reg[2] ;
input [0:0]s_axi_bready;
input [10:0]m_axi_awready;
input [3:0]m_atarget_enc;
input [10:0]m_axi_bvalid;
input [3:0]m_axi_wready;
input \m_ready_d_reg[2]_6 ;
input aresetn_d;
input \m_ready_d_reg[1]_1 ;
input [0:0]s_axi_wvalid;
input \m_atarget_enc_reg[1] ;
input \m_ready_d_reg[0]_7 ;
input aclk;
wire aclk;
wire aresetn_d;
wire \gen_no_arbiter.m_grant_hot_i_reg[0] ;
wire [3:0]m_atarget_enc;
wire \m_atarget_enc_reg[1] ;
wire \m_atarget_enc_reg[2] ;
wire [10:0]m_axi_awready;
wire [10:0]m_axi_bvalid;
wire [3:0]m_axi_wready;
wire [2:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d[2]_i_11_n_0 ;
wire \m_ready_d[2]_i_13_n_0 ;
wire \m_ready_d[2]_i_15_n_0 ;
wire \m_ready_d[2]_i_1_n_0 ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[0]_1 ;
wire \m_ready_d_reg[0]_2 ;
wire \m_ready_d_reg[0]_3 ;
wire \m_ready_d_reg[0]_4 ;
wire \m_ready_d_reg[0]_5 ;
wire \m_ready_d_reg[0]_6 ;
wire \m_ready_d_reg[0]_7 ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[2]_0 ;
wire \m_ready_d_reg[2]_1 ;
wire \m_ready_d_reg[2]_2 ;
wire \m_ready_d_reg[2]_3 ;
wire \m_ready_d_reg[2]_4 ;
wire \m_ready_d_reg[2]_5 ;
wire \m_ready_d_reg[2]_6 ;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_wvalid;
LUT5 #(
.INIT(32'h0000BA00))
\m_ready_d[0]_i_1
(.I0(m_ready_d[0]),
.I1(\m_ready_d_reg[0]_7 ),
.I2(s_axi_bready),
.I3(aresetn_d),
.I4(\m_ready_d_reg[1]_1 ),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0000F200))
\m_ready_d[1]_i_1
(.I0(s_axi_wvalid),
.I1(\m_atarget_enc_reg[1] ),
.I2(m_ready_d[1]),
.I3(aresetn_d),
.I4(\m_ready_d_reg[1]_1 ),
.O(\m_ready_d[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'h04))
\m_ready_d[2]_i_1
(.I0(\m_ready_d_reg[2]_6 ),
.I1(aresetn_d),
.I2(\m_ready_d_reg[1]_1 ),
.O(\m_ready_d[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT5 #(
.INIT(32'h40444444))
\m_ready_d[2]_i_10
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(m_axi_awready[4]),
.O(\m_ready_d_reg[2]_3 ));
LUT5 #(
.INIT(32'hF0AC00AC))
\m_ready_d[2]_i_11
(.I0(m_axi_awready[6]),
.I1(m_axi_awready[0]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(m_axi_awready[9]),
.O(\m_ready_d[2]_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT2 #(
.INIT(4'h7))
\m_ready_d[2]_i_12
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.O(\m_ready_d_reg[2]_2 ));
LUT6 #(
.INIT(64'h0000000011011111))
\m_ready_d[2]_i_13
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(m_axi_bvalid[6]),
.I5(\m_ready_d_reg[0]_0 ),
.O(\m_ready_d[2]_i_13_n_0 ));
LUT6 #(
.INIT(64'h000000000000FD00))
\m_ready_d[2]_i_15
(.I0(m_axi_bvalid[1]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(\m_ready_d_reg[0]_1 ),
.O(\m_ready_d[2]_i_15_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFF08))
\m_ready_d[2]_i_5
(.I0(m_axi_awready[2]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(\m_ready_d[2]_i_11_n_0 ),
.O(\m_ready_d_reg[2]_4 ));
LUT6 #(
.INIT(64'h00000000FF33550F))
\m_ready_d[2]_i_6
(.I0(m_axi_awready[5]),
.I1(m_axi_awready[8]),
.I2(m_axi_awready[1]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[3]),
.I5(\m_ready_d_reg[2]_2 ),
.O(\m_ready_d_reg[2]_1 ));
LUT6 #(
.INIT(64'h5555555455555555))
\m_ready_d[2]_i_7
(.I0(m_ready_d[0]),
.I1(\m_ready_d_reg[0]_6 ),
.I2(\m_ready_d[2]_i_13_n_0 ),
.I3(\m_atarget_enc_reg[2] ),
.I4(\m_ready_d[2]_i_15_n_0 ),
.I5(s_axi_bready),
.O(\gen_no_arbiter.m_grant_hot_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'hAFC0A0C0))
\m_ready_d[2]_i_8
(.I0(m_axi_awready[10]),
.I1(m_axi_awready[7]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(m_axi_awready[3]),
.O(\m_ready_d_reg[2]_0 ));
FDRE \m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE \m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
FDRE \m_ready_d_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[2]_i_1_n_0 ),
.Q(m_ready_d[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT5 #(
.INIT(32'h40444444))
\s_axi_bvalid[0]_INST_0_i_12
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(m_axi_bvalid[4]),
.O(\m_ready_d_reg[0]_3 ));
LUT2 #(
.INIT(4'hE))
\s_axi_bvalid[0]_INST_0_i_3
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.O(\m_ready_d_reg[0]_5 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT2 #(
.INIT(4'hB))
\s_axi_bvalid[0]_INST_0_i_4
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.O(\m_ready_d_reg[0]_2 ));
LUT5 #(
.INIT(32'hA0FCA00C))
\s_axi_bvalid[0]_INST_0_i_5
(.I0(m_axi_bvalid[9]),
.I1(m_axi_bvalid[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.I4(m_axi_bvalid[2]),
.O(\m_ready_d_reg[0]_0 ));
LUT6 #(
.INIT(64'hDD0C000000000000))
\s_axi_bvalid[0]_INST_0_i_7
(.I0(m_axi_bvalid[5]),
.I1(m_atarget_enc[3]),
.I2(m_axi_bvalid[8]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[1]),
.O(\m_ready_d_reg[0]_4 ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\s_axi_bvalid[0]_INST_0_i_8
(.I0(m_axi_bvalid[10]),
.I1(m_axi_bvalid[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.I4(m_axi_bvalid[7]),
.O(\m_ready_d_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT2 #(
.INIT(4'h2))
\s_axi_bvalid[0]_INST_0_i_9
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.O(\m_ready_d_reg[2]_5 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_wready[0]_INST_0_i_6
(.I0(m_axi_wready[3]),
.I1(m_axi_wready[1]),
.I2(m_atarget_enc[2]),
.I3(m_axi_wready[2]),
.I4(m_atarget_enc[3]),
.I5(m_axi_wready[0]),
.O(\m_ready_d_reg[1]_0 ));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_12_splitter" *)
module system_xbar_1_axi_crossbar_v2_1_12_splitter__parameterized0
(m_ready_d,
\m_ready_d_reg[1]_0 ,
\m_ready_d_reg[1]_1 ,
\m_ready_d_reg[1]_2 ,
\m_ready_d_reg[0]_0 ,
\m_ready_d_reg[0]_1 ,
\m_atarget_enc_reg[2] ,
\m_ready_d_reg[1]_3 ,
m_axi_arready,
m_atarget_enc,
\m_atarget_enc_reg[0] ,
aresetn_d,
m_valid_i_reg,
sr_rvalid,
Q,
s_axi_rready,
\gen_no_arbiter.grant_rnw_reg ,
aresetn_d_reg,
aclk);
output [1:0]m_ready_d;
output \m_ready_d_reg[1]_0 ;
output \m_ready_d_reg[1]_1 ;
output \m_ready_d_reg[1]_2 ;
output \m_ready_d_reg[0]_0 ;
output \m_ready_d_reg[0]_1 ;
input \m_atarget_enc_reg[2] ;
input \m_ready_d_reg[1]_3 ;
input [11:0]m_axi_arready;
input [3:0]m_atarget_enc;
input \m_atarget_enc_reg[0] ;
input aresetn_d;
input m_valid_i_reg;
input sr_rvalid;
input [0:0]Q;
input [0:0]s_axi_rready;
input \gen_no_arbiter.grant_rnw_reg ;
input aresetn_d_reg;
input aclk;
wire [0:0]Q;
wire aclk;
wire aresetn_d;
wire aresetn_d_reg;
wire \gen_no_arbiter.grant_rnw_reg ;
wire [3:0]m_atarget_enc;
wire \m_atarget_enc_reg[0] ;
wire \m_atarget_enc_reg[2] ;
wire [11:0]m_axi_arready;
wire [1:0]m_ready_d;
wire [1:1]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_10_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d[1]_i_4_n_0 ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[0]_1 ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[1]_2 ;
wire \m_ready_d_reg[1]_3 ;
wire m_valid_i_reg;
wire [0:0]s_axi_rready;
wire sr_rvalid;
LUT6 #(
.INIT(64'h00000000FFFF0080))
\m_ready_d[0]_i_1
(.I0(sr_rvalid),
.I1(Q),
.I2(s_axi_rready),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.I4(m_ready_d[0]),
.I5(aresetn_d_reg),
.O(\m_ready_d[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT2 #(
.INIT(4'h7))
\m_ready_d[0]_i_6
(.I0(m_atarget_enc[3]),
.I1(m_atarget_enc[2]),
.O(\m_ready_d_reg[0]_1 ));
LUT5 #(
.INIT(32'h44404444))
\m_ready_d[0]_i_7
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(m_axi_arready[2]),
.O(\m_ready_d_reg[0]_0 ));
LUT3 #(
.INIT(8'h80))
\m_ready_d[1]_i_1
(.I0(aresetn_d),
.I1(m_ready_d0),
.I2(m_valid_i_reg),
.O(\m_ready_d[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFA0C0A0C))
\m_ready_d[1]_i_10
(.I0(m_axi_arready[7]),
.I1(m_axi_arready[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.I4(m_axi_arready[10]),
.O(\m_ready_d[1]_i_10_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAABAA))
\m_ready_d[1]_i_2
(.I0(m_ready_d[1]),
.I1(\m_ready_d[1]_i_4_n_0 ),
.I2(\m_atarget_enc_reg[2] ),
.I3(\m_ready_d_reg[1]_0 ),
.I4(\m_ready_d_reg[1]_1 ),
.I5(\m_ready_d_reg[1]_3 ),
.O(m_ready_d0));
LUT6 #(
.INIT(64'h0000000000007F00))
\m_ready_d[1]_i_4
(.I0(m_axi_arready[11]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(\m_ready_d_reg[1]_2 ),
.O(\m_ready_d[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFF08))
\m_ready_d[1]_i_6
(.I0(m_axi_arready[4]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(\m_ready_d[1]_i_10_n_0 ),
.O(\m_ready_d_reg[1]_0 ));
LUT6 #(
.INIT(64'h00000000FF33550F))
\m_ready_d[1]_i_7
(.I0(m_axi_arready[6]),
.I1(m_axi_arready[9]),
.I2(m_axi_arready[3]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[3]),
.I5(\m_atarget_enc_reg[0] ),
.O(\m_ready_d_reg[1]_1 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT5 #(
.INIT(32'h0ACF0AC0))
\m_ready_d[1]_i_8
(.I0(m_axi_arready[8]),
.I1(m_axi_arready[5]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.I4(m_axi_arready[1]),
.O(\m_ready_d_reg[1]_2 ));
FDRE \m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE \m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_11_axic_register_slice" *)
module system_xbar_1_axi_register_slice_v2_1_11_axic_register_slice
(sr_rvalid,
aa_rready,
\m_ready_d_reg[1] ,
Q,
\m_payload_i_reg[2]_0 ,
\m_payload_i_reg[1]_0 ,
\m_payload_i_reg[1]_1 ,
\m_payload_i_reg[1]_2 ,
\m_payload_i_reg[2]_1 ,
\m_payload_i_reg[2]_2 ,
\skid_buffer_reg[3]_0 ,
\skid_buffer_reg[3]_1 ,
\skid_buffer_reg[3]_2 ,
m_valid_i_reg_0,
m_valid_i_reg_1,
m_axi_rready,
aclk,
m_valid_i_reg_2,
\m_ready_d_reg[0] ,
m_atarget_enc,
\m_atarget_enc_reg[1] ,
s_axi_rready,
aa_grant_rnw,
m_valid_i,
m_ready_d,
m_axi_rresp,
m_axi_rdata,
\m_atarget_enc_reg[1]_rep ,
\m_atarget_enc_reg[0]_rep ,
m_axi_rvalid,
\m_atarget_hot_reg[13] ,
reset,
E);
output sr_rvalid;
output aa_rready;
output \m_ready_d_reg[1] ;
output [34:0]Q;
output \m_payload_i_reg[2]_0 ;
output \m_payload_i_reg[1]_0 ;
output \m_payload_i_reg[1]_1 ;
output \m_payload_i_reg[1]_2 ;
output \m_payload_i_reg[2]_1 ;
output \m_payload_i_reg[2]_2 ;
output \skid_buffer_reg[3]_0 ;
output \skid_buffer_reg[3]_1 ;
output \skid_buffer_reg[3]_2 ;
output m_valid_i_reg_0;
output m_valid_i_reg_1;
output [12:0]m_axi_rready;
input aclk;
input m_valid_i_reg_2;
input \m_ready_d_reg[0] ;
input [3:0]m_atarget_enc;
input \m_atarget_enc_reg[1] ;
input [0:0]s_axi_rready;
input aa_grant_rnw;
input m_valid_i;
input [0:0]m_ready_d;
input [27:0]m_axi_rresp;
input [447:0]m_axi_rdata;
input \m_atarget_enc_reg[1]_rep ;
input \m_atarget_enc_reg[0]_rep ;
input [9:0]m_axi_rvalid;
input [12:0]\m_atarget_hot_reg[13] ;
input reset;
input [0:0]E;
wire [0:0]E;
wire [34:0]Q;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire \aresetn_d_reg_n_0_[0] ;
wire \aresetn_d_reg_n_0_[1] ;
wire [3:0]m_atarget_enc;
wire \m_atarget_enc_reg[0]_rep ;
wire \m_atarget_enc_reg[1] ;
wire \m_atarget_enc_reg[1]_rep ;
wire [12:0]\m_atarget_hot_reg[13] ;
wire [447:0]m_axi_rdata;
wire [12:0]m_axi_rready;
wire [27:0]m_axi_rresp;
wire [9:0]m_axi_rvalid;
wire \m_payload_i[1]_i_2_n_0 ;
wire \m_payload_i[1]_i_3_n_0 ;
wire \m_payload_i[1]_i_4_n_0 ;
wire \m_payload_i[1]_i_5_n_0 ;
wire \m_payload_i[1]_i_6_n_0 ;
wire \m_payload_i[1]_i_7_n_0 ;
wire \m_payload_i[1]_i_8_n_0 ;
wire \m_payload_i[2]_i_10_n_0 ;
wire \m_payload_i[2]_i_2_n_0 ;
wire \m_payload_i[2]_i_3_n_0 ;
wire \m_payload_i[2]_i_4_n_0 ;
wire \m_payload_i[2]_i_5_n_0 ;
wire \m_payload_i[2]_i_6_n_0 ;
wire \m_payload_i[2]_i_7_n_0 ;
wire \m_payload_i[2]_i_8_n_0 ;
wire \m_payload_i[2]_i_9_n_0 ;
wire \m_payload_i_reg[1]_0 ;
wire \m_payload_i_reg[1]_1 ;
wire \m_payload_i_reg[1]_2 ;
wire \m_payload_i_reg[2]_0 ;
wire \m_payload_i_reg[2]_1 ;
wire \m_payload_i_reg[2]_2 ;
wire [0:0]m_ready_d;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[1] ;
wire m_valid_i;
wire m_valid_i_i_1_n_0;
wire m_valid_i_i_2_n_0;
wire m_valid_i_i_4_n_0;
wire m_valid_i_i_7_n_0;
wire m_valid_i_reg_0;
wire m_valid_i_reg_1;
wire m_valid_i_reg_2;
wire reset;
wire [0:0]s_axi_rready;
wire s_ready_i_i_1_n_0;
wire [34:0]skid_buffer;
wire \skid_buffer[0]_i_1_n_0 ;
wire \skid_buffer[10]_i_1_n_0 ;
wire \skid_buffer[10]_i_2_n_0 ;
wire \skid_buffer[10]_i_3_n_0 ;
wire \skid_buffer[10]_i_4_n_0 ;
wire \skid_buffer[10]_i_5_n_0 ;
wire \skid_buffer[10]_i_6_n_0 ;
wire \skid_buffer[10]_i_7_n_0 ;
wire \skid_buffer[11]_i_1_n_0 ;
wire \skid_buffer[11]_i_2_n_0 ;
wire \skid_buffer[11]_i_3_n_0 ;
wire \skid_buffer[11]_i_4_n_0 ;
wire \skid_buffer[11]_i_5_n_0 ;
wire \skid_buffer[11]_i_6_n_0 ;
wire \skid_buffer[11]_i_7_n_0 ;
wire \skid_buffer[12]_i_1_n_0 ;
wire \skid_buffer[12]_i_2_n_0 ;
wire \skid_buffer[12]_i_3_n_0 ;
wire \skid_buffer[12]_i_4_n_0 ;
wire \skid_buffer[12]_i_5_n_0 ;
wire \skid_buffer[12]_i_6_n_0 ;
wire \skid_buffer[12]_i_7_n_0 ;
wire \skid_buffer[13]_i_1_n_0 ;
wire \skid_buffer[13]_i_2_n_0 ;
wire \skid_buffer[13]_i_3_n_0 ;
wire \skid_buffer[13]_i_4_n_0 ;
wire \skid_buffer[13]_i_5_n_0 ;
wire \skid_buffer[13]_i_6_n_0 ;
wire \skid_buffer[13]_i_7_n_0 ;
wire \skid_buffer[14]_i_1_n_0 ;
wire \skid_buffer[14]_i_2_n_0 ;
wire \skid_buffer[14]_i_3_n_0 ;
wire \skid_buffer[14]_i_4_n_0 ;
wire \skid_buffer[14]_i_5_n_0 ;
wire \skid_buffer[14]_i_6_n_0 ;
wire \skid_buffer[14]_i_7_n_0 ;
wire \skid_buffer[15]_i_1_n_0 ;
wire \skid_buffer[15]_i_2_n_0 ;
wire \skid_buffer[15]_i_3_n_0 ;
wire \skid_buffer[15]_i_4_n_0 ;
wire \skid_buffer[15]_i_5_n_0 ;
wire \skid_buffer[15]_i_6_n_0 ;
wire \skid_buffer[15]_i_7_n_0 ;
wire \skid_buffer[16]_i_1_n_0 ;
wire \skid_buffer[16]_i_2_n_0 ;
wire \skid_buffer[16]_i_3_n_0 ;
wire \skid_buffer[16]_i_4_n_0 ;
wire \skid_buffer[16]_i_5_n_0 ;
wire \skid_buffer[16]_i_6_n_0 ;
wire \skid_buffer[16]_i_7_n_0 ;
wire \skid_buffer[17]_i_1_n_0 ;
wire \skid_buffer[17]_i_2_n_0 ;
wire \skid_buffer[17]_i_3_n_0 ;
wire \skid_buffer[17]_i_4_n_0 ;
wire \skid_buffer[17]_i_5_n_0 ;
wire \skid_buffer[17]_i_6_n_0 ;
wire \skid_buffer[17]_i_7_n_0 ;
wire \skid_buffer[18]_i_1_n_0 ;
wire \skid_buffer[18]_i_2_n_0 ;
wire \skid_buffer[18]_i_3_n_0 ;
wire \skid_buffer[18]_i_4_n_0 ;
wire \skid_buffer[18]_i_5_n_0 ;
wire \skid_buffer[18]_i_6_n_0 ;
wire \skid_buffer[18]_i_7_n_0 ;
wire \skid_buffer[19]_i_1_n_0 ;
wire \skid_buffer[19]_i_2_n_0 ;
wire \skid_buffer[19]_i_3_n_0 ;
wire \skid_buffer[19]_i_4_n_0 ;
wire \skid_buffer[19]_i_5_n_0 ;
wire \skid_buffer[19]_i_6_n_0 ;
wire \skid_buffer[19]_i_7_n_0 ;
wire \skid_buffer[20]_i_1_n_0 ;
wire \skid_buffer[20]_i_2_n_0 ;
wire \skid_buffer[20]_i_3_n_0 ;
wire \skid_buffer[20]_i_4_n_0 ;
wire \skid_buffer[20]_i_5_n_0 ;
wire \skid_buffer[20]_i_6_n_0 ;
wire \skid_buffer[20]_i_7_n_0 ;
wire \skid_buffer[21]_i_1_n_0 ;
wire \skid_buffer[21]_i_2_n_0 ;
wire \skid_buffer[21]_i_3_n_0 ;
wire \skid_buffer[21]_i_4_n_0 ;
wire \skid_buffer[21]_i_5_n_0 ;
wire \skid_buffer[21]_i_6_n_0 ;
wire \skid_buffer[21]_i_7_n_0 ;
wire \skid_buffer[22]_i_1_n_0 ;
wire \skid_buffer[22]_i_2_n_0 ;
wire \skid_buffer[22]_i_3_n_0 ;
wire \skid_buffer[22]_i_4_n_0 ;
wire \skid_buffer[22]_i_5_n_0 ;
wire \skid_buffer[22]_i_6_n_0 ;
wire \skid_buffer[22]_i_7_n_0 ;
wire \skid_buffer[23]_i_1_n_0 ;
wire \skid_buffer[23]_i_2_n_0 ;
wire \skid_buffer[23]_i_3_n_0 ;
wire \skid_buffer[23]_i_4_n_0 ;
wire \skid_buffer[23]_i_5_n_0 ;
wire \skid_buffer[23]_i_6_n_0 ;
wire \skid_buffer[23]_i_7_n_0 ;
wire \skid_buffer[24]_i_1_n_0 ;
wire \skid_buffer[24]_i_2_n_0 ;
wire \skid_buffer[24]_i_3_n_0 ;
wire \skid_buffer[24]_i_4_n_0 ;
wire \skid_buffer[24]_i_5_n_0 ;
wire \skid_buffer[24]_i_6_n_0 ;
wire \skid_buffer[24]_i_7_n_0 ;
wire \skid_buffer[25]_i_1_n_0 ;
wire \skid_buffer[25]_i_2_n_0 ;
wire \skid_buffer[25]_i_3_n_0 ;
wire \skid_buffer[25]_i_4_n_0 ;
wire \skid_buffer[25]_i_5_n_0 ;
wire \skid_buffer[25]_i_6_n_0 ;
wire \skid_buffer[25]_i_7_n_0 ;
wire \skid_buffer[26]_i_1_n_0 ;
wire \skid_buffer[26]_i_2_n_0 ;
wire \skid_buffer[26]_i_3_n_0 ;
wire \skid_buffer[26]_i_4_n_0 ;
wire \skid_buffer[26]_i_5_n_0 ;
wire \skid_buffer[26]_i_6_n_0 ;
wire \skid_buffer[26]_i_7_n_0 ;
wire \skid_buffer[27]_i_1_n_0 ;
wire \skid_buffer[27]_i_2_n_0 ;
wire \skid_buffer[27]_i_3_n_0 ;
wire \skid_buffer[27]_i_4_n_0 ;
wire \skid_buffer[27]_i_5_n_0 ;
wire \skid_buffer[27]_i_6_n_0 ;
wire \skid_buffer[27]_i_7_n_0 ;
wire \skid_buffer[28]_i_1_n_0 ;
wire \skid_buffer[28]_i_2_n_0 ;
wire \skid_buffer[28]_i_3_n_0 ;
wire \skid_buffer[28]_i_4_n_0 ;
wire \skid_buffer[28]_i_5_n_0 ;
wire \skid_buffer[28]_i_6_n_0 ;
wire \skid_buffer[28]_i_7_n_0 ;
wire \skid_buffer[29]_i_1_n_0 ;
wire \skid_buffer[29]_i_2_n_0 ;
wire \skid_buffer[29]_i_3_n_0 ;
wire \skid_buffer[29]_i_4_n_0 ;
wire \skid_buffer[29]_i_5_n_0 ;
wire \skid_buffer[29]_i_6_n_0 ;
wire \skid_buffer[29]_i_7_n_0 ;
wire \skid_buffer[30]_i_1_n_0 ;
wire \skid_buffer[30]_i_2_n_0 ;
wire \skid_buffer[30]_i_3_n_0 ;
wire \skid_buffer[30]_i_4_n_0 ;
wire \skid_buffer[30]_i_5_n_0 ;
wire \skid_buffer[30]_i_6_n_0 ;
wire \skid_buffer[30]_i_7_n_0 ;
wire \skid_buffer[31]_i_1_n_0 ;
wire \skid_buffer[31]_i_2_n_0 ;
wire \skid_buffer[31]_i_3_n_0 ;
wire \skid_buffer[31]_i_4_n_0 ;
wire \skid_buffer[31]_i_5_n_0 ;
wire \skid_buffer[31]_i_6_n_0 ;
wire \skid_buffer[31]_i_7_n_0 ;
wire \skid_buffer[32]_i_1_n_0 ;
wire \skid_buffer[32]_i_2_n_0 ;
wire \skid_buffer[32]_i_3_n_0 ;
wire \skid_buffer[32]_i_4_n_0 ;
wire \skid_buffer[32]_i_5_n_0 ;
wire \skid_buffer[32]_i_6_n_0 ;
wire \skid_buffer[32]_i_7_n_0 ;
wire \skid_buffer[33]_i_1_n_0 ;
wire \skid_buffer[33]_i_2_n_0 ;
wire \skid_buffer[33]_i_3_n_0 ;
wire \skid_buffer[33]_i_4_n_0 ;
wire \skid_buffer[33]_i_5_n_0 ;
wire \skid_buffer[33]_i_6_n_0 ;
wire \skid_buffer[33]_i_7_n_0 ;
wire \skid_buffer[34]_i_1_n_0 ;
wire \skid_buffer[34]_i_2_n_0 ;
wire \skid_buffer[34]_i_3_n_0 ;
wire \skid_buffer[34]_i_4_n_0 ;
wire \skid_buffer[34]_i_5_n_0 ;
wire \skid_buffer[34]_i_6_n_0 ;
wire \skid_buffer[34]_i_7_n_0 ;
wire \skid_buffer[34]_i_8_n_0 ;
wire \skid_buffer[3]_i_1_n_0 ;
wire \skid_buffer[3]_i_2_n_0 ;
wire \skid_buffer[3]_i_3_n_0 ;
wire \skid_buffer[3]_i_4_n_0 ;
wire \skid_buffer[3]_i_5_n_0 ;
wire \skid_buffer[3]_i_6_n_0 ;
wire \skid_buffer[3]_i_7_n_0 ;
wire \skid_buffer[4]_i_1_n_0 ;
wire \skid_buffer[4]_i_2_n_0 ;
wire \skid_buffer[4]_i_3_n_0 ;
wire \skid_buffer[4]_i_4_n_0 ;
wire \skid_buffer[4]_i_5_n_0 ;
wire \skid_buffer[4]_i_6_n_0 ;
wire \skid_buffer[4]_i_7_n_0 ;
wire \skid_buffer[5]_i_1_n_0 ;
wire \skid_buffer[5]_i_2_n_0 ;
wire \skid_buffer[5]_i_3_n_0 ;
wire \skid_buffer[5]_i_4_n_0 ;
wire \skid_buffer[5]_i_5_n_0 ;
wire \skid_buffer[5]_i_6_n_0 ;
wire \skid_buffer[5]_i_7_n_0 ;
wire \skid_buffer[6]_i_1_n_0 ;
wire \skid_buffer[6]_i_2_n_0 ;
wire \skid_buffer[6]_i_3_n_0 ;
wire \skid_buffer[6]_i_4_n_0 ;
wire \skid_buffer[6]_i_5_n_0 ;
wire \skid_buffer[6]_i_6_n_0 ;
wire \skid_buffer[6]_i_7_n_0 ;
wire \skid_buffer[7]_i_1_n_0 ;
wire \skid_buffer[7]_i_2_n_0 ;
wire \skid_buffer[7]_i_3_n_0 ;
wire \skid_buffer[7]_i_4_n_0 ;
wire \skid_buffer[7]_i_5_n_0 ;
wire \skid_buffer[7]_i_6_n_0 ;
wire \skid_buffer[7]_i_7_n_0 ;
wire \skid_buffer[8]_i_1_n_0 ;
wire \skid_buffer[8]_i_2_n_0 ;
wire \skid_buffer[8]_i_3_n_0 ;
wire \skid_buffer[8]_i_4_n_0 ;
wire \skid_buffer[8]_i_5_n_0 ;
wire \skid_buffer[8]_i_6_n_0 ;
wire \skid_buffer[8]_i_7_n_0 ;
wire \skid_buffer[9]_i_1_n_0 ;
wire \skid_buffer[9]_i_2_n_0 ;
wire \skid_buffer[9]_i_3_n_0 ;
wire \skid_buffer[9]_i_4_n_0 ;
wire \skid_buffer[9]_i_5_n_0 ;
wire \skid_buffer[9]_i_6_n_0 ;
wire \skid_buffer[9]_i_7_n_0 ;
wire \skid_buffer_reg[3]_0 ;
wire \skid_buffer_reg[3]_1 ;
wire \skid_buffer_reg[3]_2 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire sr_rvalid;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(1'b1),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(reset));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg_n_0_[0] ),
.Q(\aresetn_d_reg_n_0_[1] ),
.R(reset));
LUT2 #(
.INIT(4'h8))
\m_axi_rready[0]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [0]),
.O(m_axi_rready[0]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[11]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [10]),
.O(m_axi_rready[10]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[12]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [11]),
.O(m_axi_rready[11]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[13]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [12]),
.O(m_axi_rready[12]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[1]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [1]),
.O(m_axi_rready[1]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[2]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [2]),
.O(m_axi_rready[2]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[3]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [3]),
.O(m_axi_rready[3]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[4]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [4]),
.O(m_axi_rready[4]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[5]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [5]),
.O(m_axi_rready[5]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[6]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [6]),
.O(m_axi_rready[6]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[7]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [7]),
.O(m_axi_rready[7]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[8]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [8]),
.O(m_axi_rready[8]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[9]_INST_0
(.I0(aa_rready),
.I1(\m_atarget_hot_reg[13] [9]),
.O(m_axi_rready[9]));
LUT6 #(
.INIT(64'h7FFFFFFF7FFF0000))
\m_payload_i[0]_i_1
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.I4(aa_rready),
.I5(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(\skid_buffer[10]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(\skid_buffer[11]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(\skid_buffer[12]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1
(.I0(\skid_buffer[13]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(\skid_buffer[14]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(\skid_buffer[15]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(\skid_buffer[16]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(\skid_buffer[17]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(\skid_buffer[18]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(\skid_buffer[19]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
LUT6 #(
.INIT(64'hEEEEEEEEEEEEE0EE))
\m_payload_i[1]_i_1
(.I0(\skid_buffer_reg_n_0_[1] ),
.I1(aa_rready),
.I2(\m_payload_i[1]_i_2_n_0 ),
.I3(\m_payload_i[1]_i_3_n_0 ),
.I4(\m_payload_i[1]_i_4_n_0 ),
.I5(\m_payload_i[1]_i_5_n_0 ),
.O(skid_buffer[1]));
LUT6 #(
.INIT(64'hEFEEFFFFEFEEEFEE))
\m_payload_i[1]_i_2
(.I0(\m_payload_i[1]_i_6_n_0 ),
.I1(\m_payload_i[1]_i_7_n_0 ),
.I2(\m_payload_i_reg[1]_0 ),
.I3(m_axi_rresp[18]),
.I4(\m_payload_i_reg[1]_1 ),
.I5(m_axi_rresp[12]),
.O(\m_payload_i[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hA2A200A2))
\m_payload_i[1]_i_3
(.I0(\m_payload_i[1]_i_8_n_0 ),
.I1(m_axi_rresp[6]),
.I2(\m_payload_i_reg[1]_2 ),
.I3(m_axi_rresp[10]),
.I4(\m_payload_i[2]_i_9_n_0 ),
.O(\m_payload_i[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0083000000800000))
\m_payload_i[1]_i_4
(.I0(m_axi_rresp[26]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rresp[2]),
.O(\m_payload_i[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0023000000200000))
\m_payload_i[1]_i_5
(.I0(m_axi_rresp[20]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rresp[4]),
.O(\m_payload_i[1]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFF44F4FFFFFFFF))
\m_payload_i[1]_i_6
(.I0(\skid_buffer_reg[3]_1 ),
.I1(m_axi_rresp[24]),
.I2(m_axi_rresp[8]),
.I3(\m_payload_i_reg[2]_0 ),
.I4(\m_payload_i_reg[2]_2 ),
.I5(aa_rready),
.O(\m_payload_i[1]_i_6_n_0 ));
LUT6 #(
.INIT(64'h2C00000020000000))
\m_payload_i[1]_i_7
(.I0(m_axi_rresp[22]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rresp[14]),
.O(\m_payload_i[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFF1FFFFFFFD))
\m_payload_i[1]_i_8
(.I0(m_axi_rresp[0]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rresp[16]),
.O(\m_payload_i[1]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(\skid_buffer[20]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(\skid_buffer[21]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(\skid_buffer[22]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(\skid_buffer[23]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(\skid_buffer[24]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(\skid_buffer[25]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(\skid_buffer[26]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(\skid_buffer[27]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(\skid_buffer[28]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(\skid_buffer[29]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
LUT6 #(
.INIT(64'hEEEEEEEEEEEEE0EE))
\m_payload_i[2]_i_1
(.I0(\skid_buffer_reg_n_0_[2] ),
.I1(aa_rready),
.I2(\m_payload_i[2]_i_2_n_0 ),
.I3(\m_payload_i[2]_i_3_n_0 ),
.I4(\m_payload_i[2]_i_4_n_0 ),
.I5(\m_payload_i[2]_i_5_n_0 ),
.O(skid_buffer[2]));
LUT6 #(
.INIT(64'h0000008300000080))
\m_payload_i[2]_i_10
(.I0(m_axi_rresp[25]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rresp[1]),
.O(\m_payload_i[2]_i_10_n_0 ));
LUT6 #(
.INIT(64'hEFEEFFFFEFEEEFEE))
\m_payload_i[2]_i_2
(.I0(\m_payload_i[2]_i_6_n_0 ),
.I1(\m_payload_i[2]_i_7_n_0 ),
.I2(\m_payload_i[2]_i_8_n_0 ),
.I3(m_axi_rresp[21]),
.I4(\m_payload_i_reg[2]_0 ),
.I5(m_axi_rresp[9]),
.O(\m_payload_i[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000D0DD))
\m_payload_i[2]_i_3
(.I0(m_axi_rresp[7]),
.I1(\m_payload_i_reg[1]_2 ),
.I2(\m_payload_i[2]_i_9_n_0 ),
.I3(m_axi_rresp[11]),
.I4(\m_payload_i[2]_i_10_n_0 ),
.O(\m_payload_i[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0003080000000800))
\m_payload_i[2]_i_4
(.I0(m_axi_rresp[13]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rresp[3]),
.O(\m_payload_i[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'h2003000020000000))
\m_payload_i[2]_i_5
(.I0(m_axi_rresp[23]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rresp[5]),
.O(\m_payload_i[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF4FFF4FFFFFFF4FF))
\m_payload_i[2]_i_6
(.I0(\m_payload_i_reg[2]_1 ),
.I1(m_axi_rresp[17]),
.I2(\m_payload_i_reg[2]_2 ),
.I3(aa_rready),
.I4(m_axi_rresp[27]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\m_payload_i[2]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0C20000000200000))
\m_payload_i[2]_i_7
(.I0(m_axi_rresp[19]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rresp[15]),
.O(\m_payload_i[2]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'hFDFF))
\m_payload_i[2]_i_8
(.I0(m_atarget_enc[3]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.O(\m_payload_i[2]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'hFDFF))
\m_payload_i[2]_i_9
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\m_payload_i[2]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(\skid_buffer[30]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1
(.I0(\skid_buffer[31]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(\skid_buffer[32]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(\skid_buffer[33]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_2
(.I0(\skid_buffer[34]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(\skid_buffer[3]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(\skid_buffer[4]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(\skid_buffer[5]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(\skid_buffer[6]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(\skid_buffer[7]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(\skid_buffer[8]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(\skid_buffer[9]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h000000007FFFFFFF))
\m_ready_d[1]_i_3
(.I0(sr_rvalid),
.I1(Q[0]),
.I2(s_axi_rready),
.I3(aa_grant_rnw),
.I4(m_valid_i),
.I5(m_ready_d),
.O(\m_ready_d_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hA2))
m_valid_i_i_1
(.I0(\aresetn_d_reg_n_0_[1] ),
.I1(m_valid_i_i_2_n_0),
.I2(m_valid_i_reg_2),
.O(m_valid_i_i_1_n_0));
LUT5 #(
.INIT(32'hA8A8A8AA))
m_valid_i_i_2
(.I0(aa_rready),
.I1(m_valid_i_i_4_n_0),
.I2(\m_ready_d_reg[0] ),
.I3(m_atarget_enc[0]),
.I4(\m_atarget_enc_reg[1] ),
.O(m_valid_i_i_2_n_0));
LUT6 #(
.INIT(64'h0000000000007F00))
m_valid_i_i_4
(.I0(m_axi_rvalid[9]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_valid_i_i_7_n_0),
.O(m_valid_i_i_4_n_0));
LUT5 #(
.INIT(32'h0AFC0A0C))
m_valid_i_i_7
(.I0(m_axi_rvalid[6]),
.I1(m_axi_rvalid[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.I4(m_axi_rvalid[3]),
.O(m_valid_i_i_7_n_0));
LUT6 #(
.INIT(64'hDD0C000000000000))
m_valid_i_i_8
(.I0(m_axi_rvalid[4]),
.I1(m_atarget_enc[3]),
.I2(m_axi_rvalid[7]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[1]),
.O(m_valid_i_reg_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
m_valid_i_i_9
(.I0(m_axi_rvalid[8]),
.I1(m_axi_rvalid[2]),
.I2(m_atarget_enc[2]),
.I3(m_axi_rvalid[5]),
.I4(m_atarget_enc[3]),
.I5(m_axi_rvalid[0]),
.O(m_valid_i_reg_1));
FDRE m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1_n_0),
.Q(sr_rvalid),
.R(1'b0));
LUT4 #(
.INIT(16'hFFFE))
\s_axi_bresp[0]_INST_0_i_11
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\skid_buffer_reg[3]_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'hFFFD))
\s_axi_bresp[0]_INST_0_i_5
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\m_payload_i_reg[2]_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'hFDFF))
\s_axi_bresp[0]_INST_0_i_6
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.O(\m_payload_i_reg[1]_1 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT4 #(
.INIT(16'hFDFF))
\s_axi_bresp[1]_INST_0_i_1
(.I0(m_atarget_enc[3]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\m_payload_i_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT4 #(
.INIT(16'hFFFD))
\s_axi_bresp[1]_INST_0_i_10
(.I0(m_atarget_enc[3]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\m_payload_i_reg[2]_1 ));
LUT4 #(
.INIT(16'hFFF7))
\s_axi_bresp[1]_INST_0_i_12
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\skid_buffer_reg[3]_1 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT4 #(
.INIT(16'h4000))
\s_axi_bresp[1]_INST_0_i_2
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.O(\m_payload_i_reg[2]_2 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT4 #(
.INIT(16'hEFFF))
\s_axi_bresp[1]_INST_0_i_6
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\m_payload_i_reg[1]_2 ));
LUT2 #(
.INIT(4'hE))
\s_axi_bvalid[0]_INST_0_i_10
(.I0(m_atarget_enc[3]),
.I1(m_atarget_enc[2]),
.O(\skid_buffer_reg[3]_2 ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hA2))
s_ready_i_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(m_valid_i_reg_2),
.I2(m_valid_i_i_2_n_0),
.O(s_ready_i_i_1_n_0));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1_n_0),
.Q(aa_rready),
.R(1'b0));
LUT4 #(
.INIT(16'h7FFF))
\skid_buffer[0]_i_1
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\skid_buffer[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[10]_i_1
(.I0(\skid_buffer[10]_i_2_n_0 ),
.I1(\skid_buffer[10]_i_3_n_0 ),
.I2(\skid_buffer[10]_i_4_n_0 ),
.I3(\skid_buffer[10]_i_5_n_0 ),
.I4(\skid_buffer[10]_i_6_n_0 ),
.I5(\skid_buffer[10]_i_7_n_0 ),
.O(\skid_buffer[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[10]_i_2
(.I0(m_axi_rdata[327]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[359]),
.O(\skid_buffer[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[10]_i_3
(.I0(m_axi_rdata[263]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[295]),
.O(\skid_buffer[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[10]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[7]),
.I2(\skid_buffer_reg[3]_1 ),
.I3(m_axi_rdata[391]),
.I4(m_axi_rdata[423]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\skid_buffer[10]_i_5
(.I0(m_axi_rdata[71]),
.I1(m_axi_rdata[103]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[39]),
.O(\skid_buffer[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[10]_i_6
(.I0(m_axi_rdata[199]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[231]),
.O(\skid_buffer[10]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[10]_i_7
(.I0(m_axi_rdata[135]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[167]),
.O(\skid_buffer[10]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[11]_i_1
(.I0(\skid_buffer[11]_i_2_n_0 ),
.I1(\skid_buffer[11]_i_3_n_0 ),
.I2(\skid_buffer[11]_i_4_n_0 ),
.I3(\skid_buffer[11]_i_5_n_0 ),
.I4(\skid_buffer[11]_i_6_n_0 ),
.I5(\skid_buffer[11]_i_7_n_0 ),
.O(\skid_buffer[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[11]_i_2
(.I0(m_axi_rdata[328]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[360]),
.O(\skid_buffer[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[11]_i_3
(.I0(m_axi_rdata[296]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[264]),
.O(\skid_buffer[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[11]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[8]),
.I2(\skid_buffer_reg[3]_1 ),
.I3(m_axi_rdata[392]),
.I4(m_axi_rdata[424]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\skid_buffer[11]_i_5
(.I0(m_axi_rdata[72]),
.I1(m_axi_rdata[104]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[40]),
.O(\skid_buffer[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[11]_i_6
(.I0(m_axi_rdata[232]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[200]),
.O(\skid_buffer[11]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[11]_i_7
(.I0(m_axi_rdata[168]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[136]),
.O(\skid_buffer[11]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF7))
\skid_buffer[12]_i_1
(.I0(\skid_buffer[12]_i_2_n_0 ),
.I1(\skid_buffer[12]_i_3_n_0 ),
.I2(\skid_buffer[12]_i_4_n_0 ),
.I3(\skid_buffer[12]_i_5_n_0 ),
.I4(\skid_buffer[12]_i_6_n_0 ),
.I5(\skid_buffer[12]_i_7_n_0 ),
.O(\skid_buffer[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFF3FFF7FFFFFFF7))
\skid_buffer[12]_i_2
(.I0(m_axi_rdata[265]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[297]),
.O(\skid_buffer[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF7F3FFFFF7FFFFFF))
\skid_buffer[12]_i_3
(.I0(m_axi_rdata[361]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[329]),
.O(\skid_buffer[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[12]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[9]),
.I2(m_axi_rdata[393]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[425]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[12]_i_5
(.I0(m_axi_rdata[73]),
.I1(m_axi_rdata[41]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[105]),
.O(\skid_buffer[12]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[12]_i_6
(.I0(m_axi_rdata[201]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[233]),
.O(\skid_buffer[12]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[12]_i_7
(.I0(m_axi_rdata[169]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[137]),
.O(\skid_buffer[12]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[13]_i_1
(.I0(\skid_buffer[13]_i_2_n_0 ),
.I1(\skid_buffer[13]_i_3_n_0 ),
.I2(\skid_buffer[13]_i_4_n_0 ),
.I3(\skid_buffer[13]_i_5_n_0 ),
.I4(\skid_buffer[13]_i_6_n_0 ),
.I5(\skid_buffer[13]_i_7_n_0 ),
.O(\skid_buffer[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[13]_i_2
(.I0(m_axi_rdata[330]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[362]),
.O(\skid_buffer[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[13]_i_3
(.I0(m_axi_rdata[266]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[298]),
.O(\skid_buffer[13]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[13]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[10]),
.I2(\skid_buffer[34]_i_8_n_0 ),
.I3(m_axi_rdata[426]),
.I4(m_axi_rdata[394]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[13]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[13]_i_5
(.I0(m_axi_rdata[74]),
.I1(m_axi_rdata[42]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[106]),
.O(\skid_buffer[13]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[13]_i_6
(.I0(m_axi_rdata[202]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[234]),
.O(\skid_buffer[13]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[13]_i_7
(.I0(m_axi_rdata[138]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[170]),
.O(\skid_buffer[13]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFF))
\skid_buffer[14]_i_1
(.I0(\skid_buffer[14]_i_2_n_0 ),
.I1(\skid_buffer[14]_i_3_n_0 ),
.I2(\skid_buffer[14]_i_4_n_0 ),
.I3(\skid_buffer[14]_i_5_n_0 ),
.I4(\skid_buffer[14]_i_6_n_0 ),
.I5(\skid_buffer[14]_i_7_n_0 ),
.O(\skid_buffer[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[14]_i_2
(.I0(m_axi_rdata[363]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[331]),
.O(\skid_buffer[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[14]_i_3
(.I0(m_axi_rdata[267]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[299]),
.O(\skid_buffer[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[14]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[11]),
.I2(m_axi_rdata[395]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[427]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[14]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[14]_i_5
(.I0(m_axi_rdata[75]),
.I1(m_axi_rdata[43]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[107]),
.O(\skid_buffer[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF3FFF7FFFFFFF7FF))
\skid_buffer[14]_i_6
(.I0(m_axi_rdata[203]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[235]),
.O(\skid_buffer[14]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFFF3FFF7FFFFFFF7))
\skid_buffer[14]_i_7
(.I0(m_axi_rdata[139]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[171]),
.O(\skid_buffer[14]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[15]_i_1
(.I0(\skid_buffer[15]_i_2_n_0 ),
.I1(\skid_buffer[15]_i_3_n_0 ),
.I2(\skid_buffer[15]_i_4_n_0 ),
.I3(\skid_buffer[15]_i_5_n_0 ),
.I4(\skid_buffer[15]_i_6_n_0 ),
.I5(\skid_buffer[15]_i_7_n_0 ),
.O(\skid_buffer[15]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[15]_i_2
(.I0(m_axi_rdata[332]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[364]),
.O(\skid_buffer[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[15]_i_3
(.I0(m_axi_rdata[268]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[300]),
.O(\skid_buffer[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[15]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[12]),
.I2(\skid_buffer_reg[3]_1 ),
.I3(m_axi_rdata[396]),
.I4(m_axi_rdata[428]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\skid_buffer[15]_i_5
(.I0(m_axi_rdata[76]),
.I1(m_axi_rdata[108]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[44]),
.O(\skid_buffer[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[15]_i_6
(.I0(m_axi_rdata[204]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[236]),
.O(\skid_buffer[15]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[15]_i_7
(.I0(m_axi_rdata[140]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[172]),
.O(\skid_buffer[15]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[16]_i_1
(.I0(\skid_buffer[16]_i_2_n_0 ),
.I1(\skid_buffer[16]_i_3_n_0 ),
.I2(\skid_buffer[16]_i_4_n_0 ),
.I3(\skid_buffer[16]_i_5_n_0 ),
.I4(\skid_buffer[16]_i_6_n_0 ),
.I5(\skid_buffer[16]_i_7_n_0 ),
.O(\skid_buffer[16]_i_1_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[16]_i_2
(.I0(m_axi_rdata[365]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[333]),
.O(\skid_buffer[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[16]_i_3
(.I0(m_axi_rdata[301]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[269]),
.O(\skid_buffer[16]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[16]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[13]),
.I2(m_axi_rdata[397]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[429]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[16]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[16]_i_5
(.I0(m_axi_rdata[77]),
.I1(m_axi_rdata[45]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[109]),
.O(\skid_buffer[16]_i_5_n_0 ));
LUT6 #(
.INIT(64'h00C0000000A00000))
\skid_buffer[16]_i_6
(.I0(m_axi_rdata[205]),
.I1(m_axi_rdata[237]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(\m_atarget_enc_reg[0]_rep ),
.O(\skid_buffer[16]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[16]_i_7
(.I0(m_axi_rdata[173]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[141]),
.O(\skid_buffer[16]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[17]_i_1
(.I0(\skid_buffer[17]_i_2_n_0 ),
.I1(\skid_buffer[17]_i_3_n_0 ),
.I2(\skid_buffer[17]_i_4_n_0 ),
.I3(\skid_buffer[17]_i_5_n_0 ),
.I4(\skid_buffer[17]_i_6_n_0 ),
.I5(\skid_buffer[17]_i_7_n_0 ),
.O(\skid_buffer[17]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[17]_i_2
(.I0(m_axi_rdata[334]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[366]),
.O(\skid_buffer[17]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[17]_i_3
(.I0(m_axi_rdata[270]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[302]),
.O(\skid_buffer[17]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[17]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[14]),
.I2(\skid_buffer_reg[3]_1 ),
.I3(m_axi_rdata[398]),
.I4(m_axi_rdata[430]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[17]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[17]_i_5
(.I0(m_axi_rdata[78]),
.I1(m_axi_rdata[46]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[110]),
.O(\skid_buffer[17]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[17]_i_6
(.I0(m_axi_rdata[206]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[238]),
.O(\skid_buffer[17]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[17]_i_7
(.I0(m_axi_rdata[142]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[174]),
.O(\skid_buffer[17]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[18]_i_1
(.I0(\skid_buffer[18]_i_2_n_0 ),
.I1(\skid_buffer[18]_i_3_n_0 ),
.I2(\skid_buffer[18]_i_4_n_0 ),
.I3(\skid_buffer[18]_i_5_n_0 ),
.I4(\skid_buffer[18]_i_6_n_0 ),
.I5(\skid_buffer[18]_i_7_n_0 ),
.O(\skid_buffer[18]_i_1_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[18]_i_2
(.I0(m_axi_rdata[367]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[335]),
.O(\skid_buffer[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[18]_i_3
(.I0(m_axi_rdata[271]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[303]),
.O(\skid_buffer[18]_i_3_n_0 ));
LUT6 #(
.INIT(64'h22F222F2FFFF22F2))
\skid_buffer[18]_i_4
(.I0(m_axi_rdata[15]),
.I1(\skid_buffer_reg[3]_0 ),
.I2(m_axi_rdata[431]),
.I3(\skid_buffer[34]_i_8_n_0 ),
.I4(m_axi_rdata[399]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[18]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[18]_i_5
(.I0(m_axi_rdata[79]),
.I1(m_axi_rdata[47]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[111]),
.O(\skid_buffer[18]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[18]_i_6
(.I0(m_axi_rdata[239]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[207]),
.O(\skid_buffer[18]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[18]_i_7
(.I0(m_axi_rdata[143]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[175]),
.O(\skid_buffer[18]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[19]_i_1
(.I0(\skid_buffer[19]_i_2_n_0 ),
.I1(\skid_buffer[19]_i_3_n_0 ),
.I2(\skid_buffer[19]_i_4_n_0 ),
.I3(\skid_buffer[19]_i_5_n_0 ),
.I4(\skid_buffer[19]_i_6_n_0 ),
.I5(\skid_buffer[19]_i_7_n_0 ),
.O(\skid_buffer[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[19]_i_2
(.I0(m_axi_rdata[336]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[368]),
.O(\skid_buffer[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[19]_i_3
(.I0(m_axi_rdata[272]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[304]),
.O(\skid_buffer[19]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[19]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[16]),
.I2(\skid_buffer[34]_i_8_n_0 ),
.I3(m_axi_rdata[432]),
.I4(m_axi_rdata[400]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[19]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[19]_i_5
(.I0(m_axi_rdata[80]),
.I1(m_axi_rdata[48]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[112]),
.O(\skid_buffer[19]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[19]_i_6
(.I0(m_axi_rdata[208]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[240]),
.O(\skid_buffer[19]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[19]_i_7
(.I0(m_axi_rdata[144]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[176]),
.O(\skid_buffer[19]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[20]_i_1
(.I0(\skid_buffer[20]_i_2_n_0 ),
.I1(\skid_buffer[20]_i_3_n_0 ),
.I2(\skid_buffer[20]_i_4_n_0 ),
.I3(\skid_buffer[20]_i_5_n_0 ),
.I4(\skid_buffer[20]_i_6_n_0 ),
.I5(\skid_buffer[20]_i_7_n_0 ),
.O(\skid_buffer[20]_i_1_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[20]_i_2
(.I0(m_axi_rdata[369]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[337]),
.O(\skid_buffer[20]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[20]_i_3
(.I0(m_axi_rdata[273]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[305]),
.O(\skid_buffer[20]_i_3_n_0 ));
LUT6 #(
.INIT(64'h22F222F2FFFF22F2))
\skid_buffer[20]_i_4
(.I0(m_axi_rdata[17]),
.I1(\skid_buffer_reg[3]_0 ),
.I2(m_axi_rdata[433]),
.I3(\skid_buffer[34]_i_8_n_0 ),
.I4(m_axi_rdata[401]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[20]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[20]_i_5
(.I0(m_axi_rdata[81]),
.I1(m_axi_rdata[49]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[113]),
.O(\skid_buffer[20]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[20]_i_6
(.I0(m_axi_rdata[209]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[241]),
.O(\skid_buffer[20]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[20]_i_7
(.I0(m_axi_rdata[145]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[177]),
.O(\skid_buffer[20]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[21]_i_1
(.I0(\skid_buffer[21]_i_2_n_0 ),
.I1(\skid_buffer[21]_i_3_n_0 ),
.I2(\skid_buffer[21]_i_4_n_0 ),
.I3(\skid_buffer[21]_i_5_n_0 ),
.I4(\skid_buffer[21]_i_6_n_0 ),
.I5(\skid_buffer[21]_i_7_n_0 ),
.O(\skid_buffer[21]_i_1_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[21]_i_2
(.I0(m_axi_rdata[370]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[338]),
.O(\skid_buffer[21]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000000C0000000A0))
\skid_buffer[21]_i_3
(.I0(m_axi_rdata[274]),
.I1(m_axi_rdata[306]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(\m_atarget_enc_reg[0]_rep ),
.O(\skid_buffer[21]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[21]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[18]),
.I2(m_axi_rdata[402]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[434]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[21]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[21]_i_5
(.I0(m_axi_rdata[82]),
.I1(m_axi_rdata[50]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[114]),
.O(\skid_buffer[21]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[21]_i_6
(.I0(m_axi_rdata[242]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[210]),
.O(\skid_buffer[21]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[21]_i_7
(.I0(m_axi_rdata[146]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[178]),
.O(\skid_buffer[21]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[22]_i_1
(.I0(\skid_buffer[22]_i_2_n_0 ),
.I1(\skid_buffer[22]_i_3_n_0 ),
.I2(\skid_buffer[22]_i_4_n_0 ),
.I3(\skid_buffer[22]_i_5_n_0 ),
.I4(\skid_buffer[22]_i_6_n_0 ),
.I5(\skid_buffer[22]_i_7_n_0 ),
.O(\skid_buffer[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[22]_i_2
(.I0(m_axi_rdata[339]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[371]),
.O(\skid_buffer[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[22]_i_3
(.I0(m_axi_rdata[307]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[275]),
.O(\skid_buffer[22]_i_3_n_0 ));
LUT6 #(
.INIT(64'h22F222F2FFFF22F2))
\skid_buffer[22]_i_4
(.I0(m_axi_rdata[435]),
.I1(\skid_buffer[34]_i_8_n_0 ),
.I2(m_axi_rdata[403]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[19]),
.I5(\skid_buffer_reg[3]_0 ),
.O(\skid_buffer[22]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[22]_i_5
(.I0(m_axi_rdata[83]),
.I1(m_axi_rdata[51]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[115]),
.O(\skid_buffer[22]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[22]_i_6
(.I0(m_axi_rdata[211]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[243]),
.O(\skid_buffer[22]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[22]_i_7
(.I0(m_axi_rdata[179]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[147]),
.O(\skid_buffer[22]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[23]_i_1
(.I0(\skid_buffer[23]_i_2_n_0 ),
.I1(\skid_buffer[23]_i_3_n_0 ),
.I2(\skid_buffer[23]_i_4_n_0 ),
.I3(\skid_buffer[23]_i_5_n_0 ),
.I4(\skid_buffer[23]_i_6_n_0 ),
.I5(\skid_buffer[23]_i_7_n_0 ),
.O(\skid_buffer[23]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[23]_i_2
(.I0(m_axi_rdata[340]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[372]),
.O(\skid_buffer[23]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[23]_i_3
(.I0(m_axi_rdata[308]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[276]),
.O(\skid_buffer[23]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[23]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[20]),
.I2(\skid_buffer[34]_i_8_n_0 ),
.I3(m_axi_rdata[436]),
.I4(m_axi_rdata[404]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0C0F0A000C000A00))
\skid_buffer[23]_i_5
(.I0(m_axi_rdata[52]),
.I1(m_axi_rdata[116]),
.I2(\skid_buffer_reg[3]_2 ),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[84]),
.O(\skid_buffer[23]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[23]_i_6
(.I0(m_axi_rdata[244]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[212]),
.O(\skid_buffer[23]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[23]_i_7
(.I0(m_axi_rdata[148]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[180]),
.O(\skid_buffer[23]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[24]_i_1
(.I0(\skid_buffer[24]_i_2_n_0 ),
.I1(\skid_buffer[24]_i_3_n_0 ),
.I2(\skid_buffer[24]_i_4_n_0 ),
.I3(\skid_buffer[24]_i_5_n_0 ),
.I4(\skid_buffer[24]_i_6_n_0 ),
.I5(\skid_buffer[24]_i_7_n_0 ),
.O(\skid_buffer[24]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[24]_i_2
(.I0(m_axi_rdata[341]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[373]),
.O(\skid_buffer[24]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[24]_i_3
(.I0(m_axi_rdata[277]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[309]),
.O(\skid_buffer[24]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[24]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[21]),
.I2(\skid_buffer_reg[3]_1 ),
.I3(m_axi_rdata[405]),
.I4(m_axi_rdata[437]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[24]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[24]_i_5
(.I0(m_axi_rdata[85]),
.I1(m_axi_rdata[53]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[117]),
.O(\skid_buffer[24]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[24]_i_6
(.I0(m_axi_rdata[213]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[245]),
.O(\skid_buffer[24]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[24]_i_7
(.I0(m_axi_rdata[181]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[149]),
.O(\skid_buffer[24]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[25]_i_1
(.I0(\skid_buffer[25]_i_2_n_0 ),
.I1(\skid_buffer[25]_i_3_n_0 ),
.I2(\skid_buffer[25]_i_4_n_0 ),
.I3(\skid_buffer[25]_i_5_n_0 ),
.I4(\skid_buffer[25]_i_6_n_0 ),
.I5(\skid_buffer[25]_i_7_n_0 ),
.O(\skid_buffer[25]_i_1_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[25]_i_2
(.I0(m_axi_rdata[374]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rdata[342]),
.O(\skid_buffer[25]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000000C0000000A0))
\skid_buffer[25]_i_3
(.I0(m_axi_rdata[278]),
.I1(m_axi_rdata[310]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.I5(m_atarget_enc[0]),
.O(\skid_buffer[25]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[25]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[22]),
.I2(m_axi_rdata[406]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[438]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[25]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[25]_i_5
(.I0(m_axi_rdata[86]),
.I1(m_axi_rdata[54]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[118]),
.O(\skid_buffer[25]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[25]_i_6
(.I0(m_axi_rdata[246]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rdata[214]),
.O(\skid_buffer[25]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[25]_i_7
(.I0(m_axi_rdata[150]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[182]),
.O(\skid_buffer[25]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[26]_i_1
(.I0(\skid_buffer[26]_i_2_n_0 ),
.I1(\skid_buffer[26]_i_3_n_0 ),
.I2(\skid_buffer[26]_i_4_n_0 ),
.I3(\skid_buffer[26]_i_5_n_0 ),
.I4(\skid_buffer[26]_i_6_n_0 ),
.I5(\skid_buffer[26]_i_7_n_0 ),
.O(\skid_buffer[26]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[26]_i_2
(.I0(m_axi_rdata[343]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[375]),
.O(\skid_buffer[26]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[26]_i_3
(.I0(m_axi_rdata[279]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[311]),
.O(\skid_buffer[26]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[26]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[23]),
.I2(\skid_buffer[34]_i_8_n_0 ),
.I3(m_axi_rdata[439]),
.I4(m_axi_rdata[407]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[26]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[26]_i_5
(.I0(m_axi_rdata[87]),
.I1(m_axi_rdata[55]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[119]),
.O(\skid_buffer[26]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[26]_i_6
(.I0(m_axi_rdata[247]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rdata[215]),
.O(\skid_buffer[26]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[26]_i_7
(.I0(m_axi_rdata[151]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[183]),
.O(\skid_buffer[26]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[27]_i_1
(.I0(\skid_buffer[27]_i_2_n_0 ),
.I1(\skid_buffer[27]_i_3_n_0 ),
.I2(\skid_buffer[27]_i_4_n_0 ),
.I3(\skid_buffer[27]_i_5_n_0 ),
.I4(\skid_buffer[27]_i_6_n_0 ),
.I5(\skid_buffer[27]_i_7_n_0 ),
.O(\skid_buffer[27]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A000C000000000))
\skid_buffer[27]_i_2
(.I0(m_axi_rdata[376]),
.I1(m_axi_rdata[344]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[0]),
.I5(m_atarget_enc[1]),
.O(\skid_buffer[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[27]_i_3
(.I0(m_axi_rdata[312]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[280]),
.O(\skid_buffer[27]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[27]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[24]),
.I2(m_axi_rdata[440]),
.I3(\skid_buffer[34]_i_8_n_0 ),
.I4(m_axi_rdata[408]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[27]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[27]_i_5
(.I0(m_axi_rdata[88]),
.I1(m_axi_rdata[56]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[120]),
.O(\skid_buffer[27]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[27]_i_6
(.I0(m_axi_rdata[248]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rdata[216]),
.O(\skid_buffer[27]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[27]_i_7
(.I0(m_axi_rdata[184]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[152]),
.O(\skid_buffer[27]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[28]_i_1
(.I0(\skid_buffer[28]_i_2_n_0 ),
.I1(\skid_buffer[28]_i_3_n_0 ),
.I2(\skid_buffer[28]_i_4_n_0 ),
.I3(\skid_buffer[28]_i_5_n_0 ),
.I4(\skid_buffer[28]_i_6_n_0 ),
.I5(\skid_buffer[28]_i_7_n_0 ),
.O(\skid_buffer[28]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[28]_i_2
(.I0(m_axi_rdata[345]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[377]),
.O(\skid_buffer[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[28]_i_3
(.I0(m_axi_rdata[313]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[281]),
.O(\skid_buffer[28]_i_3_n_0 ));
LUT6 #(
.INIT(64'h22F222F2FFFF22F2))
\skid_buffer[28]_i_4
(.I0(m_axi_rdata[441]),
.I1(\skid_buffer[34]_i_8_n_0 ),
.I2(m_axi_rdata[409]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[25]),
.I5(\skid_buffer_reg[3]_0 ),
.O(\skid_buffer[28]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\skid_buffer[28]_i_5
(.I0(m_axi_rdata[89]),
.I1(m_axi_rdata[121]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[57]),
.O(\skid_buffer[28]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[28]_i_6
(.I0(m_axi_rdata[217]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[249]),
.O(\skid_buffer[28]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[28]_i_7
(.I0(m_axi_rdata[153]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[185]),
.O(\skid_buffer[28]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[29]_i_1
(.I0(\skid_buffer[29]_i_2_n_0 ),
.I1(\skid_buffer[29]_i_3_n_0 ),
.I2(\skid_buffer[29]_i_4_n_0 ),
.I3(\skid_buffer[29]_i_5_n_0 ),
.I4(\skid_buffer[29]_i_6_n_0 ),
.I5(\skid_buffer[29]_i_7_n_0 ),
.O(\skid_buffer[29]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[29]_i_2
(.I0(m_axi_rdata[346]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[378]),
.O(\skid_buffer[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[29]_i_3
(.I0(m_axi_rdata[282]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[314]),
.O(\skid_buffer[29]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[29]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[26]),
.I2(\skid_buffer[34]_i_8_n_0 ),
.I3(m_axi_rdata[442]),
.I4(m_axi_rdata[410]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[29]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\skid_buffer[29]_i_5
(.I0(m_axi_rdata[90]),
.I1(m_axi_rdata[122]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[58]),
.O(\skid_buffer[29]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[29]_i_6
(.I0(m_axi_rdata[250]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rdata[218]),
.O(\skid_buffer[29]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[29]_i_7
(.I0(m_axi_rdata[154]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[186]),
.O(\skid_buffer[29]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[30]_i_1
(.I0(\skid_buffer[30]_i_2_n_0 ),
.I1(\skid_buffer[30]_i_3_n_0 ),
.I2(\skid_buffer[30]_i_4_n_0 ),
.I3(\skid_buffer[30]_i_5_n_0 ),
.I4(\skid_buffer[30]_i_6_n_0 ),
.I5(\skid_buffer[30]_i_7_n_0 ),
.O(\skid_buffer[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[30]_i_2
(.I0(m_axi_rdata[347]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[379]),
.O(\skid_buffer[30]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[30]_i_3
(.I0(m_axi_rdata[283]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[315]),
.O(\skid_buffer[30]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[30]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[27]),
.I2(\skid_buffer_reg[3]_1 ),
.I3(m_axi_rdata[411]),
.I4(m_axi_rdata[443]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[30]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[30]_i_5
(.I0(m_axi_rdata[91]),
.I1(m_axi_rdata[59]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[123]),
.O(\skid_buffer[30]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[30]_i_6
(.I0(m_axi_rdata[219]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[251]),
.O(\skid_buffer[30]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[30]_i_7
(.I0(m_axi_rdata[187]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[155]),
.O(\skid_buffer[30]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[31]_i_1
(.I0(\skid_buffer[31]_i_2_n_0 ),
.I1(\skid_buffer[31]_i_3_n_0 ),
.I2(\skid_buffer[31]_i_4_n_0 ),
.I3(\skid_buffer[31]_i_5_n_0 ),
.I4(\skid_buffer[31]_i_6_n_0 ),
.I5(\skid_buffer[31]_i_7_n_0 ),
.O(\skid_buffer[31]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[31]_i_2
(.I0(m_axi_rdata[348]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[380]),
.O(\skid_buffer[31]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[31]_i_3
(.I0(m_axi_rdata[284]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[316]),
.O(\skid_buffer[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[31]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[28]),
.I2(\skid_buffer[34]_i_8_n_0 ),
.I3(m_axi_rdata[444]),
.I4(m_axi_rdata[412]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[31]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\skid_buffer[31]_i_5
(.I0(m_axi_rdata[92]),
.I1(m_axi_rdata[124]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[60]),
.O(\skid_buffer[31]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[31]_i_6
(.I0(m_axi_rdata[252]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rdata[220]),
.O(\skid_buffer[31]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[31]_i_7
(.I0(m_axi_rdata[156]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[188]),
.O(\skid_buffer[31]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[32]_i_1
(.I0(\skid_buffer[32]_i_2_n_0 ),
.I1(\skid_buffer[32]_i_3_n_0 ),
.I2(\skid_buffer[32]_i_4_n_0 ),
.I3(\skid_buffer[32]_i_5_n_0 ),
.I4(\skid_buffer[32]_i_6_n_0 ),
.I5(\skid_buffer[32]_i_7_n_0 ),
.O(\skid_buffer[32]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[32]_i_2
(.I0(m_axi_rdata[349]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[381]),
.O(\skid_buffer[32]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000000C0000000A0))
\skid_buffer[32]_i_3
(.I0(m_axi_rdata[285]),
.I1(m_axi_rdata[317]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.I5(m_atarget_enc[0]),
.O(\skid_buffer[32]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[32]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[29]),
.I2(m_axi_rdata[445]),
.I3(\skid_buffer[34]_i_8_n_0 ),
.I4(m_axi_rdata[413]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[32]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[32]_i_5
(.I0(m_axi_rdata[93]),
.I1(m_axi_rdata[61]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[125]),
.O(\skid_buffer[32]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[32]_i_6
(.I0(m_axi_rdata[253]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rdata[221]),
.O(\skid_buffer[32]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[32]_i_7
(.I0(m_axi_rdata[157]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[189]),
.O(\skid_buffer[32]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[33]_i_1
(.I0(\skid_buffer[33]_i_2_n_0 ),
.I1(\skid_buffer[33]_i_3_n_0 ),
.I2(\skid_buffer[33]_i_4_n_0 ),
.I3(\skid_buffer[33]_i_5_n_0 ),
.I4(\skid_buffer[33]_i_6_n_0 ),
.I5(\skid_buffer[33]_i_7_n_0 ),
.O(\skid_buffer[33]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[33]_i_2
(.I0(m_axi_rdata[350]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[382]),
.O(\skid_buffer[33]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[33]_i_3
(.I0(m_axi_rdata[318]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[286]),
.O(\skid_buffer[33]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[33]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[30]),
.I2(m_axi_rdata[446]),
.I3(\skid_buffer[34]_i_8_n_0 ),
.I4(m_axi_rdata[414]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[33]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[33]_i_5
(.I0(m_axi_rdata[94]),
.I1(m_axi_rdata[62]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[126]),
.O(\skid_buffer[33]_i_5_n_0 ));
LUT6 #(
.INIT(64'h00C0000000A00000))
\skid_buffer[33]_i_6
(.I0(m_axi_rdata[222]),
.I1(m_axi_rdata[254]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[3]),
.I4(m_atarget_enc[1]),
.I5(m_atarget_enc[0]),
.O(\skid_buffer[33]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[33]_i_7
(.I0(m_axi_rdata[190]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[158]),
.O(\skid_buffer[33]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[34]_i_1
(.I0(\skid_buffer[34]_i_2_n_0 ),
.I1(\skid_buffer[34]_i_3_n_0 ),
.I2(\skid_buffer[34]_i_4_n_0 ),
.I3(\skid_buffer[34]_i_5_n_0 ),
.I4(\skid_buffer[34]_i_6_n_0 ),
.I5(\skid_buffer[34]_i_7_n_0 ),
.O(\skid_buffer[34]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[34]_i_2
(.I0(m_axi_rdata[351]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[383]),
.O(\skid_buffer[34]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[34]_i_3
(.I0(m_axi_rdata[287]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[319]),
.O(\skid_buffer[34]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[34]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[31]),
.I2(\skid_buffer_reg[3]_1 ),
.I3(m_axi_rdata[415]),
.I4(m_axi_rdata[447]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[34]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\skid_buffer[34]_i_5
(.I0(m_axi_rdata[95]),
.I1(m_axi_rdata[127]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[63]),
.O(\skid_buffer[34]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[34]_i_6
(.I0(m_axi_rdata[255]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_rdata[223]),
.O(\skid_buffer[34]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[34]_i_7
(.I0(m_axi_rdata[159]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rdata[191]),
.O(\skid_buffer[34]_i_7_n_0 ));
LUT4 #(
.INIT(16'hF7FF))
\skid_buffer[34]_i_8
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.O(\skid_buffer[34]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[3]_i_1
(.I0(\skid_buffer[3]_i_2_n_0 ),
.I1(\skid_buffer[3]_i_3_n_0 ),
.I2(\skid_buffer[3]_i_4_n_0 ),
.I3(\skid_buffer[3]_i_5_n_0 ),
.I4(\skid_buffer[3]_i_6_n_0 ),
.I5(\skid_buffer[3]_i_7_n_0 ),
.O(\skid_buffer[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[3]_i_2
(.I0(m_axi_rdata[320]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[352]),
.O(\skid_buffer[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[3]_i_3
(.I0(m_axi_rdata[256]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[288]),
.O(\skid_buffer[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h22F222F2FFFF22F2))
\skid_buffer[3]_i_4
(.I0(m_axi_rdata[0]),
.I1(\skid_buffer_reg[3]_0 ),
.I2(m_axi_rdata[384]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[416]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[3]_i_5
(.I0(m_axi_rdata[64]),
.I1(m_axi_rdata[32]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[96]),
.O(\skid_buffer[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[3]_i_6
(.I0(m_axi_rdata[192]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[224]),
.O(\skid_buffer[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[3]_i_7
(.I0(m_axi_rdata[160]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[1]),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[128]),
.O(\skid_buffer[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[4]_i_1
(.I0(\skid_buffer[4]_i_2_n_0 ),
.I1(\skid_buffer[4]_i_3_n_0 ),
.I2(\skid_buffer[4]_i_4_n_0 ),
.I3(\skid_buffer[4]_i_5_n_0 ),
.I4(\skid_buffer[4]_i_6_n_0 ),
.I5(\skid_buffer[4]_i_7_n_0 ),
.O(\skid_buffer[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A000C000000000))
\skid_buffer[4]_i_2
(.I0(m_axi_rdata[353]),
.I1(m_axi_rdata[321]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(\m_atarget_enc_reg[1]_rep ),
.O(\skid_buffer[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[4]_i_3
(.I0(m_axi_rdata[289]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[257]),
.O(\skid_buffer[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[4]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[1]),
.I2(m_axi_rdata[417]),
.I3(\skid_buffer[34]_i_8_n_0 ),
.I4(m_axi_rdata[385]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[4]_i_5
(.I0(m_axi_rdata[65]),
.I1(m_axi_rdata[33]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[97]),
.O(\skid_buffer[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[4]_i_6
(.I0(m_axi_rdata[225]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[193]),
.O(\skid_buffer[4]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[4]_i_7
(.I0(m_axi_rdata[161]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[129]),
.O(\skid_buffer[4]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[5]_i_1
(.I0(\skid_buffer[5]_i_2_n_0 ),
.I1(\skid_buffer[5]_i_3_n_0 ),
.I2(\skid_buffer[5]_i_4_n_0 ),
.I3(\skid_buffer[5]_i_5_n_0 ),
.I4(\skid_buffer[5]_i_6_n_0 ),
.I5(\skid_buffer[5]_i_7_n_0 ),
.O(\skid_buffer[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[5]_i_2
(.I0(m_axi_rdata[322]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[354]),
.O(\skid_buffer[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[5]_i_3
(.I0(m_axi_rdata[258]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[290]),
.O(\skid_buffer[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[5]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[2]),
.I2(\skid_buffer_reg[3]_1 ),
.I3(m_axi_rdata[386]),
.I4(m_axi_rdata[418]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[5]_i_5
(.I0(m_axi_rdata[66]),
.I1(m_axi_rdata[34]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[98]),
.O(\skid_buffer[5]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[5]_i_6
(.I0(m_axi_rdata[194]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[226]),
.O(\skid_buffer[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[5]_i_7
(.I0(m_axi_rdata[162]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[130]),
.O(\skid_buffer[5]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[6]_i_1
(.I0(\skid_buffer[6]_i_2_n_0 ),
.I1(\skid_buffer[6]_i_3_n_0 ),
.I2(\skid_buffer[6]_i_4_n_0 ),
.I3(\skid_buffer[6]_i_5_n_0 ),
.I4(\skid_buffer[6]_i_6_n_0 ),
.I5(\skid_buffer[6]_i_7_n_0 ),
.O(\skid_buffer[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[6]_i_2
(.I0(m_axi_rdata[323]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[355]),
.O(\skid_buffer[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[6]_i_3
(.I0(m_axi_rdata[291]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[259]),
.O(\skid_buffer[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\skid_buffer[6]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[3]),
.I2(\skid_buffer_reg[3]_1 ),
.I3(m_axi_rdata[387]),
.I4(m_axi_rdata[419]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\skid_buffer[6]_i_5
(.I0(m_axi_rdata[67]),
.I1(m_axi_rdata[99]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[35]),
.O(\skid_buffer[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[6]_i_6
(.I0(m_axi_rdata[227]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[195]),
.O(\skid_buffer[6]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[6]_i_7
(.I0(m_axi_rdata[131]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[163]),
.O(\skid_buffer[6]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[7]_i_1
(.I0(\skid_buffer[7]_i_2_n_0 ),
.I1(\skid_buffer[7]_i_3_n_0 ),
.I2(\skid_buffer[7]_i_4_n_0 ),
.I3(\skid_buffer[7]_i_5_n_0 ),
.I4(\skid_buffer[7]_i_6_n_0 ),
.I5(\skid_buffer[7]_i_7_n_0 ),
.O(\skid_buffer[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[7]_i_2
(.I0(m_axi_rdata[356]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[324]),
.O(\skid_buffer[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000000A0000000C0))
\skid_buffer[7]_i_3
(.I0(m_axi_rdata[292]),
.I1(m_axi_rdata[260]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(\m_atarget_enc_reg[0]_rep ),
.O(\skid_buffer[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[7]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[4]),
.I2(m_axi_rdata[388]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[420]),
.I5(\skid_buffer[34]_i_8_n_0 ),
.O(\skid_buffer[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[7]_i_5
(.I0(m_axi_rdata[68]),
.I1(m_axi_rdata[36]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[100]),
.O(\skid_buffer[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[7]_i_6
(.I0(m_axi_rdata[196]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[228]),
.O(\skid_buffer[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[7]_i_7
(.I0(m_axi_rdata[132]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[164]),
.O(\skid_buffer[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[8]_i_1
(.I0(\skid_buffer[8]_i_2_n_0 ),
.I1(\skid_buffer[8]_i_3_n_0 ),
.I2(\skid_buffer[8]_i_4_n_0 ),
.I3(\skid_buffer[8]_i_5_n_0 ),
.I4(\skid_buffer[8]_i_6_n_0 ),
.I5(\skid_buffer[8]_i_7_n_0 ),
.O(\skid_buffer[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0C00080000000800))
\skid_buffer[8]_i_2
(.I0(m_axi_rdata[325]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[357]),
.O(\skid_buffer[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[8]_i_3
(.I0(m_axi_rdata[293]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[261]),
.O(\skid_buffer[8]_i_3_n_0 ));
LUT6 #(
.INIT(64'h22F222F2FFFF22F2))
\skid_buffer[8]_i_4
(.I0(m_axi_rdata[421]),
.I1(\skid_buffer[34]_i_8_n_0 ),
.I2(m_axi_rdata[389]),
.I3(\skid_buffer_reg[3]_1 ),
.I4(m_axi_rdata[5]),
.I5(\skid_buffer_reg[3]_0 ),
.O(\skid_buffer[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000CAF00000CA00))
\skid_buffer[8]_i_5
(.I0(m_axi_rdata[69]),
.I1(m_axi_rdata[101]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[37]),
.O(\skid_buffer[8]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[8]_i_6
(.I0(m_axi_rdata[229]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[197]),
.O(\skid_buffer[8]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[8]_i_7
(.I0(m_axi_rdata[133]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[165]),
.O(\skid_buffer[8]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\skid_buffer[9]_i_1
(.I0(\skid_buffer[9]_i_2_n_0 ),
.I1(\skid_buffer[9]_i_3_n_0 ),
.I2(\skid_buffer[9]_i_4_n_0 ),
.I3(\skid_buffer[9]_i_5_n_0 ),
.I4(\skid_buffer[9]_i_6_n_0 ),
.I5(\skid_buffer[9]_i_7_n_0 ),
.O(\skid_buffer[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A000C000000000))
\skid_buffer[9]_i_2
(.I0(m_axi_rdata[358]),
.I1(m_axi_rdata[326]),
.I2(m_atarget_enc[3]),
.I3(m_atarget_enc[2]),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(\m_atarget_enc_reg[1]_rep ),
.O(\skid_buffer[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0008000C00080000))
\skid_buffer[9]_i_3
(.I0(m_axi_rdata[294]),
.I1(m_atarget_enc[3]),
.I2(m_atarget_enc[2]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[262]),
.O(\skid_buffer[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\skid_buffer[9]_i_4
(.I0(\skid_buffer_reg[3]_0 ),
.I1(m_axi_rdata[6]),
.I2(m_axi_rdata[422]),
.I3(\skid_buffer[34]_i_8_n_0 ),
.I4(m_axi_rdata[390]),
.I5(\skid_buffer_reg[3]_1 ),
.O(\skid_buffer[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FAC000000AC0))
\skid_buffer[9]_i_5
(.I0(m_axi_rdata[70]),
.I1(m_axi_rdata[38]),
.I2(\m_atarget_enc_reg[0]_rep ),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\skid_buffer_reg[3]_2 ),
.I5(m_axi_rdata[102]),
.O(\skid_buffer[9]_i_5_n_0 ));
LUT6 #(
.INIT(64'h080C000008000000))
\skid_buffer[9]_i_6
(.I0(m_axi_rdata[230]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[0]_rep ),
.I4(\m_atarget_enc_reg[1]_rep ),
.I5(m_axi_rdata[198]),
.O(\skid_buffer[9]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000C000800000008))
\skid_buffer[9]_i_7
(.I0(m_axi_rdata[134]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[3]),
.I3(\m_atarget_enc_reg[1]_rep ),
.I4(\m_atarget_enc_reg[0]_rep ),
.I5(m_axi_rdata[166]),
.O(\skid_buffer[9]_i_7_n_0 ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[0]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[10]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[11]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[12]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[13]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[14]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[15]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[16]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[17]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[18]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[19]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[20]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[21]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[22]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[23]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[24]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[25]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[26]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[27]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[28]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[29]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[30]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[31]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[32]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[33]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[34]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[3]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[4]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[5]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[6]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[7]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[8]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[9]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/19.1std/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2018/11/07 $
// $Author: psgswbuild $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DFRTP_PP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module bpm_from_interval(
input [31:0] counter, //Interval to calculate BPM from
input wire [7:0] default_bpm, //Default BPM to use if no beats are detected
output wire [7:0] counted_bpm //Calculated BPM
);
assign counted_bpm = (counter < 32'd23529 ) ? 254 : //Less than interval corresponding to 255 BPM
(counter < 32'd23622 ) ? 253 : //Less than interval corresponding to 254 BPM
(counter < 32'd23715 ) ? 252 : //etc...
(counter < 32'd23809 ) ? 251 :
(counter < 32'd23904 ) ? 250 :
(counter < 32'd24000 ) ? 249 :
(counter < 32'd24096 ) ? 248 :
(counter < 32'd24193 ) ? 247 :
(counter < 32'd24291 ) ? 246 :
(counter < 32'd24390 ) ? 245 :
(counter < 32'd24489 ) ? 244 :
(counter < 32'd24590 ) ? 243 :
(counter < 32'd24691 ) ? 242 :
(counter < 32'd24793 ) ? 241 :
(counter < 32'd24896 ) ? 240 :
(counter < 32'd25000 ) ? 239 :
(counter < 32'd25104 ) ? 238 :
(counter < 32'd25210 ) ? 237 :
(counter < 32'd25316 ) ? 236 :
(counter < 32'd25423 ) ? 235 :
(counter < 32'd25531 ) ? 234 :
(counter < 32'd25641 ) ? 233 :
(counter < 32'd25751 ) ? 232 :
(counter < 32'd25862 ) ? 231 :
(counter < 32'd25974 ) ? 230 :
(counter < 32'd26086 ) ? 229 :
(counter < 32'd26200 ) ? 228 :
(counter < 32'd26315 ) ? 227 :
(counter < 32'd26431 ) ? 226 :
(counter < 32'd26548 ) ? 225 :
(counter < 32'd26666 ) ? 224 :
(counter < 32'd26785 ) ? 223 :
(counter < 32'd26905 ) ? 222 :
(counter < 32'd27027 ) ? 221 :
(counter < 32'd27149 ) ? 220 :
(counter < 32'd27272 ) ? 219 :
(counter < 32'd27397 ) ? 218 :
(counter < 32'd27522 ) ? 217 :
(counter < 32'd27649 ) ? 216 :
(counter < 32'd27777 ) ? 215 :
(counter < 32'd27906 ) ? 214 :
(counter < 32'd28037 ) ? 213 :
(counter < 32'd28169 ) ? 212 :
(counter < 32'd28301 ) ? 211 :
(counter < 32'd28436 ) ? 210 :
(counter < 32'd28571 ) ? 209 :
(counter < 32'd28708 ) ? 208 :
(counter < 32'd28846 ) ? 207 :
(counter < 32'd28985 ) ? 206 :
(counter < 32'd29126 ) ? 205 :
(counter < 32'd29268 ) ? 204 :
(counter < 32'd29411 ) ? 203 :
(counter < 32'd29556 ) ? 202 :
(counter < 32'd29702 ) ? 201 :
(counter < 32'd29850 ) ? 200 :
(counter < 32'd30000 ) ? 199 :
(counter < 32'd30150 ) ? 198 :
(counter < 32'd30303 ) ? 197 :
(counter < 32'd30456 ) ? 196 :
(counter < 32'd30612 ) ? 195 :
(counter < 32'd30769 ) ? 194 :
(counter < 32'd30927 ) ? 193 :
(counter < 32'd31088 ) ? 192 :
(counter < 32'd31250 ) ? 191 :
(counter < 32'd31413 ) ? 190 :
(counter < 32'd31578 ) ? 189 :
(counter < 32'd31746 ) ? 188 :
(counter < 32'd31914 ) ? 187 :
(counter < 32'd32085 ) ? 186 :
(counter < 32'd32258 ) ? 185 :
(counter < 32'd32432 ) ? 184 :
(counter < 32'd32608 ) ? 183 :
(counter < 32'd32786 ) ? 182 :
(counter < 32'd32967 ) ? 181 :
(counter < 32'd33149 ) ? 180 :
(counter < 32'd33333 ) ? 179 :
(counter < 32'd33519 ) ? 178 :
(counter < 32'd33707 ) ? 177 :
(counter < 32'd33898 ) ? 176 :
(counter < 32'd34090 ) ? 175 :
(counter < 32'd34285 ) ? 174 :
(counter < 32'd34482 ) ? 173 :
(counter < 32'd34682 ) ? 172 :
(counter < 32'd34883 ) ? 171 :
(counter < 32'd35087 ) ? 170 :
(counter < 32'd35294 ) ? 169 :
(counter < 32'd35502 ) ? 168 :
(counter < 32'd35714 ) ? 167 :
(counter < 32'd35928 ) ? 166 :
(counter < 32'd36144 ) ? 165 :
(counter < 32'd36363 ) ? 164 :
(counter < 32'd36585 ) ? 163 :
(counter < 32'd36809 ) ? 162 :
(counter < 32'd37037 ) ? 161 :
(counter < 32'd37267 ) ? 160 :
(counter < 32'd37500 ) ? 159 :
(counter < 32'd37735 ) ? 158 :
(counter < 32'd37974 ) ? 157 :
(counter < 32'd38216 ) ? 156 :
(counter < 32'd38461 ) ? 155 :
(counter < 32'd38709 ) ? 154 :
(counter < 32'd38961 ) ? 153 :
(counter < 32'd39215 ) ? 152 :
(counter < 32'd39473 ) ? 151 :
(counter < 32'd39735 ) ? 150 :
(counter < 32'd40000 ) ? 149 :
(counter < 32'd40268 ) ? 148 :
(counter < 32'd40540 ) ? 147 :
(counter < 32'd40816 ) ? 146 :
(counter < 32'd41095 ) ? 145 :
(counter < 32'd41379 ) ? 144 :
(counter < 32'd41666 ) ? 143 :
(counter < 32'd41958 ) ? 142 :
(counter < 32'd42253 ) ? 141 :
(counter < 32'd42553 ) ? 140 :
(counter < 32'd42857 ) ? 139 :
(counter < 32'd43165 ) ? 138 :
(counter < 32'd43478 ) ? 137 :
(counter < 32'd43795 ) ? 136 :
(counter < 32'd44117 ) ? 135 :
(counter < 32'd44444 ) ? 134 :
(counter < 32'd44776 ) ? 133 :
(counter < 32'd45112 ) ? 132 :
(counter < 32'd45454 ) ? 131 :
(counter < 32'd45801 ) ? 130 :
(counter < 32'd46153 ) ? 129 :
(counter < 32'd46511 ) ? 128 :
(counter < 32'd46875 ) ? 127 :
(counter < 32'd47244 ) ? 126 :
(counter < 32'd47619 ) ? 125 :
(counter < 32'd48000 ) ? 124 :
(counter < 32'd48387 ) ? 123 :
(counter < 32'd48780 ) ? 122 :
(counter < 32'd49180 ) ? 121 :
(counter < 32'd49586 ) ? 120 :
(counter < 32'd50000 ) ? 119 :
(counter < 32'd50420 ) ? 118 :
(counter < 32'd50847 ) ? 117 :
(counter < 32'd51282 ) ? 116 :
(counter < 32'd51724 ) ? 115 :
(counter < 32'd52173 ) ? 114 :
(counter < 32'd52631 ) ? 113 :
(counter < 32'd53097 ) ? 112 :
(counter < 32'd53571 ) ? 111 :
(counter < 32'd54054 ) ? 110 :
(counter < 32'd54545 ) ? 109 :
(counter < 32'd55045 ) ? 108 :
(counter < 32'd55555 ) ? 107 :
(counter < 32'd56074 ) ? 106 :
(counter < 32'd56603 ) ? 105 :
(counter < 32'd57142 ) ? 104 :
(counter < 32'd57692 ) ? 103 :
(counter < 32'd58252 ) ? 102 :
(counter < 32'd58823 ) ? 101 :
(counter < 32'd59405 ) ? 100 :
(counter < 32'd60000 ) ? 99 :
(counter < 32'd60606 ) ? 98 :
(counter < 32'd61224 ) ? 97 :
(counter < 32'd61855 ) ? 96 :
(counter < 32'd62500 ) ? 95 :
(counter < 32'd63157 ) ? 94 :
(counter < 32'd63829 ) ? 93 :
(counter < 32'd64516 ) ? 92 :
(counter < 32'd65217 ) ? 91 :
(counter < 32'd65934 ) ? 90 :
(counter < 32'd66666 ) ? 89 :
(counter < 32'd67415 ) ? 88 :
(counter < 32'd68181 ) ? 87 :
(counter < 32'd68965 ) ? 86 :
(counter < 32'd69767 ) ? 85 :
(counter < 32'd70588 ) ? 84 :
(counter < 32'd71428 ) ? 83 :
(counter < 32'd72289 ) ? 82 :
(counter < 32'd73170 ) ? 81 :
(counter < 32'd74074 ) ? 80 :
(counter < 32'd75000 ) ? 79 :
(counter < 32'd75949 ) ? 78 :
(counter < 32'd76923 ) ? 77 :
(counter < 32'd77922 ) ? 76 :
(counter < 32'd78947 ) ? 75 :
(counter < 32'd80000 ) ? 74 :
(counter < 32'd81081 ) ? 73 :
(counter < 32'd82191 ) ? 72 :
(counter < 32'd83333 ) ? 71 :
(counter < 32'd84507 ) ? 70 :
(counter < 32'd85714 ) ? 69 :
(counter < 32'd86956 ) ? 68 :
(counter < 32'd88235 ) ? 67 :
(counter < 32'd89552 ) ? 66 :
(counter < 32'd90909 ) ? 65 :
(counter < 32'd92307 ) ? 64 :
(counter < 32'd93750 ) ? 63 :
(counter < 32'd95238 ) ? 62 :
(counter < 32'd96774 ) ? 61 :
(counter < 32'd98360 ) ? 60 :
(counter < 32'd100000 ) ? 59 :
(counter < 32'd101694 ) ? 58 :
(counter < 32'd103448 ) ? 57 :
(counter < 32'd105263 ) ? 56 :
(counter < 32'd107142 ) ? 55 :
(counter < 32'd109090 ) ? 54 :
(counter < 32'd111111 ) ? 53 :
(counter < 32'd113207 ) ? 52 :
(counter < 32'd115384 ) ? 51 :
(counter < 32'd117647 ) ? 50 :
(counter < 32'd120000 ) ? 49 :
(counter < 32'd122448 ) ? 48 :
(counter < 32'd125000 ) ? 47 :
(counter < 32'd127659 ) ? 46 :
(counter < 32'd130434 ) ? 45 :
(counter < 32'd133333 ) ? 44 :
(counter < 32'd136363 ) ? 43 :
(counter < 32'd139534 ) ? 42 :
(counter < 32'd142857 ) ? 41 :
(counter < 32'd146341 ) ? 40 :
(counter < 32'd150000 ) ? 39 :
(counter < 32'd153846 ) ? 38 :
(counter < 32'd157894 ) ? 37 :
(counter < 32'd162162 ) ? 36 :
(counter < 32'd166666 ) ? 35 :
(counter < 32'd171428 ) ? 34 :
(counter < 32'd176470 ) ? 33 :
(counter < 32'd181818 ) ? 32 :
(counter < 32'd187500 ) ? 31 :
(counter < 32'd193548 ) ? 30 : default_bpm;
endmodule
|
// MBT 11/10/14
//
// bsg_round_robin_1_to_n
//
// this is intended to take one input and send it to
// one of several channels in round robin order.
//
// assumings a valid/ready interface
//
// we omit the data part as it is just duplication.
//
`include "bsg_defines.v"
module bsg_round_robin_1_to_n #(parameter `BSG_INV_PARAM(width_p )
,parameter num_out_p = 2)
(input clk_i
, input reset_i
// from one fifo
, input valid_i
, output ready_o
// to many
, output [num_out_p-1:0] valid_o
, input [num_out_p-1:0] ready_i
// to downstream
);
// If only one output, feed through the signals
if (num_out_p == 1)
begin: one_to_one
assign valid_o = valid_i;
assign ready_o = ready_i;
end
else
begin: one_to_n
wire [`BSG_SAFE_CLOG2(num_out_p)-1:0] ptr_r;
wire yumi_i = valid_i & ready_o;
bsg_circular_ptr #(.slots_p(num_out_p)
,.max_add_p(1)
) circular_ptr
(.clk (clk_i )
,.reset_i(reset_i)
,.add_i (yumi_i )
,.o (ptr_r )
,.n_o ()
);
// bsg_decode_with_v could potentially be used to optimize this critical path
// at the cost of area
assign valid_o = (valid_i << ptr_r);
// binary to one hot
assign ready_o = ready_i[ptr_r];
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_round_robin_1_to_n)
|
//////////////////////////////////////////////////////////////////////////////////////////////
// File : encoder.v
//-----------------------------------------------------------------------------
//**************************************************************************
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2003 Xilinx, Inc.
// All rights reserved.
//
//**************************************************************************
//
//
// Revision 1.0
//
// Modification History:
// Date Init Description
// -------- ------ ---------------------------------------------------------
// 9/15/2003 MD Initial release.
//-------------------------------------------------------------------------------
// Description:
//
//-----------------------------------------------------------------------------
// Description : The encoder takes the 64-bit XGMII formatted data from the
// fifo and convertes it to the 66-bit scheme given in section 49.2.4 of the
// IEEE P802.3ae specification.
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module encoder (clk, xgmii_txd, xgmii_txc, data_out, t_type, init, enable);
input clk;
input[63:0] xgmii_txd;
input[7:0] xgmii_txc;
output[65:0] data_out;
reg[65:0] data_out;
output [2:0] t_type;
reg [2:0] t_type;
input init;
input enable;
//---------------------------------------------------------------------------------
// Signals used to indicate what type of data is in each of the pre-xgmii data lanes.
//---------------------------------------------------------------------------------
// Lane 0
reg lane_0_data;
reg lane_0_control;
reg lane_0_idle;
reg lane_0_start;
reg lane_0_terminate;
reg lane_0_error;
reg lane_0_seq;
reg lane_0_res0;
reg lane_0_res1;
reg lane_0_res2;
reg lane_0_res3;
reg lane_0_res4;
reg lane_0_res5;
reg lane_0_seqr;
// Lane 1
reg lane_1_data;
reg lane_1_control;
reg lane_1_idle;
reg lane_1_terminate;
reg lane_1_res0;
reg lane_1_res1;
reg lane_1_res2;
reg lane_1_res3;
reg lane_1_res4;
reg lane_1_res5;
// Lane 2
reg lane_2_data;
reg lane_2_control;
reg lane_2_idle;
reg lane_2_terminate;
reg lane_2_res0;
reg lane_2_res1;
reg lane_2_res2;
reg lane_2_res3;
reg lane_2_res4;
reg lane_2_res5;
// Lane 3
reg lane_3_data;
reg lane_3_control;
reg lane_3_idle;
reg lane_3_terminate;
reg lane_3_res0;
reg lane_3_res1;
reg lane_3_res2;
reg lane_3_res3;
reg lane_3_res4;
reg lane_3_res5;
// Lane 4
reg lane_4_data;
reg lane_4_control;
reg lane_4_idle;
reg lane_4_start;
reg lane_4_terminate;
reg lane_4_seq;
reg lane_4_res0;
reg lane_4_res1;
reg lane_4_res2;
reg lane_4_res3;
reg lane_4_res4;
reg lane_4_res5;
reg lane_4_seqr;
// Lane 5
reg lane_5_data;
reg lane_5_control;
reg lane_5_idle;
reg lane_5_terminate;
reg lane_5_res0;
reg lane_5_res1;
reg lane_5_res2;
reg lane_5_res3;
reg lane_5_res4;
reg lane_5_res5;
// Lane 6
reg lane_6_data;
reg lane_6_control;
reg lane_6_idle;
reg lane_6_terminate;
reg lane_6_res0;
reg lane_6_res1;
reg lane_6_res2;
reg lane_6_res3;
reg lane_6_res4;
reg lane_6_res5;
// Lane 7
reg lane_7_data;
reg lane_7_control;
reg lane_7_idle;
reg lane_7_terminate;
reg lane_7_res0;
reg lane_7_res1;
reg lane_7_res2;
reg lane_7_res3;
reg lane_7_res4;
reg lane_7_res5;
//---------------------------------------------------------------------------------
// Internal data and control bus signals.
//---------------------------------------------------------------------------------
wire[63:0] int_txd;
wire[7:0] int_txc;
reg[63:0] reg_txd;
reg[7:0] reg_txc;
reg[63:0] reg_reg_txd;
reg[7:0] reg_reg_txc;
wire[7:0] int_txd_0;
wire[7:0] int_txd_1;
wire[7:0] int_txd_2;
wire[7:0] int_txd_3;
wire[7:0] int_txd_4;
wire[7:0] int_txd_5;
wire[7:0] int_txd_6;
wire[7:0] int_txd_7;
wire[65:0] int_data_out;
//---------------------------------------------------------------------------------
// Signals for the type field generation.
//---------------------------------------------------------------------------------
reg[7:0] type_field;
wire type_1e;
wire type_2d;
wire type_33;
wire type_66;
wire type_55;
wire type_78;
wire type_4b;
wire type_87;
wire type_99;
wire type_aa;
wire type_b4;
wire type_cc;
wire type_d2;
wire type_e1;
wire type_ff;
wire type_illegal;
wire type_data;
reg int_error;
reg[16:0] type_reg;
reg[16:0] type_reg_reg;
//---------------------------------------------------------------------------------
// Signals for the other output data fields.
//---------------------------------------------------------------------------------
reg[1:0] sync_field;
reg[55:0] data_field;
reg[6:0] lane_0_code;
reg[6:0] lane_1_code;
reg[6:0] lane_2_code;
reg[6:0] lane_3_code;
reg[6:0] lane_4_code;
reg[6:0] lane_5_code;
reg[6:0] lane_6_code;
reg[6:0] lane_7_code;
reg[3:0] o_code0;
reg[3:0] o_code4;
//---------------------------------------------------------------------------------
// Signals to tell the transmit state machine what type of data is present at
// the input.
//---------------------------------------------------------------------------------
wire t_type_c;
wire t_type_s;
wire t_type_t;
wire t_type_d;
wire t_type_e;
//---------------------------------------------------------------------------------
// A wee delay for simulation. The synthesis tool ignores this.
//---------------------------------------------------------------------------------
parameter dly = 1;
parameter [2:0] control = 3'b000;
parameter [2:0] start = 3'b001;
parameter [2:0] data = 3'b010;
parameter [2:0] terminate = 3'b011;
parameter [2:0] error = 3'b100;
//o_code <= \"0000\";
assign int_txd = xgmii_txd ;
assign int_txc = xgmii_txc ;
//-------------------------------------------------------------------------------
// Split the data into the 8 lanes.
//-------------------------------------------------------------------------------
assign int_txd_0 = int_txd[7:0] ;
assign int_txd_1 = int_txd[15:8] ;
assign int_txd_2 = int_txd[23:16] ;
assign int_txd_3 = int_txd[31:24] ;
assign int_txd_4 = int_txd[39:32] ;
assign int_txd_5 = int_txd[47:40] ;
assign int_txd_6 = int_txd[55:48] ;
assign int_txd_7 = int_txd[63:56] ;
//-------------------------------------------------------------------------------
// Register the txd and txc signals. This is to maintain the timing
// relationship between the data and the control signals that are generated
// in this design.
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // regips
if (init == 1'b1)
begin
reg_txd <= #dly {64{1'b0}} ;
reg_txc <= #dly {8{1'b0}} ;
reg_reg_txd <= #dly {64{1'b0}} ;
reg_reg_txc <= #dly {8{1'b0}} ;
end
else
begin
if (enable == 1'b1)
begin
reg_txd <= #dly int_txd ;
reg_txc <= #dly int_txc ;
reg_reg_txd <= #dly reg_txd ;
reg_reg_txc <= #dly reg_txc ;
end
end
end
//-------------------------------------------------------------------------------
// Generate the lane 0 data and control signals. These are dependent on just the
// TXC(0) input from the MAC. 0 indicates data, 1 indicates control.
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl0_dc_gen
if (init == 1'b1)
begin
lane_0_data <= #dly 1'b0 ;
lane_0_control <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
lane_0_data <= #dly ~(int_txc[0]) ;
lane_0_control <= #dly int_txc[0] ;
end
end
end
//-------------------------------------------------------------------------------
// Generate the lane 0 specific control signals. Here we decode the XGMII_TXD
// data to determine what type of control character has been transmitted.
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl0_sc_gen
if (init == 1'b1)
begin
lane_0_idle <= #dly 1'b0 ;
lane_0_start <= #dly 1'b0 ;
lane_0_terminate <= #dly 1'b0 ;
lane_0_error <= #dly 1'b0 ;
lane_0_seq <= #dly 1'b0 ;
lane_0_res0 <= #dly 1'b0 ;
lane_0_res1 <= #dly 1'b0 ;
lane_0_res2 <= #dly 1'b0 ;
lane_0_res3 <= #dly 1'b0 ;
lane_0_res4 <= #dly 1'b0 ;
lane_0_res5 <= #dly 1'b0 ;
lane_0_seqr <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
// Idle = 0x07
lane_0_idle <= #dly ~(int_txd_0[7]) & ~(int_txd_0[6]) & ~(int_txd_0[5]) & ~(int_txd_0[4]) & ~(int_txd_0[3]) & int_txd_0[2] & int_txd_0[1] & int_txd_0[0] & int_txc[0] ;
// Start = 0xFB
lane_0_start <= #dly int_txd_0[7] & int_txd_0[6] & int_txd_0[5] & int_txd_0[4] & int_txd_0[3] & ~(int_txd_0[2]) & int_txd_0[1] & int_txd_0[0] & int_txc[0] ;
// Terminate = 0xFD
lane_0_terminate <= #dly int_txd_0[7] & int_txd_0[6] & int_txd_0[5] & int_txd_0[4] & int_txd_0[3] & int_txd_0[2] & ~(int_txd_0[1]) & int_txd_0[0] & int_txc[0] ;
// Error = 0xFE
lane_0_error <= #dly int_txd_0[7] & int_txd_0[6] & int_txd_0[5] & int_txd_0[4] & int_txd_0[3] & int_txd_0[2] & int_txd_0[1] & ~(int_txd_0[0]) & int_txc[0] ;
// Sequence = 0x9C
lane_0_seq <= #dly int_txd_0[7] & ~(int_txd_0[6]) & ~(int_txd_0[5]) & int_txd_0[4] & int_txd_0[3] & int_txd_0[2] & ~(int_txd_0[1]) & ~(int_txd_0[0]) & int_txc[0] ;
// Reserved 0
lane_0_res0 <= #dly ~(int_txd_0[7]) & ~(int_txd_0[6]) & ~(int_txd_0[5]) & int_txd_0[4] & int_txd_0[3] & int_txd_0[2] & ~(int_txd_0[1]) & ~(int_txd_0[0]) & int_txc[0] ;
// Reserved 1
lane_0_res1 <= #dly ~(int_txd_0[7]) & ~(int_txd_0[6]) & int_txd_0[5] & int_txd_0[4] & int_txd_0[3] & int_txd_0[2] & ~(int_txd_0[1]) & ~(int_txd_0[0]) & int_txc[0] ;
// Reserved 2
lane_0_res2 <= #dly ~(int_txd_0[7]) & int_txd_0[6] & int_txd_0[5] & int_txd_0[4] & int_txd_0[3] & int_txd_0[2] & ~(int_txd_0[1]) & ~(int_txd_0[0]) & int_txc[0] ;
// Reserved 3
lane_0_res3 <= #dly int_txd_0[7] & ~(int_txd_0[6]) & int_txd_0[5] & int_txd_0[4] & int_txd_0[3] & int_txd_0[2] & ~(int_txd_0[1]) & ~(int_txd_0[0]) & int_txc[0] ;
// Reserved 4
lane_0_res4 <= #dly int_txd_0[7] & int_txd_0[6] & ~(int_txd_0[5]) & int_txd_0[4] & int_txd_0[3] & int_txd_0[2] & ~(int_txd_0[1]) & ~(int_txd_0[0]) & int_txc[0] ;
// Reserved 5
lane_0_res5 <= #dly int_txd_0[7] & int_txd_0[6] & int_txd_0[5] & int_txd_0[4] & ~(int_txd_0[3]) & int_txd_0[2] & int_txd_0[1] & int_txd_0[0] & int_txc[0] ;
// Reserved Ordered Set
lane_0_seqr <= #dly ~(int_txd_0[7]) & int_txd_0[6] & ~(int_txd_0[5]) & ~(int_txd_0[4]) & int_txd_0[3] & int_txd_0[2] & ~(int_txd_0[1]) & ~(int_txd_0[0]) & int_txc[0] ;
end
end
end
//-------------------------------------------------------------------------------
// Do the same as above for all the other data lanes.
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
// Lane 1
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl1_dc_gen
if (init == 1'b1)
begin
lane_1_data <= #dly 1'b0 ;
lane_1_control <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
lane_1_data <= #dly ~(int_txc[1]) ;
lane_1_control <= #dly int_txc[1] ;
end
end
end
//-------------------------------------------------------------------------------
// Generate the lane 1 specific control signals. These are the same as above (lane 0)
// but without the start or sequence detection as these can only occur in lanes
// 0 or 4. In addition I have designed the MAC transmitter so that an error
// character can only occur in lane 0 and so there is no error detection on this lane.
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin// dl1_sc_gen
if (init == 1'b1)
begin
lane_1_idle <= #dly 1'b0 ;
lane_1_terminate <= #dly 1'b0 ;
lane_1_res0 <= #dly 1'b0 ;
lane_1_res1 <= #dly 1'b0 ;
lane_1_res2 <= #dly 1'b0 ;
lane_1_res3 <= #dly 1'b0 ;
lane_1_res4 <= #dly 1'b0 ;
lane_1_res5 <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
// Idle = 0x07
lane_1_idle <= #dly ~(int_txd_1[7]) & ~(int_txd_1[6]) & ~(int_txd_1[5]) & ~(int_txd_1[4]) & ~(int_txd_1[3]) & int_txd_1[2] & int_txd_1[1] & int_txd_1[0] & int_txc[1] ;
// Terminate = 0xFD
lane_1_terminate <= #dly int_txd_1[7] & int_txd_1[6] & int_txd_1[5] & int_txd_1[4] & int_txd_1[3] & int_txd_1[2] & ~(int_txd_1[1]) & int_txd_1[0] & int_txc[1] ;
// Reserved 0
lane_1_res0 <= #dly ~(int_txd_1[7]) & ~(int_txd_1[6]) & ~(int_txd_1[5]) & int_txd_1[4] & int_txd_1[3] & int_txd_1[2] & ~(int_txd_1[1]) & ~(int_txd_1[0]) & int_txc[1] ;
// Reserved 1
lane_1_res1 <= #dly ~(int_txd_0[7]) & ~(int_txd_1[6]) & int_txd_1[5] & int_txd_1[4] & int_txd_1[3] & int_txd_1[2] & ~(int_txd_1[1]) & ~(int_txd_1[0]) & int_txc[1] ;
// Reserved 2
lane_1_res2 <= #dly ~(int_txd_1[7]) & int_txd_1[6] & int_txd_1[5] & int_txd_1[4] & int_txd_1[3] & int_txd_1[2] & ~(int_txd_1[1]) & ~(int_txd_1[0]) & int_txc[1] ;
// Reserved 3
lane_1_res3 <= #dly int_txd_1[7] & ~(int_txd_1[6]) & int_txd_1[5] & int_txd_1[4] & int_txd_1[3] & int_txd_1[2] & ~(int_txd_1[1]) & ~(int_txd_1[0]) & int_txc[1] ;
// Reserved 4
lane_1_res4 <= #dly int_txd_1[7] & int_txd_1[6] & ~(int_txd_1[5]) & int_txd_1[4] & int_txd_1[3] & int_txd_1[2] & ~(int_txd_1[1]) & ~(int_txd_1[0]) & int_txc[1] ;
// Reserved 5
lane_1_res5 <= #dly int_txd_1[7] & int_txd_1[6] & int_txd_1[5] & int_txd_1[4] & ~(int_txd_1[3]) & int_txd_1[2] & int_txd_1[1] & int_txd_1[0] & int_txc[1] ;
end
end
end
//-------------------------------------------------------------------------------
// Lane 2
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl2_dc_gen
if (init == 1'b1)
begin
lane_2_data <= #dly 1'b0 ;
lane_2_control <= #dly 1'b0 ;
lane_2_idle <= #dly 1'b0 ;
lane_2_terminate <= #dly 1'b0 ;
lane_2_res0 <= #dly 1'b0 ;
lane_2_res1 <= #dly 1'b0 ;
lane_2_res2 <= #dly 1'b0 ;
lane_2_res3 <= #dly 1'b0 ;
lane_2_res4 <= #dly 1'b0 ;
lane_2_res5 <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
lane_2_data <= #dly ~(int_txc[2]) ;
lane_2_control <= #dly int_txc[2] ;
// Idle = 0x07
lane_2_idle <= #dly ~(int_txd_2[7]) & ~(int_txd_2[6]) & ~(int_txd_2[5]) & ~(int_txd_2[4]) & ~(int_txd_2[3]) & int_txd_2[2] & int_txd_2[1] & int_txd_2[0] & int_txc[2] ;
// Terminate = 0xFD
lane_2_terminate <= #dly int_txd_2[7] & int_txd_2[6] & int_txd_2[5] & int_txd_2[4] & int_txd_2[3] & int_txd_2[2] & ~(int_txd_2[1]) & int_txd_2[0] & int_txc[2] ;
// Reserved 0
lane_2_res0 <= #dly ~(int_txd_2[7]) & ~(int_txd_2[6]) & ~(int_txd_2[5]) & int_txd_2[4] & int_txd_2[3] & int_txd_2[2] & ~(int_txd_2[1]) & ~(int_txd_2[0]) & int_txc[2] ;
// Reserved 1
lane_2_res1 <= #dly ~(int_txd_2[7]) & ~(int_txd_2[6]) & int_txd_2[5] & int_txd_2[4] & int_txd_2[3] & int_txd_2[2] & ~(int_txd_2[1]) & ~(int_txd_2[0]) & int_txc[2] ;
// Reserved 2
lane_2_res2 <= #dly ~(int_txd_2[7]) & int_txd_2[6] & int_txd_2[5] & int_txd_2[4] & int_txd_2[3] & int_txd_2[2] & ~(int_txd_2[1]) & ~(int_txd_2[0]) & int_txc[2] ;
// Reserved 3
lane_2_res3 <= #dly int_txd_2[7] & ~(int_txd_2[6]) & int_txd_2[5] & int_txd_2[4] & int_txd_2[3] & int_txd_2[2] & ~(int_txd_2[1]) & ~(int_txd_2[0]) & int_txc[2] ;
// Reserved 4
lane_2_res4 <= #dly int_txd_2[7] & int_txd_2[6] & ~(int_txd_2[5]) & int_txd_2[4] & int_txd_2[3] & int_txd_2[2] & ~(int_txd_2[1]) & ~(int_txd_2[0]) & int_txc[2] ;
// Reserved 5
lane_2_res5 <= #dly int_txd_2[7] & int_txd_2[6] & int_txd_2[5] & int_txd_2[4] & ~(int_txd_2[3]) & int_txd_2[2] & int_txd_2[1] & int_txd_2[0] & int_txc[2] ;
end
end
end
//-------------------------------------------------------------------------------
// Lane 3
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl3_dc_gen
if (init == 1'b1)
begin
lane_3_data <= #dly 1'b0 ;
lane_3_control <= #dly 1'b0 ;
lane_3_idle <= #dly 1'b0 ;
lane_3_terminate <= #dly 1'b0 ;
lane_3_res0 <= #dly 1'b0 ;
lane_3_res1 <= #dly 1'b0 ;
lane_3_res2 <= #dly 1'b0 ;
lane_3_res3 <= #dly 1'b0 ;
lane_3_res4 <= #dly 1'b0 ;
lane_3_res5 <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
lane_3_data <= #dly ~(int_txc[3]) ;
lane_3_control <= #dly int_txc[3] ;
// Idle = 0x07
lane_3_idle <= #dly ~(int_txd_3[7]) & ~(int_txd_3[6]) & ~(int_txd_3[5]) & ~(int_txd_3[4]) & ~(int_txd_3[3]) & int_txd_3[2] & int_txd_3[1] & int_txd_3[0] & int_txc[3] ;
// Terminate = 0xFD
lane_3_terminate <= #dly int_txd_3[7] & int_txd_3[6] & int_txd_3[5] & int_txd_3[4] & int_txd_3[3] & int_txd_3[2] & ~(int_txd_3[1]) & int_txd_3[0] & int_txc[3] ;
// Reserved 0
lane_3_res0 <= #dly ~(int_txd_3[7]) & ~(int_txd_3[6]) & ~(int_txd_3[5]) & int_txd_3[4] & int_txd_3[3] & int_txd_3[2] & ~(int_txd_3[1]) & ~(int_txd_3[0]) & int_txc[3] ;
// Reserved 1
lane_3_res1 <= #dly ~(int_txd_3[7]) & ~(int_txd_3[6]) & int_txd_3[5] & int_txd_3[4] & int_txd_3[3] & int_txd_3[2] & ~(int_txd_3[1]) & ~(int_txd_3[0]) & int_txc[3] ;
// Reserved 2
lane_3_res2 <= #dly ~(int_txd_3[7]) & int_txd_3[6] & int_txd_3[5] & int_txd_3[4] & int_txd_3[3] & int_txd_3[2] & ~(int_txd_3[1]) & ~(int_txd_3[0]) & int_txc[3] ;
// Reserved 3
lane_3_res3 <= #dly int_txd_3[7] & ~(int_txd_3[6]) & int_txd_3[5] & int_txd_3[4] & int_txd_3[3] & int_txd_3[2] & ~(int_txd_3[1]) & ~(int_txd_3[0]) & int_txc[3] ;
// Reserved 4
lane_3_res4 <= #dly int_txd_3[7] & int_txd_3[6] & ~(int_txd_3[5]) & int_txd_3[4] & int_txd_3[3] & int_txd_3[2] & ~(int_txd_3[1]) & ~(int_txd_3[0]) & int_txc[3] ;
// Reserved 5
lane_3_res5 <= #dly int_txd_3[7] & int_txd_3[6] & int_txd_3[5] & int_txd_3[4] & ~(int_txd_3[3]) & int_txd_3[2] & int_txd_3[1] & int_txd_3[0] & int_txc[3] ;
end
end
end
//-------------------------------------------------------------------------------
// Lane 4
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl4_dc_gen
if (init == 1'b1)
begin
lane_4_data <= #dly 1'b0 ;
lane_4_control <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
lane_4_data <= #dly ~(int_txc[4]) ;
lane_4_control <= #dly int_txc[4] ;
end
end
end
//-------------------------------------------------------------------------------
// Generate the lane 4 specific control signals. Here we decode the XGMII_TXD
// data to determine what type of control character has been transmitted. The
// start and sequence characters can appear on this lane.
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl4_sc_gen
if (init == 1'b1)
begin
lane_4_idle <= #dly 1'b0 ;
lane_4_start <= #dly 1'b0 ;
lane_4_terminate <= #dly 1'b0 ;
lane_4_seq <= #dly 1'b0 ;
lane_4_res0 <= #dly 1'b0 ;
lane_4_res1 <= #dly 1'b0 ;
lane_4_res2 <= #dly 1'b0 ;
lane_4_res3 <= #dly 1'b0 ;
lane_4_res4 <= #dly 1'b0 ;
lane_4_res5 <= #dly 1'b0 ;
lane_4_seqr <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
// Idle = 0x07
lane_4_idle <= #dly ~(int_txd_4[7]) & ~(int_txd_4[6]) & ~(int_txd_4[5]) & ~(int_txd_4[4]) & ~(int_txd_4[3]) & int_txd_4[2] & int_txd_4[1] & int_txd_4[0] & int_txc[4] ;
// Start = 0xFB
lane_4_start <= #dly int_txd_4[7] & int_txd_4[6] & int_txd_4[5] & int_txd_4[4] & int_txd_4[3] & ~(int_txd_4[2]) & int_txd_4[1] & int_txd_4[0] & int_txc[4] ;
// Terminate = 0xFD
lane_4_terminate <= #dly int_txd_4[7] & int_txd_4[6] & int_txd_4[5] & int_txd_4[4] & int_txd_4[3] & int_txd_4[2] & ~(int_txd_4[1]) & int_txd_4[0] & int_txc[4] ;
// Sequence = 0x9C
lane_4_seq <= #dly int_txd_4[7] & ~(int_txd_4[6]) & ~(int_txd_4[5]) & int_txd_4[4] & int_txd_4[3] & int_txd_4[2] & ~(int_txd_4[1]) & ~(int_txd_4[0]) & int_txc[4] ;
// Reserved 0
lane_4_res0 <= #dly ~(int_txd_4[7]) & ~(int_txd_4[6]) & ~(int_txd_4[5]) & int_txd_4[4] & int_txd_4[3] & int_txd_4[2] & ~(int_txd_4[1]) & ~(int_txd_4[0]) & int_txc[4] ;
// Reserved 1
lane_4_res1 <= #dly ~(int_txd_4[7]) & ~(int_txd_4[6]) & int_txd_4[5] & int_txd_4[4] & int_txd_4[3] & int_txd_4[2] & ~(int_txd_4[1]) & ~(int_txd_4[0]) & int_txc[4] ;
// Reserved 2
lane_4_res2 <= #dly ~(int_txd_4[7]) & int_txd_4[6] & int_txd_4[5] & int_txd_4[4] & int_txd_4[3] & int_txd_4[2] & ~(int_txd_4[1]) & ~(int_txd_4[0]) & int_txc[4] ;
// Reserved 3
lane_4_res3 <= #dly int_txd_4[7] & ~(int_txd_4[6]) & int_txd_4[5] & int_txd_4[4] & int_txd_4[3] & int_txd_4[2] & ~(int_txd_4[1]) & ~(int_txd_4[0]) & int_txc[4] ;
// Reserved 4
lane_4_res4 <= #dly int_txd_4[7] & int_txd_4[6] & ~(int_txd_4[5]) & int_txd_4[4] & int_txd_4[3] & int_txd_4[2] & ~(int_txd_4[1]) & ~(int_txd_4[0]) & int_txc[4] ;
// Reserved 5
lane_4_res5 <= #dly int_txd_4[7] & int_txd_4[6] & int_txd_4[5] & int_txd_4[4] & ~(int_txd_4[3]) & int_txd_4[2] & int_txd_4[1] & int_txd_4[0] & int_txc[4] ;
// Reserved Ordered Set
lane_4_seqr <= #dly ~(int_txd_4[7]) & int_txd_4[6] & ~(int_txd_4[5]) & ~(int_txd_4[4]) & int_txd_4[3] & int_txd_4[2] & ~(int_txd_4[1]) & ~(int_txd_4[0]) & int_txc[4] ;
end
end
end
//-------------------------------------------------------------------------------
// Lane 5
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl5_dc_gen
if (init == 1'b1)
begin
lane_5_data <= #dly 1'b0 ;
lane_5_control <= #dly 1'b0 ;
lane_5_idle <= #dly 1'b0 ;
lane_5_terminate <= #dly 1'b0 ;
lane_5_res0 <= #dly 1'b0 ;
lane_5_res1 <= #dly 1'b0 ;
lane_5_res2 <= #dly 1'b0 ;
lane_5_res3 <= #dly 1'b0 ;
lane_5_res4 <= #dly 1'b0 ;
lane_5_res5 <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
lane_5_data <= #dly ~(int_txc[5]) ;
lane_5_control <= #dly int_txc[5] ;
// Idle = 0x07
lane_5_idle <= #dly ~(int_txd_5[7]) & ~(int_txd_5[6]) & ~(int_txd_5[5]) & ~(int_txd_5[4]) & ~(int_txd_5[3]) & int_txd_5[2] & int_txd_5[1] & int_txd_5[0] & int_txc[5] ;
// Terminate = 0xFD
lane_5_terminate <= #dly int_txd_5[7] & int_txd_5[6] & int_txd_5[5] & int_txd_5[4] & int_txd_5[3] & int_txd_5[2] & ~(int_txd_5[1]) & int_txd_5[0] & int_txc[5] ;
// Reserved 0
lane_5_res0 <= #dly ~(int_txd_5[7]) & ~(int_txd_5[6]) & ~(int_txd_5[5]) & int_txd_5[4] & int_txd_5[3] & int_txd_5[2] & ~(int_txd_5[1]) & ~(int_txd_5[0]) & int_txc[5] ;
// Reserved 1
lane_5_res1 <= #dly ~(int_txd_5[7]) & ~(int_txd_5[6]) & int_txd_5[5] & int_txd_5[4] & int_txd_5[3] & int_txd_5[2] & ~(int_txd_5[1]) & ~(int_txd_5[0]) & int_txc[5] ;
// Reserved 2
lane_5_res2 <= #dly ~(int_txd_5[7]) & int_txd_5[6] & int_txd_5[5] & int_txd_5[4] & int_txd_5[3] & int_txd_5[2] & ~(int_txd_5[1]) & ~(int_txd_5[0]) & int_txc[5] ;
// Reserved 3
lane_5_res3 <= #dly int_txd_5[7] & ~(int_txd_5[6]) & int_txd_5[5] & int_txd_5[4] & int_txd_5[3] & int_txd_5[2] & ~(int_txd_5[1]) & ~(int_txd_5[0]) & int_txc[5] ;
// Reserved 4
lane_5_res4 <= #dly int_txd_5[7] & int_txd_5[6] & ~(int_txd_5[5]) & int_txd_5[4] & int_txd_5[3] & int_txd_5[2] & ~(int_txd_5[1]) & ~(int_txd_5[0]) & int_txc[5] ;
// Reserved 5
lane_5_res5 <= #dly int_txd_5[7] & int_txd_5[6] & int_txd_5[5] & int_txd_5[4] & ~(int_txd_5[3]) & int_txd_5[2] & int_txd_5[1] & int_txd_5[0] & int_txc[5] ;
end
end
end
//-------------------------------------------------------------------------------
// Lane 6
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl6_dc_gen
if (init == 1'b1)
begin
lane_6_data <= #dly 1'b0 ;
lane_6_control <= #dly 1'b0 ;
lane_6_idle <= #dly 1'b0 ;
lane_6_terminate <= #dly 1'b0 ;
lane_6_res0 <= #dly 1'b0 ;
lane_6_res1 <= #dly 1'b0 ;
lane_6_res2 <= #dly 1'b0 ;
lane_6_res3 <= #dly 1'b0 ;
lane_6_res4 <= #dly 1'b0 ;
lane_6_res5 <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
lane_6_data <= #dly ~(int_txc[6]) ;
lane_6_control <= #dly int_txc[6] ;
// Idle = 0x07
lane_6_idle <= #dly ~(int_txd_6[7]) & ~(int_txd_6[6]) & ~(int_txd_6[5]) & ~(int_txd_6[4]) & ~(int_txd_6[3]) & int_txd_6[2] & int_txd_6[1] & int_txd_6[0] & int_txc[6] ;
// Terminate = 0xFD
lane_6_terminate <= #dly int_txd_6[7] & int_txd_6[6] & int_txd_6[5] & int_txd_6[4] & int_txd_6[3] & int_txd_6[2] & ~(int_txd_6[1]) & int_txd_6[0] & int_txc[6] ;
// Reserved 0
lane_6_res0 <= #dly ~(int_txd_6[7]) & ~(int_txd_6[6]) & ~(int_txd_6[5]) & int_txd_6[4] & int_txd_6[3] & int_txd_6[2] & ~(int_txd_6[1]) & ~(int_txd_6[0]) & int_txc[6] ;
// Reserved 1
lane_6_res1 <= #dly ~(int_txd_6[7]) & ~(int_txd_6[6]) & int_txd_6[5] & int_txd_6[4] & int_txd_6[3] & int_txd_6[2] & ~(int_txd_6[1]) & ~(int_txd_6[0]) & int_txc[6] ;
// Reserved 2
lane_6_res2 <= #dly ~(int_txd_6[7]) & int_txd_6[6] & int_txd_6[5] & int_txd_6[4] & int_txd_6[3] & int_txd_6[2] & ~(int_txd_6[1]) & ~(int_txd_6[0]) & int_txc[6] ;
// Reserved 3
lane_6_res3 <= #dly int_txd_6[7] & ~(int_txd_6[6]) & int_txd_6[5] & int_txd_6[4] & int_txd_6[3] & int_txd_6[2] & ~(int_txd_6[1]) & ~(int_txd_6[0]) & int_txc[6] ;
// Reserved 4
lane_6_res4 <= #dly int_txd_6[7] & int_txd_6[6] & ~(int_txd_6[5]) & int_txd_6[4] & int_txd_6[3] & int_txd_6[2] & ~(int_txd_6[1]) & ~(int_txd_6[0]) & int_txc[6] ;
// Reserved 5
lane_6_res5 <= #dly int_txd_6[7] & int_txd_6[6] & int_txd_6[5] & int_txd_6[4] & ~(int_txd_6[3]) & int_txd_6[2] & int_txd_6[1] & int_txd_6[0] & int_txc[6] ;
end
end
end
//-------------------------------------------------------------------------------
// Lane 7
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // dl7_dc_gen
if (init == 1'b1)
begin
lane_7_data <= #dly 1'b0 ;
lane_7_control <= #dly 1'b0 ;
lane_7_idle <= #dly 1'b0 ;
lane_7_terminate <= #dly 1'b0 ;
lane_7_res0 <= #dly 1'b0 ;
lane_7_res1 <= #dly 1'b0 ;
lane_7_res2 <= #dly 1'b0 ;
lane_7_res3 <= #dly 1'b0 ;
lane_7_res4 <= #dly 1'b0 ;
lane_7_res5 <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
lane_7_data <= #dly ~(int_txc[7]) ;
lane_7_control <= #dly int_txc[7] ;
// Idle = 0x07
lane_7_idle <= #dly ~(int_txd_7[7]) & ~(int_txd_7[6]) & ~(int_txd_7[5]) & ~(int_txd_7[4]) & ~(int_txd_7[3]) & int_txd_7[2] & int_txd_7[1] & int_txd_7[0] & int_txc[7] ;
// Terminate = 0xFD
lane_7_terminate <= #dly int_txd_7[7] & int_txd_7[6] & int_txd_7[5] & int_txd_7[4] & int_txd_7[3] & int_txd_7[2] & ~(int_txd_7[1]) & int_txd_7[0] & int_txc[7] ;
// Reserved 0
lane_7_res0 <= #dly ~(int_txd_7[7]) & ~(int_txd_7[6]) & ~(int_txd_7[5]) & int_txd_7[4] & int_txd_7[3] & int_txd_7[2] & ~(int_txd_7[1]) & ~(int_txd_7[0]) & int_txc[7] ;
// Reserved 1
lane_7_res1 <= #dly ~(int_txd_7[7]) & ~(int_txd_7[6]) & int_txd_7[5] & int_txd_7[4] & int_txd_7[3] & int_txd_7[2] & ~(int_txd_7[1]) & ~(int_txd_7[0]) & int_txc[7] ;
// Reserved 2
lane_7_res2 <= #dly ~(int_txd_7[7]) & int_txd_7[6] & int_txd_7[5] & int_txd_7[4] & int_txd_7[3] & int_txd_7[2] & ~(int_txd_7[1]) & ~(int_txd_7[0]) & int_txc[7] ;
// Reserved 3
lane_7_res3 <= #dly int_txd_7[7] & ~(int_txd_7[6]) & int_txd_7[5] & int_txd_7[4] & int_txd_7[3] & int_txd_7[2] & ~(int_txd_7[1]) & ~(int_txd_7[0]) & int_txc[7] ;
// Reserved 4
lane_7_res4 <= #dly int_txd_7[7] & int_txd_7[6] & ~(int_txd_7[5]) & int_txd_7[4] & int_txd_7[3] & int_txd_7[2] & ~(int_txd_7[1]) & ~(int_txd_7[0]) & int_txc[7] ;
// Reserved 5
lane_7_res5 <= #dly int_txd_7[7] & int_txd_7[6] & int_txd_7[5] & int_txd_7[4] & ~(int_txd_7[3]) & int_txd_7[2] & int_txd_7[1] & int_txd_7[0] & int_txc[7] ;
end
end
end
//-------------------------------------------------------------------------------
// Decode the TXC input to decide on the value of the type field that is appended
// to the data stream. This is only present for double words that contain
// one or more control characters.
//-------------------------------------------------------------------------------
// All the data is control characters (usually idles) :-
assign type_1e = lane_0_control & ~(lane_0_terminate) & ~(lane_0_error) & lane_1_control & lane_2_control & lane_3_control & lane_4_control & lane_5_control & lane_6_control & lane_7_control ;
// The input contains control codes upto lane 3 but an ordered set from lane 4 onwards :-
assign type_2d = lane_0_control & lane_1_control & lane_2_control & lane_3_control & lane_4_seq & lane_5_data & lane_6_data & lane_7_data ;
// The input contains a start of packet in lane 4 :-
assign type_33 = lane_0_control & lane_1_control & lane_2_control & lane_3_control & lane_4_start & lane_5_data & lane_6_data & lane_7_data ;
// The input contains an ordered set in lanes 0 to 3 and the start of a packet
// in lanes 4 to 7 :-
assign type_66 = lane_0_seq & lane_1_data & lane_2_data & lane_3_data & lane_4_start & lane_5_data & lane_6_data & lane_7_data ;
// The input contains two ordered sets, one starting in lane 0 and the other in lane 4 :-
assign type_55 = lane_0_seq & lane_1_data & lane_2_data & lane_3_data & lane_4_seq & lane_5_data & lane_6_data & lane_7_data ;
// The input contains a start of packet in lane 0 :-
assign type_78 = lane_0_start & lane_1_data & lane_2_data & lane_3_data & lane_4_data & lane_5_data & lane_6_data & lane_7_data ;
// The input contains an ordered set starting in lane 0 and control characters
// in lanes 4 to 7 :-
assign type_4b = lane_0_seq & lane_1_data & lane_2_data & lane_3_data & lane_4_control & lane_5_control & lane_6_control & lane_7_control ;
// The following types are used to code inputs that contain the end of the packet.
// The end of packet delimiter (terminate) can occur in any lane. There is a
// type field associated with each position.
//
// Terminate in lane 0 :-
assign type_87 = lane_0_terminate & lane_1_control & lane_2_control & lane_3_control & lane_4_control & lane_5_control & lane_6_control & lane_7_control ;
// Terminate in lane 1 :-
assign type_99 = lane_0_data & lane_1_terminate & lane_2_control & lane_3_control & lane_4_control & lane_5_control & lane_6_control & lane_7_control ;
// Terminate in lane 2 :-
assign type_aa = lane_0_data & lane_1_data & lane_2_terminate & lane_3_control & lane_4_control & lane_5_control & lane_6_control & lane_7_control ;
// Terminate in lane 3 :-
assign type_b4 = lane_0_data & lane_1_data & lane_2_data & lane_3_terminate & lane_4_control & lane_5_control & lane_6_control & lane_7_control ;
// Terminate in lane 4 :-
assign type_cc = lane_0_data & lane_1_data & lane_2_data & lane_3_data & lane_4_terminate & lane_5_control & lane_6_control & lane_7_control ;
// Terminate in lane 5 :-
assign type_d2 = lane_0_data & lane_1_data & lane_2_data & lane_3_data & lane_4_data & lane_5_terminate & lane_6_control & lane_7_control ;
// Terminate in lane 6 :-
assign type_e1 = lane_0_data & lane_1_data & lane_2_data & lane_3_data & lane_4_data & lane_5_data & lane_6_terminate & lane_7_control ;
// Terminate in lane 7 :-
assign type_ff = lane_0_data & lane_1_data & lane_2_data & lane_3_data & lane_4_data & lane_5_data & lane_6_data & lane_7_terminate ;
// None of the above scenarios means that the data is in an illegal format.
assign type_illegal = lane_0_control | lane_1_control | lane_2_control | lane_3_control | lane_4_control | lane_5_control | lane_6_control | lane_7_control ;
assign type_data = lane_0_data & lane_1_data & lane_2_data & lane_3_data & lane_4_data & lane_5_data & lane_6_data & lane_7_data ;
//-------------------------------------------------------------------------------
// Translate these signals to give the actual type field output.
// Prior to this the type signals above are registered as the delay through the
// above equations could be considerable.
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // reg_type
if (init == 1'b1)
begin
type_reg <= #dly {17{1'b0}} ;
end
else
begin
if (enable == 1'b1)
begin
type_reg <= {type_data, type_illegal, type_ff, type_e1, type_d2, type_cc, type_b4, type_aa, type_99, type_87, type_4b, type_78, type_55, type_66, type_33, type_2d, type_1e} ;
end
end
end
//-------------------------------------------------------------------------------
// Work out the ocode that is sent
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // ocode0_gen
if (init == 1'b1)
begin
o_code0 <= #dly {4{1'b0}} ;
end
else
begin
if (lane_0_seqr == 1'b1)
begin
o_code0 <= #dly 4'b1111 ;
end
else
begin
o_code0 <= #dly 4'b0000 ;
end
end
end
always @(posedge init or posedge clk)
begin // ocode4_gen
if (init == 1'b1)
begin
o_code4 <= #dly {4{1'b0}} ;
end
else
begin
if (lane_4_seqr == 1'b1)
begin
o_code4 <= #dly 4'b1111 ;
end
else
begin
o_code4 <= #dly 4'b0000 ;
end
end
end
always @(posedge init or posedge clk)
begin // type_field_gen
if (init == 1'b1)
begin
type_field <= #dly {8{1'b0}} ;
end
else
begin
if (enable == 1'b1)
begin
if ((type_reg[0]) == 1'b1)
begin
type_field <= #dly 8'b00011110 ;
end
else if ((type_reg[1]) == 1'b1)
begin
type_field <= #dly 8'b00101101 ;
end
else if ((type_reg[2]) == 1'b1)
begin
type_field <= #dly 8'b00110011 ;
end
else if ((type_reg[3]) == 1'b1)
begin
type_field <= #dly 8'b01100110 ;
end
else if ((type_reg[4]) == 1'b1)
begin
type_field <= #dly 8'b01010101 ;
end
else if ((type_reg[5]) == 1'b1)
begin
type_field <= #dly 8'b01111000 ;
end
else if ((type_reg[6]) == 1'b1)
begin
type_field <= #dly 8'b01001011 ;
end
else if ((type_reg[7]) == 1'b1)
begin
type_field <= #dly 8'b10000111 ;
end
else if ((type_reg[8]) == 1'b1)
begin
type_field <= #dly 8'b10011001 ;
end
else if ((type_reg[9]) == 1'b1)
begin
type_field <= #dly 8'b10101010 ;
end
else if ((type_reg[10]) == 1'b1)
begin
type_field <= #dly 8'b10110100 ;
end
else if ((type_reg[11]) == 1'b1)
begin
type_field <= #dly 8'b11001100 ;
end
else if ((type_reg[12]) == 1'b1)
begin
type_field <= #dly 8'b11010010 ;
end
else if ((type_reg[13]) == 1'b1)
begin
type_field <= #dly 8'b11100001 ;
end
else if ((type_reg[14]) == 1'b1)
begin
type_field <= #dly 8'b11111111 ;
end
else if ((type_reg[15]) == 1'b1)
begin
type_field <= #dly 8'b00011110 ;
end
else
begin
// If the input doesn\'t contain a control character then the type field
// is set to be the first data byte.
type_field <= #dly reg_reg_txd[7:0] ;
end
end
end
end
//-------------------------------------------------------------------------------
// Now figure out what the rest of the data output should be set to. This is
// given in Figure 49-7 in the spec.
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
// Firstly the sync field. This is 01 for a data double and 10 for a double
// containing a control character.
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // sync_field_gen
if (init == 1'b1)
begin
sync_field <= #dly 2'b10 ;
end
else
begin
if (enable == 1'b1)
begin
if (type_reg == 17'b10000000000000000)
begin
sync_field <= #dly 2'b10 ;
end
else
begin
sync_field <= #dly 2'b01 ;
end
end
end
end
//-------------------------------------------------------------------------------
// The remaining 7 bytes of the data output
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
// The idle and error control characters are mapped from their 8-bit xgmii
// representation into a 7-bit output representation. Idle (0x07) maps to 0x00
// and error (0xFE) maps to 0x1e. The other control characters are encoded
// by the type field.
//-------------------------------------------------------------------------------
// Lane 0
always @(posedge clk)
begin // ctrl_code_gen_0
if (enable == 1'b1)
begin
if (init == 1'b1 | lane_0_idle == 1'b1)
begin
lane_0_code <= #dly {7{1'b0}} ;
end
else if (lane_0_res0 == 1'b1)
begin
lane_0_code <= #dly 7'b0101101 ;
end
else if (lane_0_res1 == 1'b1)
begin
lane_0_code <= #dly 7'b0110011 ;
end
else if (lane_0_res2 == 1'b1)
begin
lane_0_code <= #dly 7'b1001011 ;
end
else if (lane_0_res3 == 1'b1)
begin
lane_0_code <= #dly 7'b1010101 ;
end
else if (lane_0_res4 == 1'b1)
begin
lane_0_code <= #dly 7'b1100110 ;
end
else if (lane_0_res5 == 1'b1)
begin
lane_0_code <= #dly 7'b1111000 ;
end
else
begin
lane_0_code <= #dly 7'b0011110 ;
end
//lane_0_code <= \"1111000\" after dly;
end
end
// Lane 1
always @(posedge clk)
begin // ctrl_code_gen_1
if (enable == 1'b1)
begin
if (init == 1'b1 | lane_1_idle == 1'b1)
begin
lane_1_code <= #dly {7{1'b0}} ;
end
else if (lane_1_res0 == 1'b1)
begin
lane_1_code <= #dly 7'b0101101 ;
end
else if (lane_1_res1 == 1'b1)
begin
lane_1_code <= #dly 7'b0110011 ;
end
else if (lane_1_res2 == 1'b1)
begin
lane_1_code <= #dly 7'b1001011 ;
end
else if (lane_1_res3 == 1'b1)
begin
lane_1_code <= #dly 7'b1010101 ;
end
else if (lane_1_res4 == 1'b1)
begin
lane_1_code <= #dly 7'b1100110 ;
end
else if (lane_1_res5 == 1'b1)
begin
lane_1_code <= #dly 7'b1111000 ;
end
else
begin
lane_1_code <= #dly 7'b0011110 ;
end
//lane_1_code <= \"1111000\" after dly;
end
end
// Lane 2
always @(posedge clk)
begin // ctrl_code_gen_2
if (enable == 1'b1)
begin
if (init == 1'b1 | lane_2_idle == 1'b1)
begin
lane_2_code <= #dly {7{1'b0}} ;
end
else if (lane_2_res0 == 1'b1)
begin
lane_2_code <= #dly 7'b0101101 ;
end
else if (lane_2_res1 == 1'b1)
begin
lane_2_code <= #dly 7'b0110011 ;
end
else if (lane_2_res2 == 1'b1)
begin
lane_2_code <= #dly 7'b1001011 ;
end
else if (lane_2_res3 == 1'b1)
begin
lane_2_code <= #dly 7'b1010101 ;
end
else if (lane_2_res4 == 1'b1)
begin
lane_2_code <= #dly 7'b1100110 ;
end
else if (lane_2_res5 == 1'b1)
begin
lane_2_code <= #dly 7'b1111000 ;
end
else
begin
lane_2_code <= #dly 7'b0011110 ;
end
//lane_2_code <= \"1111000\" after dly;
end
end
// Lane 3
always @(posedge clk)
begin // ctrl_code_gen_3
if (enable == 1'b1)
begin
if (init == 1'b1 | lane_3_idle == 1'b1)
begin
lane_3_code <= #dly {7{1'b0}} ;
end
else if (lane_3_res0 == 1'b1)
begin
lane_3_code <= #dly 7'b0101101 ;
end
else if (lane_3_res1 == 1'b1)
begin
lane_3_code <= #dly 7'b0110011 ;
end
else if (lane_3_res2 == 1'b1)
begin
lane_3_code <= #dly 7'b1001011 ;
end
else if (lane_3_res3 == 1'b1)
begin
lane_3_code <= #dly 7'b1010101 ;
end
else if (lane_3_res4 == 1'b1)
begin
lane_3_code <= #dly 7'b1100110 ;
end
else if (lane_3_res5 == 1'b1)
begin
lane_3_code <= #dly 7'b1111000 ;
end
else
begin
lane_3_code <= #dly 7'b0011110 ;
end
//lane_3_code <= \"1111000\" after dly;
end
end
// Lane 4
always @(posedge clk)
begin // ctrl_code_gen_4
if (enable == 1'b1)
begin
if (init == 1'b1 | lane_4_idle == 1'b1)
begin
lane_4_code <= #dly {7{1'b0}} ;
end
else if (lane_4_res0 == 1'b1)
begin
lane_4_code <= #dly 7'b0101101 ;
end
else if (lane_4_res1 == 1'b1)
begin
lane_4_code <= #dly 7'b0110011 ;
end
else if (lane_4_res2 == 1'b1)
begin
lane_4_code <= #dly 7'b1001011 ;
end
else if (lane_4_res3 == 1'b1)
begin
lane_4_code <= #dly 7'b1010101 ;
end
else if (lane_4_res4 == 1'b1)
begin
lane_4_code <= #dly 7'b1100110 ;
end
else if (lane_4_res5 == 1'b1)
begin
lane_4_code <= #dly 7'b1111000 ;
end
else
begin
lane_4_code <= #dly 7'b0011110 ;
end
//lane_4_code <= \"1111000\" after dly;
end
end
// Lane 5
always @(posedge clk)
begin // ctrl_code_gen_5
if (enable == 1'b1)
begin
if (init == 1'b1 | lane_5_idle == 1'b1)
begin
lane_5_code <= #dly {7{1'b0}} ;
end
else if (lane_5_res0 == 1'b1)
begin
lane_5_code <= #dly 7'b0101101 ;
end
else if (lane_5_res1 == 1'b1)
begin
lane_5_code <= #dly 7'b0110011 ;
end
else if (lane_5_res2 == 1'b1)
begin
lane_5_code <= #dly 7'b1001011 ;
end
else if (lane_5_res3 == 1'b1)
begin
lane_5_code <= #dly 7'b1010101 ;
end
else if (lane_5_res4 == 1'b1)
begin
lane_5_code <= #dly 7'b1100110 ;
end
else if (lane_5_res5 == 1'b1)
begin
lane_5_code <= #dly 7'b1111000 ;
end
else
begin
lane_5_code <= #dly 7'b0011110 ;
end
//lane_5_code <= \"1111000\" after dly;
end
end
// Lane 6
always @(posedge clk)
begin // ctrl_code_gen_6
if (enable == 1'b1)
begin
if (init == 1'b1 | lane_6_idle == 1'b1)
begin
lane_6_code <= #dly {7{1'b0}} ;
end
else if (lane_6_res0 == 1'b1)
begin
lane_6_code <= #dly 7'b0101101 ;
end
else if (lane_6_res1 == 1'b1)
begin
lane_6_code <= #dly 7'b0110011 ;
end
else if (lane_6_res2 == 1'b1)
begin
lane_6_code <= #dly 7'b1001011 ;
end
else if (lane_6_res3 == 1'b1)
begin
lane_6_code <= #dly 7'b1010101 ;
end
else if (lane_6_res4 == 1'b1)
begin
lane_6_code <= #dly 7'b1100110 ;
end
else if (lane_6_res5 == 1'b1)
begin
lane_6_code <= #dly 7'b1111000 ;
end
else
begin
lane_6_code <= #dly 7'b0011110 ;
end
//lane_6_code <= \"1111000\" after dly;
end
end
// Lane 7
always @(posedge clk)
begin // ctrl_code_gen_7
if (enable == 1'b1)
begin
if (init == 1'b1 | lane_7_idle == 1'b1)
begin
lane_7_code <= #dly {7{1'b0}} ;
end
else if (lane_7_res0 == 1'b1)
begin
lane_7_code <= #dly 7'b0101101 ;
end
else if (lane_7_res1 == 1'b1)
begin
lane_7_code <= #dly 7'b0110011 ;
end
else if (lane_7_res2 == 1'b1)
begin
lane_7_code <= #dly 7'b1001011 ;
end
else if (lane_7_res3 == 1'b1)
begin
lane_7_code <= #dly 7'b1010101 ;
end
else if (lane_7_res4 == 1'b1)
begin
lane_7_code <= #dly 7'b1100110 ;
end
else if (lane_7_res5 == 1'b1)
begin
lane_7_code <= #dly 7'b1111000 ;
end
else
begin
lane_7_code <= #dly 7'b0011110 ;
end
//lane_7_code <= \"1111000\" after dly;
end
end
//-------------------------------------------------------------------------------
// Rest of the data output depends on the type_field :-
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // data_field_gen
if (init == 1'b1)
begin
data_field <= #dly {56{1'b0}} ;
int_error <= #dly 1'b0 ;
end
else
begin
if (enable == 1'b1)
begin
if ((type_reg[0]) == 1'b1)
begin
// type 0x1e
data_field <= #dly {lane_7_code, lane_6_code, lane_5_code, lane_4_code, lane_3_code, lane_2_code, lane_1_code, lane_0_code} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[1]) == 1'b1)
begin
// type 0x2d
data_field <= #dly {reg_reg_txd[63:40], o_code4, lane_3_code, lane_2_code, lane_1_code, lane_0_code} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[2]) == 1'b1)
begin
// type 0x33
data_field <= #dly {reg_reg_txd[63:40], 4'b0000, lane_3_code, lane_2_code, lane_1_code, lane_0_code} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[3]) == 1'b1)
begin
// type 0x66
data_field <= #dly {reg_reg_txd[63:40], 4'b0000, o_code0, reg_reg_txd[31:8]} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[4]) == 1'b1)
begin
// type 0x55
data_field <= #dly {reg_reg_txd[63:40], o_code4, o_code0, reg_reg_txd[31:8]} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[5]) == 1'b1)
begin
// type 0x78
data_field <= #dly reg_reg_txd[63:8] ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[6]) == 1'b1)
begin
// type 0x4b
data_field <= {lane_7_code, lane_6_code, lane_5_code, lane_4_code, o_code0, reg_reg_txd[31:8]} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[7]) == 1'b1)
begin
// type 0x87
data_field <= #dly {lane_7_code, lane_6_code, lane_5_code, lane_4_code, lane_3_code, lane_2_code, lane_1_code, 7'b0000000} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[8]) == 1'b1)
begin
// type 0x99
data_field <= #dly {lane_7_code, lane_6_code, lane_5_code, lane_4_code, lane_3_code, lane_2_code, 6'b000000, reg_reg_txd[7:0]} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[9]) == 1'b1)
begin
// type 0xaa
data_field <= #dly {lane_7_code, lane_6_code, lane_5_code, lane_4_code, lane_3_code, 5'b00000, reg_reg_txd[15:0]} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[10]) == 1'b1)
begin
// type 0xb4
data_field <= #dly {lane_7_code, lane_6_code, lane_5_code, lane_4_code, 4'b0000, reg_reg_txd[23:0]} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[11]) == 1'b1)
begin
// type 0xcc
data_field <= #dly {lane_7_code, lane_6_code, lane_5_code, 3'b000, reg_reg_txd[31:0]} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[12]) == 1'b1)
begin
// type 0xd2
data_field <= #dly {lane_7_code, lane_6_code, 2'b00, reg_reg_txd[39:0]} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[13]) == 1'b1)
begin
// type 0xe1
data_field <= #dly {lane_7_code, 1'b0, reg_reg_txd[47:0]} ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[14]) == 1'b1)
begin
// type 0xff
data_field <= #dly reg_reg_txd[55:0] ;
int_error <= #dly 1'b0 ;
end
else if ((type_reg[15]) == 1'b1)
begin
// The data has a control character in it but it
// doesn\'t conform to one of the above formats.
data_field <= #dly {lane_7_code, lane_6_code, lane_5_code, lane_4_code, lane_3_code, lane_2_code, lane_1_code, lane_0_code} ;
int_error <= #dly 1'b1 ;
end
else
begin
// If the input doesn\'t contain a control character then the data
// is set to be the rest of the data.
data_field <= #dly reg_reg_txd[63:8] ;
int_error <= #dly 1'b0 ;
end
end
end
end
assign int_data_out = {data_field, type_field, sync_field} ;
//-------------------------------------------------------------------------------
// Register the data before it leaves for the outside world.
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // doutgen
if (init == 1'b1)
begin
data_out <= #dly {66{1'b0}} ;
end
else
begin
if (enable == 1'b1)
begin
data_out <= #dly int_data_out ;
end
end
end
//-------------------------------------------------------------------------------
// Send the transmitter state machine a code indicating if the data is a control
// block, a data block, a start block, a terminate block or an error block. These
// are generated from the type_reg signal (except for data and error). To maintain
// timing we\'ll register this before decoding it.
//-------------------------------------------------------------------------------
always @(posedge init or posedge clk)
begin // regtype
if (init == 1'b1)
begin
type_reg_reg <= #dly {17{1'b0}} ;
end
else
begin
if (enable == 1'b1)
begin
type_reg_reg <= #dly type_reg ;
end
end
end
always @(posedge init or posedge clk)
begin // ttypegen
if (init == 1'b1)
begin
t_type <= #dly control ;
end
else
begin
if (enable == 1'b1)
begin
if ((type_reg[0]) == 1'b1 | (type_reg[1]) == 1'b1 | (type_reg[4]) == 1'b1 | (type_reg[6]) == 1'b1)
begin
t_type <= #dly control ;
end
else if ((type_reg[2]) == 1'b1 | (type_reg[3]) == 1'b1 | (type_reg[5]) == 1'b1)
begin
t_type <= #dly start ;
end
else if ((type_reg[16]) == 1'b1)
begin
t_type <= #dly data ;
end
else if ((type_reg[7]) == 1'b1 | (type_reg[8]) == 1'b1 | (type_reg[9]) == 1'b1 | (type_reg[10]) == 1'b1 | (type_reg[11]) == 1'b1 | (type_reg[12]) == 1'b1 | (type_reg[13]) == 1'b1 | (type_reg[14]) == 1'b1)
begin
t_type <= #dly terminate ;
end
else
begin
t_type <= #dly error ;
end
end
end
end
endmodule
|
// ghrd_10as066n2_f2sdram2_m.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_f2sdram2_m (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
ghrd_10as066n2_f2sdram2_m_altera_jtag_avalon_master_171_wqhllki #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) f2sdram2_m (
.clk_clk (clk_clk), // input, width = 1, clk.clk
.clk_reset_reset (clk_reset_reset), // input, width = 1, clk_reset.reset
.master_address (master_address), // output, width = 32, master.address
.master_readdata (master_readdata), // input, width = 32, .readdata
.master_read (master_read), // output, width = 1, .read
.master_write (master_write), // output, width = 1, .write
.master_writedata (master_writedata), // output, width = 32, .writedata
.master_waitrequest (master_waitrequest), // input, width = 1, .waitrequest
.master_readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
.master_byteenable (master_byteenable), // output, width = 4, .byteenable
.master_reset_reset (master_reset_reset) // output, width = 1, master_reset.reset
);
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:08:51 11/14/2014
// Design Name: program
// Module Name: program
// Project Name: VGA Playing
// Target Devices: Spartan 3AN Starter Kit
// Tool versions: ISE Project Navigator P.20131013
// Description:
//
//
//////////////////////////////////////////////////////////////////////////////////
module program # (
parameter TRUE = 1'b1,
parameter FALSE = 1'b0,
// VGA specification from http://en.wikipedia.org/wiki/Video_Graphics_Array
parameter H_ACTIVE_PIXEL = 640,
parameter H_FPORCH_PIXEL = 16,
parameter H_SYNC_PIXEL = 96,
parameter H_BPORCH_PIXEL = 48,
parameter H_LIMIT_PIXEL = H_ACTIVE_PIXEL + H_FPORCH_PIXEL + H_SYNC_PIXEL + H_BPORCH_PIXEL,
parameter V_ACTIVE_LINE = 480,
parameter V_FPORCH_LINE = 10,
parameter V_SYNC_LINE = 2,
parameter V_BPORCH_LINE = 33,
parameter V_LIMIT_LINE = V_ACTIVE_LINE + V_FPORCH_LINE + V_SYNC_LINE + V_BPORCH_LINE,
parameter BLOCK_SIZE = 10,
parameter H_BLOCK_COUNT = H_ACTIVE_PIXEL / BLOCK_SIZE,
parameter V_BLOCK_COUNT = V_ACTIVE_LINE / BLOCK_SIZE,
parameter BLOCK_COUNT = H_BLOCK_COUNT * V_BLOCK_COUNT,
parameter SERIAL_CLOCK_PER_BAUD_RATE = 5208,
parameter SERIAL_STATE_LAST = 8,
parameter SERIAL_STATE_SENT = 9,
parameter SERIAL_STATE_WAIT = 10
)(
input wire CLOCK_50M,
output wire [3:0] VGA_R,
output wire [3:0] VGA_G,
output wire [3:0] VGA_B,
output wire VGA_HSYNC,
output wire VGA_VSYNC,
input wire RS232_DCE_RXD,
output wire RS232_DCE_TXD,
// input ROT_A,
// input ROT_B,
input wire BUTTON_NORTH,
input wire BUTTON_WEST,
input wire BUTTON_EAST,
input wire BUTTON_SOUTH,
output wire [4:0] LED
);
/*
* SERIAL CLOCK GENERATOR
*/
reg CLOCK_SERIAL = FALSE;
reg [12:0] serial_clock_counter;
always @(posedge CLOCK_50M) begin
if (serial_clock_counter < SERIAL_CLOCK_PER_BAUD_RATE) begin
CLOCK_SERIAL <= FALSE;
serial_clock_counter <= serial_clock_counter + 1;
end
else begin
CLOCK_SERIAL <= TRUE;
serial_clock_counter <= 0;
end
end
/*
* SERIAL TX
*/
reg [63:0] send_buffer = 64'b0;
reg [2:0] send_buffer_count = 3'b0;
reg [7:0] tx_buffer = 8'b0;
reg [3:0] tx_counter = SERIAL_STATE_SENT; // 0->start bit sent,1=>first bit sent,...8=>wight bit sent,9=>sent, 10=>not send yet
reg tx_state = TRUE;
assign RS232_DCE_TXD = tx_state;
// reg [63:0] receive_buffer = 64'b0;
// reg [2:0] receive_buffer_count = 3'b0;
reg [7:0] rx_buffer = 8'b0;
reg [3:0] rx_counter = SERIAL_STATE_WAIT;
wire rx_state = RS232_DCE_RXD;
initial begin
send_buffer[7:0] <= "B";
send_buffer_count <= 1;
end
always @(posedge CLOCK_SERIAL or posedge BUTTON_WEST) begin
if (BUTTON_WEST == TRUE) begin
send_buffer[7:0] <= "B";
send_buffer_count <= 1;
end
else begin
// TX
if (tx_counter < SERIAL_STATE_LAST) begin
tx_state <= tx_buffer[tx_counter];
tx_counter <= tx_counter + 1;
end
else if (tx_counter == SERIAL_STATE_LAST) begin
tx_state <= TRUE;
tx_counter <= SERIAL_STATE_SENT;
end
else if (tx_counter == SERIAL_STATE_SENT && send_buffer_count > 0) begin
tx_buffer <= send_buffer[7:0];
tx_counter <= SERIAL_STATE_WAIT;
send_buffer <= send_buffer >> 8;
send_buffer_count <= send_buffer_count - 1;
end
else if (tx_counter == SERIAL_STATE_WAIT) begin
tx_state <= FALSE;
tx_counter <= 0;
end
// RX
if (rx_counter < SERIAL_STATE_LAST) begin
rx_buffer[rx_counter] <= rx_state;
rx_counter <= rx_counter + 1;
end
else if (rx_counter == SERIAL_STATE_LAST) begin
send_buffer[7:0] <= rx_buffer;
send_buffer_count <= 1;
block <= block << 1;
block[0] <= rx_buffer == "1" ? TRUE : FALSE;
rx_counter <= SERIAL_STATE_WAIT;
end
else if (rx_counter == SERIAL_STATE_WAIT && rx_state == FALSE) begin
rx_counter <= 0;
end
end
end
// serial serial(
// .CLOCK_50M(CLOCK_50M),
// .TX(RS232_DCE_TXD),
// .LED1(LED[3]),
// .LED2(LED[4]),
// .send_buffer_in(send_buffer),
// .send_buffer_count_in(send_buffer_count),
// .send_buffer_out(send_buffer_out),
// .send_buffer_count_out(send_buffer_count_out)
// );
/*
* CLOCK GENERATOR
*/
reg CLOCK_25M = FALSE;
always @(posedge CLOCK_50M) begin
CLOCK_25M <= !CLOCK_25M;
end
/*
* VIDEO OUTPUT
* 800*525 = 420000
*/
reg [9:0] line_pos = 10'b0; // horizontal position
reg [9:0] pixel_pos = 10'b0; // vertical position
reg [3:0] vga_r_out;
reg [3:0] vga_g_out;
reg [3:0] vga_b_out;
reg vga_hsync_out;
reg vga_vsync_out;
assign VGA_R = vga_r_out;
assign VGA_G = vga_g_out;
assign VGA_B = vga_b_out;
assign VGA_HSYNC = vga_hsync_out;
assign VGA_VSYNC = vga_vsync_out;
reg led_state1;
reg led_state2;
assign LED[1] = led_state1;
assign LED[2] = led_state2;
reg [BLOCK_COUNT-1:0] block = 1'b0;
reg [3:0] select_line_pos = 4'b0;
reg [3:0] select_pixel_pos = 4'b0;
always @(posedge BUTTON_EAST) begin
if (BUTTON_EAST == TRUE) begin
if (select_pixel_pos == 15) begin
select_pixel_pos = 0;
if (select_line_pos == 11) begin
select_line_pos = 0;
end
else begin
select_line_pos = select_line_pos + 1;
end
end
else begin
select_pixel_pos = select_pixel_pos + 1;
end
end
end
reg [3:0] color = 4'd15;
always @(posedge BUTTON_NORTH) begin
if (BUTTON_NORTH == TRUE) begin
color <= color + 1;
end
end
always @(posedge CLOCK_25M) begin
led_state1 <= !led_state1;
// active video
if (pixel_pos == H_ACTIVE_PIXEL || line_pos == V_ACTIVE_LINE) begin
vga_r_out <= 4'd0;
vga_g_out <= 4'd0;
vga_b_out <= 4'd0;
end
else if (pixel_pos < H_ACTIVE_PIXEL && line_pos < V_ACTIVE_LINE) begin
if (block[(pixel_pos/BLOCK_SIZE) + ((line_pos/BLOCK_SIZE)*H_BLOCK_COUNT)]) begin
vga_r_out <= 4'd15;
vga_g_out <= 4'd0;
vga_b_out <= 4'd0;
end
else begin
vga_r_out <= color;
vga_g_out <= color;
vga_b_out <= color;
end
end
// horizontal sync
if (pixel_pos == H_ACTIVE_PIXEL + H_FPORCH_PIXEL) begin
vga_hsync_out <= FALSE;
end
if (pixel_pos == H_ACTIVE_PIXEL + H_FPORCH_PIXEL + H_SYNC_PIXEL) begin
vga_hsync_out <= TRUE;
end
// vertical sync
if (line_pos == V_ACTIVE_LINE + V_FPORCH_LINE) begin
vga_vsync_out <= FALSE;
end
if (line_pos == V_ACTIVE_LINE + V_FPORCH_LINE + V_SYNC_LINE) begin
vga_vsync_out <= TRUE;
end
// counter
pixel_pos <= pixel_pos + 1;
if (pixel_pos == H_LIMIT_PIXEL + 1) begin
pixel_pos <= 0;
line_pos <= line_pos + 1;
if (line_pos == V_LIMIT_LINE + 1) begin
line_pos <= 0;
led_state2 <= !led_state2;
end
end
end
/*
* PLAYING
*/
// reg led_state0;
assign LED[0] = TRUE;
assign LED[3] = TRUE;
assign LED[4] = TRUE;
always @(posedge BUTTON_SOUTH) begin
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_burst #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
input flush,
output reg busy,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
output reg pipe_stb_o,
input pipe_ack_i,
output reg [fml_depth-5-1:0] burst_addr, /* in 256-bit words */
/* 16-bit granularity selection that needs to be expanded
* to 8-bit granularity selection to drive the FML lines.
*/
output reg [15:0] burst_sel,
output reg [255:0] burst_do
);
wire burst_hit = dadr[fml_depth-1-1:4] == burst_addr;
/* Always memorize input in case we have to ack a cycle we cannot immediately handle */
reg [15:0] color_r;
reg [fml_depth-1-1:0] dadr_r;
always @(posedge sys_clk) begin
if(pipe_stb_i & pipe_ack_o) begin
color_r <= color;
dadr_r <= dadr;
end
end
/* Write to the burst storage registers */
reg clear_en;
reg write_en;
reg use_memorized;
wire [15:0] color_mux = use_memorized ? color_r : color;
wire [fml_depth-1-1:0] dadr_mux = use_memorized ? dadr_r : dadr;
always @(posedge sys_clk) begin
if(sys_rst)
burst_sel = 16'd0;
else begin
if(clear_en)
burst_sel = 16'd0;
if(write_en) begin
burst_addr = dadr_mux[fml_depth-1-1:4]; /* update tag */
case(dadr_mux[3:0]) /* unmask */
4'd00: burst_sel = burst_sel | 16'h8000;
4'd01: burst_sel = burst_sel | 16'h4000;
4'd02: burst_sel = burst_sel | 16'h2000;
4'd03: burst_sel = burst_sel | 16'h1000;
4'd04: burst_sel = burst_sel | 16'h0800;
4'd05: burst_sel = burst_sel | 16'h0400;
4'd06: burst_sel = burst_sel | 16'h0200;
4'd07: burst_sel = burst_sel | 16'h0100;
4'd08: burst_sel = burst_sel | 16'h0080;
4'd09: burst_sel = burst_sel | 16'h0040;
4'd10: burst_sel = burst_sel | 16'h0020;
4'd11: burst_sel = burst_sel | 16'h0010;
4'd12: burst_sel = burst_sel | 16'h0008;
4'd13: burst_sel = burst_sel | 16'h0004;
4'd14: burst_sel = burst_sel | 16'h0002;
4'd15: burst_sel = burst_sel | 16'h0001;
endcase
case(dadr_mux[3:0]) /* register data */
4'd00: burst_do[255:240] = color_mux;
4'd01: burst_do[239:224] = color_mux;
4'd02: burst_do[223:208] = color_mux;
4'd03: burst_do[207:192] = color_mux;
4'd04: burst_do[191:176] = color_mux;
4'd05: burst_do[175:160] = color_mux;
4'd06: burst_do[159:144] = color_mux;
4'd07: burst_do[143:128] = color_mux;
4'd08: burst_do[127:112] = color_mux;
4'd09: burst_do[111: 96] = color_mux;
4'd10: burst_do[ 95: 80] = color_mux;
4'd11: burst_do[ 79: 64] = color_mux;
4'd12: burst_do[ 63: 48] = color_mux;
4'd13: burst_do[ 47: 32] = color_mux;
4'd14: burst_do[ 31: 16] = color_mux;
4'd15: burst_do[ 15: 0] = color_mux;
endcase
end
end
end
wire empty = (burst_sel == 16'd0);
reg state;
reg next_state;
parameter RUNNING = 1'b0;
parameter DOWNSTREAM = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= RUNNING;
else
state <= next_state;
end
/*
* generate pipe_ack_o using an assign statement to work around a bug in CVER
*/
assign pipe_ack_o = (state == RUNNING) & (~flush | empty);
always @(*) begin
next_state = state;
busy = 1'b1;
// CVER WA (see above) pipe_ack_o = 1'b0;
pipe_stb_o = 1'b0;
write_en = 1'b0;
clear_en = 1'b0;
use_memorized = 1'b0;
case(state)
RUNNING: begin
busy = 1'b0;
if(flush & ~empty)
next_state = DOWNSTREAM;
else begin
// CVER WA (see above) pipe_ack_o = 1'b1;
if(pipe_stb_i) begin
if(burst_hit | empty)
write_en = 1'b1;
else
next_state = DOWNSTREAM;
end
end
end
DOWNSTREAM: begin
pipe_stb_o = 1'b1;
use_memorized = 1'b1;
if(pipe_ack_i) begin
clear_en = 1'b1;
write_en = 1'b1;
next_state = RUNNING;
end
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
module RM_ctl # (
parameter integer C_STEP_NUMBER_WIDTH = 32,
parameter integer C_SPEED_DATA_WIDTH = 32
) (
input wire clk,
input wire resetn,
output reg exe_done,
input wire req_abs,
input wire [C_SPEED_DATA_WIDTH-1:0] req_speed,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] req_step,
output wire m_sel ,
input wire m_ntsign ,
input wire m_zpsign ,
input wire m_ptsign ,
input wire m_state ,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] m_position,
output reg m_start ,
output reg m_stop ,
output reg [C_SPEED_DATA_WIDTH-1:0] m_speed ,
output reg signed [C_STEP_NUMBER_WIDTH-1:0] m_step ,
output reg m_abs ,
output reg m_mod_remain,
output reg signed [C_STEP_NUMBER_WIDTH-1:0] m_new_remain
);
reg m_started;
wire m_running;
assign m_running = m_state;
always @ (posedge clk) begin
if (resetn == 1'b0)
m_started <= 1'b0;
else if (m_start)
m_started <= 1'b1;
end
reg m_run_over;
always @ (posedge clk) begin
if (resetn == 1'b0)
m_run_over <= 1'b0;
else if (m_running)
m_run_over <= 1'b1;
end
wire m_stopped;
assign m_stopped = (m_run_over && ~m_running);
/// stop
always @ (posedge clk) begin
if (resetn == 1'b0)
m_stop <= 1'b0;
else if (m_stop == 1'b1)
m_stop <= 1'b0;
/// @todo always 0 now
end
/// start
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_start <= 1'b0;
end
else if (m_start == 1'b1) begin
m_start <= 1'b0;
end
else if (m_started == 1'b0) begin
m_start <= 1'b1;
m_speed <= req_speed;
m_step <= req_step;
m_abs <= req_abs;
end
end
/// change remain step
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_mod_remain <= 1'b0;
m_new_remain <= 0;
end
end
//////////////// exe_done
always @ (posedge clk) begin
if (resetn == 1'b0)
exe_done <= 1'b0;
else if (m_stopped)
exe_done <= 1'b1;
end
assign m_sel = resetn;
endmodule
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